201040705 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電源管理方法及其相關管理裝置 以及晶片組，特別是有關於一種基於進階組態與電源界面 (Advanced Configuration and Power Interface, ACPI)的處理 器電源狀態的電源管理方法，用以控制一電腦系統中的鎖 相迴路之操作。 【先前技術】 為了提供電源管理，目前的電腦系統例如個人電腦或 可攜式電腦均採用進階組態與電源界面（Advanced Configuration and Power Interface，以下簡稱 ACPI)，以有 效地監控以及分配供應的能源給電腦系統中的每一元件。 ACPI定義了五種狀態，例如：s〇、S1、S3、S4和S5五種 狀態。然而，只有狀態S0是電腦系統正常操作的狀態，其 餘S1至S5狀態，電腦系統皆處於休眠狀態。此外，ACPI 更定義了在狀態SO時的中央處理器省電狀態。 第1圖為ACPI定義中央處理器之電源狀態示意圖。 ACPI定義中央處理器在工作狀態（fun running state)時(C0 狀態）正常地運作，例如執行各項指令與工作。如果電腦系 統閒置超過一段預定時間，作業系統會讓中央處理器進入 省電狀態例如C1-C4狀態。作業系統會根據電腦系統上的 匯流排主控元件動作狀態（Bus Master activity status)來決 定讓中央處理器進入哪一種省電狀態。ACPI標準中所定義 的中央處理器省電狀態包含第一（C1)、第二(C2)、第三(C3) 嘸 省電狀態以及比C3狀態更省電的第四（C4)省電狀態，其中 VIC09-0003I00-TW/ 0608-A41997三TW/Final/ 4 201040705 C2狀態比C1狀態省電， ，C3狀態會比C2狀態省電，C4 ’ C4狀201040705 VI. Description of the Invention: [Technical Field] The present invention relates to a power management method and related management apparatus and chipset thereof, and more particularly to an advanced configuration and power interface (Advanced Configuration and Power Interface) , ACPI) A power management method for the processor power state to control the operation of a phase locked loop in a computer system. [Prior Art] In order to provide power management, current computer systems such as personal computers or portable computers use Advanced Configuration and Power Interface (ACPI) to effectively monitor and distribute the supply. Energy is given to every component in the computer system. ACPI defines five states, such as s〇, S1, S3, S4, and S5. However, only the state S0 is the state in which the computer system is operating normally, and the remaining S1 to S5 states, the computer system is in a sleep state. In addition, ACPI defines the CPU power saving state in state SO. Figure 1 is a schematic diagram showing the power state of the central processor defined by ACPI. ACPI defines that the central processor operates normally during the fun running state (C0 state), such as executing instructions and work. If the computer system is idle for more than a predetermined period of time, the operating system will put the central processor into a power-saving state such as the C1-C4 state. The operating system determines which power saving state the central processor enters based on the Bus Master activity status on the computer system. The central processor power saving state defined in the ACPI standard includes a first (C1), a second (C2), a third (C3) power saving state, and a fourth (C4) power saving state that is more power efficient than the C3 state. , where VIC09-0003I00-TW/ 0608-A41997 three TW/Final/ 4 201040705 C2 state saves power compared to C1 state, C3 state will save power compared to C2 state, C4 'C4 shape
中匯流排主控元件仙在電腦线巾具有匯流排主^ 元件’例如USB控制器、PCI控制器等等。此時，: 斷事件產生使得中斷(lntemipt)產生時、或中央處理器被請 求執行指令時’中央處理ϋ會從C2狀態回到Cq狀離。在 C3或C4狀態（以下_C3/C4狀態）中，中央處理=、停止 時脈，同時也不能窺探匯流排主控元件的存取動作。匚4狀 態與C3狀態相比，中央處理器處於更深度的睡眠狀態中。 因此，C4為處理器的所有省電狀態中的低耗電狀態，亦即 損耗最少的能源。 當電腦系統中的作業系統偵測到電腦系統無任何動作 超過一段既疋時間時，將致使中央處理器進入C3/C4狀 態’藉此使得電腦系統更有效地節省電源。 電腦糸統中’鎖相迴路(phase lock loop，PLL)係用來產 生各種不同頻率的時脈訊號，其係根據一接收到的低頻率 來源時脈訊號輸入’產生各種不同頻率的高時脈訊號輸出 以供電腦系統内部使用。鎖相迴路係被整合至大部分的整 合晶片中’以產生各種不同的高頻率時脈來源。然而，鎖 相迴路的動作將會造成大量的電力耗損。因此，如何有效 的控制鎖相迴路成為降低電源損耗的重要課題之一。 習知地’鎖相迴路係依據ACPI系統狀態例如S1狀態 來加以控制’而在電腦系統正常操作的狀態S0下，鎖相迴 VIC09-0003IOO-TW/ 〇6〇8-A41997-TW/Final/ 5 201040705 路-，=常執行伽e running)，並未加^制。換言 之’备電腦系統正常操作時，由於鎖相迴路係 、 此無法有效降低電源損耗。 I耗電因 sl:t作統—般不會頻繁地1動進入休眠狀態 S1-S5，而作業糸統部會經常送出指令以將處 省電狀態C3/C4狀態。因此，處理器在省電狀態狀 態的時間遠比電腦系統在休眠狀態S1或其他休眠狀態長。 因此’需要—種可於處理器狀態設為省電狀態（(^3/C4 狀態）時的鎖相迴路控制方法以及裝置。 一 【發明内容】 有鑑於此’本發明提供—種電源f理方法，適用於一 電腦系統’其中電_統具有—處理單元、—電源管理模 組(PMU)以及-鎖相迴路(PLL)電路’電源管理模組輛接複 數個周邊模組，並且電腦系統以及該處理單元可分別操作 於-工作狀態與複數省電狀態下。其方法包括：當電腦系 統操作於工作狀態且處理單元進入省電狀態中之一最低功 耗省電狀態時，偵測周邊模組之狀態，以判斷一特定條件 是否符合；以及當周邊模組之狀態符合特定條件時，依據 一控制狀態設定，致使處理單元進入一控制狀態以控制鎖 相迴路之操作。 本發明實施例另提供一種晶片組，其耦接至一時脈產 生器以及一處理器，包括一鎖相迴路、一閘控單元、複數 周邊模組以及一電源管理模組。鎖相迴路用以依據時脈產 生益產參之一第一時脈訊號’產生至少·一第二時脈訊號。 閘控皁元輕接至鎖相迴路，用以控制鎖相迴路產生之第二 VICO9-OO03IO0-TW/ 0608-A41997-TW/Final/ 6 201040705 時脈訊號之輸出。每一周邊模組分別具有一低功耗省電狀 態。電源管理模組耦接至閘控單元、周邊模組以及鎖相迴 路。其中當處理單元進入省電狀態中之一最低功耗省電狀 態時，電源管理模組偵測周邊模組之狀態，以判斷一特定 條件是否符合，並當周邊模組之狀態符合特定條件時，依 據一控制狀態設定，致使處理單元進入一控制狀態以控制 鎖相迴路之操作。 本發明實施例另提供一種電腦系統，包括一時脈產生 Ο 器、一處理單元以及一晶片組。時脈產生器用以產生一第 一時脈訊號。晶片組耦接至時脈產生器以及處理單元，其 包括一鎖相迴路、一閘控單元、複數周邊模組以及一電源 管理模組。鎖相迴路依據第一時脈訊號，產生至少一第二 時脈訊號。閘控單元耦接至鎖相迴路，用以控制鎖相迴路 產生之第二時脈訊號之輸出。每一周邊模組分別具有一低 功耗省電狀態。電源管理模組耦接至閘控單元、周邊模組 以及鎖相迴路。其中，當電腦系統操作於一工作狀態且處 〇 理單元進入控制狀態中之一最低功耗省電狀態時，電源管 理模組偵測周邊模組之狀態，以判斷一特定條件是否符 合，並當周邊模組之狀態符合特定條件時，依據一控制狀 態設定，致使處理單元進入一控制狀態以控制鎖相迴路之 操作。 本發明上述方法可以透過程式碼方式收錄於實體媒體 中。當程式碼被機器載入且執行時，機器變成用以實行本 發明之裝置。 . 為使本發明之上述和其他目的、特徵、和優點能更明 ΥΙΟ09-0003Ι00-Ρ^/ 0608-Α41997-TW/Final/ 7 201040705 顯易It，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下。 【實施方式】 第2圖顯不依據本發明實施例之電腦系統2〇〇。其中， 電腦系統2GG可操作於—工作狀態(如ACpi狀態s〇)以及 多個省電狀態（如ACPI狀態S1_S5)，只有當操作於工作 狀態時’電腦系統2GG為正常操作的狀態，其餘省電狀態 皆處於休眠狀態。如第2圖所示，電腦系統細至少包括 一處理單元210、一時脈產生器22〇、以及一晶片组 (ChiPSet)230。時脈產生器22〇係用以產生一第一時脈訊 號。晶片組230 _接至處理單元21〇以及時脈產生器 220,其中晶片組230包括一鎖相趣路232、一閑控單元 234、-電源管理模組236以及多個周邊模組挪。其中， 周邊模組238係為匯流排主控元件(如馳㈣或各種輸出 入裝置控制器。舉例來說，周邊模* 238可包括dram控 制器、PCIe控制器、HDAC控制器、§腿训控制器、Lpc 控制器、即時時脈產生器（RTC)、中斷控制器（8259)、Apic、 PCI控制器、SPI&SPI快閃記憶體、SDI〇以及記憶卡介面 控制器、鍵盤滑鼠控制器、繪圖控制晶片（GFX)、USB控 制器以及SATA控制器等，但不限於此。每一個周邊模組 238分別具有工作狀態以及多個省電狀態，其中省電狀態 中最省電的模式稱為低功耗省電模式。舉例來說，若周邊 模組238為記憶體控制器時，其低功耗省電模式即係工作 於自我更新（self-refresh)模式’右周邊模組23 8為繪圖控制 曰曰片時’其低功耗省電模式即係工作於快照（snapSh〇t)模 VIC09-0003I00-TW/ 0608-A41997-TW/Final/ 8 201040705 即係將USB裝置設為工作於D 、 SATA控制考拄甘把丄±|模式.右周邊模組238為 為工作於部1時〜、低功耗，電模式即係將SATA裝置敦 1相增路232係接收時脈產生器220所產生的第一時 I依據第-時脈《，產生至少—第二時脈訊號， …〜時脈訊號—般具有比第—時脈訊號高的頻率。 ΟThe main bus component of the bus bar has a bus bar main component such as a USB controller, a PCI controller, and the like in the computer wire towel. At this time, when the interrupt event is generated such that the interrupt (lntemipt) is generated, or when the central processing unit is requested to execute the command, the central processing unit returns from the C2 state to the Cq state. In the C3 or C4 state (hereinafter _C3/C4 state), the central processing =, the stop clock, and the access operation of the bus master control element cannot be peeked. The 匚4 state is in a deeper sleep state than the C3 state. Therefore, C4 is the low power state of all power-saving states of the processor, that is, the energy with the least loss. When the operating system in the computer system detects that the computer system has not been operated for more than a period of time, it will cause the central processing unit to enter the C3/C4 state, thereby making the computer system more efficient in saving power. In the computer system, a phase lock loop (PLL) is used to generate clock signals of various frequencies, which are based on a received low frequency source clock signal input to generate high clocks of various frequencies. Signal output for internal use in computer systems. The phase-locked loop is integrated into most of the integrated wafers' to produce a variety of different high frequency clock sources. However, the action of the phase-locked loop will cause a large amount of power loss. Therefore, how to effectively control the phase-locked loop becomes one of the important topics to reduce power loss. It is customary that the 'phase-locked loop is controlled according to the ACPI system state, such as the S1 state', and in the state S0 of the normal operation of the computer system, the phase lock back to VIC09-0003IOO-TW/〇6〇8-A41997-TW/Final/ 5 201040705 Road -, = often perform gamma running), without adding control. In other words, when the standby computer system is operating normally, the power loss is not effectively reduced due to the phase-locked loop. I consumes power because sl:t does not frequently enter the sleep state S1-S5, and the operating system often sends instructions to save the power state C3/C4 state. Therefore, the processor is in a state of power saving state for a longer period of time than the computer system is in a sleep state S1 or other sleep state. Therefore, there is a need for a phase-locked loop control method and apparatus that can be set to a power-saving state ((^3/C4 state) when the processor state is set. [Invention] In view of the present invention, a power supply is provided. The method is applicable to a computer system, wherein the power system has a processing unit, a power management module (PMU), and a phase locked loop (PLL) circuit, and the power management module is connected to a plurality of peripheral modules, and the computer system And the processing unit can be respectively operated in the - working state and the plurality of power saving states. The method comprises: detecting the periphery when the computer system is operating in the working state and the processing unit enters one of the lowest power consumption states in the power saving state The state of the module to determine whether a particular condition is met; and when the state of the peripheral module meets certain conditions, according to a control state setting, causing the processing unit to enter a control state to control the operation of the phase locked loop. A chip set is coupled to a clock generator and a processor, including a phase lock loop, a gate control unit, a plurality of peripheral modules, and a processor The source management module: the phase-locked loop is configured to generate at least one second clock signal according to the first pulse signal of the pros and cons of the clock. The gate-controlled soap element is lightly connected to the phase-locked loop for controlling the lock Phase II loop generated by the second VICO9-OO03IO0-TW/ 0608-A41997-TW/Final/ 6 201040705 clock signal output. Each peripheral module has a low power consumption state. The power management module is coupled to The gate control unit, the peripheral module, and the phase locked loop. When the processing unit enters one of the lowest power consumption states in the power saving state, the power management module detects the state of the peripheral module to determine whether a specific condition meets And when the state of the peripheral module meets a certain condition, according to a control state setting, the processing unit enters a control state to control the operation of the phase-locked loop. The embodiment of the invention further provides a computer system including a clock generator a processing unit and a chip set. The clock generator is configured to generate a first clock signal. The chip set is coupled to the clock generator and the processing unit, and includes a phase locked loop and a gate control a plurality of peripheral modules and a power management module. The phase locked loop generates at least a second clock signal according to the first clock signal. The gate control unit is coupled to the phase locked loop for controlling the phase locked loop to generate The output of the second clock signal. Each peripheral module has a low power consumption state. The power management module is coupled to the gate control unit, the peripheral module, and the phase locked loop. When the working state is in the lowest power consumption state in which the processing unit enters the control state, the power management module detects the state of the peripheral module to determine whether a specific condition is met, and when the state of the peripheral module meets the specificity In the condition, according to a control state setting, the processing unit enters a control state to control the operation of the phase-locked loop. The above method of the present invention can be recorded in the physical medium through code. When the code is loaded and executed by the machine, the machine becomes the means for carrying out the invention. The above and other objects, features, and advantages of the present invention will become apparent from the Detailed Description of the Drawings. The drawings are described in detail below. [Embodiment] FIG. 2 shows a computer system according to an embodiment of the present invention. The computer system 2GG can be operated in a working state (such as ACpi state s〇) and a plurality of power saving states (such as ACPI state S1_S5), and only when the operating state is in operation, the computer system 2GG is in a normal operating state, and the remaining provinces The electrical states are all in a sleep state. As shown in Fig. 2, the computer system includes at least a processing unit 210, a clock generator 22A, and a chip set (ChiPSet) 230. The clock generator 22 is configured to generate a first clock signal. The chipset 230 is connected to the processing unit 21A and the clock generator 220, wherein the chipset 230 includes a lock phase circuit 232, an idle control unit 234, a power management module 236, and a plurality of peripheral modules. The peripheral module 238 is a bus bar main control component (such as Chi (four) or various input and output device controllers. For example, the peripheral mode * 238 may include a dram controller, a PCIe controller, an HDAC controller, § leg training Controller, Lpc Controller, Instant Clock Generator (RTC), Interrupt Controller (8259), Apic, PCI Controller, SPI&SPI Flash Memory, SDI〇 and Memory Card Interface Controller, Keyboard Mouse Control , but not limited to, the peripheral control module 238 has a working state and a plurality of power saving states, wherein the most power saving mode in the power saving state It is called a low-power power-saving mode. For example, if the peripheral module 238 is a memory controller, its low-power power-saving mode operates in a self-refresh mode 'right peripheral module 23 8 is the control power of the drawing. 'The low power consumption mode is working on the snapshot (snapSh〇t) mode VIC09-0003I00-TW/ 0608-A41997-TW/Final/ 8 201040705 is to set the USB device Working in D, SATA control test The right peripheral module 238 is for operating at the part 1 and low power consumption, and the electric mode is to increase the SATA device to the first phase I generated by the clock generator 220. The pulse ", produces at least - the second clock signal, ... ~ clock signal - generally has a higher frequency than the first - clock signal.
甲工早兀234係麵接至鎖相迴路加，用以控制鎖相迴路 232產生的第二時脈訊號的輸出。於-實施例中，閘控單 元 更耦接至電源管理模組236，其係依據電源管理模 組236的一控制訊號pLLG(第一控制訊號），決定是否遮 斷(gating)鎖相迴路232的第二時脈訊號的輸出，亦即是否 停止第一時脈訊號的輸出。鎖相迴路232耦接至電源管理The 234 system is connected to the phase-locked loop to control the output of the second clock signal generated by the phase-locked loop 232. In the embodiment, the gate control unit is further coupled to the power management module 236, which determines whether to lock the phase locked loop 232 according to a control signal pLLG (first control signal) of the power management module 236. The output of the second clock signal, that is, whether to stop the output of the first clock signal. Phase-locked loop 232 is coupled to power management
模組236 ’其係依據電源管理模組236的一控制訊號PLLD (第一控制訊號），決定是否關閉（p〇wer d〇wn )鎖相迴 路 232。 電源官理模組236係耦接至閘控單元234以及所有周 邊模組238’用以執行依據本發明實施例的電源管理方法， 用以依據處理單元210的省電狀態，控制鎖相迴路232的 操作。 第3圖顯示一依據本發明實施例之電源管理方法之流 程圖。如前述，依據本發明實施例之電源管理方法可以由 如第2圖中的電源管理模組236所執行。請同時參照第2 圖。首先，當電腦系統200操作於工作狀態且處理.單元21〇 進入控制狀態中之一最低功耗省電狀態C4時，如步驟 VIC09-0003I00-TW/ 0608-A41997-,^^/Final/ 9 201040705 S310，電源管理模組236偵測所有周邊模組238的狀態， 以判斷一特定條件是否符合(步驟s320)。請注意，電源管 理模組236偵測周邊模組238的狀態（例如電源狀態）以判 斷特定條件是否符合係於所有周邊模組238皆閒置一既定 時間之後才進行判斷。由於每一周邊模組238分別具有一 低功耗省電模式，因此電源管理模組23 6偵測周邊模組2 3 8 之狀態以判斷特定條件是否符合係判斷周邊模組中的既定 周邊模組是否處於對應的低功耗省電模式。於—實施例 中，既定周邊模組可包括（但不限於此記憶體控制器、 一繪圖控制器、USB控制器以及SATA控制器，則當下列 條件成立時，特定條件係判斷為符合： (1) s己憶體控制器係工作於自我更新模式； (2) 繪圖控制器係工作於快照模式； (3) USB控制器係將USB裝置設為工作於出模式：以 及 、工* WSATA控制器係將SATA裝置設為工作於部分 (partial/slumber)模式。 民 換言之，只有當上述條件(1H4)都符合時 組236才會判斷特定條件為符合， 、、/原e理模 條件。如前述，由於上述判斷係於所有】斷為不符合特定 置-既定時間之後才進行’因此除了 g 1邊权組238皆閒 需符合上述條件（1)-(4)之外，其他周既^邊模组的狀態 當周邊模組的狀態不符合特^ j抵組則疋閒置狀態。 否），例如上述條件（1)-(4)不.符合# + 叮卩^鄉S320的 件發生時，便不做特別處理，流程社束弋我好的喚醒事 VIC09-0003I00-TW/ 0608-A41997-TW/FinaI/ 10 201040705 S.周邊模組的狀態符合特定條件時（步驟S3 2〇 @ 3 電源管理模組236便依據一預設的控制狀態設定，疋， 理單元210進入一鎖相迴路控制狀態以控制鎖相迴路Μ? 的操作（步驟S330)。舉例來說，於一實施例中，可於電腦 系統的基本輸出入系統(BI0S)(未繪示）中提供一控制狀態 設定選項，以設定進入鎖相迴路控制狀態後的控制狀態了 於本實施例中，鎖相迴路控制狀態有兩種控制狀態設定 值：第一控制狀態（C4PG)以及第二控制狀態（C4pD)e此設 〇 定值將儲存於一暫存器（未繪示）中，例如設定值i表示第 一控制狀態，而設定值0表示第二控制狀態。請參見第4 圖，係顯示依據本發明實施例之中央處理器之電源狀態示 意圖。如第4圖所示，中央處理器之電源狀態共有工作狀 態C0、第一省電狀態C1、第二省電狀態c2、第三省電狀 態C3、最低功耗省電狀態C4以及兩種可能的鎖相迴路控 制狀態C4PG(第一控制狀態）以及C4pD(第二控制狀態）。 其中，狀態C0至C4係類似於第1圖中的對應狀態，鎖相 Ο 迴路控制狀態C4PG以及C4PD則依據暫存器中的設定值 選擇性地進入。舉例來說，當處理單元21〇進入最低功耗 省電狀態C4時’若暫存器中的設定值為〗，則處理單元21〇 將進入第一控制狀態（C4PG)。反之，當處理單元210進入 最低功耗省電狀態C4時，若暫存器中的設定值為〇,則處 理單元210將進入第二控制狀態（C4pD)。當處理單元21〇 進入第一或第二控制狀態後，若偵測到有任何唤醒事件發 生時，電源管理模組230便執行一恢復程序以將處理單元 210恢復至最低功耗省電狀態C4。 V1C09-0003I00-TW/ 〇6〇8-A41997-TW/Final/ 11 201040705 電源控制狀態設定為第-控制狀態時， 電源&理模組236送出一控制訊號PLLG至閘控單元234, =過閘控單元234停止鎖相迴路232的時脈輸出。此時， =迴路232㈣脈輸出被遮斷，但是鎖相迴路232並未 do㈣’仍保留電源。當控制狀態設定 控 制狀態時，《管理触236㈣㈣喊plld至鎖相 迴路232 ’當鎖相迴路232接收到控制訊號pLLD之後，鎖 ^路232將整個關閉。於—實施例中，當控制狀態設定 為第二控制狀態時’電源管理模組236分別送出控制訊號 PLLD以及控制訊號C4psT〇p (第三控制訊號）至鎖相迴 路232以及晶片組230外部的時脈產生器22〇(鎖相迴路232 對應的來源時脈產生單元）。當鎖相迴路232接收到控制訊 號PLLD之後，鎖相迴路232將整個關閉。當時脈產生器 220接收到控制訊號（：4朽11〇1)之後，時脈產生器22〇將停 止輸出時脈訊號至鎖相迴路232。 在處理單元210進入鎖相迴路控制狀態之後，若偵測 到一喚醒事件發生時，電源管理模組236將執行一恢復程 序以致使該處理單元恢復至該最低功耗省電狀態C4。 第5圖顯示一依據本發明實施例之恢復程序之流程 圖’如前述’依據本發明實施例之電源管理方法可以由如 第2圖中的電源管理模組236所執行。 如第5圖所示，同時參照第4圖，如步驟S510，電源 管理模組236先由暫存器的設定值判斷處理單元210處於 .第一或第一控制狀態。舉例來説，於一實施例中，當暫存 器的設定值為1或〇時，可判斷處理單元210係分別處於 VIC09-0003I00-TW/ 0608-A41997-TW/Final/ 12 201040705 第一或第二控制狀態。若處於第一控制狀態，表示處 兀210係欲從第一控制狀態返回至C4狀態，反之表早 單/0 21。係欲從第二控制狀態返回至二二理 的設定值判斷處理單元-處於第-控制狀態； =0:相迴路232益未關閉’只是其時脈輸出被閘 二早7G 遮斷，因此恢復程序便直接透過間押單_ Ο 〇 停止遮斷鎖相迴路232，接著執行步驟s。當^ 的設定值判斷處理單元加處於第二控制狀 ^ S530中判斷時脈產生器，^接收到控制= 之:否時，時脈產生器220並未停止輸出時脈 ^號 表不時脈產生器220停止了輸出時脈訊號。當 ，脈接收到控制訊號C4P瞻（步驟s530的 疋）’由於鎖相迴路232被關閉且外部時脈產生器的輸^ 停止，因此恢復程序便執行步驟SMG及娜 鮮 止的時脈以及啟動鎖相迴路232。如步驟S540， t 先啟動鎖相迴路232對應的來源時脈產生單元(亦即時脈產 生器220)的輸出’並如步驟⑽’於來源時脈產生單元啟 動完成之後，再啟動鎖相趣路232，接著執行步驟挪〇。 當時脈產生H細並未接收到控制訊號⑽灯 ㈣的否），因為時脈產生器22〇並未停止輸出時脈訊號， 因此恢復程序便直接執行步驟S55G啟動鎖相迴路232 著執行步驟—S560。如步驟_，恢復程序等待鎖相迴路 232啟動穩定之後，最後，便將處理單元21 恢復至最低功耗省電狀態C4。 1： 以下列舉-實施例，用以進一步說明本發明之電源管 VIC09-0003I00-TW/0608-A41997-TW/FinaV 13 201040705 理方法，但並非用以限定本發明。 於本實施例令，假設處理單元21〇因一段時間未 已經進入最低魏省電狀態C4且暫存器的設定值為〇。於 所有周邊模組238皆閒置一既定時間之後，電源管理模組 236偵測周邊模組238的狀態以判斷特定條件是否符合、'， 即判斷前述條件⑴_(4)是否都滿足。假設條件⑴·(4)都滿 足，表不特定條件符合，電源管理模組236便依據預設的 控制狀態妓，致使處理單元21G進人—鎖相迴路控制狀 態以控制鎖相迴路232的操作。由於暫存器的設定值為0, 表不要進入第二控制狀態，電源f理模組23 號PLLD鎖相迴路，告始士n、 ^ ^ ^ 迴路232接收到控制訊號 PLLD之後，鎖相迴路232將整個關閉。 於=實施财，暫存器的設定值為〇,表示要進入第二 控制狀態，電源管理模組236分 及控制訊號⑽ST0P至鎖相迴刀路 =出控制訊號咖以 的時脈產生1^20。當鎖相趣路攻接 = 之後’鎖相迴路232將整個關閉。 工 到控制訊號C4PST0P之後，賠r立、產生窃20接收 脈訊號至鎖相迴路232。因^二生器一22。將停止輸出時 控制狀態且鎖相迴路232被關門^早7^ 21()係進入第二 出被停止。之後，若她外部時脈產生器的輸 執行-恢復程序，由於時脈產生Ϊ22= 了控制訊號⑽瞻，表示鎖相迴路加被關閉且外部時 使的被Λ止，恢復程序便先啟動時脈產生 ’在㈣產生器22Q啟動完成之後， VIC09-0003100-TW/ 0608-A41997-TW/FinaI/ 14 201040705 致使處理單元21G恢復至最低功耗省電狀態C4。 、絲上所述，依據本發明之電源管理方法及相關之晶片 以及ί腦系統，可透過新增的鎖相迴路控制狀態，提供 在處理單疋進入最低功耗省電狀態（即狀態C4)下的鎖相迴 路控=目為正常執行時處理單元將經常處於最低功耗省 電狀態’可更有效地減少整個電腦系統的電源損耗，達到 電源控制的目的。The module 236' determines whether to turn off the phase-locked loop 232 according to a control signal PLLD (first control signal) of the power management module 236. The power management module 236 is coupled to the thyristor 234 and all of the peripheral modules 238 ′ for performing a power management method according to an embodiment of the present invention for controlling the phase locked loop 232 according to the power saving state of the processing unit 210 . Operation. Figure 3 is a flow chart showing a power management method in accordance with an embodiment of the present invention. As described above, the power management method according to an embodiment of the present invention can be performed by the power management module 236 as shown in FIG. Please also refer to Figure 2. First, when the computer system 200 is operating in the operating state and processing. The unit 21 is entering one of the control states, the lowest power consumption state C4, as in steps VIC09-0003I00-TW/0608-A41997-, ^^/Final/9 201040705 S310, the power management module 236 detects the status of all the peripheral modules 238 to determine whether a specific condition is met (step s320). Please note that the power management module 236 detects the status of the peripheral module 238 (e.g., power state) to determine whether the particular condition is met after all of the peripheral modules 238 are idle for a predetermined period of time. Since each peripheral module 238 has a low power consumption mode, the power management module 236 detects the state of the peripheral module 2 3 8 to determine whether the specific condition is consistent with the predetermined peripheral mode in the peripheral module. Whether the group is in the corresponding low power saving mode. In an embodiment, the predetermined peripheral module may include (but is not limited to the memory controller, a graphics controller, a USB controller, and a SATA controller, and the specific conditions are determined to be consistent when the following conditions are met: 1) The sufficiency controller operates in self-updating mode; (2) the drawing controller works in snapshot mode; (3) the USB controller sets the USB device to work in the output mode: and, * * WSATA control In other words, the SATA device is set to work in the partial/slumber mode. In other words, only when the above conditions (1H4) are met, the group 236 will judge that the specific condition is the compliance, , and / original e-module conditions. In the foregoing, since the above judgment is made after all the breaks are not in conformity with the specific set-set time, the other weeks are satisfied except that the g 1 edge weight group 238 is free to satisfy the above conditions (1)-(4). The state of the edge module is idle when the state of the peripheral module does not meet the special state. No), for example, the above condition (1)-(4) does not. When the piece corresponding to #+ 叮卩^乡S320 occurs , I will not do special treatment, the process community will bring me a good call. VIC09-0003I00-TW/ 0608-A41997-TW/FinaI/ 10 201040705 S. When the status of the peripheral module meets certain conditions (step S3 2〇@ 3 power management module 236 is set according to a preset control state, Then, the processing unit 210 enters a phase locked loop control state to control the operation of the phase locked loop (step S330). For example, in an embodiment, the basic input/output system (BI0S) of the computer system (not A control state setting option is provided to set the control state after entering the phase locked loop control state. In this embodiment, the phase locked loop control state has two control state setting values: the first control state (C4PG) And the second control state (C4pD) e, the set value will be stored in a register (not shown), for example, the set value i represents the first control state, and the set value 0 represents the second control state. 4 is a schematic diagram showing a power state of a central processing unit according to an embodiment of the present invention. As shown in FIG. 4, the power state of the central processing unit has a working state C0, a first power saving state C1, and a second power saving state. C2, the third province Electrical state C3, lowest power consumption state C4, and two possible phase-locked loop control states C4PG (first control state) and C4pD (second control state). Among them, states C0 to C4 are similar to those in FIG. The corresponding state, phase-locked loop control state C4PG and C4PD are selectively entered according to the set value in the register. For example, when the processing unit 21〇 enters the lowest power consumption state C4, 'if the register The set value in YES, the processing unit 21 〇 will enter the first control state (C4PG). Conversely, when the processing unit 210 enters the lowest power consumption state C4, if the set value in the register is 〇, the processing unit 210 will enter the second control state (C4pD). After the processing unit 21 enters the first or second control state, if any wake-up event is detected, the power management module 230 performs a recovery procedure to restore the processing unit 210 to the lowest power consumption state C4. . V1C09-0003I00-TW/ 〇6〇8-A41997-TW/Final/ 11 201040705 When the power control state is set to the first control state, the power & module 236 sends a control signal PLLG to the gate control unit 234, = The gate control unit 234 stops the clock output of the phase locked loop 232. At this point, the =circuit 232 (four) pulse output is blocked, but the phase-locked loop 232 is not do (four)' remains power. When the control state sets the control state, the management touch 236 (four) (four) calls plld to the phase-locked loop 232 '. After the phase-locked loop 232 receives the control signal pLLD, the lock circuit 232 will be completely closed. In the embodiment, when the control state is set to the second control state, the power management module 236 sends the control signal PLLD and the control signal C4psT〇p (third control signal) to the phase-locked loop 232 and the outside of the chip set 230, respectively. The clock generator 22 is (the source clock generating unit corresponding to the phase locked loop 232). After the phase locked loop 232 receives the control signal PLLD, the phase locked loop 232 will be fully closed. After the clock generator 220 receives the control signal (: 4 〇 11 〇 1), the clock generator 22 停 stops outputting the clock signal to the phase locked loop 232. After the processing unit 210 enters the phase locked loop control state, if a wakeup event is detected, the power management module 236 will perform a recovery procedure to cause the processing unit to return to the lowest power consumption state C4. Figure 5 is a flow chart showing a recovery procedure in accordance with an embodiment of the present invention. The power management method according to an embodiment of the present invention can be performed by the power management module 236 as shown in Figure 2. As shown in Fig. 5, referring to Fig. 4, in step S510, the power management module 236 first determines whether the processing unit 210 is in the first or first control state by the set value of the register. For example, in an embodiment, when the setting value of the register is 1 or ,, it can be determined that the processing unit 210 is respectively at the first of VIC09-0003I00-TW/ 0608-A41997-TW/Final/ 12 201040705 or The second control state. If it is in the first control state, it means that the location 210 is to return from the first control state to the C4 state, and the table is earlier than /0 21 . The set value judgment processing unit that wants to return from the second control state to the second control state is in the first control state; =0: the phase loop 232 benefits are not closed 'only the clock output is blocked by the brake 2 early 7G, thus recovering The program stops interrupting the phase-locked loop 232 directly through the inter-banking order _ Ο ,, and then proceeds to step s. When the set value judgment processing unit of ^ is determined to be in the second control state S530, the clock generator is judged, and when the control = is received, the clock generator 220 does not stop outputting the clock number. The generator 220 stops outputting the clock signal. When the pulse receives the control signal C4P (step s530), since the phase locked loop 232 is turned off and the external clock generator stops, the recovery program executes the steps SMG and the clock and starts. Phase locked loop 232. In step S540, t first starts the output of the source clock generation unit (also the instant pulse generator 220) corresponding to the phase-locked loop 232 and starts the phase-locked circuit after the source clock generation unit is started according to the step (10). 232, and then perform the steps. When the pulse generation H is not receiving the control signal (10) lamp (4), because the clock generator 22〇 does not stop outputting the clock signal, the recovery procedure directly executes step S55G to start the phase-locked loop 232. S560. In step _, the recovery program waits for the phase-locked loop 232 to start stable, and finally, the processing unit 21 is restored to the lowest power-saving state C4. 1: The following examples are provided to further illustrate the power supply tube VIC09-0003I00-TW/0608-A41997-TW/FinaV 13 201040705 of the present invention, but are not intended to limit the present invention. In the present embodiment, it is assumed that the processing unit 21 has not entered the minimum Wei power saving state C4 for a period of time and the set value of the register is 〇. After all the peripheral modules 238 are idle for a predetermined period of time, the power management module 236 detects the status of the peripheral module 238 to determine whether the specific conditions are met, that is, whether the foregoing conditions (1)_(4) are satisfied. Assuming that both conditions (1) and (4) are satisfied, and the specific conditions are not met, the power management module 236 causes the processing unit 21G to enter the human-phase-locked loop control state to control the operation of the phase-locked loop 232 according to the preset control state. . Since the setting value of the register is 0, the table does not enter the second control state, the power supply module 23rd PLLD phase-locked loop, the starter n, ^ ^ ^ circuit 232 receives the control signal PLLD, the phase-locked loop 232 will shut down the whole. In the implementation of the fiscal, the setting value of the register is 〇, indicating that the second control state is to be entered, the power management module 236 and the control signal (10) ST0P to the phase-locked return path = the clock of the control signal is generated 1^ 20. When the lock phase is tapped = then the phase lock loop 232 will be closed. After the control signal C4PST0P is received, the signal is sent to the phase-locked loop 232. Because of the two bio-a 22. The control state will be stopped when the output is stopped and the phase-locked loop 232 is closed. ^7:21() is entered and the second exit is stopped. After that, if the external clock generator's input execution-recovery program, the clock generation Ϊ22= control signal (10), indicating that the phase-locked loop is turned off and the external time is stopped, the recovery procedure starts first. Pulse Generation 'After the (4) generator 22Q startup is completed, VIC09-0003100-TW/0608-A41997-TW/FinaI/ 14 201040705 causes the processing unit 21G to return to the lowest power consumption state C4. As described above, the power management method and related chip and the brain system according to the present invention can control the state through a new phase-locked loop, and provide a power-saving state (ie, state C4) in the processing unit. The following phase-locked loop control = the target unit will always be in the lowest power consumption state when it is normally executed, which can reduce the power loss of the entire computer system more effectively and achieve the purpose of power supply control.
Ο 本發明之方法，或較型態或其部份，可以以程式错 含於實體媒體’如軟碟、光碟片、硬碟、或是隹 °、/、器可讀取(如電腦可讀取）儲存媒體，其中，告程 = = =’如電腦載人且執行時，此機器變成㈣參與 透過一 。本發明之方法與裝置也可以以程式碼型態 中如纖、或是任何傳輸 /、Α式碼被機S，如電腦接收、載 入且執仃時’此機H變成㈣參與本 般用途處理器實作時，程式碼結合處理器提 於應用特定邏輯電路之獨特裝置。 ’、二, 雖然本發明已以較佳實施例揭露 :定本發明’任何熟悉此項技藝者，在不脫離;=;乂 範圍當視後附之申請專利範圍二為因準此本發明之保護 【圖式簡單說明】 中.央處理器之電源狀 第1圖係顯示一習知的ACPI定義 態示意圖。 ^C^0〇〇3I〇〇-TW/0608-A4l997^TW/Fma]/ 15 201040705 第2圖係顯示一依據本發明實施例之電腦系統。 第3圖係顯示一依據本發明實施例之電源管理方法之 流程圖。 第4圖係顯示一依據本發明實施例之中央處理器之電 源狀態示意圖。 第5圖係顯示一依據本發明實施例之恢復程序之流程 圖。 【主要元件符號說明】 C0-C4、C4PD、C4PG〜狀態； 200〜電腦系統； 210〜處理單元； 220〜時脈產生器； 230〜晶片組； 232〜鎖相迴路； 234〜閘控單元； 236〜電源管理模組； 23 8〜周邊模組； C4PSTOP、PLLD、PLLG-控制訊號； S310-S330〜執行步驟； S510-S560〜執行步驟。 VIC09-0003I00-TW/ 0608-A41997-TW/FinaV 16"Ο The method of the present invention, or a relatively type or part thereof, may be misinterpreted in a physical medium such as a floppy disk, a CD, a hard disk, or a readable device, such as a computer readable computer. Take) the storage medium, where the ticket ===' If the computer is manned and executed, the machine becomes (4) participating through one. The method and device of the present invention can also be used in the program type, such as fiber, or any transmission/reception code, such as a computer, when the computer receives, loads, and executes, the machine H becomes (four) participates in the general purpose. When the processor is implemented, the code is combined with the processor to provide a unique means of applying a particular logic circuit. The present invention has been disclosed in the preferred embodiments of the present invention. Any one skilled in the art will be able to refrain from departing from the scope of the invention; [Simple description of the diagram] The power supply of the central processing unit Fig. 1 shows a conventional ACPI definition state diagram. ^C^0〇〇3I〇〇-TW/0608-A4l997^TW/Fma]/ 15 201040705 FIG. 2 shows a computer system in accordance with an embodiment of the present invention. Figure 3 is a flow chart showing a power management method in accordance with an embodiment of the present invention. Figure 4 is a diagram showing the state of a power supply of a central processing unit in accordance with an embodiment of the present invention. Figure 5 is a flow chart showing a recovery procedure in accordance with an embodiment of the present invention. [Main component symbol description] C0-C4, C4PD, C4PG~ state; 200~ computer system; 210~ processing unit; 220~ clock generator; 230~ chipset; 232~ phase-locked loop; 234~ gate control unit; 236~ power management module; 23 8~ peripheral module; C4PSTOP, PLLD, PLLG-control signal; S310-S330~ execution step; S510-S560~ execution step. VIC09-0003I00-TW/ 0608-A41997-TW/FinaV 16"