TW201038956A - Probing system for integrated circuit device - Google Patents

Probing system for integrated circuit device Download PDF

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TW201038956A
TW201038956A TW099109815A TW99109815A TW201038956A TW 201038956 A TW201038956 A TW 201038956A TW 099109815 A TW099109815 A TW 099109815A TW 99109815 A TW99109815 A TW 99109815A TW 201038956 A TW201038956 A TW 201038956A
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Taiwan
Prior art keywords
test
integrated circuit
module
circuit component
transceiver module
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TW099109815A
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Chinese (zh)
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TWI392888B (en
Inventor
Cheng-Wen Wu
Chih-Tsun Huang
Yu-Tsao Hsing
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Nat Univ Tsing Hua
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Publication of TWI392888B publication Critical patent/TWI392888B/en

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Abstract

A probing system for integrated circuit device, which transmits testing data/signal between an automatic test equipment (ATE) and an integrated circuit device, is disclosed. The probing system comprising a test head having a first transceiving module; a test station having a test unit couple to the test head to perform test operation; a communication module having a second transceiving module configured to exchange data with the first transceiving module; an integrated circuit device having at least one core circuit being tested; and at least one test module having a self-test circuit couple to the core circuit and the communication module for performing the core circuit self-testing.

Description

201038956 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種積體電路元件檢測系統。 【先前技術】 一般而言,晶圓上之積體電路元件必須先行測試其電 氣特性,以判定積體電路元件是否良好。良好的積體電路 將被選出以進行後續之封裝製程,而不良品將被捨棄以避 免增加額外的封裝成本。 習知自動檢測設備(automatic test equipment,ATE)係 利用一測試卡之探針接觸一待測元件之訊號墊,以便傳送 一量測機台之測試訊號至一待測元件,並將量測到之電性 參數傳送回該量測機台。惟,隨著半導體製造技術不斷地 創新,積體電路元件(例如電晶體)之工作速度亦不斷地提昇 ,習知技藝利用探針(即機械式檢測)檢測晶片,因而其整體 時間精密度(overall time accuracy,OTA)無法趕上快速發展 的晶片工作速度。因此,習知之自動檢測設備顯然無法適 用於未來之快速積體電路元件之電性測試。 【發明内容】 本發明係提供一積體電路元件檢測系統,其可於一包 含一第一收發模組之測試機及由該測試機進行測試之積體 電路元件之間傳輸如檢測訊號及經測試之f氣參數等測試 資料。 -實施範財,所述之積體電路元件包含—核心電路 、-電連接於該核心電路之自我㈣電路(Buiu_in s心如 201038956 circuit,BIST)、一用於控制該自我測試電路之操作之控制 器以及一用於與第一收發模組交換測試資料之第二收發模 組0201038956 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an integrated circuit component detecting system. [Prior Art] In general, an integrated circuit component on a wafer must first be tested for its electrical characteristics to determine whether the integrated circuit component is good. A good integrated circuit will be selected for subsequent packaging processes, and defective products will be discarded to avoid additional packaging costs. The automatic test equipment (ATE) uses a probe of a test card to contact a signal pad of a device to be tested, so as to transmit a test signal of a measuring machine to a device to be tested, and measure The electrical parameters are transmitted back to the measuring machine. However, as semiconductor manufacturing technology continues to innovate, the operating speed of integrated circuit components (such as transistors) continues to increase, and conventional techniques use probes (ie, mechanical inspection) to detect wafers, thus providing overall time precision ( Overall time accuracy (OTA) cannot keep up with the fast-growing wafer work speed. Therefore, the conventional automatic detecting device is obviously not suitable for the electrical test of the future rapid integrated circuit components. SUMMARY OF THE INVENTION The present invention provides an integrated circuit component detecting system that can transmit a detection signal and a test signal between a test machine including a first transceiver module and an integrated circuit component tested by the tester. Test data such as test gas parameters. Implementing a fan, the integrated circuit component comprising - a core circuit, an electrical (four) circuit electrically connected to the core circuit (Buiu_in s heart such as 201038956 circuit, BIST), and an operation for controlling the self-test circuit a controller and a second transceiver module for exchanging test data with the first transceiver module

另一實施範例中,一積體電路元件之檢測系統包含一 具有一第一收發模組之測試頭以及一具有一檢測單元之測 试台,s亥檢測單元耦接於該測試頭以進行測試。該檢測系 統另包含一通訊模組,該通訊模組具有一第二收發模組, 其可與第一收發模組以無線通訊方式進行資料交換;一積 體電路元件,其具有一待測核心電路;以及一測試模組, 其具有一耦接該核心電路及通訊模組之自我測試電路,以 進行核心電路之自我測試。 再一實施範例中,一積體電路元件之檢測系統包含一 測試頭、一測試台和一積體電路元件。該測試頭包含一第 -收發模組。該測試台包含一檢測單元,該檢測單元麵接 於該測試頭以進行測試。該積體電路元件包含一通訊模組 、複數個被測試之核心電路和至少—個測試模組。各測試 模組皆具有-純錢等核心電路及該通訊模組之自我測 試電路以進行該等核心電路之自我測試。該等核心電路係 分別製作於-晶粒上。該通訊模組包含一第二收發模級以 设定與該第-收發模組間以進行f料交換1通訊模組、 該等核心電路和該至少—個測試模組係封裝於單—封裝内 【實施方式】 圖1例示本發明之一實施例之藉栌 J义積體電路兀件檢測系統 201038956 1 〇 ’其係利用無線通訊在一測試機台20與一待測元件30之 間傳送測試資料。該測試機台20包含一第一收發模組22、 電氣連接於該第一收發模組22之物理層模组24、一電氣 連接於該物理層模組24之檢測單元26以及一電氣連接於該 物理層模組24之診斷單元28。該待測元件30可為一系統單 晶片(system on chip),其包含一核心電路32、一電氣連接 於該核心電路32之自我測試電路34、一用以控制該自我測 ❹ 試電路34之控制器36以及一可與該第一收發模組22交換測 試資料之第二收發模組38。該第一收發模組22與第二收發 模組38各包含一收發器及一天線。 該核心電路32可為記憶體電路、邏輯電路或類比電路 。該自我測試電路34之設計技術可參考本案發明人之中華 民國專利第088103352號申請案及第09〇1〇7845號申請案。 較佳地,該待測元件30另包含一電氣連接於該第二收發模 組38之時脈產生器40以及一電氣連接於該第二收發模組38 〇 之電力穩壓器42,其中該測試機台20藉由該第一收發模組 22發射一射頻訊號,而該第二收發模組刊接收該射頻訊號 以驅動該電力穩壓器42產生該待測元件3〇運作所需之電力 。此外,該待測元件30可另包含一標示暫存器料,用以儲 存該待測元件30之識別碼(iD)。 在進行電性檢測時,該測試機台2〇藉由該第一收❹ 組22發射一射頻訊號,而該待測元件3〇之第二收發模組“ 接收該射頻訊號以驅動該電力穩壓器42產生該待測元件 運作所需之電力。該測試機台2〇之檢測單元26再經由該第 201038956 一收發模組22設定各待測元件3〇之識別碼,而各待測元件 3 0係將其識別碼儲存於該標示暫存器44。之後,該檢測單 元26再傳送啟始指令至該待測元件3〇之第二收發模組“以 啟動該自我測試電路34進行該核心電路32之電性檢測。 在一實施例中,該診斷單元28收集各待測元件,3〇完成 測試後傳回之測試資料,即可據以診斷各待測元件3〇之優 劣並分析不良元件之失效原因。該物理層模組24控制資料 0 訊號之傳輸及接收。 圖2例示本發明另一實施例之積體電路元件測試系統 80,其係應用於一包含複數個待測元件3〇之晶圓9〇的電性 檢測。特而言之,積體電路元件測試系統8〇係應用於晶圓 層次(wafer level)之電性檢測。此外,該晶圓9〇可另包含一 圍繞該待測元件30之電力供應線92,且該待測元件3〇運作 所需之電力係取自該電力供應線92,而非經由該電力穩壓 器42接收射頻訊號產生之電力。特而言之,該電力供應線 Q 92係設置於該晶圓90之切割線上。 圖3例示本發明另一實施例之積體電路元件測試系統 70,其係應用於一封裝晶粒72的最終測試卬仙丨test)。如圖 2所示之晶圓90沿著該電力供應線%切割成個別之待測元 件30。經圖2之積體電路元件測試系統8〇之篩選,具有良好 電氣特性之待測元件30將包裝成該封裝晶粒72,而不良之 待測元件30將被捨棄。之後,該測試機台20之檢測單元26 經由該第一收發模組22傳送啟始指令至該待測元件3〇之第 二收發模組38以啟動該自我測試電路34進行該核心電路32 201038956 之電性檢測。之後,該診斷單 單兀2 8收集該待測元件3 〇完成 測試後傳回之測試資料,g 計即可據以診斷該待測元件30之優 劣並分析不良元件之失效原因。In another embodiment, the detection system of an integrated circuit component includes a test head having a first transceiver module and a test bench having a detection unit coupled to the test head for testing. . The detection system further includes a communication module, the communication module has a second transceiver module, which can exchange data with the first transceiver module in a wireless communication manner; an integrated circuit component having a core to be tested And a test module having a self-test circuit coupled to the core circuit and the communication module for self-testing of the core circuit. In still another embodiment, an integrated circuit component detection system includes a test head, a test station, and an integrated circuit component. The test head includes a first transceiver module. The test station includes a detection unit that is flanked by the test head for testing. The integrated circuit component comprises a communication module, a plurality of tested core circuits and at least one test module. Each test module has a core circuit such as pure money and a self-test circuit of the communication module for self-testing of the core circuits. These core circuits are fabricated separately on the die. The communication module includes a second transceiver module for setting a communication module with the first transceiver module, and the core circuit and the at least one test module are packaged in a single package. [Embodiment] FIG. 1 illustrates an embodiment of the present invention, which utilizes wireless communication to transmit between a test machine 20 and a device under test 30. Test data. The test machine 20 includes a first transceiver module 22, a physical layer module 24 electrically connected to the first transceiver module 22, a detection unit 26 electrically connected to the physical layer module 24, and an electrical connection. The diagnostic unit 28 of the physical layer module 24. The device under test 30 can be a system on chip, including a core circuit 32, a self-test circuit 34 electrically connected to the core circuit 32, and a control circuit 34 for controlling the self-test circuit 34. The controller 36 and a second transceiver module 38 that can exchange test data with the first transceiver module 22. The first transceiver module 22 and the second transceiver module 38 each include a transceiver and an antenna. The core circuit 32 can be a memory circuit, a logic circuit or an analog circuit. The design technique of the self-test circuit 34 can be referred to the application of the inventor of the Chinese Patent No. 088103352 and the application No. 09〇1784. Preferably, the device under test 30 further includes a clock generator 40 electrically connected to the second transceiver module 38 and a power regulator 42 electrically connected to the second transceiver module 38. The test machine 20 transmits an RF signal through the first transceiver module 22, and the second transceiver module receives the RF signal to drive the power regulator 42 to generate power required for the operation of the device under test 3 . In addition, the device under test 30 may further include an identifier register to store an identification code (iD) of the device under test 30. During the electrical detection, the test machine 2 transmits an RF signal by the first receiving group 22, and the second transceiver module of the device under test 3 receives the RF signal to drive the power stable. The voltage generating device 42 generates the power required for the operation of the device under test. The detecting unit 26 of the testing machine 2 further sets the identification code of each component to be tested through the 201038956 transceiver module 22, and each component to be tested The system stores the identification code in the identifier register 44. After that, the detecting unit 26 transmits a start command to the second transceiver module of the device under test 3 to "activate the self-test circuit 34 to perform the Electrical detection of the core circuit 32. In one embodiment, the diagnostic unit 28 collects the components to be tested, and the test data returned after the test is completed, thereby diagnosing the advantages and disadvantages of each component to be tested and analyzing the cause of failure of the defective component. The physical layer module 24 controls the transmission and reception of the data 0 signal. Fig. 2 illustrates an integrated circuit component test system 80 according to another embodiment of the present invention, which is applied to an electrical test of a wafer 9 comprising a plurality of devices to be tested. In particular, the integrated circuit component test system 8 is applied to the electrical detection of the wafer level. In addition, the wafer 9A may further include a power supply line 92 surrounding the device under test 30, and the power required for the operation of the device under test 3 is taken from the power supply line 92 instead of being stabilized via the power. The voltage converter 42 receives the power generated by the radio frequency signal. In particular, the power supply line Q 92 is disposed on the cutting line of the wafer 90. 3 illustrates an integrated circuit component test system 70 in accordance with another embodiment of the present invention, which is applied to a final test of a package die 72. The wafer 90 shown in Fig. 2 is cut along the power supply line % into individual test elements 30 to be tested. After screening by the integrated circuit component test system 8 of Fig. 2, the device under test 30 having good electrical characteristics will be packaged into the package die 72, and the defective component 30 to be tested will be discarded. Then, the detecting unit 26 of the testing machine 20 transmits a start command to the second transceiver module 38 of the device under test 3 via the first transceiver module 22 to activate the self-test circuit 34 to perform the core circuit 32 201038956 Electrical detection. Thereafter, the diagnostic unit 28 collects the test data returned by the device under test 3 after the test is completed, and the g meter can be used to diagnose the quality of the device under test 30 and analyze the cause of failure of the defective device.

圖4例不本發明另一實施例之積體電路元件檢測系統 6〇。該積體電路元件檢測系統之測試機台20另包含一電 氣連接於市電之輸送裝置62。該待測元件3〇係設置於一電 路板上,該電路板5G可經由於輸送裝置㈣氣連接於市 電’而該待測元件30運作所需之電力係取自該電路板%, 亦即間接地取自該輸送裝置62。該輸送裝置62可將該電路 板50傳送至一預定測試位置64,由該測試機台之檢測單 元26經由該第一收發模組22傳送啟始指令至該待測元件3〇 之第二收發模組38以啟動該自我測試電路34進行該核心電 路32之電性檢測。之後,該診斷單元28收集各待測元件邛 凡成測試後傳回之測試資料,即可據以診斷各待測元件 之是否符合電氣性質之規格並分析不良元件之失效原因。 圖1所示之積體電路元件檢測系統10可改變其内部模 組或元件之配置而進行調整,以增加多種應用的彈性。 圖5例示本發明另一實施例之積體電路元件檢測系統 MO。該積體電路元件檢測系統100包含一測試機u〇及—待 測之積體電路元件(DUT)l20。測試機110包含一測試頭m 、—測試台112及一承載器113。該測試台112包含一診斷單 元132及一檢測單元134,其中該診斷單元Π2屬自由選項, 其可提供診斷功能。測試頭111包含一物理層模組115及一 柄接於物理層模組U5之第一收發模組114。該物理層模組 201038956 115耦接於該檢測單元134,而該診斷單元132耦接於該檢測 單元I34。承載器113係運載DUT 120,且包含一通訊模組116 及一電力穩壓器117。通訊模組116包含一第二收發模組13〇 、一通訊控制器118及一時脈產生器119。 通訊控制器118電耦接該第二收發模組13〇,該時脈產 生器119電連接該第二收發模組130、通訊控制器U8&dut 120以提供時脈訊號。DUT 120(例如系統單晶片(s〇c))包含 ^ 一核心電路121及一測試模組12 2。一實施例中,測試模組Fig. 4 is a view showing an integrated circuit component detecting system of another embodiment of the present invention. The test machine 20 of the integrated circuit component detecting system further includes a conveyor 62 electrically connected to the mains. The device under test 3 is disposed on a circuit board, and the circuit board 5G can be connected to the mains via the transmission device (4), and the power required for the operation of the device under test 30 is taken from the circuit board %, that is, The grounding is taken from the conveying device 62. The transport device 62 can transmit the circuit board 50 to a predetermined test position 64, and the detecting unit 26 of the test machine transmits a start command to the second transceiver of the device under test through the first transceiver module 22 The module 38 activates the self-test circuit 34 to perform electrical detection of the core circuit 32. Then, the diagnostic unit 28 collects the test data returned by each of the components to be tested, and then diagnoses whether the components to be tested meet the specifications of the electrical properties and analyzes the failure causes of the defective components. The integrated circuit component sensing system 10 of Figure 1 can be modified by changing the configuration of its internal modules or components to increase the flexibility of a variety of applications. Fig. 5 illustrates an integrated circuit component detecting system MO of another embodiment of the present invention. The integrated circuit component detecting system 100 includes a tester u and a integrated circuit component (DUT) l20 to be tested. The test machine 110 includes a test head m, a test station 112, and a carrier 113. The test station 112 includes a diagnostic unit 132 and a detection unit 134, wherein the diagnostic unit Π2 is a free option that provides diagnostic functionality. The test head 111 includes a physical layer module 115 and a first transceiver module 114 that is coupled to the physical layer module U5. The physical layer module 201038956 is coupled to the detecting unit 134, and the diagnostic unit 132 is coupled to the detecting unit I34. The carrier 113 carries the DUT 120 and includes a communication module 116 and a power regulator 117. The communication module 116 includes a second transceiver module 13A, a communication controller 118, and a clock generator 119. The communication controller 118 is electrically coupled to the second transceiver module 13A. The clock generator 119 is electrically connected to the second transceiver module 130 and the communication controller U8&dut 120 to provide a clock signal. The DUT 120 (e.g., system single chip (s〇c)) includes a core circuit 121 and a test module 12 2 . In one embodiment, the test module

122包含一記憶體BIST 123、一邏輯BIST 124、一類比BIST 125及一測試控制器126。另一實施例中,該測試模組j 22 可僅包含記憶體BIST 123、邏輯BIST 124或類比BIST 125 ’或任二個連接至測試控制器126之BIST電路之結合。122 includes a memory BIST 123, a logic BIST 124, an analog BIST 125, and a test controller 126. In another embodiment, the test module j 22 may only include a combination of the memory BIST 123, the logic BIST 124 or the analog BIST 125 ' or any of the BIST circuits connected to the test controller 126.

DUT 120可位於該承載器113上,且自該承載器ι13獲得 操作電力。另外,DUT 120可由輸送裝置傳送至預定位置。 一實施例中’核心電路121可包含記憶體電路、邏輯電路及 〇 類比電路。核心電路121耦接記憶體BIST 123、邏輯BIST 124及類比BIST 125’且該些BIST電路之操作係由測試控制 器126控制。另一實施例中,核心電路ι21可為單一之記憶 體電路、邏輯電路或類比電路,或任兩上述電路之結合。 該核心電路121係耦接相應之記憶體BIST 123、邏輯BIST 124或類比BIST 125。檢測訊號及經測試之電氣參數等測試 資料係藉由該第一收發模組丨14及第二收發模組13〇以無線 通訊方式傳輸於測試頭11丨及承載器U3之間。換言之,第 一收發模組114及第二收發模組13〇係相互交換測試資料。 201038956 該物理層模組115及通訊控制器118分別控制資料訊號之傳 送及接收。 一實施例中,第一收發模組114及第二收發模組13〇各 包含一收發器及一天線。電力穩壓器117電連接通訊模組 116及DUT 120。測試機11 〇由該第一收發模組丨丨4傳送射頻 訊號,該第二收發模組130接收射頻訊號以驅動電力穩壓器 117 ’從而產生DUT 120所需之操作電力。 0 圖6例示本發明另一實施例之積體電路元件檢測系統 140。相較於圖5所示之系統1〇〇,測試模組122係改變為包 含於測試機110,之承載器113,中。因此,DUT 120,僅包含核 心電路121而易於製造。電力穩壓器117係電連接通訊模組 116、測試模組122及DUT 120·。 圖7例示本發明另一實施例之積體電路元件檢測系統 150。相較於圖5,通訊模組116係改變為包含於Dut 12〇,, 中。因此,DUT 120·,包含核心電路121、測試模組122及通 〇 訊模組116,且該測試機110"之承載器113,,僅包含電力穩壓 器U7。電力穩壓器117係電連接該DUT120,,。 圖8顯示根據本發明一實施例之可檢測複數duT之檢 測系統之訊號傳輸示意圖。測試機係包含一測試台及複數 個測試頭,各測試頭係相應於一通訊模組。如檢測訊號及 、’’二測试之電氣參數等測試資料係於測試頭及通訊模組間進 行無線傳輸。詳言之,所述通訊係以一對一的方式進行。 各通訊模組係電連接一測試模組,該測試模組係連接一核 心電路。因為本實施例包含複數個測試頭,故可顯著提昇 201038956 測試效率。 圖9顯示根據本發明另一實施例之可檢測複數dut之 檢測系統之訊號傳輸示意圖。測試機係包含一測試台及一 測試頭’該測試頭係相應於複數個通訊模組。如檢測訊號 及經測試之電氣參數等測試資料係於測試頭及複數個通訊 模組間進行無線傳輸。詳言之,所述通訊係以一對多的方 式進行。各通訊模組係耦接一測試模組,該測試模組係連 ^ 接一核心電路0 ❹ 圖10例示本發明另一實施例之積體電路元件檢測系統 1000。該積體電路元件檢測系統1000包含一測試器i〇i〇和 一 DUT 1020。該測試器1 〇 1 〇包含一測試頭i J i、一測試台 1012和一承載器1〇13。該測試台1〇12包含一診斷單元i 〇32 和一檢測單元1034,其中該診斷單元1〇32係一選用元件以 提供診斷功能。該測試頭1011包含一物理層模組1〇15和一 搞接至該物理層模組1015之第一收發模組1〇14。該物理層 〇 模組1015耦接至該檢測單元1034,而該診斷單元1032亦耦 接至檢測單元1034。該承載器1 〇 13係設定以裝載該DUT 1020,並包含一電力穩壓器1〇17。 該運用3D封裝技術之DUT 1020包含一通訊模組ι〇16 、一測試模組1022和複數個核心電路1 〇21,其中該通訊模 組1016、該測試模組1〇22和該等核心電路1021皆分別製作 於一晶粒上。該通訊模組1 〇 16包含一通訊控制器丨〇丨8、一 時脈產生器1019和一第二收發模組1〇3〇。該通訊控制器 1018係電性耦接至該第二收發模組1〇3〇,而該時脈產生器 •11- 201038956 1019係電性耦接至該第二收發模組1030、該通訊控制器 1 01 8及該DUT 1020以提供時脈訊號。在一實施例中,該測 試模組1022包含一記憶體BIST 1023、一邏輯BIST 1024、 一類比BIST 1〇25和一測試控制器1026。在另一實施例中, 該測試模組1022可僅包含記憶體BIST 1023、邏輯BIST 1024或類比BIST 1025,或任二個連接至測試控制器1〇26之 BIST電路之結合。 ❹ 該DUT 120可位於該承載器1013上,且自該承載器1013 獲得操作電力。另外,DUT 1 020可由輸送裝置傳送至預定 位置。在一實施例中,該等核心電路1021可包含記憶體電 路、邏輯電路及類比電路。該等核心電路1021耦接至該記 憶體BIST 1023、該邏輯BIST 1024及該類比BIST 1025,且 該等BIST電路之操作係由該測試控制器1026所控制。另一 實施例中,該等核心電路1021可為單一之記憶體電路、邏 輯電路或類比電路,或任兩上述電路之結合。該等核心電 〇 路1021係耦接至相應之記憶體BIST 1023、邏輯BIST 1024 或類比BIST 1 025。檢測訊號及經測試之電氣參數等測試資 料係藉由該第一收發模組1014及第二收發模組1〇3〇以無線 通訊方式傳輸於測試頭1011及承載器1〇13之間。換言之, 第一收發模組1014及第二收發模組1030係相互交換測試資 料。該物理層模組1015及通訊控制器1018分別控制資料訊 號之傳送及接收。 在一實施例中,該第一收發模組1014及該第二收發模 組1030各包含一收發器及一天線。該電力穩壓器ι〇17電連 -12- 201038956 接至該通訊模組1016及DUT 1020。該測試器1 〇 1 〇由該第一 收發模組1014傳送射頻訊號,該第二收發模組1〇3〇接收射 頻訊號以驅動該電力穩壓器1017,從而產生該DUT 1020所 需之操作電力。 圖11例示本發明另一實施例之積體電路元件檢測系統 1 1 00。該積體電路元件檢測系統1 1 00包含一測試器丨丨丨〇和 一 DUT 1120。相較於圖10所示之積體電路元件檢測系統 0 1000,該運用3D封裝技術之DUT 1120包含一通訊模組1016 、複數個測試模組1022和複數個核心電路1〇21,其中各核 心電路1021係連同一測試模組1〇22製作於一晶粒上,而該 通訊模組101 6係另製作於一不同之晶粒。 圖12例示本發明另一實施例之積體電路元件檢測系統 1200。該積體電路元件檢測系統12〇〇包含一測試器121〇和 一 DUT 1220。相較於圖1〇所示之積體電路元件檢測系統 1000,該運用3D封裝技術之DUT 1220包含一通訊模組1016 〇 、一測試模組1 〇22和複數個核心電路1 〇21,其中該通訊模 組1016和該測試模組1〇22係製作於同一晶粒,且該晶粒不 同於該等核心電路1021之晶粒。 圖13例示本發明另一實施例之積體電路元件檢測系統 1300。該積體電路元件檢測系統13〇〇包含一測試器131〇和 一 DUT 1320。相較於圖1〇所示之積體電路元件檢測系統 1000,該第一收發模組1314和該第一收發模組1330係以不 同於無線方式之連線技術進行資料交換。在一實施例中, 該第一收發模組1314和該第一收發模組133〇係以有線方式 -13- 201038956 3資料交換°在另—實施財,該第-收發模組測和 以第收發模組1330係以光學連線方式進行資料交換。 ::技藝係以機械元件(探針)傳送測試資料,因而整體 a⑽度無法趕上快速發展的晶片卫作速度。相對地, 2明之積體電路元件檢測系統係利用不同方式在該測試 口與該待測元件之間傳送測試資料’因而整體時間精密 又與該待測元件之積體電路一致而不會受到機械元件之限 ΟThe DUT 120 can be located on the carrier 113 and obtain operating power from the carrier ι13. Additionally, the DUT 120 can be delivered to a predetermined location by the delivery device. In one embodiment, the core circuit 121 can include a memory circuit, a logic circuit, and a analog circuit. The core circuit 121 is coupled to the memory BIST 123, the logic BIST 124, and the analog BIST 125' and the operation of the BIST circuits is controlled by the test controller 126. In another embodiment, the core circuit ι21 can be a single memory circuit, a logic circuit or an analog circuit, or a combination of any two of the above. The core circuit 121 is coupled to the corresponding memory BIST 123, logic BIST 124 or analog BIST 125. The test data and the tested electrical parameters are transmitted between the test head 11 and the carrier U3 by means of the first transceiver module 14 and the second transceiver module 13 in a wireless communication manner. In other words, the first transceiver module 114 and the second transceiver module 13 exchange test data with each other. 201038956 The physical layer module 115 and the communication controller 118 respectively control the transmission and reception of data signals. In one embodiment, the first transceiver module 114 and the second transceiver module 13 each include a transceiver and an antenna. The power regulator 117 is electrically coupled to the communication module 116 and the DUT 120. The test machine 11 transmits an RF signal from the first transceiver module 丨丨4, and the second transceiver module 130 receives the RF signal to drive the power regulator 117' to generate the operating power required by the DUT 120. Figure 6 illustrates an integrated circuit component detecting system 140 in accordance with another embodiment of the present invention. Compared to the system 1 shown in FIG. 5, the test module 122 is changed to be included in the carrier 113 of the test machine 110. Therefore, the DUT 120 includes only the core circuit 121 and is easy to manufacture. The power regulator 117 is electrically connected to the communication module 116, the test module 122, and the DUT 120·. Fig. 7 illustrates an integrated circuit component detecting system 150 according to another embodiment of the present invention. Compared with FIG. 5, the communication module 116 is changed to be included in the Dut 12,. Therefore, the DUT 120· includes the core circuit 121, the test module 122, and the communication module 116, and the carrier 113 of the test machine 110" only includes the power regulator U7. A power regulator 117 is electrically connected to the DUT 120. Figure 8 is a diagram showing the signal transmission of a detection system capable of detecting a complex number of duTs in accordance with an embodiment of the present invention. The test machine system includes a test bench and a plurality of test heads, and each test head corresponds to a communication module. Test data such as the test signal and the electrical parameters of the ''two test' are transmitted wirelessly between the test head and the communication module. In particular, the communication is performed in a one-to-one manner. Each communication module is electrically connected to a test module, and the test module is connected to a core circuit. Since this embodiment includes a plurality of test heads, the test efficiency of 201038956 can be significantly improved. Figure 9 is a diagram showing the signal transmission of a detection system capable of detecting a complex dut according to another embodiment of the present invention. The test machine system includes a test stand and a test head. The test head corresponds to a plurality of communication modules. Test data such as test signals and tested electrical parameters are transmitted wirelessly between the test head and a plurality of communication modules. In particular, the communication is performed in a one-to-many manner. Each communication module is coupled to a test module, which is connected to a core circuit 0. FIG. 10 illustrates an integrated circuit component detection system 1000 according to another embodiment of the present invention. The integrated circuit component detecting system 1000 includes a tester i〇i〇 and a DUT 1020. The tester 1 〇 1 〇 includes a test head i J i, a test stand 1012 and a carrier 1〇13. The test station 110 includes a diagnostic unit i 〇 32 and a detection unit 1034, wherein the diagnostic unit 〇 32 is an optional component to provide a diagnostic function. The test head 1011 includes a physical layer module 1〇15 and a first transceiver module 1〇14 connected to the physical layer module 1015. The physical layer 10 module 1015 is coupled to the detecting unit 1034, and the diagnostic unit 1032 is also coupled to the detecting unit 1034. The carrier 1 〇 13 is configured to load the DUT 1020 and includes a power regulator 1〇17. The DUT 1020 using the 3D packaging technology includes a communication module ι 16 , a test module 1022 and a plurality of core circuits 1 〇 21 , wherein the communication module 1016 , the test module 1 〇 22 and the core circuits 1021 are each fabricated on a die. The communication module 1 〇 16 includes a communication controller 丨〇丨8, a clock generator 1019 and a second transceiver module 1〇3〇. The communication controller 1018 is electrically coupled to the second transceiver module 1 〇 3 〇, and the clock generator 11-201038956 1019 is electrically coupled to the second transceiver module 1030, the communication control The device 1 01 8 and the DUT 1020 provide a clock signal. In one embodiment, the test module 1022 includes a memory BIST 1023, a logic BIST 1024, an analog BIST 1〇25, and a test controller 1026. In another embodiment, the test module 1022 can include only a combination of a memory BIST 1023, a logical BIST 1024, or an analog BIST 1025, or any two BIST circuits connected to the test controller 1〇26. ❹ The DUT 120 can be located on the carrier 1013 and obtain operating power from the carrier 1013. Alternatively, the DUT 1 020 can be transported by the transport device to a predetermined location. In one embodiment, the core circuits 1021 can include memory circuits, logic circuits, and analog circuits. The core circuits 1021 are coupled to the memory BIST 1023, the logic BIST 1024, and the analog BIST 1025, and the operations of the BIST circuits are controlled by the test controller 1026. In another embodiment, the core circuits 1021 can be a single memory circuit, a logic circuit or an analog circuit, or a combination of any of the above. The core circuits 1021 are coupled to corresponding memory BIST 1023, logic BIST 1024, or analog BIST 1 025. The test signals and the tested electrical parameters are transmitted between the test head 1011 and the carrier 1〇13 by wireless communication through the first transceiver module 1014 and the second transceiver module 1〇3〇. In other words, the first transceiver module 1014 and the second transceiver module 1030 exchange test data with each other. The physical layer module 1015 and the communication controller 1018 respectively control transmission and reception of data signals. In one embodiment, the first transceiver module 1014 and the second transceiver module 1030 each include a transceiver and an antenna. The power regulator ι〇17 electrical connection -12- 201038956 is connected to the communication module 1016 and the DUT 1020. The tester 1 〇1 传送 transmits the RF signal by the first transceiver module 1014, and the second transceiver module receives the RF signal to drive the power regulator 1017, thereby generating the operation required by the DUT 1020. electric power. Fig. 11 illustrates an integrated circuit component detecting system 1 100 of another embodiment of the present invention. The integrated circuit component detecting system 1 100 includes a tester 丨丨丨〇 and a DUT 1120. Compared with the integrated circuit component detecting system 0 1000 shown in FIG. 10, the DUT 1120 using the 3D packaging technology includes a communication module 1016, a plurality of test modules 1022, and a plurality of core circuits 1〇21, wherein each core The circuit 1021 is fabricated on a die by the same test module 1 22, and the communication module 101 6 is fabricated on a different die. Fig. 12 illustrates an integrated circuit component detecting system 1200 according to another embodiment of the present invention. The integrated circuit component detecting system 12A includes a tester 121A and a DUT 1220. Compared with the integrated circuit component detecting system 1000 shown in FIG. 1A, the DUT 1220 using the 3D packaging technology includes a communication module 1016 〇, a test module 1 〇 22, and a plurality of core circuits 1 〇 21, wherein The communication module 1016 and the test module 1 22 are fabricated on the same die, and the die is different from the die of the core circuit 1021. Fig. 13 illustrates an integrated circuit component detecting system 1300 according to another embodiment of the present invention. The integrated circuit component detecting system 13A includes a tester 131A and a DUT 1320. The first transceiver module 1314 and the first transceiver module 1330 exchange data in a different wireless connection mode than the integrated circuit component detection system 1000 shown in FIG. In an embodiment, the first transceiver module 1314 and the first transceiver module 133 are in a wired manner - 13 - 201038956 3 data exchange, in another implementation, the first transceiver module measures The transceiver module 1330 exchanges data in an optical connection manner. :: The art system transmits test data with mechanical components (probes), so the overall a(10) degree cannot keep up with the fast-growing wafer security speed. In contrast, the integrated circuit component detection system of the second embodiment transmits the test data between the test port and the device to be tested in different manners, and thus the overall time precision is consistent with the integrated circuit of the device to be tested without being mechanically Component limit

制,可應用於高速積體電路之電性檢測。特而言之,本發 明之積體電路元件檢測系統除了可進行該待測元件之電性 檢測之外’亦可用以診斷該待測元件之失效原因。除此之 外,本發明之積體電路元件檢測系統不限於應用於單一晶 粒之積體電路元件,而可應用於以戰裳技術製成之積體 電路元件。 本發明之技術内容及技術特點已揭示如上,然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種種 不背離本發明精神之替換及修飾。因此,本發明之保護範 圍應不限於實施例所揭示者,而應包括各種不背離本發明 之替換及修飾,並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1例示本發明之一實施例之積體電路元件檢測系統 圖2例示本發明另一實施例之積體電路元件檢測系統 圖3例示本發明另一實施例之積體電路元件檢測系統 圖4例示本發明另一實施例之積體電路元件檢測系統 圖5例示本發明另一實施例之積體電路元件檢測系統 •14- 201038956 圖6例示本發明另一實施例之積體電路元件檢測系統; 圖7例示本發明另一實施例之積體電路元件檢測系統; 圖8及9例示本發明之實施例之積體電路元件檢測系統 之訊號傳輸示意圖; 圖10例示本發明另一實施例之積體電路元件檢測系統 圖11例示本發明另一實施例之積體電路元件檢測系統 〇 , 圖12例不本發明另一實施例之積體電路元件檢測系统 ;以及 圖13例示本發明另一實施例之積體電路元件檢測系統 【主要元件符號說明】 1 〇積體電路元件檢測系統 22第一收發模組 26 檢測單元 30待測元件 34自我測試電路 38第二收發模組 42電力穩壓器 50 電路板 62輸送裝置 70積體電路元件檢測系統 80積體電路元件檢測系統 20 測試機台 24物理層模組 28診斷單元 32 核心電路 36控制器 40時脈產生器 44標示暫存器 60積體電路元件檢測系統 64預定測試位置 72封裝晶粒 90 晶圓 -15- 201038956 100積體電路元件檢測系統110測試機It can be applied to the electrical detection of high-speed integrated circuits. In particular, the integrated circuit component detecting system of the present invention can be used to diagnose the cause of failure of the component to be tested, in addition to performing electrical detection of the device to be tested. In addition, the integrated circuit component detecting system of the present invention is not limited to the integrated circuit component applied to a single crystal grain, but can be applied to an integrated circuit component which is manufactured by the technique. The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention is not limited by the scope of the invention, and the invention is intended to cover various alternatives and modifications. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing an integrated circuit component detecting system according to an embodiment of the present invention. FIG. 2 is a view showing an integrated circuit component detecting system according to another embodiment of the present invention. FIG. 3 is a view showing an integrated body according to another embodiment of the present invention. Circuit element detecting system FIG. 4 illustrates an integrated circuit component detecting system according to another embodiment of the present invention. FIG. 5 illustrates an integrated circuit component detecting system according to another embodiment of the present invention. FIG. 6 illustrates another embodiment of the present invention. Integrated circuit component detecting system; FIG. 7 illustrates an integrated circuit component detecting system according to another embodiment of the present invention; FIGS. 8 and 9 are schematic diagrams showing signal transmission of the integrated circuit component detecting system of the embodiment of the present invention; Integral circuit component detecting system according to another embodiment of the present invention, FIG. 11 illustrates an integrated circuit component detecting system according to another embodiment of the present invention, and FIG. 12 illustrates an integrated circuit component detecting system according to another embodiment of the present invention; 13 shows an integrated circuit component detecting system according to another embodiment of the present invention. [Main component symbol description] 1 Cascade circuit component detecting system 22 first transceiver module 26 detection unit 30 device under test 34 self-test circuit 38 second transceiver module 42 power regulator 50 circuit board 62 transport device 70 integrated circuit component detection system 80 integrated circuit component detection system 20 test machine 24 physical layer mode Group 28 Diagnostic Unit 32 Core Circuit 36 Controller 40 Clock Generator 44 Labels Register 60 Integrated Circuit Component Detection System 64 Predetermined Test Location 72 Package Die 90 Wafer-15 - 201038956 100 Integrated Circuit Component Detection System 110 Test machine

111測試頭 113承載器 115物理層模組 117電力穩壓器 119時脈產生器 121核心電路 123記憶體BIST Ο 125 類比 BIST 130第二收發模組 134檢測單元 110'測試機 120' DUT 110"測試機 120" DUT 10 10測試器 〇 1 012測試台 1014第一收發模組 1016通訊模組 1 01 8通訊控制器 1020 DUT 1022測試模組 1024 邏輯BIST 1026測試控制器 1032診斷單元 112測試台 114第一收發模組 116通訊模組 11 8通訊控制器 120 DUT 122測試模組 124 邏輯 BIST 126測試控制器 132診斷單元 140積體電路元件檢測系統 1131承載器 1 50積體電路元件檢測系統 113"承載器 1000積體電路元件檢測系統 1011測試頭 1013承載器 1015物理層模組 1017電力穩壓器 1019時脈產生器 1021核心電路111 test head 113 carrier 115 physical layer module 117 power regulator 119 clock generator 121 core circuit 123 memory BIST Ο 125 analog BIST 130 second transceiver module 134 detection unit 110 'test machine 120 ' DUT 110 " Test machine 120" DUT 10 10 tester 〇 1 012 test bench 1014 first transceiver module 1016 communication module 1 01 8 communication controller 1020 DUT 1022 test module 1024 logic BIST 1026 test controller 1032 diagnostic unit 112 test station 114 First transceiver module 116 communication module 11 8 communication controller 120 DUT 122 test module 124 logic BIST 126 test controller 132 diagnostic unit 140 integrated circuit component detection system 1131 carrier 1 50 integrated circuit component detection system 113 " Carrier 1000 Integrated Circuit Component Detection System 1011 Test Head 1013 Carrier 1015 Physical Layer Module 1017 Power Regulator 1019 Clock Generator 1021 Core Circuit

1023記憶體BIST1023 memory BIST

1025 類比 BIST 1030第二收發模組 1034檢測單元 16- 2010389561025 analog BIST 1030 second transceiver module 1034 detection unit 16- 201038956

1100積體電路元件檢測系統1110測試器 1120 DUT 1200積體電路元件檢測系統1100 integrated circuit component detection system 1110 tester 1120 DUT 1200 integrated circuit component detection system

1220 測試器 1220 DUT 1300積體電路元件檢測系統1310測試器1220 Tester 1220 DUT 1300 Integrated Circuit Component Detection System 1310 Tester

1320 DUT -17-1320 DUT -17-

Claims (1)

201038956 七、申請專利範圍: 1. 一種積體電路元件檢測系統,包含: 一測試頭,包含一第一收發模組; 一測試台,包含一檢測單元,該檢測單元輕接於該測 試頭以進行測試;以及 一積體電路元件,包含一通訊模組、複數個被測試之 核心電路和至少一個測試模組;201038956 VII. Patent application scope: 1. An integrated circuit component detection system, comprising: a test head comprising a first transceiver module; a test station comprising a detection unit, the detection unit being lightly connected to the test head Testing; and an integrated circuit component comprising a communication module, a plurality of tested core circuits, and at least one test module; 其中該通訊模組包含一第二收發模組以設定與該第一 收發模組間以進行資料交換; 其中各核心電路係分別製作於不同晶粒上; 其中該至少一測試模組具有對應其數量且耦接至該等 核心電路及該通訊模組之自我測試電路以進行該等核心 電路之自我測試; 其中該通訊模組、該等核心電路和該至少一個測試模 •組係封裝於單一封裝内。 2·根據請求項i之積體電路騎檢測系統,其中該通訊模紅 和該至少-個測試模組係分別製作於兩個晶粒,且該兩晶 粒不同於該等核心電路之晶粒。 3.根據請求項1之積體電路元侔蛉 午檢測系統,其中該等核心電 路和該至少一測試模組之數量 双重相同,且各核心電路係連同 其對應之測試模組製作於不同曰 ,, u日日粒,而該通訊模組係另製 作於一不同之晶粒。 4·根據請求項1之積體電路元 和〜4 件檢剩系統’其中該通訊模組 和忒至少一個測試模組係製 作於同一晶粒,且該晶粒不同 -18- 201038956 於該等核心電路之晶粒。 5. 根據請求項1之積體電路元件檢測系統,其中該通訊模組 另包含一耦接於該第二收發模組之時脈產生器。 6. 根據請求項5之積體電路元件檢測系統,其中該通訊模組 另包含一耦接於該第二收發模組及該時脈產生器之通訊 控制器。The communication module includes a second transceiver module for setting data exchange with the first transceiver module; wherein each core circuit is separately fabricated on different dies; wherein the at least one test module has a corresponding Quantitatively coupled to the core circuit and the self-test circuit of the communication module for self-testing of the core circuits; wherein the communication module, the core circuits, and the at least one test module are packaged in a single Inside the package. 2. The integrated circuit riding detection system according to claim i, wherein the communication mode red and the at least one test module are respectively fabricated on two crystal grains, and the two crystal grains are different from the crystal grains of the core circuits . 3. The integrated circuit element noon detection system according to claim 1, wherein the number of the core circuits and the at least one test module are the same, and each core circuit is manufactured differently from its corresponding test module. , u, the day of the grain, and the communication module is made in a different grain. 4. According to the integrated circuit element of claim 1 and the ~4 pieces of the remaining system, wherein the communication module and the at least one test module are fabricated in the same die, and the die is different -18-201038956 The die of the core circuit. 5. The integrated circuit component detection system of claim 1, wherein the communication module further comprises a clock generator coupled to the second transceiver module. 6. The integrated circuit component detection system of claim 5, wherein the communication module further comprises a communication controller coupled to the second transceiver module and the clock generator. 7. 根據請求項5之積體電路元件檢測系統,其中該時脈產生 器耦接於該測試模組。 8·根據請求項丨之積體電路元件檢測系統,其另包含一提供 該積體電路元件之電力穩壓器,該第二收發模組接收該第 一收發模組所傳輸之訊號以驅動該電力穩壓器產生電力。 9. 根據請求項8之積體電路元件檢測系統,其中該積體電路 元件係位於包含該電力穩壓器之—承载器,且自 獲得其操作電力。 窃 10. 根據請求項i之積體電路元件檢測系統,其中該測試頭另 包含一耦接於該第一收發模組之物理層模組。 U.根據請求項i之積體電路元件檢測系統,其中該測試台另 包含一叙接於該檢測單元之診斷單元。 12·根據請求項i之積體電路元件檢測系統,其中該自我測試 電路係一記憶體自我測試電路。 請求項i之積體電路㈣檢測系統,其中該自我測試 電路係一邏輯自我測試電路。 14’根據請求項i之積體電路元件檢測系統,其中該自我測試 電路係一邏輯類比測試電路。 •19- 201038956 15·根據請求項1之積體電路元件檢測系統, 々 共中該第一收發 模組係以無線方式和該第二收發模組進行資料交換 16.根據請求項1之積體電路元件檢測系統, 丹甲該第一收發 模組係以有線方式和該第二收發模組進行資料交換 17·根據請求項1之積體電路元件檢測系統,其中該第—收發 模組係以光學連線方式和該第二收發模組進行資料交換。7. The integrated circuit component detection system of claim 5, wherein the clock generator is coupled to the test module. The integrated circuit component detecting system according to the request item further includes a power regulator for providing the integrated circuit component, wherein the second transceiver module receives the signal transmitted by the first transceiver module to drive the The power regulator generates electricity. 9. The integrated circuit component detecting system of claim 8, wherein the integrated circuit component is located in a carrier including the power regulator, and self-obtaining its operating power. 10. The integrated circuit component detecting system according to claim i, wherein the test head further comprises a physical layer module coupled to the first transceiver module. U. The integrated circuit component detection system of claim i, wherein the test station further comprises a diagnostic unit coupled to the detection unit. 12. The integrated circuit component detection system of claim i, wherein the self test circuit is a memory self test circuit. The integrated circuit of claim i (4) is a detection system, wherein the self-test circuit is a logic self-test circuit. 14' The integrated circuit component detecting system according to claim i, wherein the self-test circuit is a logic analog test circuit. • 19- 201038956 15· According to the integrated circuit component detecting system of claim 1, the first transceiver module wirelessly exchanges data with the second transceiver module. 16. According to the integrated item of claim 1 The circuit component detecting system, the first transceiver module performs data exchange with the second transceiver module in a wired manner. 17. The integrated circuit component detecting system according to claim 1, wherein the first transceiver module is The optical connection mode and the second transceiver module exchange data. Ο -20-Ο -20-
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Cited By (4)

* Cited by examiner, † Cited by third party
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CN103852714A (en) * 2012-11-30 2014-06-11 联发科技股份有限公司 Integrated circuit, test equipment and RF testing system
US9525500B2 (en) 2011-06-13 2016-12-20 Mediatek Inc. Low-cost test/calibration system and calibrated device for low-cost test/calibration system
US10069578B2 (en) 2011-06-13 2018-09-04 Mediatek Inc. RF testing system with parallelized processing
US10320494B2 (en) 2011-06-13 2019-06-11 Mediatek Inc. RF testing system using integrated circuit

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TW514927B (en) * 2001-04-02 2002-12-21 Faraday Tech Corp Built-in programmable self-diagnosis method and circuit SRAM
TWI264551B (en) * 2005-05-04 2006-10-21 Univ Tsinghua System for probing integrated circuit devices
US20060282735A1 (en) * 2005-05-24 2006-12-14 Texas Instruments Incorporated Fasttest module
US7477875B2 (en) * 2005-07-26 2009-01-13 Texas Instruments Incorporated Built in loop back self test in design or on test board for transceivers

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US9525500B2 (en) 2011-06-13 2016-12-20 Mediatek Inc. Low-cost test/calibration system and calibrated device for low-cost test/calibration system
US10069578B2 (en) 2011-06-13 2018-09-04 Mediatek Inc. RF testing system with parallelized processing
US10110325B2 (en) 2011-06-13 2018-10-23 Mediatek Inc. RF testing system
US10320494B2 (en) 2011-06-13 2019-06-11 Mediatek Inc. RF testing system using integrated circuit
CN103852714A (en) * 2012-11-30 2014-06-11 联发科技股份有限公司 Integrated circuit, test equipment and RF testing system
CN103852714B (en) * 2012-11-30 2016-11-23 联发科技股份有限公司 Integrated circuit, test equipment and radio frequency test system

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