CN101770967A - Test method, device and system of common substrate integrated circuit - Google Patents

Test method, device and system of common substrate integrated circuit Download PDF

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Publication number
CN101770967A
CN101770967A CN200910044937A CN200910044937A CN101770967A CN 101770967 A CN101770967 A CN 101770967A CN 200910044937 A CN200910044937 A CN 200910044937A CN 200910044937 A CN200910044937 A CN 200910044937A CN 101770967 A CN101770967 A CN 101770967A
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China
Prior art keywords
unit under
test
under test
result
common base
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CN200910044937A
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Chinese (zh)
Inventor
林正浩
耿红喜
任浩琪
张冰淳
郑长春
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上海芯豪微电子有限公司
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Priority to CN200910044937A priority Critical patent/CN101770967A/en
Publication of CN101770967A publication Critical patent/CN101770967A/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2886Features relating to contacting the IC under test, e.g. probe heads; chucks
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides a test method, a device and a system of a common substrate integrated circuit, a plurality of tested units and a plurality of devices for comparing running results of the tested units are arranged on a common substrate, the different tested units implement the same input incentive and respectively produce the running results, the running results are compared by the devices for comparing the corresponding running results on the common substrate, a comparison feature is produced, and the failed tested units are detected according to the feature. The invention can reduce the test cost, shorten the mass production time for scale formation and reduce the missing test rate.

Description

A kind of common substrate integrated circuit method of testing, device and system

Technical field

The invention belongs to integrated circuit fields, be specially a kind of IC testing method, device and system.

Background technology

Typical semiconductor fabrication process is to approach and a plurality of identical rectangle crystal grain (die) of the last making of homogeneous semiconductor material wafer (wafer) at one.Intercrystalline is isolated by 60~80 microns Cutting Road (scribe line) by width.Often place mask (mask) on the Cutting Road and aim at wafer acceptance test (wafer acceptance test, testing element WAT) of monitoring quality in symbol (alignment mark) and the production process.

In manufacturing process, zone of mask aligner single exposure is called patterned area (stepper field), and each patterned area comprises one or more crystal grain.After all production process were finished, each crystal grain on the wafer all will be by functional test.Wafer sort platform (wafer prober) uses the weld pad (pad) of pin measuring card (probe card) the contact tested crystal grain of wanting, the test and excitation that test program is generated is delivered in the tested crystal grain, tested crystal grain response input produces corresponding output, be delivered in the testboard (tester) through pin measuring card and compare with expected results, if both equate/coupling, think that then tested crystal particle function is correct.Once test a crystal grain.

After a tested crystal grain passes through all test programs, its position will go on record, for follow-up encapsulation is prepared.The tested crystal grain by test will not use ink to carry out mark or positional information will be deposited in a file that is called wafer map (wafermap).After all tests are finished, will be along the Cutting Road cutting crystal wafer, the correct crystal grain of separated function is with packed, and the crystal grain of inefficacy will be dropped.Chip after the encapsulation will encapsulate the back test, and the chip that function is correct will be consigned to the client.

Fig. 1 is general wafer sort (wafer test) schematic diagram, wafer to be measured (101) is placed on the wafer sort platform (102), the test and excitation that tester (103) is produced test vector generator (104) passes to pin measuring card (107) on the measuring head (106) by input cable (105), pin measuring card (107) is input to data in the crystal grain to be measured (108), and from crystal grain to be measured (108), read operation result, pass to tester (103) by measuring head (106) and output cable (111), tester (103) is sent into this result in the comparator (109), compares with expected results (110) and judges whether this crystal grain to be measured (107) lost efficacy.

Along with the development of integrated circuit production technology, the size of wafer rises to 12 inches from 1 inch, makes the degree of parallelism of crystal grain production constantly improve, and can hold nearly ten thousand crystal grain on each wafer.But because the restriction of testboard passage (channel) number makes wafer sort be still serial and carry out that test each crystal grain one by one, the number of crystal grain is directly proportional on wafer sort time and the wafer, the testing time becomes extremely long, and it is very high that testing cost becomes.On testboard, only probe (probe) time of moving to another crystal grain after testing a crystal grain just is 100ms~250ms, can't be used for test during this period of time, is wasted.This has further increased the testing time, has improved testing cost.At present, in integrated circuit was produced, test, packaging cost had accounted for 25%~30% of whole production cost, even have reached 50%.

Because testboard has limited test frequency to the wiring delay of crystal grain, test can only be carried out under lower frequency in addition.

For addressing this problem, a kind of method is to use multiprobe (Multi-site) to realize concurrent testing.But this method is subjected to the restriction of the port number of testboard; The port number of each testboard is between 128~1024, and the weld pad of a crystal grain is hundreds and thousands of, makes that the degree of parallelism rising space of test is little, generally two to four the tunnel, and passage costs an arm and a leg, and increases passage and will significantly increase the price of testboard, has improved testing cost.

Also have a kind of method to realize chip self-test on the wafer exactly, below three patents relate to this method, but different with this patent.

The patent No. is that the Chinese patent of 200510008164.X " can be implemented wafer and implementation method thereof aging and testing electrical property " and propose a kind of method that can wear out simultaneously with testing electrical property on wafer.This method is provided with aging pattern generative circuit (aging pattern generation circuit) on wafer, this circuit can produce no function meaning, constantly the excitation of counter-rotating is delivered in the crystal grain and worn out simultaneously and testing electrical property, and it does not need to output test result to testboard.

The patent No. be 200410046002.0 Chinese patent " semiconductor crystal wafer and manufacture method " with test circuit propose a kind of can be on wafer accurate measured chip voltage method.This method is provided with test circuit on Cutting Road, make the impedance of output impedance much smaller than probe, and its input impedance is convenient to the reference voltage that probe can be measured each electronic pads of crystal grain accurately much larger than the output impedance of crystal grain.

The patent No. is that 86105604 Chinese patent " circuit structure that is used for testing integrated circuit components " has proposed a kind of test circuit structure based on on-chip circuit element.The circuit-under-test element is formed on the common substrate as integrated circuit, and can be through on-chip public power supply and incoming line operation.The test circuit of this circuit structure and switch element are formed on the same substrate as integrated circuit, switch element can and be inserted in the line that connects test circuit and circuit element by test circuit control, and its desired value will be transferred to and be used on the substrate making comparisons with circuit-under-test.Test circuit is equipped with the output circuit that transmits test result, and when the test circuit element, self-test utilizes the relatively actual and desired value of the central location of test circuit to come discriminating element whether qualified, and testing of serial successively.

Crystal grain will encapsulate the back test to chip after being packaged into chip.Its test process as shown in Figure 2, tester (201) is connected to to-be-measured integrated circuit device board (Device Under Test board) (204) on the measuring head (203) by input cable (202), by to-be-measured integrated circuit device board (204) test and excitation that test vector generator (205) is produced is input in the chip to be measured (206).Chip to be measured (206) responsing excitation, produce operation result, and by to-be-measured integrated circuit device board (204), measuring head (203) and output cable (209) transmit back in the comparator (207) in the tester (201), compare with the expected results (208) in the tester (201), whether function is correct to judge this chip.Can test one by one chip by testboard.

In sum, existing integrated circuits method of testing, device and system because the restriction of test channel number can only be tested one or several unit under tests at every turn, can't accomplish extensive while of unit under test/relatively parallel.The test channel number is limited to be the bottleneck that the restriction testing efficiency improves.

The present invention realizes by the following technical solutions:

IC testing method, device and system on a kind of common base that the present invention proposes, on common base, include a plurality of unit under tests and a plurality of unit under test operation result comparison means, different unit under tests are carried out same input stimulus, produce operation result respectively.All operation results by the corresponding operation result comparison means on the common base and expected results simultaneously/parallel comparison or operation result between by the corresponding operation result comparison means on the common base simultaneously/parallel mutually relatively, comparative result according to the operation result comparison means, based on simple judgement, detect the inefficacy unit under test.The present invention by on common base simultaneously/parallel method relatively, do not increasing under the prerequisite of test channel substantially, realized thousands of unit under test time/concurrent testings.

IC testing method on a kind of common base of the present invention comprises:

(a) (device under test is DUT) in down while/parallel running of same input stimulus (Input Stimulation), respectively simultaneously/parallel generation operation result for the unit under test that a plurality of functions on the common base are identical;

(b) if there is expected results to exist,

(i) to above-mentioned a plurality of operation results respectively with expected results simultaneously/the parallel comparison that whether equates/mate;

(ii) draw test feature, promptly comparative result equated/those unit under tests of coupling are labeled as effective unit, with comparative result unequal/unmatched those unit under tests are labeled as doubtful disabling unit; If necessary, can carry out conventionally test separately to doubtful disabling unit, to determine whether real inefficacy;

(c) if there is not expected results to exist,

(i) to above-mentioned a plurality of operation results mutually simultaneously/parallelly carry out whether equating/comparison of coupling;

(ii) draw test feature, promptly comparative result equated/those unit under tests of coupling are labeled as effective unit, with comparative result unequal/unmatched those unit under tests are labeled as doubtful disabling unit; If necessary, can carry out conventionally test separately to doubtful disabling unit, to determine whether real inefficacy;

(d) separate effective unit and disabling unit according to test feature.

Arrangement for testing integrated circuit on a kind of common base of the present invention comprises:

(a) the identical unit under test of a plurality of functions on the described common base;

(b) a plurality of operation result comparison means on the described common base;

(c) internet on the described common base;

(d) the test feature let-off gear(stand) on the described common base.

Common base of the present invention can be a single integrated circuit, and when described common base was single integrated circuit, unit under test was the functional module on this integrated circuit; Described common base also can be a wafer, and when described common base was wafer, unit under test was crystal grain on the wafer; Described common base can also be a circuit board, and when described common base was circuit board, unit under test was the chip on the circuit board.

Operation result comparison means of the present invention, whether these operation results of sampling, conversion and comparison that are used for each unit under test is carried out the operation result after the same excitation equate/coupling; Described operation result can be the signal value on the external output port of unit under test, also can be the signal value of unit under test inside; Described operation result sampling point can be the external output port of unit under test, also can be the sampling point of unit under test inside; The sample of described sampling can be the signal of arbitrary form, includes but not limited to digital signal, analog signal; Described conversion includes but not limited to simulate as signals such as electric current, voltage, impedances to the conversion to analog signal of the conversion of digital signal or digital signal; Described comparison can be each unit under test operation result respectively and between the expected results that imports into the time/relatively parallel, also can be between each unit under test operation result the time/relatively parallel.

Operation result comparison means of the present invention can be the device that includes only sampling and comparing function, also can be the device that comprises sampling, conversion and comparing function.

In operation result comparison means of the present invention, can be earlier to the operation result sampling, the sample that sampling is obtained compares again; Also can compare continuously operation result earlier, more continuous comparative result be taken a sample, as actual comparative result.

Operation result comparison means of the present invention can also comprise the inefficacy decision-making function.When expected results existed, concrete decision method was: if the operation result of unit under test all equate with expected results/mate, can judge that then this unit under test is effective unit; If the operation result of unit under test and expected results be unequal/do not match, can judge that then this unit under test is doubtful disabling unit.When expected results does not exist, concrete decision method is: the operation result of each unit under test and adjacent odd number corresponding operation result individual or a plurality of unit under tests compares, if all equate/coupling more fully, can judge that then this unit under test is effective unit, otherwise can judge that this unit under test is doubtful disabling unit.Can also further screen according to simple rule for doubtful disabling unit, this examination can realize on common base, also can realize outside common base.Because the number of effective unit therefore for doubtful disabling unit, can carry out the conventionally test excitation far more than the number of disabling unit separately as required in the unit under test, determines whether to be true disabling unit.

Operation result comparison means of the present invention and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.When all or part of operation result comparison means in substrate outside the unit under test time, described all or part of operation result comparison means promptly is positioned at the outer vacant position of unit under test in the substrate.

When described common base is that single integrated circuit, unit under test are during for the functional module on this integrated circuit, operation result comparison means in the common substrate integrated circuit testing apparatus of the present invention can be manufactured on the semiconductor technology of producing this wafer on the same integrated circuit simultaneously, it includes but not limited in tested functional module at the particular location on the same integrated circuit, part in tested functional module part on integrated circuit outside the tested functional module, all on integrated circuit outside the tested functional module.When all or part of operation result comparison means on integrated circuit outside the tested functional module time, described all or part of operation result comparison means can be positioned at the vacant position between tested functional module.

When described common base is that wafer, unit under test are on the wafer during crystal grain, operation result comparison means in the common substrate integrated circuit testing apparatus of the present invention can be manufactured on the semiconductor technology of producing this wafer on the same wafer simultaneously, its particular location on same wafer includes but not limited at tested intragranular, part in tested intragranular part on wafer outside the tested crystal grain, all on wafer outside the tested crystal grain.When all or part of operation result comparison means on wafer outside the tested crystal grain time, described all or part of operation result comparison means can be positioned at tested intercrystalline Cutting Road or other vacant positions.

When described common base is that circuit board, unit under test are when being chip on the circuit board, operation result comparison means in the common substrate integrated circuit testing apparatus of the present invention can be with device or/and the form of chip be present on the same circuit board, and described all or part of operation result comparison means can be positioned at the outer vacant position of chip under test on the circuit board.

Internet of the present invention comprises the power supply transmission network, is used for the power supply supply is transferred to each unit under test; The input stimulus transmission network is used for shared excitation is transferred to each unit under test, and described shared excitation can produce outside common base, also can produce outside the unit under test on common base, also can produce in unit under test; If there is expected results to exist, then expected results also is transferred to corresponding operation result comparison means by described input stimulus transmission network; The operation result transmission network is used for the operation result after the transmission operation excitation is transferred to corresponding operation result comparison means.

Power supply transmission network of the present invention has the switched-mode power supply ability, can be configurable, also can fix; When described power supply transmission network when being configurable, can realize switched-mode power supply by the break-make of switching device, the unit under test in the selection areas different on the common base is powered respectively; Described input stimulus transmission network can be transferred to some or all unit under tests from the unit under test at probe place with input stimulus and expected results;

Input stimulus transmission network of the present invention can be configurable, also can fix; Can be to disconnect, also can be on-disconnectable; Can be that band drives, also can be not to be with driving.Described input stimulus transmission network and operation result transmission network can comprise signal delay device, also can not comprise signal delay device; Described signal delay device is used for latch signal when transmission excitation or expected results, includes but not limited to register and latch.

When the connection of input stimulus transmission network of the present invention or operation result transmission network is configurable, can be configured the break-make that connects in this internet by the mode of external equipment with parallel configuration or series arrangement.During signals such as transmission input stimulus or expected results, described connection is configured to conducting; When comparing as output, described connection is configured to disconnect.By the connection between two identical input ports of unit under test is configured, according to the residing position of test and excitation generator, conducting is away from the connection of the direction of the residing position of test and excitation generator and disconnect rightabout connection, can constitute the communication network of same input stimulus between each unit under test, make each unit under test obtain identical excitation.Have between identical operation result output port and corresponding comparison means to be connected, the output of operation result output port identical between different unit under tests can be compared.

Input stimulus transmission network of the present invention can have function switching signal, includes but not limited to that digital signal is to the conversion to digital signal of the conversion of analog signal or analog signal.

Internet of the present invention and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.

When described common base is that single integrated circuit, unit under test are when being functional module on the integrated circuit, tested functional module in the common substrate integrated circuit testing apparatus of the present invention interconnected comprises the connection that the band that can disconnect between the identical input port of each tested functional module drives, and also comprises being connected of operation result output port and corresponding comparison means.The connection that band between the identical input port of the tested functional module of difference is driven is configured, according to the residing position of test and excitation generator, conducting is left the connection that the band of the direction of the residing position of test and excitation generator drives and is disconnected the connection that rightabout band drives, can constitute the communication network of same input stimulus between each tested functional module, make each tested functional module obtain identical excitation.

When described common base is that wafer, unit under test are on the wafer during crystal grain, tested crystal grain in the common substrate integrated circuit testing apparatus of the present invention interconnected comprises the connection that the band that can disconnect between the identical input port of each tested crystal grain drives, and also comprises being connected of operation result output port and corresponding comparison means.The connection that band between the identical input port of the tested crystal grain of difference is driven is configured; according to the residing position of test and excitation generator; conducting is left the connection that the band of the direction of the residing position of test and excitation generator drives and is disconnected the connection that rightabout band drives; can constitute the communication network of the same input stimulus of each tested intercrystalline, make each tested crystal grain obtain identical excitation.

When described common base is that circuit board, unit under test are when being chip on the circuit board, chip under test in the common substrate integrated circuit testing apparatus of the present invention interconnected comprises the connection that the band that can disconnect between the identical input port of each chip under test drives, and also comprises being connected of operation result output port and corresponding comparison means.The connection that band between the identical input port of different chip under test is driven is configured, according to the residing position of test and excitation generator, conducting is left the connection that the band of the direction of the residing position of test and excitation generator drives and is disconnected the connection that rightabout band drives, can constitute the communication network of same input stimulus between each chip under test, make each chip under test obtain identical excitation.

Test feature let-off gear(stand) of the present invention can be configurable, also can fix.When described test feature let-off gear(stand) when being configurable, comprise deriving the path and being connected switch, derive the individual or a plurality of operation result comparison means of path connection odd number for every.Connect switch according to disposing conducting, the difference that connects switch ends can be derived the path and be connected to odd number bar test feature derivation chain, connect switch according to disposing to disconnect, the difference derivation path that connects switch ends is separately independently test feature derivation chain.When test feature let-off gear(stand) of the present invention constitutes odd number bar or a plurality of test feature and derives chain with fixing line, can save the connection switch.

The test feature derivation mode of test feature let-off gear(stand) of the present invention includes but not limited to the serial derivation, derive as deriving the chain serial shift by odd number bar test feature, or parallel the derivation, obtain operation result as multiprobe is parallel from a plurality of test feature derivation chains, or derive parallel mixing of serial.Derive chain if the test feature let-off gear(stand) only comprises odd number bar test feature, can obtain all operation results successively with the mode of serial shift.If comprising a plurality of test feature, the test feature let-off gear(stand) derives chain, can derive chain from a plurality of test feature concurrently with multiprobe and obtain test feature simultaneously successively, also can derive chain from a plurality of test feature in turn and obtain test feature successively with odd number cover or plural number cover probe.

The test feature that test feature let-off gear(stand) of the present invention is derived can be the judgement conclusion whether each unit under test lost efficacy, and also can be the comparative feature of unit under test operation result comparison means output.

Test feature let-off gear(stand) of the present invention and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.

Input stimulus transmission network of the present invention, operation result transmission network and test feature derive chain and can set up simultaneously by the mode of serial input configuration information, also can set up step by step by the mode of repeatedly importing configuration information.Described input stimulus transmission network can be transferred to all unit under tests from the unit under test at probe place with input stimulus and expected results.Described test feature derives the unit under test that chain can export to the test feature of all unit under tests the probe place.It is higher than the designed reliability of unit under test that internet of the present invention and test feature derive the design of chain, and possesses self-checking function, can after foundation is finished, carry out a pretest earlier, derive the correctness of chain itself to guarantee described input stimulus transmission network, operation result transmission network and test feature.If not by pretest, then can rebulid input stimulus transmission network, operation result transmission network and test feature derivation chain from other unit under test by traveling probe, and repeat described from detecting.The described detection certainly can be carried out as following embodiment, and this embodiment implements under the prerequisite of technical solution of the present invention, but the present invention is not limited by this embodiment.Under self-testing mode, the excitation of by the input stimulus transmission network self-test being used earlier is transferred to each unit under test, and the excitation serial of above-mentioned self-test being used by the test feature let-off gear(stand) is derived again.

In the common substrate integrated circuit testing apparatus of the present invention, can be to the judgement of taking a sample of the odd number of odd number or a plurality of unit under tests or a plurality of operation result signals, the variation of guaranteeing this or these operation result signal is correct, avoiding because of some mistake, as electric power disconnection cause unit under test can't work but operation result all to show effective erroneous judgement disconnected.Described odd number or a plurality of operation result signals can be the one or more of numeral output, also can be one or more ports of simulation output.Described multidigit or a plurality of port can be taken from different unit under tests.Described sampling is judged, deliver to external equipment after can taking a sample to corresponding odd number or a plurality of operation result signals and judge, the judgement after also can using logical device/chip on the common base that corresponding odd number or a plurality of operation result signals are taken a sample.Described logical device/chip includes but not limited to counter/counter chip.Described determination methods includes but not limited to check whether the signal change frequency of counter records is consistent with expection.

Can be that example illustrates above-mentioned sampling determination methods with the microprocessor chip, this embodiment implements under the prerequisite of technical solution of the present invention, but the present invention is not limited by this embodiment.Get the judgement of taking a sample of a certain position signal in this microprocessor chip data-out bus.The corresponding counts utensil has memory function, the numerical value that the energy stored record is got off.This counter is initially zero, behind the test vector that brings into operation, in the logical value of each this signal of internal clocking cycle detection of this microprocessor chip, whenever detects a logical one, and then the corresponding counts device is from increasing 1.After all the test vector operation finishes,, represent that then this test is effectively, can determine whether unit under test is effective according to corresponding test feature if the numerical value of corresponding counts device stored is consistent with expected value.If the numerical value and the expected value of corresponding counts device stored are inconsistent, represent that then this test is invalid, or unit under test lost efficacy.

In the common substrate integrated circuit testing apparatus of the present invention, when described common base is that wafer, unit under test are on the wafer during crystal grain, it aims at corner pad (corner pad) position that symbol can move on to crystal grain.Described internet, operation result comparison means and test feature let-off gear(stand) can be placed on intragranular, also can be placed in the Cutting Road, and (wafer acceptance test, test structure WAT) coexist with being used for wafer acceptance test.The method of described coexistence can be to walk around the WAT test structure or share the WAT test structure in some position, as uses the input that the weld pad in the WAT test structure is used to encourage.

The testing cushion (test pad) that device of the present invention additionally needs can be placed on intragranular, also can be placed in the Cutting Road, also can be placed on the untapped corner of crystal grain pad position, can also be placed on the untapped vacant pad of crystal grain (no connection pad) position; The line that is used to constitute internet or test feature and derives chain can be placed in the Cutting Road, also can be placed on intragranular or pass crystal grain.Described device and the line that is placed in the Cutting Road can be excised when crystal grain cuts automatically, can not influence the function of crystal grain own; The described testing cushion that is placed on corner pad and vacant pad position can not influence the function of crystal grain own yet.

In addition, can also in Cutting Road, make electric capacity and be used to imitate the load that tested crystal grain output will drive, make test truer.

Part or all of domain (layout) in internet of the present invention, operation result comparison means and the test feature let-off gear(stand) can use computer automatic placement and routing software (place and route tool) to generate automatically.

The electric current that provides because of existing testing equipment is big inadequately, and the common substrate integrated circuit test macro that uses existing testing equipment to build is difficult to finish large-scale common substrate integrated circuit test with high clock frequency.A kind of solution is that common substrate integrated circuit is repeatedly tested.Described repeatedly test can be carried out the complete long test program test of a large amount of unit under tests earlier with low speed, finish functional test, rezones with the short test program test of the critical path of carrying out a small amount of unit under test at a high speed, the speed of test unit under test.Another kind of solution is to use integrated circuit test system on the following common base.

Integrated circuit test system on a kind of common base of the present invention, its feature comprises:

(a) common base and on identical unit under test, a plurality of operation result comparison means and the odd number of a plurality of functions or a plurality of test feature let-off gear(stand)s;

(b) can provide big electric current, common base top or all unit under tests are powered simultaneously, and guarantee that some or all unit under tests can be with the work of nominal operation frequency;

(c) can deliver to some or all unit under tests with encouraging simultaneously/walking abreast;

(d) above-mentioned some or all unit under test can be simultaneously/parallelly carry out the described comparison of claim 1, and produce test feature;

(e) test feature can be derived.

The essential distinction of a kind of common substrate integrated circuit method of testing, device and system and existing methods, devices and systems that the present invention proposes is:

1, adopt the technical scheme of the present invention can be, and existing methods, devices and systems all can only once be sent to a unit under test with shared excitation and/or expected results by the internet on the common base with shared excitation and/or expected results is disposable is sent to the unit under test of all in the selection area on the common base;

2, adopt technical scheme of the present invention can to all unit under tests in the selection area on the common base simultaneously/parallel the test, and existing methods, devices and systems all can only be tested successively in turn to all unit under tests;

When 3, the comparison in the technical scheme of the present invention can be the operation result of all unit under tests and expected results/relatively parallel, and existing methods, devices and systems all to be operation result and expected resultss with unit under test compare respectively separately;

4, in the technical scheme of the present invention more also can be unknown whether effectively between unit under test between the operation result time/relatively parallel, and existing methods, devices and systems all are with the operation result of unit under test and known reference point relatively, and known reference point comprises the value that is stored in the tester or the operation result of known effective unit.

The technology that aforementioned 200510008164.X patent is mentioned just wears out and testing electrical property to crystal grain, does not relate to functional test, and is different with this patent.

Aforementioned 200410046002.0 patents are provided with test circuit on line of cut, purpose only is to be convenient to the more accurate reference voltage of measuring crystal grain inside of probe, does not relate to functional test, and is different with this patent.

Though aforementioned 86105604 patents have realized test circuit structure in common substrate, but still be only to test a unit under test at every turn, and need expected results, be not parallel compare test under the situation of unknown expected results, different with this patent.

Beneficial effect:

The direction of making great efforts in the integrated circuit testing field mainly is aspect following three at present:

1, reduces testing cost (Test Cost);

2, shorten formation scale time to volume (Time to Market);

3, reduce false pass rate (Defective Parts Per Million);

The present invention adopts the method for a plurality of tested integrated circuit concurrent testings, once move input stimulus and can test the individual or a plurality of tested integrated circuits of odd number, N crystal grain of method test of once testing single tested integrated circuit and test one by one with respect to tradition needs N* (M+L) testing time, method of testing of the present invention only needs the M+L+N*R testing time, and (wherein M is mobile pin measuring card or moves the tested time that encapsulates the back integrated circuit, L is for carrying out the time of test and excitation, R is the time of output test feature, R is much smaller than M+L), therefore the present invention can become the order of magnitude to reduce the integrated circuit testing time, reduced testing cost, also shortened product and formed the scale time to volume; The present invention can suitably increase the length of test and excitation because significantly reduce the input stimulus number of run, improves test coverage, effectively reduces false pass rate.The present invention does not have extra demand to the testboard port number, helps to reduce testing cost; For wafer sort, when comparison means is integrated on the wafer, can avoid the delay of high-frequency signal through cable transmission, therefore can carry out the test of higher frequency, also can carry out high-end test with the testboard of low side.

Description of drawings

Though the modification that this invention can be in a variety of forms and replace and expand has also been listed some concrete enforcement legends and has been described in detail in the specification.Should be understood that inventor's starting point is not that this invention is limited to the specific embodiment of being set forth, antithesis, inventor's starting point is to protect all based on the improvement of carrying out in the spirit or scope by the definition of this rights statement, equivalence conversion and modification.

Fig. 1, Fig. 2 is the background introduction of wafer sort and chip testing; Fig. 3 is implementing procedure figure of the present invention; Fig. 4~Figure 11 is an implementation detail of the present invention; Figure 12~Figure 15, Figure 17, the embodiment of Figure 18 for using existing testboard to test; Figure 16, the embodiment that Figure 19 tests for the testboard of compatible right 12 described requirements; Figure 20 is the embodiment of the present invention in chip; Figure 21 is applied in the embodiment that tests after the Chip Packaging for the present invention.

Fig. 1 is the wafer sort schematic diagram.

Fig. 2 is the chip testing schematic diagram.

Fig. 3 carries out the flow chart of common substrate integrated circuit test for common substrate integrated circuit testing apparatus of the present invention.

The structural representation that Fig. 4 compares with expected results for crystal grain output.

The structural representation that Fig. 5 compares mutually for crystal grain output.

Fig. 6 is the schematic diagram of comparator outside intragranular and crystal grain the time.

Fig. 7 is that the crystal grain failure conditions is judged schematic diagram in the test process.

Fig. 8 is the embodiment of adjacent unit under test position relation among the present invention.

Fig. 9 is a relatively schematic diagram of analog signal for operation result.

Figure 10 is the embodiment that the present invention is directed to supply power mode.

Figure 11 the present invention is directed to embodiment and the pin of aiming at the symbol position to survey the possible position distribution map of pad on wafer.

Figure 12 is photoetching intra-zone test and excitation transmission structure figure and test feature derived type structure figure on the wafer.

Figure 13 the present invention is directed to the crystal grain embodiment of more configurable internet mutually.

Figure 14 is the embodiment that the present invention is directed to collocation method.

Figure 15 is that wafer sort input path and test feature derive the path schematic diagram.

Figure 16 is a kind of wafer schematic diagram with big current interface.

Figure 17 is the wafer sort schematic diagram of radio frequency chip crystal grain.

Figure 18 is a self-test wafer schematic diagram.

Figure 19 is a kind of novel wafer sort system diagram.

Figure 20 is multioperation unit/multi core chip close beta structure chart.

Figure 21 is encapsulation back chip testing schematic diagram.

Embodiment

Technical thought of the present invention is that the identical a plurality of tested integrated circuit/crystal grain/functional block of 26S Proteasome Structure and Function is carried out same input stimulus, produce operation result separately, operation result by simultaneously/parallel relatively or with expected results carrying out simultaneously mutually/parallel the comparison to detect inefficacy integrated circuit/crystal grain/functional block.

See also Fig. 3, Fig. 3 carries out the flow chart of common substrate integrated circuit test for common substrate integrated circuit testing apparatus of the present invention.Among Fig. 3 (a), the operation result comparison means does not comprise the inefficacy decision-making function.At first enter step 1 (302), input stimulus enters each unit under test of step 2 (303) parallel running again.Enter step 3 (305) afterwards the operation result of each unit under test is taken a sample, and walk abreast relatively with expected results, the record comparative result, this sampling rate number of times depends on the requirement of measuring accuracy.After the operation result sampling rate of whole test vectors finished, enter step 4 (306), carry out the result and judge, produce test feature.Enter step 5 (307) at last, derive test feature.Among Fig. 3 (b), the operation result comparison means comprises the inefficacy decision-making function.At first enter step 1 (302), input stimulus enters each unit under test of step 2 (303) parallel running again.Enter step 3 (304) afterwards the operation result of each unit under test taken a sample, the sampling rate of carrying out the operation result between unit under test, and record comparative feature.This sampling rate number of times depends on the requirement of measuring accuracy.After the operation result sampling rate of whole test vectors finished, enter step 4 (306), result produces test feature according to sampling rate.Enter step (307) at last, derive test feature.Test feature is doubtful disabling unit or disabling unit result of determination.This result of determination can be the information that disabling unit coordinate information or other can the locate failure unit.After finishing the common substrate integrated circuit test, can test again doubtful disabling unit as required, can think simply according to demand that also doubtful disabling unit is real the inefficacy.Disabling unit can come out by the mode mark of physics.

The structural representation that Fig. 4 compares with expected results for crystal grain output.Bidirectional switch (403), bidirectional switch (404), bidirectional switch (443), bidirectional switch (444) are configured to transmit to the right, and the excitation (401) that excitation transmission network (402) imports the left side into is imported crystal grain (409), crystal grain (410), crystal grain (411) respectively into by input weld pad (406), input weld pad (407), input weld pad (408).Expected results (412) imports into from the left side, import comparator (414), comparator (415), comparator (416) into by expected results transmission network (413), the following operation result of crystal grain (409), crystal grain (410), crystal grain (411) imports comparator (414), comparator (415), comparator (416) respectively into by exporting weld pad (425), output weld pad (426), output weld pad (427) separately.The comparative feature of comparator (414), comparator (415), comparator (416) is stored in respectively in feature register (417), feature register (418), the feature register (419).The initial value of all feature register is provided with by external control signal is unified, or is produced by autoexcitation.When two groups of inputs of comparator unequal/when not matching, the feature register intrinsic value changes, and only change once, i.e. the output of adjacent crystal grain as long as once more unequal/do not match, just the relevant crystal grain of sign is doubtful inefficacy crystal grain.Feature register (417), feature register (418), feature register (419) can connect into shift register chain (420) with other feature register, are used to derive the test feature value.Excitation (401) can directly not be connected with internal module with metal wire by input weld pad (406), input weld pad (407), input weld pad (408), and operation result can directly will not exported derivation with metal wire by output weld pad (425), output weld pad (426), output weld pad (427) yet.Described comparator can have odd number or a plurality of input.

The structural representation that Fig. 5 compares mutually for crystal grain output.Bidirectional switch (503), bidirectional switch (504) are configured to transmit to the right, and the excitation (501) that excitation transmission network (502) imports the left side into is imported crystal grain (508), crystal grain (509), crystal grain (510) respectively into by input weld pad (505), input weld pad (506), input weld pad (507).The following operation result of crystal grain (509) sends comparator (514), comparator (515) to by output weld pad (512), and the following operation result of crystal grain (508) compares by the output that output weld pad (511) sends comparator (514) and crystal grain (509) to.The following operation result of crystal grain (510) compares by the output that output weld pad (513) sends comparator (515) and crystal grain (509) to.Comparator (514), the comparative feature of comparator (515) are stored in respectively in feature register (516), the feature register (517).The initial value of all feature register is provided with by external control signal is unified, or is produced by autoexcitation.When two groups of inputs of comparator unequal/when not matching, the feature register intrinsic value changes, and only change once, i.e. the output of adjacent crystal grain as long as once more unequal/do not match, just the relevant crystal grain of sign is doubtful inefficacy crystal grain.Feature register (516), feature register (517) can connect into shift register chain (518) with other feature register, are used to derive the test feature value.Excitation (501) can directly not be connected with internal module with metal wire by input weld pad (505), input weld pad (506), input weld pad (507), and output can directly will not exported derivation with metal wire by output weld pad (511), output weld pad (512), output weld pad (513) yet.Described comparator can have odd number or a plurality of input.

Fig. 6 (a) is the schematic diagram of comparator when intragranular; Transmission network (601) is input to the weld pad (603) of the operation result of expected results or adjacent crystal grain by input/output port (I/O pin) (602) in the current crystal grain, uses comparator (605) to compare with the corresponding operation result (604) of current crystal grain.In output port this moment (602), enable (607) of output driver (606) are closed, and enter drive (608) is opened.

Fig. 6 (b) is the schematic diagram of comparator outside crystal grain the time; The operation result of current crystal grain (611) compares by the operation result (615) that output driver (612) and its weld pad (613) output in the comparator (614) with expected results or adjacent crystal grain.

Fig. 7 is that the crystal grain failure conditions is judged schematic diagram in the test process, in this schematic diagram, operation result on each four limit of tested crystal grain respectively with adjacent tested crystal grain corresponding edge on operation result compare by the operation result comparison means, wherein, comparative feature is illustrated as white for the comparison means that equates/mate, and comparative feature is that unequal/unmatched comparison means is illustrated as black.In this embodiment, all judge that device that whether crystal grain lost efficacy can be on wafer, also can be outside wafer on the tester.As shown in the figure, the test case schematic diagram of Fig. 7 (a) during for no inefficacy crystal grain, the operation result of wherein tested crystal grain (701) on four limits compares by the operation result of line (as 707) with tested crystal grain (702,703,704,705) corresponding edge respectively, comparator (706) is illustrated as relatively equating/mating of the tested crystal grain of white expression (701) and tested crystal grain (704) corresponding edge, equating more fully among the figure on four limits/coupling, therefore can judge that tested crystal grain (701) is normal crystal grain.Test case schematic diagram when Fig. 7 (b) is a tested crystal grain partial failure, tested crystal grain (711) on four limits respectively with the operation result of tested crystal grain (712,713,714,715) corresponding edge relatively, wherein comparator (716) and comparator (717) are illustrated as black, represent respectively tested crystal grain (711) and tested crystal grain (712) and tested crystal grain (714) more unequal/do not match, line (718,719) is its corresponding line.And therefore relatively equating on tested crystal grain (711) and tested crystal grain (713, the 715) corresponding edge/coupling can judge that tested crystal grain (711) is partial failure.Test case schematic diagram when Fig. 7 (c) is a tested crystal grain complete failure, tested crystal grain (721) and tested crystal grain (722,723,724,725) on four limits corresponding operation result whole unequal/do not match, eight comparators (726,727,728,729,730,731,732,733) as shown in the figure all are black, and wherein line (734) is the line between unit under test (711) and the comparator (726).Therefore can judge that tested crystal grain (721) is inefficacy crystal grain.

Fig. 8 is the embodiment of adjacent unit under test position relation among the present invention, wherein A, B, C, D are four angles of unit under test, as shown in the figure, Fig. 8 (a) is common placement location schematic diagram, four unit under tests (801,802,803,804) are according to unifying towards placement, each unit under test output port compares by the output port on line and the adjacent unit under test corresponding edge, compares as the output port of unit under test (801) and the corresponding output end mouth of unit under test (802).The line of line among the figure (813) for comparing between unit under test (802) and unit under test (804) corresponding output end mouth.Fig. 8 (b) is rotation placement location schematic diagram, the placement location of each unit under test and the placement location of adjacent unit under test are rotation relationship, be 180 degree rotation relationships with the placement location of unit under test (805) and unit under test (808) respectively as the placement location of unit under test (806), the placement location of unit under test (808) is 180 with the placement location of unit under test (806) and unit under test (807) respectively and spends rotation relationships.When testing, the output port of each unit under test is adjacent with the output port of adjacent unit under test like this, shortens cable run distance and be easy to connect.As shown in the figure, wherein line (814) is the line that compares between unit under test (806) and unit under test (808) the corresponding output end mouth.Fig. 8 (c) is a mirror image placement location schematic diagram, the placement location of each unit under test and the placement location of adjacent unit under test are mirror, be mirror with the placement location of unit under test (810) and unit under test (811) respectively as the placement location of unit under test (809), the placement location of unit under test (811) is mirror with the placement location of unit under test (809) and unit under test (812) respectively.The corresponding output end mouth position of the output port of unit under test and adjacent unit under test is more closed on, and it is convenient to connect cabling.As shown in the figure, wherein line (815) is the line that compares between unit under test (810) and unit under test (812) the corresponding output end mouth.This embodiment is more suitable in the test of non-directional chips such as RFID.

Fig. 9 is a relatively schematic diagram of analog signal for operation result; The operation result of crystal grain (901) is an analog signal, then utilize analog to digital converter (902) that signals sampling is changed, again comparative result is delivered in the digital comparator (903), produced the output characteristic whether two crystal grain equate/mate, and feature is deposited in the feature register (904).The input of crystal grain (901) can also can be that digital signal is imported after digital-to-analogue conversion for directly analog signal input.

Figure 10 is the embodiment that the present invention is directed to supply power mode, and the power supply weld pad (1002) of all crystal grains (1001) can all be connected into global power network (1003) in the wafer, or the subregion power supply links together, and forms a plurality of locally supplied power sources network.Ground connection weld pad (1004) also can be connected into earth grid (1005) or subregion entirely and be connected to form a plurality of local ground networks.Weld pad is made of metal, places on the crystal grain outside or the crystal grain, can be connected with structure of the present invention with metal connecting line.

Figure 11 (a) is for the present invention is directed to the embodiment that aims at the symbol position, each intergranule has 60 microns-80 microns Cutting Road (1101) on the wafer, aim at the aligning that symbol (1102) is used for every layer mask version, be in usually in the Cutting Road (1101), and take all domain layers.Because the present invention need design long line in Cutting Road (1101),, can aim at corner pad (1104) position that symbol moves on to crystal grain for not conflicting with the aligning symbol.Internet, operation result comparison means and test feature let-off gear(stand) can coexist mutually with the test structure that is used for wafer acceptance test.Coexistence method can be to walk around the WAT test structure or share the WAT test structure in some position, as the pin of using in the WAT test structure is surveyed the input that pad is used to encourage.

Figure 11 (b) is that a kind of pin is surveyed the possible position distribution map of pad on wafer; In the present invention, need survey pad for importing clock into, configuration information etc. for test network provides pin.If the vacant weld pad that is not used is arranged in crystal grain (1111), then can be used as pin and survey the pad use, as A (1112), (1103) two positions of B; Also can survey the corner pad that pad is located at crystal grain (1111) to pin, as position C (1114).Also can survey pad to pin and be located in the Cutting Road (1101), as D (1117), (1118) two positions of E.

Figure 11 (c) surveys for pin and fills up the location drawing possible when crystalline substance (flip chip) encapsulation is covered in use; When using chip package, probe can be used the vacant weld pad (1122) on the crystal grain (1121) to be used as pin and survey the pad use.

See also Figure 12, Figure 12 is photoetching intra-zone test and excitation transmission structure figure and test feature derived type structure figure on the wafer.Wherein Figure 12 (a) is photoetching intra-zone test and excitation transmission structure figure on the wafer, and Figure 12 (b) is the interior tested crystal grain test feature derived type structure figure of patterned area on the wafer.Shown in Figure 12 (a), test and excitation is transferred to each interior tested crystal grain (as 1203) of this patterned area (1206) respectively via pin measuring card (1201) and by the line on the Cutting Road on the wafer (as 1202), wherein the line on the Cutting Road was determined in the domain stage, and can not change at whole test phase, each tested crystal grain operation test and excitation, produce operation result, through the operation result comparison means mutually relatively or with expected results back formation test feature relatively, shown in Figure 12 (b), in this patterned area (1206), the test feature of each tested crystal grain is coupled together by the derivation chain (1204) that constitutes with shift register and hardwired, and export to external equipment by deriving chain warp pin measuring card (1201), the derivation chain is here determined in the domain stage, and can not be changed at whole test phase.

Figure 13 the present invention is directed to the crystal grain embodiment of more configurable internet mutually, and Figure 13 (a) is the top view of this embodiment, and Figure 13 (b) shows wherein three intercrystalline connection details.The chaining pin of pin measuring card (1316) drops on the crystal grain (1311), and the input stimulus that imports into can be transferred on the corresponding input weld pad of crystal grain (1310), crystal grain (1312) by internal transmission network (1302).Transmission network (1302) is made up of numerous Basic Transmission Unit (1303).Basic Transmission Unit (1303) guarantees that by bidirectional switch (1304) signal can (the right) pass to the right (left side) from the left side, or from the top (bottom) passes to bottom (top), bidirectional switch is configured by configuration network, thereby makes pin measuring card (1316) all can be transferred to all crystal grains at the input stimulus of arbitrary crystal grain.During the transmission input stimulus, bidirectional switch (1304) is unidirectional conducting, and when comparing as output, bidirectional switch (1304) all disconnects.When bidirectional switch (1304) was unidirectional conducting, its conducting direction can be by config memory (1308) decision, also can be by the common decision of unit under test I/O control weld pad (1309) and config memory (1308).The driver (driver) (1305) of Basic Transmission Unit (1303) makes the signal transmission not produce decay.If decay is little, transmission network can not have driver (1305) yet.Also can on transmission network, add latch if desired, by the pipeline system transmission signals.In comparison phase, bidirectional switch (1304) is configured to all disconnect, and weld pad (1301) spreads out of the crystal grain operation result as the output weld pad, comparator this moment (1306) work.Weld pad in the foregoing description (1301) is the I/O weld pad, and the method for attachment of independent input weld pad or output weld pad is the subclass of this embodiment.

Figure 14 is the embodiment that the present invention is directed to collocation method.The input stimulus transmission network is derived chain with test feature and is had different topological structures, and input stimulus is that requirement is transmitted with shortest path to the four directions from the probe drop point, and test feature derives chain and wants serial through each to-be-measured cell.On each node, the input stimulus transmission network is derived the chain direction of transfer with test feature might not be consistent.The present invention seeks to set up the derivation chain of the unit under test that a test feature serial all to-be-measured cells exports to the probe place and configuration simultaneously from the unit under test at probe place transmission network to four directions transmission input stimulus with the mode of series arrangement.The mode of being taked is to set up the chain of each to-be-measured cell of process from the probe position in the mode that pointwise configuration pointwise is transmitted, the reverse of this chain is exactly real test feature direction of transfer, when setting up this chain, also disposed the transmission direction of input stimulus delivery network.The configuration information of each node by this chain transmission comprises: the chain structure configuration information is derived in excitation transport network architecture configuration information, test feature serial.Specific practice is to pass through network (1402) serial transmission to all nodes, shown in Figure 14 (a) from configuration information and the clock (1427) that probe location (1401) comes.For node (1408), clock signal and node configuration information (1427) transmit from above, dispose the config memory (1308) of the transmission direction of pumping signal on this node (1408) and the config memory (1407) that the control test feature derives direction.Config memory (1407) indication is built feature to the right and is derived chain (comprising forward clock transmission, configuration information transmission forward and reverse comparative feature transmission channels).Input stimulus (1414) is transmitted in config memory (1308) indication downwards.For node (1403), clock signal and node configuration information arrive this node (1403) from left node (1408), dispose the config memory (1308) of the transmission direction of pumping signal on this node (1403) and the config memory (1407) that the control test feature derives direction.Config memory (1407) indication continues to build feature to the right derives chain (comprising forward clock transmission, configuration information transmission forward and reverse comparative feature transmission channels).Input stimulus (1404) is transmitted in config memory (1308) indication downwards.For node (1406), clock signal and node configuration information arrive this node (1406) from left node (1403), dispose the config memory (1308) of the transmission direction of pumping signal on this node (1406) and the config memory (1407) that the control test feature derives direction.Config memory (1407) indication continues to build feature to the right derives chain (comprising forward clock transmission, configuration information transmission forward and reverse comparative feature transmission channels).Input stimulus (1488) is transmitted in config memory (1308) indication downwards.After each node once disposed, config memory (1308) and config memory (1407) did not change because of follow-up configuration information by this node.But when sending into reset signal, all be changed to initial value in outage and outside.So transmit all node configuration informations and clock successively, be transferred to the link nodes that needs by demand by node configuration information and transmission path clock (1427), node configuration information and transmission path clock (1415), node configuration information and transmission path clock (1405), node configuration information and transmission path clock (1420).Set up reverse comparative feature chain by comparative feature transmission path (1429), comparative feature transmission path (1430), comparative feature transmission path (1431), comparative feature transmission path (1433) etc., all comparative features are derived, and the transmission direction configuration of input stimulus is also disposed when setting up chain and is finished.Figure 14 (b) is the connection diagram of node (1408), node (1403), node (1406).

Figure 15 (a) is a wafer sort input path schematic diagram, and this figure is a kind of top view; Pin measuring card (1501) is transferred to each crystal grain (1504) to excitation by the excitation transmission network (1503) on the wafer to be measured (1502), wherein encourages transmission network (1503) to be configured and selects to encourage transmission path.Use this structure, pin measuring card (1501) does not need to move the transmission that just can finish test and excitation, saves the testing time; Also can be by configuration, the subregion test is carried out in the transmission excitation of selection portion subregion.

Figure 15 (b) is that a wafer sort feature derives the path schematic diagram, and this figure also is a kind of top view; Have a test feature to derive path (1505) on the tested wafer (1502), this path connects the feature register of all crystal grain to be measured (1504); All feature register are formed a shift register, and its test feature can be read by this shift register serial shift, does not need mobile pin measuring card (1501) just can read all test feature.Also can be by the subregional test feature of a configuration leading-out portion.Test feature derives path (1505) can carry out a pretest earlier after foundation is finished, derive the correctness of chain itself with input stimulus transmission network, operation result transmission network and the test feature shown in guaranteeing, its input can be imported into by node (1506) from pin measuring card (1501), behind test feature derivation chain, read from node (1507) by pin measuring card (1501), both compare mutually again, equate/mate that then expression is by pretest, otherwise, then by pretest.If not by pretest, then can rebulid input stimulus transmission network, operation result transmission network and test feature derivation chain from another unit under test by mobile pin measuring card (1501), and repeat described from detecting.Under self-testing mode, the excitation of by the input stimulus transmission network self-test being used earlier is transferred to each unit under test, and the excitation serial of above-mentioned self-test being used by the test feature let-off gear(stand) is derived again.

Figure 15 (a) and Figure 15 (b) have used input stimulus transmission network and the test feature set up among Figure 14 to derive chain.

Figure 16 is a kind of wafer schematic diagram with big current interface; Go up except having general crystal grain (1602) at a wafer (1601), several big current interfaces (1603) can also be arranged, the power supply of general crystal grain around this interface (1603) connects by hardwired.Because it can pass through bigger electric current, a plurality of crystal grain that can supply with simultaneously in the zone use, and make crystal grain to test under higher frequency.This need cooperate special-purpose can using by the probe of big electric current.

Figure 17 is the wafer sort schematic diagram of radio frequency chip crystal grain.As shown in the figure, when carrying out the wafer sort of radio frequency chip crystal grain, the antenna input weld pad that pin measuring card (1703) is gone up each tested crystal grain (as 1702) to wafer (1701) all has a corresponding reception antenna or coupler (as 1704), corresponding tested radio frequency chip crystal grain (as 1702) input test is encouraged through antenna with Wireless transmission mode, each tested radio frequency chip crystal grain (as 1702) operation test and excitation, operation result is transferred to corresponding operation result comparison means by the line on the wafer (1701), draw test feature after comparing by the mutual comparison of each tested crystal grain (as 1702) operation result or with expected results, test feature arrives the signature device by the output probe transmission on the pin measuring card (1703), thereby realizes the wafer sort of radio frequency chip crystal grain.

Figure 18 is a self-test wafer schematic diagram, as shown in the figure, this wafer (1803) has been gone up integrated test and excitation generation device (1801), the test and excitation of its generation is transferred to each tested crystal grain (as 1802) by line, and the output port of each tested crystal grain (as 1802) also is connected to wafer (1803) by line and goes up on the corresponding comparison means, whole wafer has formed complete test environment on (1803), under the situation of energising, whole wafer (1803) does not need the participation of external test facility just can independently finish the test of all crystal grains, and test feature is outputed to the signature device by the output probe on the pin measuring card.In this embodiment, test and excitation generation device (1801) also can be integrated in the Cutting Road (1804) on the wafer (1803), and occupation crystal particle position not.

Figure 19 is a kind of novel wafer sort system diagram; In this structure, comprise a tester (1901), a special test device (1902), both can test the tested wafer (1905) on the wafer sort platform (1904) by cable (1903).This special test device (1902) can provide big electric current, probe (1906) on this special test device (1902) can upward contact on the power supply/ground of all crystal grains with tested wafer (1905), realizes tested wafer (1905) holocrystalline circle or the power supply of part wafer area.Can walk abreast by the excitation that special test device (1902) is produced tester (1901) and pass to a plurality of unit under tests, drive tested wafer (1905) and go up all or part of tested crystal grain, each crystal grain is high-speed cruising input stimulus simultaneously; Test feature will export in the tester (1901) by special test device (1902) and cable (1903), if test feature is a comparative result, then tester (1901) will be judged doubtful disabling unit according to the test feature that derives.This system can also test separately doubtful disabling unit according to operation result, and has the function of mark disabling unit.

Figure 20 is multioperation unit/multi core chip close beta structure chart, as shown in the figure, in this multioperation unit/multi core chip (2010) inside, test and excitation maker (2001) produces test and excitation, and being transferred to each unit under test (as 2002,2004,2007,2009), unit under test is the arithmetic element or the processor core of multioperation unit/multi core chip inside here.Each unit under test (as 2002,2004,2007,2009) operation test and excitation, operation result is transferred to corresponding comparator and relatively draws test feature mutually, test feature writes feature register, thereby realizes the test of chip internal multioperation unit/multinuclear.In this embodiment, by relatively testing mutually, in concrete enforcement, also can relatively test between the operation result of each unit under test (as 2002,2004,2007,2009) by the operation result and the expected results of unit under test.

Figure 21 is encapsulation back chip testing schematic diagram.As shown in the figure, chip (as 2101) after each encapsulation is fixed on the circuit board (2102), the test and excitation that the test and excitation generation device produces is transferred on the input port of each chip under test, comparison strategy according to the operation result of being taked connects accordingly simultaneously, compare mutually for each chip under test, according to the comparison between each chip under test (as 2101) operation result the operation result of each chip under test is outputed to corresponding operation result comparison means (as 2103), compare for operation result and expected results, operation result of each chip under test (as 2101) and expected results are connected to corresponding operation result comparison means (as 2103), after relatively, draw test feature, form the test macro of encapsulation back chip.

Claims (12)

1. IC testing method on the common base comprises:
(a) (device under test is DUT) in down while/parallel running of same input stimulus (input stimulation), respectively simultaneously/parallel generation operation result for the unit under test that a plurality of functions on the common base are identical;
(b) if there is expected results to exist,
(i) to above-mentioned a plurality of operation results respectively with expected results simultaneously/the parallel comparison that whether equates/mate;
(ii) draw test feature, promptly comparative result equated/those unit under tests of coupling are labeled as effective unit, with comparative result unequal/unmatched those unit under tests are labeled as doubtful disabling unit; If necessary, can carry out conventionally test separately to doubtful disabling unit, to determine whether real inefficacy;
(c) if there is not expected results to exist,
(i) to above-mentioned a plurality of operation results mutually simultaneously/parallelly carry out whether equating/comparison of coupling;
(ii) draw test feature, promptly comparative result equated/those unit under tests of coupling are labeled as effective unit, with comparative result unequal/unmatched those unit under tests are labeled as doubtful disabling unit; If necessary, can carry out conventionally test separately to doubtful disabling unit, to determine whether real inefficacy;
(d) separate effective unit and disabling unit according to test feature.
2. can be single integrated circuit according to the described common base of claim 1, when described common base was single integrated circuit, unit under test be the functional module on this integrated circuit; Described common base also can be a wafer, and when described common base was wafer, unit under test was crystal grain on the wafer; Described common base can also be a circuit board, and when described common base was circuit board, unit under test was the chip on the circuit board.
3. arrangement for testing integrated circuit on the common base comprises:
(a) the identical unit under test of a plurality of functions on the described common base;
(b) a plurality of operation result comparison means on the described common base;
(c) internet on the described common base;
(d) the test feature let-off gear(stand) on the described common base.
4. can be single integrated circuit according to the described common base of claim 3, when described common base was single integrated circuit, unit under test be the functional module on this integrated circuit; Described common base also can be a wafer, and when described common base was wafer, unit under test was crystal grain on the wafer; Described common base can also be a circuit board, and when described common base was circuit board, unit under test was the chip on the circuit board.
5. according to the described operation result comparison means of claim 3, whether these operation results of sampling, conversion and comparison that are used for each unit under test is carried out the operation result after the same excitation equate/coupling; Described operation result can be the signal value on the external output port of unit under test, also can be the signal value of unit under test inside; Described operation result sampling point can be the external output port of unit under test, also can be the sampling point of unit under test inside; The sample of described sampling can be the signal of arbitrary form, includes but not limited to digital signal, analog signal; Described conversion includes but not limited to that analog signal is to the conversion to analog signal of the conversion of digital signal or digital signal; Described comparison can be each unit under test operation result respectively and between the expected results that imports into the time/relatively parallel, also can be between each unit under test operation result the time/relatively parallel; Described operation result comparison means can be the device that includes only sampling and comparing function, also can be the device that comprises sampling, conversion and comparing function; In described operation result comparison means, can be earlier to the operation result sampling, the sample that sampling is obtained compares again; Also can compare continuously operation result earlier, continuous comparative result taken a sample, as actual comparative result; Described operation result comparison means can also comprise the inefficacy decision-making function; Described operation result comparison means and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.
6. comprise the power supply transmission network according to the described internet of claim 3, be used for the power supply supply is transferred to each unit under test; The input stimulus transmission network is used for shared excitation is transferred to each unit under test, and described shared excitation can produce outside common base, also can produce outside the unit under test on common base, also can produce in unit under test; If there is expected results to exist, then expected results also is transferred to corresponding operation result comparison means by described input stimulus transmission network; The operation result transmission network is used to transmit the operation result after operation encourages; Described power supply transmission network has the switched-mode power supply ability, can be configurable, also can fix; When described power supply transmission network when being configurable, can realize switched-mode power supply by the break-make of switching device; Described input stimulus transmission network can be transferred to some or all unit under tests from the unit under test at probe place with input stimulus and expected results; Described input stimulus transmission network can be configurable, also can fix; Can be to disconnect, also can be on-disconnectable; Can be that band drives, also can be not to be with driving; Described input stimulus transmission network and operation result transmission network can comprise signal delay device, also can not comprise signal delay device; When the connection of described input stimulus transmission network or operation result transmission network is configurable, can be configured the break-make that connects in this internet by the mode of external equipment with parallel configuration or series arrangement; When described connection is configured to conducting, can be used as the input stimulus transmission network; When described connection is configured to disconnect, can be used as the operation result transmission network, each unit under test operation result output port is connected with corresponding operation result comparison means; Described input stimulus transmission network can have function switching signal, includes but not limited to that digital signal is to the conversion to digital signal of the conversion of analog signal or analog signal; Described internet and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.
7. can be configurable according to the described test feature let-off gear(stand) of claim 3, also can fix; When described test feature let-off gear(stand) when being configurable, comprise deriving the path and being connected switch, the connection switch is configured, can set up odd number bar or a plurality of test feature derivation chain, be used to derive test feature; When described test feature let-off gear(stand) for fixedly the time, constitute by fixing test feature derivation chain, can save the connection switch; The test feature that described test feature let-off gear(stand) is derived can be the judgement conclusion whether each unit under test lost efficacy, and also can be the comparative feature of unit under test operation result comparison means output; The derivation mode of test feature includes but not limited to that serial is derived, the parallel derivation and serial parallel mixing derivation; Described test feature let-off gear(stand) and unit under test on common base, it includes but not limited in unit under test at the particular location on the common base, part in unit under test part in substrate outside the unit under test and all in substrate outside the unit under test.
8. deriving chain according to the described input stimulus transmission network of claim 3, operation result transmission network and test feature can set up simultaneously by the mode of serial input configuration information, also can set up step by step by the mode of repeatedly importing configuration information; Described input stimulus transmission network can be transferred to some or all unit under tests from the unit under test at probe place with input stimulus and expected results; Described test feature derives the unit under test that chain can export to the test feature of some or all unit under tests the probe place; It is higher than the designed reliability of unit under test that described internet and test feature derive the design of chain, and possess self-checking function.
9. in the common substrate integrated circuit testing apparatus according to claim 3, can be to the judgement of taking a sample of the odd number of odd number or a plurality of unit under tests or a plurality of operation result signals, guarantee that the variation of this or these operation result signal is correct; Described odd number or a plurality of operation result signals can be the one or more of numeral output, also can be one or more ports of simulation output; Described multidigit or a plurality of port can be taken from different unit under tests; Described sampling is judged, deliver to external equipment after can taking a sample to corresponding odd number or a plurality of operation result signals and judge, the judgement after also can using logical device/chip on the common base that corresponding odd number or a plurality of operation result signals are taken a sample; Described logical device/chip includes but not limited to counter/counter chip; Described determination methods includes but not limited to check whether the signal change frequency of counter records is consistent with expection.
10. in the common substrate integrated circuit testing apparatus according to claim 3, when described common base is that wafer, unit under test are on the wafer during crystal grain, it aims at corner pad (corner pad) position that symbol (alignment mark) can move on to crystal grain; Described internet, operation result comparison means and test feature let-off gear(stand) can be placed on intragranular, also can be placed in the Cutting Road, and be used for wafer and accept test (wafer acceptance test, test structure coexistence WAT); The testing cushion (testpad) that described device additionally needs can be placed on intragranular, also can be placed in the Cutting Road, also can be placed on the untapped corner of crystal grain pad position, can also be placed on the untapped vacant pad of crystal grain (no connection pad) position; The line that is used to constitute internet or test feature and derives chain can be placed in the Cutting Road, also can be placed on intragranular or pass crystal grain; Described device and the line that is placed in the Cutting Road can be excised when crystal grain cuts automatically, can not influence the function of crystal grain own; The described testing cushion that is placed on corner pad and vacant pad position can not influence the function of crystal grain own yet.
11. can use computer automatic placement and routing software (place and routetool) to generate automatically according to the part or all of domain (layout) in the described internet of claim 3, operation result comparison means and the test feature let-off gear(stand).
12. integrated circuit test system on the common base, its feature comprises:
(a) common base and on identical unit under test, a plurality of operation result comparison means and the odd number of a plurality of functions or a plurality of test feature let-off gear(stand)s;
(b) can provide big electric current, common base top or all unit under tests are powered simultaneously, and guarantee that some or all unit under tests can be with the work of nominal operation frequency;
(c) can deliver to some or all unit under tests with encouraging simultaneously/walking abreast;
(d) above-mentioned some or all unit under test can be simultaneously/parallelly carry out the described comparison of claim 1, and produce test feature;
(e) test feature can be derived.
CN200910044937A 2009-01-03 2009-01-03 Test method, device and system of common substrate integrated circuit CN101770967A (en)

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