TW201034359A - Boost converter having two-step soft start mechanism - Google Patents

Abstract

A boost converter having two-step soft start mechanism includes a tri-input comparator for performing a current limit control process, a tri-input error amplifier for performing a voltage feedback control process, a transistor for controlling an output voltage furnished to a load, and a sensing resistor for generating a current sensing voltage. The boost converter carries out a booting operation through sequentially performing the current limit control process and the voltage feedback control process. The current limit control process is employed to compare a current sensing voltage with a first soft start voltage so as to prevent an occurrence of inrush current flowing through the transistor. The voltage feedback control process is utilized for performing error amplification over a feedback voltage generated by the load based on a second soft start voltage in an attempt to avoid a voltage overshoot occurring to the output voltage.

Description

201034359 VI. Description of the Invention: [Technical Field] The present invention relates to a boost converter, and more particularly to a boost converter having a two-stage slow start mechanism. ^ [Prior Art] Please refer to Figure 1, which is a circuit diagram of a conventional boost converter. As shown in FIG. 1, the boost converter 100 includes a slow start unit 150, a reference voltage supply unit 111, a binary wave generator 113, a two-input error amplifier, a first comparator 117, a second comparator 119, and An gate (ANDGate) 121, an N-type MOS transistor 123, an inductor 125, a sense resistor 127, a Schottky diode 129, and a filter capacitor 131. The three-input error amplifier 115 is configured to perform error amplification processing on the feedback voltage Vfb generated by the load (9) according to the first reference voltage Vref1 or the slow start voltage Vss to generate an error signal Sen_, thereby adjusting the boost converter 1〇. The output voltage Vout of 〇. Generally, in the startup phase, the output voltage V〇Ut generated by the boost converter 100 is a low f voltage that has just gradually risen from the ground voltage. At this time, if the anti-ship Vfb is directly in error with the first reference voltage Vref1 In comparison, an excessive voltage error 4 is generated as a voltage overshoot of the output voltage Vout. Therefore, the 201034359 three-input error amplifier 115 is used to first compare the feedback voltage Vfb with the slow start voltage Vss' until the output voltage v〇ut rises close to the required voltage level, and then the feedback voltage Vfb is The first reference voltage Vref1 is compared for error to avoid a voltage overshoot phenomenon of the output voltage Vout. The sense resistor 12 7 is used to sense the current Ix flowing through the transistor 丨 23 to generate a current sense voltage Vcur. The comparator 119 compares the current sensing voltage Vcur with the second reference voltage φ voltage Vref2 to control the current lx flowing through the transistor 123. However, since the current sensing voltage Vcur is a low voltage that has just gradually risen from the ground voltage during the startup phase, the current sensing voltage Vcur is directly compared with the second reference voltage Vref2, and flows through the transistor 123. The current Ιχ generates an inrush current (Inmsh Current), thereby reducing the lifetime of the transistor 123. SUMMARY OF THE INVENTION According to the practice of the present invention, a ship-type two-stage step-up boost converter is used to prevent the occurrence of surge current and voltage overshoot, thereby prolonging its electro-crystal body. Long life and stable output voltage to avoid load damage. Such boost converter H & slow start unit, three losses (9) error amplifier A||, three input terminal comparator, comparison β, AND gate (AND Gate), inductor, transistor, sense resistor, and two Polar body. The slow start unit gamma is based on the input crane and the first reference electric recording. The three-wheeled eight-differential amplifier includes 帛-positive input 7 201034359: the first round of the eight-end and the wheel-out end', wherein the first positive-wheel end is used to connect one I, the second positive input is electrically connected to the slow-starting scale, such as receiving the second The buffer input terminal receives the feedback voltage generated by the load, and the output terminal uses the transmission = green call. The three input end coffee cup includes a first non-inverting input ginseng Φ input end and an output end, wherein the first non-inverting input end is connected to the first non-inverting input end to be electrically connected to the slow start unit to receive = move f, The inverting input terminal is configured to receive the current sense detection, and the output terminal is configured to include a non-inverting input terminal, an inverting input terminal and an output terminal, wherein the non-inverting input terminal is electrically connected to the output of the three-input error amplifier. The receiving end is used for receiving the oblique wave signal, and the output end is for outputting the first pulse width modulation domain. The gate comprises a first-input terminal, a second input terminal and an output terminal, wherein the first input terminal is electrically connected to the three inputs, and the second input terminal is electrically connected to the output of the comparator. The terminal receives the first pulse width modulation signal, and the output terminal outputs the second pulse width modulation signal. The inductor includes a first end and a second end, and the first end is configured to receive the input voltage. The transistor includes a first end, a second end, and an intermediate end, wherein the first end is electrically connected to the second end of the inductor, and the gate terminal is electrically connected to the output end to receive the second pulse width modulation signal, and the second end is electrically Connected to the inverting input of the three-input comparator to provide current-voltage. The sensing resistor is electrically connected between the second end of the transistor and the ground terminal. The current sensing voltage is the voltage of the sensing resistor. The diode includes a positive terminal (Anode) and a negative terminal (Cath0de), wherein the positive terminal is electrically connected to the first end of the transistor, and the output voltage is output from the negative terminal to the load. [Embodiment] 8 201034359 In order to make the present invention more understandable, the following is a detailed description of the boosting conversion n' special embodiment of the two-stage slow start system according to the present invention, which is provided in detail. The examples are not intended to limit the scope of the invention.

Please refer to Fig. 2, which is a circuit diagram of the boost converter of the first embodiment of the present invention. As shown in FIG. 2, the boost converter includes a slow start unit 250, a reference voltage supply unit 2U, a ramp generator 213, a three-input error amplifier 215, a three-input comparator 219, a first comparator 217, and a The gate 22 has an inductor 225, a first transistor 223, a sensing resistor 227, a pole 229, and a first capacitor 231. The boost converter 2 boosts the input voltage Vin to the output voltage Vom' to the load 2. In one embodiment, the load 201 includes a series connected LED unit 2〇2 and a current limiting resistor 2 The feedback voltage Vfb generated by the load 201 is the voltage drop of the current limiting resistor 2〇3. The light emitting diode unit 2G2 may include a light emitting diode or a plurality of light emitting diodes. The reference voltage supply unit 211 is configured to provide a first reference voltage % milk, a second voltage Vref2, and a third reference voltage Vref3. The slow start unit 25 is lightly light; = the voltage Vin and the first reference voltage are finely generated to generate the first slow start voltage M2 and the second slow start voltage Vss2. The two-input error amplifier 215 includes a first-input terminal, a second positive input terminal, a negative input terminal and an output terminal, wherein the first forward wheel receives the second reference voltage and the second positive wheel is electrically connected to the slow start unit. ^ 9 201034359 To receive the second slow start voltage Vss2, the negative input terminal is electrically connected to the load 201 to receive the feedback voltage vfb, and the output terminal is used for outputting the error signal Serr. The two-input comparator 219 includes a first non-inverting input terminal, a second non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the first non-inverting input terminal is electrically connected to the reference voltage supply unit 211 for receiving a third reference voltage Vref3, the second non-inverting input terminal is electrically connected to the slow start unit 25A to receive the first slow start voltage Vssl'. The inverting input terminal is electrically connected to the sensing resistor 227 to receive the current sensing voltage Vcur, The output is used to output the comparison signal Scmp. The ramp generator 213 is used to provide a ramp signal Srimp, and the ramp signal is a triangular wave voltage or a fault tooth voltage. The first comparator 217 includes a non-inverting input terminal, an inverting input terminal, and an output terminal, wherein the non-inverting input terminal is electrically connected to the output terminal of the three-input error amplifier 215 to receive the error signal §err, the inverting input terminal. It is electrically connected to the ramp generator 213 to receive the ramp signal sramp, and the output terminal is used for outputting the pulse width Width Modulation signal Spwml. The first AND gate 221 includes a first input end, a second input end, and an output end of the output end, wherein the first input end is electrically connected to the output end of the three-wheel input comparator 219 to receive the comparison signal Scmp'. The second input end is electrically connected to the second input end. The output of the first comparator 217 receives the first pulse width modulation signal Spwml, and the output terminal outputs the second pulse width modulation signal Spwm2. The inductor 225 includes a first end and a second end 'where the first end is for receiving the input voltage Vin. The first transistor 223 includes a first end, a second end, and an output end of 201034359, wherein the first end is electrically connected to the second end of the inductor 225, and the first end is electrically connected to the round end of the first and second gates 221 to receive the first The second end of the two-pulse width modulation signal SPwm2' is electrically connected to the inverting input of the three-input comparator 219 to provide a current sensing voltage Vcur. The sensing resistor 227 is electrically connected between the second end of the first transistor 223 and the ground GND, and the current sensing voltage is the voltage drop of the sensing resistor 227. The diode 229 includes a positive terminal (An anode) and a negative terminal (Cathode), wherein the positive terminal is electrically connected to the first end of the first transistor 223, and the output voltage V〇ut is output from the negative terminal to the load 20 In the preferred embodiment, the diode 229 is a Schottky diode having a low forward voltage. The first capacitor 231 is electrically connected between the negative terminal of the diode 229 and the ground GND for performing filtering and wave processing on the output voltage v〇ut. The slow start unit 250 includes a second transistor 251, a second capacitor 253, a current source 254, a first switch 257, a second switch 259, a third switch 261, a second comparator 263, a 反相 inverter 265, and a second And gate 267. Current source 254 provides approximately a fixed current Is for performing a charging procedure on second capacitor 253 to generate capacitor voltage Vc. The second transistor 251 is used to pull down the capacitor voltage Vc to the ground voltage according to the control signal Set. The second comparator 263 performs a comparison process of the first slow start voltage vssl with the first reference voltage vren to generate the first internal signal Sint1. The inverter 265 performs an inversion process of the first internal signal sint]l to generate a second internal signal Sint2. The second AND gate 267 performs a logical AND process of the first internal signal Sint1 and the second internal signal sint2 to generate a control signal Set. Basically, the second AND gate 267 is coupled to the inverter 265 to perform the rising edge detection processing of the first internal signal Sint1 for generating a pulse wave as a control when the first internal signal Sim1 occurs the rising edge event 11 201034359 The signal Sct is used to turn on the second transistor 251, thereby pulling down the capacitor voltage Vc. The first transistor 251 includes a first end, a second end, and a gate terminal 'where the gate terminal is for receiving the control signal Sct and the second terminal is electrically connected to the ground terminal GND. The second capacitor (5) is electrically connected between the first end of the second transistor 251 and the ground GN〇. The current source 254 includes a first end and a second end of the package 3, wherein the first end is for receiving the input voltage vin, and the second end is electrically connected to the first end of the second transistor 251. The first switch 257 includes a first end, a first end, and a gate terminal, wherein the first end is electrically connected to the first end of the second transistor (5), the idle end is used to receive the first switch control signal Sswl, and the second end is used To output the first slow start voltage Vss, the second switch 259 includes a first end, a second end, and a free terminal, wherein the first end is for receiving the input voltage Vin, and the second end is electrically connected to the second paste (5) The terminal 'gate terminal' is for receiving the second switch control signal Ssw2. The second comparator 2 includes a non-inverting input and an inverting input, wherein the non-inverting input is electrically connected to the second end of the first switch 257, and the inverting input is configured to receive the first reference voltage Vrefl , Output: Used to output the first internal signal Sintl. Inverter 265 & includes an input end and an output end,

The input terminal is electrically connected to the output of the second comparator 263 to receive the first internal signal, and the Smtl' output is used to output the second internal signal Sint2. The second AND gate 267 includes a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal f is connected to the second comparator 263 money output terminal to receive the first internal signal SinU, and the second input terminal is electrically Connected to the output of the inverter 265 to receive the second internal air number Sint2, the output terminal for outputting the control signal Sct to the gate terminal of the second transistor ^ 12 201034359 The first switch 261 includes a first end, a second The terminal and the gate terminal, wherein the first end of the second crystal 251, the idle terminal is used for receiving the third switch control signal to tear the first end for outputting the second slow start voltage (4). The second transistor is attacked by an N-type gold-oxygen half-field effect transistor _-type junction field effect transistor. In one embodiment, the first switch 257, the second switch, and the third tear system are p-type gold oxide half-field f-body or P-type junction field effect transistor, and the first-switch control signal Sswl is first. The inner 4 signal Sintl, the second switch control signal Ssw2 and the third switch control signal _ are the second internal signal Sint2. Please refer to FIG. 3, which is a related signal diagram of the boost converter of FIG. 2 performing the power-on operation, and the horizontal axis of the towel is _. In the third figure, the signals from top to bottom are capacitor voltage Vc, first slow start voltage Vssl, second slow start voltage Vss2, first internal signal SinU, second internal signal plus 2, and control signals such as . As shown in Fig. 3, when the boost converter 200 performs the power-on operation, the P-flow control program is performed before the time period Tdimit parameter β and the voltage feedback control program is performed in the time period Tvfb. The circuit operation principle is as follows. In the period Tclimit, the first switch 257 is turned on, the second switch 259 and the third switch 261 are turned off, and the current source 254 provides about a fixed current Is to charge the second capacitor 2, so that the capacitor voltage Vc gradually rises from the ground voltage. At this time, the capacitance voltage % can be output as the first slow start voltage offset via the first switch 257. The three-input comparator 219 compares the gradually rising first-slow-start voltage Vss1 with the current-sense voltage Vcw to generate a comparison signal Semp, thereby controlling the current flowing through the first transistor 223, "13 201034359 to prevent the current it from protruding. The current of the first transistor 223 is reduced by the current of the wave. When the capacitor voltage vc rises to the first reference voltage Vref1, the first internal signal Smtl is switched from the low voltage level to the high voltage level, and is passed through the inverter 265. After the internal delay time ΔΤ, the second internal signal Sint2 is switched from the high voltage level to the low voltage level, that is, within the short delay time Δτ, the first internal signal is high and the second internal signal is high. Bit, so the second AND gate 267 outputs a pulse wave as a control signal Set to turn on the second transistor 251, thereby pulling down the capacitor voltage Vc to the ground voltage. In the period Tvfb, the first switch 257 is turned off, and the second switch 259 The third switch 261 is turned on, so the first slow start voltage Vss1 is pulled up to the input voltage vin, and the input % comparator 219 compares the second reference voltage Vrefi with the current sense voltage Vcu. r is to generate the comparison signal Scmp. At the same time, the current source 4 provides about a fixed current I current Is still charging the second capacitor 253, so that the capacitor voltage Vc is gradually increased by the ground voltage, and the capacitor voltage Vc is via the third switch The output of 261 is the second slow start voltage Vss2. The two-input error amplifier 215 performs error amplification processing on the feedback voltage vfb according to the gradually rising second slow start voltage Vss2 to generate the error signal Serr, thereby controlling the output voltage Vout to avoid causing The voltage overshoot phenomenon of the output voltage v 〇 m. When the second slow start voltage Vss2 rises to about the input voltage vin, the three-input error amplifier 215 performs error amplification processing on the feedback voltage vfb according to the second reference voltage Vref2 to generate an error. The signal Serr, in turn, controls the output voltage v〇ut. In an embodiment, the second reference voltage Vref2 is approximately the input voltage Vin. 14 201034359 Referring to FIG. 4, FIG. 4 is a boost conversion according to a second embodiment of the present invention. The circuit diagram of the device. As shown in Figure 4, the boost converter is similar to the boost converter 200 shown in Figure 2, the main difference is that the power is The source 254 is replaced by a current source 354. The current source 354 includes a third transistor 355, a fourth transistor 356, and a reference resistor Rref. The third transistor 355 includes a first end, a second end, and a gate terminal, wherein the first The terminal is configured to receive the input voltage Vin, and the gate is electrically connected to the second rib. The reference resistor Rref is electrically connected between the first end of the third transistor 355 and the ground GND. The fourth transistor 356 includes the first end. The second end is connected to the gate terminal of the third transistor 355, and the second terminal is electrically connected to the first end of the second transistor 251. Used to output a fixed current Is. The third transistor 355 and the fourth transistor 356 are p-type gold oxide half field effect transistors or p-type junction field effect transistors. The boost converter _ performs the power-on operation related signal waveform is the same as the signal waveform shown in Figure 3, so it will not be described again. - Please refer to Fig. 5. Fig. 5 is a circuit diagram of a preferred embodiment of the three-input error amplifier shown in Fig. 2. As shown in FIG. 5, the three-input error amplifier 215 includes a plurality of transistors 551 to 558, wherein the transistors 551 to 555 are P-type gold oxide half field effect transistors or p-type junction field effect transistors, and transistors 556. The ~558 series is an N-type gold oxide half field effect transistor or an N-type junction field effect transistor. The transistor 551 includes a first end, a second end, and a gate terminal, wherein the first terminal receives the input voltage Vin' gate terminal for receiving the bias voltage for 15 201034359. The transistor 552 includes a first end i% and a free terminal, wherein the first end is electrically connected to the first end of the transistor, the first end of the gate is electrically connected to the gate of the transistor 551, and the second end is electrically connected to the node 590. The electric body 553 includes a first end, a second end, and a gate terminal, wherein the first end is electrically connected to the second end of the electric solar body 551, and the gate end is configured to receive the second slow start voltage vs. the transistor 554 The first end, the second end, and the gate terminal are included, wherein the first end is electrically connected to the second end of the transistor 551, the gate terminal is configured to receive the second reference voltage, and the second end is electrically connected to the transistor 553. The second end. The transistor milk includes a first end, a second end, and a gate terminal, wherein the first end is electrically connected to the second end of the transistor 551, and the gate terminal receives the feedback voltage Vfb. The transistor 556 includes a first end, a second end, and a free terminal, wherein the first end is electrically connected to the second end of the transistor 553, and the idle end is electrically connected to the first end, and the first transistor 557 includes a first end, The second end, the closed end, the = terminal, and the second end of the electric body 555, the gate terminal is electrically connected to the transistor, and the second end is electrically connected to the ground terminal _. The transistor 558 is provided with a second end and a gate terminal, wherein the 鸲 and 雷 ^ terminals are electrically connected to the node 590, the gate terminal is electrically connected to the _ day _ terminal, and the second terminal is electrically connected to the ground terminal GND. The gate terminal of the above-mentioned fine 554 is a three-wheeled human-end error amplifier 215. The electro-crystals are connected to the three-input error amplifier 215 $ input terminal, and the transistor 555 is between the upper step and the positive step. At the turn-in end, node_ is == is the negative three-input error amplifier error amplifier 215 of the three-input error amplifier 215. Since 5 is a prior art, the circuit operation is not described in detail. 16 201034359 In summary, the power-on operation of the boost converter of the present invention first utilizes a three-input comparator to perform a current limiting control program and reuses The three-input error amplifier performs the voltage feedback control program' so that not only the surge current flowing through the transistor current can be avoided, but also the voltage occurrence phenomenon can be prevented from occurring. In other words, the boost converter of the present invention can significantly extend its electron crystal_lifetime and can provide a good output voltage to avoid Φ load-free damage. Although the present invention has been disclosed above, Having defined the present invention, any person who has a knowledge of Linfa's vocation and recitation can't make various changes and refinements within the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is attached to the patent application scope. The definition is final. [Simple diagram of the diagram] Lu Figure 1 is a schematic circuit diagram of a conventional boost converter. • Fig. 2 is a circuit diagram of a boost converter according to a first embodiment of the present invention. Figure 3 is a schematic diagram of the relevant signal for the boost converter of Figure 2 to perform the power-on operation, wherein the horizontal axis is the time axis. Fig. 4 is a circuit diagram showing a boost converter of a second embodiment of the present invention. Fig. 5 is a circuit diagram showing a preferred embodiment of the three-input error amplifier shown in Fig. 2. 17 201034359 [Description of main component symbols] 100, 200, 300 boost converter 1 (U, 201 load 111, 211 reference voltage supply unit 113 triangular wave generator 115, 215 three-input error amplifier 117, 217 first comparator 119 263 second comparator 121 and gate 123N type gold oxide semi-transistor 125, 225 inductor 127, 227 sense resistor 129 Schottky diode 131 filter capacitor 150, 250 slow start unit 202 light-emitting diode unit 203 Current resistance 213 ramp generator 219 three-input comparator 221 first and gate 223 first transistor 18 201034359 229 diode 231 first capacitor 251 second transistor 253 second capacitor 254 current source 257 first switch 259 Second switch _ 261 third switch 263 second comparator 265 inverter 267 second and gate 355 third transistor 356 fourth transistor 551 ~ 558 transistor © GND ground

Is, It, lx current

Scmp comparison signal

Set control signal

Serr error signal

Sintl first internal signal

Sint2 second internal signal

Spwml first pulse width modulation signal

Spwm2 second pulse width modulation signal 19 201034359

Sramp ramp signal

Sswl first switch control signal

Ssw2 second switch control signal

Ssw3 third switch control signal

Vbias bias

Vc capacitor voltage

Vfb feedback voltage φ Vin input voltage

Vout output voltage

Vrefl first reference voltage

Vref2 second reference voltage

Vref3 third reference voltage

Vssl first slow start voltage

Vss2 second slow start voltage

Rref reference resistance parameter △ T delay time

Claims (1)

201034359 VII, the scope of application for patents: 1. - A boost converter with a two-stage slow-start mechanism, scoop man. - Slow start solution, sam - input crane and = ginseng slow start series H (four) tJS; 2 amplifier, Including - a first positive input terminal, a second positive input 4 = terminal and a - terminal end, wherein the first positive input terminal is used to receive the - Wei pair - the positive wheel terminal is electrically connected to the Lai start unit to / / a slow start voltage, the negative input terminal is used to receive a feedback voltage generated by a load, and the output terminal is used for outputting an error signal; the first and second output comparators include a first-non-inverting input terminal The second non-inverting input terminal is connected to the third output voltage, and the second non-inverting input terminal is electrically connected to the slow start The unit is connected to (4) the first - slow start (four), the inverting input terminal is used to connect a current sense ", the output is used for output - comparison signal; the comparator" includes - non-inverting input, a reverse a phase input terminal and an output terminal, wherein the non-inverting input terminal is electrically connected to the wheel of the three-input error amplifier The terminal receives the error signal, the inverting input terminal is configured to receive a ramp signal, and the output terminal is configured to output a first pulse width modulation signal; the first AND (ANDGate) includes a -first input terminal a second input end is electrically connected to the output end of the three-input comparator to receive the comparison signal, and the second input end is electrically connected to the first comparator wheel The output terminal receives the first pulse width modulation signal, and the output terminal outputs a second pulse width modulation signal for 21 201034359; the inductor includes - a first end and a second end, wherein the first end For receiving the wheel-in voltage; - the first body ' includes - a first end, a second end and a - gate extreme, wherein the first end is electrically connected to the second end of the Wei sense, and the paste is electrically connected to the terminal The first and the idle output end receive the second pulse width modulation signal, and the second end is electrically connected to the inverting input end of the three-input comparator to provide the current sense 9 voltage; a sensing resistor Electrically connected between the second end of the first transistor and the ground. The current sensing voltage is a voltage drop of the sensing resistor; and a diode 'including a positive terminal (Anc) de) and a negative terminal (Ca_e), wherein the positive terminal is electrically connected to the first portion - The first end of the transistor, the negative terminal is used for: one round of voltage to the load. 2. The boost converter of claim 1, further comprising: a capacitor electrically connected between the negative terminal of the diode and the ground for performing a filtering process on the output voltage. The boost converter of claim 1, further comprising: - a ramp generator electrically coupled to the inverting input of the first comparator for providing the ramp signal. 4. The boost converter of claim 1, wherein the ramp signal is a triangular wave power 22 201034359 voltage or a fault tooth wave voltage. 5. The boost converter of claim 1, further comprising: a reference voltage supply unit electrically coupled to the slow start unit, the first positive input of the three input error amplifier, and the three input comparator The first non-reverse input terminal is configured to provide the first reference voltage, the second reference voltage, and the third reference voltage. The boost converter of claim 1, wherein the diode system is a Schottky Diode. 7. The boost converter of claim 1, wherein the first electro-optic system is a -n-type metal oxide half field effect transistor (Ν·_ Metal 0xide Semic〇nduct〇r Md (10) Transistor) or N-type The junction field effect transistor cup Typejuncti〇n is also (10) transistor). 8. The converter of claim 1, wherein the slow start unit comprises: n crystal 'comprising -m two-terminal and - gate extremes, wherein the one extreme is used to receive a control signal, and the second terminal is electrically Connected to the ground; a capacitor 'electrically connected between the first end of the second transistor and the ground; an electric containing - the first end - the second end, wherein the first end is used to receive a Into the voltage, the second end is electrically connected to the first end of the second transistor, the 1 source is used to provide a substantially fixed current to perform charging on the capacitor 23 201034359 program; - the first switch, including - a first end, a second end, and a gate terminal, wherein the first end is electrically connected to the first end of the second transistor, and the _ is received to receive the first H field out of the first a slow start voltage; - a second switch comprising - a first end, a second end and a - gate extreme, wherein the first end is for receiving the input voltage, and the second end is electrically connected to the second end of the first switch The end of the gate is for receiving a second switch control signal; # a second comparator comprising a non-inverting input An inverting input end and a round out end, wherein the non-inverting input end is electrically connected to the second end of the first switch, and the inverting input end is configured to receive the first reference voltage, and the output end is used for the wheel a first internal signal; an inverter comprising an input end and an output end, wherein the input end is electrically connected to the output end of the second comparator to receive the first internal signal, and the output end is used for outputting a second internal signal; the first and second gates include a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is electrically connected to the output end of the second comparator to receive the a first internal signal, the second input terminal is electrically connected to the output end of the inverter to receive the second internal signal, and the output end is electrically connected to the extreme between the second transistors for outputting the control signal And a second switch comprising a first end, a second end and a gate terminal, wherein the first end is electrically connected to the first end of the second transistor, and the gate end is configured to receive a third switch Control signal, the second end is used A slow start to the second voltage. 24 201034359 / The boost converter of claim 8, wherein the second electro-optic system is an n-switched half field effect transistor or an N-type junction field effect transistor. The boost converter of claim 8, wherein the first switch, the second switch, and the first-on relationship are P-type MOS field effect transistors or p-type junction field effect transistors. 9 U.7, wherein the second AND gate cooperates with the inverter β, and performs an edge detection processing on the first internal signal of the Hai, for the first internal signal. In the event of a rising edge event, a pulse wave is generated as a chirp minus to turn on the second transistor. The boost converter of claim 8, wherein the first switch control signal is the first internal signal. The boost converter of claim 8, wherein the second switch control signal and the * third switch control signal are the second internal signal. 14. The boost converter of claim 8, wherein the current source comprises: a second transistor comprising a first terminal, a second terminal and a gate terminal, wherein the first terminal is configured to receive the input voltage The second end is electrically connected to the gate terminal; the reference resistor is electrically connected between the second end of the third transistor and the ground terminal; and 25 201034359 a fourth transistor comprising the first end of the crucible a second end and a gate terminal, wherein the first terminal is configured to receive the input voltage, the gate terminal is electrically connected to the gate terminal of the third transistor, and the second terminal is electrically connected to the second transistor One end. The boost converter of claim 14 wherein the third transistor and the fourth transistor system are p-type gold oxide half field effect transistors or P-type junction field effect transistors. The boost converter of claim 1, wherein the three-input error amplifier comprises: a second transistor comprising a first end, a second end and a gate terminal, wherein the first end Receiving the input voltage 'the gate terminal is for receiving a bias voltage; a third transistor includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the second electric The first end of the crystal is electrically connected to the gate terminal of the second transistor, and the second end is electrically connected to a node; the fourth transistor includes a first end, a second end and a gate Extremely, wherein the first end is electrically connected to the second end of the second transistor, the gate end is configured to receive the second slow start voltage; and the fifth transistor comprises a first end and a second end And a gate terminal, wherein the first terminal is electrically connected to the second end of the second transistor, the gate terminal is configured to receive the second reference voltage, and the second terminal is electrically connected to the fourth transistor a second transistor, comprising a first end, a second end and a gate terminal, The first end is electrically connected to the second end of the second transistor. The gate terminal is configured to receive the feedback voltage. 26 201034359 - The seventh transistor includes - the first end, the second end and the _ gate terminal The first end is electrically connected to the second end of the fourth transistor, and is electrically connected to the first end, the second end is electrically connected to the ground end; 9 - the eighth transistor, including - a second terminal and a gate terminal, wherein the first terminal is electrically connected to the second terminal of the sixth transistor, the gate terminal is electrically connected to the gate terminal of the seventh transistor, and the second terminal is electrically connected Connected to the ground terminal; and - the ninth transistor 'includes a first end, a second end and a gate terminal, wherein the first end is electrically connected to the node 'the gate terminal is electrically connected to the sixth transistor The second end is electrically connected to the ground end; wherein the gate terminal of the fifth transistor is the first=transmission terminal of the three-input error amplifier, and the gate terminal of the fourth transistor is The second positive input terminal of the three-input human error amplifier is the gate terminal of the sixth transistor, Input terminal of the error amplifying the negative input terminal H, the point-based three input terminal for the output of the error amplifier. 17. The boost converter, wherein the second transistor, the third electric solar cell, the fourth transistor, the fifth transistor, and the type of gold oxide half field effect transistor or Ρ type Surface field effect transistor.曰曰糸:,, Ρ t seeking = the boost conversion 11 ' wherein the seventh transistor, the eighth electric field effect: the crystal system is an N-type gold-oxygen half-field effect transistor 接 junction 27 201034359 19. The boost converter of claim 1, wherein the load comprises one of a series of light emitting diode units and a current limiting resistor, the feedback voltage being one of the voltage limiting resistors. The boost converter of claim 19, wherein the light emitting diode unit comprises a light emitting diode or a plurality of serially connected light emitting diodes. ,figure: 28