.201033681 4 . 六、發明說明： 【發明所屬之技術領域】 本發明係有關一種顯示面板，特別是關於一種可避免於面板角落 區堆積真空泡之顯示面板。 【先前技術】 請參閱第1圖，液晶面板是平面顯示裝置中的關鍵元件，其主要 構件包含二基板及封裝於該二基板間之液晶層。上述二基板中，其中 薄膜電晶體基板10具有陣列的畫素電極，用以控制液晶分子的旋轉角 度；另一彩色濾光片基板12則用以使液晶面板呈現彩色的影像。液晶 ® 則被夾置於此二基板之間，且在此二基板的周圍部分利用框膠14封 裝。 在液晶面板的製造過程中，因應大尺寸液晶面板量產的需求，通 常採用液晶滴注技術，及液晶材料採用滴下的方式注入，從而適當控 制液晶材料的使用量而節省液晶材料的成本，並大幅縮減灌注液晶時 間。在使用液晶滴注法時，首先將框膠14塗布於其中一基板表面，形 成一收容空間，接著將液晶滴入此收容空間，再來將二基板疊合，藉 由紫外光照射使框膝硬化以黏合二基板。框膠14除了黏合上述之基板 外，其中還有間隔物（spacer)可用來支撐二基板，以確保二基板1〇、 12間的間距恒定。 然而，通常液晶注入量較低時，常於面板之角落區堆積較大的真 空泡16 ’此真空泡16内部因無液晶’故無法顯示影像，導致該面板 必須報廢，造成損失。 請同時參閱第2圖，此圓為第1圖沿Α·Α，線之剖視圖，分析造成 角落真空泡16積聚的原因，在於當液晶量注入過少時，因大氣壓力會 使上方的彩色濾光片基板12之玻璃基板扭曲，所以彩色濾光片基板 12中央部分會較低’而彩色濾光片基板12邊緣部分則由框膠14支樓 所以可維持原來間隔，即二基板1〇、12在邊緣處的間隔D1大於其在 3 .201033681 中央部分處的間隔D2。但由於框膠14之角落區係有水準與垂直二方 向的力支撐基板10、12 ,而其邊緣區則僅有垂直方向的力支撐基板 10、12，就基板10、12整體而言，所被支撐的力分佈不平均，因此 才會在靠近框膠14之角落區積聚較大的真空泡16。 因此，本發明係在針對上述之困擾，提出一種可避免於角落區堆 積真空泡之顯示面板，以解決上述該等缺失。 【發明内容】 本發明之主要目的，在於提供一種顯示面板，其係在面板邊緣的 框膠塗布區設置一墊高層，使此框膠塗布區的之邊緣區上下兩側基板 ® 的間距大於其角落區之上下兩側基板的間距，進而避免在面板之角落 區積聚真空泡。 為達上述目的，本發明提供一種可避免於角落區堆積真空泡之顯 示面板，包含一彼此相對設置之薄膜電晶體基板與彩色濾光片基板， 在薄膜電晶體基板與該彩色濾光片基板之間係夾置有一框膝，此框膠 塗布於薄膜電晶體基板與該彩色濾光片基板之角落區與邊緣區，另在 薄膜電晶體基板之邊緣區上設有至少一塾高層，此塾高層係與框勝重 曼。 自為使貴審查委員對本發明之結構特徵及所達成之功效更有進 -步之瞭解無識，謹佐以較佳之實施侧及配合詳細之說明，說明 如後： 【實施方式】 為了避免於顯示面板的角落區積聚較大的真空泡，本發明提出一 種顯不面板，其俯視圓如第3囷所示，第4圓為第3圖中沿A_A，線之 結構剖視圖，以下請同時參閲此二圖。顯示面板包含一薄膜電晶體基 板18與-彩色戚光片基板2〇 ’此基板2〇係與薄膜電晶效基板佔相 對設置，且-框膠塗布區位於薄膜電晶體基板18與彩色遽光片基板 20之周邊的邊緣區與角落區上。此框膠塗布區係塗布有一框膝22，使 4 .201033681 薄膜電晶艘基板18與彩色渡光片基板20之間夾置有此框勝22。框膠 塗布區的角落區為框膠22的四個轉折處，其餘部分為邊緣區，即相鄰 二轉折處所夾的框膠22區。上述之二基板18、2〇之角落區舆邊緣區， 分別緊靠框膠塗布區之角落區與邊緣區，框膠22内含有複數球狀間隔 物24，以用來支撐薄膜電晶體基板18與彩色濾光片基板20。 另在薄膜電晶體基板18之邊緣區上設有一墊高層26，此塾高層 26係與框膠22重疊’使框膠塗布區之邊緣區上下兩側的薄膜電晶體 基板18與彩色濾光片基板20的間距D1大於其角落區上下兩側的薄 膜電晶艘基板18與彩色遽光片基板20的間距D2，如此才能使彩色 參濾光片基板20受大氣壓力壓迫時，其中央部分不會太靠近薄膜電晶體 基板18，而積聚真空泡於框膠塗布區之角落區，且在設計上，墊高層 26的厚度約0.05〜0.4微米。 薄膜電晶體基板18包含一玻璃基板與複數薄膜電晶體，薄膜電晶 體設於玻璃基板上，其中墊高層26可以選自薄膜電晶體之第一金屬 層、絕緣層、半導體層、第二金屬層、保護層與透明電極層，且半導 體層包含非晶矽層與歐姆接觸層。 以下參閱第3圖及第5圖，第5圖為第3圖沿B-B，線之結構剖視 圖。從第5圖中可以看出薄膜電晶體基板18之玻璃基板28、薄膜電 〇 晶艘30與儲存電容32 ’且在薄膜電晶體基板18與彩色遽光片基板 20之間係夾持一液晶層34與球狀間隔物24，且其周圍係環設框膠22。 以下先敍述薄膜電晶體基板18之薄膜電晶體3〇與儲存電容32 的製作過程，與其組成材質及厚度。當欲製作薄膜電晶體基板18時， 係先提供一玻璃基板28，並依序在此玻璃基板28上形成第一金屬層 36、絕緣層38、半導體層40、第二金屬層46、保護層48與透明電 極層50，以同時製作出如第5圖中所示的薄膜電晶艘3〇與儲存電容 32 ’其中半導艘層40之非晶梦層42與歐姆接觸層44係同時形成， 且非晶梦層42在歐姆接觸層44與絕緣層38之間。 上述之第-金屬層36係作為薄膜電晶體3〇之閘極與儲存電容32 5 201033681 之一電極，此第一金屬層36又分成一上下二層，上層之材質為鉬 (Mo) ’下層的材質為鈥化鋁（AINd)，下層介於上廣與玻璃基板28 之間’上層介於下層與絕緣層38之間。對於7吋以下面板，上下二層 的厚度分別為500與1500埃；對於7吋以上面板，上下二層的厚度 分別為500與3000埃。 上述之絕緣層38係作為薄膜電晶體30之閘極絕緣層與儲存電容 32之介電層’其材質為氮化矽，其厚度约為2970〜3630埃。 上述之半導體層40包含非晶矽層42舆歐姆接觸層44,其係作為 薄膜電晶體30的通道，歐姆接觸層44的材質為n+摻雜之非晶矽，其 ❹厚度約為255〜345埃，非晶矽層42之厚度約為1530〜1870埃。 上述之第二金屬層46係作為薄膜電晶體30之源極舆沒極，此第 二金屬層46又分成一上、中、下三層，上、下層之材質為鉬，中層的 材質為銘’中層位於上下二層之間，下層介於中層與半導體層4〇之 間，上層介於中層與保護層48之間。上、中、下三層的厚度分別為 250、2500、300 埃。 上述之保護層48係覆蓋薄膜電晶體30之源極與汲極，並作為儲 存電容32之介電層，其材質為氮化矽，厚度約為17㈤〜23〇〇埃。上 述之透明電極層50係作為薄膜電晶體基板18之畫素電極，其材質 ❹ 氧化銦錫，厚度約為360〜440埃。 上面有說到本發明之墊高層可選自第一金屬層36、絕緣層38、半 導體層40、第二金屬層46、保護層48與透明電極層5〇，以下介紹第 一實施例，請同時參閱第3圖至第5圖，第4囷中的墊高層26即為 第5圖中介於玻璃基板28與框膠22之間的第一金屬層36，且第一金 屬層36係於同一步驟中形成薄膜電晶體基板18之薄膜電晶艘閘 極與此墊高層26。 第二實施例請同時參閱第3圖、第4圖與第6圊，第6囷為第3 圖沿B-B線之結構剖視圖。第4圖中的餐高層26即為第6圖中介於 玻璃基板28與框膠22之間的絕緣層38，且絕緣層38係於同一步驟 6 201033681 中形成賴電晶财板18之薄料紐3G _極躲層舆此塾高廣 26 〇 26 第二實施例請同時參閱第3圖、第4圖與第7圖，第7圊為第3 圖沿B-B線之結構剖視圖。第4圏中的塾高層26即為第7圖中介於 玻璃基板28與框膠22之間的半導邀層4〇，且半導趙層4〇係於同一 步驟中形成薄膜電晶艘基板18之薄膜電晶雜3G的通道與此塾高層 第四實施例請同時參閱第3圖、第4圖與第8圏，第8圖為第3 圖沿B-B’線之結構剖視圖。第4圖中的墊高層26即為第8圖中介於 參玻璃基板28與框膠22之間的第二金屬層46，且第二金屬層46係於 同-步驟巾一成薄膜電祕基板18之賴電晶體30的雜、汲極與 此墊高層26。 第五實施例請同時參閱第3圖、第4圖與第9圖，第9圖為第3 圖沿B-B’線之結構剖視圖。第4圖中的墊高層26即為第9圖中介於 玻璃基板28與框膠22之間的保護層48，且作為此塾高層26之保護 層48係於形成薄膜電晶體基板18之薄膜電晶體30上，以復蓋薄膜 電晶體30之步驟中同步形成。 第六實施例請同時參閱第3圖、第4圖與第1〇囷，第1〇圖為第 ® 3圖沿B-B’線之結構刮視圖。第4圖中的墊高層26即為第1〇圖中介 於玻璃基板28與框璆22之間的透明電極層50，且透明電極層50係 於同一步驟中形成薄膜電晶體基板18之畫素電極與此墊高層26» 墊高層26的數量也可以在一層以上，如二層。如第11圓所示， 並請同時參閱第3圖，第11圖為第3圓沿A-A，線之結構剖視囷。第 11圖與第4圖的結構差異在於墊高層26的數量多了一層，此二層第 一、第二墊高層52、54互相完全重疊，第一墊高層52係直接設於薄 膜電晶體基板18上，第二墊高層54係設於第一墊高層52上，且二 墊高層52、54皆可選自薄膜電晶體之第一金屬層、絕緣層、半導體層、 第二金屬層、保護層與透明電極層的其中二層，又二墊高層52、54 201033681 的相對位置必須與薄膜電晶艘3〇各層一致，每一層形成的步称順序亦 皆與上述相同。 以下介绍其中二種實施例，請同時參閱第3圊、第11圖與第12 圖’第12圖為第3圖沿B_B，線之結構剖視圖第h圖中的第一第 二整高層52、54係分別選自第一金屬層36與半導艘層40,即第一、 第一墊高層52、54分別為第12圖中介於玻璃基板28與框膠22之間 的第一金屬層36與半導艘層40,由於在薄膜電晶體3〇中，第一金屬 層36係位於半導體層4〇與玻璃基板28之間，因此二墊高層52、54 若欲選自第一金屬層36與半導體層40,則第一金屬層36必位於半導 Ο 體層40與玻璃基板28之間。另外，第一金屬層36係亦於同一步驟 中形成薄膜電晶艘基板18之薄膜電晶體30閘極與此第一墊高層52， 半導體層40係亦於同一步驟中形成薄膜電晶體基板18之薄膜電晶體 30的通道與此第二墊高層54 » 接著請同時參閱第3圖、第11圖與第13圖’第13圖為第3圖 沿B-B線之結構剖視圖》第11圖中的第一、第二塾高層52、54係分 別選自半導體層40與第二金屬層46,即第一、第二墊高層52、54 分別為第13圓中介於玻璃基板28與框膠22之間的半導體層40與第 二金屬層46 ’由於在薄膜電晶體30中，半導體層40係位於第二金屬 ❹ 層46與玻璃基板28之間，因此二墊高層52、54若欲選自半導體層 40與第二金屬層46，則半導體層40必位於第二金屬層46與玻璃基 板28之間。另外，半導艘層40係亦於同一步驟中形成薄琪電晶艘基 板18之薄膜電晶體30通道與此第一墊高層52，第二金屬層46係亦 於同一步驟中形成薄膜電晶體基板18之薄膜電晶體30的源極、汲極 與此第二墊高層54。 墊高層的設計還有一種漸層式的實施例，以下請參閱第3圖、第 14圖，第14圖為第3圖沿A-A’線之結構剖視圖。第14囫與第11囷 之結構差異在於墊高層的設計’在第3圖與第14圖中，二墊高層52、 54的總厚度由框膠塗布區之兩角落區向其邊緣區中部逐漸增加，換言 8 201033681 之’薄膜電晶體基板18與彩色濾光片基板20之邊緣區上的墊高層膜 厚高於其角落區上的墊高層。第一墊高層52設於薄膜電晶體基板18 上’且靠近薄膜電晶體基板18與彩色濾光片基板20之角落區，第二 塾高層54係遠離薄膜電晶體基板18與彩色濾光片基板2〇之角落區， 使此兩層墊高層52、54構成階梯狀的墊層，且墊高層52、54在靠近 薄膜電晶體基板18與彩色濾光片基板20之角落區的部分為間斷的墊 層，其中此間斷區開口密度以薄膜電晶體基板18與彩色濾光片基板 20之邊緣區向其角落區漸增。 二墊高層52、54皆可選自薄膜電晶體之第一金屬層、絕緣層、半 〇 導體層、第二金屬層、保護層與透明電極層的其中二層，又二墊高層 52、54的相對位置必須與薄膜電晶體各層一致，每一層形成的步驟順 序亦皆與上述相同。 以下介紹其中二種實施例，請同時參閲第3圖、第14圖與第15 圖，第15圓為第3圊沿B-B’線之結構剖視圖，第14圖中的第一、第 二塾高層52、54係分別選自第一金屬層36與半導體層4〇,即第一、 第一塾高層52、54分別為第15圖中介於玻璃基板28與框膠22之間 的第一金屬層36與半導體層40,由於在薄膜電晶體3〇中，第一金屬 層36係位於半導體層4〇與玻璃基板28之間，因此二墊高層52、54 參 若欲選自第一金屬層36與半導體層40,則第一金屬層36必位於半導 體層40與玻璃基板28之間。另外，第一金屬層36係亦於同一步驟 中形成薄膜電晶體基板18之薄膜電晶體30閘極與此第一墊高層52, 半導體層40係亦於同一步驟中形成薄膜電晶體基板18之薄膜電晶體 30的通道與此第二墊高層54。 接著請同時參閱第3囷、第14圓與第16囷，第16圓為第3圖 沿B-B線之結構剖視囷。第14圖中的第一、第二塾高層52、54係分 別選自半導體層40與第二金屬層46，即第-、第二塾高層52、54 分別為第16圖中介於玻璃基板28與框膠22之間的半導體層40與第 二金屬層46,由於在薄膜電晶體30中，半導體層4〇係位於第二金屬 9 201033681 層46與玻璃基板28之間，因此二墊高層52、54若欲選自半導艎層 40與第二金屬層46，則半導體層40必位於第二金屬層46與玻璃基 板28之間。另外，半導體層40係亦於同一步驟中形成薄膜電晶體基 板18之薄膜電晶體30通道與此第一墊高層52，第二金屬層46係亦 於同一步驟中形成薄膜電晶體基板18之薄膜電晶體30的源極、汲極 與此第二墊高層54。 綜上所述，本發明藉由墊高層的設計，使框膠塗布區之邊緣區上 下兩側基板的間距大於其角落區之上下兩側基板的間距，進而避免在 框膠塗布區之角落區積聚真空泡。 ® 以上所述者’僅為本發明一較佳實施例而已，並非用來限定本發 依本發明中請專利範圍所述之形狀、構造、特 冑化與修飾，均聽括於本發明之中請專利範圍 内。 【圓式簡單說明】 =圖為先馳術之顯柯祕構俯視圖。 1 ®之顯抑板結構沿Α·Α，狀結構剖視圖。 ^圓為本發明之顯料缝構俯視圖。 ❹ 第5 = 之顯不面板結構沿Α·Α’線之第一實施例的結構剖視圖。 顯示面板結構沿Β·Β，線並對應第4圖之第-實施例 的結構剖視圖。 Β-Β’線並對應第4圖之第二實施例 第6圏為第3圓之顯示面板結構沿 的結構剖視圓。 Β-Β’線並對應第4圖之第三實施例 第7圖為第3圖之顯示面板結構沿 的結構剖視圖。 圖面板結構沿Β-Β’線並對應第4圖之第四實施例 第3圖之顯不面板結構沿Β-Β，線並對應$ 4圓之第五實施例 10 201033681 的結構剖視圖。 第10圖為第3圖之顯示面板結構沿B-B’線並對應第4圖之第六實施 例的結構剖視圖。 第11圖為第3圖之顯示面板結構沿A-A’線之第二實施例的結構剖視 圖。 第12圖為第3圖之顯示面板結構沿B-B’線並對應第11圖之第一實施 例的結構剖視圖。 第13圖為第3圖之顯示面板結構沿B-B’線並對應第11圖之第二實施 例的結構剖視圖》 φ 第14圖為第3圖之顯示面板結構沿A-A’線之第三實施例的結構剖視 圖。 第15圖為第3圖之顯示面板結構沿B-B’線並對應第14圖之第一實施 例的結構剖視圖。 第16圖為第3圖之顯示面板結構沿B-B’線並對應第14圖之第二實施 例的結構剖視圖。 【主要元件符號說明】 10薄膜電晶體基板 12彩色渡光片基板 14框膠 16真空泡 18薄膜電晶體基板 20彩色濾光片基板 22框膠 24間隔物 26墊高層 28玻璃基板 30薄膜電晶體 32儲存電容 34液晶層 36第一金屬層 38絕緣層 40半導體層 42非晶矽層 44歐姆接觸層 46第二金屬層 48保護層 50透明電極層 52第一墊高層 201033681 54第二墊高層.201033681 4. Description of the Invention: [Technical Field] The present invention relates to a display panel, and more particularly to a display panel which can avoid stacking vacuum bubbles in a corner region of a panel. [Prior Art] Referring to Fig. 1, a liquid crystal panel is a key component in a flat display device, and its main components include two substrates and a liquid crystal layer interposed between the two substrates. In the above two substrates, the thin film transistor substrate 10 has an array of pixel electrodes for controlling the rotation angle of the liquid crystal molecules, and the other color filter substrate 12 is for causing the liquid crystal panel to display a color image. The liquid crystal ® is sandwiched between the two substrates, and the peripheral portion of the two substrates is sealed with a sealant 14. In the manufacturing process of the liquid crystal panel, in response to the demand for mass production of a large-sized liquid crystal panel, a liquid crystal dropping technique is generally employed, and a liquid crystal material is injected by dropping, thereby appropriately controlling the usage amount of the liquid crystal material and saving the cost of the liquid crystal material, and Significantly reduce the time of perfusion liquid crystal. When the liquid crystal dropping method is used, the sealant 14 is first applied to the surface of one of the substrates to form a receiving space, and then the liquid crystal is dropped into the receiving space, and then the two substrates are laminated, and the frame is covered by ultraviolet light. Hardened to bond the two substrates. In addition to the above-mentioned substrate, the sealant 14 has a spacer which can be used to support the two substrates to ensure a constant spacing between the two substrates 1 and 12. However, when the liquid crystal injection amount is low, a large vacuum bubble 16 is often accumulated in the corner region of the panel. The inside of the vacuum bubble 16 cannot display an image because there is no liquid crystal, and the panel must be scrapped and cause loss. Please also refer to Figure 2, this circle is the cross-sectional view of the line along the line Α·Α, and the reason for the accumulation of the corner vacuum bubble 16 is that when the liquid crystal amount is injected too little, the upper color filter will be caused by the atmospheric pressure. The glass substrate of the substrate 12 is distorted, so that the central portion of the color filter substrate 12 is lower, and the edge portion of the color filter substrate 12 is supported by the frame rubber 14 so that the original interval can be maintained, that is, the two substrates 1 and 12 The spacing D1 at the edge is greater than its spacing D2 at the central portion of 3.201033681. However, since the corner regions of the sealant 14 have the horizontal and vertical directions supporting the substrates 10 and 12, and the edge regions have only the vertical force to support the substrates 10 and 12, the substrates 10 and 12 as a whole are The supported forces are not evenly distributed, so that a larger vacuum bubble 16 is accumulated near the corner of the sealant 14. Accordingly, the present invention has been directed to a display panel that avoids the accumulation of vacuum bubbles in corner regions in order to solve the above-mentioned problems. SUMMARY OF THE INVENTION The main object of the present invention is to provide a display panel that is provided with a high-rise layer in the sealant coating area of the edge of the panel, so that the spacing between the upper and lower substrates of the edge region of the sealant-coated region is greater than The spacing of the substrates on the lower side of the corner area avoids the accumulation of vacuum bubbles in the corner areas of the panel. In order to achieve the above object, the present invention provides a display panel capable of avoiding the accumulation of vacuum bubbles in a corner region, comprising a thin film transistor substrate and a color filter substrate disposed opposite each other, and a thin film transistor substrate and the color filter substrate. A frame knee is interposed between the film and the edge region and the edge region of the color filter substrate, and at least one upper layer is disposed on the edge region of the thin film transistor substrate.塾 High-rise department and frame wins heavy man. In order to make your reviewer's understanding of the structural features and effects of the present invention more in-depth, please refer to the preferred implementation side and the detailed description, as explained below: [Embodiment] The corner area of the display panel accumulates a large vacuum bubble. The present invention provides a display panel having a plan view circle as shown in FIG. 3, and a fourth circle is a cross-sectional view along the line A_A in FIG. Read these two pictures. The display panel comprises a thin film transistor substrate 18 and a color calender substrate 2 〇 'the substrate 2 〇 is opposite to the thin film electro-crystalline substrate, and the splicing coating region is located on the thin film transistor substrate 18 and the color ray The edge area and the corner area of the periphery of the sheet substrate 20. The sealant coating zone is coated with a frame knee 22 so that the frame win 22 is sandwiched between the 4.201033681 thin film electro-crystal substrate 18 and the color light guide substrate 20. The corner area of the sealant coating area is the four turning points of the sealant 22, and the remaining part is the edge area, that is, the sealant 22 area sandwiched by the adjacent two turns. The edge regions of the corner regions of the two substrates 18 and 2 are respectively abutted against the corner regions and the edge regions of the sealant coating region, and the sealant 22 contains a plurality of spherical spacers 24 for supporting the thin film transistor substrate 18 And the color filter substrate 20. In addition, a pad high layer 26 is disposed on the edge region of the thin film transistor substrate 18, and the upper layer 26 is overlapped with the sealant 22 to form a thin film transistor substrate 18 and a color filter on the upper and lower sides of the edge region of the sealant coating region. The pitch D1 of the substrate 20 is greater than the distance D2 between the thin film electro-crystal substrate 18 on the upper and lower sides of the corner region and the color filter substrate 20, so that the central portion of the color reference filter substrate 20 is not pressed by atmospheric pressure. Will be too close to the thin film transistor substrate 18, and accumulate vacuum bubbles in the corner regions of the sealant coating region, and in design, the pad layer 26 has a thickness of about 0.05 to 0.4 microns. The thin film transistor substrate 18 comprises a glass substrate and a plurality of thin film transistors. The thin film transistor is disposed on the glass substrate, wherein the upper layer 26 of the pad may be selected from the first metal layer, the insulating layer, the semiconductor layer and the second metal layer of the thin film transistor. And a protective layer and a transparent electrode layer, and the semiconductor layer comprises an amorphous germanium layer and an ohmic contact layer. Referring to Figures 3 and 5 below, Figure 5 is a cross-sectional view of the line taken along line B-B of Figure 3. It can be seen from FIG. 5 that the glass substrate 28 of the thin film transistor substrate 18, the thin film electric crystal cell 30 and the storage capacitor 32' are sandwiched between the thin film transistor substrate 18 and the color light-emitting substrate 20 The layer 34 and the spherical spacer 24 are provided with a sealant 22 around the ring. Hereinafter, the fabrication process of the thin film transistor 3〇 and the storage capacitor 32 of the thin film transistor substrate 18 will be described, and the material and thickness thereof will be formed. When the thin film transistor substrate 18 is to be fabricated, a glass substrate 28 is first provided, and a first metal layer 36, an insulating layer 38, a semiconductor layer 40, a second metal layer 46, and a protective layer are sequentially formed on the glass substrate 28. 48 and the transparent electrode layer 50 are simultaneously formed to simultaneously form the thin film electro-crystal cell 3 〇 and the storage capacitor 32 ′ as shown in FIG. 5 , wherein the amorphous layer 42 and the ohmic contact layer 44 of the semi-conductor layer 40 are simultaneously formed. And the amorphous dream layer 42 is between the ohmic contact layer 44 and the insulating layer 38. The first metal layer 36 is used as one of the gate of the thin film transistor 3 and the storage capacitor 32 5 201033681. The first metal layer 36 is further divided into two upper and lower layers, and the upper layer is made of molybdenum (Mo) 'lower layer. The material is aluminum hydride (AINd), and the lower layer is between the upper and the glass substrate 28'. The upper layer is between the lower layer and the insulating layer 38. For panels below 7 inches, the thickness of the upper and lower layers is 500 and 1500 angstroms respectively; for panels above 7 inches, the thickness of the upper and lower layers is 500 and 3000 angstroms, respectively. The insulating layer 38 is used as the gate insulating layer of the thin film transistor 30 and the dielectric layer of the storage capacitor 32. The material is tantalum nitride and has a thickness of about 2970 to 3630 angstroms. The semiconductor layer 40 includes an amorphous germanium layer 42 ohmic contact layer 44 as a channel of the thin film transistor 30, and the ohmic contact layer 44 is made of an n+ doped amorphous germanium having a germanium thickness of about 255 to 345. The thickness of the amorphous germanium layer 42 is about 1530 to 1870 angstroms. The second metal layer 46 is used as the source annihilation pole of the thin film transistor 30. The second metal layer 46 is further divided into an upper layer, a middle layer and a lower layer. The upper and lower layers are made of molybdenum, and the middle layer is made of a material. The middle layer is located between the upper and lower layers, the lower layer is interposed between the middle layer and the semiconductor layer 4, and the upper layer is interposed between the middle layer and the protective layer 48. The thicknesses of the upper, middle and lower layers are 250, 2500 and 300 angstroms, respectively. The protective layer 48 covers the source and the drain of the thin film transistor 30 and serves as a dielectric layer for the storage capacitor 32. The material is tantalum nitride and has a thickness of about 17 (f) to 23 angstroms. The transparent electrode layer 50 described above serves as a pixel electrode of the thin film transistor substrate 18, and has a material of ❹ indium tin oxide and a thickness of about 360 to 440 angstroms. The upper layer of the pad of the present invention may be selected from the first metal layer 36, the insulating layer 38, the semiconductor layer 40, the second metal layer 46, the protective layer 48 and the transparent electrode layer 5A. The first embodiment is described below. Referring to FIG. 3 to FIG. 5 together, the upper layer 26 of the fourth layer is the first metal layer 36 between the glass substrate 28 and the sealant 22 in FIG. 5, and the first metal layer 36 is the same. In the step, a thin film cell gate of the thin film transistor substrate 18 and the pad upper layer 26 are formed. For the second embodiment, please refer to FIG. 3, FIG. 4 and FIG. 6 at the same time, and FIG. 6 is a cross-sectional view of the structure taken along line B-B of FIG. The high-rise floor 26 in FIG. 4 is the insulating layer 38 between the glass substrate 28 and the sealant 22 in FIG. 6 , and the insulating layer 38 is formed into a thin material of the Lai electric crystal board 18 in the same step 6 201033681. New 3G _ extremely hiding layer 舆 塾 塾 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 The upper layer 26 of the fourth layer is the semi-conductive layer 4 between the glass substrate 28 and the sealant 22 in FIG. 7, and the semi-conductive layer 4 is formed in the same step to form a thin film electro-crystal substrate. The channel of the 18th film electro-optical crystal 3G and the fourth embodiment of the high-rise layer are also referred to Fig. 3, Fig. 4 and Fig. 8 at the same time, and Fig. 8 is a cross-sectional view of the structure taken along line BB' of Fig. 3. The high-layer pad 26 in FIG. 4 is the second metal layer 46 between the glass substrate 28 and the sealant 22 in FIG. 8, and the second metal layer 46 is attached to the same-step towel to form a thin film acoustic substrate. The 18th is the impurity and the bungee of the transistor 30 and the upper layer 26 of the pad. In the fifth embodiment, please refer to Fig. 3, Fig. 4, and Fig. 9, and Fig. 9 is a cross-sectional view of the structure taken along line B-B' of Fig. 3. The high-layer pad 26 in FIG. 4 is the protective layer 48 between the glass substrate 28 and the sealant 22 in FIG. 9, and the protective layer 48 as the high-rise layer 26 is attached to the thin film electric circuit forming the thin film transistor substrate 18. The crystal 30 is formed synchronously in the step of covering the thin film transistor 30. For the sixth embodiment, please refer to Fig. 3, Fig. 4 and Fig. 1 at the same time. Fig. 1 is a structural view of the structure of Fig. 3 along line B-B'. The high-layer pad 26 in FIG. 4 is the transparent electrode layer 50 between the glass substrate 28 and the frame 22 in the first drawing, and the transparent electrode layer 50 is formed into the pixel of the thin film transistor substrate 18 in the same step. The number of electrodes and the upper layer of the pad 26» pad can also be more than one layer, such as two layers. As shown in the 11th circle, please also refer to Figure 3, which is the cross-sectional view of the third circle along A-A. The difference between the structure of the 11th and 4th is that the number of the upper layers 26 of the pad is one more layer. The first and second upper layers 52 and 54 of the two layers completely overlap each other, and the first high layer 52 is directly disposed on the thin film transistor substrate. 18, the second pad upper layer 54 is disposed on the first pad upper layer 52, and the two pad layers 52, 54 can be selected from the first metal layer of the thin film transistor, the insulating layer, the semiconductor layer, the second metal layer, and the protection The two layers of the layer and the transparent electrode layer, and the relative positions of the two upper layers 52, 54 201033681 must be identical to the layers of the thin film electro-ceramics, and the order of the steps formed by each layer is the same as above. Two embodiments are described below. Please refer to the third, eleventh and twelfth figures. The 12th figure is the third figure along the B_B, the first structural view of the line, the first second high layer 52 in the figure h. The 54 series are respectively selected from the first metal layer 36 and the semi-conductor layer 40, that is, the first and first pad layers 52, 54 are respectively the first metal layer 36 between the glass substrate 28 and the sealant 22 in FIG. With the semi-conductor layer 40, since the first metal layer 36 is located between the semiconductor layer 4 and the glass substrate 28 in the thin film transistor 3, the two pad layers 52, 54 are to be selected from the first metal layer 36. With the semiconductor layer 40, the first metal layer 36 must be located between the semiconductor body layer 40 and the glass substrate 28. In addition, the first metal layer 36 also forms the gate of the thin film transistor 30 of the thin film transistor substrate 18 and the first pad layer 52 in the same step, and the semiconductor layer 40 also forms the thin film transistor substrate 18 in the same step. The channel of the thin film transistor 30 and the second pad upper layer 54 » Next, please refer to Fig. 3, Fig. 11 and Fig. 13 'Fig. 13 is a sectional view of the structure of Fig. 3 along line BB, Fig. 11 The first and second upper layers 52, 54 are respectively selected from the semiconductor layer 40 and the second metal layer 46, that is, the first and second upper layers 52, 54 are respectively in the 13th circle between the glass substrate 28 and the sealant 22 Since the semiconductor layer 40 and the second metal layer 46' are in the thin film transistor 30, the semiconductor layer 40 is located between the second metal layer 46 and the glass substrate 28, so that the two high layers 52, 54 are selected from the semiconductor. The layer 40 and the second metal layer 46, the semiconductor layer 40 must be located between the second metal layer 46 and the glass substrate 28. In addition, the semi-conductor layer 40 also forms a thin film transistor 30 channel of the thin crystal cell substrate 18 and the first pad layer 52 in the same step, and the second metal layer 46 also forms a thin film transistor in the same step. The source and drain of the thin film transistor 30 of the substrate 18 and the second pad upper layer 54. The design of the upper layer of the mat also has a gradation type embodiment. Please refer to Figs. 3 and 14 below, and Fig. 14 is a cross-sectional view of the structure taken along line A-A' of Fig. 3. The difference between the structure of the 14th and 11th is the design of the upper layer of the mat. In Figures 3 and 14, the total thickness of the two high-rise layers 52, 54 is gradually increased from the two corner areas of the sealant-coated area to the middle of the edge area. In addition, in other words, the thickness of the high-rise film on the edge regions of the thin film transistor substrate 18 and the color filter substrate 20 of 201033681 is higher than that of the pad on the corner region. The first pad high layer 52 is disposed on the thin film transistor substrate 18 and adjacent to the corner regions of the thin film transistor substrate 18 and the color filter substrate 20, and the second upper layer 54 is away from the thin film transistor substrate 18 and the color filter substrate. In the corner area of the second layer, the two-layer high-rise layers 52, 54 constitute a stepped cushion layer, and the upper portions 52, 54 of the pad are intermittently located near the corner regions of the thin film transistor substrate 18 and the color filter substrate 20. The underlayer, wherein the discontinuity of the discontinuous region is increased toward the corner regions of the edge regions of the thin film transistor substrate 18 and the color filter substrate 20. The two pad layers 52, 54 may be selected from the first metal layer of the thin film transistor, the insulating layer, the semi-turned conductor layer, the second metal layer, the protective layer and the transparent electrode layer, and the second layer of the high-layer 52, 54 The relative position of the film must be identical to the layers of the thin film transistor, and the order of steps for forming each layer is the same as above. Two examples are described below. Please refer to Figure 3, Figure 14 and Figure 15 at the same time. The 15th circle is the structural view of the 3rd 圊 along the B-B' line. The first and the first in Figure 14 The second high-rise layers 52 and 54 are respectively selected from the first metal layer 36 and the semiconductor layer 4, that is, the first and first high-rise layers 52 and 54 are respectively between the glass substrate 28 and the sealant 22 in FIG. A metal layer 36 and a semiconductor layer 40, since in the thin film transistor 3, the first metal layer 36 is located between the semiconductor layer 4 and the glass substrate 28, the two high layers 52, 54 are selected from the first The metal layer 36 and the semiconductor layer 40, the first metal layer 36 must be located between the semiconductor layer 40 and the glass substrate 28. In addition, the first metal layer 36 also forms the gate of the thin film transistor 30 of the thin film transistor substrate 18 and the first pad layer 52 in the same step, and the semiconductor layer 40 also forms the thin film transistor substrate 18 in the same step. The channel of the thin film transistor 30 is connected to the second pad upper layer 54. Please also refer to the 3rd, 14th, and 16th, and the 16th is the 3rd section along the line B-B. The first and second upper layers 52, 54 in FIG. 14 are respectively selected from the semiconductor layer 40 and the second metal layer 46, that is, the first and second upper layers 52, 54 are respectively in the glass substrate 28 in FIG. The semiconductor layer 40 and the second metal layer 46 between the sealant 22 and the second metal layer 46 are disposed between the second metal 9 201033681 layer 46 and the glass substrate 28 in the thin film transistor 30. If the semiconductor layer 40 is to be selected from the semiconducting layer 40 and the second metal layer 46, the semiconductor layer 40 must be located between the second metal layer 46 and the glass substrate 28. In addition, the semiconductor layer 40 is also formed in the same step as the thin film transistor 30 of the thin film transistor substrate 18 and the first pad layer 52, and the second metal layer 46 is also formed into a thin film of the film transistor substrate 18 in the same step. The source and drain of the transistor 30 and the second pad upper layer 54. In summary, according to the design of the upper layer of the pad, the spacing between the upper and lower substrates of the edge region of the sealant coating area is greater than the spacing between the upper and lower substrates of the corner region, thereby avoiding the corner area of the sealant coating area. Accumulate vacuum bubbles. The above-mentioned 'is only a preferred embodiment of the present invention, and is not intended to limit the shape, structure, specialization and modification of the present invention as claimed in the present invention. Please refer to the patent scope. [Circular Simple Description] = The picture shows the top view of the explicit structure of the first. The 1 ® display panel structure is a cross-sectional view along the Α·Α structure. ^Circle is a top view of the material sewing structure of the present invention. ❹ 5th = a cross-sectional view of the structure of the first embodiment of the panel structure along the Α·Α' line. The display panel structure is a cross-sectional view along the structure of the first embodiment of Fig. 4 along the line Β·Β. The Β-Β' line corresponds to the second embodiment of Fig. 4, and Fig. 6 is a structural cross-sectional circle along the display panel structure of the third circle. The Β-Β' line corresponds to the third embodiment of Fig. 4. Fig. 7 is a cross-sectional view showing the structure of the display panel of Fig. 3. The panel structure is along the Β-Β' line and corresponds to the fourth embodiment of Fig. 4, and the panel structure of Fig. 3 is a cross-sectional view of the fifth embodiment 10 201033681 along the Β-Β line and corresponding to the $4 circle. Fig. 10 is a cross-sectional view showing the structure of the display panel structure of Fig. 3 taken along line B-B' and corresponding to the sixth embodiment of Fig. 4. Figure 11 is a cross-sectional view showing the structure of the second embodiment of the display panel structure of Figure 3 taken along line A-A'. Fig. 12 is a cross-sectional view showing the structure of the display panel structure of Fig. 3 taken along line B-B' and corresponding to the first embodiment of Fig. 11. Figure 13 is a cross-sectional view showing the structure of the display panel of Figure 3 taken along line BB' and corresponding to the second embodiment of Figure 11 φ. Figure 14 is a view of the display panel structure of Figure 3 along line A-A'. A cross-sectional view of the structure of the third embodiment. Fig. 15 is a cross-sectional view showing the structure of the display panel structure of Fig. 3 taken along line B-B' and corresponding to the first embodiment of Fig. 14. Fig. 16 is a cross-sectional view showing the structure of the display panel structure of Fig. 3 taken along line B-B' and corresponding to the second embodiment of Fig. 14. [Major component symbol description] 10 thin film transistor substrate 12 color light-receiving substrate 14 frame glue 16 vacuum bubble 18 thin film transistor substrate 20 color filter substrate 22 frame glue 24 spacer 26 pad high-rise 28 glass substrate 30 thin film transistor 32 storage capacitor 34 liquid crystal layer 36 first metal layer 38 insulating layer 40 semiconductor layer 42 amorphous germanium layer 44 ohmic contact layer 46 second metal layer 48 protective layer 50 transparent electrode layer 52 first pad high layer 201033681 54 second pad high layer