TW201032297A - Semiconcductor package and manufacturing method thereof and encapsulating method thereof - Google Patents

Abstract

A semiconcductor package and a manufacturing method thereof and an encapsulating method thereof are provided. The semiconcductor package includes a substrate, a flip chip, a plurality of conductive parts and a sealant. The substrate has an upper surface. The flip chip has an active surface and a chip surface opposite to the active surface. The conductive parts electrically connect the upper surface and the active surface. The sealant covers the flip chip, and the space between the upper surface and the active surface is filled with portion of the sealant. The sealant has top surface is spaced apart from the chip surface by a first distance, and the upper surface is spaced apart from the active surface by a second distance. The ratio of the first distance to the second distance is from two to five.

Description

201032297

TW5309PA VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for encapsulating abundance of conductors, and in particular to a method for manufacturing a body of a method and a method for sealing the same. Semi-conductor of the film [Prior Art] There are many types of semiconductor packages, such as 跎

Bail Grid Array) or Fccsp (FUp (the PCP uses a sealant to seal the wafer and become a semiconductor package.), etc., but the process of filling the cavity in the cavity causes the flow speed (4), thus causing the seal to fail _ = In the hole. If this is done, the packaged semiconductor package is sealed with a lot of loose and large-sized fine (1), so that the package:: ❹ Therefore, how to reduce the hole of the sealing of the semiconductor package One aspect of the present invention relates to a semiconductor package and a method of fabricating the same, the wafer and the encapsulant having a first distance, and the wafer and the encapsulating substrate having a second distance, the first distance The ratio to the second distance is a pre-two ratio 'to reduce the flow resistance of the sealant so that it is uniformly filled in the hole to reduce the size of the hole inside the sealant. According to the first aspect of the invention, a semiconductor is proposed Package. 4 201032297

• r TW5309PA The semiconductor package includes a Happiness Cup - Conductive and Sealant. And: the flip chip, a plurality of first wafers have corresponding surfaces of the active surface substrate. The flip chip and the surface of a wafer. The first electrode 4 is electrically connected to the upper surface of the substrate and the active meter, and the chip is partially filled on the upper surface of the substrate and the active package has a top surface of the sealant. The distance between the faces is - the distance between the faces, and the upper surface of the substrate is "the ratio of the first-distance to the second distance of the surface is between 2 and 5. A distance according to the second aspect of the invention provides a manufacturing The method includes the following steps: providing a to-be-suppressed component: a package substrate, a plurality of flip-chip wafers, and a plurality of second "pieces" having corresponding-active surfaces and a cymbal surface The first conductive portion is formed between the upper surface of the substrate of the package substrate to electrically connect the package substrate and the flip-chip surface to a second distance from the active surface. The setting of the inside of the mold cavity of the two main to #胶模具's sealing mold has a top surface of the cavity facing the surface of the wafer, and the top surface of the cavity is spaced from the surface of the wafer - the first distance, wherein the first distance The ratio to the second distance is between 2 and 5. A mold is filled in the cavity to cover the wafer, and the sealant and the component to be sealed are formed into a package, and a portion of the sealant is filled between the upper surface of the substrate and the active surface. According to a third aspect of the invention, a method of encapsulating a semiconductor package is provided. The sealing method includes the following steps. Providing a component to be sealed, the component to be encapsulated comprises: a package substrate, a plurality of flip chip and a plurality of first conductive portions each of the flip chip has a corresponding active surface and a 201032297 TW5309PA-s chip The surface of the first conductive portion is formed on the surface of the first inner surface of the cavity. The first distance of the wafer surface: the ratio of the two distances to the second distance is between 2 and 5; the air of the wedge 2 is extracted to bring the cavity to a vacuum pressure, wherein the vacuum force is less than negative _ kPa (hpa) Filling the cavity with a glue to cover the wafer, so that the sealant and the component to be sealed are formed into a package, and one part of the seal is filled between the upper surface of the substrate and the active surface; The speed required to enter the cavity, the time required for the sealant to fill the cavity is controlled within 15 seconds; when the sealant approaches one of the second inner wall surfaces of the cavity, the flow rate of the sealant is slowed down, wherein the first inner wall surface Facing the first inner wall surface; wherein the sealing mold includes a first a first-stage channel, a second flow channel and a third flow channel and having a cavity injection port on the inner wall surface of the cavity, a second die injection port and a second die injection port, wherein one end of the first flow channel is connected One end of the first mold injection port and the second flow path is connected to the second mold odor injection port, and one end of the third flow channel is connected to the cavity injection port, and the other end of the first flow channel, the other end of the second flow channel, and the The other end of the three-way road is replaced by a meeting place. Thereby, one part of the sealant enters from the first mold injection port A and another part of the sealant enters from the second mold injection port and meets at the intersection, flows to the cavity injection port and enters the mold. Inside the cave. In order to make the above contents of the present invention more obvious and easy to understand, the following is a special introduction to 201032297.

The preferred embodiment of the TW5309PA is described in detail below with reference to the accompanying drawings: [Embodiment] The following is a description of the preferred embodiments of the present invention, but the contents of the embodiments are for illustrative purposes only. The drawing is for the purpose of illustration and is not intended to limit the scope of the invention. Further, the drawings of the embodiments are also omitted from the unnecessary elements to clearly show the technical features of the present invention. First Embodiment Referring to Figure 1, there is shown a schematic view of a semiconductor package in accordance with a first embodiment of the present invention. The semiconductor package 1 includes a package substrate 102, a flip chip 104, a plurality of first conductive portions 〇6, a glue 108, and a plurality of second conductive portions 138. The flip chip 104 has a corresponding one of the active surface HQ and a wafer surface 112. The first conductive portion 106 is electrically connected to the substrate upper surface 114 of the package substrate 1 〇 2 and the active surface 110 . The encapsulant 108 encloses the wafer 104 and a portion 116 of the encapsulant is filled between the upper surface 114 of the substrate and the active surface 110. The knee 108 is sealed with a top surface and a side 134'. The glue side 134 is substantially flush with the substrate side 136 of the package substrate 1〇2. The second conductive portion 138 is disposed on the substrate lower surface 140 of the package substrate 102, and the second conductive portion 138 is electrically connected to the flip chip 104 through the package substrate 102. In addition, the wafer surface 112 is spaced from the top surface 118 of the sealer - a first distance 7 201032297

TW5309PA D1, and the upper surface 114 of the substrate is spaced apart from the active surface 110 by a second distance D2, and the ratio of the first distance D1 to the second distance D2 is between 2 and 5. For example, when the distance between the upper surface 114 of the substrate and the top surface 118 of the sealing material is 0.53 mm, the first distance D1 may be between 丨〇〇 micrometers (μπι) to 150 μπι and the second distance. j) 2 may be between 30 μm and 50 μm. The design of the preset ratio of the first distance D1 and the second distance D2 can reduce the flow resistance of the high temperature liquid sealant during the sealing process, so that it is evenly filled in the cavity to reduce the size of the hole inside the sealant. . Furthermore, if the ratio of the first distance D1 to the second distance D2 is too large, for example, greater than 5, the high temperature liquid sealant (not shown in FIG. 1) flows through the active surface 110 during the sealing process. The resistance to the upper surface 114 of the substrate may be greater than the resistance between the surface of the wafer 112 and the top surface 118 of the sealant. This large resistance makes the high temperature liquid sealant relatively unsmooth in flow. Before the high temperature liquid sealant has not completely filled the active surface with the upper surface 114 of the substrate, the seal may cool and solidify, thus resulting in The solidified sealant 108, particularly one portion 116 of the sealant 1〇8, has an uneven tissue density and the pore size inside the sealant is too large. In contrast, in the present embodiment, the ratio of the first distance D1 to the second distance D2 is not more than 5, which can effectively avoid the above-mentioned problem caused by excessive flow resistance. Referring to Fig. 2, there is shown a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention. 1 flat conductor 堉冋 Refer to the third diagram, which shows a schematic diagram of the second element. In step S2G2 ^ Dingdi No. 2 Figure = to (5) The components to be sealed still include - package substrate 122, several:::: 201032297

• [TW5309PA 104 and several first conductive parts 106. Each flip chip 104 has a corresponding active surface 110 and wafer surface 112. The first conductive portion 106 is formed between the substrate upper surface i24 of the package substrate 122 and the active surface 11A to electrically connect the sealing substrate 122 and the flip chip 104. The upper surface 124 of the substrate is spaced apart from the active surface 11 by a second distance D2. Further, the component to be encapsulated 120 in this step S202 can be completed in several steps. That is, the package substrate 122 and the flip chip 1 〇 4 are provided. The first conductive portion 106 is formed between the upper surface 124 of the substrate and the active surface 110 to complete the component to be encapsulated 120. _ Then, in step S204, please refer to FIG. 3B at the same time, and the edge thereof is not shown in FIG. 3A in which the component to be sealed is disposed in the cavity. A plurality of pieces 120 to be sealed are placed in one of the cavities 128 of one of the glue molds 126. The encapsulation mold 126 further has a cavity inner top surface 130 that faces the wafer surface 112. The top surface 130 of the cavity is spaced from the wafer surface 112 by a first distance D1, wherein the ratio of the first distance D1 to the second distance D2 is between 2 and 5. If the ratio of the first distance D1 to the second distance D2 is not between 2 and 5, a step (not shown) may be added in step S202: grinding the flip chip 104 from the wafer surface 112, The ratio of the first distance D1 to the second distance D2 is between 2 and 5 in order to thin the thickness of the flip chip 104. _ Then, in step S206, please refer to FIG. 3C at the same time, which does not provide a schematic diagram of the component to be sealed which is sealed in FIG. 3B. A high temperature liquid sealant 144 is supplied from the cavity injection port 142' and filled into the cavity 128 to cover the wafer 104. The solidified sealant 108 forms a package 132 with the sealant 11 of the sealant, as shown in FIG. 3D, which is painted 9 201032297

TW5309PA is a schematic diagram of the package of this embodiment. Wherein, the high temperature liquid sealant 144 flows into the space between the upper surface 124 of the substrate and the active surface Π0 to form a portion 116 of the sealant 108 in Fig. 1 after solidification. Further, after the step S206, the manufacturing method of the embodiment may include a step of forming the second conductive portion. For example, the second conductive portion 138 as shown in the second figure may be formed on the substrate lower surface 140. The second conductive portion 138 is electrically connected to the flip chip 1〇4 through the package substrate 102. Further, after the step S206, the manufacturing method of the embodiment may include a cutting step. For example, as shown in FIG. 3D, in step S2〇8, according to the position of the flip-chip wafer 1〇4, a cutting tool (not shown) is cut along the cutting path P of the 3D drawing. The package body 132 of the 3D pattern is preferably a plurality of semiconductor packages as shown in FIG. 1 . Preferably, but not limited to, the cutting path p of the 3D drawing passes through the overlap of the sealing material 1 8 and the package substrate 120. In the semiconductor package after dicing, the sealing side 134 of the encapsulant 108 and the substrate side 136 of the substrate 12 to be packaged are flush, as shown in FIG. The second embodiment is the same as the first embodiment, and the same reference numerals are used in the second embodiment, and details are not described herein again. The second embodiment is different from the first embodiment in that, in addition to the preset ratio of the first distance D1 and the second distance D2 of the semiconductor package 1 , the control can be combined with the sealing method. The process parameters are used to achieve the effect of fine-graining the size of the pores inside the sealant 108. The following describes the first process control method in the sealing method. On the 2nd 201032297

Prior to step S206 of the TW5309PA diagram, the air in the cavity 128 in Fig. 3B is withdrawn to bring the cavity 128 to a vacuum pressure, preferably less than minus 900 hectopascals (hpa), for example, minus 95 〇hpa. Thus, the impurities in the cavity 128 can be completely extracted and the internal air resistance of the cavity 28 can be lowered. Under this circumstance, in the subsequent sealing process, no excessive impurities hinder the flow of the high-temperature liquid sealant 144 (shown in Figure 3C), and it will not be affected by impurities. The structure of the sealant 108 after solidification is therefore denser and more sensitive. As a result, since the internal air resistance of the cavity 128 is lowered, the high-temperature liquid sealant 144 flows more smoothly. This is more conducive to making the seal density of the solidified seal more compact and detailed. The second process control method in the sealing method will be described below. In step S206 of Fig. 2, the speed at which the high temperature liquid sealant 144 enters the cavity 128 can be controlled. The time required for the high temperature liquid sealant 144 to fill the cavity 128 is controlled for a predetermined time, for example, 15 Within seconds. Because if the high temperature liquid sealant 144 flows in the cavity 128 for a long time, the high temperature liquid sealant 144 may begin to cool and solidify when it has not filled the entire cavity 128, thereby causing the sealant structure after solidification. Uniform and the problem of excessive hole size inside the sealant. Therefore, in this embodiment, the filling time of the high-temperature liquid sealing compound 144 is controlled for a predetermined period of time to help the density of the pores inside the solidified sealing material 108 to be tighter and finer. The following describes the third process control method in the sealing method. Please refer to Fig. 4' for a view of the sealing mold and the substrate to be glued as viewed in the direction VI of Fig. 3C. The sealing mold 126 further has a corresponding first inner wall surface 146 and a second inner wall surface 148. Cavity injection port ^ 42 position 201032297

TW5309PA is on the first inner wall surface 146. The high temperature liquid sealant 144 enters from the cavity injection port 142 and flows in the direction D5. When the high temperature liquid sealant 144 approaches the second inner wall surface 148, the flow rate of the high temperature liquid sealant 144 can be slowed to avoid high temperature. The rebound rate of the liquid sealant 144 after hitting the inner wall surface of the cavity 128 is too fast to impact the normally flowing high temperature liquid sealant. If the high-temperature liquid sealant 144 hits the inner wall surface of the cavity 128, the phenomenon of bounce is severe, which will result in unevenness of the sealant structure after solidification. In contrast, in the present embodiment, the flow rate of the sealant 144 which slows down the high temperature liquid is slowed down or the above-mentioned undesirable phenomenon is avoided, so that the sealant structure after solidification can be made uniform. In addition, another embodiment of the above third process control method will be described below. Continuing to refer to FIG. 4, the array of flip-chip wafers 104 is arrayed. The last row of flip-chip wafers, for example, are adjacent to a plurality of flip-chip wafers 104(1) adjacent to the second inner wall surface 148. When the high temperature liquid sealant 144 contacts the flip chip 104 (1), the flow rate of the high temperature liquid sealant 144 can be slowed down. In this way, it is also possible to avoid the problem that the high-temperature liquid sealant 144 hits the inner wall surface of the cavity 128 and rebounds rapidly. Referring to Fig. 5, a schematic view of the sealing mold of the second embodiment is shown. The sealing mold 126 includes a first flow channel 404, a second flow channel 4〇6 and a third flow channel 408 and has a cavity injection port 410, a second die injection port 412 and/or a second die injection port. 414. One end of the first flow path 404 is connected to the first, the mold inlet 412' second flow> «λ cj 414, one end of the third flow path 408 is connected to the cavity to inject the second mold into the second mold, and the other is the other. One end, the second flow channel 406, the male one port 410, the third side, the L person, the # >, the other end of the line is connected to a meeting place 416. And the mold eight / main and third flow passage 12 201032297

• The 'TW5309PA inlet 142 is located on the first inner wall surface 146 of the cavity 128, preferably but not exclusively, intermediate the first inner wall surface 146. During the encapsulation process, one portion 424 of the high temperature liquid sealant 144 flows from the first mold injection port 412 and another portion 426 of the high temperature liquid sealant 144 flows from the second mold injection port 414. The sealant meets at the intersection 416 and flows into a single hole into the cavity injection port 142 and into the cavity 128. Since the high temperature liquid Fengsheng 144 entering the cavity 128 is a single fluid, there is no problem of other influent liquid interference. This helps to make the sealant structure after solidification tighter, and the pore size inside the sealant is finer. Furthermore, please refer to Fig. 6, which shows a schematic view of a sealing mold having a plurality of mold inlets. The sealant mold 5〇0 has a cavity 506 and four cavity injection ports 502. Since the seal mold 500 has a plurality of cavity injection ports 502. Therefore, the plurality of high-temperature liquid sealants 5〇4 entering the cavity 506 from the plurality of cavity injection ports 502 respectively interfere with each other to hinder the flow and advancement of each other. In this way, the sealing structure after solidification is uneven, and the size of the pores inside the sealing rubber is too large. In contrast, the sealing mold 126' of the present embodiment is a single-pack high-temperature liquid sealant entering the cavity 128, so that the plurality of high-temperature liquid sealants 504 in the cavity 506 of FIG. 6 do not interfere with each other. problem. In the second embodiment, the wafer surface 112 is spaced from the encapsulating top surface 118 by a first distance D1, and the active surface 11 is spaced from the substrate upper surface 114 by a second distance D2' of the first distance D1 and the second distance D2. The ratio is between 2 and 5. In addition, after matching the above three process control methods and the mold flow path design of the seal mold 126, the high temperature liquid seal can be reduced 13 201032297

The flow resistance of the TW5309PA glue 144 is such that it fills the cavity 128 evenly and tightly. Therefore, the size of the inside of the seal 1 〇 8 can be reduced to a hole size of less than 10 mils. THIRD EMBODIMENT Referring to Figure 7, there is shown a schematic view of a semiconductor package in accordance with a third embodiment of the present invention. In the third embodiment, the same reference numerals are used for the same parts as the first embodiment, and the details are not described herein again. The third embodiment is different from the first embodiment in that the semiconductor package element 600 of the third embodiment has a ratio of the first distance D1 to the second distance D2 of between 2 and 5, which further includes Non-weld mask definition type (N〇n_s〇lder

Defined, NSMD type pad 6〇2, for example, a pad containing copper metal. The structure is described in detail below. As shown in the enlarged view of the portion A in FIG. 7 (the first conductive portion 106 is not shown), the package substrate 6〇4 of the semiconductor package 6 includes a substrate 606, a plurality of pads 6〇2, and An insulating layer 610 having a plurality of openings 6〇8. The active surface 614 of the flip chip 612 in the semiconductor package 600 is oriented toward the insulating layer 61.

The interface 602 and the insulating layer 610 are disposed on the substrate 606, and the opening 608 of the insulating layer 610 exposes the corresponding pad 602. Further, in the NSMD type configuration, the inner side 620 of the opening 608 has a gap with the outer side 622 of the corresponding pad 602. The NSMD type pad 602 and the first conductive portion 106 of the present embodiment do not need to be pre-set as the SMD structure, compared to the solder mask type (SMD) type connector (not shown). Solder 14 201032297 (pre-solder). Therefore, in the NSMD structure, the distance between the active surface 614 and the upper surface 616 of the substrate becomes smaller, thus causing the ratio of the first distance to the second distance D2 to be larger. However, according to the spirit of the present invention, as long as the ratio of the first distance D1 to the second distance D2 is controlled to be between 2 and 5, the pores inside the solidified sealant can be made to have a fine sensitizing effect. For example, similar to the technical content described in the first embodiment above, the flip chip 612 is ground from the wafer surface 618 to thin the thickness of the flip chip 612 to make the first distance D1 and the second The ratio of distance D2 is between 2 • and 5. The semiconductor package disclosed in the above embodiments of the present invention, the manufacturing method thereof and the sealing method have many advantages. The following only some of the advantages are described as follows: (1) The surface of the wafer is separated from the top surface of the sealing material by a first distance, and the active The surface is spaced apart from the upper surface of the substrate by a second distance, and the ratio of the first distance to the second distance is between 2 and 5, so as to reduce the flow resistance of the sealant, so that 10 of them are filled in the cavity from the ground, and the seal is small. (4) Dimensions of the material hole. (2) By combining the process design of the ratio design and the sealing process of the above (1), the three process control methods in the second embodiment and the design of the sealing mold of the fifth figure, the sealant after solidification can be obtained. The internal hole size is more sensitized. (3) Embodiments of the present invention are applicable to pads of the NSMJ type. Although the ratio of the first distance D1 to the second distance D2 of the semiconductor package having the NSMD type pad is large, according to the spirit of the present invention, the ratio of the first distance D1 to the second distance]) 2 is controlled at Between 2 and 5, the internal pores of the closed knee after solidification can still achieve the effect of fine payment. 15 201032297

TW5309PA In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a semiconductor package in accordance with a first embodiment of the present invention. 2 is a flow chart showing a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention. Fig. 3A is a schematic view showing the component to be sealed mentioned in Fig. 2. Fig. 3B is a schematic view showing the sealing member to be sealed in the cavity in Fig. 3A. Fig. 3C is a view showing the purpose of providing a sealant to be sealed in Fig. 3B. FIG. 3D is a schematic view showing the package of the embodiment. Fig. 4 is a view showing the sealing mold and the components to be sealed viewed in the direction VI in Fig. 3C. FIG. 5 is a schematic view showing the sealing mold of the second embodiment. Fig. 6 is a schematic view showing a sealing mold having a plurality of cavity injection ports. Figure 7 is a schematic view showing a semiconductor package in accordance with a third embodiment of the present invention. 201032297

I 1 1W5309PA [Description of main component symbols] 100, 600: semiconductor package 102, 122, 604: package substrate 104, 612: flip chip 104: first conductive portion 108: sealant 110, 614: active surface 112, 618: wafer surface ❿ 114, 124, 616: substrate upper surface 116: one part of the sealant 118: sealant top surface 120: to be sealed components 126, 500: sealant mold 128, 506: mold cavity 130: mold In-hole top surface 132: package body 134: sealant side 136: substrate side 138: second conductive portion 140: substrate lower surface 142, 502: cavity injection port 144, 504: high temperature liquid sealant 146: first inner Wall 148: second inner wall surface 404: first flow path 17 201032297

TW5309PA 406: second flow channel 408: third flow channel 412: first mold injection port 414: second mold injection port 416: intersection 424: one part of high temperature liquid sealant 426: high temperature liquid sealant Another portion 602: pad 606: substrate 608: opening 610: insulating layer 620: inner side 622: outer side D1: first distance D2: second distance D5, VI: direction P: cutting path 18

Claims (1)

201032297 VII. Patent application scope: 1. A semiconductor package, comprising: a package substrate having an upper surface of a substrate; Between the faces, the sealant has a glue, covering the flip chip, and a top surface between the upper surface of the substrate and the active surface; wherein the surface of the wafer is separated from the top surface of the sealant a first distance, wherein the upper surface of the substrate is at a second distance from the active surface, and the ratio of the first distance to the second distance is between 2 and 5. The semiconductor package of claim 1, wherein the package substrate has a lower surface of the substrate corresponding to the upper surface of the substrate, the semiconductor package further comprising: a plurality of second conductive portions, The second conductive portions are electrically connected to the flip chip via the package substrate on the lower surface of the substrate. 3. The semiconductor package of claim 2, wherein the package substrate further has a substrate side, and the seal has a glue, wherein the seal side is flush with the side of the substrate. The semiconductor package of claim 1, wherein the package substrate comprises a substrate, an insulating layer and a plurality of pads, wherein the pads are disposed on the substrate, the insulating layer has A plurality of openings, the 201032297 TW5309PA covering the openings and exposing the corresponding pads, so that the first guides correspond to the pads. T-pack 5. The inner side of each of the openings in the semi-conductive state described in claim 4 has a gap with the outer nest of the corresponding pad. Between the faces: 6· The semi-conductor described in item 1 of the patent application scope has a distance from the top surface of the substrate to the top surface of the sealant, which is a distance Q between ΙΟΟμπι and 15〇μΠι and The second mm, read between 3〇um and 50_. A method for manufacturing a semiconductor package, comprising: providing a device to be encapsulated, the device to be encapsulated comprising a slab, a plurality of flip-chip wafers, and a plurality of first conductive portions, each The base wafer has a corresponding active surface and a wafer. The covered conductive portions are formed between the upper surface of the substrate and the moving surface of the package substrate to electrically connect the package substrate and the substrate. The flip-chip is mainly provided with the mold-sealing component to a mold hole X曰9, and the glue mold has a top surface of the cavity facing the surface of the wafer, and the top surface of the cavity is spaced apart from each other. The surface of the wafer has a first distance, - the distance from the active surface - the second distance, wherein the ratio of the distance from the upper surface to the upper surface is between 2 and 5; and the second sealing material is filled in the cavity to The encapsulation forms a package with the component to be encapsulated, and the sealing sheet is filled in a portion between the upper surface of the substrate and the active surface. 8. As described in claim 7 The step of manufacturing the component to be encapsulated includes: In 20 201032297 • TW5309PA provides the sealing substrate; providing the flip chip; and forming the first conductive portions between the upper surface of the substrate to form the to-be-sealed component. ", reading the active surface, wherein the step of producing the material to be encapsulated as described in claim 7 of the patent application scope includes: Method '10. Manufacturing as described in claim 7 The thickness of the flip chip wafer flip chip is ground from the surface of the wafer such that the ratio of the first distance to the thinning is between 2 and 5. The second momentary separation method further includes extracting the air in the cavity to make the cavity reach a vacuum pressure as described in claim 10 of claim 10. The vacuum pressure is less than minus 900 hectopascals (hpa). ^方法' wherein: 12, as described in claim 7, the step of filling the cavity with the sealant includes controlling the speed at which the sealant enters the cavity, and the time required for the cavity is controlled In a preset time. The method of manufacturing according to claim 12, wherein the predetermined time is 15 seconds. 14. The manufacturing method according to claim 7, wherein the sealing mold further has a population of mold cavities, the mold population is located on a first inner wall surface of the mold cavity, and the sealant passes through The cavity injection port is filled into the cavity. In the step of filling the sealant in the cavity, when the sealant approaches the second inner wall surface of the cavity, the cover 21 is slowed down. 201032297 TW5309PA Glue The flow speed is facing. The method of manufacturing the method of claim 14, wherein the portion of the flip chip is adjacent to the second inner surface, The step of filling the sealant in the mold cavity includes slowing the flow rate of the sealant when the sealant contacts the portion of the flip chip. The manufacturing method according to the item, wherein a second flow channel and a third flow channel cavity injection port, a first mode 16. The scope of the patent application is as follows: the sealing mold comprises a first flow path, and has an inner wall mask injection opening at the cavity and a second mold injection port, wherein one end of the first flow path is connected to the first mold One end of the second flow channel is connected to the second mold injection port, and one end of the third flow channel is connected to the cavity injection port, and the other end of the first flow channel and the other end of the second flow channel are The other end of the third flow path is connected to a meeting place; Thereby, one part of the sealant enters from the first mold injection port and another part of the sealant enters from the second mold injection port to meet the intersection, and flows to the cavity injection port. And enter the cavity. 17. The method of claim 7, wherein the package substrate comprises a substrate, an insulating cover, and a plurality of pads, the pads being disposed on the substrate, the insulating layer having a plurality of Opening holes, the openings are exposed to the corresponding swears, so that the first conductive portions cover the corresponding pads. 18. The manufacturing method according to claim 7, further comprising: 22 201032297 • 1 TW5309PA The package is diced into a plurality of semiconductor packages according to the positions of the flip chip. The manufacturing method of claim 18, wherein the cutting step comprises: cutting the package along a cutting path, the cutting path passing through the seal and the overlap of the package substrate, so that After the dicing, the side of the adhesive of the sealant and the side of the substrate of the package substrate are flush. The manufacturing method of claim 7, wherein the sealant further has a top surface of the seal, the top surface of the seal corresponding to the surface of the wafer, the upper surface of the substrate being spaced apart from the top surface of the knee seal The distance is 〇. 53 coffee, the first distance is between 1〇〇|11111 to 150μπι and the second distance is between 30μιη to 5〇um. The manufacturing method of claim 7, wherein the package substrate further has a substrate lower surface, the manufacturing method further comprising: forming a plurality of second conductive portions on the lower surface of the substrate, the second The conductive portion is electrically connected to the flip chip via the package substrate. 22. The method of sealing a semiconductor package comprises: = - a component to be encapsulated, the component to be encapsulated comprising a package-based wafer and a plurality of first conductive portions, each of which: parent = corresponding An active surface and a wafer surface, wherein the == formation: one of the upper surface of the substrate of the package substrate and the main substrate of the county (four) of the flip chip, the second channel, a second channel and a The third flow channel 23 201032297 TW5309PA is located at the cavity injection port of the first inner wall surface of the cavity, the main population and the second mold population, wherein the first flow channel is connected to the first mold. The inlet, the second mold injection port and the end of the first channel are connected, and one end of the sister green first flow channel is connected to the cavity injection::: the other end of the first flow channel, the second flow channel The other end and the other end of the first track are connected to the intersection, the mold hole further includes a second inner wall surface, and the ιφ诗牮-七加侠八也匕雅弟参柚屮2 - inner wall surface The first inner wall faces face each other; the air in the cavity is extracted to bring the cavity to a vacuum pressure Wherein the vacuum pressure is less than minus 900 hpa; - the tracing, enamel sealant is filled in the cavity" such that the particular portion enters from the second inlet and the other portion of the sealant from the second mold Note: After it meets at the intersection, it flows to the cavity injection port and enters the element: 2. Covering the flip chip to make the sealant and the part to be a package Filling between the upper surface of the substrate and the active surface; Q, making the molder the speed of the mold (10), so that the time required to fill the cavity is controlled within 15 seconds; and when the sealant is close to the The second inner wall of the cavity slows down the flow rate of the glue. twenty four