TW201029138A - Leadframe strip, molding method thereof and semiconductor package having leadframe - Google Patents

Leadframe strip, molding method thereof and semiconductor package having leadframe Download PDF

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Publication number
TW201029138A
TW201029138A TW98102949A TW98102949A TW201029138A TW 201029138 A TW201029138 A TW 201029138A TW 98102949 A TW98102949 A TW 98102949A TW 98102949 A TW98102949 A TW 98102949A TW 201029138 A TW201029138 A TW 201029138A
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TW
Taiwan
Prior art keywords
lead frame
strip
leadframe
lead
units
Prior art date
Application number
TW98102949A
Other languages
Chinese (zh)
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TWI419288B (en
Inventor
Tien-Szu Chen
Kuang-Hsiung Chen
Chih-Hung Hsu
Huan-Wen Chen
Mei-Lin Hsieh
Shih-Chieh Chiu
Ying-Shih Lin
Shu-Ming Chang
Chung-Kuo Chen
Ming-Mao Hsu
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Advanced Semiconductor Eng
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Priority to TW98102949A priority Critical patent/TWI419288B/en
Publication of TW201029138A publication Critical patent/TW201029138A/en
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Publication of TWI419288B publication Critical patent/TWI419288B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A leadframe strip, a molding method of the leadframe strip and a semiconductor package having a leadframe are provided. The leadframe strip includes a plurality of leadframe units, each of which has a die pad, a plurality of leads and four tie bars. When the leadframe strip is molded by an encapsulant, the encapsulant flows through at least one top runner which is connected to a plurality of vertical gates. Each of the vertical gates is disposed above each of the leadframe units, and the encapsulant encapsulates each of the leadframe units from an upper space thereof through the vertical gates, so as to form an encapsulant body. Thus, traditional runner bars on the leadframe strip can be miniaturized, while the amount of the leadframe units can be relatively increased.

Description

201029138 - 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種導線架條及其封膠方法與具有導 線架之半導體封裝構造,特別是關於一種能提高單位時 間產出直(units per hour ’ UPH)之導線架條及其封膠方 法與具有導線架之半導體封裝構造。 【先前技術】 現今,半導體封裝產業為了滿足各種封裝需求,逐 漸發展出各種不同型式之封裝構造,其中由半導體石夕晶 圓(wafer)切割而成的矽晶片(chip)通常是先利用打線 (wire bonding)或凸塊(bumping)等適當方式選擇固定在 導線架(leadframe)或基板(substrate)上,接著再利用封裝 膠體封裝包覆保護矽晶片,如此即可完成一半導體封裝 構造的基本架構。一般常見具有導線架之封裝構造包含 小外型封裝(small outline package,SOP)、小外型j形 引腳封裝(small outline J-leaded package,SOJ)、小外型 電晶體封裝(small outline transistor,SOT)、寬體小外型 封裝(small outline package (wide-type),SOW)、雙列直 插式封裳(Dual In-line Package,DIP)、四方扁平封裝 (quad flat package ’ QFP)及四方形扁平無外引腳封裝 (quad flat non_leaded package,QFN)等。目前,為 了符 & 1產需求,通常是在一導線架條(leadframe strip)上設 置數個導線架單元,以同時進行數個晶片的固定、電性 4 201029138 連接及封膠等加工程序,最後再切割去除多餘框架,以 便同時製造完成數個具有導線架之封裝構造。 舉例而言’請參照第ΙΑ、1B及1C圖所示,其揭示 一種習用四方扁平封裝(quad flat package,QFP)構造之 導線架條在封膠前及封膠後的示意圖。如第圖所 示,一導線架條1包含一外框1〇、數個連結支架u、 數個流道支架12及數個導線架單元13。該外框1〇、連 結支架11及流道支架12相互連接,該連結支架u及 流道支架12相互垂直交叉排列,以支撐、區隔及定義 該數個導線架單元13❶各該導線架單元13具有一晶片 承座131、數個内引腳部132、數個外引腳部133、數 個壩桿(dam bar)134、三個支撐助條(tie bar)135及一個 簧形支撐助條(spring bar)136,該晶片承座131的四個 角位置利用該三個支樓助條135及該簧形支撐助條136 連接到該流道支架12及該連結支架11(或外框10)上。 該:引腳部132、外y腳部133及娜134環繞排列在 該晶片承座131的四周。該内引腳部132連接在該壤桿 \34上,該外引腳部133連接在該壩桿及該連結支 架ιι(或外框1〇)之間。再者,每一該流道支架12及其 一侧的-排科_單元13制定義成—流道分支模 塊 100 〇 如第1A圖所示,在進行封膠前,先將數個晶片W ^別固定在各該晶片承座131上,各該晶片14可利用 條導線(wire) 15電性連接至該内引腳部132。如第 5 201029138 1B圖所不,在進行封膠時,將具有該晶片14及導線15 的該導線架條1利用轉移模塑成形(transferm〇lding) 方式進行處理,其中將該導線架條〗夾置在二模具16 之間。此時,該導線架單元13對位於該二模具16共同 形成之一模穴區161中,且該二模具16在一料穴 (well)162位置利用一活塞163將一封裝膠材17壓入一 流道部(ruimer)164内’直到該封裝膠材17沿數個侧澆 口(side gate)165注入到各該模穴區161,以包覆保護各 該晶>1承座131、内引腳部132(如第1A圖所示)、晶片 14及導線15(如第1A圖所示)。該側澆口 165對應位於 該導線架單元13的簧形支撐助條136上。 如第1C圖所示’在完成封膠後,固化該封裝膠材 17,並移除該二模具16。此時,該封裝膠材17對應該 流道部164、侧澆口 165及模穴區161分別形成一流道 膠條171、數個侧澆口膠條172及數個封裝膠體173 ’ 其中該流道膠條171包覆在該流道支架12上,且每一 滅流道勝條171在每一分流點A通過一個該侧澆口膠 條172連换一個該封裝膠體I73。也就是,在每一該流 .曾分支模瑰100中,每設置一排該導線架單元13,就 必需在該導線架單元13之一侧設置一組該流道部 164(亦即該流道膠條171)’每一分流點A是以1:1的比 例經由該挪澆口 165(亦即該侧澆口膠條Π2)侧向連接 〆個該封裝膠體I73。 然而,在此種導線架條1的流道分支模塊10〇設計 6 201029138 中’每隔一排該導線架單元13就必需設置一個該流道 去牟]9 、 八 ’以方便後續形成該流道膠條171及侧澆口膠 條172。但是’此種流道支架12與導線架單元13的1:1 排列比例設計具有過多數量的流道支架12 ,其相對限 制了該導線架條1可用以設置該導線架單元13的空 間’,即相對限制該導線架單元13的總單元數量。結 果’母進行一次封膠製程,僅能在該導線架條1上形成 有限數量的該封裝膠體Π3,同時必需浪費不少的該導 ® ,架條1空間’因而導致難以進-步提高該封膠製程的 早位時間產出量(units per hour,UPH) 〇 故’有必要提供一種導線架條及其封膠方法與具有 導線架之半導體封裝構造,崎決習知賴所存在的問 題。 【發明内容】 、本發明之主要目的在於提供-種導線架條及其封膠 方法與具有導線架之半導體封裝構造,其中導線架條設 置數個導線架單元,且導線架條省略設置現有流道支 架’進而有利於增加導線架單元的佈局數量、提升導線 架條的工間细率、增加封膠製程的單位時間產出量 (UPH) JU目對降低半導體封裝構造的平均封膠成本。 本發明之-人要目的在於提供—種導絲條及其封膝 方法與具有導線架之半導體封裝構造,其中利用至少一 上流道部連結數個垂錢口,以分別由各該導線架單元 7 201029138 2方進行封膠,分別形成—封裝膠體,上流道部及垂 而:位於導線架條上方,不會佔用導線架條的空間, 提升空間利用率、增加單位時間產 降低平均封膠成本。 t發明之另—目的在於提供—種導線祕及其封膠 f與具有導線架之半導體封裝構造,其中在完成封膠 ,垂直洗口膠條可與各料線架單元的封裝膠體輕易201029138 - VI. Description of the Invention: [Technical Field] The present invention relates to a lead frame strip and a sealing method thereof, and a semiconductor package structure having a lead frame, in particular to a unit capable of improving unit time per unit (per units per Hour 'UPH) lead frame strip and its sealing method and semiconductor package structure with lead frame. [Prior Art] Nowadays, in order to meet various packaging requirements, the semiconductor packaging industry has gradually developed various types of package structures. Among them, chip chips cut from semiconductor wafers are usually first used for wire bonding ( Wire bonding or bumping is selected to be fixed on a leadframe or substrate, and then encapsulated to protect the germanium wafer by encapsulation, so that the basic structure of a semiconductor package can be completed. . Generally, a package structure having a lead frame includes a small outline package (SOP), a small outline J-leaded package (SOJ), and a small outline transistor package (small outline transistor). , SOT), small outline package (wide-type), SOW, dual in-line package (DIP), quad flat package 'QFP' And quad flat non-leaded package (QFN). At present, in order to meet the production requirements, a plurality of lead frame units are usually arranged on a leadframe strip to simultaneously perform processing of fixing several wafers, electrical connection, and sealing and sealing. Finally, the excess frame is cut and removed to simultaneously manufacture a plurality of package structures having lead frames. For example, please refer to Figures 1, 1B and 1C for a schematic diagram of a conventional quad flat package (QFP) constructed lead frame strip before and after sealing. As shown in the figure, a lead frame strip 1 includes an outer frame 1 〇, a plurality of connecting brackets u, a plurality of flow path brackets 12, and a plurality of lead frame units 13. The outer frame 1 , the connecting bracket 11 and the runner bracket 12 are connected to each other, and the connecting bracket u and the runner bracket 12 are vertically arranged to cross each other to support, partition and define the plurality of lead frame units 13 and the lead frame unit. 13 has a wafer holder 131, a plurality of inner lead portions 132, a plurality of outer lead portions 133, a plurality of dam bars 134, three support bars 135 and a spring support Spring bar 136, the four corner positions of the wafer holder 131 are connected to the flow path bracket 12 and the joint bracket 11 (or the outer frame by the three branch bar 135 and the spring support bar 136) 10) On. The lead portion 132, the outer y leg portion 133, and the 134 are circumferentially arranged around the wafer holder 131. The inner lead portion 132 is connected to the soil rod \34, and the outer lead portion 133 is connected between the dam rod and the joint bracket (or the outer frame 1). Furthermore, each of the flow path support 12 and its side-distribution unit 13 is defined as a flow path branching module 100. As shown in FIG. 1A, a plurality of wafers are first processed before sealing. It is not fixed to each of the wafer holders 131. Each of the wafers 14 can be electrically connected to the inner lead portion 132 by a wire 15 . As shown in FIG. 5 201029138 1B, when the encapsulation is performed, the lead frame strip 1 having the wafer 14 and the wires 15 is processed by transfer molding, wherein the lead frame is processed. Sandwiched between the two molds 16. At this time, the lead frame unit 13 is formed in a cavity region 161 formed by the two molds 16 together, and the two molds 16 press a package adhesive 17 into the package 163 at a position of a well 162. In the ruimer 164, the package material 17 is injected into each of the cavity regions 161 along a plurality of side gates 165 to cover and protect each of the crystals > The lead portion 132 (shown in FIG. 1A), the wafer 14 and the lead 15 (as shown in FIG. 1A). The side gate 165 corresponds to the spring-shaped support bar 136 of the lead frame unit 13. As shown in FIG. 1C, after the encapsulation is completed, the encapsulant 17 is cured and the two molds 16 are removed. At this time, the encapsulating material 17 corresponding to the flow channel portion 164, the side gate 165 and the cavity region 161 respectively form a first-class rubber strip 171, a plurality of side gate strips 172 and a plurality of encapsulants 173 ' The rubber strip 171 is coated on the flow path bracket 12, and each of the extinguishing strips 171 is connected to the encapsulant I73 through one of the side gate strips 172 at each of the diverting points A. That is, in each of the streams, the branch module 100, each of which is provided with a row of the lead frame unit 13, it is necessary to provide a set of the flow path portion 164 on one side of the lead frame unit 13 (i.e., the flow) The rubber strip 171)' each split point A is laterally connected to the encapsulant I73 via the sprue 165 (ie, the side gate strip 2) at a ratio of 1:1. However, in the flow path branching module 10 〇 design 6 201029138 of such a lead frame strip 1 , every other row of the lead frame unit 13 must be provided with a flow path to 牟 9 , 8 ' to facilitate subsequent formation of the flow Rubber strip 171 and side gate strip 172. However, the 1:1 arrangement ratio of the flow path bracket 12 and the lead frame unit 13 has an excessive number of flow path brackets 12, which relatively restricts the space available for the lead frame strips 13 to set the lead frame unit 13, That is, the total number of units of the lead frame unit 13 is relatively limited. As a result, the mother performs a sealing process, and only a limited number of the encapsulating colloids 3 can be formed on the lead frame strip 1, and at the same time, a lot of the guides® must be wasted, and the rack 1 space is made, which makes it difficult to further improve the The unit per hour (UPH) of the sealant process is why it is necessary to provide a lead frame strip and its sealing method and a semiconductor package structure with a lead frame. . SUMMARY OF THE INVENTION The main object of the present invention is to provide a lead frame strip and a method for sealing the same, and a semiconductor package structure having a lead frame, wherein the lead frame strip is provided with a plurality of lead frame units, and the lead frame strip is omitted from the existing flow. The track brackets, in turn, help to increase the number of layouts of the leadframe units, increase the fineness of the leadframe strips, and increase the throughput per unit time of the encapsulation process (UPH). The purpose of reducing the average sealing cost of the semiconductor package construction is to reduce the average sealing cost of the semiconductor package structure. The present invention has an object to provide a guide wire and a method for sealing the same, and a semiconductor package having a lead frame, wherein at least one upper flow portion is used to connect a plurality of money money ports to respectively be used by each of the lead frame units 7 201029138 2 square sealing, respectively forming - encapsulation colloid, upper runner and vertical: above the lead frame strip, does not occupy the space of the lead frame strip, improve space utilization, increase unit time production and reduce average sealing cost . Another object of the invention is to provide a kind of wire secret and its sealing material f and a semiconductor package structure having a lead frame, wherein in the completion of the sealing, the vertical cleaning strip can be easily combined with the encapsulating colloid of each material line frame unit.

刀離、’且垂直洗口接點殘留在—引腳順序指示部之凹部 2 ’進而有利於提高導線架條的去膠㈣她)便利性及 簡化產品加工過程。The knife is separated, and the vertical wash contact remains in the recess 2' of the pin sequence indicating portion, which in turn facilitates the stripping of the lead frame strip, and facilitates the product processing.

為達上述之目的,本發明提供一種導線架條,其包 含數個導線架單元。該數個導線架單元呈矩陣狀相互鄰 接排列’且各該導線架單元具有—晶片承座、數個引腳 部及四個支撐助條。該數個引腳部環繞排列在該晶片承 座之至少二侧。該四個支撐肋條設置在該晶片承座之四 個角位置。各該導線架早元具有一封裝膠體預留區,在 該封裝膠體預留區之範圍内具有一澆口接點預留區。 再者,本發明提供一種導線架條之封膠方法,其包 含步驟:提供一導線架條,其包含數個導線架單元;使 一熱熔之封裝膠材沿一上流道部流動,該上流道部延伸 在該數個導線架單元上方;使該上流道部之封裝膠材經 由數個分流點分別向下流入一垂直澆口;以及,使各該 垂直澆口内之封裝膠材分別注入各該導線架單元内,以 分別形成一封裝膠體。 8 201029138 另外,本發明提供一種具有導線架之半導體封裝構 造,其包含一導線架、至少一晶片及一封裝膠體。該導 線架包含一晶片承座、數個内引腳及數個外引腳。該晶 片設置在該晶片承座上,並電性連接於該内引腳。該封 裝膠體包覆該晶片承座、内引腳及晶片。該封裝膠體之 一上表面具有一引腳順序指示部,在該引腳順序指示部 之範圍内殘留有一垂直澆口接點。 在本發明之一實施例中,該導線架單元的四個支撑 • 肋條實質相同。 在本發明之一實施例中’該澆口接點預留區位於該 導線架單元之封裝膠體預留區最接近一封裝膠材來源 端的角位置附近。 在本發明之一實施例中,該垂直洗口位於該導線架 單元最接近一封裝膠材來源端的角位置附近。 在本發明之一實施例中,該最接近封裴膠材來源端 參 的角位置係該導線架具有一第一引腳的角位置。 在本發明之一實施例中,該引腳順序指示部是一凹 部。 在本發明之一實施例中,該引腳順序指示部係位於 該導線架具有一第一引腳的角位置附近。 ' ^ 在本發明之一實施例中, 引腳之導線架單元。 在本發明之一實施例中, 成在一組模具上。 該導線架單元選自具四排 該上流道部及垂直海口形 201029138 在本發明之一實施例中,在提供該導線架條之步驟 後’另包含:分別在各該導線架單元上放置至少一晶 片,並使該晶片電性連接該導線架單元。 【實施方式】 為了讓本發明之上述及其他目的、特徵、優點能更 明顯易懂,下文將特舉本發明較佳實施例,並配合所附 圖式,作詳細說明如下。 請參照第2A、2B、2C及2D圖所示,本發明較佳 實施例之導線架條及其封膠方法主要應用於製造具四 排引腳導線架之半導體封裝產品,例如應用於製造四方 扁平封裝(quad flat package,QFP)、四方形扁平無外引 腳封裝(quad flat non-leaded package,QFN)或其他類似 的封裝產品,但亦可應用於製造具雙排引腳導線架之半 導體封裝產品,例如小外型封裝(S〇p)、小外型j形引 腳封裝(SOJ)、小外型電晶體封裝(s〇T)、寬體小外型封 裝(S0W)、雙列直插式封裝(DIP)或其他類似的封裝產 品0 請參照第2A圖所示,本發明較佳實施例之導線架 條2係一條狀板體,其通常係由銅、鐵、鋁、鎳或等效 金屬或合金所製成,並經由沖壓(punching)或其他等效 方法加工形成下列細部構造,其中該導線架條2包含一 外框20、數個連結支架21及22及數個導線架單元23。 該外框20、連結支架21及22相互連接,該連結支架 201029138 向間隔排列在該外框2〇心 向間隔排列在該外框20内,該 ==22縱 垂直交叉排列,以支撐、區隔及定義單Its互 使,導線架單元23呈矩陣狀相互鄰導接^ 明再參照第2A圖所示,本發明輕去 架單开Μ齡杜力a Θ較佳實施例之導線 胸腳2 湘腳之導線架,但亦可為具雙 HI腳之導線架。各該導線架單元 OQt 具有一晶片承座To achieve the above objects, the present invention provides a lead frame strip comprising a plurality of lead frame units. The plurality of lead frame units are arranged adjacent to each other in a matrix shape and each of the lead frame units has a wafer holder, a plurality of lead portions, and four support tabs. The plurality of pin portions are circumferentially arranged on at least two sides of the wafer holder. The four support ribs are disposed at four angular positions of the wafer holder. Each of the lead frames has an encapsulation colloid reserved area in the early element, and has a gate contact reserved area within the range of the encapsulation colloid reserved area. Furthermore, the present invention provides a method for sealing a lead frame strip, comprising the steps of: providing a lead frame strip comprising a plurality of lead frame units; and flowing a hot-melt encapsulating material along an upper flow path portion, the upper flow Extending the plurality of lead frame units above the plurality of lead frame units; causing the encapsulating material of the upper flow path portion to flow downwardly into a vertical gate through the plurality of splitting points; and injecting the sealing adhesive materials in each of the vertical gates into the respective vertical gates The lead frame unit is internally formed to form an encapsulant. 8 201029138 Additionally, the present invention provides a semiconductor package structure having a leadframe comprising a leadframe, at least one wafer, and an encapsulant. The lead frame includes a wafer holder, a plurality of inner pins, and a plurality of outer pins. The wafer is disposed on the wafer holder and electrically connected to the inner lead. The encapsulant encapsulates the wafer holder, inner leads and wafer. An upper surface of the encapsulant has a pin sequence indicating portion, and a vertical gate contact remains in the range of the pin sequence indicating portion. In one embodiment of the invention, the four support ribs of the leadframe unit are substantially identical. In one embodiment of the invention, the gate contact reserve area is located near an angular position of the package colloid reserved area of the lead frame unit that is closest to a source end of a package adhesive. In one embodiment of the invention, the vertical wash is located adjacent the angular position of the leadframe unit closest to a source end of the encapsulant. In one embodiment of the invention, the angular position closest to the source of the sealant source is such that the leadframe has an angular position of a first pin. In an embodiment of the invention, the pin sequence indicating portion is a recess. In one embodiment of the invention, the pin sequence indicating portion is located adjacent the angular position of the lead frame having a first pin. ' ^ In one embodiment of the invention, the leadframe unit of the pin. In one embodiment of the invention, it is formed on a set of dies. The lead frame unit is selected from the group consisting of four rows of the upper flow channel portion and the vertical seaport shape 201029138. In an embodiment of the present invention, after the step of providing the lead frame strip, the method further comprises: respectively placing at least one of the lead frame units A wafer is electrically connected to the leadframe unit. The above and other objects, features and advantages of the present invention will become more <RTIgt; Referring to FIGS. 2A, 2B, 2C and 2D, the lead frame strip and the sealing method thereof according to the preferred embodiment of the present invention are mainly applied to manufacturing a semiconductor package product having a four-row lead frame, for example, for manufacturing a square. Quad flat package (QFP), quad flat non-leaded package (QFN) or other similar package, but can also be used to manufacture semiconductors with double row lead frame Packaged products, such as small outline package (S〇p), small outline j-lead package (SOJ), small outline transistor package (s〇T), wide body small outline package (S0W), double column In-line package (DIP) or other similar package product 0. Referring to FIG. 2A, the lead frame strip 2 of the preferred embodiment of the present invention is a strip-shaped plate body, which is usually made of copper, iron, aluminum, and nickel. Or an equivalent metal or alloy, and processed by punching or other equivalent method to form the following detailed structure, wherein the lead frame strip 2 comprises an outer frame 20, a plurality of connecting brackets 21 and 22 and a plurality of wires Rack unit 23. The outer frame 20 and the connecting brackets 21 and 22 are connected to each other. The connecting brackets 201029138 are arranged at intervals in the outer frame 2, and are arranged in the outer frame 20 at intervals. The==22 vertical and vertical crosses are arranged to support and area. The lead frame unit 23 is adjacent to each other in a matrix shape, as shown in FIG. 2A, and the wire leg of the preferred embodiment of the present invention is lightly removed. 2 The lead frame of Xiang feet, but it can also be a lead frame with double HI feet. Each of the lead frame units OQt has a wafer holder

、數個㈣腳部232、數個外引腳部如、數個壞桿 及四個支撐助條235 ’其t_聊部232及外引 腳部233亦可統稱為引腳部。該内引腳部232及外引腳 部如環繞排列在該晶片承座231之至少二側,例如排 列在其四周。該内引腳部232連接在該壩桿Μ#上該 外引腳部233連接在該續桿234及該連結支架21或22 之間。該四個支撐肋條235設置在該晶片承座231之四 個角位置。在本發明中,該四個支撐肋條235係具有實 質相同之構造,不需額外設計如第1A圖所示之現有簧 开&gt;支撐助條136的構造,以供側洗口 165使用。再者, 各該導線架單元23具有一封裝膠體預留區B,在該封 裝膠體預留區B之範園内則具有一澆口接點預留區〇 在本實施例中’該澆口接點預留區C位於該導線架單元 23之封裝膠體預留區B最接近一封裝膠材來源端的角 仅置附近,該角位置通常係指對應於一第一引腳(pin one)的角位置(未標示)。再者,在進行封膠前,該導線 架單元23皆可用以承載至少一晶片24,並利用數個導 11 201029138 ;内弓^他適當方式(例如凸塊)電性連接該晶片24與 該内引腳部232。 請參照第9ft ® _ ' 圖所不,本發明較佳實施例之導線架 u、、,方法係包含下列步驟:提直 包含數個導錄恕留-η 导深朱悚2 - 、-’、卓7^ 23 ;使一熱熔之封裝膠材3沿一 _ 一卩41 /;,L動,該上流道部41延伸在該數個導線架 二上方’使該上流道部41之封裝膠材3經由數個 D分別向下流入-垂直澆口 42 ;以及,使各該 口 42 ~之封裝膠材3分別注入各該導線架單元 23内以分別形成一封裴膠體33。 明參照第2B圖所示,在提供該導線架條2之步驟 後,本發3聽分別在該導線架單元23上放置至少-晶 片24 ’並使該晶片24利用數個導線25電性連接該内 引腳部232。接著,利用轉移模塑成形(transfer_molding ) 方式進行封膠製程。此時,本發明較佳實齡丨之導線架 條2係夾置在-組模具4之間’該模具*是由數個模塊 所、、且成例如由二個模塊所組成,但並不限於此。該模 具4共同形成一料穴40、一上流道部41、數個垂直洗 口 42、數個模穴區43及—活塞44,其中該上流道部 41並具有該數個分流點D以向下連接該數個垂直洗口 42。該垂直洗口 42的延伸方向是垂直於該導線架條2 及上流道部41之水平方向。賴熔之封裝膠材3放置 在該料穴40中’並利用該活塞44將該封裝膠材3壓入 該上流道部41内。在本發財,該模具4之上流道部 201029138 41對應懸空延伸於該數個導線架單元23上方;該分流 點D及垂直洗口 42在垂直方向上對應於該導線架單元 23的洗口接點預留區C 該模穴區43對靡_於該導線竿 單元23之封裝膠體預留區B。再者,該垂直洗口 42較 佳位於該導線架早元23最接近該封裝膠材3來源端的 角位置附近。依據上述的導線架單元23設計,每一該 分流點D是以1:1的比例垂直連接一個導線架單元23, 由於該上流道部41對應懸空延伸於該導線架單元23上 ❿ 方而沒有直接形成在該導線架條2的表面上,因此該導 線架條2可省略設置現有流道支架i2(如第1 a圖所 不)’僅需没置簡早而不佔空間的該連結支架22,因而 能相對增加該導線架單元23的佈局數量及提升該導線 架條2的空間利用率。 請參照第2B及2C圖所示,在完成封膠後及移除該 模具4前,本發明較佳實施例之封裝膠材3將固化形成 ©至少一上流道膠條31、數個垂直澆口膠條32及數個封 裝膠體33。再者,在移除該模具4時,該上流道膠條 31及垂直澆口膠條32可同時與各該導線架單元23的 封裝膠體33分離,其有利於提高該導線架條2的去膠 (dejunk)便利性。接著,請參照第2C及2D圖所示,本 發明進一步進行去膠/去緯(dejunk/trim)等程序,如此即 可製得數個半導體封裝構造的產品(未繪示)。本發明較 佳實施例之半導體封裝構造包含一導線架(亦即該導線 架單元23)、至少一晶片24及一封裝膠體33。該導線 13 201029138 架包含一晶片承座231、數個内引腳232及數個外引腳 233。遠晶片24設置在該晶片承座231上,並利用數個 導線25或其他適當方式(例如凸塊)電性連接於該内引 腳231。該封裝膠體33包覆該晶片承座231、内引腳 232、晶片24及導線25。該封裝膠體33之一上表面具 有一引腳順序指示部331。該引腳順序指示部331較佳 係一凹部,在該引腳順序指示部331之範圍内殘留有一 垂直澆口接點321’其係在去膠期間因由該封裝膠體幻 上移除该垂直洗口膠條32時所形成之殘留不規則斷裂 面構造。該垂直澆口接點321位於該引腳順序指示部 331的凹部内’而不會凸出在該封裝膠體33之上表面 外’因此可省略對該垂直澆口接點321進行磨平的加工 程序’其相對簡化產品加工過程。該引卿順序指示部 331通常位於該導線架(亦即該導線架單元23)具有一第 一引腳(pin one)的角位置(未標示)附近’也就是位於最 接近該封裝膠材3來源端的角位置附近。 如上所述,相較於第1A至1C圖之習用導線架條! 之流道分支模塊100具有該流道支架12與導線架單元 13呈1:1的排列比例設計,造成在該導線架條1上僅能 在有限空間形成有限數量的該導線架單元13等缺點, 第2A至2D圖之本發明之導線架條2的每一導線架單 元23在其封裝膠體預留區B之範圍内具有該澆口接點 預留區C,並利用該上流道部31連結該垂直澆口 32, 以分別由各該導線架單元23之上方進行封膠形成該封 201029138 裝膠體33,由於該上流道部31及垂直澆口 32位於該 導線架條2上方,故不會佔用該導線架條2的空間,因 而可以省略設置現有流道支架12’僅需設置簡單而不 佔空間的連結支架22。例如,在78x250mm的相同尺 寸下’習用導線架條1上最多僅能設置5x14個該導線 架單元13,但本發明之導線架條2上最多則能設置5x2〇 個該導線架單元23❶因此,本發明確實能相對増加該 導線架單元23的佈局數量,進而有效提升該導線架條 Φ 2的空間利用率,大幅增加封膠製程的單位時間產出量 (UPH)大約42.9%或更多’並可相對降低半導體封裝構 造的平均封膠成本。 雖然本發明已以較佳實施例揭露,然其並非用以限 制本發明,任何熟習此項技藝之人士,在不脫離本發明 之精神和範圍内,當可作各種更動與修飾,因此本發明 之保護範圍當視後附之申請專利範圍所界定者為準。 Φ 【圖式簡單說明】 第1A圖·翫用導線架條之局部正視圖。 第iB圖m㈣條在進行封料之局部剖視圖。 第ic圖m線架條在完成轉後之局部正視圖。 第2A圖:本發明較佳實施例之導線架條之局部正視圖。 第邡圖:本發明較佳實施例之導線架條在進行封膠時 之局部剖視圖。 第2C圖:本㈣健實施例之―條在完成封膠後 15 201029138 之局部正視圖。 第2D圖:本發明較佳實施例之半導體封裝體造之剖視 圖。A plurality of (four) leg portions 232, a plurality of outer pin portions, a plurality of broken bars, and four support bars 235', wherein the t_chasing portion 232 and the outer leg portion 233 are also collectively referred to as a pin portion. The inner lead portion 232 and the outer lead portion are circumferentially arranged on at least two sides of the wafer holder 231, for example, arranged around the wafer holder 231. The inner lead portion 232 is connected to the dam rod Μ #, and the outer lead portion 233 is connected between the struts 234 and the joint bracket 21 or 22. The four support ribs 235 are disposed at four angular positions of the wafer holder 231. In the present invention, the four support ribs 235 have substantially the same configuration, and the configuration of the existing spring opening &gt; support bar 136 as shown in Fig. 1A is not required to be used for the side wash port 165. Moreover, each of the lead frame units 23 has an encapsulation reserve area B, and has a gate contact reserved area in the enclosing area of the encapsulation colloid reserved area B. In the embodiment, the gate connection is The point reserved area C is located near the corner of the package colloid reserved area B of the lead frame unit 23 which is closest to the source end of the package adhesive. The angular position generally refers to the angle corresponding to a first pin (pin one). Location (not shown). Moreover, before performing the sealing, the lead frame unit 23 can be used to carry at least one wafer 24, and electrically connected to the wafer 24 by using a plurality of leads 11 201029138; Inner lead portion 232. Please refer to the 9th ft ® _ ' figure. The lead frame u, , the method of the preferred embodiment of the present invention comprises the following steps: straightening includes several guides to stay - η deep-depth Zhu Xi 2 - , -' , Zhuo 7^ 23; a hot-melt encapsulating material 3 is moved along a _ 卩 41 /;, L, the upper flow path portion 41 extends over the plurality of lead frames 2 'encapsulation of the upper flow path portion 41 The glue material 3 flows down into the vertical gates 42 through a plurality of Ds respectively; and the respective package materials 3 of the ports 42 are injected into the lead frame units 23 to form a tantalum body 33, respectively. Referring to FIG. 2B, after the step of providing the lead frame strip 2, the present invention 3 places at least a wafer 24' on the lead frame unit 23, and electrically connects the wafer 24 with a plurality of wires 25. The inner lead portion 232. Next, the encapsulation process is carried out by transfer molding. At this time, the lead frame 2 of the preferred embodiment of the present invention is sandwiched between the set of molds 4. The mold * is composed of a plurality of modules, and is composed of, for example, two modules, but Limited to this. The molds 4 collectively form a cavity 40, an upper flow path portion 41, a plurality of vertical wash ports 42, a plurality of cavity portions 43 and a piston 44, wherein the upper flow path portion 41 has the plurality of flow points D to The plurality of vertical wash ports 42 are connected below. The direction in which the vertical washing port 42 extends is perpendicular to the horizontal direction of the lead frame strip 2 and the upper flow path portion 41. The encapsulating rubber 3 of Lai Rong is placed in the pocket 40 and the encapsulating material 3 is pressed into the upper flow path portion 41 by the piston 44. In the present invention, the flow path portion 201029138 41 of the mold 4 extends over the plurality of lead frame units 23 correspondingly to the dangling; the shunt point D and the vertical shroud 42 correspond to the washing port connection of the lead frame unit 23 in the vertical direction. Point reserved area C The cavity area 43 is opposite to the encapsulation colloid reserved area B of the lead unit 23. Moreover, the vertical wash 42 is preferably located near the angular position of the lead frame 23 closest to the source end of the encapsulant 3. According to the above design of the lead frame unit 23, each of the shunting points D is vertically connected to a lead frame unit 23 in a ratio of 1:1, since the upper flow path portion 41 extends correspondingly to the lead frame unit 23 without being suspended. Directly formed on the surface of the lead frame strip 2, so the lead frame strip 2 can omit the existing flow path bracket i2 (as shown in FIG. 1a), and the connection bracket does not need to be placed early and does not occupy space. 22, thereby increasing the number of layouts of the leadframe unit 23 and increasing the space utilization of the leadframe strip 2. Referring to FIGS. 2B and 2C, after the encapsulation is completed and before the mold 4 is removed, the encapsulant 3 of the preferred embodiment of the present invention will be cured to form at least one upper runner strip 31, and several vertical pourings. The adhesive strip 32 and a plurality of encapsulants 33. Moreover, when the mold 4 is removed, the upper flow strip 31 and the vertical gate strip 32 can be separated from the encapsulant 33 of each lead frame unit 23 at the same time, which is advantageous for improving the lead strip 2 Dejunk convenience. Next, as shown in Figs. 2C and 2D, the present invention further performs a process such as dejunk/trim, so that a plurality of semiconductor package structures (not shown) can be obtained. The semiconductor package structure of the preferred embodiment of the present invention comprises a leadframe (i.e., the leadframe unit 23), at least one wafer 24, and an encapsulant 33. The lead 13 201029138 includes a wafer holder 231, a plurality of inner leads 232, and a plurality of outer leads 233. The remote wafer 24 is disposed on the wafer carrier 231 and is electrically coupled to the inner pin 231 by a plurality of wires 25 or other suitable means (e.g., bumps). The encapsulant 33 covers the wafer holder 231, the inner leads 232, the wafer 24, and the wires 25. One of the upper surfaces of the encapsulant 33 has a pin sequence indicating portion 331. The pin sequence indicating portion 331 is preferably a recessed portion, and a vertical gate contact 321 ′ remains in the range of the pin sequence indicating portion 331 during the stripping process because the vertical washing is phantomly removed by the encapsulating glue. The residual irregular fracture surface structure formed when the rubber strip 32 is formed. The vertical gate contact 321 is located in the recess of the lead sequence indicating portion 331 and does not protrude outside the upper surface of the encapsulant 33. Therefore, the vertical gate joint 321 can be omitted. The program 'is relatively simplified in the product processing process. The lead sequence indicating portion 331 is generally located near the angular position (not labeled) of the lead frame (ie, the lead frame unit 23) having a first pin (that is, located closest to the package adhesive 3) Near the angular position of the source. As mentioned above, compared to the conventional lead frame strips of Figures 1A to 1C! The flow path branching module 100 has a 1:1 arrangement ratio of the flow path bracket 12 and the lead frame unit 13, so that a limited number of the lead frame unit 13 can be formed only in a limited space on the lead frame strip 1. Each of the lead frame units 23 of the lead frame strip 2 of the present invention in FIGS. 2A to 2D has the gate contact reserved area C in the range of its encapsulation-preserving area B, and the upper flow path portion 31 is utilized. The vertical gate 32 is connected to form a seal of the 201029138 by the upper portion of each of the lead frame units 23, and the upper runner portion 31 and the vertical gate 32 are located above the lead frame strip 2, so The space of the lead frame strip 2 is occupied, so that it is possible to omit the provision of the existing flow path bracket 12' only by providing the connection bracket 22 which is simple and does not occupy space. For example, at the same size of 78x250mm, the conventional lead frame strip 1 can only be provided with a maximum of 5x14 of the lead frame unit 13, but the lead frame strip 2 of the present invention can be provided with up to 5x2 of the lead frame unit 23, therefore, The invention can actually increase the layout quantity of the lead frame unit 23, thereby effectively improving the space utilization ratio of the lead frame strip Φ 2, and greatly increasing the unit time output (UPH) of the sealing process by about 42.9% or more. The average sealing cost of the semiconductor package construction can be relatively reduced. The present invention has been disclosed in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. Φ [Simple description of the diagram] Figure 1A shows a partial front view of the lead frame strip. Section iB Figure m (4) is a partial cross-sectional view of the sealing material. Part ic is a partial front view of the m-line frame after the completion of the rotation. 2A is a partial front elevational view of a leadframe strip in accordance with a preferred embodiment of the present invention. Fig. 1 is a partial cross-sectional view showing the lead frame strip of the preferred embodiment of the present invention when it is sealed. Figure 2C: Partial front view of the article (4) of the embodiment of the present invention after the completion of the sealant 15 201029138. Figure 2D is a cross-sectional view showing the fabrication of a semiconductor package in accordance with a preferred embodiment of the present invention.

【主要元件符號說明】 1 導線架條 10 外框 100 流道分支模塊 11 連結支架 12 流道支架 13 導線架單元 131 晶片承座 132 内引腳部 133 外引腳部 134 壩桿 135 支#助條 136 簧形支樓助條 14 晶片 15 導線 16 模具 161 模穴區 162 料穴 163 活塞 164 流道部 165 側澆口 17 封裝膠材 171 流道膠條 172 侧澆口膠條 173 封裝膠體 2 導線架條 20 外框 21 連結支架 22 連結支架 23 導線架單元 231 晶片承座 232 内引腳部 233 外引腳部 234 壩桿 235 支撐助條 24 晶片 25 導線 3 封裝膠材 31 流道膠條 16 201029138[Main component symbol description] 1 lead frame strip 10 outer frame 100 flow path branching module 11 connection bracket 12 flow path bracket 13 lead frame unit 131 wafer holder 132 inner pin portion 133 outer lead portion 134 dam 135 support Article 136 Spring-shaped branch bar 14 Wafer 15 Wire 16 Mold 161 Cavity area 162 Hole 163 Piston 164 Flow path 165 Side gate 17 Package rubber 171 Flow strip 172 Side gate strip 173 Encapsulant 2 Lead frame strip 20 outer frame 21 joint bracket 22 joint bracket 23 lead frame unit 231 wafer holder 232 inner lead portion 233 outer lead portion 234 dam rod 235 support brace 24 wafer 25 wire 3 package adhesive 31 flow strip 16 201029138

32 侧澆口膠條 321 33 封裝膠體 331 4 模具 40 41 上流道部 42 43 模穴區 44 A 分流點 B C 澆口接點預留區 D 垂直澆口接點 引腳順序指示部 料穴 垂直澆口 活塞 封裝膠體預留區 分流點32 side gate strips 321 33 encapsulant colloids 331 4 mold 40 41 upper flow channel portion 42 43 cavity region 44 A split point BC gate joint reserved area D vertical gate contact pin sequence indication part vertical hole pouring Port piston package colloid reserved to distinguish flow points

1717

Claims (1)

201029138 七、申請專利範圍: 1. 一種導線架條,其包含: 數個導線架單元,其係呈矩陣狀相互鄰接排列,且各 該導線架單元具有: 一晶片承座; 數個引腳部,其環繞排列在該晶片承座之至少二 侧;及 四個支禮助條’其設置在該晶片承座之四個角位 ❹ 置; 其中各該導線架單元具有一封裝膠體預留區,在該 封裝膠體預留區之範圍内具有一澆口接點預留區。 2. 如申請專利範圍第1項所述之導線架條,其中該導線 架單元的四個支撐肋條實質相同。 3. 如申請專利範圍第1項所述之導線架條,其中該澆口 接點預留區位於該導線架單元之封裝膠體預留區最 接近一封裝膠材來源端的角位置附近。 ® 4.如申請專利範圍第3項所述之導線架條,其中該最接 近封裝膠材來源端的角位置係該導線架具有一第一 引腳的角位置。 5. 如申請專利範圍第1項所述之導線架條,其中該導線 架單元選自具四排引腳之導線架單元。 6. —種導線架條之封膠方法,其包含: 提供一導線架條,其包含數個導線架單元; 使一熱熔之封裝膠材沿一上流道部流動,該上流道部 18 201029138 延伸在該數個導線架單元上方; 使該上流道部之封裝膠材經由數個分流點分別向下 流入一垂直澆口;以及 使各該垂直澆口内之封裝膠材分別注入各該導線架 單元内,以分別形成一封裝膠體。 、 7·如申請專利範圍第6項所述之導線架條之封膠方 法’其中各該導線架單元包含四個支撐肋條,以支撐 一晶片承座,該四個支撐肋條實質相同。 _ 8.如申請專利範圍第6項所述之導線架條之封膠方 法’其中該垂直澆口位於該導線架單元最接近一封裝 膠材來源端的角位置附近。 9.如申請專利範圍第8項所述之導線架條之封膠方 法’其中該最接近封裝膠材來源端的角位置係該導線 架具有一第一引腳的角位置。 1〇·如申請專利範圍第6項所述之導線架條之封膠方 ❹ 法’其中該上流道部及垂直澆口形成在一組模具上。 U.如申請專利範圍第6項所述之導線架條之封膠方 法’其中在提供該導線架條之步驟後,另包含:分別 在各該導線架單元上放置至少一晶片,並使該晶片電 性連接該導線架單元。 12.如申請專利範圍第6項所述之導線架條之封膠方 法其中該導線架單元選自具四耕弓丨腳之導線架单 元。 —種具有導線架之半導體封裝構造,其包含: 19 201029138 一導線架,其包含一晶片承座、數個内引腳及數個外 引腳; 至少一晶片,其設置在該晶片承座上,並電性連接於 該内引腳;及 一封裝膠體,其包覆該晶片承座、内引腳及晶片,且 該封裝膠體之一上表面具有一引腳順序指示部,在該 引腳順序指示部之範圍内殘留有一垂直澆口接點。 14. 如申請專利範圍第13項所述之具有導線架之半導體 # 封裝構造,其中各該導線架單元包含四個支撐肋條, 以支撐該晶片承座,該四個支撐肋條實質相同。 15. 如申請專利範圍第13項所述之具有導線架之半導體 封裝構造,其中該引腳順序指示部是一凹部。 16. 如申請專利範圍第13項所述之具有導線架之半導體 封裝構造,其中該引腳順序指示部係位於該導線架具 有一第一引腳的角位置附近。 17. 如申請專利範圍第13項所述之具有導線架之半導體 ❿ 封裝構造,其中該導線架單元選自具四排引腳之導線 架單元。 20201029138 VII. Patent application scope: 1. A lead frame strip comprising: a plurality of lead frame units arranged in a matrix adjacent to each other, and each of the lead frame units has: a wafer holder; a plurality of lead portions Surrounded by at least two sides of the wafer holder; and four gift strips disposed at four corner positions of the wafer holder; wherein each of the lead frame units has an encapsulation reserve area, There is a gate contact reserved area within the scope of the encapsulation colloid reserved area. 2. The lead frame strip of claim 1, wherein the four support ribs of the leadframe unit are substantially identical. 3. The lead frame strip according to claim 1, wherein the gate contact reserved area is located near an angular position of the encapsulating colloid reserved area of the lead frame unit closest to a source end of the encapsulating material. The lead frame strip of claim 3, wherein the angular position closest to the source end of the package adhesive material is such that the lead frame has an angular position of a first pin. 5. The lead frame strip of claim 1, wherein the lead frame unit is selected from the group consisting of four rows of lead frame units. 6. A method of encapsulating a lead frame strip, comprising: providing a lead frame strip comprising a plurality of lead frame units; causing a hot melt encapsulating material to flow along an upper flow path portion, the upper flow path portion 18 201029138 Extending over the plurality of lead frame units; causing the encapsulating material of the upper flow path portion to flow downwardly into a vertical gate through a plurality of diverting points; and injecting the encapsulating materials in each of the vertical gates into the respective lead frames Inside the unit to form an encapsulant separately. 7. The method of sealing a leadframe strip as described in claim 6 wherein each of the leadframe units comprises four support ribs for supporting a wafer holder, the four support ribs being substantially identical. 8. The method of sealing a leadframe strip as described in claim 6, wherein the vertical gate is located near an angular position of the leadframe unit closest to a source end of a package of glue. 9. The method of encapsulating a leadframe strip as described in claim 8 wherein the angular position closest to the source end of the encapsulant is such that the leadframe has an angular position of a first pin. 1. The method of sealing a lead frame strip as described in claim 6 wherein the upper flow path portion and the vertical gate are formed on a set of molds. U. The method of sealing a lead frame strip according to claim 6, wherein after the step of providing the lead strip, the method further comprises: placing at least one wafer on each of the lead frame units, and The wafer is electrically connected to the lead frame unit. 12. The method of sealing a lead frame strip according to claim 6, wherein the lead frame unit is selected from the group consisting of a lead frame unit having a four-pronged foot. A semiconductor package structure having a lead frame, comprising: 19 201029138 a lead frame comprising a wafer holder, a plurality of inner leads and a plurality of outer leads; at least one wafer disposed on the wafer holder And electrically connected to the inner lead; and an encapsulant covering the wafer holder, the inner lead and the wafer, and one of the upper surfaces of the encapsulant has a pin sequence indicating portion at the pin A vertical gate contact remains in the range of the sequence indicator. 14. The semiconductor # package construction having a lead frame according to claim 13, wherein each of the lead frame units includes four support ribs for supporting the wafer holder, the four support ribs being substantially identical. 15. The semiconductor package structure having a lead frame according to claim 13, wherein the lead sequence indicating portion is a recess. 16. The semiconductor package structure having a lead frame according to claim 13, wherein the lead sequence indicating portion is located near an angular position of the lead frame having a first pin. 17. The semiconductor package structure having a lead frame according to claim 13, wherein the lead frame unit is selected from the group consisting of four rows of lead frame units. 20
TW98102949A 2009-01-23 2009-01-23 Leadframe strip, molding method thereof and semiconductor package having leadframe TWI419288B (en)

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Publication number Priority date Publication date Assignee Title
TWI646608B (en) * 2016-03-17 2019-01-01 東芝記憶體股份有限公司 Semiconductor device manufacturing method and semiconductor device

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JP3660861B2 (en) * 2000-08-18 2005-06-15 株式会社ルネサステクノロジ Manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI646608B (en) * 2016-03-17 2019-01-01 東芝記憶體股份有限公司 Semiconductor device manufacturing method and semiconductor device

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