TW201027638A - Manufacturing process for a chip package structure - Google Patents

Manufacturing process for a chip package structure Download PDF

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Publication number
TW201027638A
TW201027638A TW098101390A TW98101390A TW201027638A TW 201027638 A TW201027638 A TW 201027638A TW 098101390 A TW098101390 A TW 098101390A TW 98101390 A TW98101390 A TW 98101390A TW 201027638 A TW201027638 A TW 201027638A
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TW
Taiwan
Prior art keywords
layer
conductive layer
patterned
solder resist
wafer
Prior art date
Application number
TW098101390A
Other languages
Chinese (zh)
Other versions
TWI393193B (en
Inventor
Geng-Shin Shen
Chun-Ying Lin
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW098101390A priority Critical patent/TWI393193B/en
Publication of TW201027638A publication Critical patent/TW201027638A/en
Application granted granted Critical
Publication of TWI393193B publication Critical patent/TWI393193B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

Description

201027638 ------〇02 16667-0P2twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片封裝結構的製程，且特別是 有關於一種較薄的晶片封裝結構的製程。 【先前技術】 在半導體產業中’積體電路（integrated circuits，ic ) • 的製程主要分為三個階段：積體電路設計、積體電路的製 作及積體電路的封裝。 在積體電路的製程中，晶片係.經由晶圓(wafer)製作、 電路設計以及切割晶圓等步驟而完成。晶圓具有一主動 面，其為有多個主動元件形成於其上的表面。於形成晶圓 内的積體電路之後，在晶圓的主動面上形成多個接墊，以 使由切割晶圓所形成的晶片可透過接塾電性連接至承載 器。承載器可為一導線架或一線路板。晶片經由打線接合 (wire bonding)或覆晶接合(flip chip bonding)等方式電性連 接至承載器(carrier)，其中晶片的接墊電性連接至承載器的 接墊，以形成一晶片封裝結構。 一般而言’習知的線路板製程都必需用到核心介電 層’而圖案化線路層與圖案化介電層以全加成法（fully additive process )、半加成法（semi_additive process )、減 成法（subtractive process)或是其他適合的方法交替地堆 豐於核心介電層上。由前述可知，核心介電層的厚度為線 路板的總厚度的主要部分。因此，若無法有效地降低核心 4 yu02 16667-0P2tw£doc/n 201027638 介電層的厚度，勢必不利於降低晶片封裳結構的總厚度。 【發明内容】 較薄雖結制⑼，料製得厚度 先，一種晶片封裝結構的製程如下所述。首 ί，=二電層與—圖案化防焊層圖案化防焊 層其中圖案化導電層具有多個第α， 圖上。接著，接合多個晶片至圖案= 層二與 =叫峨貫至 1形成至少一封裝膠體，以包覆道二 化防焊層、晶片以及導線。铁導電層、圖案 導電層與圖案化防焊層。…、刀^封裝膠體、圖案化 魯 防焊層在=::例:先提==層與圖案化 成一防痒層於導雷芦t ，、導電層。接著，形 圖案化導電相形成圖案化出心導電層。之後， 防焊層先提::案=層與圖案化 層，其令圖案化防焊層暴露出部分導電層。^案 ρυ02 16667-〇P2twf.d〇c/n 201027638 圖案化導電層以形成圖案化導電層。 在本發明之一實施例中，提供圖案化導電層與圖案化 防焊層的方法如下所述。首先，提供一導電層。然後了形 成一防焊層於導電廣上。之後，圖案化導電層以^成圖案 化導電層。然後，圖案化防焊層以形成圖案化防燁層，^ 中圖案化防焊層暴露出部分圖案化導電層。 曰八 ❹ 在本發明之-實施例中，提供圖案化導電層與圖案化 法如下所述。首先，提供一防焊層。餘，形 焊層上。然後，圖案化導電層以形成圖案 之後，圖案化防焊層以形成圖案化防焊層，盆 中圖案化防焊層暴露出部分圖案化導電層。 、 層上在本發明之一實施例中，多個引聊ς成於圖案化導電 在本發明之一實施例中，多個第__ 防焊層上，其中第二開口暴露出各成於圖案化 分圖案化導電層。 的局部區域以及部 在本發明之一實施例中，多個第二 防焊層上。〜開口形成於圖案化 在本發明之—實施例中，晶片封摄 於各第三開口中形成—外部電極，且^^的製程更包括 口電性連接至圖案化導電層。 卜邵電極透過第三開 在本發明之—實施例中，晶片封 形成-黏著層於晶片與圖案化導電層=構的製程更包括 在本發明之—實施例中，黏著 曰芍一 Β階黏著層。 6 方υ02 16667-0P2twf.doc/n 201027638 的-f謝’BPt轉層縣形成於晶片 在本發明之一實施例中，在 之前，B階黏著層形成於圖案化導以:至圖案化導電層 在本發明之-實施例中，封裳膠 在本發明之一實施例中，封裝膠體覆$刀曰曰片。 基於上述’本發明之晶片封裝結構的製程可在不需用 之晶片封裝結構的製程所製得的晶片封發明 習4口夕旦ti封壯^θ A 裝、〜構的厚度小於 :全面包覆晶片 ' 6¾ ^ ❿ ❹ 到核心介電層的情況下，製作出晶片封 之晶片封裝結構的製程所製 x、、、°構’ 習知之晶片封裝結構的厚度 下文特 為=本發1上述舰和優靴㈣顯易懂， 舉實施例，亚配合所附圖式作詳細說明如下。 【實施方式】 本發明的實施例可參照對應的圖示，且 中標號相狀處為彼此相_她。 、圖不或為述 圖1A至圖1H為本發明—, 製程剖面圖。請參照圖1A，提供_導電層結構的 防焊層m，其中導電層11〇具有相對的一第二 與一第二表面114，®案化防焊層12G具有多個第 122與多個第三開口 m。此外，圖案化 =201027638 ------〇02 16667-0P2twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to a process for a chip package structure, and more particularly to a thinner wafer The process of packaging the structure. [Prior Art] In the semiconductor industry, the process of 'integrated circuits (ic) is mainly divided into three stages: integrated circuit design, integrated circuit fabrication, and integrated circuit packaging. In the process of the integrated circuit, the wafer system is completed by steps of wafer fabrication, circuit design, and wafer dicing. The wafer has an active surface that is a surface having a plurality of active elements formed thereon. After forming the integrated circuit in the wafer, a plurality of pads are formed on the active surface of the wafer, so that the wafer formed by the dicing wafer is electrically connected to the carrier through the interface. The carrier can be a lead frame or a circuit board. The wafer is electrically connected to a carrier by wire bonding or flip chip bonding, wherein the pads of the wafer are electrically connected to the pads of the carrier to form a chip package structure. . In general, the conventional circuit board process requires the use of a core dielectric layer, and the patterned circuit layer and the patterned dielectric layer are fully additive process, semi-additive process, Subtractive processes or other suitable methods are alternately stacked on the core dielectric layer. As can be seen from the foregoing, the thickness of the core dielectric layer is a major portion of the total thickness of the circuit board. Therefore, if the thickness of the core layer is not effectively reduced, it is not conducive to reducing the total thickness of the wafer sealing structure. SUMMARY OF THE INVENTION Thinner, although finished (9), the thickness of the material is made. First, the process of a chip package structure is as follows. The first ί, = two electrical layers and the patterned solder mask patterned solder mask have a patterned conductive layer having a plurality of alpha, on the figure. Next, a plurality of wafers are bonded to the pattern = layer 2 and = to form at least one encapsulant to encapsulate the solder resist layer, the wafer, and the wires. Iron conductive layer, patterned conductive layer and patterned solder mask. ..., knife ^ encapsulation colloid, patterning Lu solder mask in =:: Example: first mention == layer and pattern into an anti-itch layer in the lead thunder, t, conductive layer. Next, the patterned conductive phase forms a patterned core conductive layer. Thereafter, the solder mask first mentions: a layer = a patterned layer that exposes the patterned solder mask to a portion of the conductive layer. ^案ρυ02 16667-〇P2twf.d〇c/n 201027638 The conductive layer is patterned to form a patterned conductive layer. In one embodiment of the invention, a method of providing a patterned conductive layer and a patterned solder resist layer is as follows. First, a conductive layer is provided. A solder mask is then formed over the conductive area. Thereafter, the patterned conductive layer is patterned into a conductive layer. Then, the solder resist layer is patterned to form a patterned anti-corrugated layer, and the patterned solder resist layer exposes a portion of the patterned conductive layer. ❹ ❹ In the embodiment of the present invention, the patterned conductive layer and the patterning method are provided as follows. First, a solder mask is provided. I, on the solder layer. Then, after patterning the conductive layer to form a pattern, the solder resist layer is patterned to form a patterned solder resist layer, and the patterned solder resist layer in the pot exposes a portion of the patterned conductive layer. In one embodiment of the present invention, a plurality of quotations are formed in patterned electrical conduction. In one embodiment of the present invention, a plurality of __ solder resist layers are exposed, wherein the second openings are exposed to each other. The patterned sub-patterned conductive layer. The partial regions and portions are in a plurality of second solder mask layers in one embodiment of the invention. The opening is formed in the patterning. In the embodiment of the invention, the wafer is encapsulated in each of the third openings to form an external electrode, and the process further includes electrically connecting to the patterned conductive layer. The second electrode is in the embodiment of the present invention, and the process of forming a wafer-forming layer on the wafer and the patterned conductive layer is further included in the embodiment of the present invention. Adhesive layer. 6 υ 16 16 16 16 16 16 16 16 16 16 BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP BP Layer In the embodiment of the present invention, in one embodiment of the invention, the sealant is coated with a gel-coated sheet. The thickness of the wafer package structure of the present invention can be obtained by the process of the wafer package structure which is not required, and the thickness of the wafer package is less than: the full package is less than: In the case where the wafer is covered with a core dielectric layer, the process of fabricating the wafer package structure of the wafer package is made by x, and the thickness of the conventional chip package structure is as follows: The ship and the boots (4) are easy to understand, and the embodiments are described in detail below with reference to the drawings. [Embodiment] Embodiments of the present invention can refer to corresponding illustrations, and the reference numerals are in phase with each other. FIG. 1A to FIG. 1H are cross-sectional views showing the process of the present invention. Referring to FIG. 1A, a solder resist layer m of a conductive layer structure is provided, wherein the conductive layer 11 has an opposite second and a second surface 114, and the solder resist layer 12G has a plurality of 122th and a plurality of Three openings m. In addition, patterning =

J電層no的第—表面112上，且圖案 U 出部分第-表面m。在—較佳的實施例中 = no (brown oxidati〇n) 201027638⑽ 16667-0P2tw£doc/n oxidation)製程，以增加導電層11〇的表面粗糙度。如此， 可提升導電層110與圖案化防焊層12〇的接合度。 在本實施例中，形成圖案化防焊層12〇的方法為貼附 一 B階膠膜（Bstagedfilm)於導電層π〇的第一表面112 上’其中Β階賴亦為-防焊層，且此固態狀的防焊層於 =附至導電層11G之前或之後可被_化㈣彡賴案化防 焊層120。在一實施例中，圖案化防焊層12〇的形成方式On the first surface 112 of the J electrical layer no, and the pattern U is a portion of the first surface m. In the preferred embodiment, = no (brown oxidati〇n) 201027638 (10) 16667-0P2 tw / doc / n oxidation) process to increase the surface roughness of the conductive layer 11 。. In this way, the degree of bonding between the conductive layer 110 and the patterned solder resist layer 12 can be improved. In this embodiment, the method of forming the patterned solder resist layer 12 is to attach a B-stage film (Bstaged film) on the first surface 112 of the conductive layer π〇, wherein the layer is also a solder resist layer. And the solid solder resist layer can be smear (four) to the solder resist layer 120 before or after being attached to the conductive layer 11G. In an embodiment, the patterning of the solder resist layer 12 is formed.

=先於導電層U0的第一表面112上塗佈一液態防焊材 如B階液態防焊材料），然後，固化與圖案化此液 先、防焊材料，以形成圖案化防焊層120，固化方式可藉由 力…或是照射紫外光。在本實施例中，圖案化防焊層 可為B階膠膜。再者，圖案化防嬋層12〇可為一咸光性 的B階膠膜。 〜Applying a liquid solder resist such as a B-stage liquid solder resist material to the first surface 112 of the conductive layer U0, and then curing and patterning the liquid first, solder resist material to form the patterned solder resist layer 120. The curing method can be done by force... or by ultraviolet light. In this embodiment, the patterned solder mask layer may be a B-stage film. Furthermore, the patterned anti-mite layer 12 can be a salty B-stage film. ~

，著’請參闕1B ’叫光顯影以及㈣的方式圖 ^導雷Ϊ層11G，以形成—具有多個第—開口 UGa的圖案 118 " 11〇> ，其中圖案化導電層110，具有多個引腳 八第’_且圖案化防焊層120暴露出圖案化導電層110,的部 圖索各表面112。換言之，形成於部分第一表面112上的 是，、J烊層120定義出多個第—接墊116。值得注意的 案化成圖案化導電層11()，與圖案化防焊層120的圖 中，^^的順序並非用以限定本發明。在一較佳實施例 ιΐό進行電鍍製程（piatingpr〇cess)，以於第一接墊 為-领成—電錢導電層（未繪示）。前述電鍍導電層可 ’’鎳金疊層或是其他適合的金屬層。 8 20102763 8ϋϋ2 16667-0P2twf.doc/n 然後，清參照圖1C，多個晶片130黏著至圖宰化導 電層110’ ’然後’形成多條貫穿第一開口 1 l〇a的導線15〇， 以連接第一接塾116與晶片130，其中各晶片go具有一 主動面132、一相對於主動面132的背面134以及多個配 置於主動面132上的第二接塾136，且一第二開口 122暴 露出這些弟一接塾136。各晶片130藉由一配置於晶片130 與圖案化導電層110’之間的黏著層140黏著至圖案化導電 層 110,。 、 在本實施例中，導線150是以打線接合的方式形成， 且各導線150電性連接一第一接墊116與一第二接墊 。導線150例如為金導線。 在本實施例中，黏著層140例如為一 Β階黏著層。Β 階黏著層可為ABLESTIK的8008或8008ΤΗ。此外，Β階 黏者層亦可為ABLESTIK的6200、6201或6202或 HITACHI Chemical CO” Ltd.提供的 SA-200-6、 SA-200-10。在本發明之一實施例中，3階黏著層14〇形成 ❹ 在晶圓的主動面。當晶圓被切割時，可形成多個晶片13〇, 且晶片130具有位於其主動面132上的黏著層14〇。因此， Β階黏著層140有利於量產。此外，Β階黏著層14〇的形 成方式包括旋轉塗佈、印刷或是其他適合的製程。更明確 而言，黏著層140是形成在晶片13〇的主動面132上。具 體而。，可先k供一晶圓，其具有多個成陣列排列的晶 咖,然後，於晶片13G的主動面132上形成—二階黏著層， 並藉由加熱或是照射紫外光的方式使此二階黏著層部分固 16667-0P2twf.doc/n 20102763 8 nn ▲ 一 — v v w *^002 化 =形成B階黏著層另外，在晶片13G黏著至 案化導電層110,之前，B 化導電層110’上 圖 階黏著層140可預先形成在圖案 在本貝施例中’在晶片n〇黏著至圖案化導電層⑽ 或者衫-封裝膠體包覆晶片m之後，b階黏著 才兀王固化。在其他實施例中，更可對B階黏著層 140進行—後續的固化製程，使其完全固化。, "Please refer to 1B" called light development and (4) mode diagram to guide the Thunder layer 11G to form - a pattern 118 "11〇> having a plurality of first opening UGA, wherein the conductive layer 110 is patterned, A plurality of pins VIII' and the patterned solder mask 120 exposes the patterned conductive layer 110, the portions of the surface 112. In other words, formed on a portion of the first surface 112, the J 烊 layer 120 defines a plurality of first pads 116. It is noted that the patterning of the conductive layer 11() and the patterning of the solder resist layer 120 are not intended to limit the invention. In a preferred embodiment, pi is subjected to a plating process so that the first pad is a lead-electric conductive layer (not shown). The electroplated conductive layer can be a nickel-gold laminate or other suitable metal layer. 8 20102763 8ϋϋ2 16667-0P2twf.doc/n Then, referring to FIG. 1C, a plurality of wafers 130 are adhered to the patterned conductive layer 110'′′ and then a plurality of wires 15 贯穿 passing through the first opening 1 l〇a are formed to The first interface 116 and the wafer 130 are connected, wherein each wafer go has an active surface 132, a back surface 134 opposite to the active surface 132, and a plurality of second interfaces 136 disposed on the active surface 132, and a second opening 122 exposed these brothers to pick up 136. Each wafer 130 is adhered to the patterned conductive layer 110 by an adhesive layer 140 disposed between the wafer 130 and the patterned conductive layer 110'. In this embodiment, the wires 150 are formed by wire bonding, and each of the wires 150 is electrically connected to a first pad 116 and a second pad. The wire 150 is, for example, a gold wire. In the present embodiment, the adhesive layer 140 is, for example, a stepped adhesive layer. The 黏 order adhesive layer can be 8008 or 8008 ABLE of ABLESTIK. In addition, the layer of the adhesive layer may also be SA2000-1, 60-1, 62020 or 6202 of ABLESTIK or SA-200-6, SA-200-10 provided by HITACHI Chemical CO" Ltd. In one embodiment of the present invention, the 3rd order adhesive The layer 14 is formed on the active side of the wafer. When the wafer is diced, a plurality of wafers 13 可 can be formed, and the wafer 130 has an adhesive layer 14 位于 on the active surface 132. Therefore, the gradual adhesion layer 140 In addition, the formation of the crucible adhesive layer 14 turns includes spin coating, printing or other suitable processes. More specifically, the adhesive layer 140 is formed on the active surface 132 of the wafer 13 . Alternatively, a wafer can be provided for a plurality of wafers, and then a plurality of wafers arranged in an array are arranged, and then a second-order adhesive layer is formed on the active surface 132 of the wafer 13G, and is heated or irradiated with ultraviolet light. The second-order adhesive layer portion is solid 16667-0P2twf.doc/n 20102763 8 nn ▲ one - vvw *^002 = forming a B-stage adhesive layer. Further, before the wafer 13G is adhered to the conductive layer 110, the B-conductive layer 110 is formed. 'The upper layer of the adhesive layer 140 can be formed in advance in the pattern in the present embodiment' After the wafer n is adhered to the patterned conductive layer (10) or the shirt-package colloid coated wafer m, the b-stage adhesion is cured. In other embodiments, the B-stage adhesive layer 140 may be subjected to a subsequent curing process. Make it fully cured.

㈣接著，明參照圖1〇，—封裝膠體160包覆圖案化導 :曰110、圖案化防焊層120、晶片13〇與導線15〇。封 裝膠體160的材質例如為環氧樹脂（ep〇x声in)。然後， 分別於第三開口 m中形成多個外部電極17G，以電性連 接圖案化導電層11G’。外部電極m例如為鲜球。 請參照® 1E，相較於_出是形成封裝膠體16〇來包 覆圖案化導電層110、圖案化防焊層12Q、晶片13〇與導 線150,圖1E是形成多個封裝膠體16〇，來包覆圖案化導電 層110，、圖案化防焊層120、晶片130與導線15〇。 月參照圖1F與圖1G，圖id或圖1E中的結構經單顆 化（singularize)之後可分別形成多個晶片封裝結構1〇〇(如 圖1F所示）或多個晶片封裝結構1〇〇，（如圖1G所示）， 其中單顆化的製程包括一衝壓製程（punch pr〇cess)或一 切割製程（sawing process )。 在本實施例中，封裝膠體160是部分包覆晶片13〇且 暴露出晶月130的背面134，在其他實施例中，封裝膠體 160亦可完全包覆晶片130(如圖所示）。 201027638 *-------f〇〇2 I6667-0P2twf.doc/n Φ 如圖IF所示，本實施例之晶片封裝結構100主要包 括一圖案化導電層110’、一圖案化防谭層12〇、一晶片 130、夕條導線150與一封裝膠體160。圖案化導電層11〇， ，相對的-第—表面112與—第二表面114。圖日案化防 焊層120配置於第一表面112。圖案化防焊層⑽暴露出 部分的第-表面112。晶片13G配置於圖案化導電層ιι〇, 上^•線150電性連接至晶# 13〇以及由圖案化防谭層⑽ f暴露出的圖案化導電層11〇,。封裝膠體16〇包覆圖案化 導電層11G’、圖案化防焊層晶片m以及導線⑼。 綜上所述，相較於習知之晶片封裝結構的製程， ^製程可製得無如介電層且厚錄小的晶片封裝二 構。因此，本發明可降低製作成本並提升產量。 =然本翻已以實_賊如上，财並細以限定 屬技術領域中具有通常知識者，在不脫離 圍内，當可作些許之更動與潤飾，故本 "”杨11當視後附之冑請專鄕騎界定者為準。 【圖式簡單說明】 製程圖1Η為本發明—實施例之晶片封裝結構的 【主要元件符號說明】 100、100’ ：晶片封裝結構 導電層 201027638 u02 16667-0P2twf.doc/n 110’ ：圖案化導電層 110a :第一開口 112 :第一表面 114 :第二表面 116 :第一接墊 118 :引腳 120:圖案化防焊層 122 :第二開口 • 124 :第三開口 130 :晶片 132 :主動面 134 :背面 136 :第二接墊 140 :黏著層 150 :導線 160、160’ ：封裝膠體 ❿ 170:外部電極 12(4) Next, referring to FIG. 1A, the encapsulant 160 is coated with a patterned conductive layer: 曰110, patterned solder resist layer 120, wafer 13 〇 and wire 15 〇. The material of the encapsulant 160 is, for example, epoxy resin (ep〇x sound in). Then, a plurality of external electrodes 17G are formed in the third openings m to electrically connect the patterned conductive layers 11G'. The external electrode m is, for example, a fresh ball. Referring to FIG. 1E, the patterned conductive layer 110, the patterned solder resist layer 12Q, the wafer 13A and the wires 150 are coated in comparison with the NMOS, and FIG. 1E is formed by forming a plurality of encapsulants. The patterned conductive layer 110 is patterned, and the solder resist layer 120, the wafer 130, and the wires 15 are patterned. Referring to FIG. 1F and FIG. 1G, the structure in FIG. 1D or FIG. 1E may be separately formed into a plurality of chip package structures 1 (as shown in FIG. 1F) or a plurality of chip package structures after singularizing. 〇, (as shown in FIG. 1G), wherein the singulation process includes a punch pr〇cess or a sawing process. In the present embodiment, the encapsulant 160 is partially covered with the wafer 13 and exposes the back side 134 of the crystal 130. In other embodiments, the encapsulant 160 may also completely encapsulate the wafer 130 (as shown). 201027638 *-------f〇〇2 I6667-0P2twf.doc/n Φ As shown in FIG. IF, the chip package structure 100 of the present embodiment mainly includes a patterned conductive layer 110' and a patterned anti-tan. The layer 12A, a wafer 130, the ridge wire 150 and an encapsulant 160 are provided. The patterned conductive layer 11〇, the opposite-first surface 112 and the second surface 114. The patterned solder resist layer 120 is disposed on the first surface 112. The patterned solder mask (10) exposes a portion of the first surface 112. The wafer 13G is disposed on the patterned conductive layer ιι, and the upper line 150 is electrically connected to the crystal #13〇 and the patterned conductive layer 11〇 exposed by the patterned anti-tan layer (10) f. The encapsulant 16 is coated with a patterned conductive layer 11G', a patterned solder mask wafer m, and a wire (9). In summary, the process can produce a wafer package structure that is as thin as a dielectric layer and has a small thickness compared to the conventional chip package structure process. Therefore, the present invention can reduce the manufacturing cost and increase the yield. = Although the book has been turned into a real _ thief as above, the wealth and fine to limit the general knowledge of the technical field, without leaving the circle, when you can make some changes and retouch, so this " Yang 11 after the sight附 界定 鄕 。 【 【 【 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 制 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 16667-0P2twf.doc/n 110': patterned conductive layer 110a: first opening 112: first surface 114: second surface 116: first pad 118: pin 120: patterned solder mask 122: second Opening • 124: third opening 130: wafer 132: active surface 134: back surface 136: second pad 140: adhesive layer 150: wires 160, 160': encapsulant ❿ 170: external electrode 12

Claims (1)

W2 16667-0P2twf.doc/n 201027638 七、申謗專利範®: ι· -種晶；ί封裝結構的製程，包括： 提供一圖案化導電層與—圖案化 化導電層具有多個第—開：二、广圖索 案化導電層上，· ㈣化防~層配置於該圖 兮闰f/合多個晶片至該_化導電層上，以使該此曰 ^化防谭層分別配置於該圖案化導電層的 藉由多條導線電性連接誃此s 牵化二屏〆封裝膠體’以包覆該圖案化導電層：：’ 案化防知層、該些晶片以及該些導線·以及胃讀圖 刀割該封裝膠體、該圖案化導電層與_案化防淳 ❹ 層 程 括 ^如申請專利範圍第i項所述之晶片封裝 八愤供該圖案化導電層與該圖案化防焊層 提供一導電層； 形成一防焊層於該導電層上； 圖案化該防蟬層以形成該圖案化防焊 化防焊層暴露㈣分料電層；歧 ί这圖案 圖案化該導電層以形成該圖案化導電層。 申叫專利範圍第1項所述之晶片封裝結構的製 ，/、中提供該圖案化導電層與該圖案化防焊層的方法^ 13 201027638 x^uv〇u^002 16667-0P2twf.doc/n 括： 提供一防焊層； 形成一導電層於該防焊層上； 圖案化該防焊層以形成該圖案化焊 化防谭層暴露出部分該導電層；以及 Ί該圖案 圖案化該導電層以形成該圖案化導電層。 Ο ❿ 招^如申請專利範圍第1項所述之晶片封裝結構的製 ^ 其中提供該随化導電層與該_化防焊層的方法包 提供一導電層； 形成一防焊層於該導電層上； 圖案化該導電層以形成該圖案化導電層；以及 圖案化該防焊層以形成關案化 化防焊層暴露出部分該圖案化導電層。層〃中案 請專利項所述之晶片封裝結 ^ 其仏供該_料絲與該®案化晴層的方法包 提供一防焊層； 形成一導電層於該防焊層上丨 圖案化該導電相形成該随化導電層；以及 ，案化該防焊層以形成該圖案化防焊層，其中 方焊層暴露出部分該圖案化導電層。 〃 矛。，^由請專利範圍第1項所述之晶片封展結構的製 王"中夕個引腳形成於該圖案化導電層上。 201027638 n u -----VJ002 16667-0P2twf.doc/n 7·如申請專利範圍第巧所述之晶片封農結構 权，其中多個第二開口形成於該圖案化防焊層上，其 些第二開口暴露出部分該圖案化導電層以及各該曰 = 部區域。 日日乃的局 8. 如申請專利範圍第i項所述之晶片封裳結構的製 程，其中多個第三開口形成於該圖案化防焊層上。 9. 如申請專利範圍第δ項所述之晶片封裳結構的製 ❹ ❹ 程，更包括： 、 於各該第三開口中形成一外部電極，且該些外部電極 透過該些第三開口電性連接至該圖案化導電層。 f ^ ί申請專利範圍第1項所述^晶片雜結構的製 形成一黏著層於該些晶片與該圖案化導電層之間。 製程1乂 ig項所述之晶片龍結構的 表枉关τ通黏考層為—B階黏著層。 12.如申請專利範圍第u項所述之晶片封裝結 製程’其巾該BP皆黏著層預先形成於該晶片的—主動面上。 ,I3·如申請專利範圍第11項所述之晶片封裝結構的 製程’其巾在該晶黏著至該圖案化導電狀前，該 黏著層形成於該圖案化導電層上。 白 14·如申請專利範圍第丨項所述之晶片封裝結構 程，其中該封裝膠體包覆部分該晶片。 15_如申請專利範圍第丨項所述之晶片封裝結構 程，其中該封裝膠體全面包覆該晶片。 15W2 16667-0P2twf.doc/n 201027638 VII. Application for Pharmacy: ι· - seed crystal; 封装 package structure process, including: providing a patterned conductive layer and - patterned conductive layer having multiple first-on : 2. On the broad-formed conductive layer, (4) the layer is placed on the pattern 兮闰f/multiple wafers to the _-conducting layer, so that the 防 化 防 防 layer is separately arranged The patterned conductive layer is electrically connected by a plurality of wires, and the second screen package encapsulant is coated to coat the patterned conductive layer: the case-preventing layer, the wafers, and the wires And the stomach-reading knife cuts the encapsulating colloid, the patterned conductive layer, and the patterned encapsulation layer, such as the wafer package described in claim i, for the patterned conductive layer and the pattern The solder resist layer provides a conductive layer; forming a solder resist layer on the conductive layer; patterning the anti-corrugated layer to form the patterned solder resist solder resist layer exposing (4) the sub-electric layer; The conductive layer forms the patterned conductive layer. The method for providing the patterned conductive layer and the patterned solder resist layer is provided in the manufacture of the chip package structure described in the first paragraph of the patent scope. 13 13 201027638 x^uv〇u^002 16667-0P2twf.doc/ n: providing a solder resist layer; forming a conductive layer on the solder resist layer; patterning the solder resist layer to form the patterned solder resist layer to expose a portion of the conductive layer; and patterning the pattern A conductive layer to form the patterned conductive layer. The method of providing a wafer package structure according to claim 1, wherein the method for providing the passivation conductive layer and the method for providing a solder resist layer provides a conductive layer; forming a solder resist layer on the conductive layer And patterning the conductive layer to form the patterned conductive layer; and patterning the solder resist layer to form a patterned solder resist layer to expose a portion of the patterned conductive layer. The chip package described in the patent application provides a solder resist layer for the method package of the wire and the clear layer; forming a conductive layer on the solder resist layer to be patterned The conductive phase forms the compliant conductive layer; and the solder resist layer is patterned to form the patterned solder resist layer, wherein the square solder layer exposes a portion of the patterned conductive layer. 〃 spear. ^, the king of the wafer sealing structure described in the first paragraph of the patent scope is formed on the patterned conductive layer. 201027638 nu -----VJ002 16667-0P2twf.doc/n 7. The wafer sealing structure right as described in the patent application scope, wherein a plurality of second openings are formed on the patterned solder resist layer, The second opening exposes a portion of the patterned conductive layer and each of the 曰= regions. The process of the wafer sealing structure of claim i, wherein a plurality of third openings are formed on the patterned solder mask. 9. The manufacturing process of the wafer sealing structure of claim δ, further comprising: forming an external electrode in each of the third openings, and the external electrodes are electrically transmitted through the third openings Sexually connected to the patterned conductive layer. The fabrication of the wafer dummy structure described in claim 1 of the invention is to form an adhesive layer between the wafers and the patterned conductive layer. The process of the wafer dragon structure described in the 1 ig process is a B-stage adhesive layer. 12. The wafer package process of claim 5, wherein the BP adhesion layer is preformed on the active surface of the wafer. I3. The process of the wafer package structure of claim 11, wherein the adhesive layer is formed on the patterned conductive layer before the crystal is adhered to the patterned conductive layer. The wafer package structure of the invention of claim 1, wherein the encapsulant covers a portion of the wafer. The wafer package structure of claim 2, wherein the encapsulant completely covers the wafer. 15
TW098101390A 2009-01-15 2009-01-15 Manufacturing process for a chip package structure TWI393193B (en)

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