201027636 —wv„vj〇〇3 I6667-0P3twf.doc/n 六、發明說明： 【發明所屬之技術領域】 有關於-種較薄的晶片的製程，且特別是 【先前技術】 在半導體產業中，_電路（integmted circuits，1C) 鲁❸製程主要分為三個階段：積體電路設計、積體電路的 作及積體電路的封裝。 在積體電路的製程中，晶片係經由晶圓(wafer)製作、 電路設計以及切割晶圓等步驟而完成。晶圓具有一主動 面，其為有多個主動元件形成於其上的表面。於形成晶圓 内的積體電路之後，在晶圓的主動面上形成多個接墊，以 使由切割晶圓所形成的晶片可透過接墊電性連接至承载 器。承載器可為一導線架或一線路板。晶片經由打線接合 ❹ (wire bonding)或覆晶接合(flip咖口 bonding)等方式電性連 接至承載器(carrier)，其中晶片的接墊電性連接至承載器的 接墊，以形成一晶片封裝結構。 一般而言，習知的線路板製程都必需用到核心介電 層，而圖案化線路層與圖案化介電層以全加成法（fully additive process)、半加成法（semi-additive process)、減 成法（subtractive process)或是其他適合的方法交替地堆 疊於核心介電層上。由前述可知，核心介電層的厚度為線 路板的總厚度的主要部分。因此，若無法有效地降低 4 201027636 u>_w〇〇3 16667-〇p3twfd〇c/n 介電層的厚度，勢必不利於降低晶片封裝結構的總厚度。 【發明内容】 製程，其可製得厚度 *本發明&供一種晶片封裝結構的 較薄的晶片封裝結構。 ，發明提出-種晶片封震結構的製程如下所述。首201027636 —wv„vj〇〇3 I6667-0P3twf.doc/n VI. Description of the Invention: [Technical Fields of the Invention] Processes relating to thinner wafers, and in particular [Prior Art] In the semiconductor industry, Integmted circuits (1C) The reckless process is mainly divided into three stages: integrated circuit design, integrated circuit, and integrated circuit packaging. In the integrated circuit process, the wafer is waferd (wafer) The fabrication, the circuit design, and the step of cutting the wafer are completed. The wafer has an active surface, which is a surface on which a plurality of active components are formed. After forming an integrated circuit in the wafer, on the wafer A plurality of pads are formed on the active surface, so that the wafer formed by the dicing wafer can be electrically connected to the carrier through the pad. The carrier can be a lead frame or a circuit board. The wafer is bonded by wire bonding. Or a flip-chip bonding or the like electrically connected to a carrier, wherein the pads of the wafer are electrically connected to the pads of the carrier to form a chip package structure. Known The core dielectric layer is required for the board process, and the patterned circuit layer and the patterned dielectric layer are fully additive process, semi-additive process, and subtractive method. Process) or other suitable method is alternately stacked on the core dielectric layer. As can be seen from the foregoing, the thickness of the core dielectric layer is a major part of the total thickness of the circuit board. Therefore, if it cannot be effectively reduced 4 201027636 u>_w 〇〇 3 16667-〇p3twfd〇c/n The thickness of the dielectric layer is not necessarily conducive to reducing the total thickness of the chip package structure. SUMMARY OF THE INVENTION Process, which can produce thickness * The present invention & Thinner chip package structure. The invention proposes that the process of the wafer seal structure is as follows.
ί化圖Γ導ί層與—第—圖案化防焊層，其中圖 圖牵化多個Ϊ —開口 ’第—圖案化防悍層配置於 :曾 s上。接著，形成一第二圖案化防焊層於圖案 广電層上，以使第—圖案化防焊層與第二圖案化防焊層 1配置於圖案化導電層的相對二表面上。然後，接合多 個曰曰片至第—圖案化防焊層上，以使第—圖案化防焊層位 ^晶片與㈣化導電層之間。之後’藉由多條導線電性連 接晶片至圖案化導電層，其中導線貫穿圖案化導電層的第 開口。接著，开》成至少一封裝膠體，以包覆圖案化導電 層、第—圖案化防焊層、第二圖案化防焊層、晶片以及導 線。然後，分離封裝膠體、第一圖案化防焊層與第二圖案 化防焊層。…^ 在本發明之一實施例中，提供圖案化導電層與第一圖 案化防焊層的方法如下所述。首先，提供一導電層。接著， 形成一防焊層於導電層上。然後，圖案化防焊層以形成第 一圖案化防焊層，其中第/圖案化防焊層暴露出部分導電 層。之後’圖案化導電層以形成圖案化導電層。 在本發明之一實施例中，提供圖案化導電層與第一圖 201027636 ^ 16667-0P3twf.doc/n 案化防焊層的方法方法如下所述。首先，提供—防焊層。 接著，形成一導電層於防焊層上。然後，圖案化防焊層以 形成第一圖案化防焊層，其中第一圖案化防烊層暴露出部 分導電層。之後，圖案化導電層以形成圖案化導電層。 在本發明之一實施例中，提供圖案化導電層與第一圖 案化防焊層的方法如下所述。首先，提供一導電層。接著， 形成一防焊層於導電層上。 圖案化導電層以形成圖案化導電層。然後，圖案化防 知層以形成第一圖案化防焊層。 在本發明之一實施例中，提供圖案化導電層與第一圖 案化防焊層的方法如下所述。首先，提供一防焊層。接著θ， 形成一導電層於防焊層上。然後，圖案化導電層以形成圖 案化導電層。之後’圖案化防焊層以形成第—圖案化防 層。 吁 在本發明 之一 層上 實施例中，多個引腳形成於圖案化導電 在^發明之—實施例中，多個第二開口形成於第一圖 化防焊層上，其_第二開口暴露出各晶片的局部區域。 2發明之_實施例中’多㈣三開口形成於第二圖 防知層上，且第三開口暴露出部分圖案化導電層以及 各晶片的局部區域。 θ 案化實施例中，多個第四開口形成於第二圖 在本發明之一實施例中，晶片封裝結構的製程更包括 ^°〇3 16667-0P3twf.doc/r 201027636 於各第四開口中形成一外部電極，並經由第四開口使外部 電極電性連接至圖案化導電層。 在本發明之一實施例中，晶片封裝結構的製程更包括 形成一黏著層於晶片與第一圖案化防焊層之間。 在本發明之一實施例中，黏著層為一 B階黏著層。 在本發明之一實施例中，B階黏著層預先形成於晶片 的一主動面上。 ❹ 义在本發明之一實施例中，在晶片黏著至圖案化導電層 之則，B階黏著層形成於圖案化導電層上。 在本發明之一實施例中，封裝膠體包覆部分晶片。 在本發明之一實施例中，封裝膠體全面包覆晶片。 在本發明之一實施例中，第—/ • 膠層。 弟圖案化防焊層為一B階 膠。在本發明之一實施例中’ B階膠層為—感光性的B階 β到核ίίίί的^^=，=，程可在不需用 晶片封裝結構的製程所製得的晶片封;發明之 知之晶片封裝結構的厚度。$㈣、、、。構的厚度小於習 為讓本發明之上述特徵和優點能 舉實施例，並配合所附圖式作詳細說明如;易幢’下文特 【實施方式】 且於圖示或描述 本發明的實施例可參照對應的圖示 7 201027636 ........»003 16667-0P3twf.doc/n 中標遗相同之處為彼此相同或相似。 圖1A至圖1J為本發明一實施例之晶片封裝結構的製 程剖面圖。請參照圖1A，提供一導電層11〇與一第一圖案 化防焊層120,其中導電層110具有相對的一第一表面112 與一第一表面114，第一圖案化防焊層120具有多個第二 開口 122。此外，第一圖案化防焊層120配置於導電層11〇 的苐一表面112上。在一較佳的實施例中，可對導電層11〇 施加一棕化（brown oxidation )製程或一黑化（Wack oxidation)製程，以增加導電層11〇的表面粗糙度。如此， 可提升導電層110與第一圖案化防焊層120的接合度。 ❿ 在本實施例中，形成第一圖案化防焊層12〇的^法為 貼附一 B階膠膜（B staged fllm)於導電層i 1〇的第一表面 112上，其中B階膠膜亦為一防焊層，且此固態狀的防焊 2貼附至導電層1H)之前或之後可被圖案化而形成第一 ^案化防焊層12〇。在-實施财，第—圖案化防焊層12〇 2成方式包括缺導電層11G的第—表面112上塗佈一 焊材料（例如B階液態防焊材料），然後，固化盥 液態防焊材料’以形成第1案化防焊層12〇, -Η亲ί可猎由加熱或是照射紫外光。在本實施例中，第 防^ ^烊層⑽可為—Β階膠膜。再者，第一圖案化 防知層120可為一感光性的Β階膠膜。 安化請參照圖1Β，以曝光顯影以及_的方式圖 ’以形成一圖案化導電層130,其中圖案化 導電層m具有多個引腳132與多個第一開口 136。值得 8 201027636 扁 16667-0P3twf. doc/n 注意的是’前述形成圖案化導電層130與第一圖案化防焊 層120的圖案化製程的順序並非用以限定本發明。 然後，請參照圖1C，於圖案化導電層130的第二表 面114上形成一第二圖案化防焊層140,第二圖案化防焊 層140具有多個第三開口 144，其中部分第二表面114暴 露於第二圖案化防焊層140之外。換言之，形成於部分第 二表面114上的第二圖案化防焊層14〇定義出多個第一接 墊134。第二圖案化防烊層140的形成方法包括封膠、印 刷或薄膜貼附。在一較佳的實施例中，可進行—電鑛製程 (platingPr〇cess)，以於第一接墊134上形成—電^導電 層（未繪示）。前述電鍍導電層可為一鎳/金疊層或是其他 適合的金屬層。 μ 之後，請參照圖ID，將多個晶片15〇黏著至第一圖 案化防知層120，並形成多條導線mo，以連接第一接墊 134與晶片150。各晶片15〇具有一主動面152、一相對於 主動面152的背面154、多個配置於主動面152上的第二 ® 接墊156,且一第一開口 136暴露出這些第二接墊156。各 曰曰片150藉由一配置於晶片15〇與第一圖案化防焊層 之間的黏著層170黏著至第一圖案化防焊層12〇，其中第 一圖案化防焊層120位於圖案化導電層13〇與各晶片15〇 之間在貝施例中，晶片150可不需經由黏著層17〇而 ^接黏著至第-圖案化防焊層12()上，其中第—圖案化防 焊層120為一形成於導電層13〇上的B階膠膜，而且，在 晶片150黏著之前，此3階膠膜未被完全固化。 9 201027636 jj^-zuv6uy〇03 16667-0P3twf.doc/n 在本實施例中，導線160是以打線接合的方式形成， 且各導線160電性連接一第一接墊丨34與一第二接墊 156。導線160例如為金導線。 在本實施例中’黏著層170例如為一 B階黏著層。B 階黏著層可為ABLESTIK的8008或8008TH。此外，B階 黏著層亦可為ABLESTIK的6200、6201或6202或 HITACHI Chemical CO.，Ltd.提供的 SA-200-6、 SA-200-10。在本發明之一實施例中，B階黏著層17〇形成 在晶圓的主動面。當晶圓被切割時，可形成多個晶片i 50， 且晶片150具有位於其主動面152上的黏著層170。因此， B階黏著層170有利於量產。此外，b階黏著層170的形 成方式包括旋轉塗佈、印刷或是其他適合的製程。更明確 而言’黏著層170是形成在晶片150的主動面152上。具 體而言，可先提供一晶圓，其具有多個成陣列排列的晶片 150。然後’於晶片150的主動面152上形成一二階黏著層， 並藉由加熱或是照射紫外光的方式使此二階黏著層部分固 ❿ 化，以形成B階黏著層170。另外，在晶片15〇黏著至第 一防焊層120之前，B階黏著層170可預先形成在第一防 焊層120上。 在本實施例中’當晶片150黏著至第一防焊層12〇之 後或在之後的後固化製程中，或者是當一封裝膠體包覆晶 片150之後，B階黏著層170才完全固化。 接著，請參照圖1E，至少一封裝膠體18〇包覆圖案化 導電層130、第一圖案化防焊層12〇、第二圖案化防焊層 140 封農膠體180的材質例如為環 ❹The layer is patterned and the first layer is patterned. The pattern is formed by a plurality of Ϊ-openings. The first patterning layer is disposed on: s. Next, a second patterned solder resist layer is formed on the patterned broadcast layer such that the first patterned solder resist layer and the second patterned solder resist layer 1 are disposed on opposite surfaces of the patterned conductive layer. Then, a plurality of ruthenium sheets are bonded to the first patterned solder resist layer to pass between the first patterned solder mask layer and the (four) conductive layer. Thereafter, the wafer is electrically connected to the patterned conductive layer by a plurality of wires, wherein the wires pass through the first opening of the patterned conductive layer. Then, at least one encapsulant is formed to cover the patterned conductive layer, the first patterned solder resist layer, the second patterned solder resist layer, the wafer and the wires. Then, the encapsulant, the first patterned solder resist layer and the second patterned solder resist layer are separated. In one embodiment of the invention, a method of providing a patterned conductive layer and a first patterned solder resist layer is as follows. First, a conductive layer is provided. Next, a solder resist layer is formed on the conductive layer. A solder mask is then patterned to form a first patterned solder mask, wherein the/patterned solder mask exposes a portion of the conductive layer. The conductive layer is then patterned to form a patterned conductive layer. In one embodiment of the present invention, a method of providing a patterned conductive layer and a first solder mask of the first embodiment is as follows. First, provide a solder mask. Next, a conductive layer is formed on the solder resist layer. A solder mask layer is then patterned to form a first patterned solder mask, wherein the first patterned anti-corrugated layer exposes a portion of the conductive layer. Thereafter, the conductive layer is patterned to form a patterned conductive layer. In one embodiment of the invention, a method of providing a patterned conductive layer and a first patterned solder resist layer is as follows. First, a conductive layer is provided. Next, a solder resist layer is formed on the conductive layer. The conductive layer is patterned to form a patterned conductive layer. The layer of anti-knowledge is then patterned to form a first patterned solder mask. In one embodiment of the invention, a method of providing a patterned conductive layer and a first patterned solder resist layer is as follows. First, a solder mask is provided. Next, θ forms a conductive layer on the solder resist layer. The conductive layer is then patterned to form a patterned conductive layer. The solder resist layer is then patterned to form a first patterned anti-layer. In an embodiment of a layer of the present invention, a plurality of pins are formed in the patterned conductive body. In the embodiment, a plurality of second openings are formed on the first patterned solder resist layer, and the second opening is formed. A partial area of each wafer is exposed. In the embodiment of the invention, the 'multiple (four) three openings are formed on the second image prevention layer, and the third opening exposes a portion of the patterned conductive layer and a partial region of each wafer. In the θ embodiment, a plurality of fourth openings are formed in the second figure. In an embodiment of the present invention, the process of the chip package structure further includes: ^°〇3 16667-0P3twf.doc/r 201027636 in each fourth opening An external electrode is formed in the middle, and the external electrode is electrically connected to the patterned conductive layer via the fourth opening. In one embodiment of the invention, the process of the wafer package structure further includes forming an adhesive layer between the wafer and the first patterned solder resist layer. In one embodiment of the invention, the adhesive layer is a B-stage adhesive layer. In one embodiment of the invention, the B-stage adhesive layer is preformed on an active face of the wafer. In one embodiment of the invention, a B-stage adhesive layer is formed on the patterned conductive layer after the wafer is adhered to the patterned conductive layer. In one embodiment of the invention, the encapsulant encapsulates a portion of the wafer. In one embodiment of the invention, the encapsulant is fully coated with the wafer. In an embodiment of the invention, the -/• glue layer. The patterned solder mask is a B-stage glue. In one embodiment of the present invention, the 'B-stage adhesive layer is a photosensitive B-stage β-to-core ^,=, a wafer seal that can be obtained without a process of using a chip package structure; The thickness of the chip package structure is known. $(4), ,,. The above-described features and advantages of the present invention are set forth in the accompanying drawings, and are described in detail in the accompanying drawings. Refer to the corresponding figure 7 201027636 ........»003 16667-0P3twf.doc/n The similarities in the mark are the same or similar to each other. 1A through 1J are process cross-sectional views showing a wafer package structure according to an embodiment of the present invention. Referring to FIG. 1A, a conductive layer 11 and a first patterned solder resist layer 120 are provided. The conductive layer 110 has a first surface 112 and a first surface 114. The first patterned solder resist layer 120 has A plurality of second openings 122. In addition, the first patterned solder resist layer 120 is disposed on the first surface 112 of the conductive layer 11A. In a preferred embodiment, a brown oxidation process or a Wack oxidation process can be applied to the conductive layer 11A to increase the surface roughness of the conductive layer 11A. As such, the degree of bonding of the conductive layer 110 to the first patterned solder resist layer 120 can be improved. In the present embodiment, the first patterned solder resist layer 12 is formed by attaching a B-stage film (B staged fllm) to the first surface 112 of the conductive layer i 1 , wherein the B-stage glue The film is also a solder resist layer, and the solid solder resist 2 is attached to the conductive layer 1H) before or after being patterned to form the first solder resist layer 12A. In the implementation, the first patterning solder resist layer 12 is formed by coating a first surface 112 of the conductive layer 11G with a solder material (for example, a B-stage liquid solder resist material), and then curing the liquid solder resist. The material 'to form the first case solder mask 12 〇, Η Η can be hung by heating or illuminating ultraviolet light. In this embodiment, the first layer (10) may be a ruthenium film. Furthermore, the first patterned anti-sense layer 120 can be a photosensitive ruthenium film. For security, please refer to FIG. 1A to form a patterned conductive layer 130 by exposing the development and the pattern, wherein the patterned conductive layer m has a plurality of leads 132 and a plurality of first openings 136. It is worth 8 201027636 flat 16667-0P3twf. doc/n Note that the order of the patterning process for forming the patterned conductive layer 130 and the first patterned solder resist layer 120 is not intended to limit the present invention. Then, referring to FIG. 1C, a second patterned solder resist layer 140 is formed on the second surface 114 of the patterned conductive layer 130. The second patterned solder resist layer 140 has a plurality of third openings 144, some of which are second. Surface 114 is exposed to the outside of second patterned solder mask layer 140. In other words, the second patterned solder mask layer 14 formed on the portion of the second surface 114 defines a plurality of first pads 134. The method of forming the second patterned tamper resistant layer 140 includes encapsulation, printing or film attachment. In a preferred embodiment, a plating process can be performed to form an electrically conductive layer (not shown) on the first pad 134. The electroplated conductive layer can be a nickel/gold laminate or other suitable metal layer. After μ, referring to the figure ID, a plurality of wafers 15 are adhered to the first patterned anti-knowledge layer 120, and a plurality of wires mo are formed to connect the first pads 134 and the wafers 150. Each of the wafers 15A has an active surface 152, a back surface 154 opposite to the active surface 152, and a plurality of second solder pads 156 disposed on the active surface 152, and a first opening 136 exposes the second pads 156. . Each of the dies 150 is adhered to the first patterned solder resist layer 12 by an adhesive layer 170 disposed between the wafer 15 and the first patterned solder resist layer, wherein the first patterned solder resist layer 120 is located in the pattern Between the conductive layer 13〇 and each of the wafers 15〇, in the embodiment, the wafer 150 can be adhered to the first patterned solder resist layer 12 without the adhesive layer 17 , wherein the first patterning prevention The solder layer 120 is a B-stage adhesive film formed on the conductive layer 13 and the third-order adhesive film is not completely cured before the wafer 150 is adhered. 9 201027636 jj^-zuv6uy〇03 16667-0P3twf.doc/n In this embodiment, the wires 160 are formed by wire bonding, and the wires 160 are electrically connected to a first pad 34 and a second connection. Pad 156. The wire 160 is, for example, a gold wire. In the present embodiment, the adhesive layer 170 is, for example, a B-stage adhesive layer. The B-stage adhesive layer can be 8008 or 8008TH of ABLESTIK. Further, the B-stage adhesive layer may be 6200, 6201 or 6202 of ABLESTIK or SA-200-6, SA-200-10 supplied by HITACHI Chemical CO., Ltd. In one embodiment of the invention, a B-stage adhesive layer 17 is formed on the active side of the wafer. When the wafer is diced, a plurality of wafers i 50 can be formed, and the wafer 150 has an adhesive layer 170 on its active surface 152. Therefore, the B-stage adhesive layer 170 is advantageous for mass production. In addition, the formation of the b-stage adhesive layer 170 includes spin coating, printing, or other suitable process. More specifically, the adhesive layer 170 is formed on the active surface 152 of the wafer 150. Specifically, a wafer may be provided having a plurality of wafers 150 arranged in an array. Then, a second-order adhesive layer is formed on the active surface 152 of the wafer 150, and the second-order adhesive layer portion is solidified by heating or irradiating ultraviolet light to form a B-stage adhesive layer 170. Further, the B-stage adhesive layer 170 may be previously formed on the first solder resist layer 120 before the wafer 15 is adhered to the first solder resist layer 120. In the present embodiment, the B-stage adhesive layer 170 is completely cured after the wafer 150 is adhered to the first solder resist layer 12 or after the post-curing process, or when an encapsulant is coated with the wafer 150. Next, referring to FIG. 1E, at least one encapsulant 18 〇 encapsulating the patterned conductive layer 130, the first patterned solder mask 12 〇, and the second patterned solder resist 140 are made of, for example, a ring ❹
201027636 iu-^w〇u9003 16667-0P3twf.doc/n 月〗50與導線160 氧樹腊（epoxy resin )。 率化，形成多個第四開σ142於第二圖 案=防知層⑽中，以暴露出圖案化導電層13G的部 ^面114 ’之後，分別於這些第四開口 142中形成多個 外部電極190，以雷性連接闇安几-首疮η 1Qrw 一 _⑽電層13G。外部電極 ⑽例如為銲球。值得注意的是，在第二_化轉層⑽ 形成於_化導電層13G㈣二表面114上_時，可开； 成第二圖案化防焊層140的第四開口 142。 7 請參照圖1G，擁於前述實_切朗裝膠體⑽ 來包覆圖案化導電層130、第一圖案化防焊層12〇、晶片 i5〇與導線副，本實施例是形成多個封裝膠體18〇，=包 覆圖案化導電層U〇、第一圖案化防焊層^、晶 ％ 與導線160。 請參照圖1H與圖II，圖1F或圖1G中的結構經單顆 化（singularize)之後可分別形成多個晶片封裝結構ι〇〇(如 圖1H所示）或多個晶片封裝結構1〇〇,（如圖u所示）， 其中單顆化的製程包括—衝壓製程（punch Pn)eess)或一 切割製程（sawing process )。. 請參照圖1H，值得注意的是，圖案化導電層13〇未 延伸至晶片封裝結構100的侧壁W，故圖案化導電層13〇 未暴露於晶片封裝結構100的側壁W之外。在本^施例 中，封裝膠體180是部分包覆晶片150且暴露出晶片15〇 的背面154，在其他實施例中，封裝膠體18〇亦可完全包 覆晶片150 (如圖1：r所示）。 11 201027636 jj/003 16667-0P3twf.doc/n ❹ 如圖1H所示，本實施例之晶片封裝結構1〇〇主要包 括一圖案化導電層130、一第一圖案化防焊層12〇、—第二 圖案化防焊層14G、-晶片15G、多條導線⑽與一封裝膠 體180。圖案化導電層13〇具有相對的一第一表面112與 一第二表面114。帛一圖案化防焊層12〇配置於第一表’面 Π2。第二圖案化防焊層140配置於第二表面114,其中第 二圖案化防焊層14G暴露出部分的第二表面114。晶片15〇 藉由黏著層170配置於第-圖案化防焊層12〇上，其中黏 為一㈣黏著層’第一圖案化防焊層心己 ^於圖案化導電層13G與晶片15G之間。導線⑽電性連 以及由第二圖案化防辉層⑽所暴露出的圖 ϋ電層130。封裝膠體⑽包覆圖案化導電層130、第 方焊層12〇、第二圖案化防烊層！ 弟 以及導線160。 曰曰乃 綜上所述，相較於習知之晶片封裴結 無核心介電層且厚度較小的= 構因此，本發明可降低製作成本並提升產量。 雖然本發明已以實施例揭露如上，然i ::明，任何所屬技術領域中具有通常知;者，在 t發明之精神和範圍内，當可作些許之更動，：T 發明之保圍當視後社申請專利翻所界定者為準本 【圖式簡單說明】 程剖至圖1 了為本發明—實施例之晶片封裝結構的製 12 201027636 003 16667-0P3twf.doc/n 【主要元件符號說明】 100、100’ ：晶片封裝結構 110 :導電層 112 :第一表面 114 :第二表面 120 :第一圖案化防焊層 122 :第二開口 130 :圖案化導電層 ® 132 :引腳 134 :第一接墊 136 :第一開口 140 :第二圖案化防焊層 142 ··第四開口 144 :第三開口 150 :晶片 152 :主動面 φ 154 :背面 156 :第二接墊 160 :導線 170:黏著層 180、180’：封裝膠體 190 :外部電極 W :側壁 13201027636 iu-^w〇u9003 16667-0P3twf.doc/n month 〗 50 with wire 160 oxygen resin (epoxy resin). The plurality of fourth openings σ 142 are formed in the second pattern=anti-sensing layer (10) to expose the portion of the patterned conductive layer 13G, and a plurality of external electrodes are respectively formed in the fourth openings 142. 190, connected to the darkness of the stunned squirrel η 1Qrw _ (10) electrical layer 13G. The external electrode (10) is, for example, a solder ball. It should be noted that the second opening 142 of the second patterned solder resist layer 140 may be formed when the second conductive layer (10) is formed on the second surface 114 of the conductive layer 13G. 7 Referring to FIG. 1G, the patterned conductive layer 130, the first patterned solder resist layer 12, the chip i5〇, and the wire pair are covered by the above-described solid-chip-cut colloid (10). In this embodiment, multiple packages are formed. The colloid 18 〇, = coated patterned conductive layer U 〇 , first patterned solder resist layer ^, crystal % and wire 160. Referring to FIG. 1H and FIG. 2, the structure in FIG. 1F or FIG. 1G may be separately formed into a plurality of chip package structures (as shown in FIG. 1H) or a plurality of chip package structures after singularizing. 〇, (as shown in Figure u), where the singulation process includes a punching process (punch Pn) eess) or a sawing process. Referring to FIG. 1H, it is noted that the patterned conductive layer 13A does not extend to the sidewall W of the wafer package structure 100, so that the patterned conductive layer 13 is not exposed to the sidewall W of the wafer package structure 100. In the embodiment, the encapsulant 180 is partially covered with the wafer 150 and exposes the back surface 154 of the wafer 15 . In other embodiments, the encapsulant 18 〇 can also completely cover the wafer 150 ( FIG. 1 : r Show). 11 201027636 jj/003 16667-0P3twf.doc/n As shown in FIG. 1H, the chip package structure 1 of the present embodiment mainly includes a patterned conductive layer 130, a first patterned solder resist layer 12, The second patterned solder resist layer 14G, the wafer 15G, the plurality of wires (10) and an encapsulant 180. The patterned conductive layer 13A has a first surface 112 and a second surface 114 opposite to each other. The patterned solder resist layer 12 is disposed on the first surface 面2. The second patterned solder mask layer 140 is disposed on the second surface 114, wherein the second patterned solder resist layer 14G exposes a portion of the second surface 114. The wafer 15 is disposed on the first patterned solder resist layer 12 by an adhesive layer 170, wherein the adhesion is a (four) adhesive layer. The first patterned solder resist layer is between the patterned conductive layer 13G and the wafer 15G. . The wire (10) is electrically connected to the conductive layer 130 exposed by the second patterned anti-fog layer (10). The encapsulant (10) encapsulates the patterned conductive layer 130, the second solder layer 12, and the second patterned anti-caries layer! Brother and wire 160. In summary, the present invention can reduce the manufacturing cost and increase the yield compared to the conventional wafer package junction having no core dielectric layer and a small thickness. Although the present invention has been disclosed in the above embodiments by way of example, i: Ming, which is generally known in the art; in the spirit and scope of the invention, when a slight change can be made, the protection of the T invention is The definition of the patent application is based on the definition of the patent. [Simplified illustration of the drawing] The process of the invention is shown in Figure 1. The wafer package structure of the present invention is 12 201027636 003 16667-0P3twf.doc/n [Main component symbol Description 100, 100': chip package structure 110: conductive layer 112: first surface 114: second surface 120: first patterned solder mask 122: second opening 130: patterned conductive layer ® 132: pin 134 : first pad 136 : first opening 140 : second patterned solder mask 142 · · fourth opening 144 : third opening 150 : wafer 152 : active surface φ 154 : back 156 : second pad 160 : wire 170: Adhesive layer 180, 180': encapsulant 190: external electrode W: side wall 13