TW201839922A - Package structure and manufacturing method thereof - Google Patents

Abstract

A package structure includes an insulation encapsulation, an adhesion layer, a first circuit layer, a chip, conductive structures, a dielectric layer and a second circuit layer. The insulation encapsulation has a first surface and a second surface. The adhesion layer, the chip, the conductive structures, and at least one part of the first circuit layer are embedded in the insulation encapsulation. Another at least one part of the first circuit layer is embedded in the adhesion layer. The first circuit layer includes first pads and second pads. The chip including connection terminals is disposed on the adhesion layer. The conductive structures are electrically connected to the first pads. The dielectric layer is disposed on the second surface of the insulation encapsulation. The second circuit layer is electrically connected to the conductive structures and the connection terminals.

Description

Package structure and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure having a molded interconnect substrate (MIS) formed therein and a method of fabricating the same.

In order to make electronic products design thin and light, semiconductor packaging technology is also progressing to develop products that meet the requirements of small size, light weight, high density, and high competitiveness in the market. Therefore, miniaturizing the package structure while maintaining process simplification has become a challenge for those skilled in the art.

The invention provides a package structure and a manufacturing method thereof, which effectively reduce the size and manufacturing cost thereof.

The present invention provides a package structure. The package structure includes an insulating sealing body, an adhesive layer, a first wiring layer, a wafer, a plurality of conductive structures, a dielectric layer, and a second wiring layer. The insulating seal has a first surface and a second surface opposite the first surface. The adhesive layer is embedded in the insulating sealing body. The first circuit layer has at least a portion embedded in the insulating sealing body and another at least a portion embedded in the adhesive layer. The first circuit layer includes a plurality of first pads and a plurality of second pads. The wafer is placed on the adhesive layer and embedded in the insulating sealing body. The wafer includes a plurality of connection terminals exposed through the second surface of the insulating sealing body. The electrically conductive structure is embedded in the insulative sealing body. The conductive structure is electrically connected to the first pad. The second surface of the insulative seal exposes a top surface of the conductor structure. The dielectric layer is disposed on the second surface of the insulating sealing body. The second circuit layer is embedded in the dielectric layer and electrically connected to the conductive structure and the connection terminal. The dielectric layer exposes a top surface of the second circuit layer.

The present invention provides a method of fabricating a package structure that includes at least the following steps. A carrier substrate is provided. A first wiring layer is formed on the carrier substrate. The first circuit layer includes a plurality of first pads and a plurality of second pads. A plurality of conductive structures are formed on the first pads. An adhesive layer and a wafer are sequentially formed on the carrier substrate. An insulating sealing body is formed on the carrier substrate. At least a portion of the first wiring layer is embedded in the insulating sealing body, and at least a portion of the other wiring layer is embedded in the adhesive layer. The thickness of the insulating sealing body is reduced such that the first surface of the insulating sealing body is adhered to the carrier substrate, and the second surface of the insulating sealing body with respect to the first surface exposes a top surface of the conductive structure and a plurality of connections of the wafer Terminal. A second wiring layer is formed on the insulating sealing body. The second circuit layer is electrically connected to the connection terminals of the conductive structure and the wafer. A dielectric layer is formed on the insulating sealing body to seal the second wiring layer. The dielectric layer exposes a top surface of the second circuit layer. The carrier substrate is removed from the first surface of the insulative sealing body.

Based on the above, the package structure of the present invention includes a molded interconnect substrate (MIS) formed therein. Therefore, the thickness of the package structure can be reduced, thereby achieving miniaturization of the package structure. In addition, the fabrication of the package structure can be ensured by using a photolithography and a plating process instead of a conventional laser drilling process to fabricate the conductive via/cylinder in the molded interconnect substrate. The simplicity of the process. Therefore, the overall production cost can be effectively reduced.

The above described features and advantages of the invention will be apparent from the following description.

1A-1J are schematic cross-sectional views showing a manufacturing process of a package structure 10 according to an embodiment of the invention.

Referring to FIG. 1A, a carrier substrate 100 is provided. The carrier substrate 100 includes a metal carrier substrate, a glass carrier substrate, or a germanium wafer substrate. For example, in the present embodiment, a metal carrier substrate can be utilized as the carrier substrate 100. Other materials of the carrier substrate utilized in other embodiments can also be used in this embodiment. A first wiring layer 200 is formed on the carrier substrate 100. In some embodiments, forming the first wiring layer 200 on the carrier substrate 100 may be performed by, for example, an electroless plating process, a chemical plating process, a thermal evaporation process, or sputtering. Sputtering process. For example, a metal layer (not shown) may be formed on the carrier substrate 100 by the above method. Thereafter, a yellow photolithography process can be performed on the metal layer to pattern the metal layer to form the first wiring layer 200. The material of the first wiring layer 200 includes copper, tin, gold, nickel, solder or other conductive material. The first circuit layer 200 includes a plurality of first pads 200a and a plurality of second pads 200b. The first pad 200a surrounds the second pad 200b. For example, the first pads 200a may be formed in the peripheral region, and the second pads 200b may be formed in the active region/wafer attaching region. It should be noted that the first circuit layer 200 further includes a plurality of traces not shown in the cross-sectional view of FIG. 1A.

A plurality of conductive structures 202 are formed on the first pads 200a and electrically connected to the first pads 200a. The material of the conductive structure 202 includes copper, tin, gold, nickel, solder or other conductive material. In some embodiments, the sidewalls of the electrically conductive structure 202 are substantially straight. In addition, each of the conductive structures 202 may be a single layer structure or a multilayer structure. In some embodiments, each of the electrically conductive structures 202 can be a single layer structure formed of copper, gold, nickel, or solder. In some alternative embodiments, each of the electrically conductive structures 202 can be a multilayer structure formed of braze or copper-nickel solder or the like.

In some embodiments, the electrically conductive structure 202 can be a conductive post. The conductive pillars can be formed by a yellow lithography process and a plating process. For example, when the conductive pillar is formed through the yellow lithography process and the plating process, the first pad 200a can serve as a seed layer. However, the invention is not limited thereto. In some alternative embodiments, an additional seed layer may be formed on the first pad 200a. A photomask (not shown) is formed on the carrier substrate 100. The photomask includes a plurality of openings corresponding to the seed layer (first pad 200a). That is, the opening exposes a portion of the first pad 200a. Thereafter, the conductive structure 202 is filled into the opening of the reticle through the plating process. The plating process is, for example, electro-plating, electroless-plating, immersion plating, or the like. Thereafter, the reticle is removed to form a plurality of conductive pillars (conductive structures 202). Alternatively, the conductive pillars can be formed by a pick-and-place process. For example, a pick and place tool can be used. The pick and place tool picks up the prefabricated conductive pillars (such as gold pillars, copper pillars, nickel pillars, etc.), and places the prefabricated conductive pillars on the corresponding first pads 200a. As shown in FIG. 1A, the width W1 of each of the first pads 200a is greater than the width W2 of each of the conductive structures 202. For example, the width W1 of each of the first pads 200a may range from 145 μm to 175 μm, and the width W2 of each of the conductive structures 202 may correspondingly range between 80 μm and 120 μm.

Referring to FIG. 1B, an adhesive layer 300 and a wafer 400 are sequentially formed on the carrier substrate 100. In some embodiments, the adhesive layer 300 and the wafer 400 are formed in regions defined by the first pads 200a and the conductive structures 202. For example, as shown in FIG. 1B, conductive structure 202 can surround wafer 400 and adhesive layer 300. The adhesive layer 300 overlaps and seals the second pads 200b. In other words, the second pad 200b is embedded in the adhesive layer 300. In some embodiments, the adhesive layer 300 may be a die attach film (DAF) to temporarily enhance adhesion between the carrier substrate 100 and the wafer 400. However, in some alternative embodiments, in order to enhance the releasibility of the wafer 400 from the carrier substrate 100 in a subsequent process, a release layer (not shown) may be disposed on the carrier substrate 100, that is, disposed at the first Between the circuit layer 200/adhesive layer 300 and the carrier substrate 100. The release layer is, for example, a light to heat conversion (LTHC) release layer or other suitable release layer.

The wafer 400 is, for example, an Application-Specific Integrated Circuit (ASIC). In some embodiments, wafer 400 can be used to perform logic applications. However, the invention is not limited thereto. Other suitable active devices can also be used as the wafer 400. The wafer 400 includes an active surface 400a and a plurality of connection terminals 402 formed on the active surface 400a. The connection terminal 402 may be a conductive bump formed using a conductive material such as copper, gold, nickel or solder. As shown in FIG. 1B, the active surface 400a of the wafer 400 faces upward.

Referring to FIG. 1C, an insulating sealing body 500 is formed on the carrier substrate 100. For example, at least a portion of the first wiring layer 200 is embedded in the insulating sealing body 500, and at least a portion of the other wiring layer 200 is embedded in the adhesive layer 300. In some embodiments, the insulative sealing body 500 seals the first pads 200a, the conductive structures 202, the adhesive layer 300, and the wafer 400. In other words, during this step, the insulative sealing body 500 completely covers the active surface 400a of the wafer 400 and the top surface 202a of the conductive structure 202. The adhesive layer 300, the wafer 400, the first pads 200a, and the conductive structure 202 are embedded in the insulating sealing body 500. The insulating sealing body 500 may include a molding compound disposed on the carrier substrate 100 through a molding process. The molding process includes, for example, a compression molding process. In some alternative embodiments, the insulative seal 500 can be formed from an insulating material such as epoxy or other suitable resin.

Referring to FIG. 1D, the thickness of the insulating sealing body 500 is reduced. For example, the insulative sealing body 500 is thinned until the top surface 202a of the conductive structure 202 and the connection terminal 402 are exposed. For example, as shown in FIG. 1D, the thinned insulating sealing body 500 includes a first surface 500a and a second surface 500b relative to the first surface 500a. The first surface 500a is adhered to the carrier substrate 100, and the second surface 500b exposes the top surface 202a of the conductive structure 202 and the connection terminal 402 of the wafer 400. In some embodiments, the top surface 202a of the conductive structure 202, the top surface of the connection terminal 402, and the second surface 500b of the insulating seal 500 are coplanar. The thinning process can be achieved by, for example, mechanical polishing, chemical-mechanical polishing (CMP), etching, or other suitable methods.

Referring to FIG. 1E, a second wiring layer 600 is formed on the insulating sealing body 500 to electrically connect the second wiring layer 600 to the conductive structure 202 and the connection terminal 402 of the wafer 400. Similar to the first circuit layer 100 and the conductive structure 202, the second circuit layer 600 can be formed through a yellow lithography process and a plating process. The material of the second wiring layer 600 includes copper, tin, gold, nickel, solder or other conductive material. In some embodiments, the second circuit layer 600 includes a plurality of third pads 602 and a plurality of pillars 604 on the third pads 602. The third pad 602 may be formed corresponding to the conductive structure 202 and the connection terminal 402 of the wafer 400. Thereafter, a post 604 is formed on the third pad 602. As shown in FIG. 1E, the width W3 of each of the third pads 602 is greater than the width W4 of each of the cylinders 604.

Referring to FIG. 1F, a dielectric layer 700 is formed on the second surface 500b of the insulating sealing body 500 to seal the second wiring layer 600. In other words, during this step, the dielectric layer 700 completely covers the top surface 600a (cylinder 604) of the second wiring layer 600 such that the second wiring layer 600 is embedded in the dielectric layer 700. In some embodiments, the dielectric layer 700 can be referred to as a solder mask. The raw material of the dielectric layer 700 includes, for example, a molding compound, an epoxy resin, or other suitable resin. However, the invention is not limited thereto. Other suitable dielectric materials can also be used as the dielectric layer 700. In some embodiments, the dielectric layer 700 can be formed by a molding process such as a compression molding process.

Referring to FIG. 1G, the thickness of the dielectric layer 700 is reduced. For example, dielectric layer 700 is thinned until the top surface 600a (cylinder 604) of second wiring layer 600 is exposed. The thinning process can be achieved by, for example, mechanical grinding, chemical mechanical polishing, etching, or other suitable method. Since the dielectric layer 700 is ground, in some embodiments, the top surface 700a of the dielectric layer 700 is coplanar with the top surface 600a of the second wiring layer 600.

Referring to FIG. 1H, the carrier substrate 100 is removed from the first surface 500a of the insulating sealing body 500. For example, the adhesive layer 300 and the insulating sealing body 500 can be separated from the carrier substrate 100 by chemical etching. Alternatively, as described above, a release layer (not shown) may be disposed on the carrier substrate 100, that is, between the insulating sealing body 500 / the adhesive layer 300 / the first wiring layer 200 and the carrier substrate 100. Therefore, external energy such as ultraviolet laser light, visible light, or thermal energy can be applied to the release layer to peel the adhesive layer 300 and the insulating sealing body 500 from the carrier substrate 100. As shown in FIG. 1H, the bottom surface 300a of the adhesive layer 300 is coplanar with the first surface 500a of the insulating sealing body 500. The first surface 500a of the insulating sealing body 500 exposes the first pad 200a, and the bottom surface 300a of the adhesive layer 300 exposes the second pad 200b. In some embodiments, the structure shown in FIG. 1H can be referred to as a molded interconnect substrate (MIS).

Referring to FIG. 1I, a plurality of electronic devices 800 are formed on the dielectric layer 700. Each electronic device 800 includes a body 802 and a plurality of conductive elements 804. The conductive element 804 electrically connects the body 802 to the second circuit layer 600. For example, the conductive element 804 can be disposed corresponding to the pillar 604 to electrically connect the electronic device 800 to the second circuit layer 600. The electronic device 800 can be, for example, a transistor, a diode, a resistor, a capacitor, an inductor, an antenna, or the like.

Referring to FIG. 1J, a plurality of conductive terminals 900 are formed on the first surface 500a of the insulating sealing body 500 to form the package structure 10. For example, the conductive terminals 900 may be formed on the first pads 200a and the second pads 200b to electrically connect the conductive terminals 900 to the first circuit layer 200. In some embodiments, the conductive terminal 900 is, for example, a conductive bump of a solder ball. However, the invention is not limited thereto. Other possible forms and shapes may also be used as the conductive terminals 900. The conductive terminal 900 can be formed by a ball placement process and a reflow process.

Referring to FIG. 1J, the package structure 10 includes a molded interconnect substrate. Therefore, the thickness of the package structure 10 can be reduced, thereby achieving miniaturization of the package structure. In addition, since the first circuit layer 200, the conductive structure 202, and the second circuit layer 600 of the interconnect substrate are fabricated by using a yellow light lithography process and a plating process, the simplicity of the manufacturing process of the package structure 10 can be ensured. Therefore, the overall production cost is reduced.

2A-2H are schematic cross-sectional views showing a manufacturing process of a package structure 20 according to another embodiment of the present invention.

The embodiment of FIGS. 2A to 2H is similar to the embodiment of FIGS. 1A to 1J, and like elements are denoted by the same reference numerals and will not be described again. The main difference between this embodiment and the embodiment of FIGS. 1A to 1J is the method of forming the dielectric layer 700. The fabrication steps illustrated in FIGS. 2A-2D are similar to FIGS. 1A through 1D, and thus are not described herein again. However, in FIG. 1A, a metal carrier substrate is taken as the carrier substrate 100 as an example. The carrier substrate 100 in FIG. 2A may be, for example, a glass carrier substrate or a germanium wafer substrate. It is to be noted that a metal carrier substrate or a carrier substrate made of other suitable materials may be utilized as the carrier substrate 100, but is not limited thereto.

Referring to FIG. 2E, the second wiring layer 600' includes a plurality of third pads and/or a plurality of redistribution layers (RDLs) electrically connected to the third pads. Referring to FIG. 2F, a dielectric layer 700 is formed on the insulating sealing body 500. Dielectric layer 700 includes a plurality of openings OP that expose a portion of second wiring layer 600'. For example, the dielectric layer 700 covers the third pad and/or the redistribution layer of the second circuit layer 600', and the opening OP of the dielectric layer 700 exposes a portion of the third pad of the second circuit layer 600'. . In some embodiments, the opening OP exposes the top surface 600'a of the second circuit layer 600'. As shown in Fig. 2F, the height of the top surface 700a of the dielectric layer 700 is higher than the height of the top surface 600'a of the second wiring layer 600'. In some embodiments, a layer of dielectric material (not shown) may be formed over the insulative sealing body 500 and the second wiring layer 600'. Thereafter, a yellow lithography process is performed to pattern the dielectric material layer to form a dielectric layer 700 having openings OP.

The fabrication steps of FIGS. 2G to 2H are similar to those of FIGS. 1H to 1J, and thus are not described herein again. Referring to FIG. 2H, the package structure 20 includes a molded interconnect substrate. Therefore, the thickness of the package structure 20 can be reduced, thereby achieving miniaturization of the package structure. In addition, since the first wiring layer 200, the conductive structure 202 and the second wiring layer 600' of the interconnect substrate are fabricated by using a yellow lithography process and a plating process, the simplicity of the manufacturing process of the package structure 20 can be ensured. Therefore, the overall production cost is reduced.

In summary, the package structure of the present invention includes a molded interconnect substrate (MIS) formed therein. Therefore, the thickness of the package structure can be reduced, thereby achieving miniaturization of the package structure. In addition, since the conductive via/cylinder in the die-bonding substrate is fabricated by using a yellow lithography and a plating process instead of the conventional laser drilling process, the simplicity of the manufacturing process of the package structure can be ensured. Therefore, the overall production cost can be effectively reduced.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10, 20‧‧‧Package structure

100‧‧‧ Carrier substrate

200‧‧‧First circuit layer

200a‧‧‧first mat

200b‧‧‧second mat

202‧‧‧Electrical structure

202a‧‧‧ top surface

300‧‧‧Adhesive layer

300a‧‧‧ bottom surface

400‧‧‧ wafer

400a‧‧‧Active surface

402‧‧‧Connecting terminal

500‧‧‧Insulation seal

500a‧‧‧ first surface

500b‧‧‧ second surface

600, 600’‧‧‧second circuit layer

600a, 600a’‧‧‧ top surface

602‧‧‧3rd pad

604‧‧‧Cylinder

700‧‧‧ dielectric layer

700a‧‧‧ top surface

800‧‧‧Electronic devices

802‧‧‧ subject

804‧‧‧Conducting components

900‧‧‧Electrical terminals

OP‧‧‧ openings

W1, W2, W3, W4‧‧‧ Width:

1A-1J are schematic cross-sectional views showing a manufacturing process of a package structure according to an embodiment of the invention. 2A-2H are schematic cross-sectional views showing a manufacturing process of a package structure according to another embodiment of the present invention.

Claims (10)

A package structure comprising: an insulating sealing body having a first surface and a second surface opposite to the first surface; an adhesive layer embedded in the insulating sealing body; a first circuit layer having an embedded in the insulation At least a portion of the sealing body and at least another portion embedded in the adhesive layer, wherein the first circuit layer includes a plurality of first pads and a plurality of second pads; and a wafer is disposed on the adhesive layer And embedded in the insulating sealing body, wherein the wafer includes a plurality of connecting terminals exposed through the second surface of the insulating sealing body; a plurality of conductive structures embedded in the insulating sealing body, The conductive structure is electrically connected to the first pad, and the second surface of the insulating sealing body exposes a top surface of the conductive structure; a dielectric layer is disposed on the insulating sealing body And the second circuit layer is embedded in the dielectric layer, wherein the second circuit layer is electrically connected to the conductive structure and the connection terminal, and the dielectric layer is exposed Market The top surface of the second circuit layer. The package structure of claim 1, wherein the second circuit layer comprises a plurality of third pads and a plurality of pillars on the third pads, and each of the third pads The width is greater than the width of each of the cylinders. The package structure of claim 1, wherein the top surface of the second wiring layer is coplanar with a top surface of the dielectric layer, and the top of the dielectric layer The surface is formed to have a plurality of openings to expose at least a portion of the top surface of the second circuit layer. The package structure of claim 1, further comprising a plurality of conductive terminals on the first surface of the insulating sealing body and a plurality of electronic devices disposed on the dielectric layer, wherein The conductive terminals are electrically connected to the first pads and the second pads of the first circuit layer, and the electronic device is electrically connected to the second circuit layer. The package structure of claim 1, wherein a width of each of the first pads is greater than a width of each of the conductive structures, the conductive structure surrounding the wafer and the adhesive layer, A bottom surface of the adhesive layer is coplanar with the first surface of the insulating sealing body. A method of fabricating a package structure, comprising: providing a carrier substrate; forming a first circuit layer on the carrier substrate, wherein the first circuit layer comprises a plurality of first pads and a plurality of second pads; Forming a plurality of conductive structures on the first pad; forming an adhesive layer and a wafer on the carrier substrate; forming an insulating sealing body on the carrier substrate, wherein at least a portion of the first circuit layer is embedded in the insulating sealing body And at least a portion of the first circuit layer is embedded in the adhesive layer; the thickness of the insulating sealing body is reduced to adhere the first surface of the insulating sealing body to the carrier substrate, and a second surface of the insulating sealing body on the first surface exposing a top surface of the conductive structure and a plurality of connecting terminals of the wafer; forming a second wiring layer on the insulating sealing body, wherein a second circuit layer electrically connected to the conductive structure and the connection terminal of the wafer; forming a dielectric layer on the insulating sealing body to seal the second circuit layer, The top surface of the dielectric layer to expose the second wiring layer electrically; and removing the carrier substrate from the first surface of the insulating sealing member. The method of fabricating a package structure according to claim 6, wherein the forming the second circuit layer comprises: forming a plurality of third pads on the conductive structure and the connection terminal of the wafer; A plurality of pillars are formed on the third pad, wherein a width of each of the third pads is greater than a width of each of the pillars. The method for fabricating a package structure according to claim 6, wherein the top surface of the second circuit layer is coplanar with a top surface of the dielectric layer, and the insulating sealing body is formed on the insulating sealing body. The step of forming a dielectric layer includes: forming a dielectric material layer on the insulating sealing body and the second wiring layer; and patterning the dielectric material layer to form the dielectric layer having a plurality of openings, Wherein the opening of the dielectric layer exposes the top surface of the second wiring layer. The manufacturing method of the package structure of claim 6, further comprising: forming a plurality of conductive terminals on the first surface of the insulating sealing body, wherein the conductive terminals are electrically connected to the first a first pad and a second pad of a wiring layer; and forming a plurality of electronic devices on the dielectric layer, wherein the electronic device is electrically connected to the second circuit layer. The method of fabricating a package structure according to claim 6, wherein a width of each of the first pads is greater than a width of each of the conductive structures, the conductive structure surrounding the wafer and the adhesive layer The bottom surface of the adhesive layer is coplanar with the first surface of the insulating sealing body.