201025870 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種乘法數位類比轉換器（multiplying digital-to-analog converter，以下簡稱為MDAC) ’且特別有關於一種高 速且低供電電壓之MDAC。 【先前技術】 於類比數位轉換器(analog-to-digital converter，以下簡稱為ADC) 之領域中’高速且高解析度之類比數位轉換運作通常使用管線 ADC(pipelineADC)。管線ADC中最重要的區塊之一係MDAC。傳統 地，管線ADC内有多個MDAC，且每一個MDAC負責產生用於下一 級MDAC之餘數(residue)。此外’MDAC —般由運算放大器(operational amplifier ’以下簡稱為〇P-amp)，電容器區塊’以及開關區塊組成，其 中’電容器區塊用於抽樣(sample)輸入信號，以協助開關區塊，且 OP-amp將輸入信號與管線ADC之次ADC(SubADC)的輸出位元之間 的餘數輸出至下一個MDAC。 第1圖係根據先前技術之開關10之示意圖。根據先前技術， OP-amp之輸入信號與輸出信號的多個共模電壓(c〇mm〇n m〇de她喂) 係設為VDD/2，其中，VDD係OP-amp之供電電壓。另外，如第i圖 所示，開關區塊内之每一開關係由一 N型金氧半導體Metal 201025870201025870 VI. Description of the Invention: [Technical Field] The present invention relates to a multiplying digital-to-analog converter (hereinafter referred to as MDAC) and particularly relates to a high speed and low supply voltage MDAC. [Prior Art] In the field of analog-to-digital converters (hereinafter referred to as ADCs), high-speed and high-resolution analog-to-digital conversion operations generally use a pipeline ADC. One of the most important blocks in the pipeline ADC is MDAC. Traditionally, there are multiple MDACs in the pipeline ADC, and each MDAC is responsible for generating the remainder for the next stage MDAC. In addition, 'MDAC is generally composed of an operational amplifier (hereinafter referred to as 〇P-amp), a capacitor block' and a switch block, where the 'capacitor block is used to sample the input signal to assist the switch block. And OP-amp outputs the remainder of the input signal to the output bit of the sub-ADC (SubADC) of the pipeline ADC to the next MDAC. Figure 1 is a schematic illustration of a switch 10 according to the prior art. According to the prior art, a plurality of common mode voltages of the input signal and the output signal of the OP-amp are set to VDD/2, where VDD is the supply voltage of OP-amp. In addition, as shown in Figure i, each open relationship in the switch block consists of an N-type MOS Semiconductor 201025870
Oxide Semiconductor，以下簡稱為NMOS)電晶體MN與一 P型金氧半 ^ 導體（P〇sitive Metal Oxide Semiconductor，以下簡稱為 PM0S)電晶體 MP之組合而組成。當MDAC於低供電電壓(例如VDD=1.2V)下運作， 且開關10係處於接通模式時’開關1〇將形成死區(dead-zone)。 請參閱第2圖。第2圖係為於接通模式的開關10之nmos電晶 體MN與PMOS電晶體PN的輸入電壓VJN與跨導(transconductance) ❹之間的關係示意圖。於第2圖中，曲線11表示nmos電晶體_之 跨導，曲線12則表示PMOS電晶體PN之跨導，VDD=1_2V。從第2 圖中可以看出，當輸入電壓VIN介於電壓(VDD-VTN)與電壓|VTP|之 間時’出現死區，其中’ VTN係為NM〇s電晶體之閾值電壓，且|VTP| 係為PMOS電晶體之絕對閾值電壓(abs〇iute threshold voltage)。換言 之，若供電電壓VDD較低，開關1〇即存在死區。於此情形下，電容 器區塊可能無法正確抽樣輸入信號。 & 由於OP-amp之輸入信號的共模電壓係設為，因此,〇p_amp 之輸入級亦被偏壓為VDD/2。然而，當vdD係低供電電壓但是系統 仍需尚速運作時，設計一個偏壓為VDD/2之輸入級十分困難。因此， 設計一個運作於較低供電電壓卻具有較高運作速度之管線MC係為 ADC領域當前的挑戰。 【發明内容】 為解決以上技術問題，本發明提供了一種高速且只需低供電電麗 201025870 之 MDAC。 本發明之一實施例提供了一種MDAC，所述MDAC包含： OP-amp，ΟΡ-amp輸入開關區塊，電容器區塊，抽樣開關區塊，參考 電壓開關區塊，以及反饋開關區塊。所述〇p_amp係於第一供電電壓 以及第二供電電壓下運作，其中，第一供電電壓高於第二供電電壓； 所述OP-amp輸入開關區塊耦接於共模電壓，選擇性地將共模電壓輕 接至OP-amp之多個輸入節點，其中，包含於0P_amp輸入開關區塊 内之所有開關係僅利用PMOS電晶體實現，且第一供電電壓與共模電❹ 壓間之第一電壓差小於共模電壓與第二供電電壓間之第二電壓差；所 述電容器區塊耦接於OP-amp輸入開關區塊，抽樣與輸入信號相應之 電荷或抽樣與參考信號相應之電荷；所述抽樣開關區塊耦接於輸入信 號，選擇性地將輸入信號耦接至電容器區塊；所述參考電壓開關區塊 耦接於電容器區塊，選擇性地將參考信號耦接至電容器區塊；以及所 述反饋開關區塊柄接於電容器區塊與〇p_amp之輸出節點之間，用於 選擇性地將OP-amp之輸出節點耦接至電容器區塊。 〇 本發明提供之MDAC能夠於低供電電壓的情形下，進行高速運 作’進而避免了由於供電電壓低而導致的運作不正確，解決了以上所 述ADC領域中的技術問題。 【實施方式】 於說明書及後續的申請專利範圍當中使用了某些詞棄來指稱特定’ 6 201025870 的元組。所屬領域巾具有通常知識者應可理解，硬體製造商可能會用 ，不同的;Μ來稱刊樣的元組。本說明書及後_申請專利範圍並不 以名稱的差異來作為區分元組的方式，而是以元組在功能上的差異來 作為區分的準則。於通篇說明書及後續的請求項當中所提及的「包含」 係為一開放式的用語’故應解釋成「包含但不限定於」。另外，「耦接」 一詞在此純含任魅接關接的電氣連接手段 。因此，若文中描述 第-裝置麵接於-第二裝置，則代表該第一裝置可直接電氣連接於 ❹該第一裝置，或透過其他裝置或連接手段間接地電氣連接至該第二裝 置。 請參閱第3圖。第3圖係依本發明一實施例之^人^㈨的示意 圖。MDAC 300包含差分〇p_amp 3〇2，〇p_amp輸入開關區塊3〇4， 電容器區塊306，抽樣開關區塊3〇8，參考電壓開關區塊31〇 ,以及反 饋開關區塊312。差分〇p_amp 3〇2係於供電電壓Vdd以及接地電壓 (ground voltage)Vss下運作。需注意，為更清楚的描述本發明之精神， ©供電電壓Vdd係為低供電電壓，例如，丨.2V，且接地電壓Vss係為〇v。 OP-amp輸入開關區塊3〇4耦接於共模電壓Vcm，用於選擇性地 將共模電壓Vcm耦接至差分〇P-amp 302之輸入節點Nip及Nin，其 中，包含於OP-amp輸入開關區塊304内之所有開關係僅利用pM〇s 電晶體實現，以減少OP-amp輸入開關區塊304之阻抗及電容。電容 - 器區塊306耦接於〇P-amp輸入開關區塊304 ’用於抽樣相應於差分輸 着 入號之電何以及抽樣相應於差分參考信號之電荷。所述差分輸入信 201025870 號包含第一輸入信號Vinn以及第二輸入信號Vinp。抽樣開關區塊308 , 耦接於第一輸入信號Vinn以及第二輸入信號Vinp，用於選擇性地將 > 第一輸入信號Vinn以及第二輸入信號Vinp耦接至電容器區塊306。 所述差分參考信號包含第一參考電壓Vdacn以及第二參考電壓 Vdacp，其中，第一參考電壓vdacn可高於第二參考電壓Vdacp。參考 電壓開關區塊310耦接於電容器區塊306，用於根據次ADC(未繪示） 之輸出選擇性地將第一參考電壓Vdacn或第二參考電壓Vdacp耦接至 電容器區塊306。反饋開關區塊312耦接於電容器區塊306與差分 ' Ο 〇P-amp 302之輸出節點Nop及Non之間，用於選擇性地將差分〇p_amp w 302之輸出節點Nop及Non耦接至電容器區塊306。根據本發明之一 實施例’ MDAC 300係配置為ΟΡ-amp共用配置，因此mdac 300進 一步包含OP-amp共用開關區塊314,然而，這並不是本發明之限制。 OP-amp共用開關區塊314搞接於差分〇P-amp 302之輸入節點Nip及 Nin與OP-amp輸入開關區塊304之間，當MDAC 300進入保持階段 (hold phase)時，用於選擇性地將差分0P_amp 3〇2之輸入節點及 Nin連接至OP-amp輸入開關區塊304,或當MDAC 300進入抽樣階段〇 (sampling phase)時’用於將差分0P_amp 3〇2之輸入節點Nip及Νώ從 OP-amp輸入開關區塊304斷開，其中，包含於0P_amp共用開關區塊 314内之所有開關係僅利用PM〇s電晶體實現。 此外’共模電壓Vcm係設為實質上與供電電壓Vdd相等。同樣 地，這並不是本發明之限制。換言之，共模電壓Vcm之選取係為符人 一種條件，此條件係供電電壓Vdd與共模電壓Vcm之間的第—電^ * 201025870 差較共模電壓Vem與接地電壓％之_第二電壓差小。更具體地， *可以選取共模電壓Vem以符合—種條件，此條件係上述第—電壓差小 於供電電壓Vdd與接地電svss之間的電壓差的四分之一，且上述第 -電壓差不小於供電電壓Vdd與接地電壓Vss之間的電壓差的四分之 請再次參閱第3圖。如第3圖所示，〇p_amp輸入開關區塊3〇4 ❹包含PMOS開關SI ’ PMOS開關S2以及PMOS開關S3。PMOS開關 SI ’ PMOS開關S2以及PMOS開關S3係由時脈CK1控制，其中， PMOS開關S1耗接於節點N1與共模電壓ycm之間，pM〇s開關S2 耦接於節點N2與共模電壓Vcm之間，以及pM〇s開關幻減於節 點N1與節點N2之間。 電容器區塊306包含電容C1，電容C2，電容C3，電容C4，其 中，電谷Cl耦接於節點N3與節點N1之間，電容C2耦接於節點N4 ©與節點N1之間，電容C3耦接於節點N5與節點N2之間，以及電容 C4耦接於節點N6與節點N2之間。 抽樣開關區塊308係由時脈CKld控制，抽樣開關區塊308包含 本徵NMOS開關S4，本徵NMOS開關S5，本徵nmos開關S6，以 及本徵NMOS開關S7，其中，本徵NM〇s開關S4粞接於第一輸入 信號Vinn與節點N3之間，本徵_〇|§開關％耦接於第一輸入信號 I Vinn與節點N4之間，本徵NMOS開關S6耦接於第二輸入信號Vinp 與節點N5之間，以及本徵nmos開關S7耦接於第二輸入信號νώρ 201025870 與節點N6之間。一般地，本徵nmqs有一個約為〇 iv-0.2V之低閾 . 值電壓Vtn。 > 參考電壓開關區塊310係由時脈cK2d控制，參考電壓開關區塊 310包含NMOS開關S8 ’PMOS開關S9，NMOS開關S15，以及PMOS 開關S14，其中，NMOS開關S8耦接於第一參考電壓Vdacn與節點 N4之間，PMOS開關S9耦接於第二參考電壓vdacp與節點N5之間， NMOS開關S15耦接於第一參考電壓vdacn與節點N5之間，以及 PMOS開關S14耦接於第二參考電壓Vdacp與節點N4之間。 ❹ 反饋開關區塊312係由時脈CK2d控制，反綱關區塊312包含 本徵NMOS開關S10以及本徵nmos開關sn，其中，本徵雇以 開關S10耦接於輸出節點N〇p與節點N3之間，以及本徵開關 sii耦接於輸出節點Non與節點N6之間。 〇P-amP共用開關區塊3! 4係由時脈㈤控制，〇p_a哪共用開關◎ 區塊314包含PM0S _ S12以及pM〇s開關si3，其中，pM〇s開 關S12耦接於相N1與輸入節點跑之間，以及脱⑽開關SB耦 接於節點N2與輸入節點Nip之間。 第4圖係依本發明一實施例之第3圖所示之姻的時脈 干暗_ CK2，時脈CKld，以及時脈⑽之時序圖。如第4圖所 獅r 係時脈㈤之延遲時脈，時脈⑽係時脈阳之延 、氏。亦即，時脈CK1與時脈.CKld之上升邊緣對準，而時脈㈤d 10 201025870 之下降邊緣晚於時脈CK1之下降邊緣，時脈CK2與時脈之上 、升邊緣對準’而時脈CK2d之下降邊緣晚於時脈CK2之下降邊緣。此 時脈CK1與時脈CK2不父疊(non-overlapped)，同時時脈cKld 與時脈CK2d不交疊。時脈CK1，時脈CK2，時脈CKld，以及時脈 CK2d之高電壓位準與供電電壓Vdd相等，亦即，1.2V，且時脈CK卜 時脈CK2，時脈CKld，以及時脈CK2d之低電壓位準與接地電屋vss 相等，亦即’ 0V。當時脈CK1/時脈CKld於高電壓位準時，膽^ 3〇〇 ❹則處於抽樣階段，且當時脈CK2/時脈CR2d於高電壓位準時，MDAC 300則處於保持階段。 當將共模電壓Vcm設為實質上與供電電壓Vdd相等時，差分 〇P-amp 302之輸入級亦應設計為偏壓於供電電壓Vdd。因此，當藉由 時脈CK1接通(turn on)PMOS開關S1，pM〇s開關幻，以及pM〇s 開關S3時’ PMOS開關SI，PMOS開關S2，以及PM〇s開關S3具 有良好的開關特性。類似地，當藉由時脈CK2接通pM〇s開關Sl2 ❿及PMOS開關S13時，PMOS開關S12及PMOS開關S13亦具有良好 的開關特性。 第5圖係為處於接通狀癌之本徵nmos開關、NMOS開關、以及 PMOS開關的輸入電壓與跨導之間的關係之示意圖。請參閱第5圖， 曲線502表示本徵NMOS開關之跨導，曲線504表示PMOS開關之跨 * 導，以及曲線506表示NM〇S開關之跨導。從第5圖可以看出，當共 』 模電壓Vcm實質上與供電電壓Vdd相等(亦即，ay)時，曲線5〇4表 11 201025870 示之跨導較為理想。另一方面，抽樣開關區塊308内之本徵_〇3開 _ 關S4 ’本徵NMOS開關S5，本徵NMOS開關S6 ’以及本徵NMOS 開關S7的跨導由第5圖之曲線502表示，因為閾值電壓V™較小，所 以上述跨導亦較為理想。然而，由於差分輸入信號係為變化信號，本 發明並不限於僅利用本徵NMOS電晶體來實現抽樣開關區塊308内之 開關。於本發明之另一實施例中，每一開關（包含抽樣開關區塊3〇8内 之開關)係利用一個本徵NMOS電晶體並聯一個pM〇s電晶體來實 現。因此’其跨導可視為曲線5〇2與曲線504之結合，則此跨導於0V 至供電電壓Vdd之範圍内不存在死區。 ® 當藉由時脈CK2d接通參考電壓開關區塊31〇時，將第一參考電 壓Vdacn耦接至節點N4之nmos開關兕之跨導可由曲線5〇6表示。 將第二參考電壓Vdacp耦接至節點N5之pM〇s開關沾之跨導可由曲 線504表示。需注意，這並不是本發明之限制。依本發明另一實施例， 參考電壓開關區塊310係利用NM0S電晶體將第一參考電壓施⑶ 耦接至節點N4，並利用本徵NMOS電晶體將第二參考電壓Vdac_❹ 接i節點N5 ’這樣可以減少ADC系統之布線以及控制邏輯數目，其 中，第一參考電壓Vdacn可高於第二參考電壓Vda(jp。 、 此外’當藉由時脈CK2d接通反饋開關區塊312時，本徵聰〇s 開關S10及本徵NM〇S開關S11之跨導亦可由第5圖所示之曲線5〇2 表示。然而’本發明並不限於侧用本徵職^電晶體魏反躺關 區塊3U内之開關。於本發明之另一實施例中，每一開關（包含反饋開、 12 201025870 ，區塊312内之開關)係利用—個本徵丽〇§電晶體與—個f 、，日日體之組合實現。因此，跨導可視為曲線5〇2與曲線5〇4之結合，則 此跨導於GV至供電電壓Vdd之範_不存在死區。 、'口 總體而言’本發明實施例提供之順^藉由設定實質上與供電電 壓相等之共模電壓Vein ’進而顯著地減輕了高速且低壓供電系統内差 分OP-amp之輸入級的設計難度。 ❹ 以上所述僅為本發明之較佳實施例，舉凡熟悉本案之人士援依本 發明之精神所做之紐變倾修飾，皆應涵胁細之申請專利範圍 内。 【圖式簡單說明】 第1圖係依先前技術之開關的示意圖。 ® 第2圖係依第1圖所示之於接通模式的開關的輸入電壓與跨導間 之關係的示意圖。 第3圖係依本發明一實施例之MDAC的示意圖。 第4圖係依本發明一實施例之第3圖所示之mdaC的時脈CK1， 時脈CK2，時脈CKld，以及時脈CK2d的時序圖。 第5圖係依本發明一實施例之處於接通狀態的本徵nmos開關、 .NMOS開關、以及PMOS開關的輸入電壓與跨導間之關係的示意圖。 【主要元件符號說明】 13 VIN :輸入電壓； MP = PMOS電晶體； |VTP| :絕對閾值電壓； 302 :差分 OP-amp ; 306 :電容器區塊； 310:參考電壓開關區塊； 314:OP-amp共用開關區塊； Vss :接地電壓； Vtn :閾值電壓； Vinp .第一輸入信號； Vdacp :第二參考電壓； Non’Nop:輪出節點； 時脈； 201025870 ίο:開關； VDD :供電電壓； MN : NMOS電晶體； 11，12 ’ 502〜506 :曲線； VTN :閾值電壓； 300 ： MDAC ； 304 : OP-amp輸入開關區塊； 308 :抽樣開關區塊； 312 :反饋開關區塊；Oxide Semiconductor (hereinafter referred to as NMOS) transistor MN is composed of a combination of a P-type metal oxide semiconductor (hereinafter referred to as PM0S) transistor MP. When the MDAC operates at a low supply voltage (eg, VDD = 1.2V) and the switch 10 is in the on mode, the switch 1 will form a dead-zone. Please refer to Figure 2. Fig. 2 is a diagram showing the relationship between the input voltage VJN and the transconductance of the nmos transistor MN and the PMOS transistor PN of the switch 10 in the on mode. In Fig. 2, curve 11 represents the transconductance of the nmos transistor, and curve 12 represents the transconductance of the PMOS transistor PN, VDD = 1_2V. As can be seen from Figure 2, when the input voltage VIN is between the voltage (VDD-VTN) and the voltage |VTP|, a dead zone occurs, where 'VTN is the threshold voltage of the NM〇s transistor, and | VTP| is the absolute threshold voltage of the PMOS transistor (abs〇iute threshold voltage). In other words, if the supply voltage VDD is low, there is a dead zone in the switch 1〇. In this case, the capacitor block may not be able to sample the input signal correctly. & Since the common mode voltage of the OP-amp input signal is set, the input stage of 〇p_amp is also biased to VDD/2. However, when the vdD is low supply voltage but the system still needs to operate at a constant speed, it is very difficult to design an input stage with a bias voltage of VDD/2. Therefore, designing a pipeline MC that operates at a lower supply voltage but has a higher operating speed is a current challenge in the ADC field. SUMMARY OF THE INVENTION In order to solve the above technical problems, the present invention provides a high speed and only low power supply of the MDAC 201025870. One embodiment of the present invention provides an MDAC comprising: an OP-amp, a ΟΡ-amp input switch block, a capacitor block, a sampling switch block, a reference voltage switch block, and a feedback switch block. The 〇p_amp is operated under the first supply voltage and the second supply voltage, wherein the first supply voltage is higher than the second supply voltage; the OP-amp input switch block is coupled to the common mode voltage, selectively The common mode voltage is lightly connected to the plurality of input nodes of the OP-amp, wherein all the open relationships included in the 0P_amp input switch block are realized only by the PMOS transistor, and the first supply voltage and the common mode voltage are connected. The first voltage difference is less than a second voltage difference between the common mode voltage and the second supply voltage; the capacitor block is coupled to the OP-amp input switch block, and the corresponding charge or sample corresponding to the input signal is corresponding to the reference signal. The sampling switch block is coupled to the input signal to selectively couple the input signal to the capacitor block; the reference voltage switch block is coupled to the capacitor block, and selectively couples the reference signal to a capacitor block; and the feedback switch block handle is coupled between the capacitor block and the output node of the 〇p_amp for selectively coupling the output node of the OP-amp to the capacitor block. 〇 The MDAC provided by the present invention can perform high-speed operation under the condition of low supply voltage, thereby avoiding the operation caused by the low supply voltage, and solving the technical problems in the above-mentioned ADC field. [Embodiment] Some words are used in the specification and subsequent patent applications to refer to the tuples of the specific '6 201025870. It should be understood by the general knowledge of the field towel that the hardware manufacturer may use, different; This specification and the scope of the patent application do not use the difference in name as the way to distinguish the tuple, but the difference in function of the tuple as the criterion for distinguishing. The term "including" as used throughout the specification and subsequent claims is an open-ended term that should be interpreted as "including but not limited to". In addition, the term "coupling" is used here to automatically include the electrical connection means. Thus, if the first device is described as being connected to the second device, it is meant that the first device can be directly electrically connected to the first device or indirectly electrically connected to the second device through other devices or connection means. Please refer to Figure 3. Fig. 3 is a schematic view of a person (9) according to an embodiment of the present invention. The MDAC 300 includes a differential 〇p_amp 3〇2, a 〇p_amp input switch block 3〇4, a capacitor block 306, a sampling switch block 3〇8, a reference voltage switch block 31〇, and a feedback switch block 312. The differential 〇p_amp 3〇2 operates under the supply voltage Vdd and the ground voltage Vss. It should be noted that in order to more clearly describe the spirit of the present invention, the © supply voltage Vdd is a low supply voltage, for example, 丨.2V, and the ground voltage Vss is 〇v. The OP-amp input switch block 3〇4 is coupled to the common mode voltage Vcm for selectively coupling the common mode voltage Vcm to the input nodes Nip and Nin of the differential 〇P-amp 302, which is included in the OP- All open relationships within the amp input switch block 304 are implemented using only the pM〇s transistor to reduce the impedance and capacitance of the OP-amp input switch block 304. Capacitor block 306 is coupled to 〇P-amp input switch block 304' for sampling the charge corresponding to the differential input number and sampling the charge corresponding to the differential reference signal. The differential input signal 201025870 includes a first input signal Vinn and a second input signal Vinp. The sampling switch block 308 is coupled to the first input signal Vinn and the second input signal Vinp for selectively coupling the > first input signal Vinn and the second input signal Vinp to the capacitor block 306. The differential reference signal includes a first reference voltage Vdacn and a second reference voltage Vdacp, wherein the first reference voltage vdacn can be higher than the second reference voltage Vdacp. The reference voltage switch block 310 is coupled to the capacitor block 306 for selectively coupling the first reference voltage Vdacn or the second reference voltage Vdacp to the capacitor block 306 according to the output of the secondary ADC (not shown). The feedback switch block 312 is coupled between the capacitor block 306 and the output nodes Nop and Non of the differential Ο 〇 P-amp 302 for selectively coupling the output nodes Nop and Non of the differential 〇p_amp w 302 to Capacitor block 306. The MDAC 300 is configured in a ΟΡ-amp common configuration in accordance with an embodiment of the present invention, and thus the mdac 300 further includes an OP-amp shared switch block 314, however, this is not a limitation of the present invention. The OP-amp shared switch block 314 is connected between the input nodes Nip and Nin of the differential 〇P-amp 302 and the OP-amp input switch block 304, and is used for selection when the MDAC 300 enters the hold phase. The input node of the differential OP_amp 3〇2 and Nin are connected to the OP-amp input switch block 304, or when the MDAC 300 enters the sampling phase, the input node Nip for the differential 0P_amp 3〇2 is used. And disconnected from the OP-amp input switch block 304, wherein all of the open relationships contained in the OP-amp shared switch block 314 are implemented using only the PM〇s transistor. Further, the common mode voltage Vcm is substantially equal to the supply voltage Vdd. Again, this is not a limitation of the invention. In other words, the common mode voltage Vcm is selected as a condition that the difference between the supply voltage Vdd and the common mode voltage Vcm is the difference between the common mode voltage Vem and the ground voltage %_second voltage. The difference is small. More specifically, * the common mode voltage Vem can be selected to meet the condition that the first voltage difference is less than a quarter of the voltage difference between the supply voltage Vdd and the ground current svss, and the first voltage difference is Not less than four points of the voltage difference between the supply voltage Vdd and the ground voltage Vss. See Figure 3 again. As shown in FIG. 3, the 〇p_amp input switch block 3〇4 ❹ includes a PMOS switch SI' PMOS switch S2 and a PMOS switch S3. PMOS switch SI ' PMOS switch S2 and PMOS switch S3 are controlled by clock CK1, wherein PMOS switch S1 is consumed between node N1 and common mode voltage ycm, pM 〇 s switch S2 is coupled to node N2 and common mode voltage Between Vcm, and the pM〇s switch is decremented between node N1 and node N2. The capacitor block 306 includes a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4. The capacitor C1 is coupled between the node N3 and the node N1, and the capacitor C2 is coupled between the node N4 and the node N1, and the capacitor C3 is coupled. Connected between the node N5 and the node N2, and the capacitor C4 is coupled between the node N6 and the node N2. The sampling switch block 308 is controlled by the clock CKld, and the sampling switch block 308 includes the intrinsic NMOS switch S4, the intrinsic NMOS switch S5, the intrinsic nmos switch S6, and the intrinsic NMOS switch S7, wherein the intrinsic NM〇s The switch S4 is connected between the first input signal Vinn and the node N3, and the eigen_〇|§ switch is coupled between the first input signal I Vinn and the node N4, and the intrinsic NMOS switch S6 is coupled to the second input. The signal Vinp and the node N5, and the intrinsic nmos switch S7 are coupled between the second input signal νώρ 201025870 and the node N6. In general, the intrinsic nmqs have a low threshold of approximately 〇 iv-0.2V. The value voltage Vtn. > The reference voltage switch block 310 is controlled by the clock cK2d, and the reference voltage switch block 310 includes an NMOS switch S8 'PMOS switch S9, an NMOS switch S15, and a PMOS switch S14, wherein the NMOS switch S8 is coupled to the first reference Between the voltage Vdacn and the node N4, the PMOS switch S9 is coupled between the second reference voltage vdacp and the node N5, the NMOS switch S15 is coupled between the first reference voltage vdacn and the node N5, and the PMOS switch S14 is coupled to the The second reference voltage Vdacp is between the node N4.反馈 The feedback switch block 312 is controlled by the clock CK2d, and the inverse switch block 312 includes the intrinsic NMOS switch S10 and the intrinsic nmos switch sn, wherein the intrinsic employee is coupled to the output node N〇p and the node by the switch S10. Between N3, and the intrinsic switch sii are coupled between the output node Non and the node N6. 〇P-amP shared switch block 3! 4 is controlled by clock (five), 〇p_a which share switch ◎ block 314 contains PM0S_S12 and pM〇s switch si3, wherein pM〇s switch S12 is coupled to phase N1 Between the input node running and the off (10) switch SB is coupled between the node N2 and the input node Nip. Fig. 4 is a timing chart of the clock pulse dryness _ CK2, clock CKld, and clock (10) shown in Fig. 3 according to an embodiment of the present invention. As shown in Figure 4, the lion r is the delayed clock of the clock (5), and the clock (10) is the delay of the yang. That is, the clock CK1 is aligned with the rising edge of the clock. CKld, and the falling edge of the clock (f) d 10 201025870 is later than the falling edge of the clock CK1, and the clock CK2 is aligned with the upper edge of the clock and the rising edge. The falling edge of the clock CK2d is later than the falling edge of the clock CK2. The clock CK1 and the clock CK2 are non-overlapped, and the clock cKld does not overlap with the clock CK2d. The high voltage level of clock CK1, clock CK2, clock CKld, and clock CK2d is equal to supply voltage Vdd, that is, 1.2V, and clock CK clock CK2, clock CKld, and clock CK2d The low voltage level is equal to the grounded electric house vss, which is '0V. When the CK1/clock CKld is at the high voltage level, the biliary 〇〇3〇〇 is in the sampling stage, and when the CK2/clock CR2d is at the high voltage level, the MDAC 300 is in the holding phase. When the common mode voltage Vcm is set to be substantially equal to the supply voltage Vdd, the input stage of the differential 〇P-amp 302 should also be designed to be biased to the supply voltage Vdd. Therefore, when the PMOS switch S1 is turned on by the clock CK1, the pM〇s switch is phantom, and the pM 〇s switch S3, the PMOS switch SI, the PMOS switch S2, and the PM 〇s switch S3 have good switches. characteristic. Similarly, when the pM〇s switch S12 and the PMOS switch S13 are turned on by the clock CK2, the PMOS switch S12 and the PMOS switch S13 also have good switching characteristics. Figure 5 is a graphical representation of the relationship between the input voltage and the transconductance of the intrinsic nmos switch, NMOS switch, and PMOS switch in an on-cancerous cancer. Referring to Figure 5, curve 502 represents the transconductance of the intrinsic NMOS switch, curve 504 represents the cross-section of the PMOS switch, and curve 506 represents the transconductance of the NM〇S switch. As can be seen from Fig. 5, when the common mode voltage Vcm is substantially equal to the supply voltage Vdd (i.e., ay), the transconductance shown by the curve 5〇4 Table 11 201025870 is ideal. On the other hand, the eigen_〇3_off S4' intrinsic NMOS switch S5, the intrinsic NMOS switch S6' and the intrinsic NMOS switch S7 in the sampling switch block 308 are represented by a curve 502 of FIG. Since the threshold voltage VTM is small, the above-described transconductance is also preferable. However, since the differential input signal is a varying signal, the present invention is not limited to implementing switching within the sampling switch block 308 using only the intrinsic NMOS transistor. In another embodiment of the invention, each switch (including a switch within the sampling switch block 3〇8) is implemented using an intrinsic NMOS transistor in parallel with a pM〇s transistor. Therefore, its transconductance can be regarded as the combination of the curve 5〇2 and the curve 504, and there is no dead zone in the range of 0V to the supply voltage Vdd. When the reference voltage switch block 31 is turned on by the clock CK2d, the transconductance of the nmos switch 将 coupling the first reference voltage Vdacn to the node N4 can be represented by a curve 5〇6. The transconductance of the pM 〇s switch coupled to the second reference voltage Vdacp to the node N5 can be represented by a curve 504. It should be noted that this is not a limitation of the present invention. According to another embodiment of the present invention, the reference voltage switching block 310 couples the first reference voltage (3) to the node N4 by using the NMOS transistor, and connects the second reference voltage Vdac_ i to the i node N5 ' using the intrinsic NMOS transistor. This can reduce the wiring of the ADC system and the number of control logics, wherein the first reference voltage Vdacn can be higher than the second reference voltage Vda (jp. Further, when the feedback switch block 312 is turned on by the clock CK2d, The transconductance of the Shuncon s switch S10 and the intrinsic NM 〇 S switch S11 can also be represented by the curve 5 〇 2 shown in Fig. 5. However, the present invention is not limited to the side eigenaction ^ electric crystal Wei lie down A switch within block 3U. In another embodiment of the invention, each switch (including feedback on, 12 201025870, switch in block 312) utilizes an intrinsic 〇 电 transistor and a f Therefore, the combination of the sun and the body is realized. Therefore, the transconductance can be regarded as the combination of the curve 5〇2 and the curve 5〇4, and the cross-guided GV to the supply voltage Vdd has no dead zone. The embodiment of the present invention provides a smooth connection with the supply voltage by setting The common mode voltage Vein 'and thus significantly reduces the design difficulty of the input stage of the differential OP-amp in the high speed and low voltage power supply system. ❹ The above is only a preferred embodiment of the present invention, and those who are familiar with the case The modification of the spirit of the present invention should be within the scope of the patent application. [Simplified Schematic] Figure 1 is a schematic diagram of the prior art switch. ® Figure 2 is based on Figure 1. A schematic diagram showing the relationship between the input voltage and the transconductance of the switch in the on mode. Fig. 3 is a schematic diagram of an MDAC according to an embodiment of the present invention. Fig. 4 is a third diagram of an embodiment of the present invention. The timing diagram of the clock CK1, the clock CK2, the clock CKld, and the clock CK2d of the mdaC shown. Fig. 5 is an intrinsic nmos switch, an .NMOS switch, in an on state according to an embodiment of the present invention, And the relationship between the input voltage of the PMOS switch and the transconductance. [Main component symbol description] 13 VIN: input voltage; MP = PMOS transistor; |VTP|: absolute threshold voltage; 302: differential OP-amp; 306: Capacitor block; 310: reference voltage on Close block; 314: OP-amp shared switch block; Vss: ground voltage; Vtn: threshold voltage; Vinp. first input signal; Vdacp: second reference voltage; Non'Nop: turn-out node; clock; 201025870 Ίο: switch; VDD: supply voltage; MN: NMOS transistor; 11, 12 '502~506: curve; VTN: threshold voltage; 300: MDAC; 304: OP-amp input switch block; 308: sample switch block ; 312: feedback switch block;
Vdd :供電電壓；Vdd: supply voltage;
Vcm :共模電壓；Vcm: common mode voltage;
Vinn :第一輸入信號；Vinn: the first input signal;
Vdacn :第一參考電壓；Vdacn: the first reference voltage;
Nin，Nip :輸入節點； N1〜N6 :節點； CK1，CKld，CK2d，CK2 C1-C4 :電容； S1 〜S3，S9 ’ S12〜S14 : PMOS 開關。 S4〜S7，S10〜S11 :本徵NMOS開關； S8，S15 : NMOS 開關。Nin, Nip: input node; N1~N6: node; CK1, CKld, CK2d, CK2 C1-C4: capacitance; S1~S3, S9 'S12~S14: PMOS switch. S4~S7, S10~S11: Intrinsic NMOS switch; S8, S15: NMOS switch.