TWI780914B - Input buffer and method for buffering voltage input signal - Google Patents

Abstract

The trend in wireless communication receivers is to capture more and more bandwidth to support higher throughput, and to directly sample the radio frequency (RF) signal to enable re-configurability and lower cost. Other applications like instrumentation also demand the ability to digitize wide bandwidth RF signals. These applications benefit from input circuitry which can perform well with high speed, wide bandwidth RF signals. An input buffer and bootstrapped switch are designed to service such applications, and can be implemented in 28nm complementary metal-oxide (CMOS) technology.

Description

Input buffer and method of buffering voltage input signal

The disclosure of the present invention relates to the field of integrated circuits, and more specifically, to the input circuit of an analog-to-digital converter (ADC).

In many electronic device applications, an analog-to-digital converter (ADC) can convert an analog input signal into a digital output signal, such as for further digital signal processing or storage by digital electronic devices. Broadly speaking, an analog-to-digital converter can convert analog electrical signals representing real environmental phenomena, such as light, sound, temperature, electromagnetic waves or pressure, for data processing purposes. For example, in a measurement system, a sensor may perform a measurement and generate an analog signal, which is then provided to an analog-to-digital converter as input to generate a digital output signal for further processing. In another example, a transmitter can use electromagnetic waves to generate an analog signal to carry information in the air, or a transmitter can emit an analog signal to carry information through a cable, which is provided to An analog-to-digital converter at a receiver serves as input to generate a digital output signal, eg for further processing by digital electronics.

Due to its wide variety of applications, the analog-to-digital converter memory Such as broadband communication (broadband communication) system, audio system, receiver system, etc. Since various applications have different requirements for performance, power, cost, and size, it is important to design the internal circuits of an analog-to-digital converter. Analog-to-digital converters are used in a wide variety of applications, including communications, energy, medical care, instrumentation and measurement, motor and power control, industrial automation, and aerospace/defense. As the number of applications requiring analog-to-digital converters increases, the need for fast and accurate conversions also grows.

The invention provides an input buffer, which includes an input, a push-pull circuit, and a first level shifter. The above-mentioned input receives a voltage input signal. The push-pull circuit outputs a voltage output signal on an output, wherein the push-pull circuit includes a first transistor of a first type and a second transistor of a second type complementary to the first type. The first level shifter is coupled to the above-mentioned input, and is used for shifting the voltage level of the voltage input signal by the first voltage offset across the first level shifter, and generating a first level offset voltage signal to bias the first transistor. The first voltage offset provided by the first level shifter is independent of the frequency of the voltage input signal.

The present invention provides a method for buffering a voltage input signal, comprising the following steps: using the first voltage shift of a first level shifter, the level shifts the voltage input signal to generate a first signal, wherein the first voltage The offset is independent of the frequency of the voltage input signal; a first transistor of the first type is offset by a first signal; a second transistor of a second type complementary to the first type is offset by a second signal , wherein the first transistor and the second transistor system are coupled in a push-pull architecture; and by A voltage output signal is output from the first transistor and the second transistor.

The present invention provides a device comprising a device for receiving an input signal, a push-pull device for generating an output signal, and a passive device for generating a first signal to bias a first transistor of the push-pull device. The first signal is coupled to the input signal across all frequencies of the input signal.

102: Input buffer

104: Transmission line

106: Sampler

MN108: Transistor

110: switch

C _S 112: sampling capacitor

104: Transmission line

200: Bootstrap switching circuit

MP202: Transistor

MP204: Transistor

MN206: Transistor

MN208: Transistor

MN210: Transistor

MN212: Transistor

MP214: Transistor

MN216: Transistor

MN218: Transistor

MN224: Transistor

302: jump start circuit

MN404: Transistor

502: sensing circuit

602: Step

604: Step

606: Step

MN702: Transistor

703: level shifter

MP704: Transistor

705: level shifter

MN706: Transistor

707: level shifter

MP708: Transistor

709: level shifter

MN710: Transistor

711: level shifter

MP712: Transistor

713: level shifter

716: level shifter

1002: step

1004: step

1006: step

In order to provide a complete understanding of the disclosed content and technical features of the present invention, please refer to the following description and reference drawings, in which similar numbers represent the same components: FIG. 1 is a front end of an analog-to-digital converter in an embodiment disclosed in the present invention.

FIG. 2 is a bootstrap switching circuit in an embodiment disclosed in the present invention.

FIG. 3 is a bootstrap switching circuit with accelerated startup in an embodiment disclosed in the present invention.

4A to 4B are an implementation example of a jump start circuit in the disclosed embodiment of the present invention.

5A to 5C are another implementation example of the jump start circuit in the disclosed embodiment of the present invention.

FIG. 6 is a flowchart of a method for accelerating the start-up of a sampling circuit.

FIG. 7 is an example of an input buffer in the disclosed embodiment of the present invention.

FIG. 8 is an example of a level shifter in the disclosed embodiment of the present invention.

FIG. 9 is another example of the input buffer in the disclosed embodiment of the present invention.

FIG. 10 is a flow chart of buffering an input signal according to an embodiment of the disclosure.

overview

The development of wireless communication receivers tends to receive more bandwidth to support higher processing power and directly sample radio frequency (RF) signals to provide reconfigurability and reduce cost. Other applications such as instrumentation also require the ability to digitize broadband RF signals. Input circuits that can properly handle high-speed, wide-band RF signals can be beneficial for these purposes. An input buffer and bootstrap switch are designed to serve these purposes and can be implemented in 28 nanometer (nm) complementary metal oxide semiconductor (CMOS) technology.

High Speed Analog to Digital Converter

An analog-to-digital converter (ADC) is an electronic device that converts a continuous physical quantity (physical quantity) carried by an analog signal into a digital output or number representing the amplitude of the quantity (or into a digital signal). An analog-to-digital converter can be defined by the application requirements: its bandwidth (the frequency range over which an analog signal can be properly converted to a digital signal) and its resolution (the maximum number of discrete levels an analog signal can be divided into and represented in a digital signal) ). Analog-to-digital converters also have various specifications for quantifying the dynamic performance of analog-to-digital converters, including signal-to-noise-distortion ratio (SINAD), effective number of bits (ENOB), signal-to-noise ratio (SNR), Total harmonic distortion (THD), total harmonic distortion plus noise (THD+N), and spurious free dynamic range (SFDR). Analog-to-digital converters come in a variety of different designs, which can be selected based on application needs and specifications.

High-speed applications are particularly important in communications and instrumentation. Input message Signal systems may have frequencies in the gigahertz range, while analog-to-digital converters may require samples in the billion-per-second range. High-frequency input signals can place various demands on the circuitry that receives the input signal, such as the "front-end" circuitry of an analog-to-digital converter. The circuit must be capable of high-speed processing, and in some applications, the circuit needs to meet specific performance requirements, such as SNR and SFDR. It is important to design an analog-to-digital converter that meets speed and power efficiency requirements.

FIG. 1 shows a front end of an analog-to-digital converter in an embodiment of the present disclosure. Generally, an input signal V _IN (such as a high frequency input signal in the MHz range) is provided to an input buffer 102, and the output V _INX of the input buffer is provided to a sampler 106, wherein from the input buffer The output of the device, and the input signal in the form of V _INX is sampled on a sampling capacitor C _S 112 .

A transistor MN108 (such as an N-type complementary metal oxide field (CMOS) transistor, or NMOS transistor) is provided so that the input signal V _INX can be provided to the sampling capacitor C _S 112 . Transistor MN108 may sometimes represent the sampling switch herein. During a sampling operation, transistor MN 108 is on and switch 110 is off. The output V _INX of the input buffer may pass through a transmission line (T-LINE) 104 connected from the input buffer 102 to the sampler 106 . When the analog-digital converter has a plurality of analog-digital converters connected in parallel (for example, the analog-digital converter is a time-sequence interleaved analog-digital converter or a random clock-interleaved analog-digital converter), it is provided with a plurality of parallel connections (mutual matching) samplers, including sampler 106. Multiple (mutually matched) transmission lines may be included to provide the output signal V _INX from a common input buffer 102 to the samplers. The time-interleaved ADC or the random time-interleaved ADC can sample the input signal V _INX one at a time. In some cases, a reference ADC and one of the time-interleaved ADCs sample the output signal _VINX at substantially the same time. For a time-interleaved ADC or a random time-interleaved ADC, at least one of the samplers may be turned off at any time when the input buffer is loaded. To reduce SFDR degradation, the rear gates of the transistors in the samplers that are coupled to receive the input signal V _INX (such as transistor MN108 ) can be connected to a negative voltage, such as -1 V _INX , by This minimizes nonlinearities in the transistors.

bootstrap switching circuit

As shown in Fig. 1, the start-up time of the transistor _MN108 is extremely fast enough to allow V _INX to be sampled to the sampling capacitor CS 112, which is very important, especially for high-speed applications. For the example of an analog-to-digital converter with a sample rate of 10 billion samples per second, transistor MN 108 must be turned on fast enough to allow input signal V _INX to be sampled onto sampling capacitor _CS 112 with only interval of 100 millionths of a second. The time required to activate transistor MN108 may depend on the transistor properties of transistor MN108 itself, and the signal V _BSTRP driving transistor MN108 at gate V _INX relative to the source signal. The examples shown here refer to signals that go up or down, representing different logic levels of those signals.

FIG. 2 shows a bootstrap switching circuit 200 according to an embodiment of the present invention. The bootstrap switching circuit includes the transistor MN108 of FIG. 1, which receives the input signal V _INX at its source, and its drain is connected to a plate of a sampling capacitor (such as the sampling capacitor C _S 112 of FIG. 1 ). . The bootstrap switching circuit also includes a bootstrap gate voltage generator (circuit) to generate a gate voltage signal V _BSTRP for driving the gate of the transistor MN108 (sampling switch). The bootstrap gate voltage generator activates the gate voltage V _{BSTRP in a manner that ensures fast start-up of the transistor MN108} .

The bootstrap gate voltage generator can receive V _INX and includes a start-up capacitor for generating a bootstrap voltage equal to V _INX +V _BOOT , the bootstrap gate voltage generator has a positive feedback loop, The positive feedback loop uses V _INX as the input of the positive feedback loop, and the positive feedback loop includes a startup capacitor in the path of the positive feedback loop. One output of the positive feedback loop generates a gate voltage signal V _BSTRP that drives the gate of the transistor MN108 (the sampling switch).

The positive feedback loop is used to transmit the gate voltage signal V _{BSTRP at a} high speed, which is enough to ensure that the transistor MN108 can be activated quickly. The positive feedback loop is connected to the input signal V _INX for bootstrapping, wherein the goal of the positive feedback loop is to drive the gate voltage signal V _BSTRP to V _INX plus the voltage V _BOOT (V _BOOT is the voltage across the startup capacitor C _BOOT ), To start the transistor MN108. More specifically, the positive feedback loop drives the gate voltage signal V _BSTRP high enough to result in a sufficient voltage V _GS across the gate and source to enable transistor MN 108 . The bootstrap gate voltage generator is driven by a clock signal CLK, and CLKB is the opposite version of CLK. The bootstrap gate voltage generator can also receive a charge phase clock signal CLKB _BST , which controls the time point of the charge phase of the boot capacitor C _BOOT . Transistor MN108 is desirably turned on quickly when CLK goes high, and transistor MN108 is desirably turned off when CLK goes low.

During the charging phase (when both CLKB and CLKB _BST are high), transistor MN224 and transistor MN210 (such as NMOS transistor) are activated to charge a voltage V _{BOOT across the startup capacitor C BOOT (} such as V _BOOT =V _DD -V _SS ). Start the system with transistor MN224 and connect the top plate of capacitor C _BOOT to V _DD . Start the system with transistor MN210 and connect the bottom plate of capacitor C _BOOT to V _SS . If V _SS is the ground plane, the boot capacitor C _BOOT is charged to V _DD .

Before the positive feedback loop starts, node X is at V _DD because CLK was low in the previous phase (charging phase). CLK drives the gate of transistor MP214 (such as a P-type complementary metal oxide field effect transistor (CMOS) or PMOS transistor). A lower CLK will turn on transistor MP214. When transistor MP214 is on, the gate (node X) of transistor MP214 is at _VDD . When node X is at V _DD and CLKB is high, transistor MP202 (eg, a PMOS transistor) is off. Here, the transistor MP202 may refer to the output transistor that drives the gate (sampling switch) of the transistor MN108 to output V _BSTRP . V _BSTRP is in a lower state, with the sample switch such as hold transistor MN108 in the off state.

CLK goes low (or CLKB goes high) to start the positive feedback loop. When the CLKB of the gate of the drive transistor MP204 (such as a PMOS transistor) decreases (such as when CLK rises), the transistor MP204 (such as a PMOS transistor) is activated, and the drain of the transistor MN208 (such as an NMOS transistor) Pulling up to close to V _DD (raised) and pulling up the drain of transistor MN206 (eg, NMOS transistor) (eg, V _DD ), thereby raising the V _BSTRP electrode.

V _BSTRP drives the gates of transistor MN216 (eg, NMOS transistor) and transistor MN212 (eg, NMOS transistor). Transistor MN212 may refer to the input transistor because transistor MN212 receives the input signal V _INX . A rise in V _{BSTRP turns} on transistor MN216 (eg, NMOS transistor) and transistor MN212 (eg, NMOS transistor). At the same time, due to the rise of CLK, the transistor MP214 is turned off. With transistors MN216 and M212 enabled, the gate of transistor MP202, eg, node X, is effectively connected to V _INX .

In a previous phase (eg, charging phase), the boot capacitor C _BOOT is charged to have V _BOOT across the boot capacitor. When the positive feedback loop is connected, the gate of the transistor MP202 can have V _INX , and the source of the transistor MP202 can have a voltage of V _INX +V _BOOT . Transistor MP202 is activated to raise V _BTSTRP to V _INX +V _BOOT , thereby increasing the voltage across the gate and source V _GS of the sampling switch (eg, transistor MN108 ) (eg, V _BSTRP -V _INX =V _BOOT ) to make it start. When V _BTSTRP rises, the raised V _BTSTRP loops through transistor MN201 and transistor MN212, thereby further raising V _BTSTRP again to activate transistor MN108. Therefore, the positive feedback loop system can provide fast start-up of transistor MN108.

In some cases, when the gate of transistor MP202, such as node X, is connected to V _INX , the positive feedback loop is activated, and the positive feedback loop helps drive both transistor MN216 and transistor MN212 of node X. The latter can delay start-up, thereby greatly slowing down the positive feedback loop when node X cannot be connected to V _INX in time.

Consider that when V _INX (such as the source of transistor MN212) is close to V _DD at a certain moment, and when CLKB is lowered at startup (startup means that CLKB just goes down, or CLK just goes up), transistor MN216 The gate of the transistor MN212 (such as the V _BSTRP electrode) is also close to V _DD . Node X is at V _DD at startup (since CLK is low and node X is at V _DD through transistor MP 214 ). This state is such that all terminals of transistor MN216 are approximately at V _DD . Transistor MN216 and transistor MN212 may not have sufficient voltage (V _GS ) across the gate and source of the respective transistors to activate thereby. Therefore, due to insufficient V _GS , transistors MN216 and MN212 may barely/weakly turn on, thus slowing down the positive feedback effect of the loop. The loop eventually starts to operate when transistors MN216 and transistor MN212 are more fully turned on and pull node X closer to V _INX to turn on transistor MP202, which allows V _INX +V _BOOT to pass through transistor MP202 and towards the transistor MP202. The gate of crystal MN108 makes V _BSTRP rise.

Jump start the positive feedback loop

In order to solve the slowdown of the positive feedback loop, a jump start circuit can be implemented to quickly start the transistor MP202 (output transistor) when the positive feedback loop is activated, so that V _INX + V _BOOT can pass through the transistor MP202 more quickly and The flow flows to the transistor MN108, so that V _{BSTRP rises} faster, thereby starting the transistor MN216 and the transistor MN212 more quickly. A faster bootstrap switching circuit is thus achieved.

FIG. 3 shows a boosted bootstrap switching circuit 300 in an embodiment of the present disclosure. The bootstrap switching circuit 300 has a sampling switch, such as transistor MN108, which receives a voltage input signal, such as V _INX , and a gate voltage, such as V _BTSTRP . The bootstrap switching circuit also has a bootstrap voltage generator, which generates the gate voltage, such as V _BTSTRP , for the sampling switch.

The bootstrap switching circuit includes a positive feedback loop to generate the gate voltage to activate the sampling switch. The positive feedback loop may include an input transistor, such as transistor MN212, for receiving the voltage input signal, such as V _INX , and an output transistor, such as transistor MP202, for outputting the gate voltage of the sampling switch. The positive feedback loop has a boot capacitor, such as C _BOOT , which can be used to generate a boot voltage, such as V _INX +V _BOOT . Since the sampling switch, such as transistor MN108, has V _INX at its source, an activation voltage at the gate of the sampling switch activates the sampling switch. In other words, the positive feedback loop activates the sampling switch, such as the transistor MN108 , by driving the gate voltage to the start-up voltage generated according to the voltage input signal V _INX and the voltage across the start-up capacitor C _BOOT . The input transistor, such as transistor MN212, is coupled to a first plate of the startup capacitor. The source of the output transistor, such as transistor MP202, is coupled to a second plate of the startup capacitor.

The operation of the positive feedback loop is to use the gate voltage as positive feedback to drive the transistors in the loop, such as transistor MN212 and transistor MN216. These transistors then drive the gate voltage of the output transistor to _VINX , such as the gate voltage of transistor MP202, and assist the output transistor, such as transistor MP202, to pass the startup voltage or drive the gate voltage to the startup voltage . The start voltage can start the sampling switch, such as transistor MN108.

For the positive feedback loop example shown, the input transistor, such as transistor MN212, is driven by the gate voltage of the sampling circuit, such as the gate voltage of transistor MN108. The positive feedback loop further has a first transistor, such as transistor MN216 , which is coupled to the gate of the output transistor, such as transistor MP202 , and a drain of the input transistor, such as transistor MN212 . The first transistor is also driven by the gate voltage of the sampling switch. After being combined with each other, the first transistor and the input transistor can drive the node X to V _INX during the function of the positive feedback loop when activated.

The bootstrap switching circuit also includes a jump start circuit 302 for enabling the output transistor for a limited period during the start-up of the output capacitor during the positive feedback loop start-up phase. The jump start circuit 302 is coupled to the node X, for example, the gate of the transistor MP202, wherein the transistor MP202 is the output transistor of the positive feedback loop. In some embodiments, the jump-start circuit 302 can provide/output a signal at node X, for example, to turn on the transistor MP202 briefly when CLKB goes low, so as to jump-start the positive feedback loop. After the limited period, the jump start circuit 302 stops enabling the output transistor and enables the positive feedback loop to operate.

In other words, the jump start circuit 302 is connected to the output transistor MP202 when the positive feedback loop function starts, and is separated from the output transistor MP202, so that the positive feedback loop can drive the output transistor MP202 (making the positive feedback loop function to drive node X to V _INX ). The jump start circuit 302 can help the positive feedback loop move faster during the delayed start (short time period) of transistor MN216 and transistor MN212. The jump start circuit 302 can temporarily pull the node X to a low logic level (such as a ground plane or some other basic voltage) by the gate of the transistor MP202, and jump start the positive feedback loop function, so that the transistor MP202 starts up, and makes V _INX +V _BOOT (such as the top plate voltage of the startup capacitor C _BOOT ) flow through the output transistor MP202 to the gate of the transistor MN108 more quickly, so that V _BSTRP rises faster.

Note that jump start circuit 302 only temporarily pulls node X to a low logic level, but preferably does not allow node X to fully reach ground or low logic level. Pulling node X all the way to ground can cause unintended stress on transistor MP202 because the source of transistor MP202 will touch V _INX +V _BOOT . Furthermore, jump-start circuit 302 quickly "releases" node X (or ceases to pull node X to a low logic level) so that the positive feedback loop can operate, and is preferably tied to transistor MN216 and transistor MN212. Fully connect node X before V _INX to "release". The timing of the jump start circuit 302 may vary according to the implementation.

During the start-up phase of the positive feedback loop, and before CLKB goes low, the node X is at V _DD to keep the output transistor MP202 off and keep V _BSTRTP low when the boot capacitor C _BOOT is charged. However, when node X starts at V _DD during the start-up phase of the positive feedback loop action, node X slows down the feedback mechanism. The jump start circuit 302 quickly activates the transistor MP202 by pulling the node X to an appropriate logic level, so that the node X starts at V _DD and will no longer hinder the action speed of the feedback loop.

In some cases, the gate of an additional transistor MN218 (such as an N-type neo-oxide semiconductor transistor) can be connected to CLK, and its source can be connected to the drain of an input transistor such as transistor MN212 (and the transistor The source of MN216) and its drain are connected to node X (eg, the gate of the output transistor MP202) to help connect node X to V _INX during the positive feedback loop. The additional transistor system is controlled by a clock signal, such as CLK, that drives the positive feedback loop. When CLK rises during the start-up phase, transistor MN218 is turned on to help connect node X to V _INX in an attempt to overcome the delayed start-up of transistor MN216. The operation of the jump start circuit 302 is different from the additional transistor MN218, and the jump start circuit 302 can provide a greater speed increase of the bootstrap switching circuit than the additional transistor MN218 alone.

The timing of pulling node X to a low logic level and releasing it quickly must be considered or based on factors such as the circuit design, circuit manufacturing process, and parasitic properties in the bootstrap switching circuit. The point in time can be determined by simulation or test operation of the circuit. The point in time is variable or controllable. In some cases, the point in time may depend on at least one voltage level or signal in the bootstrap circuit, which may indicate when the jump-start circuit 302 should initiate the pull-down and/or stop the pull down effect.

If the transistor MP202 is a PMOS transistor (in a complementary/equivalent implementation), the jump start circuit 302 can provide a temporary pull-up effect to quickly jump start the feedback loop.

Example of Jump Start Circuit Implementation

4A to 4B show an implementation example of a jump start circuit according to the disclosed embodiment of the present invention. In the example shown in FIG. 4A , the jump start circuit includes a transistor MN404 (such as an NMOS). Transistor MN404 receives CLKB at the source (used to activate the positive feedback loop, in the form of CLK and CLKB) and receives CLKB _DEL at the gate. CLKB decreases during the start-up phase of this positive feedback loop. CLKB _DEL is a delayed version of CLKB, so when CLKB decreases, CLKB _DEL remains high for a brief period. During this period, when CLKB is low and CLKB _DEL is high, transistor MN404 is enabled and pulls node X to the low logic level of CLBK (eg, ground plane). When the delay period is over, CLKB _DEL goes low to turn off transistor MN404. The jump start circuit effectively pulls node X to a low logic level and quickly releases node X, allowing the positive feedback loop to continue its operation. In other words, the transistor system is activated by a delayed version of the clock signal to output the clock signal, thereby activating the output transistor for a limited period of time.

As shown in FIG. 4B , the jump start circuit may include two inverters for generating the delayed version of the clock signal CLKB _DEL according to the clock signal CLKB. Therefore, CLKB _DEL can have the same polarity as CLKB, but with two inverter delays. Other embodiments for generating CLKB _DEL with a desired amount of delay are known from this disclosure, including the use of a pass gate, resistor-capacitor delay circuits, and the like. The embodiment shown in Figure 4B is not intended to be limiting.

5A to 5C show another implementation example of the jump start circuit according to the disclosed embodiment of the present invention. In the example shown in FIG. 5A , the jump start circuit includes a switch 501 controlled by a control signal CTRL. The switch 501 connects a gate of the output transistor (such as transistor MP202 ) to a bias voltage V _ON , thereby enabling the output transistor. The control signal can have a pulse to close the switch 501 . The pulse cross-activates the output transistor for a limited period (pulls the gate towards the bias and releases the gate, allowing the positive feedback loop to operate). FIG. 5B shows an example waveform of the control signal CTRL with a short pulse to close the switch 501 and pull node X towards the bias voltage V _ON , and quickly release node X (open the switch and pull node X from V ON . _ON cuts the connection), allowing the positive feedback loop to continue its operation. The voltage V _ON can be an appropriate bias voltage for turning on the transistor MP202, such as a ground plane, or other appropriate voltage levels. Switch 501 may be implemented using transistors.

In some embodiments, the jump start circuit includes a sensing circuit 502 (as shown in FIG. 5C ), thus implementing a closed loop delay. The sensing circuit activates the jump start circuit according to at least one state of the bootstrap switching circuit indicating the start phase of the positive feedback loop. A closed-loop delay means that the timing at which the control signal CTRL or the jump-start circuit pulls node X to a low logic level and/or releases node X depends on at least one state of the bootstrap switching circuit. Preferably, the at least one state is indicative of an activation phase of the positive feedback loop. The sensing circuit 502 can sense a voltage V _SENSE and generate the control signal CTRL accordingly. The voltage V _SENSE can represent a voltage at any applicable node in the bootstrap switching circuit. The node can be a node in the positive feedback loop.

In one example, the sensing circuit 502 includes a comparator coupled to the source of the transistor MP202 to compare the voltage of the source of the transistor MP202 with a predefined threshold, or with the positive feedback loop Another node for comparison. The voltage across the predefined threshold can indicate the active state of the positive feedback loop. If the voltage (such as the source of the transistor) rises above the predefined threshold (representing that the positive feedback loop starts its operation), the output of the comparator can accordingly drive the control signal CTRL to close the jump start function .

Method for Accelerating Start-up of a Sampling Switch

Fig. 6 is a flowchart showing a method for accelerating activation of a sampling switch. In step 602, an output transistor in a positive feedback loop (such as transistor MP202 in FIG. 3 ) outputs an output voltage of a bootstrap voltage generator (such as V _BSTRP in FIG. 3 ) to drive the Sampling switch (such as transistor MN108 in Figure 3). In some embodiments, the sampling switch receives a voltage input signal (eg, V _INX to be sampled). The positive feedback loop can receive a voltage input signal output from the output transistor and driven by the output voltage (such as V _BSTRP in FIG. 3 ) at an input transistor (such as the transistor MN212 in FIG. 3 ). The positive feedback loop can generate a bootstrap voltage signal (such as the bootstrap voltage of V _INX +V _BOOT ) as the output voltage of the bootstrap voltage generator according to the voltage input signal, so that when the positive feedback circuit is connected Activate the sampling switch.

In step 604, a jump start circuit can pull the gate voltage of the output transistor (such as node X in FIG. 3 ) to a start voltage level to start the output transistor after the positive feedback loop is activated. Crystal up to a period. In some embodiments, pulling up the gate voltage of the output transistor includes changing the gate voltage from a turn-off voltage level to a turn-on voltage level. Before the positive feedback function is connected, the gate voltage can be at V _DD , as shown in FIGS. 2 and 3 , which is regarded as one of the "turn-off voltage levels" of transistor MP202. The jump start circuit temporarily pulls the gate voltage toward a "start voltage level", such as a logic low voltage level, to turn on the output transistor for a short period of time.

In step 606, the jump start voltage may stop or interrupt pulling the gate voltage after a period of time. For example, the jump start circuit can release the gate voltage of the output transistor back to a voltage delivered by the positive feedback loop after a period of time. For example, the jump start circuit enables the positive feedback loop to operate and drive the gate voltage close to the input signal V _INX to be sampled. In some embodiments, stopping pulling the gate voltage or releasing the gate voltage of the output transistor after a period includes enabling the positive feedback loop to drive the gate voltage to the bootstrap voltage generator and a voltage level of a voltage input signal (such as V _INX ) of the sampling switch.

In some embodiments, the sensing circuit (eg, sensing circuit 502 of FIG. 5C ) can sense at least one condition indicating that the positive feedback loop has been activated. The sensing circuit can generate a control signal in response to the at least one state Sensing. The control signal can drive and adjust the gate voltage of the output transistor.

A device for accelerating the activation of a sampling switch

To speed up activation of a sampling switch, a device may include sampling means (such as transistor MN108 of FIG. 3 ) that receives an input signal to be sampled (such as V _INX of FIG. 3 ), and a switch that activates and deactivates the sampling means. A control signal (such as V _BSTRP in FIG. 3 ). The device may further include means (eg, transistors MN210, C _BOOT , and transistor MN224 of FIG. 3) for generating a boosted voltage signal based on the input signal (eg, the bootstrap voltage of _VINX + V _BOOT ). The device may include an output means for outputting the control signal (such as transistor MP202 in FIG. 3 ). The device may include means for bringing the control signal to the boosted voltage through positive feedback of the control signal, as shown in FIGS. 2 and 3 . The device may include means for activating the output means for a limited period of time during the positive feedback activation phase (eg jump start circuit 302 of FIG. 3 and related examples of FIGS. 4A-4B and 5A-5C).

input buffer

A CMOS input buffer (single-ended) may include a stack of NMOS transistors and a current source. The voltage input to the input buffer can be directly connected to the gate of the NMOS transistor whose source is connected to the current source, and the source of the NMOS transistor is the output. In this type of input buffer, the output is shifted by a voltage, V _GS , down across the gate and source, and the NMOS transistor buffers the input voltage from its gate input to its The voltage at the source (eg the output). The voltage offset from input to output means that the range of the output voltage depends on the range of the input voltage. In other words, there is an offset between the input voltage and the output voltage. If the input buffer is driving a circuit that requires a specific voltage range, this biasing is undesirable or a problem to be solved in the circuit design.

FIG. 7 shows an example of an input buffer of an embodiment of the present disclosure. The input buffer can be used in the manner shown in FIG. 1 . The input buffer has an input V _IN for receiving a voltage input signal. The voltage input signal may be a high frequency data signal to be converted by a data converter, such as a high speed analog-to-digital converter. The input buffer includes a push-pull circuit that outputs a voltage output signal on an output V _INX . The push-pull circuit has a first transistor of a first type and a second transistor of a second type complementary to the first type. For example, the first transistor system can be an NMOS transistor MN702 (such as an NMOS transistor), and the second transistor system can be a PMOS transistor MP704 (such as a PMOS transistor). The sources of the two transistors are coupled to each other, and these sources also serve as the output V _INX of the output buffer to provide an output signal V _INX .

For this input buffer, the NMOS transistor MN702 and the PMOS transistor MP704 are not directly connected to the input V _IN , but the gate of the NMOS transistor MN702 is connected to the input V _IN through the level shifter 703, and The gate of PMOS transistor MP704 is connected to input V _IN through level shifter 705 . In some embodiments, the input buffer may include a first level shifter coupled to the input for shifting by a first voltage across the first level shifter The amount shifts the voltage level of the voltage input signal, and generates a first level shifted voltage signal to bias the first transistor. For example, the level shifter 703 can shift V _IN by a first voltage offset (eg, a voltage boost) across the level shifter 703 and generate a first level The offset voltage V ₁ is used to bias the first transistor, such as transistor MN702 . In some embodiments, the input buffer may include a second level shifter coupled to the input for shifting by a second voltage across the second level shifter The amount shifts the voltage level of the voltage input signal and generates a second level shifted voltage signal to bias the second transistor. For example, the level shifter 705 can shift V _IN by a second voltage offset (eg, a voltage reduction) across the level shifter 705 and generate a second level shifter Shift the voltage V ₂ to bias the second transistor, such as PMOS transistor MP704.

In the input buffer of FIG. 7, the input buffer has a push-pull structure. The push-pull structure has at least one NMOS transistor MN702 and a PMOS transistor MP704, the source of which is connected to the source of a PMOS transistor MP704. The sources are coupled to each other and form the output V _INX . As far as the 28nm CMOS process is concerned, PMOS and NMOS are complementary in performance such as bandwidth, permittivity, and transconductance per unit current. In some other processes, the performance of PMOS transistors and NMOS transistors can be very different. This complementary push-pull architecture utilizes NMOS transistors on one side and PMOS transistors on the other side, enabling a complementary buffer on one side of the PMOS and NMOS in processes such as 28nm CMOS semiconductors. One side has the same effect. This structure provides symmetrical pull-up and pull-down properties regardless of which side supplies current to the output _VINX to drive the load. The lengths of the two sides are equal, so a symmetrical pull-up and pull-down effect can be achieved. In terms of distortion, the complementary structure means that there may be less even-order distortion (such as reducing second-harmonic distortion).

In addition to symmetrical performance, the input buffer is efficient because the NMOS transistor MN702 and PMOS transistor MP704 effectively double the transconductance of the input buffer for a given amount of current through the transistors. to the same In terms of current flow, the NMOS transistor MN702 and the PMOS transistor MP704 can make the input buffer obtain two parallel mutual conductances.

For this input buffer, it is impossible to connect the gates of the NMOS transistor MN702 and the PMOS transistor MP704 together, because when the gates of the NMOS transistor MN702 and the PMOS transistor MP704 are short-circuited, there will be no Any voltage across the source of either of these transistors (insufficient V _GS ) prevents both transistors from turning on. Therefore, at least one of the two level shifters 703 and 705 is disposed between the gates of the NMOS transistor MN702 and the PMOS transistor MP704. The level shifter pulls the gates of the two transistors apart from each other so that the voltages across the gate and source are sufficiently different to keep the transistors on.

The level shifter 703 and the level shifter 705 connected to _VIN are regarded as (programmable) voltage offsets to bias the NMOS transistor MN702 and PMOS transistor MP704 at the gates of the respective transistors . In other words, the first voltage offset is programmable, and the second voltage offset is also programmable. As used, a level shifter is a circuit that shifts the level of a voltage input to the level shifter by an amount to produce a bit at the output of the level shifter quasi-offset voltage level.

For biasing the NMOS transistor _MN702 and the PMOS transistor _MP704 , for example, it is important to set appropriate voltages V1 and V2. If the two gates are too separated, too much current may flow through the two transistors. However, if the distance between the two gates is too large (the two transistors do not have sufficient V _GS , eg lower than two V _GS ), then the transistors cannot be fully activated. Preferably, a desired amount of current flows through the transistors. In order to ensure that these transistors can have an ideal current flow, a replica bias device can be used to set the voltage of the level shifter 703 and the level shifter 705, so as to ensure that the NMOS transistor MN702 and the PMOS transistor MP704 can with ideal current.

Preferably, the voltage difference between the gates of the transistor MN702 and the PMOS transistor MP704 must be at least two V _GS , such as the threshold voltage V _GS of the NMOS transistor MN702 and the threshold voltage V _GS of the PMOS transistor MP704. Ensure that an ideal current flows through the NMOS transistor MN702 and the PMOS transistor MP704. In some embodiments, the sum of the first voltage offset (such as the level shifter 703) and the second voltage offset (such as the level shifter 705) is at least the first voltage The sum of a first threshold voltage of the crystal (such as NMOS transistor MN702 ) and a second threshold voltage of the second transistor (such as PMOS transistor MP704 ).

Input-to-output bias and design considerations for these level shifters

Based on the result of the level shifter, the input V _IN and the output V _INX are independent, and the voltage range of the input and the voltage range of the output no longer depend on each other or have to be the same. Any offset between the input and the output can be selected by implementing appropriate level shifters, such as appropriate implementation of level shifters 703 and 705 . By selecting the appropriate first voltage offset and second voltage offset, the voltage output signal at V _INX can be biased, or have a bias from the voltage input signal V _INX . In one example, the voltage input signal can be centered at 0.5 volts, and the voltage input signal can be centered at 0.25 volts. The input buffer has greater flexibility.

In some cases, the input voltage at V _IN and the output voltage at V _INX may be roughly the same voltage. For example, V _IN is raised by level shifter 703, and the gate-to-source voltage of PMOS transistor MP704 is lowered at output V _INX . V _IN falls with the level shifter 705 and raises the gate-to-source voltage of the PMOS transistor MP704 at the output V _INX . If a suitable level shifter is used, there is no input-to-output bias. This feature does not exist in other input buffers that implement single cells and followers.

However, the input-to-output offset does not have to be zero. Having the two level shifters means that the voltage range of the input V _IN can be different from the voltage range of the output V _INX . With the two level shifters, as long as there is an appropriate voltage difference between the gate of the NMOS transistor MN702 and the gate of the PMOS transistor MP704 (for example biasing the transistors so that the desired current flows through them ), the input-to-output voltage can be adjusted to suit the application (eg when the bias is ideal.)

The input-to-output bias is variable. As such, variable means vary over time or between uses. The voltage offset provided by the level shifters is also variable (and vice versa). A certain degree of freedom of the input buffer is that the level shifters 703 and 705 are adjustable to have a specific output voltage range or voltage level.

In some embodiments, level shifters 703 and 705 (and other level shifters disclosed herein) are variable or programmable. In some embodiments, a voltage offset by one level shifter may be different from another voltage offset by the input buffer by another level shifter. The voltage offset is user adjustable and/or chip controllable. The voltage offset can be optimized based on other factors, such as distortion, electrostatic discharge (ESD), and the like.

In some cases, one of the level shifters 703 and 705 can be completely omitted, wherein either the voltage at the gate of the NMOS transistor MN702 or the voltage at the gate of the PMOS transistor MP704 is level shifted , to achieve an appropriate voltage difference between the gates of the two transistors.

implements a level shifter

One aspect of the level shifter is its ability to provide a voltage offset from the input to the gates of the transistors, independent of the input frequency, or down to DC (such as a ring frequency or a constant input V _IN ) and other properties. In other words, the level shift signal can be coupled to the input V _IN across all frequencies of the output. Certain other level shifters do not have such a frequency response.

The level shifter can be implemented in different ways. For example, a level shifter can include at least one of the following: at least one current source, at least one resistor, at least one transistor, at least one diode, at least one transistor in the form of a diode, at least one Capacitor, at least one battery, and at least one non-linear resistor. In some embodiments, the level shifter includes means to provide a voltage offset that is controlled by the amount of current flowing through the level shifter and can be independent of the input frequency . For example, a diode-type transistor system can provide a voltage level shift that depends on the current flowing through the diode-type transistor (the current can be provided by at least one current source). In some embodiments, the level shifter may include a switched capacitor circuit. Preferably, a level shifter is implemented using passive circuit elements (as opposed to active elements comprising a complementary transistor as a follower, offset up and down from the input). Passive circuit elements use less current, are less noisy, and are more linear than active circuit elements. Passive circuit elements may include transistors in the form of diodes, resistors, capacitors, circuits, and suitable combinations thereof combine.

FIG. 8 shows an implementation example of the level shifter in the disclosed embodiment of the present invention. An example of the level shifter includes current sources with a resistor and a capacitor connected in parallel between the current sources. For example, a level shifter referred to herein may include at least one current source (such as I ₁ and I ₂ ), and a resistor (or resistive element, such as R) connected in parallel with the resistor The capacitor (or capacitive element, such as C). The resistor and the capacitor connected in parallel with the resistor are interposed between the current sources _I1 and _I2 . Other arrangements of these circuit elements are known from this disclosure. Any current supplied by the current sources will flow through the parallel resistor and capacitor. The resistor, and the amount of current flowing through the resistor, can set the voltage offset across the level shifter (the voltage offset can be equal to the amount of current amplified by the impedance). In other words, an amount of current flowing through the resistor and provided by the current sources sets an amount of voltage across the level shifter. For a programmable level shifter, the amount of current is programmable, or the amount of resistance of the resistor is programmable. Either of the level shifters can be implemented in the manner described and shown herein. Depending on the specific application of the level shifter, the values of the various components in the level shifter may vary.

Bootstrap connects the gates of the main transistors after the

For an input buffer, it is important to achieve high performance, such as good linearity. In some embodiments, a first rear gate of the first transistor (such as transistor MN702) and a second rear gate of the second transistor are coupled to the output V _INX or coupled to The signal V _INX is output at this voltage. For example, the rear gates (body) of the NMOS transistor MN702 and the PMOS transistor MP704 are directly connected to the output V _INX , for example, the rear gates are bootstrapped and connected to the output node V _INX . If the NMOS transistor MN702 and the PMOS transistor MP704 are connected to some fixed voltage, such as the ground plane and V _DD , when the input V _IN changes, the V _GS of the two transistors will also change. Variations in the voltage between the source and the rear gate change the V _GS of the transistors. This change also adjusts the voltage V _GS and the capacitance of the transistor. This variation can cause distortion. To avoid this problem, the back-gate NMOS transistor MN702 and PMOS transistor MP604 are connected or bootstrapped to the output V _INX . For the input signal V _IN (and V _INX coupled with V _IN ), the voltage between the rear gate and the source of the transistors is zero. When the input signal V _IN changes, V _GS does not change anymore. The capacitance of the transistor may be short. Performance has improved. The input buffer shown in Figure 7, and at least some of the features described so far, can reduce some non-linearities or variations (once).

Minimize capacitance to improve performance

When the input buffer is driving a high frequency input signal V _IN , it is preferable to minimize the associated capacitance, or at least keep the capacitance constant. Or if the capacitance is about to change, it is better to reverse bias the junction of the capacitance as much as possible, so that the change of capacitance is small, or at least keep the voltage constant across the capacitance to reduce the change. Reverse-biasing the junction as much as possible, such as depending on the junction capacitance of the voltage, results in a smaller capacitance and less nonlinear properties.

Connecting the rear gate to the source of transistor MN702 (and output V _INX ) creates capacitance between the rear gate and the deep N-well. The N-well is at a fixed potential, and the back gate moves around with the signal. The NMOS transistor MN702 can be placed in its independent P-type well (back gate), which can be placed in a deep N-type well independent area. A rear gate of a first transistor (eg, transistor MN702) and a capacitor between an N-well can be reverse biased. For example, the deep N-row well system can be connected to a high potential so that the capacitance between the gate (P) and the deep N-type well (N) is reverse biased as strongly as possible (for reasons described above) . Therefore, the non-ideal effects of the capacitance can be reduced (eg, its linearity improved). The input buffer shown in FIG. 7, with at least some of the aforementioned features, can reduce some non-linearity or variability here (once).

Bootstrapped stacking for improved performance

If the input buffer is fabricated in 28nm CMOS fabrication technology, the output conductance, or the ratio of conductance G _DS to transconductance G _M , is small, or highly non-linear. This can make it undesirable to connect the drain of NMOS transistor MN702 and the drain of PMOS transistor MP704 to a fixed supply because when the signal _VIN or _VINX moves up or down, it changes the voltage across the transistor , such as moving V _DS (drain-to-source voltage) up and down. This may cause distortion of eg 25 to 40 dBs. One way to correct this distortion is to bootstrap the drain of NMOS transistor MN702 to the drain of PMOS transistor MP704 (eg, the input V _IN or output V _INX ) so that it is no longer fixed to some supply voltage.

FIG. 9 shows another example of the input buffer of the disclosed embodiment of the present invention. The push-pull circuit of the input buffer further includes a first-type third transistor (such as transistor MN706) stacked with the first transistor (such as transistor MN702), and connected to the second transistor (such as transistor MN702). Transistor MP704) is stacked with a second-type fourth transistor (for example, transistor MP708). At least one bootstrapped stack arrangement, such as a transistor stacked with the first/second transistor, may be configured to increase the effective output impedance, thereby affecting spurious free dynamic range (SFDR). Such stacked setups may require the use of high supply voltages to improve Improve the performance of the input buffer. Additional cascading settings can further improve performance.

Wherein the first stacking system is a transistor MN706 (such as an NMOS transistor), which is another follower connected to the input V _IN . The gate of the transistor MN706 can be connected to the output V _IN through the level shifter 707 and the level shifter 703 connected in series (as shown in the figure). In some embodiments, the level shifter 707 can be directly coupled to the output V _IN . The level shifter 707 or the series-connected level shifters 707 and 703 can be a third level shifter coupled to the output V _IN so as to be shifted across the third level by The voltage level of the voltage input signal generated by a third voltage offset of the device is shifted, and a third level shifted voltage signal V ₃ is generated to bias the third transistor, such as the transistor MN706. The gate of the first stacked structure MN706 is driven by the input V _IN (which can fluctuate up and down). The first stacked structure MN706 has a specific level shifter 707, so the input voltage (the source of the MN706 Pole) can provide sufficient V _DS to the transistor MN702 to operate in the saturation state of all states. Transistor MN706 is bootstrapped connected to the input V _IN to isolate the transistor MN702 from changes in V _DS . If the (exact) source of transistor MN706 is coupled to either the input or the output, then V _DS will be substantially constant (no change).

Depending on the level of distortion that can be tolerated, more stacked structures can be added to provide this function, eg transistor MN710 (eg NMOS transistor). Each stack can provide an additional 20dB in performance. Since the input buffer has a complementary design, the stack structure added to the NMOS side is also added to the PMOS side. According to this, transistor MP708 (such as PMOS transistor) can be added to bootstrap and connect and fix the V _DS of transistor MP704. The gate of the transistor MP708 can be connected to the input V _IN through the level shifter 709 and the level shifter 705 connected in series. In some embodiments, the level shifter 709 can be directly coupled to the input V _IN . Level shifter 709 or series-connected level shifters 709 and 705 can be a fourth level shifter coupled to the input V _IN to shift A fourth voltage offset of the device shifts the voltage level of the voltage input signal, and generates a fourth level offset voltage signal V ₄ to bias the fourth transistor, such as transistor MP708.

In the example shown, the push-pull circuit of the input buffer further includes a first-type fourth transistor (such as transistor MN710) stacked with the third transistor (such as transistor MN706), and connected to the third transistor (such as transistor MN706). A fourth transistor (for example, transistor MP708 ) is stacked with a second-type sixth transistor (for example, transistor MP712 ). In other words, the second stack structure on the NMOS side, eg transistor MN710, is ultimately connected to the supply. Furthermore, a second stack structure on the PMOS side, eg transistor MP712 (eg PMOS transistor), is ultimately connected to the supply.

The gate of the uppermost stacked structure MN710 is driven from the source of the first stacked structure on the NMOS side, eg through a level shifter 711 . The level shifter 711 can be a fifth level shifter coupled to a source of the third transistor (eg, transistor 706 ) to pass across the fifth level shifter. A fifth voltage offset offsets a voltage of the source of the third transistor, and generates a fifth level offset voltage signal V ₅ for biasing the fifth transistor (eg, transistor MN710 ). The lowest stack structure MP712 is driven from the source of the first stack structure on the PMOS side, for example through a level shifter 713 . The level shifter 716 can be a sixth level shifter, which is coupled to a source of the fourth transistor (eg, transistor MP708 ) to pass across the sixth level shifter. A sixth voltage offset is offset by a voltage of the source of the fourth transistor, and a sixth level offset voltage signal V ₆ is generated to bias the sixth transistor (eg, transistor MN710 ). The bootstrap structure (eg, bootstrap connection to the source of the third/fourth transistor and the drain of the first/second transistor) is self-sustaining from a non-self-contained stack structure connected to the supply. The bootstrap gate-to-source capacitance unloads the buffer input and output (both of which are the source of choice for the bootstrap connection), and the supply is a significant source of distortion.

In the examples shown in Figures 7 and 9, the bootstrap structure is primarily accomplished by connecting the gates of the transistors to the output (or to some other node coupled to the output). This feature is intended to reduce possible ringing that may be caused by gate bootstrapping connected to the output. Since a bootstrap connection to the output may load the output and add additional parasitics, an input buffer that is less susceptible to ringing may be preferred in high-speed applications. Although there may be ringing from the upper stack structure because it is bootstrapped to the source of the first stack structure, the upper stack structure is less sensitive than other schemes when it is bootstrapped to the input or output. The ringing is still tolerable insofar as distortion at the source of the cascaded structure may cause distortion at the input V _IN and output V _INX .

Furthermore, the gates of different stacked transistors in the input buffer are bootstrap structures as shown in FIG. 9 to improve SFDR. Similar to the description of the rear gates of transistors MN702 and MP704, the rear gates of these stacked structures are preferably bootstrap structures (for example, voltage variations across the rear gate and source are not expected). Unfortunately, in some embodiments, V _SS is negative, which means that the drain of transistor MP708 is in negative swing. In 28nm CMOS process technology, the N-type well of the PMOS transistor is located in the substrate, and the substrate is at 0 volts. If the N-well system is negative, it will cause the diode to be biased between the P substrate (at 0 volts) and all N-wells (diode cathodes). If the N terminal is below the ground plane, it will bias the diode and cause distortion. The rear gate of the stacked structure on the PMOS side is connected to the source of each opposite stacked structure (the same stacked structure), which means that it may cause distortion. The solution is to connect the gates of the stacks to each other, for example the gate of an NMOS stack is connected to the source of the corresponding/complementary PMOS stack and vice versa. The sources are follow-coupled to the output, so connecting them to each other helps to bootstrap the gate (to the output) behind the stacked structures. Denoted by V _BGN1 , a rear gate of the third transistor (eg, transistor MN706 ) is coupled to a source of the fourth transistor (eg, transistor MP708 ). Denoted by V _BGP1 , a rear gate of the fourth transistor (such as transistor MP708 ) is coupled to a source of the third transistor (transistor MN706 ). Denoted by V _BGN2 , a rear gate of the fifth transistor (such as transistor MN710 ) is coupled to a source of the sixth transistor (such as transistor MP712 ). Denoted by V _BGP2 , a rear gate of the sixth transistor (such as transistor MP712 ) is coupled to a source of the fifth transistor (such as transistor MN710 ).

Connecting the rear gate to the output is less than ideal as it would load it with a non-linear capacitance. Linearity is improved due to the presence of a large voltage across the junction. Since the stacked structure on the NMOS side can connect the rear gates to their individual sources, the complementary design of connecting the rear gates to the source of the complementary stacked structure is important for achieving a Complementary designs and equivalent loads for symmetrical pull-up or pull-down effects are ideal.

Method for buffering a voltage input signal

FIG. 10 is a flow chart of buffering an input signal according to an embodiment of the present invention. In step 1002, a first voltage offset set by (at least one current source of) a first level shifter is used to shift the voltage input signal to generate a first signal. In step 1002, a second voltage offset set by (at least one voltage source of) a second level shifter shifts the voltage input signal to generate a second signal. The first voltage offset and the second voltage offset may represent the level shifters 703 and 705 in FIGS. 7 and 9 . The first signal and the second signal may represent V ₁ and V ₂ in FIGS. 7 and 9 . The first signal shifts a first type first transistor. In step 1004, the second signal bias is complementary to a second type second transistor of the first type. The first transistor and the second transistor system are coupled in a push-pull structure, as shown by transistor MN702 and transistor MP704 in FIG. 7 and FIG. 9 . In step 1006, the first transistor and the second transistor output a voltage output signal, such as V _INX in FIG. 7 and FIG. 9 .

In some embodiments, a first stack transistor coupled to the first transistor is biased according to a third signal. The third signal can be coupled to the voltage input signal. In some embodiments, a second stack transistor coupled to the second transistor is biased according to a fourth signal. The fourth signal can be coupled to the voltage input signal. For example, the third/fourth signal can be the signal V ₃ or V ₄ shown in FIG. 9 .

In some embodiments, a third stack transistor coupled to the first stack transistor is biased according to a fifth signal. The fifth signal can be coupled to the voltage input signal. In some embodiments, a sixth signal bias is coupled to a fourth stack transistor of the first stack transistor. The sixth signal can also be coupled to the voltage input signal. For example, the fifth/sixth signal can be the signal V ₅ or V ₆ shown in FIG. 9 .

device for buffering an input signal

Means for buffering an input signal may be included in implementations of the methods described herein. In some embodiments, the device includes means for receiving an input signal. For example, there may be an input node to receive an input signal (such as V _IN shown in FIGS. 1 , 7 and 9 ), such as a high frequency signal to be converted by a data converter. The device may further include push-pull means to generate an output signal. Push-pull means can include push-pull circuits as described herein as well as push-pull structures such as the transistors seen in FIGS. 7 and 9 . The device may further comprise means for generating a first signal for biasing the push-pull means, a first transistor. The first signal is coupled to the input signal across all frequencies of the input signal. Further means may be included to generate other signals to bias other transistors of the push-pull means. Means for generating signals for biasing transistors may include associated level shifters as shown in FIGS. 7-9.

The means for generating the signals for biasing the transistors (bootstrap connecting the transistors to the input) can be distinguished from other circuits that generate a bias signal based on a fixed/predefined bias voltage. The means for generating the signals for biasing the transistors are coupled to the input signal, or connected via a bootstrap to the input signal across all frequencies of the input signal, for example up to direct current (DC). Conversely, those other circuits that generate a bias signal based on a fixed/predefined bias voltage are not coupled to the input signal across all frequencies of the input signal.

For other circuits, the signal for biasing the transistor can be generated by using a fixed bias voltage and a resistor, and a capacitor in series with the input. The signals used to bias the transistors are not buffered or coupled to the input signal at low frequencies because the capacitor has a high impedance at low frequencies and resistance control. Therefore, the non-bootstrap bias signal can be set by the fixed bias voltage and resistor at low frequency (and not responsive to the input signal). In contrast, the level shifter described herein as a means of generating a bias transistor (bootstrap) signal is responsive to that input signal across all frequencies (at low and high frequencies), Because the level shifters described herein have different frequency responses.

example

Example 1 is an input buffer, which has: an input for receiving a voltage input signal; a push-pull circuit for outputting a voltage output signal at an output, wherein the push-pull circuit has a first type first transistor, a second transistor of a second type complementary to the first type; and a first level shifter coupled to the input for switching a first voltage across the first level shifter The offset shifts a voltage level of the voltage input signal, and generates a first level offset voltage signal to bias the first transistor, wherein the first level shifter provided by the first level shifter The first voltage offset is independent of a frequency of the voltage input signal.

In Example 2, Example 1 may further include a second level shifter coupled to the input for shifting the the voltage level of the voltage input signal, and generate a second level offset voltage signal to bias the second transistor.

In Example 3, Example 1 or 2 may further include that the first voltage offset is programmable.

In Example 4, any of Examples 1 to 3 may further include a current flowing through a resistive element and provided by at least one current source to set the current across the first level shifter. first voltage offset.

In Example 5, any one of Examples 1 to 4 may further include that the sum of the first voltage offset and the second voltage offset is at least a first threshold voltage of the first transistor and the The sum of the second transistor-second threshold voltage.

In Example 6, any one of Examples 1 to 5 may further include that the first voltage offset is different from the second voltage offset.

In Example 7, any one of Examples 1 to 6 may further include that the voltage output signal is biased from the voltage input signal.

In Example 8, any one of Examples 1 to 7 may further include that a first rear gate of the first transistor and a second rear gate of the second transistor are coupled to the output or follower output signal at this voltage.

In Example 9, any of Examples 1-8 may further include a capacitor between a rear gate and the deep N-well of the first transistor that is reverse biased.

In Example 10, any one of Examples 1 to 9 may include that the push-pull circuit further has: a third transistor of the first type, which is stacked with the first transistor; and a fourth transistor of the second type , and the second transistor is stacked and arranged.

In Example 11, any one of Examples 1 to 10 can further include a third level shifter coupled to the output for shifting by a third voltage across the third level shifter The amount shifts the voltage level of the voltage input signal, and generates a third level shifted voltage signal to bias the third transistor.

In Example 12, any one of Examples 1 to 11 may further include that the push-pull circuit further has: a fifth transistor of the first type, which is stacked with the third transistor; and a sixth transistor of the second type crystal, which is stacked with the fourth transistor set up.

In Example 13, any one of Examples 1 to 12 may further include a fourth level shifter coupled to a source of the third transistor to pass through the fourth level shifter A fourth voltage offset offsets a voltage of the source of the third transistor, and generates a fourth level offset voltage signal to bias the fifth transistor.

In Example 14, any one of Examples 1 to 13 may further include: a rear gate of the third transistor is coupled to a source of the fourth transistor; and a rear gate of the fourth transistor The pole is coupled to a source of the third transistor.

In Example 15, any one of Examples 1 to 14 may further include: a rear gate of the fifth transistor is coupled to a source of the sixth transistor; and a rear gate of the sixth transistor The pole is coupled to a source of the fifth transistor.

Example 16 is a method for buffering a voltage input signal, the method comprising: shifting the voltage input signal by a first voltage shift level of a first level shifter to generate a first signal, Wherein the first voltage offset is independent of a frequency of the voltage input signal; offset a first type first transistor by the first signal; offset complementary to the first type by a second signal A second transistor of the second type, wherein the first transistor and the second transistor are coupled in a push-pull structure; and a voltage output is output by the first transistor and the second transistor signal.

In Example 17, Example 16 may further include, level shifting the voltage input signal by a second voltage offset set by a second level shifter to generate the second signal.

In Example 18, Example 16 or 17 may further comprise, by A third signal offset is coupled to one of the first stack transistors of the first transistor, wherein the third signal is coupled to the voltage input signal.

In Example 19, any one of Examples 16 to 18 can further comprise offsetting a second stack transistor coupled to the first stack transistor by a fourth signal, wherein the fourth signal is coupled to the first stack transistor coupled to the voltage input signal.

Example 20 is a device comprising: means for receiving an input signal, push-pull means for generating an output signal; and a first transistor for generating a first signal to bias the push-pull means ( passive) means, wherein the first signal is coupled to the input signal across all frequencies of the input signal.

Example 21 is an apparatus comprising means for implementing/performing any one of the methods described in Examples 16-19.

Example 101 is a bootstrap switching circuit capable of accelerated startup, which includes: a sampling switch that receives a voltage input signal and a gate voltage; a bootstrap voltage generator that includes a positive feedback loop to generate the Gate voltage, so as to start the sampling switch, the positive feedback loop includes an input transistor, receives the voltage input signal, and an output transistor that outputs the gate voltage of the sampling switch; and a jump start circuit, used for the When the input transistor is activated during the positive feedback loop activation phase, the output transistor is activated for a finite period.

In Example 102, Example 101 may further include, the jump start circuit being coupled to a gate of the output transistor.

In Example 103, Examples 101 to 102 can further include, the jump start circuit deactivating the output transistor after the limited period and enabling the positive feedback loop to operate.

In Example 104, any one of Examples 101 to 103 can be further Including: the jump start circuit has a transistor to receive a clock signal for starting the positive feedback loop; and the transistor system is activated by a delayed version of the clock signal to output the clock signal to The output transistor is enabled for the limited period.

In Example 105, any one of Examples 101 to 104 may further include that the jump start circuit further has two inverters for generating the delayed version of the clock signal according to the clock signal.

In Example 106, any of Examples 101 to 105 can further include: the jump start circuit having a switch to connect a gate of the output transistor to a bias voltage to enable the output transistor, and The switch is controlled by a control signal having a pulse to close the switch.

In Example 107, any one of Examples 101 to 106 can further include the jump start circuit having a sensing circuit to activate the jump start based on at least one state of the bootstrap switching circuit indicating a positive feedback loop start phase circuit.

In Example 108, any one of Examples 101 to 107 can further include, the sensing circuit sensing a voltage representing a voltage level at a node of the bootstrap switching circuit.

In Example 109, any one of Examples 101 to 108 may further include that the node is located at a node in the positive feedback loop.

In Example 110, any of Examples 101 to 109 can further include the sensing circuit having a comparator that compares the voltage to a predefined threshold indicative of an active state of the positive feedback loop.

In Example 111, any of Examples 101 to 110 can be further Including: the positive feedback loop has a startup capacitor; and the positive feedback loop activates the sampling switch by driving the gate voltage to a startup voltage generated according to the voltage input signal and a voltage across the startup capacitor.

In Example 112, any one of Examples 101 to 111 can further include: the input transistor system coupled to a first plate of the startup capacitor; and the output transistor system coupled to a second plate of the startup capacitor plate.

In Example 113, any one of Examples 101 to 112 can further comprise: the input transistor system is driven by the gate voltage of the sampling switch; and the positive feedback loop further has a first transistor coupled to the output A gate of the transistor and a drain of the input transistor, wherein the first transistor system is driven by the gate voltage of the sampling switch.

In Example 114, any one of Examples 101 to 113 may further include: the positive feedback loop further having: an additional transistor coupled to a gate of the output transistor and a drain of the input transistor, Wherein the additional transistor system is controlled by a clock signal driving the positive feedback loop.

Example 115 is an accelerated startup method for a sampling switch, which includes: outputting an output voltage of a bootstrap voltage generator through an output transistor of a positive feedback loop to drive the sampling switch; the output transistor A gate voltage is pulled to a startup voltage level to start the output transistor for a period after the positive feedback loop is activated; and the gate voltage is stopped after the period.

In Example 116, Example 115 may further include: the sampling switch receives a voltage input signal; and the positive feedback loop receives the voltage input signal at an input transistor driven by the output voltage of the output transistor, and according to the The voltage input signal generates a bootstrap voltage signal as the bootstrap voltage The output voltage of the generator is used to activate the sampling switch when the positive feedback loop is connected.

In Example 117, Examples 115 or 116 can further comprise, pulling up the gate voltage of the output transistor, including changing the gate voltage from a shutdown voltage level to a startup voltage level.

In Example 118, any one of Examples 115 to 117 may further comprise: enabling the positive feedback loop to drive the gate voltage to a voltage level of a voltage input signal provided to the self- Lift-type voltage generator and the sampling switch.

In Example 119, any one of Examples 115 to 118 can further comprise: sensing at least one state in which only the positive feedback loop has been activated; and generating a control signal in response to sensing the at least one state, wherein the controlling The signal can drive the pull-down of the gate voltage of the output transistor.

Example 120 is a device comprising: sampling means for receiving an input signal to be sampled and a control signal for activating and deactivating the sampling means; means for generating a bootstrap voltage based on the input signal; output means for outputting the control signal; means for driving the control signal to the bootstrap voltage through positive feedback of the control signal; and means for activating the output means for a limited period during an activation phase of the positive feedback.

Example 121 is an apparatus comprising means for implementing/performing the method of any one of Examples 115-119.

Changes and Implementation

A transistor, such as a metal oxide semiconductor field effect transistor (MOSFET), has a source where charge carriers enter the transistor channel. A drain of the transistor is where the charge carriers exit the channel. In some cases, the The source and the drain may be the two terminals of the transistor. The gate of a transistor can be considered a control terminal of the transistor because the gate can control the conductance of the channel (eg, the amount of current through a transistor). A rear gate (body) of a transistor can also be regarded as a control terminal of the transistor. The gate and rear gates can be used as terminals for biasing a transistor.

It should be noted that the activities described above with reference to the diagrams are applicable to any integrated circuit involved in processing analog signals and converting them to digital data using at least one analog-to-digital converter (ADC). In particular context, the features discussed herein generally relate to analog-to-digital converters, such as various analog-to-digital converters, including pipeline analog-to-digital converters (pipeline ADCs), Delta-Sigma analog-to-digital converters (Delta-Sigma ADCs) , successive approximation register ADC, multi-stage analog-digital converter (multi-stage ADC), time-interleaved analog-digital converter (time-interleaved ADC), randomized time-interleaved analog-digital converter (randomized time-interleaved ADC), etc. These features are particularly beneficial for high-speed analog-to-digital converters, where the input frequency is relatively high, in the gigahertz range. The analog-to-digital converter can be used in medical systems, scientific instruments, wireless and wired communication systems (especially systems that require high sampling rates), radar, industrial process control, audio/video equipment, instruments and other devices that use analog-to-digital conversion Device system. The level of performance provided by high-speed analog-to-digital converters is ideal for current market needs such as high-speed communications, medical imaging, synthetic aperture radar, digital dial-in-line communication systems, broadband communication systems, high-performance imaging, and advanced test/measurement systems ( Oscilloscopes) are especially beneficial.

The content disclosed in this case covers the installation of various content described here. place. These devices may include circuitry as shown and shown herein. Components of the various devices may contain electronic circuitry to perform the functions described herein. The circuitry can operate in the analog domain, digital domain or mixed signal domain. In some cases, at least one component of the device may be provided by a processor specially configured to perform the functions described herein (eg, control-related functions, time-point related functions). In some cases, the processor may be an on-chip processor with the analog-to-digital converter. The processor may include at least one application-specific element, or may include programmable logic gates configured to implement the functions described herein. In some examples, the processor can be configured to implement the functions described herein via instructions stored on a non-transitory computer medium.

In the discussion of the embodiments herein, the components and elements may be substituted, replaced, or otherwise modified to meet specific circuit system requirements. Furthermore, it should be noted that the use of complementary electronic devices, hardware, etc. may provide equivalent options available for implementing the teachings disclosed herein. For example, complementary arrangements using PMOS transistors (P-type metal oxide semiconductor transistors) instead of NMOS transistors (N-type metal oxide semiconductor transistors), or vice versa, are known from this disclosure. For example, this disclosure/claim scope covers implementations where all NMOS devices are replaced by PMOS devices, or vice versa. The connections and circuits can be reconfigured to achieve the same function. These embodiments are equivalent to those utilizing complementary transistor devices in that they achieve substantially the same function, or achieve substantially the same result, in virtually the same manner. Those skilled in the art will appreciate that a transistor device can generally be a device with three (main) terminals. Furthermore, those skilled in the art understand that a switch, transistor, or transistor device may, in operation, have Effects of transistor characteristics corresponding to devices such as NMOS, PMOS devices (and any other equivalent transistor devices).

In an example embodiment, any number of the components in the figures may be implemented on a board of an associated electronic device. The circuit board can be a general circuit board, which can contain various components of the internal electronic system of the electronic device, and can further provide connectors for other peripheral devices. More specifically, the circuit board provides electrical connections by which other components of the system can communicate electrically. Any suitable processor (including digital signal processors, microprocessors, supporting chipsets, etc.) may be suitably coupled to the circuit board based on specific setup requirements, processing requirements, computer design, etc. Other components such as external memory, additional sensors, controllers for audio/video displays, and peripherals can be attached to the board via cables as plug-in cards, or integrated into the the circuit board itself. In various embodiments, the functionality described herein may be implemented in emulated form, as software running within at least one configurable (e.g., programmable) element disposed in a structure that supports those functions or Hardware. The software or firmware providing the emulation may be located on a non-transitory computer readable medium containing instructions to allow a processor to perform the functions.

In another example embodiment, the components in the figures may be implemented as a stand-alone module (eg, a device with associated components and circuitry configured to perform a specific application or function) or as an A plug-in module in specific hardware of a device. It should be noted that certain embodiments disclosed herein may be readily included in part or in whole in a system on chip (SOC) package. A SoC means an integrated circuit (IC) that integrates the components of a computer or other electronic system onto a single chip. which may contain Digital, Analog, Mixed Signal and Common RF Functions: These functions can all be placed on a single chip substrate. Other embodiments may include a multi-chip-module (MCM) having a plurality of individual integrated circuits that are located within a single electronic package and arranged to closely interact with each other through the electronic package effect. In various other embodiments, the error correction functionality may be implemented in at least one of Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) and other semiconductor chips Implemented in silicon cores.

Still, it should be noted that all specifications, dimensions, and relationships (eg, number of processors, logical operations, etc.) described herein are provided for illustration and teaching purposes only. Such information may vary considerably without departing from the spirit and scope of the invention disclosed and claimed or, where applicable, the scope of the embodiments described herein. These specifications apply to one non-limiting example only, and accordingly, they should be construed accordingly. In the foregoing, example embodiments have been described with reference to specific processor and/or component configurations. Various modifications and changes may be made to these embodiments without departing from the scope of the claimed invention or, where applicable, the embodiments described herein. Therefore, the embodiments and drawings are only for illustration rather than limitation.

Note that in many of the examples provided herein, two, three, four or more electronic assemblies or components may be used to describe their interaction. However, this is for clarity and example purposes only. It should be understood that the system may be enhanced in any suitable manner. Any of the components, modules, blocks and elements shown in the drawings may be combined in various possible arrangements, with reference to similar design alternatives, all of which are expressly within the scope of this description. In some cases, only through It may be easier to describe one or more functions of a given set of streams in terms of a limited number of electronic components. It should be understood that the circuits in the drawings and their teachings are readily adaptable and adaptable to larger numbers of components and more complex/sophisticated configurations and arrangements. Accordingly, the examples provided here should not be used to limit the scope or inhibit the broad teaching of the potential application of the circuit to numerous other architectures.

It should be noted that in this specification, references to "an embodiment", "example embodiment", "one embodiment", "another embodiment", "certain embodiments", "various embodiments", "other embodiments" ", "alternative embodiment" and the like include various features (such as elements, structures, modules, components, steps, operations, characteristics, etc.) that are included in at least one embodiment of the present invention. , may or may not necessarily be combined in the same embodiment. It should still be noted that the functions described herein represent only a few of the possible functions that may be performed by the systems/circuits shown in the figures. Certain parts of these operations may be deleted or removed under appropriate circumstances, or these operations may be modified or changed without departing from the scope of the present invention. In addition, the timing of these operations may vary considerably. The above operation flow is provided for the purpose of illustration and discussion only. The embodiments described herein provide substantial flexibility and may have any suitable configurations, chronologies, settings and timing mechanisms without departing from the teachings disclosed herein. Several other changes, substitutions, changes, changes and modifications can be established by those with ordinary knowledge in the technical field of the present invention, and all such changes, substitutions, changes, changes and modifications fall within the patent scope of the present invention scope or (where applicable) within the embodiments described herein. It should be noted that all optional features of the apparatus described above can also be implemented with respect to the methods or processes described herein, and details in these examples can be used anywhere in at least one embodiment.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the scope of the attached patent application.

MN 108: Transistor

200: Bootstrap switching circuit

MP 202: Transistors

MP 204: Transistor

MN 206: Transistor

MN 208: Transistor

MN 210: Transistor

MN 212: Transistor

MP 214: Transistor

MN 216: Transistor

MN 224: Transistor

Claims (20)

An input buffer comprising: An input, receiving a voltage input signal; a first transistor of a first type; a second transistor of a second type complementary to the first type, wherein the source of the second transistor is coupled to The source of the first transistor; a third transistor of the second type, which is stacked with the second transistor; an output, located between the source of the first transistor and the second transistor source; a first level shifter, which generates a first level offset voltage coupled to the voltage input signal, and is set at the gate of the first transistor and the gate of the second transistor A voltage difference between; and a second level shifter, which generates a second level offset voltage coupled to the voltage input signal to maintain across the first level when the voltage input signal moves up or down A constant drain-to-source voltage of two transistors and biasing the third transistor. The input buffer according to claim 1, wherein at least the first transistor and the second transistor are biased by the first level shifter to generate a certain amount of current flowing through the first transistor with the second transistor. The input buffer of claim 1, wherein the first level offset voltage biases the gate of the first transistor. The input buffer according to claim 1, wherein the first level shifter shifts the input voltage signal by a first voltage shift amount. The input buffer of claim 4, wherein the first voltage offset is sufficient to keep the first transistor and the second transistor turned on. For example, the input buffer of request item 1 further includes: A third level shifter generates a third level shift voltage coupled to the voltage input signal across all frequencies of the voltage input signal. The input buffer of claim 6, wherein the third level offset voltage biases the gate of the second transistor. For example, the input buffer of request item 1 further includes: A replica bias element is used for the first level shifter to set a current flowing through the first transistor and the second transistor. The input buffer according to claim 1, wherein the voltage difference is at least a sum of a threshold gate-to-source voltage of the first transistor and a threshold gate-to-source voltage of the second transistor. The input buffer according to claim 1, wherein a voltage offset caused by the first level shifter is programmable. The input buffer of claim 1, wherein the voltage difference sets a certain offset of a voltage output signal at the output relative to the voltage input signal. The input buffer of claim 11, wherein the determined offset is non-zero. For example, the input buffer of request item 1 further includes: A fourth transistor of the first type is stacked with the first transistor. For example, the input buffer of claim 13 further includes: a fourth level shifter generating a fourth level offset voltage coupled to the voltage input signal to maintain a constant drain across the first transistor as the voltage input signal moves up or down to the source voltage and biases the fourth transistor. A method of buffering a voltage input signal, comprising: generating a first voltage offset signal coupled to the voltage input signal; biasing a first transistor of a first type according to the first voltage offset signal; biasing a second type transistor according to the voltage input signal A second transistor of the second type is biased, wherein the second type is complementary to the first type; a stacked transistor of the second type coupled to the second transistor is biased by a second voltage offset signal biasing, wherein the second voltage offset signal is coupled to the voltage input signal to maintain a constant drain-to-source voltage across the second transistor as the voltage input signal moves up or down; and A voltage output signal is output from the source of the first transistor and the source of the second transistor. The method for buffering a voltage input signal as claimed in item 15 further includes: setting a voltage difference between the gate of the first transistor and the gate of the second transistor to be at least a threshold gate-to-source voltage of the first transistor and a threshold of the second transistor Sum of gate to source voltages. The method for buffering a voltage input signal as claimed in item 15 further includes: biasing another cascaded transistor of the first type coupled to the first transistor with a third voltage offset signal, wherein the third voltage offset signal is coupled to the voltage input signal to The voltage input signal maintains a constant drain-to-source voltage across the first transistor as it moves up or down. An input buffer comprising: An input, receiving a voltage input signal; a first transistor of a first type; a second transistor of a second type complementary to the first type, wherein the source of the second transistor is coupled to The source of the first transistor; an output located between the source of the first transistor and the source of the second transistor; a third transistor of the second type stacked with the second transistor connected to the setting; a first level shifter, which generates a first level offset voltage independent of the frequency of the input voltage signal and coupled to the voltage input signal, and biases the first transistor; and a second level shifter generating a second level offset voltage coupled to the voltage input signal to maintain a constant drain across the second transistor as the voltage input signal moves up or down to the source voltage and biases the third transistor. Such as the input buffer of claim 18, further comprising: A fourth transistor of the first type is stacked with the first transistor. Such as the input buffer of claim item 19, further comprising: a third level shifter generating a third level offset voltage coupled to the voltage input signal to maintain a constant drain across the first transistor as the voltage input signal moves up or down to the source voltage and biases the fourth transistor.

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