201023349 六、發明說明： 【發明所屬之技術領域】 本發明，係有關於將複數個胞配置爲字元線方向以及 位元線方向之行列狀的浮游閘極型非揮發性記憶體配置構 成。 【先前技術】 φ 作爲非揮發性記憶體，係週知有堆疊型浮游閘極構造 。圖10,係爲對於在專利文獻1中所記載之具備有先前 技術之堆疊構造的非揮發性記億體裝置作展示之圖。在矽 基板上，係形成有由薄的氧化矽膜所成之閘極絕緣膜、以 及源極、汲極區域，在閛極絕緣膜上，係依序被層積有： 由多結晶矽膜所成之浮游閘極電極、層間絕緣膜以及由多 結晶矽膜所成之控制閘極電極。圖示之非揮發性記憶體裝 置，係藉由在浮游閘極電極中積蓄電荷並從浮游閘極電極 〇 來將電荷放出，而進行資訊之寫入、保持以及消除。由於 其係爲在記憶體晶片中所通常使用的構造，因此，其製程 以及元件亦係爲週知。由於係爲在浮游閘極電極之上方層 積控制閘極電極之構造，因此，係爲高密度。但是，由於 係藉由第1層之多結晶矽膜（多晶矽）來形成浮游閘極電 極，且藉由以層間絕緣膜來從此浮游閘極電極而作了隔離 之第2層的多結晶矽膜來形成控制閘極電極，因此，製造 製程係成爲複雜，在成本上係爲不利。 因此，係週知有：使用1層之多結晶矽膜，來構成浮 -5- 201023349 游閘極電極，同時，藉由擴散區域而形成控制閘極電極的 非揮發性記憶體（參考專利文獻2、3 )。圖1 1 ( A )， 係爲對專利文獻2中所記載之先前技術之非揮發性記憶體 裝置作展示的圖案佈局圖，圖11(B)係爲展示沿著X-X 線之剖面圖。 在矽基板表面之元件區域中，係被形成有：包含源極 、汲極區域之記億體FET、和控制閘極用擴散區域。在源 極、汲極區域間之通道區域上，以及控制閘極用擴散區域 _ 之一部分上，係分別隔著極薄之氧化膜a、b而被形成有 浮游閘極。又，在汲極區域與位元線用擴散區域間之通道 區域上，係被設置有隔著閘極氧化膜而形成有選擇閘極之 選擇電晶體。進而，在於全面而被作了堆積之CVD氧化 膜上，係被形成有經由接觸孔a而與源極區域相連接之共 通電位線、以及經由接觸孔b而與位元線用擴散區域相連 接之位元線。 在此種非揮發性記憶體中，係藉由將控制閘極用擴散 φ 區域設爲高電位，並將汲極區域設爲0V，而在浮游閘極 中使電荷作積蓄，來進行消除動作。又，係藉由將控制閘 極用擴散區域設爲OV，並將汲極區域設爲高電位，而使 電荷從浮游閘極來流出至汲極區域，來進行寫入動作。 圖示之非揮發性記憶體裝置，由於係爲僅將浮游閘極 電極藉由1層之多結晶矽膜來形成者，因此，製造製程係 成爲簡單’但是，由於係並非將控制閘極電極配置在浮游 閘極電極之上方，而是配置在側方，因此，係有著胞面積 -6- 201023349 變大之問題。 另一方面，假想接地型之非揮發性記憶體，係爲週知 (參考專利文獻4)。假想接地型之非揮發性記憶體，係 以將源極與汲極作交換並使其相對稱地進行動作的方式來 構成，藉由此，而能夠將記憶體胞之積體密度提升。 [先前技術文獻] φ [專利文獻] [專利文獻1]日本特開平10-223783號公報 [專利文獻2]日本特開平6-5 3 52 1號公報 [專利文獻3]日本特開平1 0-70204號公報 [專利文獻4]日本特開2007-1 57280號公報 【發明內容】 [發明所欲解決之課題] • 本發明，係爲了解決上述之問題點，而以下述事項作 爲目的：在將對浮游閘極作共有之控制閘極部配置於記憶 體FET之側方處的浮游閘極型非揮發性記憶體中，實現 由假想接地型（virtual ground )所致之記憶體胞陣列構成 ’並實現一種製程爲低價且爲省面積之記憶體胞陣列。 [用以解決課題之手段] 本發明，係爲一種浮游閘極型非揮發性記憶體配置構 成’係將1個浮游閘極型非揮發性記憶體裝置作爲1個胞 -7- 201023349 ，並將複數個的胞配置爲字元線方向以及位元線方向之行 列狀，其特徵爲：前述1個浮游閘極型非揮發性記憶體裝 置，係爲將由對浮游閘極作共有之記憶體FET和控制閘 極部所成的2電晶體，並置在半導體基板上所構成，該控 制閘極部，係包含有相對於前述浮游閘極而隔著閘極絕緣 膜而相對峙之控制閘極。位元線，係在前述浮游閘極之上 方而朝向其之長度方向來延伸，並且，作爲前述控制閘極 而起作用之前述字元線，係在與前述位元線相正交的方向 上延伸。對相同之字元線作共有且在字元線方向上相鄰接 之胞，係相互反方向地且在位元線方向上有所偏移的而被 作配置，並且，此相鄰接之胞的控制閘極，係以在字元線 方向上直線狀地並排的方式，來將在字元線方向上相鄰接 之胞的浮游閘極配置爲相互地在位元線方向上而突出至字 元線方向之側方處。對於相同之字元線作共有之2個胞行 ，係相互使用相異之位元線。字元線，係藉由與半導體基 板相分離了的埋入字元線所形成，在記憶體配置構成之內 部’係並不從金屬片而具備有接點，而在記憶體配置構成 之外側處而被供給電位。複數個的胞，係實現假想接地型 所致之記憶體配置構成。 [發明之效果] 若藉由本發明，則係實現由假想接地型（virtual ground )所致之記憶體胞陣列構成，並能夠實現—種製程 爲低價且省面積之記憶體胞陣列。進而，藉由採用由主動 -8 - 201023349 層所致之字元線，並且將相鄰接之胞的節距作偏移配置， 而將浮游閘極配置在相互之區域的字元線方向之側方處， 並使相對面之胞彼此共享字元線，能夠將每一單位胞之字 元線的面積減少。 【實施方式】 以下，根據例示，對本發明作說明。參考圖1〜圖6 φ ，對於將本發明具體化之浮游閘極型非揮發性記憶體配置 構成的第1例作說明。圖1，係爲對佈局作展示之圖。但 是，在實際之製品中，通常係有更多的胞被配置爲行列狀 ，不過，圖1之佈局，係將其之一部分取出並作圖示（在 以下之說明中，係將字元線方向作爲行，將位元線方向作 爲列）。又，通常係具備有對於位元線以及字元線而將電 位作切換供給之解碼器，但是，於圖示中係省略。圖2( A)，係爲對於與圖1相同之佈局作展示的圖，圖2(B) • 以及圖2(C)，係分別爲圖2(A)中之以虛線所展示的 場所之字元線方向以及位元線方向的剖面圖。圖3(A) ，係爲對於與圖1相同之佈局作展示的圖，圖3(B)係 爲圖3(A)中之以虛線所展示（與圖2(B)爲相異）的 場所之字元線方向的剖面圖。 浮游閘極型非揮發性記憶體裝置之構成，係特別爲如 同在圖2(C)中所見一般，爲將由對浮游閘極作共有之 記憶體FET與控制閘極部所成之2電晶體，在位元線方 向上而相互併置於側方處所構成者。記憶體FET或控制 201023349 閘極部等之各部，係藉由以厚的氧化膜所成之元件分離區 域而被作分離。控制閘極部，係包含有相對於浮游閘極而 隔著閘極絕緣膜而相對峙之控制閘極。此浮游閘極非揮發 性記憶體裝置，係在半導體基板上形成主動區域，之後， 使例如氧化矽膜一般之閘極絕緣膜（穿隧絕緣膜）成長， 並於其上而沈積（堆積）浮游閘極（多晶矽）。主動區域 ，係如同週知一般，爲「使矽基板露出之部分」或者是「 藉由厚的氧化膜所形成之元件分離區域的外側」。記憶體 FET之閘極絕緣膜（穿隧絕緣膜），係藉由熱載體或是 FN電流而進行寫入以及消除。控制閘極部之閘極絕緣膜 ，係以藉由與記憶體FET之穿隧絕緣膜同材質的絕緣膜 來經由同一製程而製作爲理想。另外，在本說明書中，所 謂「穿隧絕緣膜」，係作爲代表在元件之動作上而通過此 膜來進行寫入以及/或是消除之絕緣膜的用語來使用。此 種穿隧絕緣膜，通常係藉由90A左右之氧化矽膜（或者 是在其中附加有若干之氮者）而被形成。爲了保證10年 間之資料保持特性，係有必要確保有某種程度的膜厚。相 反的，當就算保持期間較短亦無妨的情況時，則亦可將其 薄膜化，而不需要被此膜厚所限制。 在此些絕緣膜之上，將浮游閘極（多晶矽）以將記憶 體FET和控制閘極作連接的方式來製作。在浮游閘極之 長度方向上作延伸之位元線，係藉由金屬所形成，並透過 將層間絕緣膜作貫通之接點（以及矽化金屬層）而被連接 於記憶體FET之源極與汲極（N +源極、汲極）處。在N + 201023349 源極、汲極之表面上’係被形成有矽化金屬層。字元線， 係如同後述一般’爲經由與基板作了分離之埋入字元線所 形成。埋入字元線（主動層字元線），係作爲控制閘極而 起作用。在記憶體胞陣列內部，字元線係並不從金屬片而 具備有接點（因此，係成爲能夠省面積化），而成爲在記 憶體胞陣列之外側來被供給電位。另外，在本說明書中， 所謂「主動層」，係作爲代表（由厚的氧化膜所成之）元 φ 件分離區域以外的部分之用語而被使用。 藉由此，而能夠構成一種可藉由「控制閘極·浮游閘 極-通道」之連接而形成的非揮發性記憶體構造。之後， 經由離子注入（Ion Implantation)來作成記憶體FET之 汲極以及源極。又，依據通常之技術，如圖2(C)中所 不一般，在浮游閘極之側面，係作成 LDD ( Lightly Doped Drain)製作用之側壁間隔物，並且，浮游閘極之 上方係藉由矽化物金屬而被覆蓋。此矽化物金屬，和上述 φ 之N +源極、汲極表面之矽化物金屬，係藉由通常之製程 而同時地被矽化並被低電阻化。 特別是，如同於圖1中所見一般，係使1根的字元線 (例如wl)，由在圖中之縱方向而並排之第1行（胞1 、胞3、…）和第2行（胞2、胞4、…）所共有。但是 ，對1根的字元線作共有之2個的行，係相互使用相異之 位元線（亦即是，第1行係使用位元線a 1、a2、a3…， 第2行係使用位元線bl、b2、…）。而，在字元線方向 上相鄰接之胞（例如胞1與胞2)，係使各別之浮游閘極 -11 - 201023349 在位元線方向上而突出至相互之區域的字元線方向之側方 處，並以使控制閘極在字元線方向上作直線狀的並排的方 式，而典型性地偏移有節距之一半，並且，係相互以相反 方向（亦即是，在胞1處，控制閘極係位在圖中之左側， 相對於此，在胞2處，控制閘極係位於圖中之右側）而在 位元線方向上作偏移配置。經由此種配置，詳細而言，係 如同參考圖9而如後所述一般，而將每單位之胞的字元線 面積減少，而能夠實現一種省面積之記憶體胞陣列。 φ 記憶體FET，係可藉由NMOS或是PMOS之任一者來 形成，但是，從載體之移動度或是寫入特性等來看，係以 與通常之非揮發性記憶體同樣的而藉由NMOS來形成爲理 想。當藉由NMOS來形成的情況時，通道下之基板係爲p 型，源極S以及汲極D係爲n+，浮游閘極（多晶矽）係 爲H+。 圖1中所例示之佈局的記憶體胞之動作條件，係爲 NOR型。此記憶體胞，基本上，係準據於既存之浮游閘 · 極型記憶體胞而動作。以下，針對典型之動作條件作說明 。在寫入時，若是對於控制閘極與記憶體FET之汲極電 極施加高電壓，並將在記憶體FET之源極與汲極之間所 流動的電子設爲高能量，則電子係突破閘極絕緣膜（穿隧 絕緣膜）並進入至浮游閘極處。 資料之消除，係對於控制閘極施加負（-)的高電壓 ’並對源極電極施加正（+)的高電壓，且對汲極電極施 加〇V，而從所有之浮游閘極來將電子抽出。通常，在 -12- 201023349 NOR型之消除中，多係使汲極浮動，但是，在例示之佈 局中，由於係使汲極由複數之胞所共有，因此，係設爲 0V。 當讀出資料時，係對汲極電極施加一定之電壓，並對 控制閘極施加汲極電壓之約2倍的電壓，而判別是否流動 有多量的電流。讀出電壓，係可在兼顧有速度與信賴性的 狀態下而任意作決定。例如，在閘極處，係施加電源電壓 ❹ ，而在汲極處，係爲了防止由於高電壓而使電子被注入至 浮游閘極中，而施加某種程度之較低的電壓。在例示之佈 局中，係爲了將對汲極作共有之胞中的朝向非爲讀出側之 方向的電流消除，而對於其之源極施加與汲極相同之電位 。當在浮游閘極中不存在有電子的狀態下，在源極與汲極 之間（通道）係有多數的電子作移動，並流動有電流。另 一方面，當在浮游閘極中存在有電子的狀態時，在通道中 所流動之電子係變少。 φ 接著，記憶體FET，係可藉由NMOS或是PMOS中之 任一者來形成，但是，以下，係將藉由NMOS來形成的情 況作爲例子，而參考圖4〜圖6來針對控制閘極（字元線 )電壓之施加作說明。圖4〜圖6，係均爲在與圖2相同 之場所而作了切斷之字元線方向以及位元線方向之剖面圖 。僅有在圖4(A)中，係爲展示與圖1中所示者相同之 佈局，但是，圖5以及圖6之佈局以及切斷場所，亦爲同 一。圖4 ( B)以及（C )，係爲對於將控制閘極部形成在 P基板之N井中的第1方法作例示之圖。作爲控制閘極電 -13- 201023349 壓，當賦予正電壓的情況時，係在N井全體（與p +區域 )中施加正電壓，當賦予負電壓的情況時，係在P源極、 汲極處施加負電壓。 圖5(A)以及（B)，係爲對於追加在上述之第〗方 法中而在閘極絕緣膜之正下方處形成p型層之第2方法作 例示的圖。作爲控制閘極電壓，當賦予正電壓的情況時， 係在N井全體中施加正電壓，當賦予負電壓的情況時， 係在P型層處施加負電壓。相較於上述之第1方法，字元 線之電阻係變低。 在圖4以及圖5中’ P +層，係爲用以對於控制閘極而 賦予負電壓者。在圖4(B)中，P +區域係如同源極、汲 極區域一般之被切斷而被形成，但是，在消除時，係在浮 游閘極下方形成通道並成爲被相互作連接。相對於此，在 圖5(A)中，係被形成有連續之P +區域。在典型之n〇R 型的動作條件中’在消除時係有必要對於控制閘極而賦予 負電壓，但是，由於N井之電位係無法成爲較P基板而 更低，因此，爲了賦予負電壓，係有必要在N井之中而 定義P型之區域。 圖 6(A)以及（B)，係爲對於 SOI ( Silicon On[Technical Field] The present invention relates to a floating gate type non-volatile memory arrangement configuration in which a plurality of cells are arranged in a matrix line direction and a bit line direction. [Prior Art] As a non-volatile memory, φ is known as a stacked floating gate structure. Fig. 10 is a view showing a non-volatile memory device having the prior art stacked structure described in Patent Document 1. On the germanium substrate, a gate insulating film made of a thin tantalum oxide film, a source and a drain region are formed, and on the drain insulating film, layers are sequentially laminated: The floating gate electrode, the interlayer insulating film and the control gate electrode formed by the polycrystalline germanium film. The illustrated non-volatile memory device performs information writing, holding, and erasing by accumulating charges in the floating gate electrode and discharging the charge from the floating gate electrode 。. Since it is a structure commonly used in a memory chip, its processes and components are also well known. Since the structure of the gate electrode is laminated above the floating gate electrode, it is high density. However, the second layer of the polycrystalline ruthenium film is formed by the floating gate electrode formed by the polycrystalline ruthenium film of the first layer (polysilicon) and separated from the floating gate electrode by the interlayer insulating film. In order to form the control gate electrode, the manufacturing process system becomes complicated and disadvantageous in terms of cost. Therefore, it is known that a layer of crystalline ruthenium film is used to form a float--5-201023349 gate electrode, and a non-volatile memory for controlling a gate electrode is formed by a diffusion region (refer to the patent literature). 2, 3). Fig. 11 (A) is a pattern layout diagram showing a prior art non-volatile memory device described in Patent Document 2, and Fig. 11 (B) is a cross-sectional view taken along line X-X. In the element region of the surface of the germanium substrate, a dielectric FET including a source and a drain region and a diffusion region for controlling the gate are formed. A floating gate is formed on the channel region between the source and drain regions and on a portion of the control gate diffusion region _ via the extremely thin oxide films a and b, respectively. Further, in the channel region between the drain region and the bit line diffusion region, a selective transistor in which a gate electrode is formed via a gate oxide film is provided. Further, the CVD oxide film which is deposited in a comprehensive manner is formed with a common potential line connected to the source region via the contact hole a, and is connected to the bit line diffusion region via the contact hole b. The bit line. In such a non-volatile memory, the control gate is made to have a high potential by the diffusion φ region, and the drain region is set to 0 V, thereby accumulating charges in the floating gate to perform the elimination operation. . Further, by setting the control gate diffusion region to OV and the drain region to a high potential, the charge flows from the floating gate to the drain region to perform a write operation. In the non-volatile memory device shown, since the floating gate electrode is formed by only one layer of crystalline ruthenium film, the manufacturing process is simple. However, since the gate electrode is not controlled, It is placed above the floating gate electrode, but is arranged on the side, so there is a problem that the cell area is -6-201023349. On the other hand, a non-volatile memory of a hypothetical ground type is known (refer to Patent Document 4). The non-volatile memory of the imaginary grounding type is constructed by exchanging the source and the drain and operating it symmetrically, whereby the integrated density of the memory cells can be improved. [PRIOR ART DOCUMENT] [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei. No. Hei. No. Hei. No. Hei. [Problem to be Solved by the Invention] The present invention has been made in order to solve the above problems, and the following matters are aimed at: The control gate portion shared by the floating gate is disposed in the floating gate type non-volatile memory at the side of the memory FET, and realizes the memory cell array formed by the virtual ground type. And realize a memory cell array with a low cost and a provincial area. [Means for Solving the Problem] The present invention relates to a configuration of a floating gate type non-volatile memory configuration, wherein one floating gate type non-volatile memory device is used as one cell-7-201023349, and Configuring a plurality of cells into a matrix line direction and a bit line direction, wherein the one floating gate type non-volatile memory device is a memory that is shared by the floating gates. The two transistors formed by the FET and the control gate portion are disposed on the semiconductor substrate, and the control gate portion includes a control gate opposite to the floating gate via the gate insulating film. . a bit line extending above the floating gate and extending in a longitudinal direction thereof, and the word line functioning as the control gate is in a direction orthogonal to the bit line extend. Cells that are common to the same word line and that are adjacent in the direction of the word line are configured to be opposite to each other and offset in the direction of the bit line, and the adjacent ones are arranged The control gates of the cells are arranged side by side in the direction of the word line to arrange the floating gates of the cells adjacent to each other in the direction of the word line to protrude from each other in the direction of the bit line. To the side of the direction of the word line. For the two cell lines that are common to the same word line, different bit lines are used for each other. The word line is formed by a buried word line that is separated from the semiconductor substrate, and the inside of the memory arrangement is not provided with a contact from the metal piece, but is external to the memory arrangement. The potential is supplied. A plurality of cells are configured to realize a memory configuration by a virtual grounding type. [Effect of the Invention] According to the present invention, a memory cell array structure by a virtual ground is realized, and a memory cell array having a low cost and a small area can be realized. Furthermore, by using the word line caused by the active -8 - 201023349 layer and offsetting the pitch of the adjacent cells, the floating gates are arranged in the direction of the word lines of the mutual regions. At the side, and the cells of the opposite face share the word line with each other, the area of the word line of each unit cell can be reduced. [Embodiment] Hereinafter, the present invention will be described based on an example. A first example of the configuration of the floating gate type non-volatile memory in which the present invention is embodied will be described with reference to Figs. 1 to 6 φ. Figure 1 is a diagram showing the layout. However, in actual products, usually more cells are arranged in a matrix, however, the layout of Figure 1 is taken out and illustrated (in the following description, the word lines are drawn) The direction is the row, and the bit line direction is used as the column). Further, a decoder for switching the potential to the bit line and the word line is usually provided, but is omitted in the drawings. Fig. 2(A) is a diagram showing the same layout as Fig. 1, and Fig. 2(B) and Fig. 2(C) are the places shown by the broken lines in Fig. 2(A), respectively. A cross-sectional view of the direction of the word line and the direction of the bit line. Fig. 3(A) is a view showing the same layout as Fig. 1, and Fig. 3(B) is shown by a broken line in Fig. 3(A) (different from Fig. 2(B)). A cross-sectional view of the location of the word line. The structure of the floating gate type non-volatile memory device is particularly as shown in FIG. 2(C), which is a transistor formed by a memory FET and a control gate portion which are common to the floating gate. , in the direction of the bit line and placed side by side with each other. Memory FET or Control 201023349 Each part of the gate and the like is separated by a component separation region formed by a thick oxide film. The control gate portion includes a control gate that is opposed to the gate electrode with respect to the floating gate and is opposed to each other via the gate insulating film. The floating gate non-volatile memory device forms an active region on a semiconductor substrate, and then, for example, a gate insulating film (tunneling insulating film) of a general yttrium oxide film is grown and deposited (stacked) thereon. Floating gate (polysilicon). The active region is, as is well known, "the portion where the germanium substrate is exposed" or "the outer side of the element isolation region formed by the thick oxide film". The FET's gate insulating film (tunneling insulating film) is written and erased by a heat carrier or FN current. It is preferable that the gate insulating film of the gate portion is formed by the same process as the insulating film of the same material as the tunneling insulating film of the memory FET. In the present specification, the term "tunneling insulating film" is used as a term for an insulating film which is written and/or erased by the film in the operation of the element. Such a tunneling insulating film is usually formed by a yttrium oxide film of about 90 A (or a nitrogen gas added thereto). In order to maintain the data retention characteristics for 10 years, it is necessary to ensure a certain degree of film thickness. Conversely, even if the holding period is short, it can be thinned without being limited by the film thickness. On the insulating films, a floating gate (polysilicon) is formed by connecting a memory FET and a control gate. A bit line extending in the length direction of the floating gate is formed by a metal and is connected to the source and the drain of the memory FET through a contact (and a deuterated metal layer) through which the interlayer insulating film is formed. (N + source, bungee). On the surface of the N + 201023349 source and the drain, a layer of deuterated metal is formed. The word line, as will be described later, is formed by a buried word line separated from the substrate. Buried word lines (active layer word lines) function as control gates. In the memory cell array, the word line system does not have a contact from the metal piece (hence, it is possible to reduce the area), and the potential is supplied to the outside of the memory cell array. In the present specification, the "active layer" is used as a term representing a portion other than the element φ separation region (formed by a thick oxide film). Thereby, a non-volatile memory structure which can be formed by the connection of "control gate/floating gate-channel" can be constructed. Thereafter, the drain and the source of the memory FET are formed by ion implantation (Ion Implantation). Further, according to a conventional technique, as shown in FIG. 2(C), a sidewall spacer for LDD (Lightly Doped Drain) fabrication is formed on the side of the floating gate, and the upper portion of the floating gate is used. Covered with a telluride metal. The telluride metal, and the above-mentioned N + source of the φ and the vaporized metal of the surface of the drain are simultaneously deuterated and reduced in resistance by a usual process. In particular, as seen in Fig. 1, one character line (e.g., wl) is made up of the first row (cell 1, cell 3, ...) and the second row side by side in the longitudinal direction of the figure. (cell 2, cell 4, ...) are shared. However, for the two word lines that are shared by one word line, different bit lines are used for each other (that is, the first line uses the bit lines a 1 , a2 , a3 , ..., the second line). The bit lines bl, b2, ...) are used. However, adjacent cells in the direction of the word line (for example, cell 1 and cell 2) are such that the respective floating gates -11 - 201023349 protrude in the bit line direction to the word lines of the mutual regions. At the side of the direction, and in a manner such that the control gates are linearly arranged side by side in the direction of the word line, typically offset by one-half of the pitch, and in opposite directions to each other (ie, At cell 1, the control gate is located on the left side of the figure, whereas at cell 2, the control gate is located on the right side of the figure) and offset in the bit line direction. With this configuration, in detail, as will be described later with reference to Fig. 9, the word line area per unit cell is reduced, and a memory area array of a memory area can be realized. The φ memory FET can be formed by either NMOS or PMOS, but borrowed from the carrier's mobility or write characteristics, and is borrowed in the same way as a normal non-volatile memory. It is ideal to form by NMOS. When formed by an NMOS, the substrate under the channel is p-type, the source S and the drain D are n+, and the floating gate (polysilicon) is H+. The operating conditions of the memory cells of the layout illustrated in Fig. 1 are of the NOR type. This memory cell, basically, is based on the existing floating gates and polar memory cells. The following is a description of typical operating conditions. At the time of writing, if a high voltage is applied to the gate electrode of the control gate and the memory FET, and the electron flowing between the source and the drain of the memory FET is set to high energy, the electron system breaks through the gate. A pole insulating film (tunneling insulating film) enters the floating gate. The elimination of the data is to apply a negative (-) high voltage to the control gate and apply a positive (+) high voltage to the source electrode and apply 〇V to the drain electrode, and from all floating gates Electronic extraction. In general, in the elimination of the -12-201023349 NOR type, the multi-system floats the bungee. However, in the illustrated layout, since the bungee is shared by the plural cells, it is set to 0V. When data is read, a certain voltage is applied to the drain electrode, and a voltage about twice the gate voltage is applied to the control gate to determine whether or not a large amount of current flows. The read voltage can be arbitrarily determined in a state where both speed and reliability are achieved. For example, at the gate, a supply voltage ❹ is applied, and at the gate, a certain lower voltage is applied to prevent electrons from being injected into the floating gate due to a high voltage. In the illustrated layout, in order to eliminate the current in the direction in which the drain is shared, the direction opposite to the read side is applied, and the source having the same potential as the drain is applied to the source thereof. When there is no electron in the floating gate, a large number of electrons move between the source and the drain (the channel), and a current flows. On the other hand, when there is an electron state in the floating gate, the number of electrons flowing in the channel becomes small. φ Next, the memory FET can be formed by either NMOS or PMOS. However, in the following, a case where the NMOS is formed will be taken as an example, and the control gate will be referred to with reference to FIGS. 4 to 6 . The application of the pole (word line) voltage is explained. 4 to 6 are cross-sectional views in the direction of the character line and the direction of the bit line which are cut in the same place as in Fig. 2. Only in Fig. 4(A), the same layout as that shown in Fig. 1 is shown, but the layout and the cutting place of Figs. 5 and 6 are also the same. 4(B) and (C) are diagrams for exemplifying the first method of forming the control gate portion in the N well of the P substrate. As the control gate power -13 - 201023349, when a positive voltage is applied, a positive voltage is applied to the entire N well (with the p + region), and when a negative voltage is applied, it is at the P source, 汲A negative voltage is applied to the pole. Figs. 5(A) and 5(B) are diagrams showing a second method of forming a p-type layer directly under the gate insulating film in the above-described method. As the control gate voltage, when a positive voltage is applied, a positive voltage is applied to the entire N well, and when a negative voltage is applied, a negative voltage is applied to the P-type layer. The resistance of the word line is lower than that of the first method described above. In Figs. 4 and 5, the 'P + layer is used to apply a negative voltage to the control gate. In Fig. 4(B), the P + region such as the homologous pole and the drain region are generally cut and formed, but, in the case of elimination, channels are formed under the floating gate and are connected to each other. On the other hand, in Fig. 5(A), a continuous P + region is formed. In the typical n〇R type operating conditions, it is necessary to apply a negative voltage to the control gate during the elimination. However, since the potential of the N well cannot be lower than that of the P substrate, in order to impart a negative voltage. It is necessary to define a P-type area in the N well. Figure 6 (A) and (B) for SOI ( Silicon On
Insulator)所致之第3方法作例示的圖。在作爲絕緣膜的 氧化膜之上，形成各節點。控制閘極部，係能夠容易地從 其他節點而絕緣’又，控制閘極部之雜質型態，係可設定 爲任意。將閘極電壓施加在藉由氧化膜而被作了絕緣的控 制閘極部之基板處。 201023349 圖7(A) 、（B)以及圖8，係爲對於將本發明具體 化之浮游閘極型非揮發性記憶體配置構成的第2例作說明 之圖。圖7(A)以及（B)，係分別爲相當於圖2(B) 以及（C )之字元線方向以及位元線方向的剖面圖。又， 圖8，係爲與圖3(B)相當之字元線方向的剖面圖。在圖 7(A)以及（B)還有圖8中所例示之第2例，與上述之 第1例，係僅在於浮游閘極以及閘極絕緣膜之構成上有所 φ 相異。 在圖7(A)以及（B)還有圖8中所示之浮游閘極型 記憶體胞中，記憶體FET之閘極絕緣膜（穿隧絕緣膜） ，係藉由熱載體或是FN電流而進行寫入以及消除。控制 閘極部之閘極絕緣膜，係藉由閘極絕緣膜A (與穿隧絕緣 膜同材質之絕緣膜）與閘極絕緣膜B( High-k絕緣膜）的 2層所構成。圖示之構成，係藉由將爲了實現非揮發性記 憶體所必要之穿隧絕緣膜、和邏輯製程中所已經持有的 φ high-k絕緣膜作組合，而能夠在保持有電容的狀態下來對 於漏洩電流作抑制（高電容、低漏洩）。藉由此，而成爲 能夠進行安定之寫入與消除，並使電荷之長期保存成爲可 能。例示之2層構造（使用有high-k絕緣膜），係可經 由從通常之邏輯CMOS之製程而進行最小限度之製程變更 來實現非揮發性記憶體。 浮游閘極’係爲將閘極電極a、閘極電極b、閘極電 極c作一體化連接而構成。在控制閘極部上，係於閘極絕 緣膜B( high-k絕緣膜）上’形成由金屬或是多晶矽所成 -15- 201023349 之閘極電極b。在記憶體FET上，形成閘極電極a。進而 ，將閘極電極c (多晶矽）使用來將記憶體FET與控制閘 極作連接。當閘極電極b爲金屬的情況時，閘極電極c( 多晶矽）之雜質型態係並不會造成問題。於此，關於將薄 的金屬閘極堆積在high-k閘極絕緣膜的正上方，並於其 上堆積厚的多晶矽膜一事’係爲在考慮到能夠利用金屬閘 極之任意的工作函數、和多晶矽之易於加工性後所得的結 果。 圖9,係爲圖1中所示之浮游閘極型非揮發性記憶體 佈局的等價電路圖。但是’係藉由將圖1中所示之佈局作 了 90度旋轉後的配置來作例示。如圖示—般，而實現有 假想接地型（virtual ground )所致之記憶體胞陣列構成。 對於相同之字元線作共有之圖中的上下之記憶體胞行，係 相互使用相異之位元線。字元線’係藉由上下之胞而被有 效率地作共有。 本發明’係經由採用假想接地型之胞陣列，而能夠將 每單位胞之接點的數量減少（在汲極處1/2個、在源極處 1 /2個’合計1個）。若是非爲假想接地型的構成，則係 需要在汲極與源極處具備各1個的接點，或者是，就算是 僅使源極接點成爲能夠與其他之胞作共有，亦成爲在每單 位胞處而需要合計1.5〜2個的接點，若是對於該接點本 身之面積、或是將該接點從其他節點而切離所需的空間作 考慮’則係成爲產生大幅的面積增加。 進而’雖係採用由主動層所致之字元線，但是，藉由 -16- 201023349 對佈局作設計（將相鄰接之胞各偏移半個節距地作配置， 而使浮游閘極之突起成爲突出至相互之區域處）’來使相 對面之胞彼此分享字元線，能夠將每一單位胞之字元線的 面積減少。（爲了形成字元線）所需要之面積’係成爲主 動層最小寬幅之一半與接點節距（當將浮游閘極與接點交 互作配置的情況時之最小節距）的積。當並不使用主動層 字元線的情況時，則除了字元線的金屬配線以外，亦成爲 φ 需要用以從該處而對主動層作接觸之大的面積。又，就算 是使用主動層所致之字元線，當並未採用本佈局一般之將 字元線於相對面之胞而作共用之設計的情況時，由於係成 爲在各胞處均需要主動層，且將其與相對面之胞作分離之 面積亦成爲必要，因此，係成爲使面積增加。 以上，在本揭示中，雖係單純對於數種的實施型態作 例示並詳細的作了說明，但是，在不從本發明之新穎的揭 示內容以及有利的效果而實質性脫離的範圍內，於該實施 _ 型態中，係可存在有多數的改變例。 【圖式簡單說明】 [圖π對於將本發明具體化之浮游閘極型非揮發性記 憶體配置構成的第1例之佈局作展示的圖。 [圖2] (A)係爲對於與圖1相同之佈局作展示的圖 ，（B )以及（C )係分別爲（A )中之以虛線所展示的場 所之字元線方向以及位元線方向的剖面圖。 [圖3] (A)係爲對於與圖1相同之佈局作展示的圖 -17- 201023349 ，（B)係爲（A)中之以虛線所展示（與圖2(B)爲相 異）的場所之字元線方向的剖面圖。 [圖4]對於將控制閘極部形成在P基板之N井中的第 1方法作例示之圖。 [圖5]對於追加在圖4之第1方法中而在閘極絕緣膜 之正下方處形成P型層之第2方法作例示的圖。 [圖 6]對於 SOI ( Silicon On Insulator)所致之第 3 方 法作例示的圖。 @ [圖7](A)以及（B)，係爲對於將本發明具體化之 浮游閘極型非揮發性記憶體配置構成的第2例作說明的圖 ’且分別爲與圖2(B)以及圖2(C)相當之字元線方向 以及位元線方向之剖面圖。 [圖8]於第2例中，與圖3(B)相當之字元線方向的 剖面圖。 [圖9]圖1中所示之浮游閘極型非揮發性記憶體佈局 的等價電路圖。 @ [圖10]對於具備有先前技術之堆疊構造的非揮發性記 憶體裝置作展示之圖。 [圖1 1 ]( A )係爲對先前技術之非揮發性記憶體裝置 作展示的圖案佈局圖，（b )係爲展示沿著x-x線之剖面 圖。 【元件符號說明】 al〜a5 :位元線 -18- 201023349 b 0〜b 4 :位元線 w 1〜w 2 :字元線The third method resulting from Insulator is illustrated. On the oxide film as an insulating film, each node is formed. The gate portion can be easily insulated from other nodes, and the impurity pattern of the gate portion can be controlled to be arbitrary. A gate voltage is applied to the substrate of the control gate portion insulated by the oxide film. 201023349 Figs. 7(A), (B) and Fig. 8 are views for explaining a second example of the configuration of the floating gate type non-volatile memory in which the present invention is embodied. 7(A) and 7(B) are cross-sectional views corresponding to the character line direction and the bit line direction of Figs. 2(B) and (C), respectively. Further, Fig. 8 is a cross-sectional view taken in the direction of the character line corresponding to Fig. 3(B). In Figs. 7(A) and (B), there is also a second example illustrated in Fig. 8, and the first example described above differs only in the configuration of the floating gate and the gate insulating film. In FIGS. 7(A) and (B) and the floating gate type memory cell shown in FIG. 8, the gate insulating film (tunneling insulating film) of the memory FET is by a heat carrier or FN. Write and erase with current. The gate insulating film of the gate portion is composed of two layers of a gate insulating film A (an insulating film of the same material as the tunnel insulating film) and a gate insulating film B (a high-k insulating film). The configuration shown in the figure is capable of maintaining a capacitor state by combining a tunneling insulating film necessary for realizing a nonvolatile memory and a φ high-k insulating film which has been held in a logic process. This suppresses the leakage current (high capacitance, low leakage). As a result, writing and erasing of stability can be performed, and long-term storage of electric charges is possible. The exemplified two-layer structure (using a high-k insulating film) realizes non-volatile memory by performing a minimum process change from a conventional logic CMOS process. The floating gate electrode is formed by integrally connecting the gate electrode a, the gate electrode b, and the gate electrode c. On the gate portion of the gate, a gate electrode b of -15-201023349 formed of metal or polysilicon is formed on the gate insulating film B (high-k insulating film). On the memory FET, a gate electrode a is formed. Further, a gate electrode c (polysilicon) is used to connect the memory FET to the control gate. When the gate electrode b is a metal, the impurity type of the gate electrode c (polysilicon) does not cause a problem. Here, the deposition of a thin metal gate directly above the high-k gate insulating film and the deposition of a thick polycrystalline germanium film thereon is considered to be an arbitrary work function in consideration of the use of the metal gate. And the results obtained after the easy processing of polycrystalline germanium. Figure 9 is an equivalent circuit diagram of the floating gate type non-volatile memory layout shown in Figure 1. However, it is exemplified by the configuration in which the layout shown in Fig. 1 is rotated by 90 degrees. As shown in the figure, a memory cell array structure due to virtual ground is realized. For the upper and lower memory cell rows in the common figure of the same word line, different bit lines are used for each other. The word line ' is effectively shared by the upper and lower cells. The present invention can reduce the number of contacts per unit cell (one at 1/2 of the drain and one at the source) by using a virtual ground type cell array. If it is not a hypothetical grounding type, it is necessary to have one contact at each of the drain and the source, or even if only the source contact can be shared with other cells, A total of 1.5 to 2 contacts are required per unit cell, and if the area of the contact itself is taken or the space required to cut the contact from other nodes is considered, it is a large area. increase. Furthermore, 'the character line is caused by the active layer, but the layout is designed by-16-201023349 (the adjacent cells are offset by half pitch, and the floating gate is configured. The protrusions protrude to the mutual regions) to allow the cells of the opposite faces to share the word lines with each other, and the area of the word line of each unit cell can be reduced. The area required to form the word line is the product of one of the minimum width of the active layer and the contact pitch (the minimum pitch when the floating gate is placed in contact with the contact). When the active layer word line is not used, in addition to the metal wiring of the word line, it is also a large area where φ is required to make contact with the active layer from there. Moreover, even if the character line caused by the active layer is used, when the layout of the word line is used in the opposite side of the cell as a common design, the system needs to be active at each cell. It is also necessary to separate the layer from the cell of the opposite surface, and therefore, the area is increased. In the above, although the embodiments of the present invention have been described by way of example only, and are not described in detail, the scope of the invention In this implementation mode, there may be a majority of variations. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. π is a view showing a layout of a first example of a configuration of a floating gate type non-volatile memory device in which the present invention is embodied. [Fig. 2] (A) is a diagram showing the same layout as that of Fig. 1, and (B) and (C) are respectively the character line direction and the bit of the place shown by the broken line in (A). A cross-sectional view of the line direction. [Fig. 3] (A) is a diagram -17-201023349 which is shown for the same layout as Fig. 1, and (B) is shown by a broken line in (A) (different from Fig. 2(B)) A section of the location of the character in the direction of the line. Fig. 4 is a view showing an example of a first method of forming a control gate portion in a N-well of a P substrate. Fig. 5 is a view showing an example of a second method of forming a P-type layer directly under the gate insulating film in the first method of Fig. 4. [Fig. 6] A diagram exemplified for the third method by SOI (Silicon On Insulator). @ [Fig. 7] (A) and (B) are diagrams for explaining a second example of the configuration of the floating gate type non-volatile memory in which the present invention is embodied, and are respectively associated with Fig. 2 (B). And the cross-sectional view of the character line direction and the bit line direction corresponding to Fig. 2(C). Fig. 8 is a cross-sectional view in the direction of the character line corresponding to Fig. 3(B) in the second example. [Fig. 9] An equivalent circuit diagram of the floating gate type non-volatile memory layout shown in Fig. 1. @ [Fig. 10] A diagram showing a nonvolatile memory device having a stacked structure of the prior art. [Fig. 1 1] (A) is a pattern layout showing a prior art non-volatile memory device, and (b) is a cross-sectional view along the x-x line. [Description of component symbols] al~a5: bit line -18- 201023349 b 0~b 4 : bit line w 1~w 2 : word line
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