JPWO2010038426A1 - Floating gate type non-volatile memory layout - Google Patents

Abstract

The present invention realizes a virtual ground type memory cell array configuration, and realizes a memory cell array which is an inexpensive process and has a small area. Each of the floating gate type nonvolatile memory devices arranged in a matrix is composed of two transistors including a memory FET sharing a floating gate and a control gate portion, and the control gate portion is connected to the floating gate via a gate insulating film. Control gates that face each other. The bit line extends in the length direction above the floating gate, and the word line functioning as a control gate extends in a direction perpendicular to the bit line. Cells that share the same word line and are adjacent to each other in the word line direction are shifted by half the pitch so that the floating gates protrude from each other, and are arranged in opposite directions.

Description

  The present invention relates to a floating gate type nonvolatile memory arrangement configuration in which a plurality of cells are arranged in a matrix in a word line direction and a bit line direction.

  A stack type floating gate structure is known as a nonvolatile memory. FIG. 10 is a diagram showing a nonvolatile memory device having a conventional stack structure described in Patent Document 1. In FIG. A gate insulating film made of a thin silicon oxide film and source and drain regions are formed on the silicon substrate, and a floating gate electrode made of a polycrystalline silicon film, an interlayer insulating film and a polycrystalline silicon film are formed on the gate insulating film. Gate electrodes are sequentially stacked. In the illustrated nonvolatile memory device, information is written, held, and erased by accumulating charges in the floating gate electrode or discharging charges from the floating gate electrode. Since it is a structure usually used in a memory chip, it is well known as a process and a device. High density due to the structure in which the control gate electrode is stacked above the floating gate electrode. However, in order to form the floating gate electrode from the first polycrystalline silicon film (polysilicon) and to form the control gate electrode from the second polycrystalline silicon film separated from the floating gate electrode by the interlayer insulating film. The manufacturing process becomes complicated and disadvantageous in terms of cost.

  For this purpose, a nonvolatile memory is known in which a floating gate electrode is formed using a single layer of polycrystalline silicon film, and a control gate electrode is formed of a diffusion region (see Patent Documents 2 and 3). FIG. 11A shows a pattern layout showing a conventional nonvolatile memory device described in Patent Document 2, and FIG. 11B shows a cross-sectional view taken along line XX.

  A memory FET including source and drain regions and a control gate diffusion region are formed in the element region on the surface of the silicon substrate. Floating gates are formed on the channel region between the source and drain regions and on a part of the control gate diffusion region via ultrathin oxide films a and b, respectively. Further, a select transistor in which a select gate is formed via a gate oxide film is provided on the channel region between the drain region and the bit line diffusion region. Further, on the CVD oxide film deposited on the entire surface, a common potential line connected to the source region via the contact hole a, and a bit line diffusion region connected to the contact hole b are connected. Bit lines are formed.

  In such a nonvolatile memory, erasing is performed by setting the control gate diffusion region to a high potential, the drain region to 0 V, and accumulating charges in the floating gate. Writing is performed by setting the control gate diffusion region to 0 V, the drain region to a high potential, and allowing charge to flow out from the floating gate to the drain region.

  The non-volatile memory device shown in the figure is formed by forming only the floating gate electrode with a single layer of polycrystalline silicon film, which simplifies the manufacturing process. However, the control gate electrode is not on the floating gate electrode but on the side. Therefore, there is a problem that the cell area becomes large.

  On the other hand, a virtual ground type nonvolatile memory is known (see Patent Document 4). The virtual ground nonvolatile memory can be configured to operate symmetrically by switching the source and drain, thereby increasing the integration density of the memory cells.

Japanese Patent Laid-Open No. 10-223783 JP-A-6-53521 JP-A-10-70204 JP 2007-157280 A

  The present invention solves such a problem and realizes a virtual ground type memory cell array configuration in a floating gate type nonvolatile memory in which a control gate portion sharing a floating gate is arranged on the side of the memory FET. An object of the present invention is to realize a memory cell array which is an inexpensive process and has a small area.

  The present invention relates to a floating gate type nonvolatile memory arrangement in which one floating gate type nonvolatile memory device is used as one cell and a plurality of cells are arranged in a matrix in the word line direction and bit line direction. One floating gate type nonvolatile memory device includes a memory FET sharing a floating gate and two transistors composed of a control gate part on a semiconductor substrate. The control gate part is connected to the floating gate. A control gate is provided opposite to the gate insulating film. The bit line extends in the length direction above the floating gate, and the word line functioning as the control gate extends in a direction orthogonal to the bit line. Cells that share the same word line and are adjacent in the word line direction are arranged opposite to each other and shifted in the bit line direction, and the control gates of the adjacent cells are arranged in a straight line in the word line direction. The floating gates of the cells adjacent in the word line direction are alternately arranged on the sides in the word line direction. Two cell rows sharing the same word line use different bit lines. The word line is formed by a buried word line separated from the semiconductor substrate, and has no contact from metal inside the memory arrangement, and is supplied with a potential outside the memory arrangement. The plurality of cells implement a virtual ground type memory arrangement configuration.

  According to the present invention, it is possible to realize a memory cell array configuration of a virtual ground type, and to realize a memory cell array which is an inexpensive process and saves area. Furthermore, the word lines of the active layer are adopted, the pitches of adjacent cells are shifted, and the floating gates are alternately arranged on the side of the word line direction of each region, so that the facing cells are word-to-word. By sharing the lines, the area of the word lines per cell can be reduced.

It is a figure which shows the layout of the 1st example of the floating gate type non-volatile memory arrangement configuration which embodies this invention. (A) is a view showing the same layout as FIG. 1, and (B) and (C) are cross-sectional views in the word line direction and the bit line direction of a portion indicated by a dotted line in (A), respectively. (A) is a view showing the same layout as FIG. 1, and (B) is a cross-sectional view in the word line direction of a portion indicated by a dotted line in (A) (different from FIG. 2 (B)). . It is a figure which illustrates the 1st method which formed the control gate part in the N well of P substrate. FIG. 5 is a diagram illustrating a second method of forming a p-type layer immediately below the gate insulating film in addition to the first method of FIG. 4. It is a figure which illustrates the 3rd method by SOI (Silicon On Insulator). (A) And (B) is a figure explaining the 2nd example of the floating gate type non-volatile memory arrangement configuration which embodies the present invention, and is equivalent to Drawing 2 (B) and Drawing 2 (C), respectively. It is sectional drawing of a word line direction and a bit line direction. FIG. 4 is a cross-sectional view in the word line direction corresponding to FIG. FIG. 2 is an equivalent circuit diagram of the floating gate nonvolatile memory layout shown in FIG. 1. 1 is a diagram illustrating a nonvolatile memory device having a conventional stack structure. FIG. (A) shows a pattern layout showing a conventional nonvolatile memory device, and (B) shows a cross-sectional view taken along line XX.

  Hereinafter, the present invention will be described based on examples. A first example of a floating gate type nonvolatile memory arrangement embodying the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a layout. However, in an actual product, more cells are usually arranged in a matrix, but the layout of FIG. 1 shows a part of the layout (in the following description, a word line). Direction is row, bit line direction is column). Also, a decoder for switching the potential to the bit line and the word line is usually provided, but it is not shown. 2A is a diagram showing the same layout as FIG. 1, and FIG. 2B and FIG. 2C are the word line direction and the bit line at the locations indicated by the dotted lines in FIG. 2A, respectively. It is sectional drawing of a direction. 3A is a diagram showing the same layout as FIG. 1, and FIG. 3B is a word line at a location indicated by a dotted line in FIG. 3A (different from FIG. 2B). It is sectional drawing of a direction.

  In particular, as shown in FIG. 2C, the structure of the floating gate type nonvolatile memory device is such that a memory FET sharing a floating gate and two transistors composed of a control gate portion are arranged side by side in the bit line direction. Configured. Each part such as a memory FET or a control gate part is separated by an element isolation region made of a thick oxide film. The control gate portion includes a control gate that faces the floating gate via a gate insulating film. In this floating gate type nonvolatile memory device, after forming an active region in a semiconductor substrate, a gate insulating film (tunnel insulating film) such as a silicon oxide film is grown, and a floating gate (polysilicon) is formed thereon. Deposit (deposit). As is well known, the active region is “a portion where the silicon substrate is exposed” or “outside the element isolation region formed of a thick oxide film”. The gate insulating film (tunnel insulating film) of the memory FET is written and erased by hot carriers or FN current. The gate insulating film of the control gate portion is preferably manufactured by the same process using an insulating film made of the same material as the tunnel insulating film of the memory FET. In the present specification, the “tunnel insulating film” is used as a term meaning an insulating film in which writing and / or erasing is performed through this film during device operation. Such a tunnel insulating film is usually formed of a silicon oxide film of about 90 A (or a film in which nitrogen is slightly added). It is necessary to secure a certain film thickness in order to guarantee the data retention characteristics for 10 years. On the other hand, when the holding period may be short, the film thickness may be reduced and it is not necessary to be restricted by this film thickness.

  On these insulating films, a floating gate (polysilicon) is formed so as to connect the memory FET and the control gate. The bit line extending in the length direction of the floating gate is formed of metal, and is connected to the source and drain (N + source / drain) of the memory FET through a contact (and silicide) penetrating the interlayer insulating film. Silicide is formed on the surface of the N + source / drain. The word line is formed by a buried word line separated from the substrate as will be described later. The buried word line (active layer word line) functions as a control gate. Inside the memory cell array, the word line does not have a contact from metal (thus, the area can be saved), and a potential is supplied outside the memory cell array. In the present specification, the “active layer” is used as a term meaning a portion other than the element isolation region (by a thick oxide film).

  Thus, a nonvolatile memory structure that can be formed by a connection of control gate-floating gate-channel can be configured. Thereafter, the drain and source of the memory FET are formed by implantation (ion implantation). Further, according to a normal technique, as shown in FIG. 2C, the side surface of the floating gate is formed with a sidewall spacer for LDD (Lightly Doped Drain) fabrication, and the floating gate is covered with silicide. This silicide and the silicide on the surface of the N + source / drain are simultaneously silicided and reduced in resistance by a normal process.

  In particular, as seen in FIG. 1, one word line (for example, w1) is arranged in a first row (cell 1, cell 3,...) Arranged in the vertical direction in the figure and a second row. (Cell 2, cell 4,...) Are shared. However, two rows sharing one word line use different bit lines (that is, the first row uses bit lines a1, a2, a3,..., The second row uses bit line b1). , B2... The cells adjacent to the word line direction (for example, the cell 1 and the cell 2) are arranged so that their floating gates are staggered laterally in the word line direction, that is, to the side of the mutual word line direction. The control gates are typically offset by half the pitch so that the control gates are linearly aligned in the word line direction and in opposite directions (ie, in cell 1 the control gate is on the left side of the figure). In contrast, the cell 2 is shifted in the bit line direction (on the right side in the figure). With such an arrangement, as will be described in detail later with reference to FIG. 9, it is possible to reduce the area of the word lines per cell and to realize a memory cell array with reduced area.

  The memory FET can be formed of either NMOS or PMOS, but is preferably formed of NMOS in the same manner as a normal nonvolatile memory in view of carrier mobility and write characteristics. When formed of NMOS, the substrate under the channel is p-type, the source S and drain D are n +, and the floating gate (polysilicon) is n +.

  The operation condition of the memory cell having the layout illustrated in FIG. 1 is a NOR type. This memory cell basically operates in accordance with an existing floating gate type memory cell. Hereinafter, typical operating conditions will be described. When writing, if a high voltage is applied to the control gate and the drain electrode of the memory FET and the electrons flowing between the source and drain of the memory FET are made high energy, the electrons float through the gate insulating film (tunnel insulating film). Jump into the gate.

  To erase data, a negative (−) high voltage is applied to the control gate, a positive (+) high voltage is applied to the source electrode, and 0 V is applied to the drain electrode, and electrons are extracted from all floating gates. Normally, the drain is often floated in NOR-type erasure, but in the illustrated layout, the drain is shared by a plurality of cells, so that it is set to 0V.

  When reading data, a constant voltage is applied to the drain electrode and a voltage about twice the drain voltage is applied to the control gate to determine whether a large amount of current flows. The read voltage can be arbitrarily determined based on the balance between speed and reliability. For example, a power supply voltage is applied to the gate and a low voltage is applied to the drain to prevent electrons from being injected into the floating gate due to a high voltage. In the illustrated layout, the same potential as the drain is applied to the source of the cell sharing the drain in order to eliminate the current flowing in the direction other than the reading side. When there are no electrons in the floating gate, many electrons move between the source and drain (channel), and current flows. On the other hand, when electrons are present in the floating gate, the number of electrons flowing through the channel is reduced.

  Next, the memory FET can be formed of either NMOS or PMOS. Hereinafter, the case of forming the memory FET as an example will be described with reference to FIGS. 4 to 6 for the application of the control gate (word line) voltage. The description will be given with reference. 4 to 6 are cross-sectional views in the word line direction and the bit line direction, which are cut at the same locations as in FIG. Only the layout shown in FIG. 4A is the same as that shown in FIG. 1, but the layouts and cut portions in FIGS. 5 and 6 are also the same. FIGS. 4B and 4C are diagrams illustrating a first method in which the control gate portion is formed in the N well of the P substrate. When a positive voltage is applied as the control gate voltage, a positive voltage is applied to the entire N well (and the P + region), and when a negative voltage is applied, a negative voltage is applied to the p source / drain.

  5A and 5B are diagrams illustrating a second method for forming a p-type layer immediately below the gate insulating film in addition to the first method. When a positive voltage is applied as the control gate voltage, a positive voltage is applied to the entire N well, and when a negative voltage is applied, a negative voltage is applied to the p-type layer. The resistance of the word line is lower than that in the first method.

  4 and 5, the p + layer is for applying a negative voltage to the control gate. In FIG. 4B, the P + region is cut and formed like a source / drain region, but when erasing, a channel is formed under the floating gate and connected to each other. On the other hand, a continuous P + region is formed in FIG. In a typical NOR type operating condition, it is necessary to apply a negative voltage to the control gate at the time of erasing, but the potential of the N well cannot be lower than that of the P substrate. An area needs to be defined.

  6A and 6B are diagrams illustrating a third method using SOI (Silicon On Insulator). Each node is formed on an oxide film as an insulating film. The control gate portion can be easily insulated from other nodes, and the impurity type of the control gate portion can be arbitrarily set. A gate voltage is applied to the substrate of the control gate part insulated by the oxide film.

  7A, 7B, and 8 are diagrams for explaining a second example of the floating gate type nonvolatile memory arrangement configuration embodying the present invention. 7A and 7B are cross-sectional views in the word line direction and the bit line direction corresponding to FIGS. 2B and 2C, respectively. FIG. 8 is a cross-sectional view in the word line direction corresponding to FIG. The second example illustrated in FIGS. 7A and 7B and FIG. 8 differs from the first example described above only in the configuration of the floating gate and the gate insulating film.

  In the floating gate type memory cells shown in FIGS. 7A, 7B, and 8, the gate insulating film (tunnel insulating film) of the memory FET is written and erased by hot carriers or FN current. The gate insulating film of the control gate portion is composed of two layers of a gate insulating film A (an insulating film made of the same material as the tunnel insulating film) and a gate insulating film B (High-k insulating film). In the configuration shown in the figure, the tunnel insulating film, which is indispensable for realizing the non-volatile memory, and the high-k insulating film already possessed by the logic process are combined to suppress the leakage current while maintaining the capacity (high capacity)・ Low leakage). Thereby, stable writing and erasing and long-term storage of electric charge are possible. The exemplary two-layer structure can realize a non-volatile memory with a minimum process change from a normal logic CMOS process (using a high-k insulating film).

  The floating gate is configured by integrally connecting the gate electrode a, the gate electrode b, and the gate electrode c. On the control gate portion, a gate electrode b made of metal or polysilicon is formed on the gate insulating film B (high-k insulating film). A gate electrode a is formed on the memory FET. Further, the gate electrode c (polysilicon) is used to connect the memory FET and the control gate. When the gate electrode b is a metal, the impurity type of the gate electrode c (polysilicon) does not matter. Here, depositing a thin metal gate directly on a high-k gate insulating film and depositing a thick polysilicon on the thin metal gate makes it possible to use an arbitrary work function of the metal gate and ease the processing of the polysilicon. It is taken into consideration.

  FIG. 9 is an equivalent circuit diagram of the floating gate type nonvolatile memory layout shown in FIG. However, the layout shown in FIG. 1 is illustrated by an arrangement rotated 90 degrees. As shown, a virtual ground type memory cell array configuration is realized. The upper and lower memory cell rows in the figure sharing the same word line use different bit lines. The word line is efficiently shared between the upper and lower cells.

  The present invention can reduce the number of contacts per cell by adopting a virtual ground type cell array (1/2 for the drain and 1/2 for the source, one total). If the configuration is not a virtual ground type, one contact for each drain and source, or even if only the source contact can be shared with other cells, a total of 1.5 to 2 contacts per cell is required. Considering the space for separating it from other nodes, the area is greatly increased.

  Furthermore, the word line by the active layer is adopted, but the layout is devised (adjacent cells are shifted by half the pitch so that the protrusions of the floating gates protrude from each other area) Since the cells share the word lines, the area of the word lines per cell is reduced. The area required (to form a word line) is the product of half the minimum active layer width and the contact pitch (minimum pitch when floating gates and contacts are alternately arranged). When the active layer word line is not used, a large area is required to contact the active layer in addition to the metal wiring of the word line. In addition, even if a word line by an active layer is used, if there is no device to divide the word line face-to-face like in this layout, each cell requires an active layer and an area for separating it from the facing cell is also required. The area will increase.

Although several embodiments have been described in detail in the present disclosure by way of example only, many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the present invention. Examples are possible.

Claims (7)

In a floating gate type nonvolatile memory arrangement in which one floating gate type nonvolatile memory device is set as one cell, and a plurality of cells are arranged in a matrix in the word line direction and bit line direction.
The one floating gate type nonvolatile memory device includes a memory FET sharing a floating gate and two transistors composed of a control gate portion arranged on a semiconductor substrate, and the control gate portion is connected to the floating gate. Including a control gate facing through the gate insulating film,
The bit line extends in the length direction above the floating gate, and the word line functioning as the control gate extends in a direction orthogonal to the bit line,
Cells that share the same word line and are adjacent in the word line direction are arranged opposite to each other and shifted in the bit line direction, and the control gates of the adjacent cells are arranged in a straight line in the word line direction. A floating gate type non-volatile memory arrangement configuration in which floating gates of cells adjacent to each other in the word line direction are alternately arranged laterally in the word line direction. 2. The floating gate nonvolatile memory arrangement according to claim 1, wherein two cell rows sharing the same word line use different bit lines. 2. The floating gate according to claim 1, wherein the word line is formed by a buried word line separated from a semiconductor substrate, and has no contact from metal inside the memory arrangement, and is supplied with a potential outside the memory arrangement. Type non-volatile memory arrangement configuration. 4. The floating gate type nonvolatile memory arrangement according to claim 3, wherein the control gate is formed in a well having a conductivity type opposite to that of the semiconductor substrate. 5. The floating gate nonvolatile memory arrangement according to claim 4, wherein a layer having a conductivity type opposite to that of the well is formed immediately below the gate insulating film. 4. The floating gate nonvolatile memory according to claim 3, wherein a control gate is formed on an insulating film so as to insulate the control gate from other nodes, and a gate voltage is applied to the control gate insulated by the insulating film. Arrangement configuration. The floating gate nonvolatile memory arrangement according to claim 1, wherein the plurality of cells implement a virtual ground type memory arrangement.

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