TW201023218A - Multi-layer ceramic capacitor - Google Patents

Multi-layer ceramic capacitor Download PDF

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TW201023218A
TW201023218A TW97147731A TW97147731A TW201023218A TW 201023218 A TW201023218 A TW 201023218A TW 97147731 A TW97147731 A TW 97147731A TW 97147731 A TW97147731 A TW 97147731A TW 201023218 A TW201023218 A TW 201023218A
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Taiwan
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metal layer
compact
layer
tight
ceramic capacitor
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TW97147731A
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Chinese (zh)
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TWI389152B (en
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Ying-Chieh Lee
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Univ Nat Pingtung Sci & Tech
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Abstract

Disclosed is a multi-layer ceramic capacitor, primarily comprising a ceramic sinter and a plurality of external electrodes. The ceramic sinter is a repeating stack consists of dielectric layers and compact metal layers in turn. Therein, the compact metal layers contain nickel (Ni) and trace titanium dioxide (TiO2). The external electrodes are disposed at two ends of the ceramic sinter to electrically connect the compact metal layers. Accordingly, the MLCC has an improved internal electrical quality and offer a stable capacitance. In a preferable embodiment, the content of titanium dioxide ranges between from 0.25 wt% to 5% to present outstanding reduction in shrinkage. Furthermore, the compact metal layers connecting to the external electrodes and formed between the dielectric layers can be applied to other passive components.

Description

201023218 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種被動元件’特別係有關於一種積層 陶瓷電容器。 【先前技術】 近年來,為了得到更佳的電氣特性,通常在電子產品或 印刷電路板上會配置積層陶瓷電容器(MLCC,Multi-Layer 參 Ceramic Capacitor),並藉由積層陶瓷電容器具有提供等效串 聯電阻與等效串連電感之特性,以保持電流波動在一可允許 之範圍内。因此,積層陶瓷電容器已成為電子電路設計上不 可或缺之元件。 積層陶瓷電容器包含陶瓷燒結體以及形成於陶瓷燒結體 兩端之外部電極。陶竟燒結體係由介電層與金屬層交互堆叠 組合而成。通常在堆疊成形之後,以12〇〇它至14〇〇。〇的溫 度進行尚溫燒結,以形成陶瓷燒結體。通帝積層陶瓷電容器 • 内的金屬層係先以鎳膏印上再經過高燒步驟而形成。由於鎳 膏在高溫燒結過程中會產生收縮之現象,而使燒結後金屬層 形成有多個孔洞甚至.於斷裂(如附件一所示的多孔狀金屬 層),致使無法構成為完整的平行導電板,電容值不易控制, 導致電性品質會變差,故產品的劣品率過高,内部電性品質 低落。更嚴重地,燒結後金屬層之部分會斷裂成電絕緣的孤 島,而無法與外部電極連接,導致有電性失效的問題。 為解決此一問題,目前的業界作法是在鎳膏内混入相當 高比例(20 Wt%或更高)的介電材料,例如鈦酸鋇,以燒結 201023218201023218 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a passive component, particularly relating to a multilayer ceramic capacitor. [Prior Art] In recent years, in order to obtain better electrical characteristics, a multilayer ceramic capacitor (MLCC, Multi-Layer Sensing Ceramic Capacitor) is usually disposed on an electronic product or a printed circuit board, and an equivalent is provided by a laminated ceramic capacitor. The characteristics of the series resistor and the equivalent series inductance to keep the current fluctuation within an allowable range. Therefore, laminated ceramic capacitors have become an indispensable component in the design of electronic circuits. The multilayer ceramic capacitor includes a ceramic sintered body and external electrodes formed at both ends of the ceramic sintered body. The ceramic sintering system is a combination of a dielectric layer and a metal layer. Usually after stack forming, it is 12 至 to 14 〇〇. The temperature of the crucible is sintered at room temperature to form a ceramic sintered body. Tongdi Multilayer Ceramic Capacitors • The inner metal layer is formed by first printing with nickel paste and then subjected to a high-burning step. Due to the shrinkage of the nickel paste during the high-temperature sintering process, the sintered metal layer is formed with a plurality of holes or even fractures (such as the porous metal layer shown in Annex I), so that it cannot be formed as a complete parallel conductive. Board, the capacitance value is not easy to control, resulting in poor electrical quality, so the product's inferior rate is too high, and the internal electrical quality is low. More seriously, a portion of the metal layer after sintering breaks into an isolated island of electrical insulation and cannot be connected to an external electrode, resulting in a problem of electrical failure. In order to solve this problem, the current industry practice is to mix a relatively high proportion (20 Wt% or higher) of dielectric material, such as barium titanate, into the nickel paste to sinter 201023218

後金屬層作為内部電極,其用意在使金屬層與介電層在 同時燒結時收縮率趨向為一致,使兩者在製程中匹配性 良好,但仍無法符合連績性電極之要求。經分析,當介電 材料混入於金屬層的比例低於20 wt°/。甚至為微量添加時, 並無法有效而明顯地降低金屬層之收縮率;又,當介電材料 混入的比例過高時(>2〇 wt%),金屬層的導電性效能會變 差。此外,介電材料混入的比例提高對於連續性電極層的孔 隙縮小有其極限,仍無法完全避免孔隙的形成,此為習知積 層陶瓷電容器無法解決的問題。 【發明内容】 本發明之主要 •一H瓦电谷 器,具有緊緻金屬層作為内部電極,能提升内部電性品 質以及提供更穩定的電容值^在適當的微量添加下,便 能使緊緻金屬層内不形成過大的孔洞,以提供具有良好連 續性之電極並且不影響其導電性能。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明之一種積層陶瓷電容器 包含一陶竟燒結體、一第-外部電極以及-第二外部電 極。該陶究燒結體係依序由一第一介電層、― : 金屬層、一第二介電層與一第二緊 的重 所組合,其中該第一緊緻金屬層與該堆叠 包含鎳與微量的二氧化& 〇 金屬層係 …結體之-第電極係形成於該 層。該第二外部電極係 策緻金屬 保形成於該陶瓷燒結體 6 201023218 • 端,以電性連接該第二緊緻金屬層。在不同實施例中, 上述至少一介電層、該些緊緻金屬層以及該些外部電極 更可運用於其它被動元件。 本發明的目的及解決其技術問題還可採用以下技術 措施進一步實現。 在前述的積層陶瓷電容器中,該第一緊敏金屬層與 該第二緊緻金屬層之二氧化鈦含量係可介於0.25 wt〇/0 至 5 wt% 〇 © ^ 在前述的積層陶瓷電容器中,該第一緊緻金屬層與該 第二緊敏金屬層之二氧化鈦含量係可等於或大於i wt〇/〇。 在前述的積層陶瓷電容器中,該第一緊緻金屬層與 該第二緊緻金屬層的單位面積覆蓋率係可介於85。/〇至 100% ° 在前述的積層陶瓷電容器中,當該第一緊緻金屬層 與該笫二緊緻金屬層之二氧化鈦含量等於或大於3 • wt% ’該第—緊緻金屬廣與該第二緊緻金屬層係可為無 孔隙之金屬層。 在前述的積層陶瓷電容器中,該第一緊緻金屬層與 該第二緊緻金屬層之一長度係可不大於該第一介電層 與該第二介電層之一長度。 在前述的積層陶瓷電容器中,該第一緊緻金屬層與 該第二緊緻金屬層係可分別係顯露於該陶瓷燒結體之 第一端與第二端。 在前述的積層陶瓷電容器中,該第一介電層與該第 201023218 二介電層之材質係可包含鈦酸鋇。 在前述的積層陶瓷電容器中’該陶瓷燒結體係可為 矩形塊體。 在前述的積層陶瓷電容器中,可另包含一表面電錄 層,係形成於該第一外部電極與該第二外部電極之外表 面。 在前述的積層陶瓷電容器中’該第一緊緻金屬層與 該第二緊敏金屬層係可由混合有二氧化欽粉末的錄奮 燒結形成。 在前述的積層陶瓷電容器中,該第一緊緻金屬層與 該第二緊緻金屬層的二氧化鈦係可具有奈米等級或次 微米等級的顆粒尺寸。 在前述的積層陶瓷電容器中,所添加的二氧化鈦的結 晶係可為銳鈦碟型(anatase)或金紅石型(rutile) » 由以上技術方案可以看出,本發明之積層陶資^電容 ❹ 器,有以下優點與功效: 一、 藉由含有微量二氧化鈦的第一緊緻金屬層與第二緊 敏金屬層,能在金屬層與介電層同時高溫燒結之過 程中,防止第一緊緻金屬層與第二緊緻金屬層產生 孔洞甚至斷裂成孤島的現象,故緊緻金屬層能作為 連續性良好之内部電極,可提升積層陶瓷電容器或 被動元件之電性品質。 二、 利用第一緊緻金屬層與第二緊緻金屬層之二氧化鈦 含量等於或大於3 wt%,能使第一緊緻金屬層與第 201023218 二緊敏金屬層的單位 面積覆蓋率係為The rear metal layer acts as an internal electrode, which is intended to make the shrinkage ratio of the metal layer and the dielectric layer uniform at the same time, so that the two have good matching in the process, but still cannot meet the requirements of the continuous electrode. After analysis, the proportion of the dielectric material mixed into the metal layer is less than 20 wt ° /. Even when it is added in a small amount, the shrinkage rate of the metal layer cannot be effectively and significantly reduced. Moreover, when the proportion of the dielectric material mixed is too high (> 2 〇 wt%), the conductivity of the metal layer is deteriorated. In addition, the increase in the proportion of the dielectric material mixed has a limit to the reduction of the pores of the continuous electrode layer, and the formation of pores cannot be completely avoided. This is a problem that cannot be solved by conventional laminated ceramic capacitors. SUMMARY OF THE INVENTION The present invention mainly comprises a compact metal layer as an internal electrode, which can improve internal electrical quality and provide a more stable capacitance value. No excessive pores are formed in the metal layer to provide an electrode with good continuity and does not affect its electrical conductivity. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A multilayer ceramic capacitor according to the present invention comprises a ceramic sintered body, a first external electrode and a second external electrode. The ceramic sintering system is sequentially combined by a first dielectric layer, a: metal layer, a second dielectric layer and a second tight weight, wherein the first tight metal layer and the stack comprise nickel and A trace amount of the dioxide & ruthenium metal layer is formed in the layer. The second external electrode is formed on the ceramic sintered body 6 201023218 • to electrically connect the second tight metal layer. In various embodiments, the at least one dielectric layer, the regions of the compact metal, and the external electrodes are more applicable to other passive components. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the foregoing multilayer ceramic capacitor, the titanium dioxide content of the first tight metal layer and the second tight metal layer may be between 0.25 wt〇/0 and 5 wt% 〇© ^ in the foregoing multilayer ceramic capacitor, The titanium dioxide content of the first tight metal layer and the second tight metal layer may be equal to or greater than i wt〇/〇. In the foregoing multilayer ceramic capacitor, the unit area coverage of the first and second compact metal layers may be 85. /〇 to 100% ° In the foregoing multilayer ceramic capacitor, when the content of the titanium dioxide of the first tight metal layer and the second compact metal layer is equal to or greater than 3 • wt% 'the first-tight metal is wide The second tight metal layer can be a non-porous metal layer. In the foregoing multilayer ceramic capacitor, one of the first tight metal layer and the second tight metal layer may be no longer than one of the first dielectric layer and the second dielectric layer. In the above multilayer ceramic capacitor, the first tight metal layer and the second tight metal layer may be exposed to the first end and the second end of the ceramic sintered body, respectively. In the above multilayer ceramic capacitor, the material of the first dielectric layer and the second dielectric layer of the 201023218 may include barium titanate. In the foregoing multilayer ceramic capacitor, the ceramic sintering system may be a rectangular block. In the above multilayer ceramic capacitor, a surface galvanic layer may be further formed on the surface of the first external electrode and the second external electrode. In the foregoing multilayer ceramic capacitor, the first tight metal layer and the second tight metal layer may be formed by a recording of sintering with a dioxide powder. In the foregoing multilayer ceramic capacitor, the first compact metal layer and the second compact metal layer of the titanium dioxide system may have a particle size of a nanometer or submicron scale. In the foregoing multilayer ceramic capacitor, the crystal system of the added titanium dioxide may be an anatase or rutile type. As can be seen from the above technical solution, the laminated ceramic material of the present invention is a capacitor. The following advantages and effects are as follows: 1. By using the first compact metal layer and the second tight-sensitive metal layer containing a trace amount of titanium dioxide, the first compact metal can be prevented during the simultaneous high-temperature sintering of the metal layer and the dielectric layer. The layer and the second tight metal layer cause holes or even break into islands, so the compact metal layer can serve as an internal electrode with good continuity, which can improve the electrical quality of the laminated ceramic capacitor or passive component. 2. Using the first compact metal layer and the second compact metal layer to have a titanium dioxide content of 3 wt% or more, the unit area coverage of the first compact metal layer and the 201023218 second tight metal layer can be

生產高品質的積層陶竞電容器 【實施方式】 1 0 0 %,達到金 以將電容值控制在一 的電容值,以高良率Production of high-quality laminated Taobao capacitors [Embodiment] 100%, reaching gold to control the capacitance value in a capacitor value, with high yield

、圃不詳細說明本發明之實施例,然 各圖不均為簡化之示意圖,僅以示意方 t基·本架構或實施方法,故僅顯示與本 且所顯示之元件並非以實際實施之數 目、形狀、尺寸比例繪製,某些尺寸比例與其他相關尺 寸比例已經被修飾放大或是簡化,以提供更清楚的描 述,實際實施之數目、形狀及尺寸比例為一種選置性之 設計’詳細之元件佈局可能更為複雜。 依據本發明之第一具體實施例,一種積層陶瓷電容 器舉例說明於第1圖之立體示意囷與第2圖之截面示意 Φ 圖。該積層陶瓷電容器100主要包含一陶瓷燒結體 110、一第一外部電極120以及一第二外部電極130。 該陶瓷燒結體110係依序由一第一介電層111、一第一 緊緻金屬層112、一第二介電層113與一第二緊緻金屬 層114的重覆堆疊所組合,其中該第一緊緻金屬層112 與該第二緊緻金屬層114係包含鎳(Ni)與微量的二氧化 鈦(Ti〇2) 〇 在本實施例中,該陶瓷燒結體110係可為矩形塊 體。舉例而言,在一預設尺寸中,該陶瓷燒結體11 〇係 9 201023218 . 可為一長度約為2.〇〇 mm、寬度約為125 mm以及高度 約為〇.85 mm之矩形塊體。該陶瓷燒結體110係具有一 第端115與—第二端116,該第一端115與該第二端 U 6係為該陶瓷燒結體11 0沿一長度的對應切割端面。 明參閱第2圖所示,該第一介電層U1之長度與該 第二介電層U3之長度係為相等。該第一介電層111與 該第一介電層113之材質係可包含鈦酸鋇(BaTi03)、鍅 ❹酸鈣(CaZr〇3)、锆鈦酸鋇鈣(BaCaTiZr03)、鈦酸鎂 (MgTi〇3)或其它具有高介電係數的材料。在本實施例 中該第介與該第二介電$113之材質係包 含鈦酸鋇。 更具體地,該链 移祕人 項第一緊緻金屬層112與該第二緊緻金 屬層114之一氧化鈥含量係可介於0.25 wt%至5 wt0/〇, 以使該第一緊敏金屬㊆112與該第)緊緻金屬層114符 合「緊緻」之要龙,从 戈木’故該積層陶瓷電容器10〇具有提升 •内部電性品質以及有效控制電容值於一限定範圍内之 功效。其中,繁锄人卜 策敏金屬層之「緊緻」係表示一金屬層的 單位面積覆蓋率不低於80%,即單位面積内收縮率在20%以 下,不會有因收縮產生斷路的孤島並且緊敵金屬層内的 孔/同可大巾《縮小’甚者可到達消除之功效。因此,該第 緊緻金屬層112與該第二緊緻金屬層114可符合積層 陶瓷電容器對於内部電極連績性之要求。 具體地’該第—緊敏金屬層112與該第二緊緻金屬 層114係可由混合有二氧化鈦粉末的鎳膏燒結形成。較 10 201023218 佳地,添加於該第一緊緻金屬層112與該第二緊緻金屬 層114的二氧化鈦係可具有奈米等級或次微米等級的 顆粒尺寸,能使一氧化鈦具有與鎳膏有更大的接觸面 積。在本發明中,奈米等級係界定為小於〇」微米(um) 之尺寸,1微米等於1 000奈米。而次微米等級係 界定為介於0.1至0.5微米(um)之尺寸。在本實施例 中,所選用的二氧化鈦係為約為01微米的顆粒尺寸。 藝因此,二氧化鈦的微量添加能發揮使同時燒結金屬 層為緊緻的作用。二氧化鈦的結晶可有三種形態,為金 紅石型型,rutile)、銳鈦礦型(A型,anatase)和板鈦 礦型(brookit) ’其中經試驗以銳鈦礦型與金紅石型能達 成金屬層較佳的緊緻效果,其中又以銳鈦礦型為最佳。 請參閱第2圖所示’在本實施例中,該第一緊敏金 屬層112與該第二緊緻金屬層1M之一長度係可不大於 該第一介電層111與該第二介電層113之一長度。請參 0 閱第2圖所示,該第一緊緻金屬層112之一側邊與該第 二緊敏金屬層Π4之一側邊係可分別係顯露於該陶曼 燒結體110之該第一端115與該第二端i 16,以供分別 連接該第一外部電極120與該第二外部電極13〇。 請參閲第2圖所示,該第一外部電極12〇係形成於 該陶瓷燒結體110之該第一端115,以電性連接該第一 緊緻金屬層112。該第二外部電極130係形成於該陶篆 燒結體110之該第二端116,以電性連接該第二緊敏金 屬層114 ^該第一外部電極120與該第二外部電極13〇 201023218 . 係可為開口朝向中心的u形截面。該第一外部電極i2〇 與該第二外部電極130之形成方式係可選自於金屬粉 末喷敷、塗佈與沾印之其中之一。該第一外部電極12〇 與該第二外部電極iso之材質係可為銀或銅。請參閱第 1及2圖所示,該積層陶瓷電容器1〇〇可另包含一表面 電鍍層mo,係形成於該第一外部電極12〇與該第二外 部電極13〇之外表面,以預防該第一外部電極12〇與該 ❿第二外部電極130之外表面受到氧化,並能利用錫膏或 焊料烊接至一印刷電路板、晶片封裝構造或模組(圖中 未綠出p 第3及4圖係分別為内含0.25 ”%至5糾%二氧化 鈦之緊緻金屬層在高溫燒結後收縮率變化之曲線圖表 以及電阻值變化之曲線圖表,附件二至附件八係為在高 溫燒結之後添加0.25 Wt%至5 wt%二氧化鈦之緊敏金屬層 冑豸照片顯微圖。在相關的具體試驗中,冑溫燒結的溫度 、約為1220 C,而實體照片顯微圖係為實體的兩千倍放大。 請參閲第3圖所示,内含〇25心二氧化欽之緊緻 屬層在高溫燒結之後之收縮率係由未含時的35%快 _降至約* 12%。請參閱帛4圖所示,内含〇 25评⑼ 〇氧化欽之緊敏金屬;|之電阻值係接近但大於 緻m約為4Ε-04Ω -cm ’與單純的鎳膏燒結成的不緊 示屬層在電阻值上未有明顯的增加。請參閱附件二所 件—緊緻金屬層的單位面積覆蓋率係可約為85%。比較附 與附件一·,可知本發明的緊緻金屬層與傳統由鎳膏燒 12 201023218 結成的不緊緻金屬層’在二氧化鈦的微量添加(僅有 0.2 5 wt°/〇)便能使金屬層產生突出且明顯的緊緻作用。 請再參閱第3及4圖所示,内含0.50 wt%二氧化鈦 之緊緻金屬層在高溫燒結之後之收縮率可進一步下降 至約為8%,而電阻值係接近但大於UE-OAQ-cm’約 為3 E-04 Ω -cm 〇請參閱附件三所示,緊緻金屬層的單位 面積覆蓋率係可約為90%,故添加0.50 wt%二氧化鈦可使 金屬層的結構更為緊緻,金屬層内的孔洞有縮小的現 ❹ · 象0 請再參閱第3及4圖所示,含有0.75 wt %二氧化欽 之緊緻金屬層在高溫燒結之後之收縮率係下降至約為 7% ’而電阻值係接近但大於L0E-04 Ω -cm,約為2E-04 Ω —cm。請參閱附件四所示,緊緻金屬層的單位面積覆蓋率 係可約為95%。故添加〇.75 wt%二氧化鈦可使金屬層的 結構更為緊緻,金屬層内的孔洞數量有減少的現象。 ® 請再參閱第3及4圖所示,内含i.〇〇wt%二氧化鈦 之緊敏金屬層在高溫燒結之後之收縮率係下降至約為 0/〇 ’而電阻值係介於κ〇ε 〇4ω cm至1 〇Ε 〇5Ω _cm之 中間,約為όΕ·〇5 Ω -cm。故該第一緊緻金屬層與該第二 緊緻金屬層之二氧化鈦含量等於或大於1 wt%,符合零收縮 率的要求。請參閱附件五所示,緊緻金屬層的單位面積覆 '、可約為98 /〇。因此,添加j wt%二氧化鈦的金屬層 其孔洞幾近消除。 ”再參閱第3及4圖所示,内含2 wt%二氧化鈦之 13 201023218 緊緻金屬層在高溫燒結之後之收縮率係保持約為〇0/〇, 而電阻值係保持在1.0E-04Q-cm至1.0E-05D-cm之 間,約為9E-05 Ω -cm。請參閱附件六所示,緊緻金屬層 的單位面積覆蓋率係可約為99%。添加2 wt%二氧化鈦的 金屬層在幾近消除的唯一孔洞處更有進一步尺寸縮小 的現象。 請再參閱第3及4圓所示,内含3 wt%二氧化鈦之 ❹ 緊敏金屬層在高溫燒結之後之收縮率係保持約為〇0/〇, 而電阻值係保持在1.0E-04Q-cm至i.〇E-〇5Q-cm之 間’約為8E-05 Ω -cm。請參閱附件七所示,緊緻金屬層 的單位面積覆蓋率係可約為100%。因此,當二氧化鈦的添 加量到達3 wt%,金屬層的結構為全面緊緻,達到金屬層 内孔洞完全消除之功效。 請再參閱第3及4圖所示,内含5 wt%二氧化欽之 緊緻金屬層在高溫燒結之後之收縮率係保持約為〇%, ❹而電阻值係保持在1.0E-04 Ω -cm至1 ·0Ε_05 Ω _cni之 間,約為9E-05Q-cd^請參閱附件八所示,緊緻金屬層 的單位面積覆蓋.率係可約為1 〇〇%,金屬層内孔洞完全消 除。 故由第4圖可知,當二氧化鈦含量由〇25 wt%增加至 該第一緊敏金屬層112與該第二緊緻金屬層114 的電阻值不會有明顯的增加,電阻值不會與二氧化鈦含 量產生等比關係’故二氧化鈦含量在—預設的合理範圍内 的增加不會影響導電效能。 14 201023218 • 由附件二至附件八可知,當二氧化鈦含量係介於0.25 wt%至5 wt%,該第一緊緻金屬層112與該第二緊緻金屬 層114的單位面積覆蓋率係可介於8 5%至100% »該第 一緊緻金屬層112與該第二緊緻金屬層114能發揮良好 的平行導電板的功能並與該第一介電層111及該第二 介電層113的接合良好,進而提高内部電性品質。較佳 地,當該第一緊緻金屬層il2與該第二緊緻金屬層114 之二氧化鈦含量等於或大於3 wt%,該第一緊緻金屬層 ❹ 112與該第二緊緻金屬層114係可為無孔隙之金屬層, 能確保在高溫燒結後不會產生孔洞,並使該第一緊緻金 屬層112與該第二緊緻金屬層114的單位面積覆蓋率係 為 100%。 因此,藉由添加有二氧化鈦之該第一緊緻金屬層112 與該第二緊敏金屬層114,能在高溫燒結之過程中,避 免產生孔洞與斷裂成孤島的現象,並且該第一緊緻金屬 φ 層112、該第二緊緻金屬層114與該第一介電層111、 該第二介電層113之間接合面積佳且平坦無收縮,故能 提升該積層陶瓷電容器100之内部電性品質以及控制 該積層陶瓷電容器100之該第一緊緻金屬層U2與該第 二緊緻金屬層114之電阻值在一限定範圍内。 緊緻金屬層的技術概念可進一步運用於其它被動元 件。依據本發明之第二具體實施例,一種被動元件舉例 說明於第5圖之截面示意圖。該被動元件200主要包含 至少一介電層111、複數個緊緻金屬層112與114以及 15 201023218 . 複數個外部電極120肖"ο。其中與第一實施例相同的 主要元件將以相同符號襟示,並具有相同或類似的作用 與功效,在此不再予以贅逃。在本實施例中,該被動元 件係為一晶片型電阻。 請參閱第5圖所示’該些緊敏金屬㉟112與ιΐ4係 與該介電層lu堆養組成為—陶曼燒結體㈣,其中該 些緊緻金屬層112與114係摻雜有微量二氧化鈦。在本 實施例中,該必緊級全屉a φ 一茱緻蛍屬層112與114係形成於該介電 層1Π之局部上下表面,复 Γ衣w其中該些緊緻金屬層112與U4 之一端係分別對齊於該介雷 ;「電層111之第一端115與第二 端116。該些外部雷極 0與130係形成於該陶瓷燒結 體110之第一端115與第- *〜端116’並與該些緊緻金屬 層112與114分別電性連垃 Β ^ , 接’即該外部電極120連接該 些緊敏金屬層112 ;該外部雷 丨電極130連接該些緊緻金屬 層114。在本實施例中,丨: ^ J T該些外部電極120與130係可 _ 僅形成於該陶瓷燒結體110之切刦也丨;^ 零 I切割側面。換言之,該些 外部電極1 2 0與1 3 0之高麼总-Γ & # 兴 &咼度係可約等於該些緊緻金屬層 112與114與該介電層lu之厘廢祕人 ± 芝厚度總合。請再參閱第5 圖所示,該被動元件200可另包含一表面電鍍層14〇, 係形成於該些外部電極12〇與130之外表面。該表面電 鍍層140更形成於該些緊敏金屬層112與114之外表 面。藉由含有微量一氧化鈦的緊敏金屬層112與114, 防止緊緻金屬層11 2與114產生孔洞或斷裂的現象,以 提升内部電性品質。 16The embodiments of the present invention are not described in detail, and the drawings are not intended to be a simplified schematic diagram, and only the schematic diagrams of the present invention or the implementation method are used, and only the components shown and described herein are not actually implemented. , shape, size ratio drawing, some size ratios and other related size ratios have been modified or simplified to provide a clearer description, the actual implementation of the number, shape and size ratio is an optional design 'detailed Component layout can be more complicated. In accordance with a first embodiment of the present invention, a multilayer ceramic capacitor is illustrated in the perspective view of Figure 1 and the cross-sectional view of Figure 2 of the second embodiment. The multilayer ceramic capacitor 100 mainly includes a ceramic sintered body 110, a first external electrode 120, and a second external electrode 130. The ceramic sintered body 110 is sequentially combined by a first dielectric layer 111, a first tight metal layer 112, a second dielectric layer 113 and a second compact metal layer 114, wherein The first tight metal layer 112 and the second tight metal layer 114 comprise nickel (Ni) and a trace amount of titanium dioxide (Ti〇2). In the embodiment, the ceramic sintered body 110 can be a rectangular block. . For example, in a predetermined size, the ceramic sintered body 11 can be 9 201023218. It can be a rectangular block having a length of about 2. 〇〇 mm, a width of about 125 mm, and a height of about 〇.85 mm. . The ceramic sintered body 110 has a first end 115 and a second end 116, and the first end 115 and the second end U 6 are corresponding cutting end faces of the ceramic sintered body 110 along a length. Referring to Figure 2, the length of the first dielectric layer U1 is equal to the length of the second dielectric layer U3. The material of the first dielectric layer 111 and the first dielectric layer 113 may include barium titanate (BaTi03), calcium silicate (CaZr〇3), barium zirconate titanate (BaCaTiZr03), magnesium titanate ( MgTi〇3) or other materials with a high dielectric constant. In this embodiment, the material of the second dielectric and the second dielectric $113 comprises barium titanate. More specifically, the chain migrating person first etched metal layer 112 and the second tempered metal layer 114 may have a cerium oxide content of 0.25 wt% to 5 wt0 / 〇 to make the first tight The sensitive metal seven 112 and the first compact metal layer 114 conform to the "tightening" of the dragon. From the Gomu's, the laminated ceramic capacitor 10 has improved internal electrical quality and effective control of the capacitance value within a limited range. efficacy. Among them, the "compactness" of the metal layer of the prosperous person indicates that the coverage per unit area of a metal layer is not less than 80%, that is, the shrinkage rate per unit area is less than 20%, and there is no island that is broken due to shrinkage and Tight to the hole in the metal layer / the same can be a large towel "shrinking" can achieve the effect of elimination. Therefore, the first tight metal layer 112 and the second tight metal layer 114 can meet the requirements of the laminated ceramic capacitor for internal electrode continuity. Specifically, the first-tight metal layer 112 and the second tight metal layer 114 may be formed by sintering a nickel paste mixed with titanium oxide powder. Preferably, the titanium dioxide system added to the first compact metal layer 112 and the second compact metal layer 114 may have a nanometer or submicron particle size, which enables the titanium oxide to have a nickel paste. Have a larger contact area. In the present invention, the nanoscale is defined as a size smaller than 〇"micron (um), and 1 micrometer is equal to 1,000 nanometers. The sub-micron rating is defined as a size between 0.1 and 0.5 microns (um). In this embodiment, the titanium dioxide selected is a particle size of about 01 microns. Therefore, the trace addition of titanium dioxide can act to make the sintered metal layer compact at the same time. The crystal of titanium dioxide can be in three forms, rutile type, rutile, anatase (type), and brookit type (brookit), which can be achieved by anatase and rutile. The metal layer has a better compacting effect, and an anatase type is preferred. Referring to FIG. 2, in the embodiment, the length of the first tight metal layer 112 and the second tight metal layer 1M may be no greater than the first dielectric layer 111 and the second dielectric. One of the lengths of layer 113. Referring to FIG. 2, one side of the first tight metal layer 112 and one side of the second tight metal layer Π4 may be exposed to the Tauman sintered body 110, respectively. One end 115 and the second end i16 are connected to the first external electrode 120 and the second external electrode 13A, respectively. Referring to FIG. 2, the first external electrode 12 is formed on the first end 115 of the ceramic sintered body 110 to electrically connect the first tight metal layer 112. The second external electrode 130 is formed on the second end 116 of the ceramic sintered body 110 to electrically connect the second tight-sensitive metal layer 114. The first external electrode 120 and the second external electrode 13〇201023218 The system may be a u-shaped cross section with the opening facing the center. The first external electrode i2 〇 and the second external electrode 130 are formed in a manner selected from one of metal powder spraying, coating, and smearing. The material of the first outer electrode 12 〇 and the second outer electrode iso may be silver or copper. Referring to FIGS. 1 and 2, the multilayer ceramic capacitor 1 may further include a surface plating layer mo formed on the outer surface of the first external electrode 12 and the second external electrode 13 to prevent The first external electrode 12 and the outer surface of the second external electrode 130 are oxidized, and can be soldered to a printed circuit board, a chip package structure or a module by solder paste or solder (not green in the figure) The 3 and 4 graphs are respectively a graph of the shrinkage of the compact metal layer containing 0.25"% to 5% of titanium dioxide after sintering at high temperature and a graph of the change in resistance value. Annexes 2 to 8 are sintered at high temperature. A photomicrograph of the TiO of 0.25 Wt% to 5 wt% of titanium dioxide is then added. In the specific test, the temperature of the sinter sintering is about 1220 C, while the photomicrograph of the solid photo is solid. Two thousand times magnification. Please refer to Figure 3, the shrinkage rate of the compact layer containing 〇25 core dioxide after high temperature sintering is fast from 35% of the uncontained time to about *12% Please refer to Figure 4, which contains 〇25 reviews (9) 〇 钦 钦The resistance value of the tightly sensitive metal; | is close to but greater than the value of m is about 4 Ε -04 Ω - cm 'There is no significant increase in the resistance value of the non-compact sinter layer formed by the simple nickel paste. Please refer to Annex II The coverage per unit area of the compact metal layer can be about 85%. Compare with Annex I, it can be seen that the compact metal layer of the present invention and the conventional non-compact metal layer formed by the nickel paste 12 201023218 The micro-addition of titanium dioxide (only 0.2 5 wt ° / 〇) can make the metal layer produce outstanding and obvious compaction. Please refer to the compact metal layer containing 0.50 wt% titanium dioxide as shown in Figures 3 and 4. The shrinkage rate after high temperature sintering can be further reduced to about 8%, while the resistance value is close to but greater than UE-OAQ-cm' is about 3 E-04 Ω -cm. Please refer to Annex III for a firm metal layer. The coverage per unit area is about 90%, so adding 0.50 wt% of titanium dioxide can make the structure of the metal layer more compact, and the holes in the metal layer are reduced. See Figure 3 and Figure 4. As shown, the compact metal layer containing 0.75 wt% dioxane is sintered after high temperature sintering. The shrinkage rate drops to approximately 7%' and the resistance value is close to but greater than L0E-04 Ω-cm, which is approximately 2E-04 Ω-cm. Please refer to Annex IV for the coverage of the metal layer per unit area. It can be about 95%. Therefore, adding 75.75 wt% of titanium dioxide can make the structure of the metal layer more compact, and the number of holes in the metal layer is reduced. ® Please refer to Figures 3 and 4, including i. 收缩wt% titanium dioxide tight-sensitive metal layer shrinkage after high-temperature sintering is reduced to about 0 / 〇 ' and the resistance value is between κ 〇 ε 〇 4ω cm to 1 〇Ε 〇 5 Ω _cm, About όΕ·〇5 Ω -cm. Therefore, the content of the titanium dioxide of the first compact metal layer and the second compact metal layer is equal to or greater than 1 wt%, which meets the requirement of zero shrinkage. Please refer to Annex 5, the unit area of the tight metal layer is ', can be about 98 / 〇. Therefore, the metal layer of j wt% titanium dioxide is added and its pores are almost eliminated. Referring to Figures 3 and 4, the shrinkage of the 2010 20101818 compact metal layer after sintering at a high temperature is maintained at about 〇0/〇, while the resistance value is maintained at 1.0E-04Q. Between -cm and 1.0E-05D-cm, approximately 9E-05 Ω -cm. Please refer to Annex 6. The coverage per unit area of the tight metal layer is about 99%. Add 2 wt% of titanium dioxide. The metal layer is further reduced in size at the only hole that is almost eliminated. Please refer to the 3rd and 4th rounds, and the shrinkage rate of the tight-sensitive metal layer containing 3 wt% of titanium dioxide after high-temperature sintering is maintained. It is about 〇0/〇, and the resistance value is maintained between 1.0E-04Q-cm and i.〇E-〇5Q-cm' is about 8E-05 Ω-cm. Please refer to Appendix VII for the tightening. The coverage per unit area of the metal layer can be about 100%. Therefore, when the amount of titanium dioxide added reaches 3 wt%, the structure of the metal layer is fully compacted, and the effect of completely eliminating the pores in the metal layer is achieved. As shown in Fig. 4, the shrinkage ratio of the compact metal layer containing 5 wt% of dioxins after sintering at a high temperature is maintained at about 〇%, ❹ The resistance value is maintained between 1.0E-04 Ω -cm and 1 ·0Ε_05 Ω _cni, which is about 9E-05Q-cd^. Please refer to Appendix VIII for the coverage of the metal layer of the compact metal layer. When it is 1%, the pores in the metal layer are completely eliminated. Therefore, as shown in Fig. 4, when the titanium dioxide content is increased from 〇25 wt% to the resistance values of the first tight metal layer 112 and the second tight metal layer 114, There will be no significant increase, and the resistance value will not be related to the titanium dioxide content. Therefore, the increase in the titanium dioxide content within a predetermined reasonable range will not affect the conductivity. 14 201023218 • As can be seen from Annexes II to VIII, The titanium dioxide content is between 0.25 wt% and 5 wt%, and the unit area coverage of the first tight metal layer 112 and the second tight metal layer 114 may be between 85% and 100% » the first tight The metallization layer 112 and the second adhesion metal layer 114 can function as a good parallel conductive plate and have good bonding with the first dielectric layer 111 and the second dielectric layer 113, thereby improving internal electrical quality. Preferably, when the first tight metal layer il2 and the second compact metal The titanium dioxide content of 114 is equal to or greater than 3 wt%, and the first tight metal layer 112 and the second tight metal layer 114 may be a non-porous metal layer, which ensures that no holes are formed after sintering at a high temperature, and The unit area coverage of the first tight metal layer 112 and the second tight metal layer 114 is 100%. Therefore, the first tight metal layer 112 and the second tightness are added by adding titanium dioxide. The metal layer 114 can avoid the phenomenon of holes and broken islands during high-temperature sintering, and the first compact metal φ layer 112, the second tight metal layer 114 and the first dielectric layer 111, The bonding area between the second dielectric layer 113 is good and flat without shrinkage, so that the internal electrical quality of the multilayer ceramic capacitor 100 can be improved and the first tight metal layer U2 and the second of the multilayer ceramic capacitor 100 can be controlled. The resistance value of the compact metal layer 114 is within a limited range. The technical concept of the compact metal layer can be further applied to other passive components. In accordance with a second embodiment of the present invention, a passive component is illustrated in cross-section in Figure 5. The passive component 200 mainly includes at least one dielectric layer 111, a plurality of compact metal layers 112 and 114, and 15 201023218. The plurality of external electrodes 120 are sloppy. The same main elements as those in the first embodiment will be denoted by the same reference numerals and have the same or similar functions and effects, and will not be escaped here. In this embodiment, the passive component is a wafer type resistor. Referring to FIG. 5, the compacting metal 35512 and the ιΐ4 series and the dielectric layer lu are stacked to form a Tauman sintered body (4), wherein the compact metal layers 112 and 114 are doped with a trace amount of titanium dioxide. . In this embodiment, the intimate level of the full tray a φ and the bismuth layer 112 and 114 are formed on a part of the upper and lower surfaces of the dielectric layer 1 , the retanning coating w and the pressing metal layers 112 and U4 One end is respectively aligned with the meson; the first end 115 and the second end 116 of the electric layer 111. The external thunder poles 0 and 130 are formed at the first end 115 of the ceramic sintered body 110 and the -* The end 116' is electrically connected to the tight metal layers 112 and 114, respectively, and the external electrode 120 is connected to the tight metal layers 112; the external thunder electrode 130 is connected to the compacts The metal layer 114. In the present embodiment, 丨: ^ JT the external electrodes 120 and 130 can be formed only on the ceramic sintered body 110; ^ zero I cut side. In other words, the external electrodes The height of 1 2 0 and 1 30 is total - Γ &# 兴 & 咼 degree system can be approximately equal to the thickness of the tight metal layers 112 and 114 and the dielectric layer lu Referring to FIG. 5 again, the passive component 200 may further include a surface plating layer 14 formed on the outer surfaces of the external electrodes 12 and 130. The surface plating layer 140 is further formed on the outer surfaces of the tight-sensitive metal layers 112 and 114. The tight metal layers 112 and 114 containing trace amounts of titanium oxide prevent holes or breakage of the compact metal layers 11 2 and 114. Phenomenon to improve internal electrical quality. 16

V 201023218 - 以上所述,僅是本發明的較佳實施例而已,並非對 本發月作任何形式上的限制,本發明技術方案範圍當依 所附申叫專利冑圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 :化的等效實施例,但凡是未脫離本發明技術方案的内 奋依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾,均仍屬於本發明技術方案的 範圍内。 ❹ 【圖式簡單說明】 第圖依據本發明之第一具體實施例的一種積層陶瓷電容 器之立體示意圓。 圖依據本發明之第一具體實施例的積層陶竞電容器之 截面示意圖。 第圖依據本發明之第一具體實施例的積層冑究電容器 中,内含不同含量之二氧化鈦之緊緻金屬層在高燒 參 時收縮率變化之曲線圖表。 圖依據本發明之第一具體實施例的積層陶宽電容器 中内含不同含量之二氧化鈦之緊敏金屬層之電阻 變化之曲線圏表。 第圖·依據本發明之第〕具體實施例的一種被動元件之截 面示意圏。 件 顯示^知的積層陶瓷電容器在高溫燒結之後未添加 一氧化欽之金屬層之實體照片顯微圖。 牛依據本發明之第一具體實施例的積層陶竟電容器, 17 201023218 在高溫燒結之後添加0.25 wt%二氧化鈦之緊緻金 屬層之實體照片顯微圖。 附件三:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加0.5 wt%二氧化鈦之緊緻金屬 層之實體照片顯微圖。 附件四:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加0.75 wt%二氧化鈦之緊敏金 屬層之實體照片顯微圖。 附件五:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加1 wt%二氧化鈦之緊緻金屬層 之實體照片顯微圖。 附件六:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加2 wt%二氧化鈦之緊緻金屬層 之實體照片顯微圖。 附件七:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加3 wt%二氧化鈦之緊緻金屬層 之實體照片顯微圖。 附件八:依據本發明之第一具體實施例的積層陶瓷電容器, 在高溫燒結之後添加5 wt%二氧化鈦之緊敏金屬層 之實體照片顯微圖。 Λ 【主要元件符號說明】 100積層陶瓷電容器 110陶瓷燒結體 111第一介電層 112第一緊緻金屬層 18 201023218 113第二介電層 115第一端 120第一外部電極 200被動元件 111介電層 115第一端 120外部電極 114第二緊緻金屬 116第二端 130第二外部電極 112緊緻金屬層 116第二端 130外部電極 140表面電鍍層 114緊緻金屬層 140表面電鍵V 201023218 - The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. The scope of the technical solution of the present invention is subject to the scope of the attached patent. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments of the above-disclosed technical contents, but the technical embodiments according to the present invention are not deviated from the technical essence of the present invention. Any simple modifications, equivalent changes and modifications made by the invention are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a multilayer ceramic capacitor according to a first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a schematic cross-sectional view showing a laminated ceramic capacitor according to a first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a graph showing the change in shrinkage of a compact metal layer containing different amounts of titanium dioxide in a high-fired ginseng according to a multilayered capacitor of the first embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 5 is a graph showing the change in resistance of a tightly-sensitive metal layer containing different amounts of titanium oxide in a laminated ceramic wide capacitor according to a first embodiment of the present invention. Fig. 1 is a cross-sectional view showing a passive element according to a fourth embodiment of the present invention. The physical photomicrograph of the metal layer of the oxide was not added after the high temperature sintering. Cattle According to the first embodiment of the present invention, a laminated ceramic capacitor, 17 201023218, a solid photomicrograph of a compact metal layer of 0.25 wt% titanium dioxide after high temperature sintering. Annex III: A photomicrograph of a solid layer of a compact metal layer of 0.5 wt% titanium dioxide added after high temperature sintering in accordance with a first embodiment of the present invention. Annex IV: A photomicrograph of a solid layer of a compacted metal layer of 0.75 wt% titanium dioxide added after high temperature sintering in accordance with a first embodiment of the present invention. Annex 5: A physical photomicrograph of a layered ceramic capacitor according to a first embodiment of the present invention, after a high temperature sintering, a Tight Metal layer of 1 wt% titanium dioxide is added. Annex VI: A solid photomicrograph of a layered ceramic capacitor in accordance with a first embodiment of the present invention, followed by a 2 wt% titanium dioxide compact metal layer after high temperature sintering. Annex VII: A physical photomicrograph of a layered ceramic capacitor according to a first embodiment of the present invention, after a high temperature sintering, a compact metal layer of 3 wt% titanium dioxide is added. Annex 8: A physical photomicrograph of a multilayer ceramic capacitor according to a first embodiment of the present invention, which is added with a 5 wt% titanium dioxide tight-sensitive metal layer after high-temperature sintering. Λ [Main component symbol description] 100-layer ceramic capacitor 110 ceramic sintered body 111 first dielectric layer 112 first tight metal layer 18 201023218 113 second dielectric layer 115 first end 120 first external electrode 200 passive component 111 Electrical layer 115 first end 120 external electrode 114 second tight metal 116 second end 130 second outer electrode 112 tight metal layer 116 second end 130 outer electrode 140 surface plating layer 114 compact metal layer 140 surface key

1919

Claims (1)

201023218 十、申請專利範面: 1、 一種積層陶瓷電容器,包含: 陶瓷燒結體,係依序由一第一介電層、一第一緊緻金 屬層—第二介電層與一第二緊緻金屬層的重覆堆疊所 組《,其中該第一緊緻金屬層與該第二緊緻金屬層係包 含鎳與微量的二氧化鈦; 一第一外部電極,係形成於該陶瓷燒結體之一第一端, 參以電性連接該第一緊緻金屬層;以及 一第二外部電極,係形成於該陶瓷燒結體之一第二端, 以電性連接該第二緊緻金屬層。 2、 如申請專利範圍第1項所述之積層陶瓷電容器,其中該 第一緊緻金屬層與該第二緊緻金屬層之二氧化鈦含量係 介於 0.25 wt°/〇至 5 wt0/〇。 3、 如申請專利範圍第1項所述之積層陶瓷電容器,其中該 第一緊緻金屬層與該第二緊緻金屬層之二氧化鈦含量係 ❹ 等於或大於1 wt%。 4、 如申請專利範圍第1項所述之積層陶瓷電容器,其中該 第—緊緻金屬層與該第二緊緻金屬層的單位面積覆蓋率 係介於85°/。至1〇〇〇/0。 5、 如申請專利範圍第1項所述之積層陶瓷電容器’其中當 該第一緊緻金屬層與該第二緊緻金屬層之二氧化鈦含量 等於或大於3 wt%,以使該第一緊緻金屬層與該第二緊 緻金屬層係為無孔隙之金屬層。 6、 如申請專利範圍第1項所述之積層陶瓷電容器’其中該 20 201023218 第一緊緻金屬層與該第二緊緻金屬層 蛛油人 均嘈之一長度係不大於 該第一介電層與該第二介電層之一長度。 7 如申請專利範圍第Μ所述之積層陶究電容器其中該 第-緊緻金屬層與該第二緊緻金屬層係分別係顯露於該 陶瓷燒結體之第一端與第二端。 9、 如申請專利範圍第1項所述之積層陶瓷電容器, 第一介電層與該第二介電層之材質係包含鈦酸鋇 其中該201023218 X. Patent application: 1. A multilayer ceramic capacitor comprising: a ceramic sintered body, which is sequentially composed of a first dielectric layer, a first compact metal layer, a second dielectric layer and a second tight layer. a method of repeatedly stacking metal layers, wherein the first and second compact metal layers comprise nickel and a trace amount of titanium dioxide; and a first external electrode is formed in the ceramic sintered body The first end is electrically connected to the first tight metal layer; and a second external electrode is formed on the second end of the ceramic sintered body to electrically connect the second tight metal layer. 2. The multilayer ceramic capacitor of claim 1, wherein the first compact metal layer and the second compact metal layer have a titanium dioxide content of from 0.25 wt/〇 to 5 wt0/〇. 3. The multilayer ceramic capacitor of claim 1, wherein the first compact metal layer and the second compact metal layer have a titanium dioxide content of 等于 equal to or greater than 1 wt%. 4. The multilayer ceramic capacitor of claim 1, wherein the first-tight metal layer and the second tight metal layer have a coverage per unit area of 85°/. To 1〇〇〇/0. 5. The multilayer ceramic capacitor according to claim 1, wherein when the content of the titanium dioxide of the first and second compact metal layers is equal to or greater than 3 wt%, the first compact The metal layer and the second tight metal layer are metal layers without voids. 6. The multilayer ceramic capacitor according to claim 1, wherein the length of the 20 201023218 first compact metal layer and the second compact metal layer spider oil is not greater than the first dielectric layer One length with the second dielectric layer. 7. The laminated ceramic capacitor of claim </RTI> wherein the first and second compact metal layers are exposed to the first and second ends of the ceramic sintered body, respectively. 9. The multilayer ceramic capacitor according to claim 1, wherein the material of the first dielectric layer and the second dielectric layer comprises barium titanate. 如申請專利範圍第i項所述之積層陶究電容器其中該 陶瓷燒結體係為矩形塊體。 10、如申請專利範圍第i項所述之積層陶究電容器,另包 含一表面電鍍層,係形成於該第一外部電極與該第二外 部電極之外表面。 11、 如申請專利範圍第1項所述之積層陶瓷電容器,其中 該第一緊緻金屬層與該第二緊緻金屬層係由混合有二氧 化敛粉末的鎳膏燒結形成。The laminated ceramic capacitor of the invention of claim i wherein the ceramic sintering system is a rectangular block. 10. The laminated ceramic capacitor of claim i, further comprising a surface plating layer formed on the outer surface of the first outer electrode and the second outer electrode. 11. The multilayer ceramic capacitor of claim 1, wherein the first tight metal layer and the second tight metal layer are formed by sintering a nickel paste mixed with a oxidized powder. 12、 如申請專利範圍第1項所述之積層陶瓷電容器,其中 該第—緊緻金屬層與該第二緊緻金屬層的二氧化鈦係具 有奈米等級或次微米等級的顆粒尺寸。 13、 如申請專利範圍第1項所述之積層陶瓷電容器,其中 所添加的二氧化鈦的結晶係為銳鈦礦型(anatase)或金 紅石型(rutile)。 14、 一種被動元件,包含·· 至少一介電層; 複數個緊緻金屬層,係與該介電層堆疊組成為一陶瓷燒 21 201023218 結體’其中該些緊緻金屬層係摻雜有微量二氧化鈦;以 及 複數個外部電極,係形成於該陶瓷燒結體之兩端,旅與 該些緊緻金屬層電性連接。 15、 如申請專利範圍第14項所述之被動元件,其中該些緊 敏金屬層之二氧化鈦含量係介於0 25评1%至5 wt〇/〇。 16、 如申請專利範圍第14項所述之被動元件,其中該些緊 φ 敏金屬層之二氧化鈦含量係等於或大於lwt%。 17、 如申請專利範圍第14項所述之被動元件,其中該些緊 緻金屬層的單位面積覆蓋率係介於85%至1〇〇〇/0。 18、 如申請專利範圍第14項所述之被動元件,其中當該些 緊緻金屬層之二氧化鈦含量等於或大於3 wt°/。,以使該 些緊緻金屬層係為無孔隙之金屬層。 19、 如申請專利範圍第14項所述之被動元件,另包含一表 面電鍍層’係形成於該些外部電極之外表面。 ❹ 20、如申請專利範圍第14項所述之被動元件,其中該第一 緊緻金屬層與該第二緊緻金屬層係由混合有二氧化鈥粉 末的鎳膏燒結形成。 21、 如申請專利範圍第14項所述之被動元件,其中該些緊 緻金屬層的二氧化鈦係具有奈米等級或次微米等級的顆 粒尺寸。 22、 如申請專利範圍第14項所述之被動元件,其中所添加 的二氧化欽的結晶係為銳欽破型(anatase)或金紅石型 (rutile) 0 2212. The multilayer ceramic capacitor of claim 1, wherein the first compact metal layer and the second compact metal layer have a nanometer or submicron particle size. 13. The multilayer ceramic capacitor according to claim 1, wherein the crystal of the added titanium dioxide is an anatase or rutile. 14. A passive component comprising: at least one dielectric layer; a plurality of compact metal layers stacked with the dielectric layer to form a ceramic burn 21 201023218 a junction body in which the compact metal layer is doped A trace amount of titanium dioxide; and a plurality of external electrodes are formed at both ends of the ceramic sintered body, and the bridging is electrically connected to the tight metal layers. 15. The passive component of claim 14, wherein the titanium dioxide content of the tight metal layer is between 0 and 25 wt%/〇. 16. The passive component of claim 14, wherein the titanium dioxide content of the tight metal sensitive layer is equal to or greater than 1 wt%. 17. The passive component of claim 14, wherein the tight metal layer has a coverage per unit area of 85% to 1 〇〇〇/0. 18. The passive component of claim 14, wherein the content of the titanium dioxide of the compact metal layer is equal to or greater than 3 wt. So that the tight metal layers are made of a non-porous metal layer. 19. The passive component of claim 14, further comprising a surface plating layer formed on the outer surface of the external electrodes. The passive component of claim 14, wherein the first compact metal layer and the second compact metal layer are formed by sintering a nickel paste mixed with cerium oxide powder. 21. The passive component of claim 14, wherein the titanium dioxide of the compact metal layer has a nanometer or submicron particle size. 22. The passive component according to claim 14, wherein the crystal of the added dioxins is anatase or rutile 0 22
TW97147731A 2008-12-08 2008-12-08 Multi-layer ceramic capacitor TWI389152B (en)

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