TW201021176A - Package structure and manufacture thereof - Google Patents

Package structure and manufacture thereof Download PDF

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Publication number
TW201021176A
TW201021176A TW97145431A TW97145431A TW201021176A TW 201021176 A TW201021176 A TW 201021176A TW 97145431 A TW97145431 A TW 97145431A TW 97145431 A TW97145431 A TW 97145431A TW 201021176 A TW201021176 A TW 201021176A
Authority
TW
Taiwan
Prior art keywords
layer
package
contact
package structure
electrical
Prior art date
Application number
TW97145431A
Other languages
Chinese (zh)
Inventor
Shih-Ping Hsu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW97145431A priority Critical patent/TW201021176A/en
Publication of TW201021176A publication Critical patent/TW201021176A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

The invention provides a package structure and the manufacture thereof, comprising a packaging layer having an electrical contact surface; a circuit layer composed of a plurality of metal layers and embedded in the packaging layer while partly being exposed from the electrical connecting surface, the circuit layer having a plurality of electrical connecting pads formed thereon and comprising a first contact layer, a conductive layer and a second contact layer; and at least a semiconductor chip enclosed in the packaging layer and having an active surface whereon a plurality of electrode pads are formed to electrically connect with each electrical connecting pads via a corresponding solder bump, thereby overcoming the constraints of prior techniques by reducing the overall structure thickness.

Description

201021176 九、發明說明： 【發明所屬之技術領域】 ’尤指一種有 本發明係有關w一種封裝結構及其製法 關超薄厚度之封裝結構及其製法。^ 【先前技術】 隨者+導體封裝技術的演進，除了傳騎料⑻a g)半導體封裝技術以外，目前半導體震置 (Sennconductor device)已開發出不同的封裝型態，例如 φ-種將半導體晶片之作用面朝下並藉由金屬凸塊與封裝 基板接合的覆晶封裝（Flip_Chip) ’而使用覆晶封裝技 術之優點在於可降低晶片與基板間的電子訊號傳輸距 離，以降低阻抗，俾能提高電性功能，並可縮小晶片封裝 後的尺寸，以達薄小之目的。 " "月參閱第1A至1D圖’係為習知之封裝結構之製法 意圖。 如第1A圖所示，首先，提供一基板本體1〇，該基板 本體10可為已完成前段線路製程之兩層或多層電路板 (惟其内層線路之型式係為習知，在此不加贅述），該基 板本體10具有相對之第一表面10a及第二表面l〇b 該第一表面l〇a及第二表自1〇b上分別具有第一線路層 12a及第二線路層12b，且該第一線路層12a及第二線路 層12b可藉由設於該基板本體1〇中之導電通孔（圖式中 未表不）以互相電性連接；該第一線路層12a及第二線路 層12b分別具有複數電性接觸墊121a及焊墊121b，且於 111009 5 201021176 該基板本體10與該第一線路層12a及第二線路層12b上 /刀別具有第-防焊層13a及第二防焊層⑽，該第一防焊 .層13a及第二防焊層13b分別具有複數外露各該電性 墊心及焊墊咖之第—防焊層開孔驗 ^ 層開孔130b。 & +-.--- . 如第1B圖所示，提供複數半導體晶片14,各該半導 體晶片14係具有1 a u作用面Ha’於該作用面14a上形 數電極墊141，於各兮带祕姑魅# ir 合这电接觸墊121a上形成焊料凸媸 _ 15 ’該些電極墊141藉由該焊料凸塊15以電性連接各該 電性接觸墊121a，且於久綠主Sx 1Λ 、各該+導體晶片14與該基板本體 10之間形成底膠18。 攸+體 =1C®所示’切割該基板本體胸形成複數封裝 、’、口構1 b ’且各該封步么士播,u 14〇 合/封裝結構lb中具有至少-該半導體晶片 ^1D圖所示’於各該焊墊㈣上形成焊球17。 ❿兮主道牌I"去I知封裝結構係於該基板本體10上結合 該半導體晶片14，使得敕_ # ° 凸塊15、蟬球17、A:::封裝結構之厚度受限於焊料201021176 IX. Description of the invention: [Technical field to which the invention pertains] ‘especially a package structure having a package structure and a method for producing the same, and a method for manufacturing the same. ^ [Prior Art] With the evolution of the +conductor packaging technology, in addition to the semiconductor packaging technology (8) a g semiconductor packaging technology, the current semiconductor device (Sennconductor device) has developed different package types, such as φ-type semiconductor wafer The use of flip chip packaging technology with the face-down and flip-chip bonding of the metal bumps to the package substrate has the advantage of reducing the electronic signal transmission distance between the wafer and the substrate to reduce the impedance. Improve the electrical function, and reduce the size of the package after the chip, in order to achieve a small purpose. ""Monthly Referring to Figures 1A through 1D' is a conventional method of making a package structure. As shown in FIG. 1A, firstly, a substrate body 1 is provided, and the substrate body 10 can be a two-layer or multi-layer circuit board that has completed the front-end circuit process (only the type of the inner layer circuit is conventional, and no further description is provided herein. The substrate body 10 has a first surface 10a and a second surface 10b. The first surface 10a and the second surface have a first circuit layer 12a and a second circuit layer 12b, respectively. The first circuit layer 12a and the second circuit layer 12b are electrically connected to each other by a conductive via hole (not shown in the drawing) provided in the substrate body 1; the first circuit layer 12a and the first circuit layer The two circuit layers 12b respectively have a plurality of electrical contact pads 121a and pads 121b, and the substrate body 10 and the first circuit layer 12a and the second circuit layer 12b have a first solder mask layer 13a on the substrate layer 10 and the second circuit layer 12b. And the second solder resist layer (10), the first solder resist layer 13a and the second solder resist layer 13b respectively have a plurality of exposed electric pads and solder pads - the solder mask opening test layer opening 130b. & +-.---. As shown in Fig. 1B, a plurality of semiconductor wafers 14 are provided, each of which has an au action surface Ha' on the active surface 14a and an electrode pad 141 thereon. A solder bump _ 15 is formed on the electrical contact pad 121a. The electrode pads 141 are electrically connected to the electrical contact pads 121a by the solder bumps 15 and are in the green main Sx. A primer 18 is formed between each of the +conductor wafers 14 and the substrate body 10.攸+body=1C®shows 'cutting the substrate body to form a plurality of packages, ', and a port structure 1 b' and each of the steps of the squid, the u 14 / / package structure lb has at least - the semiconductor wafer ^ A solder ball 17 is formed on each of the pads (4) as shown in Fig. 1D. ❿兮Main board I" I know that the package structure is attached to the substrate body 10 to bond the semiconductor wafer 14, so that the thickness of the 敕_# ° bump 15, 蝉 ball 17, A::: package structure is limited by solder

L 基板本體〗〇及半導體晶片14之轉A 厂子度因此！^改良以得到超薄厚度之封裝結構。 ㈣1匕鑒於上述之問題，如何避免習知技術中之封梦 結構之整體厚度受限於之封裝 雜晶片之厚度，因ΛΓ?凸塊'焊球、基板本雜及丰導 鲁 易改良以得到超薄厚度之封裝姓構 4問通，實已成為目前虽欲解決之課題。 構 【發明内容】 111009 6 201021176 鑒於上述習知技街之缺失’本發明之主要目的係 •一種能達到超薄厚度之封裝結構及其製法。 八 ’構，述目的及其他目的’本發明揭露一種封裝結 ’、匕括.封裝層，係具有一電性接觸面；線路 相構叙嵌㈣㈣裝射絲露於該電 2接觸面’料路層❹於該封裝層巾之—侧並具有複數L substrate body 〇 and semiconductor wafer 14 turn A factory degree! ^ Improved to obtain an ultra-thin thickness package structure. (4) In view of the above problems, how to avoid the thickness of the sealed dream structure in the prior art is limited by the thickness of the packaged wafer, because the bumps, the solder balls, the substrate, and the Fengliang are improved. The ultra-thin thickness of the package name 4 is a question that has been solved. [Description of the Invention] 111009 6 201021176 In view of the above-mentioned lack of the conventional technology street, the main object of the present invention is a package structure capable of achieving an ultra-thin thickness and a method of manufacturing the same. The present invention discloses a package junction, a package layer, which has an electrical contact surface; The road layer is on the side of the encapsulating layer and has a plurality

' 電性連接墊，盆中，兮綠a户A β仿 該線路層係包括第一接觸層、導體層 2二接觸層’ ·以及至少-半導體晶片，係包覆於該封裝 ❹，中’該半導體晶片具有作用面，於該作用面設有複數電 令各該電極墊藉由焊料凸塊對應電性連接至各 性連接墊。 又依上述之封裝結構’該線路層顯露於封裝層之表 的另一側復具有複數電性接觸墊，以供植設焊球:或者 各该電性接觸墊係供作與墊閘陣列結構之電性連接。'Electrical connection pad, in the basin, the green a household A β-like circuit layer includes a first contact layer, a conductor layer 2 two contact layer 'and at least a semiconductor wafer, wrapped in the package, in the ' The semiconductor wafer has an active surface, and a plurality of electrodes are disposed on the active surface, and the electrode pads are electrically connected to the respective connection pads by solder bumps. According to the above package structure, the circuit layer is exposed on the other side of the surface of the package layer, and has a plurality of electrical contact pads for implanting solder balls: or each of the electrical contact pads is used as a pad array structure. Electrical connection.

依上述之結構’該第一接觸層之材料係可為化鎳鈀浸 金、化鎳浸金、銅、鎳、鈀及金所組成之群組之其中一者； 該導體層之材㈣可為銅及騎組成之群組之其巾—者；該 第二接觸層之材料係可為化賴浸金、化錄浸金、銅、錄: 纪及金所組成之群組之其中一者。 依上所述，該些電性接觸墊係可齊平、高於'或低於 該封裝層之電性接觸面。 本發明復包括一種封裝結構之製法，係包括：於一承 載體之至少-表面上形成複數金屬層以構成線路層，盆 中，該線路層具有複數電性連接墊，該線路層係包括第一 111009 7 201021176 接觸層I體層及第二接觸層；於各該電性連接塾上 凸塊曰於該些焊料凸塊上接置複數半導體晶片，且各 f導體sa片上形成複數電極墊，該些電極墊藉由該些焊 料凸塊對應焊接至各該電性連接墊，令各該半導體晶片電 性連接至該線路層；於該承載體、線路層及半導體晶片上 士，裝層以將各該半導體晶片及線路層埋設於該封裝 二’且該封裝層接置該承載體之表面係為電性接觸面； 移除該承載體，以露出該封裝層之電性接觸路 = ;封裝層以形成複數封裝結構，且令各該时結 構中具有至少一該半導體晶片。 又依上述之封裝結構之製法，該線路層顯露於封裝層 之表面的一側復具有複數電性接 括於各該電性接觸塾上形成焊球。权襄法復可包 該承該承載體係可包括承載板及形成於 ❹屬咬Si:封裝結構之製法，該承载板之材料係可為金 ^有機材料，而該中間層之材㈣可為金屬或有機材 又依上述之封裝結構之製法，移除該承載板之 可為化學儀刻、電漿、反應式離子钱刻或雷射方式。'、 依上述之製丨法，移除該令間層之方 刻、電漿、反應式離子钱刻或雷射方式。’、° .，、、匕學蝕 又依上述之製法，該第一接觸層之材料係可 心、化㈣金、鋼ϋ及金所組成之群組之其^ 111009 8 201021176 者；該導體層之村料係可為銅及 ，鎳、鈀及金所組成之群組之其中一者。鎳次金、鋼、 依上述之封裝結構之製法，該電性接卞、 高於、或低於該封裝層之電性接觸面。 背平、 ❹ 本&明之封裝結構，主要係先於該承载體 .層，並使該線路層電性連接至該半導體晶片，再^封梦， 包覆該線路層及半導體晶片，最後移除該承載，裝層 +導體曰曰片钱埋於封裝層中之封裝結構；如此， 結構之厚度則不再受限於焊料凸塊及半導體之 度’以達超薄厚度之封裝結構。 厚 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2F圖，係提供本發明之封裝結構之製 如第2A圖所示，提供一係為金屬或有機材料之承载 板20，於該承載板20上形成係為金屬或有機材料之中間 層21’以形成一承載體2a。 如第2B圖所示，於該承載體2a之中間層21上形成 複數金屬層以構成線路層22，其中，該線路層22係包括 第一接觸層22a、導體層22b及第二接觸層22c，該導體 層22b係為該線路層22的主體，以供傳導電流，而該第 111009 9 201021176 一接觸層22a及第二接觸層22c係保護該導體層22b，並 - 利於與外接電子元件的電性連接；該線路層22具有複數 . 電性連接墊221與電性接觸墊222，且部分電性連接墊 221及電性接觸墊222係位於相對應之兩侧。 所述之第_接觸層22a之材料係為化鎳把-浸金 • (Electroless Nickel/Electroless Pal ladium/Immersion .Gold，ENEPIG )、化錄浸金（Electroless Nickel & ImmersionGold，ENIG)、銅（Cu)、鎳（Ni)、鈀（Pd)及金 ❹（Au)所組成之群組之其中一者；該導體層22b之材料係為 銅（Cu)及鎳（Ni)所組成之群組之其中一者；該第二接觸層 22c 之材料係為化錄把浸金（Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG )、化鎳浸金 (Electroless Nickel & Immersion Gold， ENIG)、銅 (Cu)、錄（Ni)、I巴（Pd)及金（Au)所組成之群組之其中一者。 如第2C圖所示，於各該電性連接墊221上形成焊料 凸塊25 ’並於該些焊料凸塊25上接置複數半導體晶片 ®24’且各該半導體晶片24上形成複數電極墊241，該些 電極塾241藉由該些焊料凸塊25對應電性連接至各該電 性連接墊221，令該些半導體晶片24電性連接至該線路 層22 〇 如第i2D圖所示，於該承載體2a、線路層22及半導 體晶片24上形成封裝層26，以將各該半導體晶片24及 線路層22埋設於該封裝層26中，且該封裝層26接置該 承載體2a之表面係為電性接觸面26a。 10 111009 201021176 如第 2E、2E，及 _ -出哕㈣思μ 移除該承載體2a，以露 ==層26之電性接觸面心及線路層&其中移 ，除〜承餘20之方法係可為化學 ⑽)或雷射方式，而== •或•射=H電裝（piasma)、反應式離子敍刻（RIE) • ί =伴=路層22外露於電性接觸面⑽的金 線心移除該承㈣23時，保護該 參接館Π/該電性接觸塾222係齊平該封1層26之電性 & ’如第2Ε圖所示’·或該電性接觸墊222低於 ^電性接觸面26a，如第2Ε，圖所示；或該電性接觸塾M2 該電性接觸面26a，如第2Ε，’圖所示。後續製程將 以第2Ε圖所示之結構作說明。 如第2F圖所示’切割該封裝層26以形成複數封裝結 2b’且令各該封裝結構2b申具有至少一該半導體晶片 24,該電性接觸塾222係可供作與塾問陣列結構（㈤ 鬌grid array，LGA)之電性連接。 β或如第2F，圖所示，先於各該電性接觸墊222上形成 焊球27，再切割該封裝層26以形成複數封裝結構肋。 本發明復揭露一種封裝結構，係包括：封裝層26, 係具有電性接觸面26a;線路層22,係為複數金屬層所構 成且嵌埋於該封裝層26中並顯露於該電性接觸面26a， 且該線路層22嵌埋於該封裝層26中之一側並具有複數電 f生連接塾221 ’又該線路層22係包括第一接觸層22a、導 111009 11 201021176 體層22b及第二接觸層22c;以及至少一半導體晶片24， - 係包覆於該封裝層26中，該半導體晶片24具有作用面 • 24a ’於該作用面24a上設有複數電極墊241，令各該電 極墊241藉由焊料凸塊25對應電性連接至各該電性連接 墊 221。 • 依上述之封裝結構’該線路層22顯露於封裝層26 . 之表面的一侧復包括複數電性接觸塾222，以供植設焊球 27 ;或者，該些電性接觸墊222係供作與墊閘陣列結構 ❹（Land grid array, LGA)之電性連接。 依上述之結構’該第一接觸層22a之材料係為化鎳鈀浸 金（Electroless Nickel/Electroless Pal ladium/Immersion Gold，ENEPIG )、化鎳浸金（Electroless Nickel & Immersion Gold, ENIG)、銅（Cu)、鎳（Ni)、把（Pd)及金 (Au)所組成之群組之其中一者，該導體層22b之材料係為 銅（Cu)及鎳（Ni)所組成之群組之其中一者，該第二接觸層 22c 之材料係為化鎳把浸金（Electroless Nickel/Electroless ®Falladium/Immersion Gold, ENEPIG )、化鎳浸金 (Electroless Nickel & Immersion Gold, ENIG)、銅 (Cu)、錄（Ni)、|巴（Pd)及金（Au)所組成之群組之其中一者。 依上述之封裝結構，該電性接觸墊222係齊平、高 於？或低於該封裝層26之電性接觸面26a。 本發明之封裝結構，主要係藉由先於承載體上形成線 路層，且該線路層以該焊料凸塊電性連接至該半導體晶片 之電極墊，再以該封裝層覆蓋該線路層及半導體晶片，再 12 111009 201021176 移除該承载板，以將該半導體晶片嵌埋於封裝層中，並使 心線路層之電性接觸墊顯露在封裝層之表面，俾使整體封 裝結構之厚度不再受限於焊料凸塊及半導體晶片之厚 度’以達超薄厚度之封裝結構。 ^上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 =不違背本發明之精神及範訂，對上述實施例進行修 所因此本發明之權利保護範圍，應如後述之申請專 @圍所列。 【圖式簡單説明】 結構及其製法之剖視示 第1Α至1D圖係為習知之封裝 意囷；以及 干意本發明之封裝結構及其製法之剖視 第”’圖係為U圖之另—實：。2£圖之不同實施例; 【主要元件符號說明】 10 基板本體 10a 第一表面 10b 第二表面 12a 第一線路層 12b 第二線路層 121a、222 電性接觸墊 121b 焊墊 13a 第一防焊層 ® 10 111009 13 201021176 13b 第二防焊層 130a 第一防焊層開孔 130b 第二防焊層開孔 14、24 半導體晶片 14a 、 24a 作用面 • 141 > 241 電極墊 -15 ' 25 焊料凸塊 17、27 焊球 ©18 底膠 lb、2b 封裝結構 20 承載板 21 中間層 2a 承載體 22 線路層 22a 第一接觸層 22b 導體層 參22c 第二接觸層 221 電性連接墊 26 封裝層 26a 電性接觸面 14 111009According to the above structure, the material of the first contact layer may be one of a group consisting of nickel-palladium immersion gold, nickel immersion gold, copper, nickel, palladium and gold; the material of the conductor layer (4) may be It is the towel of the group consisting of copper and riding; the material of the second contact layer can be one of the group consisting of immersion gold, chemical immersion gold, copper, recording: Ji and gold. . According to the above, the electrical contact pads can be flush, higher than or lower than the electrical contact surface of the encapsulation layer. The invention further comprises a method for fabricating a package structure, comprising: forming a plurality of metal layers on at least a surface of a carrier to form a circuit layer, wherein the circuit layer has a plurality of electrical connection pads, the circuit layer includes a 111009 7 201021176 contact layer I body layer and a second contact layer; a plurality of semiconductor wafers are mounted on the solder bumps on the respective solder bumps, and a plurality of electrode pads are formed on each of the f conductors sa, The electrode pads are soldered to the respective electrical connection pads by the solder bumps, so that the semiconductor wafers are electrically connected to the circuit layer; the carrier, the circuit layer and the semiconductor wafer are slain, and the layers are stacked Each of the semiconductor wafer and the circuit layer is embedded in the package 2' and the surface of the package layer is connected to the surface of the carrier is an electrical contact surface; the carrier is removed to expose the electrical contact of the package layer; The layers are formed to form a plurality of package structures and have at least one of the semiconductor wafers in each of the structures. According to the method of fabricating the package structure described above, the circuit layer is exposed on a side of the surface of the encapsulation layer and has a plurality of electrical properties connected to each of the electrical contact pads to form a solder ball. The method of claiming that the carrier system can include a carrier plate and a method for forming a package structure of the bismuth Si: the package material can be a gold/organic material, and the material of the intermediate layer (four) can be The metal or organic material is further removed according to the above-mentioned method of packaging structure, and the carrier plate can be removed by chemical etching, plasma, reactive ion etching or laser. ', according to the above method, remove the interfacial layer of the engraving, plasma, reactive ion engraving or laser. ', ° , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The layer of the village material may be one of a group consisting of copper and nickel, palladium and gold. Nickel sub-gold, steel, according to the above-mentioned package structure, the electrical interface is higher than, or lower than the electrical contact surface of the encapsulation layer. The back-up, ❹本 & Ming package structure, mainly precedes the carrier layer, and electrically connects the circuit layer to the semiconductor wafer, and then seals the circuit layer and the semiconductor wafer, and finally moves In addition to the carrier, the package + conductor is buried in the package structure in the package layer; thus, the thickness of the structure is no longer limited by the degree of solder bumps and semiconductors to achieve an ultra-thin thickness package structure. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure. Please refer to FIGS. 2A to 2F for providing the package structure of the present invention. As shown in FIG. 2A, a carrier 20 is provided as a metal or organic material, and the carrier 20 is formed of a metal or organic material. The intermediate layer 21' is formed to form a carrier 2a. As shown in FIG. 2B, a plurality of metal layers are formed on the intermediate layer 21 of the carrier 2a to form a wiring layer 22, wherein the wiring layer 22 includes a first contact layer 22a, a conductor layer 22b, and a second contact layer 22c. The conductor layer 22b is a main body of the circuit layer 22 for conducting current, and the contact layer 22a and the second contact layer 22c protect the conductor layer 22b, and is beneficial to external electronic components. The circuit layer 22 has a plurality of electrical connection pads 221 and electrical contact pads 222, and a portion of the electrical connection pads 221 and the electrical contact pads 222 are located on opposite sides. The material of the first contact layer 22a is Electroless Nickel/Electroless Pal ladium/Immersion (Gold, ENEPIG), Electroless Nickel & Immersion Gold (ENIG), copper (Electroless Nickel/Electroless Gold) One of a group consisting of Cu), nickel (Ni), palladium (Pd), and gold (Au); the material of the conductor layer 22b is a group of copper (Cu) and nickel (Ni) One of the materials of the second contact layer 22c is Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Electroless Nickel & Immersion Gold (ENIG), Copper (Electroless Nickel/Electroless Palladium/Immersion Gold, ENIGIG) One of a group consisting of Cu), Ni (I), Ib (Pd), and Au (Au). As shown in FIG. 2C, solder bumps 25' are formed on each of the electrical connection pads 221, and a plurality of semiconductor wafers 24' are connected to the solder bumps 25, and a plurality of electrode pads are formed on the semiconductor wafers 24. 241, the electrode pads 241 are electrically connected to the electrical connection pads 221 by the solder bumps 25, and the semiconductor wafers 24 are electrically connected to the circuit layer 22, as shown in FIG. An encapsulation layer 26 is formed on the carrier 2a, the wiring layer 22 and the semiconductor wafer 24 to embed each of the semiconductor wafer 24 and the wiring layer 22 in the encapsulation layer 26, and the encapsulation layer 26 is connected to the carrier 2a. The surface is an electrical contact surface 26a. 10 111009 201021176 As in 2E, 2E, and _ - 哕 (4) 思 μ Remove the carrier 2a, to expose == layer 26 electrical contact face and circuit layer & move, except ~ to 20 The method can be chemical (10)) or laser mode, and == • or • shot = H electric (piasma), reactive ion characterization (RIE) • ί = accompanying = road layer 22 exposed to the electrical contact surface (10) When the gold wire core removes the bearing (4) 23, the protection of the entrance hall Π / the electrical contact 塾 222 is flushed with the electrical property of the first layer 26 & 'as shown in Figure 2' or the electrical The contact pad 222 is lower than the electrical contact surface 26a, as shown in FIG. 2, or the electrical contact 塾M2 is electrically connected to the surface 26a as shown in FIG. Subsequent processes will be described in the structure shown in Figure 2. As shown in FIG. 2F, the encapsulation layer 26 is cut to form a plurality of package junctions 2b', and each of the package structures 2b has at least one semiconductor wafer 24, and the electrical contact layer 222 is available for use in an array structure. ((5) 鬌grid array, LGA) electrical connection. As shown in Fig. 2F, a solder ball 27 is formed on each of the electrical contact pads 222, and the encapsulation layer 26 is further cut to form a plurality of package structure ribs. The present invention discloses a package structure comprising: an encapsulation layer 26 having an electrical contact surface 26a; and a circuit layer 22 formed by a plurality of metal layers embedded in the encapsulation layer 26 and exposed to the electrical contact. The surface layer 22a is embedded in one side of the encapsulation layer 26 and has a plurality of electrical connections 221'. The circuit layer 22 includes a first contact layer 22a, a conductor 111009 11 201021176 a body layer 22b and a The two contact layers 22c; and the at least one semiconductor wafer 24 are coated in the encapsulation layer 26, and the semiconductor wafer 24 has an active surface 24a'. The active surface 24a is provided with a plurality of electrode pads 241 for each of the electrodes. The pad 241 is electrically connected to each of the electrical connection pads 221 by solder bumps 25 . • According to the above package structure, the side of the surface of the circuit layer 22 exposed on the package layer 26 includes a plurality of electrical contacts 222 for implanting the solder balls 27; or the electrical contact pads 222 are provided. It is electrically connected to the Land Grid Array (LGA). According to the above structure, the material of the first contact layer 22a is Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), Electroless Nickel & Immersion Gold (ENIG), copper. One of a group consisting of (Cu), nickel (Ni), (Pd), and gold (Au), the material of the conductor layer 22b is a group of copper (Cu) and nickel (Ni) In one of the materials, the second contact layer 22c is made of electroless nickel (Electroless Nickel/Electroless® Falladium/Immersion Gold, ENEPIG), nickel immersion gold (Electroless Nickel & Immersion Gold, ENIG), copper. One of the group consisting of (Cu), recorded (Ni), | Pakistan (Pd), and gold (Au). According to the above package structure, the electrical contact pads 222 are flush and higher than? Or lower than the electrical contact surface 26a of the encapsulation layer 26. The package structure of the present invention is mainly formed by forming a circuit layer on the carrier, and the circuit layer is electrically connected to the electrode pad of the semiconductor chip by the solder bump, and the circuit layer and the semiconductor are covered by the package layer. Wafer, then 12 111009 201021176 remove the carrier plate to embed the semiconductor wafer in the encapsulation layer, and expose the electrical contact pads of the core layer to the surface of the encapsulation layer, so that the thickness of the overall package structure is no longer Limited by the thickness of the solder bumps and the semiconductor wafer 'to achieve an ultra-thin thickness package structure. The above embodiments are intended to exemplify the principles of the invention and its advantages, and are not intended to limit the invention. Any person skilled in the art can make modifications to the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth below. BRIEF DESCRIPTION OF THE DRAWINGS The cross-sectional view of the structure and its method shows that the first to the 1D drawings are conventional packaging intentions; and the cross-sectional view of the package structure and the method for manufacturing the same according to the present invention is U-shaped. Another embodiment of the present invention: [Main component symbol description] 10 substrate body 10a first surface 10b second surface 12a first circuit layer 12b second circuit layer 121a, 222 electrical contact pad 121b pad 13a first solder mask® 10 111009 13 201021176 13b second solder mask 130a first solder mask opening 130b second solder mask opening 14, 24 semiconductor wafer 14a, 24a active surface • 141 > 241 electrode pad -15 ' 25 Solder bumps 17, 27 Solder balls © 18 Primer lb, 2b Package structure 20 Carrier plate 21 Intermediate layer 2a Carrier 22 Circuit layer 22a First contact layer 22b Conductor layer 22c Second contact layer 221 Electrical Connection pad 26 encapsulation layer 26a electrical contact surface 14 111009

Claims (1)

201021176 .十、申請專利範圍： 1· 一種封裝結構，係包括： •封裝層’係具有電性接觸面； :路層係'為複數金屬層所構成且喪埋於該封裝 層中並顯露於該電性拄雜 觸面，且該線路層嵌埋於該封 勺二箆之垃=並具有硬數電性連接墊，又該線路層係 -接觸層 '導體層及第二接觸層；以及 導體體晶片，係包覆於該封裝層中，該半 ^ ^ 用面，且於該作用面上設有複數電極 電性連接墊。冑由㈣凸塊對應電性連接至各該 如申請專利範圍第丨項之封梦姑 顯露於封裝層之表面的一構，其中’該線路層 ^側具有複數電性接觸墊。 如申請專利範圍第2項之封裝結構，其中，該電性接 觸墊係齊平、高於、或低於 &似於该封裝層之電性接觸面。 範圍第2項之封襄結構，復包括焊球，係 植设於各該電性接觸塾上。 如申請專利範圍第2項之封褒結構，其中，該電 觸墊係供作與墊閘陣列結構之電性連接。 如申請專利範圍第1項之封裝結構，盆中 -接觸層之材料係為編巴浸金、化錄浸金、銅、鎳、 鈀及金所組成之群組之其中一者。 如申請專利範圍第1項之封裝結構，其中，該導體層 之材料係為銅及鎳所組成之群組之其中一者。 參 2. 3. 4. ❿ 5. 6. 111009 15 7. 201021176 . 8. 第1項之封裝結構，其中，該第 -接觸層之材料係為化鎳鈀浸 9. 銘及金所組成之群組之其t一者。U銅、鍊、 一種封裝結構之製法，係包括： 構成：路：载：之至少一表面上形成複數金屬層以 二=第r層具有複數電性連接塾，且該線 觸層'導趙層及第二接觸層； ❿ #"電性連接塾上形成焊料凸塊，· 導體晶上接置複數半導體晶片，各該半 凸塊對應電性連接至各：雷=電極墊藉由該些焊料 晶片電性連接該線路層；、接墊’令各該半導體 層 中 面 路層及半導體晶片上形成封農 且該封裝層接置C層埋設於該封裝層 參 载體之表面係為電性接觸 移除該承載體，以露 線路層；以及 田系封裝層之電性接觸面及 切割該封裝層以形 構係具有至少一該半導體广封裝結構，各該封裝結 W·如申請專利範圍第9 1曰。 線路層顯# # # # ，十裝結構之製法，其中，嗲 吩權顯路於封裝層之矣 、Τ忑 接觸墊。 面的—侧復具有複數電性 η.如申請專利範圍第 #之封裝結構之製法，其中， Ϊ11009 201021176 =性接觸塾係齊平、高於低 * 接解面。 这封裝層之電性 ' 12.如申請專利範廚筮ln s *各:電性接觸墊上形:::裝結構之製法，復包括 •如申μ專利範圍第9項之封裝㉔構之制 , 承載體係包括承載板及形成於該法’其’，該 • 14.如申請專利範圍第n通、〜 反上之中間層。 移除該承载板之方，封裝結構之製法，其中， ❹子餘刻或雷射方式。…匕學㈣、電聚、反應式離 15.::申請，圍第13項之封裝結構之製法 私除該中間層之方法係為化學蝕刻、電漿： 子钱刻或雷射方式。 一反應式離 16·如申請專利範圍第9項之封裝結構之製法| :’該第-接觸層之材料係為化鎳鈀浸金 ： 金、銅、錦m所組成之群組之其中 ’"又 魯17·如申請專利範圍第9項之封裝結構之製法，其中，該 導體層之材料係為銅及鎳所组成之群組之发“ 18·如申請專利範圍第9項之封裝結構之製法，其 中’該第二接觸層之材料係為化鎳鈀浸金、化鎳浸 金、銅、鎳、鈀及金所組成之群組之其中一者。，、/ 111009 17201021176 . X. Patent application scope: 1. A package structure, including: • The encapsulation layer has an electrical contact surface; the road layer system is composed of a plurality of metal layers and is buried in the encapsulation layer and exposed The electrically noisy contact surface, and the circuit layer is embedded in the sealing material and has a hard electrical connection pad, and the circuit layer is a contact layer 'conductor layer and a second contact layer; The conductor body wafer is wrapped in the encapsulation layer, and the surface is provided with a plurality of electrode electrical connection pads on the active surface. The (4) bumps are electrically connected to each of the structures of the surface of the encapsulation layer, wherein the circuit layer has a plurality of electrical contact pads. The package structure of claim 2, wherein the electrical contact pad is flush, higher, or lower than an electrical contact surface of the package layer. The sealing structure of the second item of the scope includes a solder ball and is implanted on each of the electrical contact ports. The sealing structure of claim 2, wherein the electrical contact pad is electrically connected to the pad array structure. For example, in the package structure of claim 1, the material of the basin-contact layer is one of a group consisting of immersion gold, chemical immersion gold, copper, nickel, palladium and gold. The package structure of claim 1, wherein the material of the conductor layer is one of a group consisting of copper and nickel. Refer to 2. 3. 4. ❿ 5. 6. 111009 15 7. 201021176 . 8. The package structure of item 1, wherein the material of the first contact layer is composed of nickel and palladium dip 9. Ming and Jin The group of one of them. U copper, chain, a method of manufacturing a package structure, comprising: constituting: road: carrying: forming a plurality of metal layers on at least one surface, and having a plurality of electrical connections, the second layer has a plurality of electrical connections, and the line contact layer a layer and a second contact layer; ❿ #" a solder bump is formed on the electrical connection, and a plurality of semiconductor wafers are connected to the conductor crystal, and each of the bumps is electrically connected to each of: a bump = electrode pad by the The solder pads are electrically connected to the circuit layer; the pads are formed so that the surface layer of each of the semiconductor layers and the semiconductor wafer are formed on the surface of the semiconductor layer, and the surface layer of the package layer is buried on the surface of the package layer carrier. Electrically contacting the carrier to expose the circuit layer; and electrically contacting the electrical contact surface of the field packaging layer and cutting the packaging layer to form at least one of the semiconductor wide package structures, each of the package junctions Patent scope is 91. The circuit layer shows ####, the ten-pack structure method, in which the 吩 command is used to show the 矣 and 接触 contact pads in the encapsulation layer. The surface-side complex has a complex electrical property η. The method of manufacturing the package structure of claim # ,11009 201021176 = the sexual contact system is flush, higher than the low * interface. The electrical properties of the encapsulation layer are as follows: 12. For example, the patented kitchen 筮 s s * each: electrical contact pad shape::: the structure of the structure, including: The carrying system includes a carrier board and is formed in the method of 'the', and the intermediate layer of the nth, nth, and the opposite of the patent application scope. The method of removing the carrier board and the method of manufacturing the package structure, wherein the dice are left or laser. ... dropout (4), electropolymerization, reactive separation 15.:: Application, method of packaging structure around the 13th item The method of privately removing the intermediate layer is chemical etching, plasma: money or laser. A reaction formula 16: The method for manufacturing a package structure according to claim 9 of the patent application scope: : 'The material of the first contact layer is a nickel-palladium immersion gold: among the groups consisting of gold, copper and brocade m "又鲁17· The method of manufacturing a package structure according to claim 9 of the patent scope, wherein the material of the conductor layer is a group of copper and nickel. 18) The package of the ninth application patent scope The method of fabricating the structure, wherein the material of the second contact layer is one of a group consisting of nickel-palladium immersion gold, nickel immersion gold, copper, nickel, palladium and gold., / 111009 17
TW97145431A 2008-11-25 2008-11-25 Package structure and manufacture thereof TW201021176A (en)

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