TW201019335A - High temperature test system - Google Patents

High temperature test system Download PDF

Info

Publication number
TW201019335A
TW201019335A TW97142985A TW97142985A TW201019335A TW 201019335 A TW201019335 A TW 201019335A TW 97142985 A TW97142985 A TW 97142985A TW 97142985 A TW97142985 A TW 97142985A TW 201019335 A TW201019335 A TW 201019335A
Authority
TW
Taiwan
Prior art keywords
high temperature
test system
temperature test
test
signal
Prior art date
Application number
TW97142985A
Other languages
Chinese (zh)
Other versions
TWI389128B (en
Inventor
Chen-Ang Hsiao
Sheng-Shun Yen
Chia-Hsin Tsai
Cai-Ni Lu
Original Assignee
Power Quotient Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Power Quotient Int Co Ltd filed Critical Power Quotient Int Co Ltd
Priority to TW97142985A priority Critical patent/TWI389128B/en
Publication of TW201019335A publication Critical patent/TW201019335A/en
Application granted granted Critical
Publication of TWI389128B publication Critical patent/TWI389128B/en

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

DRAM test has been applied to the current process of DRAM module manufacture. An advanced test program is built on memory test line gradually today named high temperature test. The high temperature test is a good way to screen marginal devices resulting in infant mortality from products to make sure a high reliability and quality. In this patent, we disclose a new burn-in equipment and the corresponding design method, It offers a low cost, easy maintain and simple assembly functions to manufacturer.

Description

201019335 九、發明說明: 【發明所屬之技術領域】 ^本案係一種高溫測試系統,主要是提供待測物一個瀕 臨設計極限的工作環境,在此嚴苛的環境中進行位址的定 址、資料的讀寫及邏輯控制的動作,利用這種方式提早篩 選出品質不良而具有潛在失效的產品,而本發明則提供了 一個結構成本較低,機台維護較容易的高溫測試系統。201019335 IX. Description of the invention: [Technical field to which the invention belongs] ^ This is a high-temperature test system, which mainly provides a working environment where the object to be tested is nearing the design limit, and address and address of the address in this severe environment. The operation of reading and writing and logic control uses this method to early screen out products with poor quality and potential failure, and the present invention provides a high temperature testing system with low structural cost and easy maintenance of the machine.

【先前技術J 現有之高溫測試機均具備有一個參數產生器(Pattern ® =enerator)至於其機板之後(US7,131,040),經由參數產生 器^生所要寫入待測物的資料,隨著機板的增加,參數產 ,器也需增加,這樣的設計帶來了硬體上成本的增加,但 是在實務操作上並不一定能帶給製造商一個足堪信任的測 試環境,其最終的品質還需要再經過一道常溫環境下的參 數測試’以避免之前不必要的高溫誤殺產品的情況發生, 而製造廠商這樣的測試流程安排卻使得之前所投入的硬體 成本變成徒然,論其原因,不外乎是確保製造商在記憶體 晶片上的使用效率。 • 【發明内容】 如上所述,考量到實務上客戶對商業利潤追求的現 實,本,明將多餘的參數產生器移除,以降低物料成本, 而另外,計一組固定線路,該線路可以透過計算機的控制 ,產生,易參數’利用此簡易參數本案仍然可以對記憶體 進行參數的讀寫,並順利進行相關的位址解碼及控制 邏輯is件的正常運作。 【實施方式】 本發明技術的實施方式詳細說明如下,請先參照如圖 201019335 一,圖二所示為本發明之高溫測試系統的功能方塊圖,本 發明之高溫測試系統,例如但不限於為一動態隨機存取記 憶體模組之高溫測試系統,其中2〇〇為一加熱機箱區,其具 有二隔熱層210包覆四週’形成一個可以加熱並保持怪溫的 區域,而熱源的設計則來自於一加熱鼓風器22〇,其内部具 有加熱導管及風扇(皆圖未示)之配置,利用風扇的轉動 帶動熱氣流,而該熱氣流經由該隔熱層21〇内部的熱流導管 經由A處的導流口230注入到機箱2〇〇内部;另一方面,原 本機箱200内部的冷空氣,也因風扇的帶動,而自b處的導 〇 流口230注入到該加熱鼓風器220加熱,加熱後的氣流再經 A處的導流口230注入到該機箱2〇〇内部。如此循環不已, 在該機箱200内部的形成一股熱氣流自a處傳導到已處(請 參照圖一中之箭頭方向),又由於該隔熱層21〇包覆四週, 因此該機箱200内部的溫度將不斷地上升,直到溫度達到所 ,定的溫度後,停止該加熱鼓風器220内的加熱導管的加熱 1亍程,因此只要適當地對該加熱導管作必要的加熱控制, 就可以維持該加熱機箱區2〇〇内部的溫度在一定的範圍。 ,再參照圖一’在本發明之高溫測試系統的設計上, ® ^要是由一計算機之主機板100進行運作,今舉DDR2動態 隨機存取記憶體為例’說明如下,該主機板1〇〇經由程式的 控制’將一DDR2動態隨機存取記憶體模組400的訊號傳遞 至一橋接板110上’該橋接板係負責將訊號重製後並加 大驅動電流再,遞出去,其上具有一組訊號緩衝器 ’圖未示)完成上述工作,在本發明的設計方法中, ^訊,並不具備DDR2資料(Data)的信號,僅具有DDR2的 指令信號(Command)、位址信號(Address)及時脈信號 (Clock),此外還包括一組控制訊號(CTS),這樣設計的目 201019335 的,避免了該主機板100在執行讀取指令時發生錯誤, 長距,的傳輸後,資料經由該橋接板”。傳回時: Γ9)上將失*了正確性而不會被該主機板: 所<可,因此將造成資料讀取錯誤的發生。 換言之,本發明迥異於傳統的設計之一便是 取3體模組4QQ的資料匯流排,但是 維^作業祕的正粒作,在該域板1。。上仍然一 吊連接的記憶體模組負責系統中央處理器(CPU,圖未 Z細4^n常至於測試用的DDR2動態隨機存取記憶體 Ο 插槽上,彻電路佈局將該資料匯流排透過 缺蜂二形成一低電位準位,供測試程式讀取使用,雖 二來的倾並不是紅贿於記舰崎的資料, 斷資料的正確性並不是本發明的設計目的,只要確 賴作魏下,該DDR2_義躲記憶體模 、τ *安^之雜體確冑執行資料寫人及讀取的動作,便滿足 了本案=溫測試設裝置的設計條件,篩選出早期劣化的產 二也就是滿足前文所述的前實務作法,因為記憶 料的正確性,理當在—個正常操作溫度的範圍 為各種測試參數(TeStPattern)來完成,若在高溫惡 下進行驗證,將不符合記㈣的操作規格要求, 的^高的峨結果也將徒紐成製造商_擾與生產成本 播,Ϊ再參照圖一,DDR2訊號經過了該橋接板110的推動 加赦續傳遞到一驅動板120,該驅動板120係固定於該 箱區200的外部約4(rc的空間中固鎖於該隔熱層 明參照圖二’該驅動板120上同樣配置有數組的緩衝區 7 201019335 塊,每一組緩衝區塊依據其扇出(Fan Out)的能力,推動數 支的DDR2動態隨機存取記憶體模組400,以圖二為例,每 一組緩衝區塊負責推動3支的DDR2動態隨機存取記憶體 模組400。而承架板130則置於該加熱機箱區2〇〇的内^部高 溫區域’而各待測DDR2動態隨機存取記憶體模組 400(Device Under Test,DUT)則分別組立於該承架板]3〇 上’ §玄承架板130透過置於該驅動板120上的信號連接器 122與驅動板120互相達成DDR2信號的連接,最後將來自 該主機板100的訊號傳達到各個待測DDR2動態隨機存取 ❿ 記憶體模組400上。經由該加熱機箱區200内部的滑軌設 計,便可以將該承架板130置於滑軌上與該驅動板12〇進行 結合與分離的動作,當高溫測試完畢後,該承架板13〇便可 以自該加熱機箱區200内部取出,直接取得所有的待測 DDR2動態隨機存取記憶體模組4〇〇,進入下一站的常溫讀 寫測試。需注意的是,該加熱機箱區2〇〇内部之溫度約8〇。〇 〜110°C,而該加熱機箱區200外部之溫度約4〇°c。 所以利用上述方式,經由適當的緩衝器電路及電源線 路設計,便可以利用一個驅動板120同時推動數個位於該承 ❿架板130上的DDR2動態隨機存取記憶體模組4〇〇,不僅如 此,如圖二所示,該驅動板12〇同時也將DDR2訊號傳遞至 下一級的驅動板120 ’如此層層堆置’便可以完成一個主機 板100同時測試數百隻DDR2動態隨機存取記憶體模組4〇〇 的功能,大幅降低了傳統多晶片高溫測試系統設計的組裝 與維護成本。 ^請再參照圖三’圖三為記憶體測試電路方塊圖,其中 緩衝^(Buffer)112位於該橋接板11 〇上分別對DDR2訊號 (圖未示)與控制訊號(圖未示)進行訊號緩衝,而控制訊號則 201019335 可透過計算機之平行資鱗(Pn.nt咖 ί料,器及資料準位;路 ,,資料匯流二用: 隐體負料匯流排上的邏輯準位,亦即可 二嫉 =^〇Hf!fDDR2動態隨機存取記憶“組4〇〇Ζ 入FF或〇〇的資料。由此可以觀之 = 參數產生11,械之叫的 e 魯 曰曰,種方式只能產生吓及〇〇兩種資料形態, ’對於不同參數對記__試宜在常溫 ’而本發_設計則已能_記憶體高溫 lit,的。同時本案的設計優點還包括有較佳的設 備ί用度,睛再參照圖三,由圖三可以知道本發明的元件 配置以室溫社’主要的電路祕冑安排至該加熱機箱區 200的外部約4(rc的區域’將該區域辅以散熱的氣流設計 則可確保大部份的電子零件均工作在正常的操作溫度範圍 内,因此提尚了設備的可靠度,進一步減少設備維護的次 數。 本發明另一個嶄新的設計是將該承架板彳30透過置於 該驅動板120上的該信號連接器122與該驅動板120互相達 成DDR2信號的連接’請參照圖二,其中在該承架板13〇上 設置有一組金手指(Golden Finger)132作為訊號傳遞之 用,當該承架板130穿過該隔熱層210後,便與該驅動板120 上的#说連接122相連接’這樣的設計達到了兩個優點, 第一、解決了DDR2訊號線繁多而衍生的連接線不易連接 的問題,第二、將信號連接器122隔離在加熱區域外圍,減 少了熱衝擊,增加了系統插拔使用的次數。 201019335 請再參照圖三,本發明的電源設計係採用獨立的電源 供應器300 ’以提供大批量DDR2動態隨機存取記憶體模多且 400工作所需的電力,同樣經過該計算機主機板1〇〇的控制 訊说’可以對§亥驅動板彳20上的電源線路進行控制,當該承 架板130欲脫離該驅動板120時,系統便對電源作出斷電處 置’而當承架板130再度載入驅動板120時,主動恢復電源 輸出’其目的便是保護測試產品的安全,這些控制流程皆 可以經由軟體程式的設計而達成,如圖四所示即為該驅動 板120上的電源線路設計。 _ 由上述技術說明可知,本發明之高溫測試系統為一個 具有較低成本、組裝簡易以及系統維護方便等的諸多好 處’其率皆與以在既有的尚溫測試系統迴然不同,卻可達 到與傳統高溫測試設備相同的功效’實為一個具有新穎性 及進步性的技術創作。、 因此,本案之系統設計不可不謂為一個測試技術之重 要創作’而本案所揭示者,乃舉DDR2記憶體為一說明範 例,其為較佳實施例之一種,然舉凡局部之變更或修飾而 源於本案之技術思想而為熟習該項技藝之人所易於推知 ® 者,俱不脫本案之專利權範疇。 綜上所陳,本案無論就目的、手段與功效,在在顯示 其迥異於習知之技術特徵,且其首先創作合於實用,亦在 在符合申請專利之要件,懇請貴審查委員明察,並祈早 曰賜予專利,俾嘉惠社會,實感德便。 【圖式簡單說明】 ,一為一示意圖,其繪示本發明一較佳實施例之高溫測試 系統之方塊示意圖。 圖二為一示意圖,其緣示本發明一較佳實施例之高溫測試 201019335 系統之剖面示意圖。 圖三為一示意圖,其繪示本發明之記憶體測試電路之方塊 示意圖。 【主要元件符號說明】 100 :計算機主機板 110 :橋接板 112 :緩衝器 120 :驅動板 121 :電源線 Φ 122:信號連接器 130 :承架板 131 :資料準位電路 132 :金手指 200 :加熱機箱 210 :隔熱層 220 :加熱鼓風器 230 :熱導流口 300 :電源供應器 ® 400 : DDR2動態隨機存取記憶體模組 11[Prior Art J existing high temperature testing machine has a parameter generator (Pattern ® = enerator) after its board (US7,131,040), through the parameter generator to generate the data to be tested, with The increase of the board, the parameter production, and the device also need to be increased. This design brings about an increase in hardware cost, but it does not necessarily give the manufacturer a reliable test environment in practice. The quality needs to go through a parametric test in a normal temperature environment to avoid unnecessary high temperature accidental killing of the product, and the test process arrangement of the manufacturer makes the hardware cost of the previous investment become in vain. It is nothing more than ensuring the manufacturer's efficiency on the memory chip. • [Summary of the Invention] As mentioned above, considering the reality of the customer's pursuit of commercial profit in practice, Ben, the redundant parameter generator is removed to reduce the material cost, and in addition, a fixed line is determined, and the line can be Through the control of the computer, generate, easy parameters 'Using this simple parameter, the case can still read and write the parameters of the memory, and smoothly carry out the relevant address decoding and the normal operation of the control logic is. [Embodiment] Embodiments of the present invention are described in detail below. Please refer to FIG. 201019335 first. FIG. 2 is a functional block diagram of the high temperature test system of the present invention. The high temperature test system of the present invention is, for example but not limited to, A high-temperature test system for a dynamic random access memory module, wherein 2 turns is a heating chassis area, which has two insulating layers 210 covering the periphery to form an area that can heat and maintain strange temperature, and the heat source design Then, it is from a heating air blower 22, which has a heating duct and a fan (not shown), and uses the rotation of the fan to drive the hot air flow, and the hot air flow passes through the heat flow layer inside the heat insulating layer 21 The inside of the chassis 2 is injected through the air inlet 230 at A; on the other hand, the cold air inside the chassis 200 is also driven by the fan, and the airflow port 230 from the b is injected into the heating blast. The device 220 is heated, and the heated air flow is injected into the inside of the casing 2 through the flow guiding port 230 at A. In this way, a hot air flow inside the chassis 200 is conducted from a to the place (refer to the direction of the arrow in FIG. 1), and since the heat insulation layer 21 is covered around, the inside of the chassis 200 is The temperature will continue to rise until the temperature reaches a predetermined temperature, and the heating of the heating conduit in the heating blower 220 is stopped, so that the heating control of the heating conduit can be appropriately controlled. The temperature inside the heating enclosure area 2 is maintained within a certain range. Referring to Figure 1 again, in the design of the high temperature test system of the present invention, if it is operated by a computer motherboard 100, the DDR2 dynamic random access memory is taken as an example, as follows, the motherboard 1〇 Controlling the signal of a DDR2 DRAM module 400 to a bridge board 110 via the control of the program. The bridge board is responsible for re-creating the signal and increasing the drive current, and then handing it out. With a set of signal buffers (not shown) to complete the above work, in the design method of the present invention, the signal does not have the DDR2 data (Data), only the DDR2 command signal (Command), address signal (Address) clock signal (Clock), in addition to a set of control signals (CTS), such a design of 201019335, to avoid the host board 100 in the execution of the read command error, long distance, after transmission, The data is transmitted via the bridge board. When returning: Γ9) The top will lose the correctness without being affected by the motherboard: < can, therefore, will cause a data reading error to occur. In other words, the present invention is different from the traditional One of the designs It is the data bus of the 3Q module 4QQ, but the dimension of the job is the correct grain, in the domain board 1. The memory module still connected to the system is responsible for the system central processor (CPU, Figure Z Fine 4^n is often used in the test DDR2 dynamic random access memory 插槽 slot, the circuit layout of the data bus through the bee 2 to form a low potential level for the test program to read, although the second The dumping is not the red bribe in the information of the record, the correctness of the broken data is not the design purpose of the present invention, as long as it is determined by Wei, the DDR2_ meaning memory model, τ * An ^胄 Execution of data writing and reading actions, it satisfies the design conditions of the case = temperature test device, and screening out the early deterioration of production is to meet the pre-practical practices described above, because the correctness of the memory material, The range of normal operating temperatures is determined by various test parameters (TeStPattern). If the verification is performed under high temperature, it will not meet the operating specifications of (4), and the result will be the manufacturer. Disturbance and production cost broadcast According to FIG. 1, the DDR2 signal is transmitted to the driving board 120 through the pushing and pushing of the bridge board 110, and the driving board 120 is fixed to the outside of the box area 200 by about 4 (the space of the rc is locked in the heat insulation). Referring to FIG. 2', the driver board 120 is also provided with an array of buffers 7 201019335 blocks, each of which drives a plurality of DDR2 dynamic random access memories according to its Fan Out capability. In the module 400, as shown in FIG. 2, each buffer block is responsible for driving three DDR2 DRAM modules 400. The shelf plate 130 is placed in the heating chassis area. The high-temperature area of the DDR2 DDR2 dynamic random access memory module 400 (Device Under Test, DUT) is respectively set up on the shelf plate 3 〇 § 玄 承 承 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 130 The signal connector 122 on the 120 and the driver board 120 mutually connect to the DDR2 signal, and finally transmit the signal from the motherboard 100 to each of the DDR2 dynamic random access memory modules 400 to be tested. Through the sliding rail design inside the heating chassis area 200, the receiving frame 130 can be placed on the sliding rail to combine and separate the driving board 12〇. After the high temperature test is completed, the receiving frame 13〇 It can be taken out from the heating chassis area 200, and all the DDR2 dynamic random access memory modules to be tested are directly obtained, and the normal temperature reading and writing test of the next station is entered. It should be noted that the temperature inside the heating enclosure area is about 8 〇. 〜 ~110 ° C, and the temperature outside the heating cabinet area 200 is about 4 ° ° C. Therefore, by using the above-mentioned manner, through a suitable buffer circuit and power line design, a plurality of DDR2 dynamic random access memory modules 4 on the truss plate 130 can be simultaneously driven by one driving board 120, not only Thus, as shown in FIG. 2, the driver board 12 〇 also transmits the DDR2 signal to the next stage of the driver board 120 'so stacked, so that one motherboard 100 can simultaneously test hundreds of DDR2 dynamic random accesses. The function of the memory module 4〇〇 greatly reduces the assembly and maintenance costs of the traditional multi-wafer high-temperature test system design. ^Please refer to FIG. 3 again. FIG. 3 is a block diagram of the memory test circuit, wherein the buffer (Buffer) 112 is located on the bridge board 11 and respectively signals the DDR2 signal (not shown) and the control signal (not shown). Buffering, and the control signal is 201019335. It can pass the parallel scale of the computer (Pn.nt, material and data level; road, data sinking two: the logical level on the hidden body bus, ie Can be 嫉 = ^ 〇 Hf! fDDR2 dynamic random access memory "Group 4 入 into the FF or 〇〇 data. From this can be seen = parameter generation 11, the device called e reckless, the way only It can produce two types of data, such as scare and sputum, 'for different parameters, __ try at room temperature' and the original _ design has been able to _ memory high temperature lit. At the same time, the design advantages of this case include better Referring to FIG. 3, it can be seen from FIG. 3 that the component configuration of the present invention is arranged to the outside of the heating chassis area 200 by the room circuit's main circuit tips (the area of rc' The area is supplemented with a cooling airflow design to ensure that most of the electronic components work Within the normal operating temperature range, the reliability of the device is increased, and the number of times of equipment maintenance is further reduced. Another novel design of the present invention is to transmit the carrier plate 30 through the signal connection placed on the drive plate 120. The device 122 and the driving board 120 mutually achieve a connection of DDR2 signals. Please refer to FIG. 2, in which a set of gold fingers 132 is provided on the carrier board 13 for signal transmission, when the rack board 130 is used. After passing through the heat insulating layer 210, the design is connected to the #122 connection on the driving board 120. The design achieves two advantages. First, the connection line derived from the DDR2 signal line is difficult to connect. Problem, secondly, isolating the signal connector 122 from the periphery of the heating area, reducing thermal shock and increasing the number of times the system is plugged and used. 201019335 Referring again to FIG. 3, the power supply design of the present invention uses an independent power supply 300. 'To provide high-volume DDR2 dynamic random access memory modulo and 400 power required for operation, also through the control panel of the computer motherboard 1 'can be used to § hai drive board The power line on the 彳20 is controlled. When the cradle 130 is to be detached from the driving board 120, the system performs power-off treatment on the power supply. When the susceptor board 130 is loaded again into the driving board 120, the power output is actively restored. 'The purpose is to protect the safety of the test products, these control processes can be achieved through the design of the software program, as shown in Figure 4 is the power line design on the drive board 120. _ From the above technical description, the present invention The high temperature test system has many advantages such as lower cost, easy assembly and convenient system maintenance. The rate is different from that of the existing temperature test system, but it can achieve the same effect as the traditional high temperature test equipment. 'It is a novelty and progressive technical creation. Therefore, the system design of this case can not be said to be an important creation of a test technology. The person disclosed in the present case, DDR2 memory is an illustrative example, which is a kind of preferred embodiment, but some local changes or modifications Those who are motivated by the technical ideas of this case and who are familiar with the skill of the art can not infer the patent rights of this case. In summary, this case, regardless of its purpose, means and efficacy, is showing its technical characteristics that are different from the conventional ones, and its first creation is practical, and it is also in compliance with the requirements of the patent application. I was granted a patent in the early days, and I was very happy with the society. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a high temperature test system according to a preferred embodiment of the present invention. Figure 2 is a schematic view showing a cross-sectional view of a high temperature test 201019335 system in accordance with a preferred embodiment of the present invention. Figure 3 is a schematic diagram showing the block diagram of the memory test circuit of the present invention. [Main component symbol description] 100: computer motherboard 110: bridge board 112: buffer 120: drive board 121: power line Φ 122: signal connector 130: carrier board 131: data level circuit 132: gold finger 200: Heating the chassis 210: the heat insulation layer 220: heating the air blower 230: the heat conduction port 300: power supply® 400: DDR2 dynamic random access memory module 11

Claims (1)

201019335 十、申請專利範圍: 1·一種高溫測試系統,其包括: 邱雷個計算機㈣,其可將—記憶體訊號輸出至外 控=標準輸出入控制介面以提供測試裝』 ㈣ίΐ—舰餘接裝置’其具魏魏衝元件,可提 供祕隱體訊號緩衝後再輸出以增加其扇出的能^1 =源供應II,用以提供各電路模塊所需的電力; Λ可嵌人數侧立作業的該記憶 才、、、且,忒承条裝置並可與橋接装置相互連接與分離; 埶有隔熱保溫的功能並具有一加 …、裝置對機,^卩的空錢行加熱及職的功能; ===狀卿梅峨=.= Ο 承竿所述之高獅⑽統,其中該 提供結以傳遞記賴訊號並 3·如f請專利翻第2項所述之高溫測試系統,盆中該 =指上的職進-步包括來自断算__控制訊‘ 4. 如申請專利範圍第2項所述之高溫測試系統, ίϋίίΤϊΪί熱機箱之隔熱板而與該加熱機箱外^ 該橋接裝置相結合者。 5. 如申請專利顧第1項所述之高溫測試, 橋接裝置除可將職_給該承綠置外,並可將訊 12 201019335 時傳Sdtfl置而形成訊號串接結構者。 統,其中 憶體資料 料寫入參 鲁 13201019335 X. Patent application scope: 1. A high temperature test system, including: Qiu Lei computer (4), which can output the memory signal to the external control = standard input and output control interface to provide the test device. (4) ΐ 舰 - ship surplus The device 'has its Wei Wei Chong component, which can provide the secret signal buffer and then output to increase its fan-out energy ^1 = source supply II to provide the power required by each circuit module; The memory of the operation is only, and, and the slatting device can be connected and separated from the bridging device; 埶 has the function of heat insulation and has a function of adding, ..., device, machine, and The function of the high-voltage test system described in the second item, which is the high-speed test system described in the second item. In the basin, the step-by-step includes the step-by-step calculation from the __ control. 4. The high-temperature test system described in the second paragraph of the patent application, ίϋίίΤϊΪί thermal insulation panel and the outside of the heating cabinet ^ The bridging device is combined. 5. If you apply for the high temperature test described in the first paragraph of the patent, the bridging device can be used to send the singularity to the singularity, and the Sdtfl can be transmitted to form the signal splicing structure. System, in which the memory data is written into the reference
TW97142985A 2008-11-07 2008-11-07 High temperature test system TWI389128B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW97142985A TWI389128B (en) 2008-11-07 2008-11-07 High temperature test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW97142985A TWI389128B (en) 2008-11-07 2008-11-07 High temperature test system

Publications (2)

Publication Number Publication Date
TW201019335A true TW201019335A (en) 2010-05-16
TWI389128B TWI389128B (en) 2013-03-11

Family

ID=44831715

Family Applications (1)

Application Number Title Priority Date Filing Date
TW97142985A TWI389128B (en) 2008-11-07 2008-11-07 High temperature test system

Country Status (1)

Country Link
TW (1) TWI389128B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103592527A (en) * 2012-08-14 2014-02-19 智邦科技股份有限公司 Test system
TWI742726B (en) * 2019-06-19 2021-10-11 韓商泰克元股份有限公司 Test board and test chamber

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103592527A (en) * 2012-08-14 2014-02-19 智邦科技股份有限公司 Test system
TWI465737B (en) * 2012-08-14 2014-12-21 Accton Technology Corp Burn-in test system
CN103592527B (en) * 2012-08-14 2016-08-17 智邦科技股份有限公司 Test system
TWI742726B (en) * 2019-06-19 2021-10-11 韓商泰克元股份有限公司 Test board and test chamber

Also Published As

Publication number Publication date
TWI389128B (en) 2013-03-11

Similar Documents

Publication Publication Date Title
TW497199B (en) Semiconductor device
KR20100052394A (en) Stacked memory array
US20100005202A1 (en) Dynamic segment sparing and repair in a memory system
US20140040698A1 (en) Stacked memory device with metadata mangement
US20120084483A1 (en) Die expansion bus
TW201015567A (en) SSD apparatus
US20130060399A1 (en) Sensor-based thermal specification enabling a real-time metric for compliance
KR20190019209A (en) DDR memory error recovery
US8015426B2 (en) System and method for providing voltage power gating
US20100005220A1 (en) 276-pin buffered memory module with enhanced memory system interconnect and features
US11809712B2 (en) Memory system with threaded transaction support
US20100180154A1 (en) Built In Self-Test of Memory Stressor
WO2016160162A1 (en) Method and apparatus for improving immunity to defects in a non-volatile memory
KR20140002926A (en) Integrated circuit chip and memory device
CN105808462A (en) Simulated memory realized based on FPGA (Field Programmable Gate Array), realization method for simulated memory and computer
TW201019335A (en) High temperature test system
TW201001416A (en) Semiconductor memory device
TW201344444A (en) Motherboard and data processing method thereof
TWM618092U (en) Certificate management system for automated domain verification
JP5940748B2 (en) Integrated circuit floorplan for compact clock distribution
US20120054547A1 (en) Power dissipation test method and device therefor
CN102446132B (en) Method and device for performing board-level management by simulating local bus
JP5181638B2 (en) Semiconductor integrated circuit design method
TW201040678A (en) Multi-point universal encryption transmission interface apparatus
CN101645029A (en) System and method for testing peripheral component interconnect express

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees