TW201019120A - Method, apparatus and system for reducing memory latency - Google Patents

Abstract

A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Description

201019120 VI. Description of the invention: [Technical field to which the invention pertains] - The embodiment of the present invention is generally related to the field of computer memory, and more particularly, the improvement of 5 κ for serial communication memory latency and reliability. [Prior Art] In a memory system using the same speed serial interface, a host (such as a system integrated chip, a computer, a graphics controller, or the like) or a plurality of devices and systems are used to transmit commands and data. It is expected to be able to extract, take, and combine error detection to ensure normal system operation. Serial Link has an inherent Latency because ^ is only transmitted as a bit. In addition, the 'serialization and deserialization steps will take the time outside the production. The use of these flaws alone does not significantly improve the latency, so a special access method is used (for example, accessing different, dedicated child memory regions from each node) such as serial access (StHpedA(10) width by starting 埠The link (PortBindin uses a consistent number of bee good) frequency: the memory potential can be reduced by simultaneously transmitting data containing many bits, "increasing the bandwidth without a formatted access method. There is also a need for quantitative data security. For example, in a column of channels, 'unless the system causes unacceptable latency, it may be undetectable. In the case of a link, some It is still idle during the command period. In those same periods, the = wide line is not filled with repeated instructions. This method can use the two sex = stretch to the next one to provide the characteristics of the 埠 structure. A conventional tandem bit configuration 100, according to EIA Standard 3 201019120 RS-232-C. In the figure, the serial transmission of data is similar to an RS-232 connection, in which it is observed and designated by rotation one by one. It is not in the value 124 In the same sense, the individual two-bit values (bits) ι to us can be combined into an overall value of 124. For example, if the first bit is 1〇4 and is specified as the largest value of 124 The valid bit (M〇st Significant BU, MSB) ' is followed by the second bit 1〇6 and others, etc. (such as bits 〇8, 110, 112, 114, and 116, etc.) until the least significant bit is (4) The Significant Bit (LSB) is filled with the last communication bit ι0. The combined value in this example is called Frame 128, which contains the value 124 and the stop and start bits 102 and 120. In addition, the box The 128 series is described using additional bits, called Framing Bits 126, which includes a start bit 120 and a stop bit 122, making the receiver available to find the beginning of block 128 and can be expected to be broken. When the middle frame arrives, in other architectures, even when the data rate between the transmitter and the receiver is slightly different or changed, the framed bit 126 can be utilized to facilitate the receiver to reliably find individual bits. The communication of serial links to memory will cause significant latency and provide more than one host A single memory will cause noisy memory resources. In addition, the memory may have - or multiple channels, each containing a transmitter array receiver and associated circuitry to improve latency and bandwidth. (BQUnd pQn Si Some itch is still idle during the instruction. In the same period φ, go to μ m 'sexual heavy borrowing Μ eight used bandwidth will fill the space = wide t This method can be used to repeat the time from different periods In the early days - 蟑, to provide the characteristics of the structure. In the case of the car, the 'data is transmitted in multiple orders, but the instructions must be able to operate independently. 4 201019120 =ΓFirst, if not used, may contain repeated instructions ( Command Duplicates). Second, Ganbi κ is because of the mismatch of error management; so that f can be distributed at the same time. In addition, serialization, deserialization, and data-framed are additional steps of t!, so serial communication increases latency and parallel communication. [Invented within 1 world] It is necessary to guide people and implement techniques that can reduce the potential of memory. Φ ^ 发 = expose - a method, device and system for improving the latency and reliability of memory communication. In the case of the ancient times, the invention provides a method for reducing the memory potential of the host computer system and a memory between the host computer system and a memory device. Communication data, wherein the == machine computer system is engaged in the memory, and the bee is in the group τ埴赤邮 and between the host computer system and the memory via the group A single time interval communicates the Φ related to the information. The present invention provides a method for reducing the memory potential of a host computer system 'lightweight to a memory, the card = main = bit = one of the memories or a group of bees The time interval is from two m secret data, which is expected to be one of the contents; and, the memory system is modified to receive the relevant data from the host computer at a single time interval in the computer system. Know the order in the information. In an embodiment, the present invention provides a system for reducing memory latency 5 201019120, comprising a host computer system coupled to a memory, the memory using a connection system to reduce memory latency. The linking system includes a plurality of ports for communicating data and instructions, wherein the plurality of two or more nodes can be linked into one or more sets of files, the connecting system is configured to: One or more of the memory communicates data between the host computer system and the memory over a plurality of time intervals, the lanthanum being one of the group ;; and via the 埠 or the The group communicates with the host computer system and the memory at a single time interval with respect to one of the instructions. [Embodiment] Embodiments of the present invention generally relate to improvements in serial communication memory latency and reliability, however, the same can be applied to other forms of interfaces, such as High-Speed Parallel. The term "Mem〇ry" as used herein means one of the components in a computer system (see Figures 2D and IIE), which is responsible for the operation of the previously stored material. Any "Host" (such as a computer processor) or peripherals (such as a keyboard, monitor, video camera, mass storage device (disk, light, tape, etc.), network controller, or wireless network) . Typically, a, the memory system handles - or multiple microprocessors that process data in a computer system. The data can be stored in the memory by a host, such as random access memory (RAM), static random access memory (sram), dynamic access memory (DRAM), flash memory. Flash (Flash), Memory (PROM), Can be erased -, ^ 口 口 j徕 In addition to stylized read-only memory (EPR〇M), electrically erasable programmable read-only memory ( EEPR0M) or, for example, a read-only memory (ROM) of 6 201019120. The host can access the memory directly via a bus (e.g., pci) or via an intermediate 3 memory controller. The serial access to the memory involves the conversion of a single sequence of electronic signals through a single circuit and the conversion of meaningful instructions and responsibilities between the memory (similar to the RS 232 shown in the figure). The circuit that performs the conversion is called "埠(p〇rt)". In an embodiment, in order to reduce the potential of the memory, a Masking Scheme is used to enable the writing of instructions and data to be described in the same communication frame including the masking information. To reduce the number of bits and latency in the box. In addition, in order to reduce the latency, a memory-based protocol is provided to reduce the shorter frame size, and to provide greater flexibility with respect to the old dynamic random access memory. And reduce the change of the instruction set when increasing the bandwidth. Figure 1 shows an example of a single host-connected memory. In the embodiment, the link memory 200 includes a memory core 2 (such as DRAM or flash memory), which includes a multi-bank (譬© library) and is connected to the link of the link memory 200.埠Memory System 2〇4 5 The memory of the core 202 is communicated in many ways, such as four 206 to 212. All four 埠2〇6 to 212 operate together to provide an interface to a single-host with #invertible view. These memories are used independently, such as reading from one memory and writing from another memory at the same time. The memory core 202 can also include a memory read bus to read data, and a memory f write bus to write data. However, in the memory core, there is a single connection to read and write data. In addition, the link memory system 204 includes a link multiplexer and a linker multiplexer 7 201019120 262 ′ will be described in FIG. 2 κ and II i, respectively. In the known technology, the transmission of all instructions and data bits is transmitted immediately, and each flat line arrives at the same time as the code is formed. $, while the degree becomes faster, the data flowing through these lines may be sampled incorrectly or at the wrong time (for example, using the relevant clock signal). In order to solve the problem of high-speed sampling, a self-sampling serial signal is used (譬, RS, 232). However, parallel methods will increase latency because their data are processed on time. In the embodiment, the communication between the serial port and the memory © latency and reliability utilizes multiple serial interface or iterative grouping and repeating instructions (Duplicating CoInmands) 'which may be consecutively or temporally , or in the same time or spatially. Embodiments of this technique are described herein and are implemented using a single host-connected memory. In one embodiment, a transmitter (Tx) can convert sixteen bit parallel data into a serial bit stream and transmit the single bit stream. A receiver (Receiver, RX) can receive a sixteen-bit single stream and convert it into a parallel stream. In this example, a region of memory can be three; ^ two bits wide and at about the same rate. In the memory 2〇〇 in the figure, four 埠 206 to 212 are used, so each channel between four 埠 2 〇 6 and 212 has a one hundred and twenty octet data motion, with a sixty four The data stream of the meta (for example, sixteen bits multiplied by four turns equals sixty-four bits of each channel). This one hundred and twenty-eight-bit motion system is supported by the necessary circuitry in the chip. Different from the prior art, each of the embodiments 〇2〇6 to 212 uses a serializer/deserializer to serialize the data stream at a faster rate. 201019120 and deserialization. For example, a Phase Locked Loop (PLL) (譬 244) can be utilized to multiply an input clock by a higher rate to match the input data rate used to sample the bits. Although the time at which the data stream reaches 埠206 to 212 may be slightly different, it allows these data streams to flow faster. In other words, each stream flows at the same speed and at a much faster rate (ie, each data stream can flow at the same rate as other data streams; however, each data stream can be set to flow earlier than it. The rate is faster). In addition, the timing of the elements may not be perfect, but ® does not need to be aligned to these bits because the actual arrival time of these bits does not affect. Therefore, instead of synchronizing the bits at the pin, the bits are synchronized after being deserialized in the respective blocks 206 to 212. For example, as shown by asterisks 230 through 236. Similarly, after deserializing these turns 206 to 212, the flow rates of the data bits at or near these asterisks 230 through 236 are compared to the high speed external memory interfaces 214 through 228 (representing TxO, Txl, Tx2, Tx3, respectively). RxO, Rxl, Rx2, and Rx3) (譬& such as two hundred and fifty picoseconds) may be twenty times slower (e.g., five nanoseconds). In one embodiment, the ports 206 through 212 are capable of phase detection, data bit management, data bit sampling, and lane alignment. Instruction interpreter 248 continues to process instructions based on the associated/closely related instructions of the channel configuration (further described in Figures 2C, 7C, and 7D). 240 denotes PLE signal, 242 denotes /LPD signal, 246 denotes REFCLK signal, 250 denotes mode register, 250 denotes command signal, 252 denotes triangle, 258 denotes library signal and 260 denotes mask signal. FIG. 2B shows an embodiment of a single host connection 270 9 201019120 of the four-way memory 200. The embodiment shows a connection 270 between the memory 200 and a host 271. The host 271 makes a read and a write operation. Serial Port Memory Technology (SPMT) defines groupings together to form a broad data communication. The number of 埠206 to 212 can be dynamically selected in a link group. For example, a single 埠 or any number of 埠 (such as the number of powers of two) may be combined to provide 埠 206 to 212. When fewer turns are used, fewer pins and less power will be used. When more 埠 is used, the bandwidth is increased and the latency for obtaining the same data is reduced. The number of links can be changed at any time. Figure 2C shows an embodiment of a 埠 link selection 275 for a single host interface. 276 denotes one (available for sixteen-bit access and a single instruction), 277 for two (a 32-bit data access and 32-bit instruction or instruction repetition), and 278 for four Or more (available for 64-bit data access and 32-bit instructions and repetitions at the same time). When two or more links 277 and 278 are linked, the data is passed to all the cells in the group, and is effectively multiplied by the data bandwidth. However, individual instructions may only need one 埠, leaving the rest unused. Therefore, in order to avoid wasting bandwidth, improving memory operation and storing instruction bandwidth, a set of closely related instructions or accompanying instructions (Adjunct Command) is provided. These instructions correctly use the extra bandwidth so that it is not wasted, and such closely related/affiliated instructions can be posted before or after an instruction and can be issued simultaneously with the rest. For example, when an Active Command (ACT) is issued, the current library command (Active Bank Command, ABNK) can be issued as an attachment to complete the instruction. Similarly, the auxiliary write mask instruction (Write Mask 201019120)

Command, WMSK) can be accompanied by a Write Command (WR). At 埠0, the user can receive instructions, but related dependent instructions can be received by other , to retain the command bandwidth. The commands ACT, ABNK, WR, and WMSK are further described in Figures 7B through 7D for reference. In addition, a single option initiates the repetition of instructions to improve error detection to avoid erroneous instructions from abnormal memory operating conditions. When this option is activated, a single iteration will be compared to a Duplicate of one of the instructions in the first box and the 10 subsequent boxes. When linking and using two or more of 277 and 278, no additional bandwidth is required for repetition because the repeat is displayed at the same time at the same time. Although the instructions are repeated, the material is not repeated in this embodiment. When there are at least four links 278, it will be possible to use both repeat and attached instructions. Figure 2D shows an embodiment of a smart mobile phone architecture 280 comprising a baseband processor 282 and an application processor 281, and individual volatile memory (e.g., DRAM 274, SRAM/DRAM 283), non- Volatile memory (such as NAND 272 and NOR flash 273) and communication channel (shared memory) 269 are located between the two processors 281 and 282. Memory 272 to 274 and 283 are used to store and receive executable code and maintain privacy information that is not shared by the connected processor. Any sharing or communication is performed by communication channel 269. The application processor 281 can be coupled to other peripheral devices such as the camera 201 and the display device 203. Figure 2E shows a smart phone architecture 284 for the selected embodiment of Figure 2D, which includes SPDRAM 285. In an embodiment, 11 201019120 忑 is hidden between the baseband processor 282 and the application processor 28 i. In an embodiment, SPDRAM 285 can be used to communicate baseband processor 282 and application processor 281, storage code and data for both processors, and to reduce the number of memory elements or technologies needed to implement the architecture. In addition, the number of links between the memory and the processor can be reduced, including the exclusion of specific communication channels. In one embodiment, a segmentation is provided such that some hosts can access a portion of the memory while others are not. This allows the memory device to be shared in a secure environment, such as for a baseband software. For example, the application processor 281 can load the baseband software image into the spDRAM and instruct the baseband processor 282 that its image is in place. The baseband processor 282 will then remove access to other hosts and confirm the validity of this image. If its correct baseband processor 282 can continue to operate from the image, it does not need to be split with the software running on the application 281. Figure 2F shows an embodiment of a multi-master connection configuration 286, 287, and 288. In an embodiment, the multi-host function can be combined with the multi-tan link example. If a host (such as an application processor 281) needs more bandwidth, it can utilize many interfaces of its interface, while other hosts can Continue to use single-埠. In the embodiment diagram, some combinations 286 (two independent hosts, dual ports/hosts), 287 (two independent hosts, single factory itch, host 2: double 璋) of a plurality of hosts are connected on a four-inch device and 288 (four independents per host). For example, in the combination 286, the hosts i and 2: correspond to two. In combination 287 'host! The interface is; 应, and the interface of the host 2 corresponds to two 埠 2 and 3. In the combination of Mg, the interface of each host corresponds to a single frame. It can be understood that in the embodiment, 12 201019120 can be used for any combination of hosts or interfaces, for example, a single host can connect all four ports together. What is actually corresponding to the host is dependent on the beta of the scratchpad, which gives the length of the connected itchy group. Figure 2G shows an embodiment of a multi-host interface memory 292. In the figure, the multi-host 埠 connected memory (multi-host memory system) 292 includes four 埠 mo and communicates with the memory core 291 including eight memories 289. For the sake of brevity, only a limited number of files and memory 289 are shown. Although the multi-host memory system 292 is similar to the single host memory system 204 of FIG. 2, the data from each of the 埠29〇 is available to each bank 289. In this embodiment, the memory 289 is defined as A portion of the overall multi-host memory system 292 that can track data transfers independently. In addition, by providing individual accesses, a single frame during the command period can be associated with a single-memory bank of memory 289 and does not conflict with accessing other memory banks. The multiplexer 293 and the multiplexer 294 are multiplied to produce a possible embodiment of a crossbar switch to direct data between the plurality of groups of memory banks 289 and 290. Figure 2 shows an embodiment of a 淳 link control register for up to sixteen ,, and a repeat instruction acknowledge register 296 for up to sixteen 。. For the sake of brevity, the connection used in the embodiment occurs in a continuous number of multiples of multiples (such as 埠丨, 2 or 4), and with the matching criterion (Matching ModUlus) (譬如埠〇 corresponds to four 埠, 埠〇 or 2 corresponds to two 槔, or any 埠 corresponds to a single 埠).确认 You can confirm your identity in the -link group based on the settings of the scratchpad. The figure shows a bee control register 295 in combination with a sixteen inch. This link describes and provides a '13 201019120 P white layer mode, 111 if the bit is not set, all the devices will be independent, s seven in two devices, only use the bit open n阜 will be independent Operation. For 士一一, the position 兀0 is used, and for the four 埠 device: 埠连^ to 4 describes the possible link 'by adding to the four, 阜, '. For the person's wearer = the rest of the person is in the position..., the four-way link is at the position of 5 yuan 13 and all the 埠 are at the position το 15°. This mode can continue without limit. Alone = '蟑• can not belong to a link group, in which case they can be part of a link group and can be operated individually: ^ can be more than - link group - part of a pair The processing technique of this punch = is to select the largest link group. When the temporary cache 295 is used to add a link group, the next command is then used in the content of the link group, and it is not necessary to release a new game 7 until a new one is ready. When a trip is removed from a link group, it may be stopped or used immediately afterwards. In the embodiment, each bit is allocated to a temporary register to confirm the Duplicate Command, as shown in the figure. Indeed < Register 296. If a group is linked to any group, it will confirm the private value of its, ·, λ埠. If it is not linked to a group, it will be repeated in its continuous cycle. FIG. 2I shows an embodiment of a linked demultiplexer 294. In one embodiment, the p〇rt Ready Lanes 294a (e.g., p〇n_rdy lanes) are generated by an individual and are given a link instruction. For example, when four 埠29〇 are linked, all 埠 preparation channels 294a will be issued. However, if only 29〇2 and 3 are linked to the two groups 201019120, the preparation channel 294&_ kiss [3: 2] will be released. Similar to the two right to operate alone! ‘Only publish p〇rt—_(1). This technique is used to confirm the normal transfer size and routing from 珲290 to memory 289, and to create a global memory character lock (Latches). Figure 2J shows an embodiment of Tables 2973 and 2975 which shows the route of the linker. For example, when the data arrives, the demultiplexer routes the data to the correct channel according to the routing function table 297a. The ® register is then based on the function of enable_fn (298 in Figure 2) to capture the data for the memory into the correct channel, as shown in Table %. Once all the information has been locked, the core storage data is ordered by enaMe & using wr-strobe. By using a parallel data path, write masking or copying of selected data can be achieved. At the beginning of the storage period, all masks are set according to, for example, the (four) lane is prohibited. At the time of the arrival, the masks of the relevant parts are routed and stored with the data. If not all data arrives (such as interruption or short transmission (ShGrt Trans (4)), only the arrival data will be stored 'because the data channel has not arrived so there is no chance to clear the relevant mask. Figure 2K shows a connected multiplexer (9) In an embodiment, a preparation (such as a read_cmd) signal and a read command (such as read_cmd) are read from a memory ("much", called delay 2" The data arriving at the memory (and the lock) can be selected immediately for output 埠 290. The choice of this is simply achieved by using the delayed output value 15 201019120. The P from the read command (m_rdy channel 2 is interpreted, similar to Solution: The multiplexer channel is mapped to the output 埠29. It is based on the function of Figure 2. <clothing is not for the sake of brevity, taking data characters from memory bits in every cycle, with storage or delay: rate and the need for more (four) Ge 阜. If you want more data to get the data than the output cycle, then you will build a cat, and a cedar heart, along with the pre-fetch Buffer. There are two: ': Select a shorter segment across consecutive cycles. Condition 22 can be linked to the pre-fetch buffer. To throttle the data, the instruction interpreter divides the read instruction into shorter quantities and issues intermediate instructions at a lower rate to match the output rate. Figure 3 shows a step-by-step embodiment of the block synchronization. Initially, the memory system shut down the power to reset 302. In order to turn on the power, the Link Power Close (Link P〇wer_D〇wn, /LPD) is driven to the high bit 304, causing /LPD to be equal to zero and stopping. However, when /LpD is equal to one, then block search 306 is initiated to find the particular code or bit order known as SYNc. When SYNC is detected, the step proceeds to an operational mode 3〇8. This step can continue with multiple (if implemented), as shown in Figure 4. Since the host and the memory exchange data in tandem, the receivers are synchronized to confirm the positional correspondence of the bits in a frame. In order to confirm the correct synchronization, the link searches for a specific bit sequence in the "FrameSearch" case 3〇6. For example, initially the serial link transmits one of the two 201019120 synchronization bit sequences: SYNC and SYNC2. The physical layer of the transmitter (Rx-PHY) can detect these framed data packets by using the host and the memory. SYNC plays a key role in Link Bring-up after a reset or error. In addition, in normal operation, the memory Tx-PHY will transmit SYNC in any unused box. In normal operation, the host Tx-PHY will transmit SYNC or SYNC2 in the unused box. When SYNC is detected and recognized from the memory, its steps proceed to normal operating mode 308. If the frame fails, such as an indication _ a twentieth decoding error, then for example the memory will switch back to the "box search" case 306 until SYNC is detected again. In any state, if /LPD goes to zero, it means that 埠 will switch back to the "Link Down" state 304 and start over. The memory transmits SYNC2 to indicate an error in receiving the host data, or because a "link closed" status or a framed error is left. The host exclusively responds by sending a SYNC until the memory is re-established and the S YNC is transmitted. The host transfers S YNC2 between instructions for proper error recovery operation. The SYNC and SYNC2 setup and reply connections are framed, and the host schedules the establishment of a coordinated link. Figure 4 shows an embodiment of a step for power control. It receives /LPD. At decision block 402, it is determined if a turn is on. The slash before /LPD indicates the inverse logic. For example, if the link is power-off when /LPD is equal to zero, indicating that its power is not on, the step will proceed to block 412 to stop the master. Similarly, /LPD equals one to indicate that the power is not off, indicating that it is power on. If /LPD is equal to one (e.g., the connected power is turned on) then 17 201019120 performs a training step in which block 404 is searched for a particular code or sequence of bits (e.g., SYNC). The training step for the SYNC search will continue until SYNC is detected, and then in processing block 4〇6, the steps will enter an operational mode. This step will be further described in Figure 3. At decision block 408, a confirmation is made as to whether there is an error. If so, step = will continue to decision block 402. If not, then in decision block 41, it will be confirmed whether more 埠 are successively entered into the operational mode. If no other defects are added, the step will continue to operate mode block 406. However, if an additional flaw is detected, the step will continue to process block 414 to train the new trick. Some additional (multiple) systems are processed in processing block 416. The use of multiple uses is also described in Figure IX for reference. At decision block 418, an error will be confirmed. If an error is confirmed, such as in the decision block 430, the power is turned off by the itch (e.g., /LPD = G). If so, all blocks will be stopped at processing block 432 and the step will advance to a single mode of decision block 434. If /LPD is not zero in decision block 434 (e.g., /LpD = i), then all processing blocks will be trained and the process will continue to processing block 416. Referring back to decision block 43, if /LpD is not zero (e.g., /LPD = 1) then the step will proceed to the training error in processing block 428 and continue to processing block 416. The eye returns to reference decision block 418, and if no error is found, then decision block 420 will additionally determine if there are more 璋 joins. If so, the step will continue to the new training step of processing block 414 (e.g., looking for each new =YNC). If there is no extra 开启 on the right, you will be confirmed in the decision block 疋 No 移除 will be removed. If $, the step will continue to processing block 416. If 18 201019120 is, processing block 424 will stop any removal. Here, at decision block 426, it will be confirmed if a single defect is available to switch back to the single-璋 mode. If so, the step will continue to the single mode of processing block 4〇6. If not, the step will continue to the multi-mode mode of processing block 416. Right power control 238 (refer to Figure 2A) is responsible for transmitting /LpD, while 埠 to 212 is responsible for training itself and the processing in Figures 3 and 4. Figure 5 shows the steps for repeating confirmation and instruction interpretation using a single unit. More complex steps using multiples will be shown in Figure 9. As further described in FIG. 5, in the processing block 5〇2, the receiving, reading and decoding of the data are performed in a frame (such as the first port or the main port) to start the first frame. At ^ block 504, it will be confirmed if a defect is detected. If an error is detected, at block 528, the error will be returned to the end step. If the debt is not detected, the decision block 506 will confirm whether the repetition is turned on. It should be understood that its re-use and need are turned on or off. If the repetition is turned on, the step proceeds to the data reception, reading, and decoding of the step block 508, which is performed immediately after the second frame. Furthermore, in the decision block 5 〇 〇 will confirm that it is a detected error. If it is, the step will end in the block like error back. If not, the step will continue to block 512 to confirm if the first block is equal to block = 2, and the step will continue to block Μ, if not, the step will continue until & block 528 ends with an error turn back. Block 5^ does not 7 to bee error (and does not open the repeat, please return to the reference decision area), : will continue to confirm whether this box is an instruction or data. If this box ^曰々' is in decision block 516 it will be confirmed if this instruction is valid. The traits are *, , and invalid, and the steps will end in block 528 with an error back. If the instruction = 19 201019120 = 518 will confirm whether the instruction is in the sequence or in the column, the step will end in the transmission (4). If the instruction is in the sequence, block 520 will process the instruction and block 530 will post a normal return.凊 Return to reference decision block 514, if the box is (4), block 522 will confirm whether the memory is ready for write operation. If no ^ (4) at block 528, the error is reversed. If so, the processing block 524 will be written to the memory & and the step will end at block 53. The steps of 'blocks 516, 518, and 52' in this embodiment are performed as shown in Figure 6 for an example of the steps in which various functions are performed. Block 602 provides the steps of receiving, reading, and decoding the #stream stream. For example: 埠-埠 receives a single stream of data (in bits) via RX, and in the figure shows a parallel string "IL and then decodes (such as using 1 decoding). Yu uses the Linked Power Off (/LPD) signal to control all of the power (via the power control mechanism), allowing power to enter and out of the single host to connect all of the bee memory' as shown in Figure 2A (Figure 2A) The dotted line in the middle indicates the power control of /LPD). In decision block 6〇4 it will be confirmed if /LpD is equal to zero. If zero, the step will end at block 614 with a return error. However, if /LpD is not equal to zero, the step will continue to process block 606. At processing block 606, a data frame is received that contains 埠 to receive a bitwise data stream and produces a parallel stream of frames (e.g., twenty-bit deserialization). The block is decoded at processing block 6〇8 (e.g., using 20 201019120 17B/20B decoding techniques) to then generate valid data. In decision block 61〇 the validity of the box will be confirmed. For example, it will be confirmed if the box has a twenty-bit code and is correctly decoded as a seventeen-bit value. If the conversion fails, because it is not clear that it has not produced any results, its validity will fail and an error will be returned at block 614. However, if the conversion is successful and results are produced, the data frame will be considered valid and will be returned normally at block 612, as will be further illustrated in Figure 9. Figure 7A shows an embodiment of a 17-bit post-decoding (p〇st_Dec〇ded) box 700. A seventeen bit decoding block 7A of the embodiment diagram can be used to transfer seventeen bit data, instructions and/or status, and is converted to produce a twiter box for serial transmission. Data, instructions and status are transmitted and received in a twentieth box. The opposite step will be performed when receiving' where a ten-bit conversion coding frame is decoded to produce a seven-bit box 700' to hold data, instructions and status. The seventeen-bit post-decoding block (format) 700 shown in the figure presents the first sixteen elements in the payload (Payload) 702, and contributes the last bit (ie, the seventeenth bit) to the reward. Indicator 704. The memory access format is based on the basic decoding format. For example, bit sixteen 704 may indicate that its payload is set to one or zero for use in data, instructions, or status. On the basis of the box-to-frame, the instructions and the written data can share their recipient links. To reduce latency, instructions can be inserted (or prioritized) into a write stream to delay the completion of the write command. Figure 7B shows an embodiment of an instruction, status or data encoding frame format 72. The embodiment of the figure includes, but is not limited to, an embodiment of an instruction, status, and data encoding block 720 of a serial port 21 201019120 DRAM (SPDRAM). The seventeen-bit coding block 720 in the figure is extensible, which provides flexibility to preserve multiple bits, and additional instructions can be added in the future (for example, depending on technology or demand changes). For example, flag 722 and secondary instruction 724 occupy seven bits (bits zero through seven) before block 720, and because most of the items in secondary instruction 724 are one, this region (including flag region 722) Additional instructions (e.g., up to sixteen instructions) may be added in the future to expand block 720. Similarly, other regions have a limited range (e.g., mode register ❹ group 726), which can also be used for additional instructions (e.g., the instruction region of mode register group 726, which contains only three instructions). Another such area is the DRAM instruction group 728 (e.g., the sub-instruction area of the DRAM instruction group 728, all of which is one), which can be used to add other instructions. The SYNC 730 controls and maintains the link frame synchronization, while the SYNC2 732 represents a specific link operation state. Both SYNC 730 and 732 are further described with respect to Figures 3 and 4. The data (frame) 734 contains a seventeen 10-bit box similar to the data box 700 shown in Figure 7A, which contains the seventeenth bit set to one and the next two octets. The current library instruction (ABNK) 736 and the current order (ACT) 738 will be illustrated in Figure VII. Write command (WR) 740 initiates a memory write cycle for a particular bank and column. The write mask (WMSK) 742 sets an octet byte mask for writing instructions in the step and has any effect with the WR instruction 740. WMSK 742 will be further illustrated in Figure 7D for reference. Read (RD) 744 represents a read command to initiate a 22 201019120 memory read cycle ' and Burst St〇P (BSTP) 746 represents an instruction to interrupt a current read. The instruction is fetched or written' and is based on the particular library. Precharge (PCG) 748 represents an instruction 'to pre-charge a particular bank of instructions, and Precharge All (PCA) 750 contains an instruction to pre-charge all banks simultaneously. Per-Bank Refresh (REFB) 752 enables specific banks to be automatically updated' and All-Bank Refresh (REFA) 754 updates all banks based on an internal counter. All ® banks are in the precharge state prior to the release of the REFA instruction. Mode Register Write (MRW) 758 represents an instruction to perform a write to a mode register. Mode Register Write Data (MRD) 760 provides write data following the MRW instruction 758, in the next middle frame, from 埠0, and in the form of an MRD instruction 760. Mode Register Read (MRR) 756 represents an instruction to perform a read from a mode register. The Self-Refresh Power-Down (SPRD) 762 will cause the memory core to immediately enter the self-renew state. Power-Down Exit (PDX) 764 represents an instruction that is issued to leave the self-updating power off and used to wake up the memory core after the connection is established. Figure 7C shows an embodiment of ABNK (埠0(ΑΒΝΚ)) and ACT commands 736 and 738. In order to transmit two or more instructions at the same time, they will support each other's functions or functionality as orthogonal to each other. The third criterion involves complexity' because Memory Semantics or implementation decisions can fail due to orthogonality. For example, the serial 埠 DRAM can include 23 201019120 with an instruction to initiate - the memory bank, and its column address to be started is too long for the frame. In a single case, this command would require a box of two or more, but for a link, it could be traversed in a box time on two or more. For example, ABNK 736 sets the upper five bits of target memory 753 and column address 755 for subsequent ACT instructions 738. The ACT instruction 738 is passed to the memory bank 753 specified in the last ABNK instruction 736. If two or more links are connected, a selective ABNK _ 736 instruction may appear on the second. The lower fifteen-bit 765 of the column address is assigned to the least significant fifteen of the ACT instruction 738, and the most significant five-bit element is assigned to the lower five bits of the last ABNK instruction 736, or appears ABNK 770 of Yu埠2. This embodiment indicates that instructions 736 and 738 can operate independently at any time in subsequent frames. This provides a variable group size, a general controller independent of the group size, and the semantics of the cross-link. Additionally, instructions 738 and 770 are complementary to each other and can be executed simultaneously. In addition, 757 represents a higher column address. Figure 7D shows an embodiment of WMSK and WR commands 742 and 740. Figure 7D shows a WR command 742 and associated byte/write mask 742 for selective writing. WMSK 742 represents an instruction that is set to use an octet mask 772 for the WR instruction 740 in the step and follows the WR instruction 740 to have any effect. After communicating the octet data, the mask 772 restarts the next octet. The letter "H" in the mask 772 indicates the high byte of the character conversion (e.g., bits 15 to 8), and the "L" indicates the low byte (e.g., bit 7 to 0). 24 201019120 Dish l 740 Start - a memory write cycle, to the specified memory 774 and line 776. Once the transfer order is 74〇, enter the data. If two or more links are linked, then a selective wms^ 780 = transmitted to 璋2' covers or masks the first octet (778). The masking claw repeats the female eight-bit 70' unless it is reset by the continuation of the WMSK instruction. Other embodiments of the two or more links include simultaneous reading and writing of the combination or simultaneous activation and writing of the person, according to the semantics of the memory and interface. Figures 8A, 8B and 8C show an embodiment of the write mask models _, 85 〇 and 875. For memory using serial communication, the number of bits transmitted by the reduced = indivisible is used to reduce the latent time. An indivisible transmission is defined as a box or a character length ^ 'the description of the total amount of data (such as a byte) or an executable to contain any intermediate operations that need to complete the instruction. Metadata such as "write" and destination address. For most memory, the write operator contains both the command, the address, the operator (in this case, the mask), and the data to be written. For faster memory devices, a description is required. The speed of the instruction becomes too high, so the Bum Transfer is used. The burst transmission starts at the instruction and the start data, but continues at the data stream and subsequent calculated addresses (such as increased No matter when the data is transmitted, it is accompanied by an additional mask indication signal. - Because the command and address may be required for non-continuous data transfer, the serial communication is followed by 'instruction, address, write mask and data. Encoding may be inefficient. In this case, the data will be transmitted with the boundaries & directives and addresses using 25 201019120 bursts. To reduce latency, write masks or WMSK instructions (such as one per tuple) Elementary) only need to accompany the data stored in the burst where the position value is not stored. Although such optimization can be critical for tandem interface efficiency, this mechanism can be used to reduce parallel memory. In order to improve the practicability of multi-host memory, by placing a write mask into the instruction stream, each host can use an independent write mask for independent transfer. Include WMSK companion data to reduce latency correlation' A three-purpose model will be used and illustrated in the burst. ❿ Figure VIIIA shows an embodiment of a repetitive pattern WMSK model 800. It contains the previous memory content (Mem 〇ry c〇ntents Bef〇re)8〇2, instruction stream 804 and subsequent memory contents (Mem〇ry c〇ntents After) 806. In the figure, WMSK is repeated in each transmission, for example, in containing red, green Only the red value is changed in the rectangle of the blue data, the other two colors will be masked, and the WMSK will repeatedly span all the three primary colors in this rectangle. Figure VIIIB shows an embodiment of the start and end WMSK model 85〇, including The suffix content 852, the instruction stream 854, and the subsequent memory content 856. Here, the write mask is only used for the initial portion of the transmission. For example, the network packet can start at Odd (〇dd) transfer boundary The first group of the transmitted four-bytes is optimized to access (align) the rest of the data structure in the packet. Once the starting mask is exhausted, the entire remaining packet data will be written to In order to complete the transfer, a new WMSK will be inserted to trim the last two tuples. Figure VIIIC shows an embodiment of a WMSK model 875 that utilizes a multi-string interface for repeating mode, including the previous memory. The body content 876, the command stream 878, and the subsequent memory contents 88. Among them, 26 201019120 WMSK is used for an I-cast. For example, the transmission size is selected - the data node, the eleven-digit number Only the second byte is written in the integer. Reference. Two: Mode _^ Qing & 85. Writer masks are reused or infrequently used to transmit the form (such as cache writers and mass storage to mask). In these cases, the data is included in the mask. Efficiency 'because it is not used most of the time. Compared to the early transmission, "small or smaller transmissions do not get the best of the burst transmission 1 so the data, instructions, addresses and write masks will be specified. Such a short delivery usually occurs in the internal cache memory, in order to reduce the tendency of the memory from such common use. Please, the assumptions in the Italian model _ and 850, the write mask contains 4 ' but疋Right to get the advantages of the burst transmission, it is not enough to link the man-masking fish instructions. In this case, the de-pling will be conveyed from the command and data. It is understood as a new instruction. In a single serial stream containing an indivisible transmission (box), the code is written to the address in its frame, and its data stream is calculated. The memory of the different memory is addressed in a sequence of frames and written in the occult It is described as a separate instruction and is applied to the unit burst to be published after the write command, and is located in the required data. A unit burst is defined as the number of bits ^, for the implementation of single-write The masked bit is multiplied by the number of write mask bits in the write mask instruction. When the write command is issued, the write mask will be cleared, so that subsequent data is written. Immediately follow the write command 'its application will start in the first unit burst. ... If you use the repeat mode described in model 800, the mask will repeat on 27 201019120 all units of the censored money change, the county released An additional write mask instruction 'applies a new write mask to all subsequent data. Using the start mode described in model 85G, the write mask will be cleared after the first soap level is burst. If additional masking is required (such as in the end unit bundle, medium), an additional write mask command will be issued that will only be applied to the next unit burst, and the write mask will be cleared at that time. For the Type 875, it uses a multi-version version of the model 8〇 The mask is repeated, but the WMSK instruction occurs at the same time, but on the other hand. If multiple serial interfaces are used, it may generate more complicated instruction configuration. In other words, the write command can be combined on one frame and the first write mask on the other frame to improve the usability of the bandwidth. Figure 9 shows a multi-turn for repeated verification (DupHcati〇n and instruction interpretation) The step embodiment begins at block 902 where the processing step 904 follows the processing of the first block in the processing block 904. In the block 906, the first frame receives the data via the corresponding Rx. The data = stream (which will then be decoded). The term "埠m+i" is used in the reference processing block 9〇6, the m" table does not link the group, and the "丨" indicates the number in the link group. In the example, 'i starts at zero, and because the single-host is implemented, the calendar is equal to zero. In decision block 9〇8, it will be confirmed that the first 埠(埠〇) is beneficial. If any error is found, the _ 942 will end with _ ERROR (4); ^ If the error is not detected, the step will continue to the processing block. 910 to confirm - 埠: until all 埠 has been confirmed. For example, in decision block 912, it will be true that there are no flaws left. If so, the steps will continue until the processing block is 9% and 28 201019120 to the next. If no, the step will continue to processing block 914. At decision block 916, it is confirmed whether the repetition is on. If so, at block 918, the current acknowledgment will be confirmed and, depending on the result, the steps will end at block 942 with a return error, or (if the repetition is not turned on, return to reference decision block 916) the steps will continue until the decision is made. Block 92〇, which will confirm whether this file has data. If the information is not repeated, it will not be compared. If there is data, a write operation will be performed in decision block 936. If no writes have been made, the block 942 step will end with a return error. If a write operation is performed, then at processing block 938 the data will be written to the memory from all ports and a normal switch back is performed at block 940. °° 返回 Please return to the reference decision block 920. If there is no data, the decision block 922 will perform the instruction validity check. In decision block 922, it will be confirmed whether the iteration command is valid. For example, a list of instructions will be confirmed. If the order is not valid, the step will end at block 942. If the command is found to be valid, then at decision block 924 it will be confirmed if the instruction is in the sequence (e.g., if the instruction is in the correct position). If the instruction is not in the sequence, an error will be returned at block 942. If the instruction is found to be in the sequence, then processing is performed at processing block 926. The next block will be confirmed in decision block 928 to see if there is duplicate data in the next. Since the repetition of the data usually involves a pair of defects, the number of defects in the processing block 930 will be increased by two to confirm the next two. Returning to decision decision block 928, if the answer is yes, then in processing block 934, select (single) 埠. The next step will proceed to decision block 932 to confirm if more defects are to be processed. If so, the step will continue to decision block 916. 29 201019120 Right No' will be released in block 94 0. In one embodiment, the data is received and the command is received. The instructions are processed by instruction interpreter 248 (shown in Figure 2), shown here as blocks 922, 924, and 926. The repetitive check is performed at the position indicated by the two triangles 254 (as shown in Fig. 2a), and is represented here as blocks 916, 918 and 920. Figure 10 shows an embodiment of an instruction repetition model 1 100 2, 1004, and 1006. In one embodiment, the instruction repetition is used to improve error detection. Instruction 15 is transmitted twice and the original instruction is compared to the repeated instruction. If one or two of 1002 and 1004 are used, the instructions 1010 and 1 〇 14 are repeated immediately after the original instructions 1008 and 1〇12. If four or more are used, the repeat command 1016 and 1 〇 18 will appear on the other side. The instruction is specifically selected because: (1) in a connection ▲ case ▲, the repetition can be used to fill the unused bandwidth; (2) the misinterpretation of the instruction may result in unanticipated results, such as a violation of the order of instructions (eg , start a library that has been activated, or write to an unstarted library) or destroy a memory location that is not related to the current transmission; conversely, if an instruction is correct, then any bad data is limited to at least the current transmission; (3) Although repeated data can produce better results, the effective system bandwidth will be half, because the free space available for instructions is not available in the data stream. Only "repetition model, 1GG4 卩丨 delete display - a single Γ weight 2 complex = complex link 璋 _ and _ combination. It is more obvious, and how multiple instructions work together can deliver a maximum of two different instructions. At the door [time 201019120 in the single 埠 model 1002, the instructions are issued singly, and their repetition 1010 follows the instruction 1008. For the two models 1〇〇4, the repeat command 1014 is transmitted at the same frame time. Then, if the repetition is turned off, the two instructions can occupy this frame time. For four or more models $, the two (or more) instructions 1020 and 1〇22 can be counted as one frame time, and the two instructions give 1 () 22 can be repeated in the same box time as a heavy t 1〇16 and 1G18. There is no limit to the number of instructions that can be transmitted at the same time or the granularity of the number of 中 in the group. -^ According to the use of models_2, _4 and, it is possible to perform in some cases which will save potential, but it will measure the error, and the wrong result will be available immediately. The purpose of the above is to explain the details in order to provide for the present invention = 2 in the other - some examples, some of the conventional structures; between the components in the figure may contain the second two = description Or the core member may include additional inputs or outputs without the various embodiments of the invention being implemented by hardware components, or may be included in a computer program step, which may be used to generate one-to-one or computer-readable A processor or device having instructions for performing these steps may be a combination of hardware and software:; =: selectively, one or more of the modules described in the specification of the step 31 201019120, _ related to a plurality of host modifications or components, for example, in combination with or in combination with software and/or the like. In an implementation mechanism, a module may include a hardware, a module containing software, 敕== and 1 or a setting, which may be provided via a -machine/electric TM body: f". The article may contain content The machine can access/read the medium to provide instructions, data or other sub-devices (for example, like a filter, a disk-disc-disk controller) to perform the various operations described. And the execution of the action. ❿ ^ Part of the various embodiments may be provided by a computer program product, which may include a computer readable medium having computer program instructions stored therein that can be used to program a computer (or other electronic The device is configured to perform the steps according to the embodiments of the present invention. The machine readable medium may include, but is not limited to, a floppy disk, a compact disk, a CD-ROM, a magneto-optical disk, and a read-only memory. Body, random access memory, erasable programmable read only memory (EPR〇M), electronic erasable programmable read only memory (EEPR0M), magnetic or optical card, flash memory or Other forms are suitable for storing electronic instructions The body/machine can read the media. In addition, the present invention can also be downloaded as a computer program product, and the program can be transmitted from a remote computer to a requesting computer. Forms, but without departing from the basic scope of the invention, the steps of any of these methods may be added or deleted, and the information of the message may be increased or decreased. Obviously, those skilled in the art may modify or modify the information accordingly. The specific embodiments are not intended to be limiting, but to illustrate the invention. The scope of the embodiments of the present invention is not determined by the specific embodiment of 32 201019120, but the scope of the following patent application. It is consumed to the component "B", and the component A can be directly coupled to the component B or indirectly via the component C. when

A book or a claim means that a component, feature, structure, step or characteristic A w is a t-piece, feature, structure, step or characteristic B, which means that "A" at least partially causes "B", but may include At least another component, feature, structure L step or characteristic contributes to "B". It is not necessary to include a particular element, feature, structure, step or feature in the specification. If the instructions in the manual are "fighting, "_ basin only meticulous", it does not mean that eight has only one of the components. Reference is made to "an embodiment of the present invention, which is an embodiment or an example of the present invention. In the specification, a cautionary embodiment" or "another embodiment" means one of the embodiments. Particular elements, features, or characteristics are included in at least one such embodiment, but not necessarily in all embodiments. "U", "Usage", "an embodiment", "some do not necessarily mean all embodiments. It should be understood": , · various characteristics are sometimes group material - single - real - 1 or any of them - Biting more: = Helping to understand the various ideas of the invention. The method can not be interpreted as indicating that the request for the special issue U is more than the stated characteristics in each of the 24 claims. The following claims reflect the idea of the invention. Less than all of the features of the disclosed embodiments. Therefore, it is specifically intended that::: indicates that each request item indicates itself as the invention _ independent implementation = 33 201019120 [Simplified description of the drawings] The embodiments of the present invention are illustrated by way of example and not by the drawings. The component symbols are the same components. Limitation, with the accompanying FIG. 1 showing an RS-232 conventional serial bit configuration, an embodiment of a single-host connection memory; FIG. 2 is an embodiment of a single-host connection of a four-four memory; Figure 2 "Shoulders" - an embodiment of a single host interface connection selection, an embodiment of a smart phone architecture; Figure 2 shows the use of tandem DRAM (SPDRAM) An intelligent telephone rack: an alternative embodiment; FIG. 2F shows an embodiment of a multi-host connection structure. FIG. 2G shows an embodiment of a multi-host interface memory; FIG. An embodiment of a connection control register and a repeat instruction confirmation register for up to sixteen; FIG. 2I shows an embodiment of a connection demultiplexer; FIG. An embodiment of a multiplexer routing table is illustrated; FIG. 2K shows an embodiment of a connection demultiplexer; FIG. 2L shows an embodiment of a connection multiplexer routing table; and FIG. 3 shows a method for frame synchronization. Step embodiment; Figure 4 shows one for power control Step embodiment; FIG. 5 shows an embodiment of a step of performing a single acknowledgment for repeated acknowledgment and instruction interpretation; FIG. 6 shows an embodiment of a step of receiving and decoding a frame in one ;; FIG. Post-decoding block (format) embodiment; Figure 7B shows an embodiment of an instruction, status, and data encoding block; Figure 7C shows an embodiment of a current memory bank and current instructions; Figure 7D shows a write mask And an embodiment of a write command; FIGS. 8A, 8B, and 8C show an embodiment of a write mask model; FIG. IX 34 201019120 shows an embodiment of a step of using multiple scans to repeatedly check and interpret instructions; An embodiment of an instruction repetition model is shown. [Main element symbol description] 100 conventional serial bit configuration 102, 122 stop bits 104, 106, 108, 110, 112, 114, 116, 118 bits 12 0 start Bit 124 value φ I26 into frame bit 128 frame 200 埠 memory 201 camera 202 memory core 203 display device 204 埠 memory system 206, 208, 210, 212 埠❹ 214, 216, 218, 220 ' 222 ' 224 ' 226, 228 external memory interface 230, 232, 234, 236 asterisk 238 power control 240 PLE signal 242 / LPD signal 244 phase-locked loop 246 REFCLK signal 35 201019120 248 instruction reader 250 mode register 252, 254 triangle 256 command signal 258 library signal 260 mask signal 262 solution multiplexer 264 multiplexer® 269 communication channel 270 single host link 271 host 272 NAND flash 273 NOR flash

274 DRAM 275 埠 Link Selection 〇 276 - 埠 277 2 埠 278 4 or more 279

280 smart mobile phone architecture 281 application processor 282 baseband processor 283 SRAM/DRAM 285 SPDRAM 36 201019120 286, 287, 288 multi-host connection structure 289 memory 290 槔 291 memory core 292 multi-host connection 埠 memory 293 The multiplexer 294 demultiplexer 294a prepares the channel 295. The link control register 296 repeats the command confirmation register 297a, 297b. Table 298 enable_fn 299 reads the latency 302, 304, 306, 308. Steps 402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 10 422, 424, 426, 428, 430, 432, 434, 436 Steps 502, 504, 506, 508, 510, 512, 514, 516, 518 , 520, 522, 524, 528, 530 steps 602, 604, 606, 608, 610, 612, 614 step 700 block 702 payload 704 payload index 7 2 0 coding frame format 722 flag 37 201019120 724 instructions 726 mode Register group 728 DRAM instruction group 730 SYNC 732 SYNC2 734 data 736 current library instruction 738 current instruction © 740 write instruction 742 write mask 744 read 746 burst stop 748 pre-charge 750 pre-fill all 752 library Update φ 7 5 3 Memory Library 754 All Library Updates 755 Address 756 mode register read 757 higher column address 758 mode register write 760 mode register write data 762 self-renew power off 764 power off leave 38 201019120 765 lower column address 770 ABNK 772 mask bit 774 memory 776 row address 778 mask 780 selective WMSK instruction 800, 850, 875 model 802, 852, 876 prior to memory contents 804, 854, 878 instruction stream 806, 856, 880 Subsequent memory contents 902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936 '938, 940 steps 1002, 1004, 1006 Model 10 1008, 1012 original instructions 1010, 1014, 1016, 1018 repeat instructions 1020, 1022 instructions 39

Claims (1)

201019120 VII. Patent application scope: 1. A method for reducing the memory potential time, comprising: communicating between a host computer system and a memory via a time interval of one or a group of the memory Information, wherein the brain system is coupled to the memory, the 珲 is one of the group ;; and the host computer system and the memory communicate with the data at a single time interval via the 淳 or the node An instruction. Heart, 阜❿2· The method described in item i for reducing the potential of memory = in the group 埠 (4) can be used in any operation of the memory ^ 3 · as described in claim 1 for lowering Memory latent time::::: The group 埠...occupied by the instruction' and the finger::: Item 3 is used to reduce the memory latency, wherein 1 subsequent ♦ command is like the instruction Communicate in this single time interval. "The method described in Item 1 for reducing the potential of the memory, the eighth is to maintain the group and communicate the instruction - repeat the instruction Λ 3 6. The amount of information of the 201019120 yuan cover information to reduce the communication bit The method of: wherein: the method of claim 6 is for reducing memory latency, '', the mechanism is changeable in a data stream, wherein the same is as described in 8. It is used to reduce the mechanism of writing data without masks in the communication box, and (10) the information in the communication, which is used to reduce the memory latency. The method, wherein the mechanism is automatically repeated in subsequent unit transmissions. 10:=: The method for reducing memory latency, wherein the mask mechanism stops after a soap unit is delivered. The method for reducing memory latency according to the second item 1, wherein the method can be inserted into a write data stream. 12. The use of the item i is used to reduce the memory potential. In the time method, the state information can be inserted into a write data stream. /, 13. A device for reducing the potential of memory, including · host computer system, light to the present, with the wonderful - 祠口主°己隐体, the memory via the 201019120 :» 隐隐One of the itching or a set of time to receive data from the host computer system at multiple intervals, the 埠 is one of the group ;; and ^ U e 'it system (4) modify 'to pass the material or the group 璋 in a single-time The interval is received from the host computer system related to one of the data. The apparatus for reducing the memory latency as described in claim 13, wherein the membership of the group is directly operable at any time during the operation of the memory. 15. The method of claim 14 is for reducing memory. The device of the submersible, the system is modified to receive subsequent instructions of the instruction by maintaining the group (4) not occupied by the finger 7. 16. The method for reducing memory as described in claim 15 wherein the subsequent instructions are as if the instructions were in the single body, wherein the time interval is communicated.装置. The apparatus for reducing memory latency as described in claim B, the memory system being modified to repeat the command by maintaining one of the I/, 中 commands. The sigh is 18. The memory used in claim 17 is used to reduce the potential of the memory, and the memory is modified to implement a concealer, wherein the same communication box in the bedding is prohibited from writing to the unspoken person. Write 匕3 mask information information 42 201019120 It is expected to reduce the number of communication bits and memory 201019120 body time, which = 19 is used to reduce the memory potential of the wear-through "The cover mechanism is Modify to prohibit: the device, wherein the same groove is the same as the write command; j: 曰 φ writes the data that does not contain the mask information. 21. The μ2 is used to reduce the memory potential. The mask mechanism is automatically repeated in subsequent unit transmissions. , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the data stream, the device is inserted into a data stream, and the state information is used to reduce the memory potential. A system for reducing memory latency, comprising: - a host computer system coupled to a memory The memory uses a link system to reduce the memory latency. The system contains a plurality of 43 201019120 埠 to communicate data and instructions, wherein the plurality of 埠 or more can be linked to one or The plurality of sets of ports are configured to: communicate data between the host computer system and the memory via one or more of the time intervals of the memory, the system being the group And one of the instructions relating to the information is communicated between the host computer system and the memory via the ########. In the system for reducing the potential of the memory, the membership of the group in the group can be used at any time during the operation of the memory r\T — * 27·=: claim 25 for reducing the memory potential The system two-car connection system has been modified to communicate the subsequent instructions of the instruction by maintaining the material. 28·If the π-item 25 material is reduced, the memory material is followed by the instruction. Communicate in the single-time interval, The second: the system used for / low memory latent time, its t communication changed 'to maintain the group of itching humble 30. As requested, 23 used to reduce memory potential J, the system , where 44 201019120 the link system is the same as the communication frame in the same communication box, the number of communication bits is reduced by a masking mechanism, so as to write the data without the mask information as the data is written, Memory potential. 31. As requested in Item 3, +, which is used to reduce the memory latency, the mask mechanism is am Α + τι糸, where the cargo J changes in the lean stream. 3 2. If the request item 3 丨 、, +, 〇 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Masking - U has been modified to prohibit access to information such as the instructions of the writer. 3. Two: The method described in Item 32 is used to reduce memory. The mask mechanism is modified to the forester's system, in which the same communication box is written to 匕g as if the write command was not included. Mask information. ❹34:: referred to in item 33 for reducing memory potential", the mask mechanism is automatically repeated in subsequent unit transmissions.,, wherein 35. month claim 25 is used to reduce memory latency. The system can be inserted into a write data stream. 45 201019120 37. The system for reducing memory latency according to claim 25, wherein the state information can be inserted into a read In the data stream. 46