TWI467381B - Method, apparatus and system for reducing memory latency - Google Patents

Description

Method, device and system for reducing memory latency

Embodiments of the present invention generally relate to the field of computer memory, and more particularly to improvements in serial communication memory latency and reliability.

In a memory system using a high-speed serial interface, a host (such as a system integrated chip, a computer, a graphics controller, or the like) or a plurality of hosts and memories are transmitted between the host and the memory to transmit instructions and data. Expect to provide maximum bandwidth combined with error detection to ensure proper system operation.

Serial Link has an inherent Latency because it only transmits one bit at a time. In addition, the serialization and deserialization steps will create additional latency. The use of these tricks alone does not significantly improve the latency, so a special access method (such as accessing different, dedicated memory regions, such as Striped Accesses) from various ports to improve bandwidth. By initiating Port Binding (using a consistent number of ports), the memory latency can be reduced by simultaneously transmitting data containing many bits, which increases the bandwidth without the need for a formatted access method.

Memory also requires a certain amount of data security. For example, in a series of channels, an undetectable error may occur unless a method that results in unacceptable latency is utilized. In the case of a link, some defects are still idle during the command period. In those same periods, the unused bandwidth is filled with repeated instructions. This method can be extended to a single 埠 with temporal repetition to provide the characteristics of the 埠 structure.

Figure 1 shows a conventional serial bit configuration 100, according to the EIA standard RS-232-C. In the figure, the serial transmission of the data is similar to an RS-232 connection, in which the individual two-bit values (bits) 102 are observed by taking turns to observe them one by one and assigning them different values in the value 124. Up to 118 can be combined into an overall value of 124. For example, if its first bit is 104 and is specified as the Most Significant Bit (MSB) of the value 124, then the second bit 106 and others, etc. (such as the bit 108, 110) , 112, 114, and 116, etc., until the Least Significant Bit (LSB) is filled in the last communication bit 118. The combined value in this example is referred to as a frame 128, which contains a value 124 and stop and start bits 102 and 120. In addition, block 128 is described with additional bits, referred to as Framing Bits 126, which includes start bit 120 and stop bit 122, making the receiver available to find the beginning of block 128, and Confirm when the expected frame arrives. In other architectures, even when the data rate between the transmitter and the receiver is slightly different or changed, the framed bit 126 can be utilized to facilitate the receiver to reliably look for individual bits.

Communication across the various serial links to the memory will cause significant latency, and providing more than one host access to a single memory will complicate the memory resources. In addition, the memory may have one or more ports, each including a serial transmitter, a serial receiver, and associated circuitry to improve latency and bandwidth. In the case of Bound Port Situation, some defects are still idle during the instruction. In the same period, the unused bandwidth will be filled with spatially repeated instructions, and this method can be extended to a single 利用 with time reproducibility over different periods to provide all the features of the 埠 construction. In the case of a link, the data is transmitted in multiples, but the instructions must be able to run independently. First, unused commands may contain duplicate commands (Command Duplicates). Second, some instructions may be posted at the same time. In addition, because of the serialization of error management, deserialization, framed data, and additional steps such as synchronization, tandem communication increases latency in parallel communication.

Therefore, the industry needs to introduce and implement technologies that reduce memory latency.

The invention discloses a method, device and system for improving the communication latency and reliability of the memory.

In one embodiment, the present invention provides a method for reducing memory latency, comprising communicating between a host computer system and a memory via a time interval of one or more of the memories. Information, wherein the host computer system is coupled to the memory, the UI is one of the group; and between the host computer system and the memory via the UI or the group Communicating instructions related to one of the materials at a single time interval.

In one embodiment, the present invention provides an apparatus for reducing memory latency, comprising a host computer system coupled to a memory, the memory being located via one or a group of the memory Receiving data from the host computer system at a plurality of time intervals, the 埠 being one of the groups; and wherein the memory system is modified to pass from the 埠 or the group at a single time interval from the The host computer system receives an instruction related to one of the materials.

In one embodiment, the present invention provides a system for reducing memory latency, comprising a host computer system coupled to a memory, the memory using a connection system to reduce memory latency, The 埠 link system includes a plurality of 埠 to communicate data and instructions, wherein the plurality of 埠 two or more 可 can be linked into one or more sets of 埠, the 埠 link system is used to: via the memory One or a plurality of time intervals for communicating data between the host computer system and the memory, the lanthanum being one of the group; and via the 埠 or the group Communicating an instruction related to the data between the host computer system and the memory at a single time interval.

Embodiments of the present invention generally relate to improvements in serial communication memory latency and reliability, however, they are equally applicable to other forms of interface, such as High-Speed Parallel.

The term "memory" as used herein means a component in a computer system (see Figures 2D and 2E) that is responsible for extracting previously stored data for use in any Host. (such as a computer processor) or peripherals (such as a keyboard, monitor, video camera, mass storage device (disk, CD, tape, etc.), network controller, or wireless network). In general, a memory system is coupled to one or more microprocessors that process data in a computer system. The data can be stored in a memory by a host, such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), flash memory (Flash). ), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), Electronically Erasable Programmable Read Only Memory (EEPROM) or, for example, pre-determined read-only memory ( ROM). The host can access the memory directly via a bus (such as PCI) or via an intermediate memory controller. Serial access to memory involves the conversion of a single sequence of electronic signals through a single circuit and the conversion of meaningful instructions and data to and from a memory (similar to the RS-232 shown in Figure 1). The circuit that performs the conversion is called "Port".

In an embodiment, in order to reduce the latency of the memory, a Masking Scheme is used, so that the writing of instructions and data can be described without including the masking information in the same Communication Frame. To reduce the number of bits and latency in the box. In addition, in order to reduce latency, a memory-based protocol is provided to reduce the latency of shorter frame sizes to provide greater flexibility and reduce the increase over the old DRAM protocol. The instruction group changes when the bandwidth is wide.

FIG. 2A shows an embodiment of a single host interface memory 200. In the embodiment, the link memory 200 includes a memory core 202 (such as DRAM or flash memory), which includes a plurality of banks (such as eight banks) and is connected to the link of the memory port 200. Memory system 204. The memory of the memory core 202 is communicated in many ways, such as four 206 to 212. All four 206 to 212 operate together to provide an interface to a single host with a variable frequency. These memories are used independently, such as reading from one memory and writing from another memory at the same time. The memory core 202 can also include a memory read bus to read data and a memory write bus to write data. However, there may be a single connection in memory core 202 that can read and write data. In addition, the link memory system 204 includes a link multiplexer 264 and a linker multiplexer 262, which will be described in FIG. 2K and II, respectively.

In the prior art, the transmission of all instructions and data bits is immediately transmitted to each parallel line, which simultaneously arrives at the time of code formation. However, as the speed gets faster, the data flowing through these lines may be sampled incorrectly or at the wrong time (for example, using the relevant clock signal). In order to solve the high-speed sampling problem, a self-sampling serial signal is used (譬 RS-232 as shown in Fig. 1). However, the parallel approach will increase the latency as its data is processed on time. In one embodiment, the communication latency and reliability of the serial port and the memory communication utilizes a plurality of serial interfaces or groups of Duplicating Commands, which may be consecutively or temporally. Or at the same time or in space. Embodiments of the technology are described herein and implemented using a single host-connected memory 200.

In one embodiment, a transmitter (Tx) can convert sixteen bit parallel data into a serial bit stream and transmit the single bit stream. A receiver (Receiver, Rx) can receive a sixteen-bit single stream and convert it into a parallel stream. In this example, a region of memory can be thirty-two bits wide and at about the same rate. In the memory 200 of the figure, four cells 206 to 212 are used, so each channel between 206 and 212 has a 128-bit data motion, along with a data string of sixty-four bits. Stream (for example, sixteen bits multiplied by four turns equals sixty-four bits for each channel). This one hundred and twenty-eight-bit motion system is supported by the necessary circuitry in the chip.

Different from the prior art, each of the ports 206 to 212 in the embodiment utilizes a serializer/deserializer to serialize and deserialize the data stream at a faster rate. For example, a Phase Locked Loop (PLL) (譬 244) can be utilized to multiply an input clock by a higher rate to match the input data rate used to sample the bits. Although the time at which the data stream arrives at 埠206 to 212 may be slightly different, it can make these data streams flow faster. In other words, each stream flows at the same speed and at a much faster rate (ie, each data stream can flow at the same rate as other data streams; however, each data stream can be set to flow earlier than it. The rate is faster). In addition, the timing of the elements may not be perfect, but it is not necessary to align these bits because the actual arrival time of these bits does not affect. Therefore, instead of synchronizing the bits at the pin, the bits are synchronized after deserialization in each of the ports 206 to 212. For example, as indicated by asterisks 230 through 236. Similarly, after deserializing these turns 206 to 212, the flow rates of the data bits at or near these asterisks 230 through 236 are compared to the high speed external memory interfaces 214 through 228 (representing Tx0, Tx1, Tx2, Tx3, respectively). Rx0, Rx1, Rx2, and Rx3) (for example, two hundred and fifty picoseconds) may be twenty times slower (e.g., five nanoseconds). In one embodiment, the ports 206 to 212 are capable of phase detection, data bit management, data bit sampling, and lane alignment.

Instruction interpreter 248 continues to process instructions in accordance with the associated/closely related instructions of the channel configuration (further described in Figures 2C, 7C, and 7D).

240 denotes PLE signal, 242 denotes /LPD signal, 246 denotes REFCLK signal, 250 denotes mode register, 250 denotes command signal, 252 denotes triangle, 258 denotes library signal and 260 denotes mask signal.

FIG. 2B shows an embodiment of a single host link 270 of four memory 200. The connection 270 of the memory 200 to a host 271 is shown in the embodiment. The host 271 performs a read and a write operation at a time. Serial Port Memory Technology (SPMT) defines groupings together to form a broad data communication. The number of 埠206 to 212 can be dynamically selected in a link group. For example, a single 埠 or any number of enthalpy (such as the number of powers of two) may be combined to provide 埠 206 to 212. When fewer turns are used, fewer pins and less power will be used. When more 埠 is used, the bandwidth is increased and the latency to obtain the same data is reduced. The number of links can be changed at any time.

Figure 2C shows an embodiment of a connection selection 275 for a single host interface. 276 denotes one (available for sixteen-bit access and a single instruction), 277 for two (a 32-bit data access and 32-bit instruction or instruction repetition), and 278 for four Or more (available for 64-bit data access and 32-bit instructions and repetitions at the same time). When two or more links 277 and 278 are linked, the data is passed to all the cells in the group and effectively multiplied by the data bandwidth. However, individual instructions may only need one 埠, leaving the rest unused. Therefore, in order to avoid wasting bandwidth, improving memory operation and storing instruction bandwidth, a set of closely related instructions or accompanying instructions (Adjunct Command) is provided. These instructions correctly use the extra bandwidth so that it is not wasted, and such closely related/affiliated instructions can be posted before or after an instruction and can be issued simultaneously with the rest. For example, when an Active Command (ACT) is issued, the current library command (Active Bank Command, ABNK) can be simultaneously issued as an attachment to complete the instruction. Similarly, a Write Mask Command (WMSK) can be accompanied by a Write Command (WR). All instructions are accepted at 埠0, but related dependent instructions can be received by other 埠 to preserve the instruction bandwidth. The commands ACT, ABNK, WR, and WMSK are further described in Figures 7B through 7D for reference.

In addition, a single option can initiate a repetition of instructions to improve error detection to avoid erroneous instructions from abnormal memory operating conditions. When this option is enabled, a single 埠 will be compared to Duplicate for one of the instructions in the first box and the subsequent box. When two or more 埠 277 and 278 are linked and used, no additional bandwidth is required for repetition because the repetition is displayed at the same time at the same time. Although the instructions are repeated, the material is not repeated in this embodiment. When there are at least four links 278, it will be possible to use both repeat and attached instructions.

Figure 2D shows an embodiment of a smart mobile phone architecture 280 comprising a baseband processor 282 and an application processor 281, and individual volatile memory (e.g., DRAM 274, SRAM/DRAM 283), non-volatile Sex memory (such as NAND 272 and NOR flash 273) and communication channel (shared memory) 269 are located between the two processors 281 and 282. Memory 272 to 274 and 283 are used to store and receive executable code and maintain privacy information that is not shared by the connected processor. Any sharing or communication is performed by communication channel 269. The application processor 281 can be coupled to other peripheral devices such as the camera 201 and the display device 203.

Figure 2E shows a smart mobile phone architecture 284 for the selected embodiment of Figure 2D, which includes SPDRAM 285. In one embodiment, the memory is shared between the baseband processor 282 and the application processor 281. In one embodiment, SPDRAM 285 can be used to communicate baseband processor 282 and application processor 281, store code and data for both processors, and reduce the number of memory elements or technologies needed to implement the architecture. In addition, the number of connections between the memory and the processor can be reduced, including the exclusion of specific communication channels. In one embodiment, a segmentation is provided such that some hosts have access to some of the memory while others are not. This allows the memory device to be shared in a secure environment, such as for a baseband software. For example, the application processor 281 can load the baseband software image into the SPDRAM 285 and instruct the baseband processor 282 that its image is in place. The baseband processor 282 will then remove access to other hosts and confirm the validity of this image. If it is correct, the baseband processor 282 can continue to operate from the image without having to split with the software running on the application processor 281.

Figure 2F shows an embodiment of a multi-master connection configuration 286, 287, and 288. In an embodiment, multiple host functions may be utilized in conjunction with multiple connections. For example, if a host (such as an application processor 281) requires more bandwidth, it can utilize many of its interfaces, while other hosts can continue to use a single port. In the embodiment diagram, some combinations 286 (two independent hosts, dual/hosts), 287 (two independent hosts, host 1: single port, host 2: double ports) connecting a plurality of hosts on a four-inch device are provided. 288 (four independent hosts, one host per host). For example, in combination 286, the interfaces of hosts 1 and 2 correspond to two turns, respectively. In combination 287, the interface of host 1 corresponds to 埠0, and the interface of host 2 corresponds to two 埠 2 and 3. In combination 288, the interface of each host corresponds to a single frame. It can be understood that any combination of host connections or interfaces can be provided in an embodiment, for example, a single host can connect all four ports together. The actual corresponding to the host depends on the setting of the scratchpad, which gives the length of the link group.

Figure 2G shows an embodiment of a multi-host interface memory 292. The multi-host connection memory (multi-host memory system) 292 in the figure includes four 290s and is communicated to a memory core 291 including eight memories 289. For the sake of brevity, only a limited number of files 290 and memory 289 are displayed. Although the multi-host memory system 292 is similar to the single host memory system 204 of FIG. 2A, the data from each of the ports 290 is available to each bank 289 individually. In this embodiment, memory bank 289 is defined as part of an overall multi-master memory system 292 that can track data transfers independently. Moreover, by providing individual accesses, a single frame during the command period 290 can be associated with a single memory bank of memory bank 289 and does not conflict with other ports accessing other memory banks. The multiplexer 293 and the multiplexer 294 are multiplied to create a possible embodiment of a crossbar switch to direct data between the memory banks 289 and 埠 290.

Figure 2H shows an embodiment of a 埠 link control register 295 for up to sixteen ,, and a repeat command acknowledgement register 296 for up to sixteen 。. For the sake of brevity, the linkages employed in the embodiments occur in a continuous number of multiples of multiples (such as 埠 1, 2, or 4), and with the matching criteria (Matching Modulus) (eg, 埠0 corresponds to four 埠, 埠0 or 2 corresponds to two turns, or any 埠 corresponds to a single 埠).确认 You can confirm the identity of a link group based on the settings of the register. The figure shows a control register 295 that combines the sixteen 埠. This link describes and provides a hierarchical mode, so if no bits are set, all ports will operate independently. For the two devices, only bit 0 is used, and for the four devices, bits 0 to 4 describe the possible links, by adding the remaining two for the four, and linking all port. For the gossip device, the remainder of the two links are located at bits 8 through 11, the four links are at bits 13 and 14, and all turns are at bit 15. This mode can continue without restrictions.

In addition, 埠 may not belong to a link group, in which case they operate independently.埠 may not be part of a connected group and may operate individually, or they may be part of more than one connected group. One technique for dealing with this conflict is to select a particular maximum connected group. When the scratchpad 295 is used to add a link group, the next command is then used in the content of the link group, and there is no need to issue a new command until a new one is ready. When a trip is removed from a link group, it may be stopped or immediately used alone.

In addition, in the embodiment, each bit is allocated to a register to initiate a Duplicate Command confirmation, and the repeat instruction acknowledgment register 296 is shown in the figure. If a group is linked to any group, it will confirm its continuous command value. If it is not linked to a group, it will find duplicates in its continuous cycle.

FIG. 2I shows an embodiment of a linked demultiplexer 294. In one embodiment, Port Ready Lanes 294a (e.g., port_rdy lanes) are generated by individual ports 290 and are given a link command. For example, when the four 290s are linked, all of the preparation channels 294a will be issued. However, if only 埠2 and 3 of 埠290 are linked to the two groups, port_rdy[3:2] of the preparation channel 294a is issued. Similarly, if 埠1 is operated alone, only port_rdy[1] is issued. This technique is used to confirm the transfer size and routing of the correct read preparation channel 294a from 埠290 to memory 289, as well as the creation of overall memory characters for storage of latches.

Figure 2J shows an embodiment of tables 297a and 297b showing the route to the demultiplexer. For example, when the data arrives, the demultiplexer routes the data to the correct channel according to the routing function table 297a. The demultiplexer register then functions to capture the data for the memory into the correct channel according to the function of enable_fn (298 in Figure 2I), as shown in Table 297b. Once all the data has been shackled, its core stores the data with enable_fn 298 using wr_strobe.

With a parallel data path, write masking can be achieved or storage of selected data can be disabled. At the beginning of the storage cycle, all masking is set according to enable_fn (for example, all channels are disabled). When the data arrives, the associated mask is routed and stored with the data. If not all of the data arrives (such as an interruption or a Short Transfer), only the arrival data will be stored, as the data channel has not arrived so there is no opportunity to clear the relevant mask.

Figure 2K shows an embodiment of a coupled multiplexer 293. In one embodiment, the 埠 preparation (such as port_rdy) 294a and the read command (such as read_cmd) are delayed by 299 from the memory read latency (RL), such that the memory (and shackles) The arrival data can be selected immediately for output 埠290. Such a choice is simply achieved by using a delayed output value. The port_rdy channel 294a from a read command is interpreted by the multiplexer 293, similar to the interpretation of the demultiplexer 294. The multiplexer select channel is mapped to output 埠 290, which is based on the functions shown in Table 279 of Figure 2L.

For the sake of brevity, take the possibility of transmitting a (64-bit) data character from memory to each cycle with a chance of storage or delay to reduce the data rate to cover a single frame. If more cycles are required to obtain the data than the output cycle, a core is created with a "Pre-Fetch Buffer" that carries a larger character from the memory and Select a shorter segment across consecutive cycles. In this case, the shackles of the data can be linked to the pre-fetch buffer. To throttle the data, the instruction interpreter can split the read instruction into shorter quantities and issue intermediate instructions at a lower rate to match the output rate.

Figure 3 shows an embodiment of a step for frame synchronization. Initially, the memory system turns off power to reset 302. In order to turn on the power, the Link Power-Down (LPD) is driven to the high position 304, making /LPD equal to zero and stopping the 埠. However, when /LPD is equal to one, then block search 306 is initiated to find the particular code or bit order called SYNC. When SYNC is detected, the step proceeds to an operational mode 308. This step can continue with multiple (if implemented), as shown in Figure 4.

Because the host and the memory exchange data in tandem, the receivers are synchronized to confirm the bit position correspondence in a frame. To confirm proper synchronization, the link searches for a particular sequence of bits in the "Frame Search" case 306. For example, initially the tandem link transmits one of two sequences of synchronization bits: SYNC and SYNC2. The physical layer (Rx-PHY) of the transmitter can detect these framed data packets by using the host and the memory. SYNC plays a key role in Link Bring-up after a reset or error. In addition, in normal operation, the memory Tx-PHY will transmit SYNC in any unused box. In normal operation, the host Tx-PHY will transmit SYNC or SYNC2 in the unused box. When SYNC is detected and recognized from the memory, its steps proceed to normal operating mode 308. If the frame fails, such as indicating a twentieth decoding error, then for example the memory will switch back to the "box search" case 306 until SYNC is detected again. In any state, if /LPD goes to zero, it means that 埠 will switch back to the "Link Down" state 304 and start over.

The memory transmits SYNC2 to indicate an error in receiving the host data, or because a "link closed" status or a framed error is left. The host responds exclusively by sending a SYNC until the memory is re-established into a frame and begins transmitting SYNC. The host transfers SYNC2 between instructions for proper error recovery operations. The SYNC and SYNC2 setup and reply connections are framed, and the host schedules the establishment of a coordinated link.

Figure 4 shows an embodiment of a step for power control. Its reception / LPD. At decision block 402, it is determined if a turn is on. The slash before the /LPD indicates the inverse logic. For example, if the link is powered off when /LPD is equal to zero, indicating that its power is not on, the step will proceed to block 412 to stop the master. Similarly, /LPD equals one to indicate that the power is not off, indicating that it is power on. If /LPD is equal to one (e.g., the connected power is on) then a training step is performed, and at processing block 404, a box is sought for a particular code or sequence of bits (e.g., SYNC). The training step for the SYNC search will continue until SYNC is detected, and then at processing block 406, its steps will enter an operational mode. This step will be further described with respect to Figure 3. At decision block 408, a confirmation is made as to whether there is an error. If so, the step will continue to decision block 402. If not, then at decision block 410 it will be confirmed if more 埠 are successively entered into the operational mode. If no other defects are added, the steps will continue in the operational mode of processing block 406. However, if additional defects are detected, the steps will continue to process block 414 to train the new one.

These additional (multiple) tethers are processed in processing block 416. The use of multiple uses is also described in Figure 9 for reference. At decision block 418, an error will be confirmed. If an error is confirmed, such as in the decision block 430, the error is caused by the power being turned off (e.g., /LPD = 0). If so, all blocks will be stopped at processing block 432 and the steps will advance to a single mode of decision block 434. If /LPD is not zero in decision block 434 (e.g., /LPD = 1), then all blocks will be trained at processing block 436 and the process will continue to processing block 416. Referring back to decision block 430, if /LPD is not zero (e.g., /LPD = 1), then the step will proceed to the training error 处理 in processing block 428 and further to processing block 416.

Returning to decision decision block 418, if no error is found, then in decision block 420 it is additionally determined if there are more 埠 joins. If so, the step will continue to the new training step of processing block 414 (e.g., looking for the new SYNC). If no additional defects are turned on, then at decision block 422 it will be confirmed whether any defects have been removed. If no, the step will continue to processing block 416. If so, any blocks that are removed will be stopped at processing block 424. Here, at decision block 426 it will be confirmed if a single defect is available to switch back to the single mode. If so, the step will continue to the single mode of processing block 406. If not, the step will continue to the multi-mode mode of processing block 416.

Power control 238 (refer to Figure 2A) is responsible for the transfer / LPD, while 埠 206 to 212 is responsible for training itself and the processing in Figures 3 and 4.

Figure 5 shows an embodiment of the steps of repeated confirmation and instruction interpretation using a single frame. More complex steps using multiples will be shown in Figure 9. As further described in FIG. 5, at processing block 502, the receiving, reading, and decoding of data is performed at a time (eg, first or main) to begin the first block. At decision block 504, a confirmation is made as to whether a 埠 error has been detected. If an error is detected, block 528 will return the error with one to end the step. If no error is detected, a decision block 506 will confirm whether to enable the repeat. It should be understood that its repeated visual necessity and needs are turned on or off. If the repetition is turned on, the step proceeds to the data reception, reading, and decoding of the step block 508, which is performed immediately after the second frame. Again, at decision block 510, a confirmation is made as to whether a false error has been detected. If so, the step will end with the error back to block 528. If not, the step will continue to block 512 to confirm if the first box is equal to the second block, and if so, the step will continue to block 514, and if not, the step will continue until block 528 ends with an error turn back.

If no error is detected (and no repetition is turned on, return to decision decision block 506) and the step will continue to confirm if the box is an instruction or data. If the box is an instruction, then at decision block 516 it will be confirmed if the instruction is valid. If the instruction is invalid, the step will end with block 528 turning back with an error. If the instruction is valid, then at decision block 518 it will be confirmed if the instruction is in the sequence or if it is in the correct location. If the instruction is not in the sequence, the step will end at block 528 with an error back. If the instruction is in the sequence, the processing block 520 will process the instruction and at block 530 the normal will be posted back.

Returning to decision decision block 514, if the box is data, then at decision block 522 it will be confirmed if the memory is ready for write operation. If not, the step will end at block 528 with an error back. If so, the data in processing block 524 will be written to the memory and the step will end at block 530 and then return to normal. In this embodiment, the steps of blocks 516, 518, and 520 are performed in instruction interpreter 248 of FIG. 2A, with the remaining steps being performed in FIGS.

Figure 6 shows an embodiment of the steps for performing various functions in the UI. The step of receiving, reading, and decoding the data stream is provided at block 602. For example, a single stream of data (in bits) is received via Rx, and a parallel stream is formed as shown in the figure and then decoded (eg, using 17B/20B decoding). Use the Connected Power Off (/LPD) signal to control all of the power (via the power control mechanism), allowing power to enter and out of a single host to connect all of the memory, as shown in Figure 2A (Figure 2A) The dotted line indicates the power control of /LPD). At decision block 604, it will be confirmed if /LPD is equal to zero. If zero, the step will end at block 614 with a return error. However, if /LPD is not equal to zero, the step will continue at processing block 606.

At processing block 606, a data frame is received that contains 埠 to receive a bitwise data stream and to generate a parallel stream of frames (e.g., twis de-serialization). The block is decoded at processing block 608 (e.g., using 17B/20B decoding techniques) to then generate valid data. The validity of the check box will be confirmed at decision block 610. For example, it will be confirmed if the box has a tweetal code and is correctly decoded as a seventeen bit value. If the conversion fails, its validity will fail because it is not clear that it has not produced any results, and an error is returned at block 614. However, if the conversion is successful and a result is produced, the data frame will be considered valid and will be returned normally at block 612, as will be further illustrated in FIG.

Figure 7A shows an embodiment of a 17-bit post-decoded block format 700. A seventeen-bit decoding block 700 of the embodiment diagram can be used to transfer seventeen-bit data, instructions, and/or states, and is transcoded to produce a twematon box for serial transmission. Data, instructions and status are transmitted and received in a twentieth box. The opposite step will be performed when receiving, where the twematal conversion coding frame is decoded to produce a seventeen bit box 700 to hold the data, instructions and status.

The seventeen-bit post-decoding block (format) 700 shown in the figure contributes the first sixteen bits to the Payload 702 and contributes the last bit (ie, the seventeenth bit) to the payload indicator. 704. The memory access format is based on the basic decoding format. For example, bit sixteen 704 may indicate that its payload is set to one or zero for use in data, instructions, or status. On the basis of the box-to-frame, instructions and write data can share their recipient links. To reduce latency, instructions can be inserted (or prioritized) into a write stream to delay completion of the write command.

FIG. 7B shows an embodiment of an instruction, status, or data encoding frame format 720. Embodiments of the figures include, but are not limited to, an embodiment of a serial, DRAM (SPDRAM) instruction, status, and data encoding block 720. The seventeen-bit encoding block 720 in the figure is extensible, which provides flexibility to retain multiple bits, and additional instructions can be added in the future (for example, depending on technology or demand). For example, flag 722 and secondary instruction 724 occupy seven bits (bits zero through seven) before block 720, and because most of the items in secondary instruction 724 are one, this region (including flag region 722) Additional instructions (e.g., up to sixteen instructions) may be added in the future to expand block 720.

Similarly, there are other areas with a limited range (such as mode register group 726), which can also be used for additional instructions (such as the sub-instruction area of mode register group 726, which contains only three instructions). Another such area is the DRAM instruction group 728 (e.g., the sub-instruction area of the DRAM instruction group 728, all of which is one), which can be used to add other instructions.

The SYNC 730 controls and maintains the link frame synchronization, while the SYNC2 732 represents a specific link operation state. Both SYNC 730 and 732 are further described with respect to Figures 3 and 4. The data (frame) 734 contains a seventeen-bit box similar to the data box 700 shown in Figure 7A, which includes the seventeenth bit set to one and the next two octets. The current library instruction (ABNK) 736 and the current instruction (ACT) 738 will be illustrated in Figure VIIC. Write command (WR) 740 initiates a memory write cycle for a particular bank and column. Write mask (WMSK) 742 sets an octet byte mask for writing instructions in the step and has any effect with WR instruction 740. WMSK 742 will be further illustrated in Figure 7D for reference.

Read (RD) 744 represents a read command to initiate a memory read cycle, and Burst Stop (BSTP) 746 represents an instruction to interrupt a current read or write. Instructions, and are based on the specific library. Precharge (PCG) 748 represents an instruction to precharge a particular bank of instructions, and Precharge All (PCA) 750 includes an instruction to precharge all of the banks simultaneously. Per-Bank Refresh (REFB) 752 allows specific memory banks to be automatically updated, and All-Bank Refresh (REFA) 754 updates all memory banks based on an internal counter. All banks are in the precharge state before the REFA instruction is issued.

Mode Register Write (MRW) 758 represents an instruction to perform a write to a mode register. The Mode Register Write Data (MRD) 760 provides write data following the MRW instruction 758, in the next intermediate block, from 埠0, and in the form of an MRD instruction 760. Mode Register Read (MRR) 756 represents an instruction to perform a read from a mode register. The Self-Refresh Power-Down (SPRD) 762 will cause the memory core to immediately enter the self-renew state. Power-Down Exit (PDX) 764 represents an instruction that is issued to leave the self-updating power off and to wake up the memory core after the connection is established.

Figure 7C shows an embodiment of ABNK (埠0(ABNK)) and ACT commands 736 and 738. In order to transmit two or more instructions at the same time, they will be able to support each other's functions or functionality to be orthogonal. The third standard involves complexity because Memory Semantics or implementation decisions can fail due to orthogonality. For example, a serial DRAM can include an instruction to initiate a memory and its column address to be initiated is too long for the frame. In a single case, this command would require a box of two or more, but for a link, it could be communicated in a box of time on top of two or more.

For example, ABNK 736 sets the higher five bits of target memory 753 and column address 755 for subsequent ACT instructions 738. The ACT instruction 738 is passed to the memory bank 753 specified in the last ABNK instruction 736. If two or more links are linked, a selective ABNK 736 instruction may appear on the second. The lower fifteen-bit 765 of the column address is assigned to the least significant fifteen of the ACT instruction 738, and the most significant five-bit element is assigned to the lower five bits of the last ABNK instruction 736, or appears ABNK 770 of Yu埠2. This embodiment indicates that instructions 736 and 738 can operate independently at any time in subsequent frames. This provides a variable group size, a general controller that is independent of the group size, and a semantic fit across the links. Additionally, instructions 738 and 770 are complementary to each other and can be executed simultaneously. In addition, 757 represents a higher column address.

Figure 7D shows an embodiment of a WMSK and WR commands 742 and 740. Figure 7D shows a WR command 742 and associated byte/write mask 742 for selective writing. WMSK 742 represents an instruction that is set to an octet mask 772 for the WR instruction 740 in the step and follows the WR instruction 740 to have any effect. After communicating the octet data, mask 772 restarts the next octet. The letter "H" in the mask 772 represents the high byte of the character conversion (such as bits 15 to 8), and the "L" represents the low byte (such as the bit 7 to 0).

WR instruction 740 initiates a memory write cycle to designated memory bank 774 and row 776. Once the WR command 740 is transmitted, the data will be written successively. If two or more links are linked, a selective WMSK instruction 780 is transmitted to 埠2, covering or obscuring the first octet (778). Mask 778 repeats every eight bits unless it is reset by a subsequent WMSK instruction. Other embodiments of the two or more links include a combination of simultaneous reading and writing, or simultaneous activation and writing, according to the semantics of its memory and interface.

8A, 8B, and 8C show an embodiment of writing mask models 800, 850, and 875. For memory using serial communication, reducing the number of bits of Indivisible transmission is used to reduce latency. An indivisible transmission is defined as a box or character length in bits that describes an overall amount of data (such as a tuple) or an executable instruction that contains any intermediate metadata that needs to be completed, such as " Write" and the target address.

For most memory, the write operator contains both the WR instruction, the address, the operator (in this case, the mask), and the write data. For faster memory devices, the speed at which the instructions need to be described becomes too high, so a burst transfer will be utilized. The burst transmission system starts with the instruction and the start data, but continues with the data stream and subsequent calculated addresses (such as increments). Whenever the data is transmitted, it is accompanied by an additional write mask indication signal.

Because instructions and addresses may be necessary for non-contiguous data transfer, the encoding of instructions, addresses, write masks, and data may be inefficient with serial communication. In this case, the data will be transmitted using the WR order and address to deliver the data. In order to reduce the latency, writing masks or WMSK instructions (such as one-bit per-bit tuple) only need to accompany the data that was not stored when the location value was written in the burst. While such optimization can be critical to serial interface efficiency, this mechanism can be used to reduce the required bandwidth in the parallel memory interface. Since the serial interface improves the utility of multi-host memory, by placing a write mask into the instruction stream, each host can use an independent write mask for independent transfer. In order to reduce the inclusion of WMSK companion data to reduce the latency, a three-purpose model will be used and described in the burst.

FIG. 8A shows an embodiment of a repeat mode WMSK model 800. It includes the previous Memory Contents Before 802, the command stream 804, and the following Memory Contents After 806. In the figure, the WMSK is repeated for each transmission, for example, only the red value is changed in the rectangle containing the red, green and blue data, the other two colors will be obscured, and the WMSK will repeat across all three primary colors in this rectangle. FIG. 8B shows an embodiment of a start and end WMSK model 850 that includes previous memory content 852, instruction stream 854, and subsequent memory content 856. Here, the write mask is only used for the initial portion of the transfer. For example, the network packet may start at an odd (Odd) transfer boundary (the second byte of the transferred four bytes) to optimize access (alignment) to the remaining data structures in the packet. Once the start mask is exhausted, the entire remaining packet data will be written to the memory. In order to complete the transfer, a new WMSK will be inserted to trim the last two tuples. FIG. 8C shows an embodiment of a WMSK model 875 that utilizes a multi-serial interface for repeating mode, including previous memory content 876, instruction stream 878, and subsequent memory content 880. Here, the WMSK is used for a single transmission to select a data structure among the transmission sizes. For example, only the second byte is written in an integer of thirty-two bits.

Regarding models 800 and 850, the write mask is reused or infrequently used. For example, various forms of transfer (such as cache writes and mass storage transfers) do not require masking. In these cases, it is inefficient to include a write mask in the material because it is unused most of the time. A transmission that is equally small or small compared to a cell transfer does not achieve the advantages of burst transmission, so data, instructions, addresses, and write masks are specified. Such short transfers typically occur in internal cache memory to mitigate the tendency of bursts of memory from such common operations.

Note that in the assumptions in models 800 and 850, the write mask contains data, but to obtain the advantages of burst transmission, it is not sufficient to link the write mask to the instruction. In this case, decoupling of the write mask transmission from the instruction and data can be understood as a new instruction. In a single serial stream containing an inseparable transfer (box), the write command is posted to the address in its box, and its data stream is addressed to a block sequence for the memory being computed. The write mask is described as a separate instruction and is applied to the unit burst to be published after the write command and in the desired material. A unit burst is defined as the number of bits that are used to implement a single write mask bit multiplied by the number of write mask bits in the write mask instruction. When a write command is issued, the write mask will be cleared, causing subsequent data to be written. If the write mask instruction immediately follows the write command, its application will begin with the first unit burst.

If the repeat mode described in model 800 is used, the mask will repeat for all unit bursts. If the mode will change during the transfer, an additional write mask command will be issued to apply the new write mask to all subsequent data. If the start mode described in model 850 is used, the write mask will be cleared after the first unit burst. If additional masking is required (such as in the end unit burst), an additional write mask command will be issued that will only be applied to the next unit burst, while the write mask will be cleared.

For model 875, a multi-version version of model 800 is utilized in which the mask is repeated, but the WMSK instruction occurs simultaneously with the WR instruction, but on a different scale. If multiple serial interfaces are used, it may result in a more complex instruction configuration. If two turns are used together, for example, the write command can be combined on one turn and the first write mask on the other switch to improve bandwidth utilization.

Figure 9 shows an embodiment of the steps for utilizing multiple multiplexes for Duplication Check and instruction interpretation. The step of processing 埠 at block 902 is processed at block 904 with the first 埠. At processing block 906, a data stream with data is received via the corresponding Rx at the first location (which will then be decoded). Referring to the term "埠m+i" in the processing block 906, "m" indicates a link group, and "i" indicates the number in the link group. In this embodiment, i starts at zero, and since a single host is implemented, m is equal to zero. At decision block 908, the first 埠 (埠0) will be confirmed for any errors. If an error is found, the block 942 will end with an error and end the step. If no errors are found, the process will continue to processing block 910 to confirm the next defect until all defects have been confirmed. For example, at decision block 912, it will be confirmed if any defects remain. If so, the step will continue to processing block 906 and proceed to the next step. If no, the step will continue to processing block 914.

At decision block 916, it is confirmed whether the repetition is on. If so, at decision block 918, the current acknowledgment will be confirmed and, depending on its outcome, its steps will end at block 942 with a return error, or (if no repetition is turned on, return to reference decision block 916) the steps will continue until the decision Block 920, which will confirm if the defect has data. If the information is not repeated, it will not be compared. If there is data, a write operation will be performed in decision block 936. If no writes have been made, the block 942 step will end with a return error. If a write operation is performed, then at processing block 938 the data will be written to memory from all ports and a normal switch back is performed at block 940.

Returning to decision decision block 920, if there is no data, decision order 922 will perform an instruction validity check. At decision block 922, it will be confirmed whether the command is valid, for example, a list of instructions will be confirmed. If the instruction is not valid, the step will end at block 942. If the command is found to be valid, then at decision block 924 it will be confirmed if the instruction is in the sequence (e.g., if the instruction is in the correct position). If the instruction is not in the sequence, an error will be returned at block 942. If the instruction is found to be in the sequence, then instruction processing will be performed at processing block 926.

At decision block 928, the next 将 will be confirmed to see if there is duplicate information for the next pair (Pair). Since the repetition of the data usually involves a pair of defects, the number of defects in the processing block 930 will be increased by two to confirm the next two. Returning to decision decision block 928, if the answer is yes, then (single) 将 will be selected in processing block 934. The next step will proceed to decision block 932 to confirm if more defects are to be processed. If so, the step will continue to decision block 916. If not, a normal reversal will be issued at block 940.

In one embodiment, the data is received at a time and the command is received at this location. The instructions are processed by instruction interpreter 248 (shown in Figure 2A), represented here as blocks 922, 924, and 926. The repeat check is performed at the position indicated by the two triangles 254 (as shown in FIG. 2A), and is represented here as blocks 916, 918, and 920.

Figure 10 illustrates an embodiment of an instruction repetition model 1002, 1004, and 1006. In one embodiment, the instruction repetition is used to improve error detection. The instruction is transmitted twice and the original instruction is compared to the repeated instruction. If one or two of 1002 and 1004 are used, the instructions 1010 and 1014 are repeated immediately after the original instructions 1008 and 1012. If four or more 埠1006 is used, the repeating commands 1016 and 1018 will appear in other 埠.

The instruction is specifically selected because: (1) in a connection , case, the repetition can be used to fill the unused bandwidth; (2) The misinterpretation of the instruction may result in unanticipated results, such as sorting violations (for example, Start the started library, or write to the unstarted library) or destroy the memory location that is not related to the current transfer; conversely, if an instruction is correct, then any bad data is limited to at least the current transfer; and (3) Although repeated data can produce better results, the effective system bandwidth will be half, because the free space available for instructions is not available in the data stream.

The instruction repetition models 1002, 1004, and 1006 display a single 埠 1002, and a combination of duplicate 埠 1004 and 1006. It also shows how duplicates and multiple instructions work together. For example, a different maximum number of two instructions can be transmitted in the same box time.

In a single UI model 1002, the instructions are issued singularly, and their repetition 1010 follows the instruction 1008. For the two-dimensional model 1004, the repeat instruction 1014 is transmitted at the same frame time. However, if the repetition is turned off, the two instructions can occupy this frame time. For four or more models 1006, two (or more) instructions 1020 and 1022 can occupy a frame time, and both instructions 1020 and 1022 can be repeated as repeat instructions 1016 and 1018 in the same frame time. There is no limit to the number of instructions that can be transmitted at the same time or the granularity of the number of 埠 in the group.

Depending on the usage models 1002, 1004, and 1006, the instructions are executed exponentially. In some cases this will save time, but it will measure the probability of errors and the cost of handling errors. If all copies are available in a box of time, the wrong result will be available immediately.

The above description is intended to be illustrative of the invention, and the specific details are set forth to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some specific details. In other instances, some conventional structures and devices are shown in the form of block diagrams. Intermediate structures may be included between the elements in the figures. Elements in the description or figures herein may include additional inputs or outputs without being illustrated or illustrated.

Various embodiments of the invention may include various steps. These steps may be implemented by hardware components or may be included in a computer program or computer readable instructions, and may be used to produce a general purpose or special purpose processor or logic circuit having instructions to perform the steps. Alternatively, these steps can be carried out by a combination of hardware and software.

One or more of the modules, elements or components described in the specification are located or related to a multi-master improvement mechanism such as the embodiment, and may include hardware, software, and/or combinations thereof. In one embodiment, a module includes software, software files, instructions, and/or settings that can be provided via an item made by a machine/electronic device/hardware. An article of manufacture may include media that is machine-accessible/readable by the content to provide instructions, materials, or the like. The content can be in an electronic device (such as, for example, a filter, a disk, or the one of the disk controllers) to perform the various operations and perform the actions.

Portions of various embodiments of the present invention can be provided by a computer program product, which can include a computer readable medium having computer program instructions stored therein for programming a computer (or other electronic device) to perform The steps of the embodiments of the present invention. Machine readable media can include, but is not limited to, floppy disks, compact discs, CD-ROMs, Magneto-Optical Disks, read-only memory, random access memory, erasable and programmable Read-only memory (EPROM), electronic erasable programmable read-only memory (EEPROM), magnetic or optical card, flash memory or other form of media/machine readable media suitable for storing electronic instructions. In addition, the present invention can also be downloaded as a computer program product in which a program can be transferred from a remote computer to a requesting computer.

Many of the methods described are in their most basic form, but the steps of any of these methods can be added or deleted without departing from the basic scope of the invention, and the information of the message can be increased or decreased. Obviously, those skilled in the art can modify or change them accordingly. The specific embodiments are not intended to be limiting, but to illustrate the invention. The scope of the embodiments of the invention is not to be construed as a

If an element "A" is coupled to element "B", element A can be coupled directly to element B or indirectly via element C. When the specification or the claims indicate that a component, feature, structure, step or feature A "causes" a component, feature, structure, step or characteristic B, it means that "A" at least partially causes "B", but may include at least Another element, feature, structure, step or feature contributes to "B". It is not necessary to include a particular element, feature, structure, step or feature in the specification. If the specification indicates "a" or "an" element, it does not mean that it has only one of the elements.

An embodiment is an embodiment or example of the invention. Reference is made to the "an embodiment", "an embodiment", "an embodiment" or "another embodiment" in the specification. But not necessarily in all embodiments. The "invention", "one embodiment" or "some embodiments" of the various aspects are not necessarily all embodiments. It should be understood that in the foregoing exemplary embodiments of the present invention, various features are sometimes clustered into a single embodiment, a drawing, or a description thereof, for the purpose of simplifying the disclosure to facilitate understanding of one or more of the various inventive concepts. . However, the method disclosed may not be interpreted as indicating that the claimed invention requires more features than those recited in each claim. Rather, the claims below reflect the inventive concept and rely on less than all of the features of a single disclosed embodiment. Accordingly, the claims are hereby explicitly incorporated into the description, each claim being an independent embodiment of the invention.

100. . . Conventional serial bit configuration

102, 122. . . Stop bit

104, 106, 108, 110, 112, 114, 116, 118. . . Bit

120. . . Start bit

124. . . value

126. . . Framed bit

128. . . frame

200. . . Memory

201. . . Camera

202. . . Memory core

203. . . Display device

204. . . Memory system

206, 208, 210, 212. . . port

214, 216, 218, 220, 222, 224, 226, 228. . . External memory interface

230, 232, 234, 236. . . Asterisk

238. . . Power control

240. . . PLE signal

242. . . /LPD signal

244. . . Phase-locked loop

246. . . REFCLK signal

248. . . Instruction interpreter

250. . . Mode register

252, 254. . . Triangle

256. . . Command signal

258. . . Library signal

260. . . Mask signal

262. . . Demultiplexer

264. . . Multiplexer

269. . . Communication channel

270. . . Single host link

271. . . Host

272. . . NAND flash

273. . . NOR flashes

274. . . DRAM

275. . .埠Link selection

276. . . a trip

277. . . Second

278. . . Four or more

279. . . table

280. . . Smart mobile phone architecture

281. . . Application processor

282. . . Baseband processor

283. . . SRAM/DRAM

285. . . SPDRAM

286, 287, 288. . . Multi-host connection structure

289. . . Memory bank

290. . . port

291. . . Memory core

292. . . Multi-host connection memory

293. . . Multiplexer

294. . . Demultiplexer

294a. . . Preparation channel

295. . .埠Link Control Register

296. . . Repeat instruction acknowledge register

297a, 297b. . . table

298. . . Enable_fn

299. . . Reading latency

302, 304, 306, 308. . . step

402, 404, 406, 408, 410, 412, 414, 416, 418, 420, 422, 424, 426, 428, 430, 432, 434, 436. . . step

502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 528, 530. . . step

602, 604, 606, 608, 610, 612, 614. . . step

700. . . frame

702. . . Payload

704. . . Reward indicator

720. . . Coding box format

722. . . Flag

724. . . Second instruction

726. . . Mode register group

728. . . DRAM instruction group

730. . . SYNC

732. . . SYNC2

734. . . data

736. . . Current library instruction

738. . . Current directive

740. . . Write command

742. . . Write mask

744. . . Read

746. . . Crowd stop

748. . . Precharge

750. . . Prefill all

752. . . Repository update

753. . . Memory bank

754. . . All library updates

755. . . Column address

756. . . Mode register read

757. . . Higher column address

758. . . Mode register write

760. . . Mode register write data

762. . . Self-renewed power off

764. . . Power off

765. . . Lower column address

770. . . ABNK

772. . . Mask bit

774. . . Memory bank

776. . . Row address

778. . . Mask

780. . . Selective WMSK instruction

800, 850, 875. . . model

802, 852, 876. . . Previous memory content

804, 854, 878. . . Instruction stream

806, 856, 880. . . Subsequent memory content

902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936, 938, 940. . . step

1002, 1004, 1006. . . model

1008, 1012. . . Original instruction

1010, 1014, 1016, 1018. . . Repeat instruction

1020, 1022. . . instruction

The embodiments of the present invention are intended to be illustrative and not restrictive, and the same reference numerals are used in the drawings.

Figure 1 shows an RS-232 conventional serial bit configuration; Figure 2A shows an embodiment of a single host interface memory; Figure 2B shows an embodiment of a single host connection of four memory; Figure 2 C shows an embodiment of a connection selection for a single host interface; Figure 2D shows an embodiment of a smart phone architecture; and Figure 2E shows a wisdom for using Serial DRAM (SPDRAM) for Figure 2D. An alternative embodiment of a telephone architecture; FIG. 2F shows an embodiment of a multi-host connection structure; FIG. 2G shows an embodiment of a multi-host connection memory; FIG.埠 Link control register and an embodiment for a repeat instruction acknowledgement register up to 16 ;; FIG. 2I shows an embodiment of a link multiplexer; FIG. 2 shows a link multiplexer route An embodiment of the table; FIG. 2K shows an embodiment of a connection demultiplexer; FIG. 2L shows an embodiment of a connection multiplexer routing table; FIG. 3 shows an embodiment of a step for frame synchronization; Display one for power control Step embodiment; FIG. 5 shows an embodiment of a step of performing a single acknowledgment for repeated acknowledgment and instruction interpretation; FIG. 6 shows an embodiment of a step of receiving and decoding a frame in one ;; FIG. Post-decoding block (format) embodiment; Figure 7B shows an embodiment of an instruction, status, and data encoding block; Figure 7C shows an embodiment of a current memory bank and current instructions; Figure 7D shows a write mask And an embodiment of a write command; FIGS. 8A, 8B, and 8C show an embodiment of a write mask model; FIG. 9 shows an embodiment of a step of using multiple scans to repeatedly check and interpret instructions; and FIG. An embodiment of an instruction repetition model.

902, 904, 906, 908, 910, 912, 914, 916, 918, 920, 922, 924, 926, 928, 930, 932, 934, 936, 938, 940. . . step

Claims (31)

A method for reducing memory latency includes: communicating data between a host computer system and a memory via a plurality of time intervals in a memory or a connection group, wherein the host computer system is Coupling to the memory, the port is one of the connection groups; and communicating with the host computer system and the memory via the port or the connection group at a single time interval to communicate an instruction related to the data, Wherein the number of connections of the connection group can be dynamically selected such that the membership of the connection group can be changed at any time during the operation of the memory; it further includes not being occupied by the instruction after maintaining the connection group. The subsequent instructions are communicated to the instruction. A method for reducing memory latency as described in claim 1, wherein the subsequent instruction communicates in the single time interval as the instruction. The method for reducing memory latency as described in claim 1 further includes communicating one of the instructions to repeat the command by maintaining the connection group. The method for reducing memory latency according to claim 1, further comprising implementing a masking mechanism to prohibit writing of data not including mask information in the same communication frame of the written data, so as to further reduce The number of communication bits and the potential of the memory. A method for reducing memory latency as described in claim 4, wherein the masking mechanism is changeable in a data stream. The method for reducing memory latency as described in claim 5, wherein the masking mechanism is modified to prohibit writing of data not including mask information in the same communication box as the write command. A method for reducing memory latency as described in claim 5, wherein the masking mechanism is automatically repeated for subsequent unit transfers. A method for reducing memory latency as described in claim 5, wherein the masking mechanism is stopped after a single unit transfer. A method for reducing memory latency as described in claim 1, wherein the instruction is insertable in a write data stream. The method for reducing memory latency as described in claim 1, wherein the status information is insertable in a write data stream. A device for reducing memory latency includes: a host computer system coupled to a memory, the memory being received from the host computer system via a plurality of time intervals located in the memory or a connection group Data, the 埠 is one of the connection groups; and the memory system is modified to pass through the 埠 or the connection group Receiving, at a single time interval, an instruction related to the data from the host computer system, wherein the number of connections of the connection group can be dynamically selected such that the membership of the connection group can be changed at any time during the operation of the memory Wherein the memory system is modified to receive subsequent instructions of the instruction by maintaining the connection group without being occupied by the instruction. The apparatus for reducing memory latency as described in claim 11, wherein the subsequent instruction communicates in the single time interval as the instruction. The apparatus for reducing memory latency as claimed in claim 11, wherein the memory system is modified to receive a repeat instruction of the instruction by maintaining the connection group. The apparatus for reducing memory latency as claimed in claim 13, wherein the memory is further modified to implement a masking mechanism to prohibit writing from being included in the same communication frame as the written data. Cover the information of the information to reduce the number of communication bits and memory latency. The apparatus for reducing memory latency as described in claim 14, wherein the masking mechanism is changeable in a data stream. The apparatus for reducing memory latency as claimed in claim 15, wherein the masking mechanism is modified to prohibit writing of data not including mask information in the same communication box as the write command. The apparatus for reducing memory latency as described in claim 16, wherein the masking mechanism is automatically repeated for subsequent unit transfers. A device for reducing memory latency as described in claim 16, wherein the masking mechanism is stopped after a single unit transfer. The apparatus for reducing memory latency as claimed in claim 11, wherein the instruction is insertable in a write data stream. The apparatus for reducing memory latency as described in claim 11, wherein the status information is insertable in a read data stream. A system comprising the apparatus of any one of claims 11 to 20, and for reducing memory latency, comprising: coupling a memory to a host computer to use a connection system to reduce memory latency; The 埠 link system includes a plurality of 埠 to communicate data and instructions, wherein the plurality of 埠 two or more 可 can be linked into one or more connection groups, the 埠 link system is used to: via the memory One or a connection group communicates data between the host computer system and the memory at a plurality of time intervals, the system being one of the group; and being connected to the connection group for a single time Intersecting an instruction related to the data between the host computer system and the memory, wherein the number of connections of the connection group can be dynamically selected, so that the connection group Subsequent membership may be changed at any time during the operation of the memory; wherein the connection system is further modified to communicate subsequent instructions of the instruction via the maintenance of the connection group without being occupied by instructions. A system for reducing memory latency as described in claim 21, wherein the subsequent instruction communicates in the single time interval as the instruction. A system for reducing memory latency as described in claim 21, wherein the UI connection system is further modified to communicate one of the instructions to repeat the command by maintaining the connection group. The system for reducing memory latency as described in claim 21, wherein the UI system implements a masking mechanism to prohibit writing of maskless information in the same communication frame as the written data. Information to reduce the number of communication bits and memory latency. A system for reducing memory latency as described in claim 24, wherein the masking mechanism is changeable in a data stream. A system for reducing memory latency as described in claim 25, wherein the masking mechanism is modified to prohibit writing of material containing mask information in the same communication box as the write command. A system for reducing memory latency as described in claim 26, wherein The masking mechanism is further modified to prohibit writing of material that does not contain mask information in the same communication box as the write command. A system for reducing memory latency as described in claim 27, wherein the masking mechanism is automatically repeated for subsequent unit transfers. A system for reducing memory latency as described in claim 27, wherein the masking mechanism is stopped after a single unit transfer. A system for reducing memory latency as described in claim 21, wherein the instruction is insertable in a write data stream. A system for reducing memory latency as described in claim 21, wherein the status information is insertable in a read stream.