TW200832406A - Memory controller including a dual-mode memory interconnect - Google Patents

Abstract

A memory controller including a dual-mode memory interconnect includes an input/output (I/O) circuit including a plurality of input buffers and a plurality of output drivers. The I/O circuit may be configured to operate in one of a first mode and a second mode dependent upon a state of a mode selection signal. During operation in the first mode, the I/O circuit may be configured to provide a parallel interconnect for connection to one or more memory modules. During operation in the second mode, the I/O circuit may be configured to provide a respective serial interconnect for connection to each of one or more buffer units, each configured to buffer memory data that is being read from or written to the one or more memory modules.

Description

200832406 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to computer recording of t-cells, and more particularly to data transfer between a memory controller and a memory unit. [Prior Art] Computer systems use many different types of system memory. A commonly used system memory system is implemented using a removable memory module. The memory _ body group has different types and configurations. In general, however, the memory module can be used as a printed circuit board having an edge connector and a plurality of memory devices. The far memory module can be plugged into a socket located on the motherboard (face board r board) or other system board (system b〇ard). A commonly used memory module is a dual in-line memory module (Duai "seven μ"

Memory Module, DIMM), but there are still other types. In other systems, the memory device can be non-removable and placed directly on the motherboard or system board. In the modern history, the speed and performance of computer system processors have increased rapidly. However, the performance of system memory is typically stagnant. As a result, some system performance improvements are limited by the performance of the system memory. Therefore, it is of great concern to system designers to improve the bandwidth and capacity of the system memory. While it is possible to improve system memory performance, these improvements are sometimes extremely high. In view of this, it is an extremely desirable task to improve the bandwidth and capacity of the memory of the system while keeping the cost low. SUMMARY OF THE INVENTION 5 94122 200832406 κ The present invention discloses various embodiments of a memory controller including a dual mode memory interconnect. In one embodiment, the memory controller includes an input/output (I/O) circuit having a plurality of input buffers and a plurality of output drivers. The input/output circuits can be grouped to operate in one of the first mode and the second mode depending on the state of the mode selection signal. During operation of the first mode, the input/output circuits can be grouped to provide a parallel interconnect for connection to one or more memory modules. During operation of the second mode, the input/output_circuits can be grouped to provide individual serial interconnects to each of the one or more buffer units, each buffer unit group forming a buffer positive The memory data in the one or more memory modules is read or being written from the one or more memory modules. In a particular implementation, each individual serial interconnect includes a plurality of differential bidirectional data signal paths. Each differential bidirectional data signal path can pass data between a given buffer unit and the memory controller. In another particular implementation, each individual serial interconnect includes a differential command signal path that can pass command information from the memory controller to a given buffer unit. In yet another specific implementation, each of the individual serial interconnects includes a plurality of downstream differential unidirectional signal paths and a downstream unidirectional differential clock signal path. Each downlink differential one-way signal path can pass information, address and command information from the memory controller to the one or more buffer units. The downlink unidirectional differential clock signal path can pass the serial clock signal from the memory controller to each of the one or more buffer units. In yet another particular implementation, each individual serial interconnect includes an upstream differential unidirectional signal path. Each uplink differential one-way signal path may pass data and Cyclic Redundancy Code (CRC) information from one of the one or more buffer units to the memory controller. [Embodiment] Referring now to Fig. 1, there is shown a block diagram of a memory system including a specific embodiment of a high-speed serial buffer. The memory system 10 includes a memory controller 1A that couples the memory cells 110A to -110H and the buffer cells 170A to 170J. It should be noted that an element containing a reference designator having numbers and letters may be indicated by only the number. For example, the memory unit 1 1 0 A can be indicated as a memory unit 11 合适 where appropriate. It should also be noted that the memory controller 100 can be a memory controller that is part of a chipset (e.g., can be used in a Northbridge arrangement). Or, as shown in FIG. 5, the memory controller 110 can be part of an embedded solution in which the memory controller 1 is embedded in a processing node containing one or more processor cores. In a shellfish, the 'g self-remembering body early 11 〇A to 11 can be a hate body module' such as a dual In-line Mem〇ry Module (DIMM). As such, each DIMM can include a plurality of memories 94122 7 200832406 'devices (not shown), such as devices in the dynamic random access memory (DRAM) family of memory devices. However, it is generally noted that the memory unit 11 of the system 10 can represent any type of system memory. In the illustrated embodiment, the memory controller 1 is coupled to the buffer unit 170 via high speed serial interconnects 160A and 160B. In one embodiment, each high-speed serial interconnect 160 uses a differential signaling technique. The high-speed serial 歹 'J interconnect 16 〇 may include a plurality of differential bidirectional data signal paths (DDQ), a differential buffer command signal path (BCMD), and a differential clock signal path. -(differential clock signal path)(WCLK) and differential cyclic redundancy code signal

Path) (CRC) As shown in the specific embodiment, there are two memory channels. As such, the tandem interconnect 160A can be used for one of the channels and thus coupled to the buffer cells 170A-170F, while the tandem interconnect 16b can be used for another channel and coupled to the buffer cells 170G-170J. It should be noted that in the particular embodiment illustrated, each of the buffer units 170E and 170J is not used and may be used for other purposes as needed. Furthermore, the memory controller 100 is coupled to the memory unit 110 via the parallel interconnect 165. As shown, the parallel interconnection 16 5 between the memory controller 100 and the memory unit 110 may include an address/command signal path (ADDR/CMD) and a clock signal 94122 8 200832406. 'clock signal path (MCLK). As shown by the two serial interconnects, two ADDR/CMD/MCLK signal paths are shown. Each of the ADDR/CMD/MCLK signal paths can be used for another J memory channel. As shown, one of the ADDR/CMD/MCLK signal paths is coupled to the memory cells 110A through 110D and the other ADDR/CMD/MCLK signals.

The I path is coupled to the memory cells 110E to 110H. Moreover, buffer unit 170 is also coupled to memory unit 110 via parallel interconnect 165. As shown in Figure 10, the parallel interconnect 165 also includes a data path (DQ) and a data strobe signal path (DQS). In one embodiment, the memory controller 100 can control the operation of the memory unit 110 by transmitting the address and instructions through the ADDR/CMD signal path. As will be described in more detail below, the DQ data path can transfer data between the buffer unit 170 and the memory unit 11 in both directions. The dq resource path may contain some 8-bit (byte width) data path. For example, the full data path can be 288 bits wide, but the full data path can be divided into portions of the byte size. It should be noted that in one embodiment, the 288-bit unit may include four check bytes, while in other embodiments, other numbers of acknowledged byte groups may be used. It should be noted that the full data path may include any number of data bits and may be divided into portions of the same size. The DDQ data path of the serial interconnect 160 can pass the data passed through the parallel interconnect in series and at high speed. For example, the DDQ0 signal path can pass data bits corresponding to DQ [0··3], and the DDQ1 signal path can pass data bits corresponding to DQ[4:7], but other mappings are also Possible 9 94122 200832406 0 There are many ways to make the data path lighter to the memory unit. For example, 'can be considered to buffer the single magic 7 (M乍 is part of a single integrated circuit. However, due to this To implement the required stitches ((4) number, this may be inconsistent. Because in a specific embodiment, the data path can be dispersed and grouped into smaller units. Therefore, in a specific Embodiment 'Each buffer single it 17G can be a separate integrated circuit, the integrated electric

The road system provides buffering functions to individual groups. In a specific embodiment, during the writer operation, each of the serial buffer units 170 can serially input clocks (cl〇ck(8) and store two bytes, and then transmit the two in parallel. The bytes are on the parallel interconnect. To obtain the required throughput, in one embodiment, the serial interconnect 160 can be transferred by the parallel interconnect 165 at four times the rate of the data transfer on the data signal path. However, the addr/cmd signal path and the MCLK signal path can be operated at half the rate of the data path on the parallel interconnect 165. For example, when the parallel interconnect 165 is available: the signal path DQ/DQS is available. When 1600MT/S transfers data, and the addr/CMD and MCLK signal paths can be operated with 8〇〇MT/s, the serial/column interconnection 160 can transfer data to the DDQ data path. In other embodiments, the tandem buffer unit can store any number of bytes before transferring the byte to the parallel interface l65. It should also be noted that the serial interconnection 】(6) Available for any suitable parallel 165 The data rate path can be transmitted. The CRC signal path can transmit 94122 10 200832406 r CRC information from each buffer unit 170 to the memory controller 100 via an individual one-way differential signal path. In addition, the clock signal path can be transmitted. The WCLK signal is sent to each buffer unit 170. Similarly, the BCMD signal path passes the buffer command from the memory controller 100 to each buffer unit Π 0. In one embodiment, the memory controller 100 can pass the BCMD signal. The command sent by the path controls the operation of the buffer unit 170. Thus, the buffer unit 170 can have a normal operation mode and a configuration and test mode. For example, operating on standard data. During this period, the memory controller 100 can send data and pre- and post-sync codes (pre- and post-amble 〇 - one of the continuation and intrusion '^ 日令' to δ buy and write to the poor storage device (data Storage), and corrects the phase offset (phase .offset) of the DQ signal path. In addition, for example, the memory controller 1 The structure, training, and testing of the buffer unit 17〇_ are controlled by transmitting a plurality of loopback commands, CRC control commands, and CRC training pattern commands. The possibility that the memory controller 1 (10) receives a bit error is significant. Therefore, the error detection code must be used to protect the transfer between the memory controller and the backflush unit. The error detection code will be strong and powerful. Multiple bit error. In one embodiment, the CRC code can be used to provide such multi-bit error detection. More specifically, as shown in FIG. 2, in order to simplify the logic in the buffer unit and/or the memory module, and to report the error of the memory control unit of the 94122 11 200832406, the buffer unit 170 The CRC is calculated based on the data it generates or the data received. Therefore, in order to transfer the crc information back to the memory controller 100, a one-way CRC signal path can be used. As shown in Fig. 2, the CRC unit 25 can calculate the CRC based on its internal data and send the CRC data back to the memory controller 1A. When an error is detected on the link in any direction, the memory controller 1 can correct the error by retrying the operation. In a specific embodiment, the CRC information can be calculated and simultaneously transferred with the transferred data from the buffer unit 170 to the memory controller ι, so that the CRC can be available at the same time as the memory control at its arrival. The data block protected by the device 100. In one embodiment, the delay is introduced into the data path during the conversion between write-to-read and read-t-write, Calculate the delay associated with this CRC. As described above, for example, many conventional systems control φ functions such as clock phase recovery, channel equalization, and error detection in various communication devices to control High-speed two-way communication. However, as described in more detail below, buffer unit 170 can be simplified to produce such control functionality asymmetry. In this regard, the memory controller 100 can include a control function that dynamically and adaptively corrects the signal characteristics (eg, phase, etc.) of the transmitted data to be transmitted, so that the buffer unit 170 is based on the received buffer unit 170. Read the information correctly with the information. In addition, the memory controller 100 can correct its internal receiver characteristics so that the memory controller 1 94 12 94122 200832406 can receive the data transmitted by the buffer singular 70. Furthermore, the memory controller 100 can correct the phase of the clock signal supplied to the buffer unit 17 so that the address and command information can be correctly sampled. ...more than 4 inches, at the data rate, the uncertainty of the delay in the transmission path of the different signals in the bus may require the sampling pulse of the received state of the signals (sample cl〇ck) Phase correction per bit. In order to avoid the circuit system and system in the buffer unit 17〇, the memory control ι〇0 can correct the phase of the transmitted clock and the data signal to avoid the complicated phase in the slave device (Slave). The phase shifting circuit is such that, in the particular embodiment illustrated, the memory controller i (10) includes a unit 101 coupled to the transmitting unit 102, the receiving unit 104, and the clock unit. The control unit 101 can be based on the δ-decimal phase information received from the buffer unit 17 ,, and the buffer unit 70 can be used to correct the phase of the various clock edges in the memory controller 1 〇〇. For example, in response to information such as CRC data and read data, the control unit 101 can control the phase tracking and adjustment circuits in the transmitting unit 102 and the receiving unit 104, respectively. (As shown in Figure 2). This function will be described in detail below in conjunction with the description of Figs. 2 and 5. In the second picture of the wheat, the figure of the memory system shown in Fig. 1 is explained in detail. The components corresponding to those in the i-th figure are given the same reference numerals for simplicity. The memory controller 100 is coupled to a serial buffer 170 via a differential serial interconnect 16 . It should be noted that the buffer unit 17A can represent any of the buffer units π 〇Α to 17 〇 J shown in the figure. Therefore, the differential serial interconnect 16 includes a differential WCLK signal path, a differential 94122 13 200832406 BCMD signal path, a differential crc signal path, and a differential data signal path DDQ [7:0]. The memory controller 100 includes a 6.4 GHz clock signal generated from the clock unit 106 in Fig. i, the clock signal being coupled to variable phase units 293, 294, 295 and 296. The variable phase unit can be part of the timing unit 106 and can provide an internal clock to the memory controller. The φ outputs of the variable phase units 293, 294, 295 and 296 provide the clock signals to flip-flops (FF) 290, 289, 286 and 284, respectively. The variable phase unit 293 is coupled to the clock input of the FF 290. Since the FF 290 has an inverter 292 that couples a feedback looP to the input, the 6.4 GHz clock signal output is a 3.2 GHz clock signal. The output of FF 290 is coupled to the input of a differential output driver 291 and its output is coupled to a differential WCLK signal path. This write data is coupled to the input of FF 286. The output of the FF 286 is coupled to a 10 differential equalization output driver (287). The output of the driver 287 is coupled to one of the DDQ [7:0] signal paths. Therefore, for each signal path of DDQ [7:0], a similar write data output path (not shown) can be used. Similarly, for reading data, one of the DDQ [7:0] signal paths is coupled to the differential input buffer 283 and its output is coupled to the input of the FF 284. The output of the FF 284 is provided as read data to other portions of the memory controller 100 (not shown). The CRC signal path is coupled to a differential input buffer 281 whose output is coupled to the input of a receiver clock data recovery unit (Rx CDR) 282. The Rx CDR system is coupled to a per bit offset unit 285 that is coupled to the variable phase unit 296. The buffer command information is provided to the input of FF 289. The output of FF 289 is coupled to a differential equalization output driver 288 that is coupled to the differential BCMD signal path. Buffer unit 170 includes a buffer 209 that represents a differential input buffer for each of the DDQ [7:0] signal paths. Buffer 209 is coupled to receive write data transmitted on one of the DDQ [7:0] signal paths. The output of the buffer 209 is coupled to the input of the FF 208. The output of the FF 208 is fortunate to write to the First-In-First-Out (FIFO) 220. The output of the write FIFO 220 is coupled to a DRAM interface 256, which represents an input buffer and output driver circuit for interfacing with the memory unit 110 via the parallel interconnect 165. As shown, there are 16 data selection communication path DQS 10 [15:0] and 32 data signal paths DQ [31:0] as part of the parallel interconnection 165. The write data from the write FIFO can be output to the memory unit 110 via DQ [3 1:0]. It should be noted that although only the DQ and DQS signals are displayed, the remaining signals have been omitted for simplicity. It should also be noted that although not shown for simplicity, the MCLK and DQS signals can also be differential signals. The read data from memory unit 110 via DQ [31:0] is coupled via DRAM interface 256 to one of the inputs of multiplexer (mux) 203. The output of the multiplexer 203 is provided to the input of the FF 206. 15 94122 200832406 Control logic 255 controls the multiplexer input select of the multiplexer 203. The output of FF 206 is coupled to a differential equalization data output driver 210 that is coupled to one of the differential signal paths of the DDQ [7:0]. The buffer unit 170 includes control logic 255 coupled via the input buffer 201 to receive the buffer command information (BCMD) from the memory controller ι, wherein the input buffer 201 is coupled to the FF 202 The input. The BCMD information can cause the control logic 255 to drive write data to the DQ data path, or to read data to the dq data path, or to enter and exit initialization sequences. Thus, control logic 255 can control DRAM interface 256, CRC unit 250, multiplexer 203, and other circuitry. In the illustrated embodiment, the 3.2 GHz clock signal is coupled to the clock inputs of FFs 202, 205, 208, and 206. Each FF 202, φ 205, 208 and 206 is shown as a dual edge flip flop, meaning that the flip flops form a latch 'D, which is input to the input clock signal. Both the leading edge and the trailing edge. Therefore, the write data and BCMD information can be transmitted to their respective data paths at a rate of 6.4 Gb/s, and the input is latched using a 3.2 GHz clock signal. Similarly, since the memory controller 1 operates at 6.4 GHz, the read data and CRC information can be transferred to its individual signal paths at a rate of 6.4 Gb/s and the memory controller during a specific loop return mode. Used within 1〇0. 16 94122 200832406 In one embodiment, the write data is latched by FF 208 and stored to write FIFO 220 when the write data is received. The write FIFO can store the data until enough bits are received for output to the memory unit 110 via the DRAM interface 256. As described in connection with FIG. 5, the memory controller 100 can dynamically and adaptively correct the signal characteristics (eg, phase, etc.) of the transmitted data and the internal receiver characteristics during operation. The phase of the 6.4 GHz clock signal is corrected, wherein the 6.4 GHz clock signal generates the 3.2 GHz clock signal provided to the buffer unit 170. More specifically, as described above, the receiving unit 104 includes sample clock phase adjustment circuits such as an Rx CDR 282 and an offset unit 285 to correct its own local sampling clock. The phase is more ideal to receive the data transmitted by the buffer unit 170. Thus, whenever the memory controller 100 receives the CRC data from the buffer unit 170, the receiving unit 104 can use the Rx CDR 282, the offset • unit 285, and the variable phase unit 296 to correct the clock phase of the FF 2 84. In addition, the control unit 101 in the memory controller 100 can correct the variable phase unit 293 to correct the phase of the 6.4 GHz clock signal supplied to the FF 290. During the initialization process, such as during power cycle restart, the memory controller 100 can correct the variable phase unit 294 to correct the phase of the 6.4 GHz clock signal provided to the FF 289 to allow the buffer unit 170 to properly sample the buffer. Command signal. Furthermore, during initialization and during operation during the predetermined time interval, control unit 101 may correct variable phase unit 295 to correct the phase of the 6.4 GHz pulsed signal 17 94122 200832406 ^ provided to FF 286 to correct the The phase of the write data transferred to the buffer unit 170 causes the buffer unit 170 to more desirably receive the write data. Figure 3 is a timing diagram illustrating the exemplary operation of the embodiment shown in Figures 1 and 2 during an 8-bit burst. More specifically, the timing diagram shows a read/write/read burst of 128 bytes. The figure includes the MCLK and ADDR/CMD signals, which are provided by the memory controller 100 to the memory unit 110. The figure also shows DQ and DQS signals for transmitting data and data strobe between the buffer unit 170 and the memory unit 110. The remaining signals: DDQ, BCMD and CRC signals are transmitted between the memory controller 100 and the buffer unit 170. As shown, read commands (e.g., rdA and rdB) are sent to the memory unit 110 by the memory controller 100. After several MCLK cycles, the data and data selection communication number DQS appear on the DQ signal path. A read command (e.g., r0, • rl) is sent to the buffer unit 170 via the BCMD signal path before the data appears on the DQ signal path. After the rdA data, the next MCLK cycle is on the DQ signal path, and the rdA data appears on the DDQ signal path. As described above, the rdA and rdB data are transmitted side by side from the memory unit 110 to the buffer unit 170 at a double MCLK rate (e.g., 16011^175). However, the data is serially transmitted from the buffer unit 170 to the memory controller 100 at an extremely fast data rate (e.g., 6.4 GT/S). In order to reduce the bus turn-around time when converting from read to write, the write data can be buffered in the buffer unit 170 by 18 94122 200832406 ". For example, the wrX data as shown and the associated B CMD write command (eg, wl) are sent to the buffer unit 170, but the data is not written to the memory unit 110 until later. The dotted line points to it. The read/write/read program can be roughly described as follows: The wrX data is written to the buffer unit 170 via the DDQ signal path by the memory controller 100 and stored in the buffer unit 170. The memory controller 100 simultaneously issues a read command (rdA is connected to rdB after several MCLK cycles) via the ADDR/CMD signal path to the memory unit 110. Just before the rdA data appears on the DQ bus (for example, when the wrX data is transferred on the DDQ), the memory controller 100 issues a read command (eg, r0 and rl) to the buffer unit 170 via the BCMD. . When the eight and rdB data are on the DQ bus, the memory controller 100 transmits a write command (e.g., wrX and wrY) to the memory unit 110 via the ADDR/CMD bus. The rdA and rdB data are latched in the buffer unit 170 and transmitted to the memory controller 100 via the DDQ. The memory controller 100 transmits a write command (e.g., w0, w2, and w3) to the buffer unit 170 before the rdB data transfer on the DDQ is completed. When the w3 write command causes the wrY data just sent via the DDQ signal path to be sent to the memory unit 110 via the DQ data path, the w2 instruction causes the previously stored wrX data to be written to the memory unit 110. . When the wrX data is being written to the memory unit 110, the memory controller 100 issues an rdC command to the memory unit 110 via the ADDR/CMD signal path. After some cycles, the rdC data and data strobe appear on the DQ signal path and the DQS signal path, respectively. When the rdC data is 19 94122 200832406, the data path is transferred to the buffer unit 170, the memory control ~ just test the command (for example: and (1) via the BCMD signal path to the buffer unit] 7ri m 170, thus causing the buffer unit 170 to send the read data via the DDQ data path. Similar to the wrX data, the data is not written to the memory unit during the bursting period. Conversely, the data is stored in The buffer unit 17 is used for the next write burst period. As described above, during the read and write operations between the memory controller 100 and the buffer unit 170, a CRC is generated and transmitted to the memory controller. 4 CRC is generated by BCMD information, as indicated by the arrow, and data is read. As shown, wl, r〇, w〇 command, wrX, and rdB data are used to generate CRC information. The signal is sent from the buffer unit 17〇 to the memory controller 1 on the CRC signal path. It should be noted that, as shown, although the above signal may cause the CRC information to be generated and sent to the memory controller 1 Oh, but even The CRC signal path may have a transition when the buffer singular element 170 is idle (ie, when no data is transferred). As described above, the CRC data is driven by the RXCDR 282 in the memory controller 100. Therefore, these conversions may be The read data sample clock is continuously aligned to phase to sample the read data in a cancerous manner. Figure 4 is a flow chart depicting the operation of the embodiment shown in Figures 1 and 2. As described above, the interface between the memory controller 1 (9) and the buffer unit 170 is asymmetrical. That is, the control function resident in the memory controller 100 is more buffered. In unit 170, 94122 20 200832406. Therefore, during power up and at a predetermined time during operation, the memory controller 100 can correct the signal characteristics (eg, phase, etc.) of the transmitted data to be transmitted so that The buffer unit 170 correctly reads the data based on the information received from the buffer unit 170. In addition, the memory controller 100 can correct its internal receiver characteristics to make the memory controller 1 The data transmitted by the buffer unit 170 is received. Further, the memory controller 100 can correct the phase of the clock signal supplied to the buffer unit 170, and correct the phase of the B CMD signal so that the buffer command information is buffered in a cancerous manner. Unit 170 samples. Referring collectively to Figures 1, 2 and 4, and starting from block 400 of Figure 4, in one embodiment, after a reboot or power-on state (block 400), control logic 255 initiates a buffer unit. The 170 jumps out and restarts into the training mode (block 405). Upon entering the training state, all of the two-way signal path drivers (e.g., DDQ, DQ, and DQS) may be in a high impedance state (block 410). In the training mode, during an even MCLK cycle, the BCMD signal path loops back to the CRC signal path (block 405); and during the odd MCLK period, a training pattern (eg, 10101010···) is output on the CRC path (block 420). The memory controller 100 drives a training pattern on the BCMD signal path that is output on the CRC path during the even MCLK period (block 425). The memory controller 100 obtains a bit-lock and a byte lock (byte_lock) that receive a known data pattern on the CRC path (block 430). In addition, the memory controller 100 corrects the phase 21 94122 200832406 ^ bit of the BCMD clock signal by correcting the variable phase unit 294 to enable the buffer unit 170 to obtain the bit lock on the BCMD signal path. (i.e., bit alignment) and byte concatenation (i.e., byte alignment) (block 435). More specifically, the memory unit 1 can change (offset) the pattern transmitted in one bit time (UI) to ensure that the buffer unit 170 correctly captures each bit in the string bit. Medium offset and capture the complete 8-bit byte on the correct byte boundary. The memory controller can then send a buffer command to buffer unit 170 to exit the training mode (block 440). To train the DDQ data path, memory controller 100 transmits the training pattern via the DDQ data path (eg, has many transitions) Random pattern). This pattern is stored in a write first in first out memory (write FIFO) 220 (block 445). The memory controller 100 reads back the stored pattern to obtain a bit lock (block 450). The memory controller 100 corrects the phase of the write data (e.g., by correcting the variable phase unit 295) to obtain a bit error rate of approximately 50%. A conversion error rate of 50% indicates that the written data is being sampled near the edge. The memory controller 100 then corrects the phase of the written data back at 0.5 UI. This will result in the FF 208, for example, to sample the data near the central portion of each data bit. This process can be performed for each DDQ signal path (block 455). To obtain the byte lock, the memory controller 100 transmits the training pattern via the DDQ data path. In one embodiment, the training pattern can have a different pattern for each byte. When monitoring the CRC information, the memory controller 100 22 94122 200832406 may offset the training pattern data by adding an m θ. If the crc message is correct, a byte lock is established (block 46〇). Once the training pattern is locked by the byte to the buffer unit 17 〇 π, the memory controller ι locks the read data byte. In one embodiment, memory controller 100 reads back the byte-locked training pattern (block 465). At this point, the serial interconnect should be aligned so that the bit lock and the bit, and the lock are both taken in the write and read directions. • ^ Similarly, the parallel DRAM interface 256 can be aligned. More particularly, in one embodiment, when the BCMD and ddq write phase alignment is preserved, the memory controller 100 can correct the WCLK phase until the write phase DqS edge is aligned with the appropriate MCLK edge ( Block 470), the buffer unit 170 series and the parallel interconnect are aligned, and during normal operation, the memory controller 1 can perform the write phase of the serial interconnect 160 using the training pattern described above. training. The training can be performed at predetermined time intervals. Similarly, during the idle period, the memory controller 1 can monitor and correct the BCMD and CRC alignment by sending some idle commands to the buffer unit 17A. These idle commands may cause a pre-transformation rich cRc pattern to be transmitted to the CRC signal path (block 475). Referring to Figure 5, a block diagram of an exemplary embodiment of a computer system including a memory system of the first and second figures is shown. It should be noted that, for components shown in Figures 1 and 2, the same reference numerals are used for a simple month. The computer system 500 includes a processing node 650' coupled to the memory buffer 170 and the memory unit ι10. 94] 22 23 200832406 In the implementation, the buffer unit m can be a product placed on the motherboard, the circuit chip ′ and the memory unit 11 can be inserted into the socket. In another conventional operation, the buffer sheet S 17 can be an integrated circuit chip disposed on an expansion board (ard) such as an ard, which can be inserted into a memory card socket card. In such an implementation, the expansion daughter board can have a socket to allow the memory units 11 to be inserted therein in an upright configuration. More specifically, the processing node 650 includes a processor core 601 coupled to the memory control state 100. It should be noted that there are any number of processor cores 61 in the processing node 650. As described above, the memory controller 100 signal is coupled to the memory buffer 170 via the differential serial interconnect 160 and to the memory unit 11 经由 via the parallel interconnect 165. As shown, the serial interconnect includes a unidirectional CRC signal path, a unidirectional WCLK signal path, a unidirectional BCMD signal path, and a bidirectional data signal path. In addition, between the memory buffer 170 and the memory unit 11, the parallel interconnection 165 includes bidirectional data and data selection communication path. Moreover, between processing node 650 and memory unit 110, parallel interconnect 165 includes unidirectional ADDR/CMD and MCLK signal paths. It should be noted that in addition to the ADDR/CMD signal, there are other signals, such as chip select, bank select, and others included in the parallel interconnect 165. However, for the sake of simplicity, these The signals are omitted. It should also be noted that although not shown for simplicity, the MCLK and DQS signals can be differential signals. Referring to Fig. 6, a block diagram showing a specific embodiment of a computer system 24 94122 200832406 The system includes a memory controller having a dual mode memory interconnect. The computer system 7GG is similar to the computer system shown in Figure 5. For example, computer system 700 also includes processing nodes (four) coupled to memory buffer 17 and memory unit 110. However, in Fig. 6, the controller 710 is a dual mode memory controller due to the memory, and thus is different from the memory control H 100 in Fig. More specifically, as described in more detail below, the memory control H 71G can be selectively grouped in parallel with the parallel connection to the memory or used in conjunction with the buffer unit 17〇. Connect to the operation. As outlined above, computer system designers may want to design a system that is extremely flexible so that the components can be used by more system manufacturers. Therefore, in a specific embodiment, the memory controller 71 can be electrically configured to operate in the first mode to provide a parallel memory interconnection (10) that is compatible with a plurality of memory specifications. In other embodiments, the memory unit m can be compatible with Leg 2, DDR3, or other desired specifications. Thus, the memory controller 710 can be provided as its parallel interconnection, as desired* Compatible with the parallel interconnection of the dirty 2 and DDR3 technologies. In addition, the memory controller can be configured to operate in the second mode to provide, for example, the difference between the series of serial interconnects 160 The differemial serial interconnect 〇^ _, the mother/child/ZU determines and selects the input/rounding of the memory control 710 in the memory control 710 (1/0) circuit 711. In an example, the mode of the memory controller 710 can be selected using a virtual y y λ λ process, ie, a hardwired outer 94122 25 200832406. In this particular embodiment, the processing node One or more external selection needles of 600 The foot can be hardwired to the circuit ground as shown, or fixed to VDD or other voltage. The fabric unit 720 can detect the selected pin-shaped green, and thus the memory controller 710 is configured. The I/O circuit 711. In another embodiment, the memory controller mode can be selected when executing software for Bl〇s or other system level during system start-up. In a specific embodiment, in the first mode, the memory controller 710 is directly coupled to the memory, the body unit 11. In this first configuration, the I/O circuit 711 includes, for example, DQ, DQS, ADDR/CMD, and Parallel interconnection of signal paths. In the second mode, the I/O circuit 711 is changed to a differential serial interconnect, which is coupled to the <memory buffer unit 170 as shown in Figures 1, 2 and 5 (Dash line). To achieve mode switching, I/O circuit 711 can include a plurality of wheeled drivers and input buffers. Some drivers and buffers can be differential circuits, and some can be single-ended. Single-ended. In one embodiment, the mode is considered The connection between the processing node and the various I/O pins of the buffer and the buffer can be changed. Therefore, in the I-body embodiment, part of the I/O circuit 711 can operate as a programmable interconnect ( Programmable interconnect) ° For example, as shown in Figure 6, the measure (€1/1) (^8 signal path can be changed between the bidirectional DQS signal path and the one-way CRC signal path. The DQS/BCMD can also be changed between the bidirectional DQS signal path and the one-way BCMD signal path. In addition, the WCLK/DQS signal path can be changed between the 94122 26 200832406 bidirectional DQS signal path and the unidirectional WCLK signal path. Furthermore, the DDQ/DQ signal path can be changed between a two-way single-ended DQS signal path and a bidirectional differential data DDQ signal path. Referring to Figure 7, a block diagram showing another embodiment of a memory system including a cache is shown. The memory system 80 includes a memory controller 800 coupled to the memory cells 110A through 110H and then coupled to the buffer cells 870A through 870D. It should be noted that

W is similar to the memory controller shown in Figure 1, and the memory controller 800 can also be a memory controller that is part of a chipset (e.g., can be used in a Northbridge configuration). Alternatively, as shown in FIG. 10, for example, memory controller 800 can be part of an embedded solution in which memory controller 800 is embedded within a processing node that includes one or more processor cores. Corresponding to those components shown in the foregoing drawings, the same reference numerals are used for simplicity. Thus, in one embodiment, the memory cells 110A to 110H can be represented as a memory module such as a dual in-line memory module (DIMM) as described above. In various implementations, the memory unit can be adapted to various technologies such as DDR2 and DDR3. In the particular embodiment illustrated, memory controller 800 is coupled to buffer unit 870 via serial interconnects 860A through 860D. In one embodiment, each of the serial interconnects 860 uses differential signaling techniques. As will be described in greater detail below in conjunction with the description in FIG. 8, the serial differential interconnects 860A through 860D can each include an upstream link 27 94122 200832406 (upstream link) and a downstream link connected to each buffer unit 870. . The downlink link may include a plurality of downlink serial data signal paths (DSDs) and a corresponding downlink serial clock signal that can be used to provide a clock to the data entry buffer unit 870. Signal path) (DSCLK). Similarly, each uplink link may include a plurality of upstream serial data signal paths (USD) and may be used to provide clocks to the corresponding upstream queues of data into the memory φ controller 800. Upstream serial clock signal path (USCLK). Four memory channels are shown in the specific embodiment listed, but other quantities are possible. As such, the tandem interconnect 860A can be used for one of the channels, and thus coupled to the buffer unit 870A; the tandem interconnect 860B can be used for the second channel and coupled to the buffer unit 870B; the tandem interconnect 860C can be used for the third channel, And coupled to buffer unit 870C; and tandem interconnect 860D can be used for the fourth channel and coupled to buffer unit 870D. Spring In contrast to the serial interconnect 160 used in the previous embodiment, the serial interconnect 860 uses data signal paths that each pass data, CRC, and ADDR/CMD information. Thus, in one embodiment, the serial interconnect 860 can use a packet protocol in which the packet can include encodings to indicate that the load is ADDR/CMD or data. In addition, each packet can have a format for dedicated bit times for CRC information as well as payloads (e.g., data or ADDR/CMD). In addition, buffer units 870A through 870D are coupled to memory unit 经由0 via parallel interconnects 28 94122 .200832406 '865. In one embodiment, the parallel interconnect 865 can include a data path (DQ), a data selection path (dqs), an address/command signal path (ADDR/CMD), and a clock signal path (MCLK). It should be noted that there may still be other signals, such as chip select, bank select, check bits, and others included in the parallel interconnect 865. However, these signals are It is omitted here for the sake of simplification. It should also be noted that the parallel interconnection 8 6 5 can include four channels. As shown, one of the channels is coupled to the memory cells Π A to 110D, the other is coupled to the cells hoe to n 〇H, and the other is coupled to the memory cells 110J to 11 〇Μ. The other is engaged, the memory unit 11 ON to 11 OR. As will be described in more detail below, when the differential data path of the serial interconnect can serially and high speed transfer the data transmitted via the parallel interconnect, the data path DQ can be used in the buffer unit 87 and the memory. Data is transmitted in both directions between units no. For example, a given uplink (uplink) • USD [0] or downlink (d〇wnlink) DSD [〇] signal path can pass data bits corresponding to DQ [0:3], which The USD π] signal path can pass data bits corresponding to DQ [4··7], but other mappings are also possible. In some embodiments, the tandem link can be asymmetrical according to the number of pins in the serial data. In one implementation, the uplink may have more data signal paths than the downlink since it is assumed that the read operation may consume more bandwidth than the write operation. Similar to the buffer sheet 170 described in the month, each serial interconnect 86 can be used to transfer data by transferring the data at the quadruple speed of the data signal path at the quadruple speed of 94122 29 200832406. However, the ADDR/CMD signal path and the MCLK signal path can be operated at half the rate of the data path of the parallel interconnect 865. For example, when the data signal path DQ/DQS of the parallel interconnection 865 can transfer data by 1600MT/S, and the ADDR/CMD and

When the MCLK signal path is operational with 800 MT/s, the serial interconnect 860 can use 6.4 GT/S to transfer data on the uplink and downlink data paths. It should be noted that the serial interconnect 860 can operate with any suitable data rate for the parallel interconnect 865. In one embodiment, the memory controller 8 can control the operation of the buffer unit 87 via commands sent on the DSD signal path. As such, the buffer unit 870 can have a normal mode of operation as well as a fabric and test format. For example, during normal data operation, the memory controller 8 can send read and write instructions for data and pre- and post-sync codes (pre_ and p〇st_ambles) to read and write data. Store the device and correct the phase offset of the DQ .fU Tiger Road Control. In addition, for example, the memory controller 800 can control the configuration, training, and processing of the buffer list 2 87G by transmitting a plurality of loopback commanj CRC control commands and CRC training pattern commands. At the rate of the goods, _ H w. Keep 'buffer early 87兀 or memory controller 800 code with two: the possibility is significant. Therefore, the error detection code must be protected by the memory suppression type, and the error detection heart;:: the transfer unit between the punch unit 870 is in error. Strongly and powerfully detecting multiple multi-bit errors within the protected block. In the specific embodiment, the 'CRC code can be used to provide this.

w, 彳. More specifically, as shown in FIG. 8, CRC 94122 30 200832406 information can be generated and transmitted in both the uplink and the downlink. When an error is detected on the serial interconnect in any direction, the memory control cry 800 can correct the error by retrying the operation. In the case of the second embodiment, the error detected in the downlink link can be encoded into the upstream CRc. In a specific embodiment, the memory controller 8 can include a control function that dynamically and adaptively corrects the transmitted signal (characteristics (eg, phase, etc.) of the written data to enable the buffer unit 870 to be based on The information received from the buffer unit 870 reads the data correctly. In addition, the memory controller 800 can correct its internal receiver characteristics so that the memory controller 1 can receive the data transmitted by the buffer unit 870. Furthermore, the memory controller 8 can correct the phase of the clock signal supplied to the buffer unit 87 so that the address and command information can be correctly sampled. In particular, at high data rates, for the uncertainty of the delay of the transmission path of different messages in the bus, it may be necessary to receive the phase correction of each bit of the received signal. To avoid this circuitry in the buffer unit 870, the memory controller 8 (8) can correct the phase of the transmit scoop and data signals to avoid complex phase shifting circuitry in the slave. Thus, in the particular embodiment illustrated, the memory bank 80 〇 includes a control unit 8〇1 coupled to the transmitting unit 〇2, the receiving unit 〇4, and the clock unit 806. The control unit 8.1 can calculate the phase information based on the data received from the buffer unit 870, and the buffer unit 870 can be used to respond to the CRC data by, for example, the phases of the various clock edges in the memory controller 8 And reading the information of the data, the control unit 31 94122 200832406 element 801 can be controlled by the transmission unit 802, the receiving unit 804 and the phase tracking and correction circuit in the pulse unit 806 (as shown in FIG. 8). This function will be described in detail below in conjunction with the description of Figs. 8 and 9. Referring to Fig. 8, a detailed description of the components of the memory system shown in Fig. 7 will be given. The components corresponding to those in Fig. 7 are given the same reference numerals for simplicity. The memory controller 800 is coupled to the serial buffer unit 870 via a differential serial interconnect 860. It should be noted that the buffer unit 870 can represent any of the buffer units 870A through 870D shown in FIG. Therefore, the differential serial interconnect 860 includes a downstream differential serial clock signal path (DSCLK) and a downstream differential data signal paths DSD [11:0]. Similarly, differential serial interconnect 860 includes an upstream differential serial clock signal path (USCLK) and an upstream differential data signal path USD [19:0]. The memory controller 800 includes a 6.4 GHz clock signal generated from the clock unit 806 of Figure 7. In one embodiment, a 6.4 GHz clock is used for the internal clock of the memory controller 800. The output of the variable phase unit 890 provides the clock signal to the flip-flop (flip-f1()p, FF) 889. The 6.4 GHz clock is also coupled to the iaiie deskew circuit 881. And coupled to the clock input of FF 893 to generate the serial clock signal DSCLK. Since the FF 893 has a return 892 coupled to the input terminal in a loop, the 6.4 GHz clock signal is divided into two parts and the output is a 3.2 GHz serial clock. The 3.2 GHz clock system is differentially driven by a differential output driver 891. 32 94122 200832406 In the specific embodiment illustrated, the write data, addr/cmd, and CRC are provided to the input of FF 889. The output of the FF 889 is coupled to a differential equalization output driver (888). The output of the driver 888 is coupled to a single signal path of the DSD [11:0]. Therefore, for each signal path of DSD [11:0], a similar round-out path (not shown) can be used. Similarly, for reading data, a single signal path of USD [19:0] is coupled to differential input φ into buffer 885, and the output of buffer 885 is coupled to the input of FF 886. The output of the FF 886 is coupled to the input of the pass anti-aliasing unit 881. The output of the pass anti-aliasing unit 881 is provided as read data and CRC information to other portions of the memory controller 800 (not shown). The upstream serial clock signal USCLK is coupled to a differential input buffer 887 whose output is coupled to a variable phase unit 882. The output of variable phase unit 882 is coupled to the clock input of FF 886. The buffer unit 870 includes a buffer 801 that represents a differential input buffer for each of the DSD [11: 〇] signal paths. Buffer 801 is coupled to receive write data, ADDR/CMD and CRC information transmitted on one of the paths of the DSD [11:0] signal path. Therefore, similar to the memory controller 8, a similar output path (not shown) can be used for the signal path of each DSD [11: 〇]. The output of the buffer 〇1 is coupled to the input of the FF 802. The output of the FF 802 is connected to the input of the FF 803. The output of FF 803 is coupled to command buffer 805, CRC unit 826, write FIFO 807, and output multiplex 33 94122 200832406 (mux) 809. The output of the write FIFO 807 is coupled to the DRAM interface 856' which is similar to the DRAM interface described above in connection with FIG. As shown, there are 4 MCLK signals, ADDR/CMD signals, 16 data selection communication path DQS [15:〇], and 72 data signal paths DQ [71:0] as part of the parallel interconnection 865. The write data from the write FIFO 807 can be output to the memory unit 110 via Dq [71: 〇]. It should be noted that the rest of the signals have been omitted for simplicity. 10 Note that although not shown for simplicity, the MCLK and DQS signals can also be differential signals. The read data from the memory unit 11 via DQ [71: 〇] can be coupled to one of the inputs of the multiplexer (mux) 8〇9 via the DRAM interface 856. Multiplex | § The output of 809 is provided to the input of FF 81〇. Control logic 855 controls the multiplexer input select of the multiplexer 8〇9. The output of the FF 810 is coupled to the differential equalization data output. The driver 811 is coupled to one of the differential path of the USd [19:〇]. Buffer unit 870 also includes control logic 855 that is coupled to receive command information (CMD) from the memory controller. The CMD information can cause the control logic 855 to drive the write data to the DQ data path, or to read the data to the Dq data path, or to enter and exit initialization and test procedures an (j test sequences). Thus, control logic 855 can control the dram interface 856, CRC units 826, 808, multiplexers 8, and other circuits. In the illustrated embodiment, the 3.2 GHz clock system is coupled to the clock input of 34 94122 200832406 FF 810 and to the input of the differential equalization data output driver 812 and the output of the driver 812 The upstream serial clock (USCLK). The 3.2 GHz clock signal is also coupled to a Divide by 4 unit 804 to provide an internal 800 MHz clock domain of the Mclk domain. In one embodiment, packets received via the DSD [11:0] signal path are simultaneously provided to CMD buffer 805, write FIFO 807 φ, and CRC unit 826. Since the packets can be encoded to indicate that they are ADDR/CMD or data payload, the CMD buffer 805 and the write FIFO 807 can include packet decode logic (not shown) to enable the above two Capture their respective packets. Therefore, when a write data payload packet is received, the packet can be decoded by the write FIFO 807 and the data stored in the write FIFO 807. The CMD buffer 805 can discard the data payload packet. The write FIFO 807 can store the write data until a sufficient bit is received and is output to the memory unit 110 via the DRAM interface 856. Similarly, when a CMD payload packet is received, the packet can be decoded by the CMD buffer 805 and the CMD information stored in the CMD buffer 805. The write FIFO 807 can discard the CMD load packet. Since all packets may contain a CRC payload, CRC unit 826 receives all packets and fetches the CRC information. As described in more detail below in conjunction with the description in Figure 9, during operation, the memory controller 800 can dynamically and adaptively correct the transmitted write data and the received signal characteristics (e.g., phase, etc.). More specifically, as described above, the receiving unit 804 includes sampling clock phase correction 35 94122 200832406 ...: Γί Lane anti-skew 881 and variable phase unit 890, 882, stealing =- (four) ritual clock sampling time The phase is more ideally received by the slow t = Γ data. Thus, regardless of the CRC data of the memory controller 8 (10) and the L unit 870, the receiving unit 804 t is anti-skew and the variable phase unit 882 is corrected for the day of the FF 885. The control within the device can be used to correct the phase of the write data transferred to the buffer unit 870 so that the buffer unit can more desirably receive the write data. Figure 9 is a diagram showing an operational private diagram of the specific embodiment shown in Figures 7 and 8. More specifically, it describes the initialization and fabrication procedures for establishing and maintaining communication between the memory controller and the buffer unit: see Figures 7 through 9 together, and starting from block _ of Figure 9, when When the system is restarted, the 'no serial signal path can be considered for alignment during power cycle re-opening or other system restart conditions. In this way, the memory controller and the buffer unit 8 7 〇 jump out and restart to enter the training state 1, or 疋T1. In the T1 state, the serial interconnect 86 operates at 400 MT/s (block 905). The memory controller 8 uses a dead-reckoned 0.5UI offset (0ffset) to transmit and receive data (block 910). For example, the memory controller corrects the offset to become an approximate point that does not completely span the time of the positioning element. The memory controller 8 sends a command to cause the buffer unit 870 to leave the T1 state and enter the T2 state (block 915). In the T2 state, the buffer unit 870 drives the pattern of the predetermined pattern, such as 1 〇 1 〇 〇 〇, on all the bit lanes of the USD link. For example, 94122 36 200832406 ^ says that the memory controller uses the known pattern to obtain bit lock and correct the variable phase unit 882 (block 920). In one embodiment, for example, memory controller 800 sends a buffer command to cause buffer unit 870 to exit the T2 state and to drive all of the 8-bit time units to enter the T3 state (block 925). In the T3 state, the buffer unit 870 transmits a predetermined pattern such as 101010... to the memory controller 800 over the even MCLK period via the USD signal path (block 930). The buffer unit 870 is configured to loop back the downlink data to the upstream USD signal path over the odd MCLK period, and send a pattern different from the 101010... pattern through the DSD signal path (block 935). The memory controller 800 uses the different pattern to obtain a byte lock. The memory controller 800 then corrects the downstream data phase to allow the buffer unit 870 to obtain bit lock and byte lock (block 940). When completed, the memory controller 800 drives all zeros such that the 8-bit time causes the buffer unit 870 to exit the T3 state and enter the positive 10 mode of operation (block 945), at which point the memory controller 800 can read and The data is written to the memory unit 110 and the like. Once in the standard mode of operation, the memory controller 800 can correct the divide by 4 MCLK divider 804 within each buffer unit 870 to enable all buffer units 870 to use the same clock edge (phase) ( Block 950). More specifically, memory controller 800 can send a buffer command to time retard the MCLK phase by one or more bits. The memory controller 800 can train the upstream and downstream 37 94122 200832406 signal paths (block 955) using a periodic training mode during predetermined time intervals during normal operation (eg, every 100 ps). For example, for downstream training, the memory control benefit 800 can write the training pattern to the write FIFO 807 using a predetermined training phase offset (block 960). The memory controller 8 can now read back the training pattern and calculate an error flag from the pattern conversion value (block 965). Using the calculated error flag, the memory controller 8 can correct the downstream data phase (block 970). For upstream training, the memory controller 8 can write the training pattern to the write FIFO 807 using normal phase offset (block 975). The memory controller 800 can now read back the stored training pattern and use the other predetermined training phase offset to calculate an error flag from the pattern conversion value (block 980). Using the different error flag, the memory controller 8 can correct the upstream sampling phase (block 985). Once the periodic training is complete, the buffer unit 870 will place back into the mode as described above at block 945. Referring to Figure 10, a block diagram of a particular embodiment of a computer system incorporating the memory system of Figure 7 is shown. It should be noted that the components corresponding to the components shown in Figures 7 and 8 are denoted by the same reference numerals for simplicity and clarity. Computer system 1100 includes processing node 1150 coupled to a memory buffer 870 and a memory unit 11 〇. Similar to the computer system shown in Fig. 5, in one implementation, the buffer unit 870 can be an integrated circuit chip disposed on a motherboard, and the memory unit 110 can be inserted into the socket. In another implementation, the buffer unit 870 is placed on the integrated circuit board of the expansion daughter board, and the expansion daughter board can be inserted into the DIMM. In such an implementation, the expansion daughter board can have a socket to allow the memory units 110 to be inserted into the vertical configuration 94122 38 200832406. In the particular embodiment shown in FIG. 10, the processing node 丨50 includes a processor core 11 〇 1 that is coupled to the έ 体 memory controller 8000. There may be any number of processor cores 1101 within the processing point 1150. As described above, in conjunction with the description of Figures 7 and 8, the memory controller 800 signal is coupled to the memory buffer 870 via the differential serial interconnect 86 and coupled to the memory unit 110 via the parallel interconnect 865. As shown, the serial interconnect 860 includes a one-way downlink signal path, a one-way downlink clock signal path, a one-way uplink signal path, and a one-way uplink clock signal path. In addition, between the memory buffer 87 and the memory unit 11, the parallel interconnection 865 includes a bidirectional data and a data selection number path. Furthermore, between the processing node 1150 and the memory unit 11, the parallel interconnection 865 includes a one-way ADDR/CMD and MCLK signal path. It should be noted that in addition to the ADDR/CMD signal, there are other signals, such as chip select, bank select, and others included in the parallel interconnect 865. However, for the sake of simplicity, This has been omitted. Referring to Fig. 11, there is shown a diagram of another embodiment of a computer system including a memory control state having a dual mode memory interconnect. The brain-inducing system 12 is similar to the computer system 1100 shown in Figure 1Q. For example, computer system 12A also includes processing node 125A coupled to memory buffer 87 and memory unit 110. However, in Fig. u, since the memory controller 1210 is a dual mode memory controller, it is different from the megaphone controller 8 (8) in Fig. 1 . More particularly, as described in greater detail below 94122 39 200832406, the memory controller 1210 can be selectively grouped into a parallel interconnect 865 directly connected to the memory unit 110 or used in conjunction with the buffer unit 70 870. The series interconnects 86 are used to operate, as described above in conjunction with the descriptions in Figures 7 and 8. Similar to the memory controller 710 described above, the memory control in FIG. 11 is 1210, and can also be selectively operated by any parallel interconnection directly connected to the memory module. The module is compatible with various types. Memory specifications. For example, in a different embodiment, the memory unit 110 can be compatible with DDR2, DDR3, or other desired specifications. As such, the memory (12) 1210 can be provided as its parallel interconnect, as desired to provide parallel interconnected milk compatible with DDR2 and DDR3 technologies. In addition, the memory controller 1210 can also be selectively grouped to operate in the second mode to provide serial differential interconnects to, for example, the serial interconnects 860 of FIGS. 7 and 8. , 帛 to connect to the buffer unit

In Fig. 11, the configuration unit 122 can determine and select the configuration of the I/O circuit 1211 in the memory control II 121G. In one embodiment, the mode of the memory controller (2) 0 can be selected using a fixed external pin of the processing node. In such a particular embodiment, one or more of the external selection pins of processing node U50 may be lined to the circuit ground as shown, or fixed to VDD or other voltage. Fabric unit · Side selection pin status ' So the memory / controller of the memory controller (4)! 2 U. In the other embodiment, the memory controller mode can be selected when the BIOS 1205 or other system level software is executed during the initial (resistance). In the specific embodiment, In the first mode, the memory controller 1210 is directly coupled to the memory unit 11A. In this group, the I/O circuit 1211 provides, for example, DQ, DQS, addr/cmd, and MCLK or other signal paths. Parallel interconnection. In the second mode, the ι/〇 circuit 1211 is changed to a differential serial interconnection, which is coupled to the memory buffer unit 87 〇 (dashed line) as shown in the 78th and ίο. To achieve mode switching, the 1/0 circuit 1211 can include a plurality of output drivers and input buffers. Some of the drivers and buffers can be differential circuits, while some can be single-ended. In one embodiment, Depending on the mode, the connection between the processing node and the various pins of the driver and buffer can be changed. Thus, in one embodiment, the partial 1/〇 circuit HU can operate as a programmable interconnect. As shown in the figure The DSD signal path can be changed between the unidirectional differential DDS signal path and the bidirectional single-ended DQ signal path. In addition, the USD signal path can be in the unidirectional rib 8 signal path, bidirectional single-ended ADDR/ The CMD signal path and/or the bidirectional differential DQS signal path are changed. Furthermore, the DSCLK signal path can also be changed to one or more single-ended mclk signal paths between the differential one-way clock signal paths. Other pin combinations are contemplated. While the above-described specific embodiments have been described in considerable detail, it will be apparent to those skilled in the art that many changes and modifications will be apparent to those skilled in the art. The accompanying claims are intended to cover all such changes and modifications. 94122 41 200832406 [Simplified Schematic] FIG. 1 is a block diagram of a specific embodiment of a memory system including a cache; 2 is a diagram showing a more detailed aspect of the memory system component in FIG. 1; FIG. 3 is an exemplary burst operation of the specific embodiment shown in FIGS. 1 and 2. FIG. 4 is a flow chart describing the operation of the specific embodiment shown in FIGS. 1 to 3; FIG. 5 is a specific implementation of the computer system including the memory system shown in FIG. 1. FIG. 6 is a block diagram of a specific embodiment of a computer system including a dual mode memory controller in FIG. 5; FIG. 7 is a memory including a memory controller having a dual mode interface; A block diagram of a specific embodiment of the body system; Fig. 8 is a view showing a more detailed aspect of the memory system component of Fig. 7; and Fig. 9 is a view showing a specific embodiment of Figs. 7 and 8. FIG. 10 is a block diagram of a specific embodiment of a computer system including the memory system shown in FIG. 7; and FIG. 10 includes a dual mode memory controller in FIG. A block diagram of a specific embodiment of a computer system. While the present invention is susceptible to various modifications and alternative forms, the specific embodiments of the invention are shown by way of example in FIG. 42 94122 200832406. However, it must be understood that the description of the drawings and the detailed description of the invention is not intended to limit the invention. Modifications, equivalences and substitutions within the spirit and scope defined in the patent scope. It should be noted that the word "may" used throughout the text of this application is intended to mean (perhaps: possible, capable), not mandatory (meaning that it must be). Blood [Main component symbol description] 10,80 memory system 100, 710, 800, 1210 memory controller 101, 801 control unit 102, 802 transmission unit 104, 804 receiving unit 106, 806 clock unit 110, 110A to 110H, 110J To 110N, 110P to U0R memory unit 160, 160A, 160B, 860, 86ΌΑ, 860B, 860C tandem interconnect 165, 865 parallel interconnects 170, 170A to 170J, 870, 870A to 870D buffer unit / memory buffer Crying 201 input buffers 202, 205, 206, 208, 284, 286, 289, 290, 803, 810, 821 886 893, 889 flip-flops 203, 809 multiplexers 209, 218, 801 buffers 210, 811, 812 differential equalization data output driver 211, 287, 288, 888 differential equalization output driver 220, 807 writes first-in first-out memory (write FIFO) 250, 808, 826 CRC unit 255, 855 control logic 43 94122 200832406 '256 , 856 DRAM interface 281, 283, 885, 887 differential input buffer 282 receiver clock data return unit 285 offset unit 2 91, 8 91 differential output driver 292, 892 reverser 293, 294, 295, 296 , 882, 890 variable phase unit 400, 405, 410, 415, 420, 425, 430 , 435, 440, 445, 450, 455, 460, 465, 470, 475, 900, 905, 910, 915, 920, 925, 930, 935, 940, 945, 950, 955, 960, 965, 970, 975, 980, 985 Block 500, 700, 1100, 1200 Computer System 601, 1101 Processor Core 605, 1205 Basic Input Output System 650, 1150, 1250 Processing Node 711, 1211 Input/Output Circuit 720, 1220 1 Fabric Unit 805 Instruction buffer 881 pass anti-skew unit / circuit ADDR address BCMD buffer command CLKS clock signal CMD command CRC cyclic redundancy code DDQ differential data DSCLK downlink serial clock signal DSD downlink serial data DQ data DQS data selection Through MCLK clock signal Mode Sel. Mode select USCLK Upstream serial clock signal USD Upstream serial data WCLK Differential clock signal r0, rl, rdA, rdB, rdC Read command w0, wl, w2, w3, wrX, wrY Write command 44 94122

Claims (1)

200832406 X. Patent application scope: 1. A memory controller, comprising: an input/output (I/O) circuit, the number of output drivers, wherein the (10): the number of input buffers and the state of the complex selection signal The composition of the operation of the bag system depends on the mode; in the middle of the mode and the second mode, the UO circuit is operated in the first hand, the vehicle, and the J. Department 2. The attack is provided for connection to a guest connection; and the 1U second memory module is juxtaposed with each other, during operation of the second mode, (4) the circuit system is provided for connection to one or more buffer units. Each of the individual, column interconnects 'each buffer unit group constitutes a buffer to read or write the memory data of the one or more buffer units from the one or more buffer units. The memory controller of claim 1, wherein each of the individual serial interconnects comprises a plurality of differential bidirectional data signal paths, each of the differential bidirectional data signal path groups constituting the transfer data to the one or more buffer units Between the given buffer unit and the memory controller. The memory controller of claim 1, wherein each of the individual serial interconnections comprises a differential command signal path, and the differential command signal path & group constitutes to transmit the command information from the memory controller to the one Or a given buffer unit in multiple buffer units. 4. The memory controller of claim 1 of the patent scope, including the fabric sheet 70', the fabric unit coupled to the I/O circuit and the group composition detection will select 45 94122 200832406 _ @ 信号 对 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / rate. The stomach cramps are transferred to the private car. 6. == The memory controller of the fifth item, where each differential clock signal path s, the differential clock signal path. The transmission clock is transmitted from the memory controller to the one or more of the M M k impulses, wherein each of the differential clock signals operates at the rate of the brood. 7. The memory controller of claim 5, wherein the parallel interconnection comprises one or more clock signals, each of the clock signal paths forming a second clock signal from the memory The body controller to the one or more memory modules 'where the second clock signal operates at the second data transfer rate. 8. The memory controller of claim i, wherein the parallel interconnection comprises a plurality of configured bidirectional data signal paths, each of the bidirectional data signal path groups forming a transfer data to the memory controller and the A special module between one or more memory modules. 9. If the patent application scope is in the i-th item, the parallel connection includes a plurality of bidirectional data selection communication path paths, and the plurality of bidirectional data selection communication number path groups constitute the transmission data strobe in the memory. The body control benefits between the particular module in the one or more memory modules. The memory controller of claim 1, wherein the parallel interconnection comprises a plurality of unidirectional addresses and a command signal path, and the plurality of unidirectional addresses and command signal path groups are formed. Transfer the address and command information from the memory controller to the one or more memory modules. 11. The memory controller of claim 1, wherein each of the individual serial interconnects constitutes a signal path via one or more Cyclic RedundanCy code (CRC) signals. Cyclic redundancy code information for one or more buffer units, wherein the CRC signal corresponds to the data transmitted by the UE through the individual serial interconnects. 12. The memory controller of claim 1, wherein each individual serial interconnect comprises a plurality of downlink differential one-way signal paths, each of the downlink differential one-way signal path groups forming a transmission data, an address, and a command From the § memory controller to the one or more buffer units. 13. The memory controller of claim 12, wherein each individual serial interconnect comprises a downlink unidirectional differential clock signal path, and the downlink unidirectional differential clock signal path group constitutes a transmission string The clock signal is the memory controller to each of the one or more buffer units. 14. The memory controller of claim i, wherein each of the individual serial interconnects comprises a plurality of uplink differential one-way signal paths, each of the upstream differential knife one-way signal path groups forming a transmission data and a loop redundancy Remaining (CRC) information to one of the one or more buffer units to the body controller. u 15. The memory controller of claim i, wherein each of the 94122 47 200832406 serial interconnects comprises an uplink unidirectional differential clock signal path, and the uplink unidirectional differential clock signal path group constitutes Passing one of the serial clock signals to the one or one of the buffers to the memory controller. 16. A computer system comprising: a processor; and a memory controller coupled to the processor, wherein the memory controller comprises: • a vertical input/output (1/〇) circuit comprising a plurality of inputs The buffer and the reset-out drive & 'where 'I/C) circuit group constitute one of the first mode and the second mode depending on the state of the mode control signal; ', among them, During the operation of the first mode, the shame circuit is configured to be connected to a parallel interconnection of one or more memory modules; and wherein during operation of the second mode, the (8) circuit group constitutes : a differential serial interconnect for connecting to one or more buffer units, each unit group forming a buffer from which the memory of the one or more buffer units is being read from the one or more buffer units Body data. String: Please refer to the computer system of the 16th item of the range ‧ where each individual j interconnect contains a plurality of differential bidirectional f-material domain roads #, each bidirectional data signal path group constitutes a transmission inverse 77 Xuliu-zhan λ Fu Feng The given buffer is between the given buffer unit and the memory controller. 8. The power-to-parallel interconnection of the 16th article of the patent application includes a differential command message, the parent individual P 7 Λ said path, the differential command signal path 94122 48 200832406 group constitutes the command information to be transmitted from the memory control To a given buffer unit in the one or more buffer units. A computer system of claim 6 of the patent scope, including a configuration unit _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ This mode selects a signal for the I/O circuit. A computer system as claimed in claim 16, wherein each individual serial interconnect operates at a first data transfer rate, and the parallel interconnection operates at a second data transfer rate, wherein the first data transfer rate Faster than the second transfer rate. 21. In the computer system of claim 2, wherein each of the individual serial interconnects comprises a differential clock signal path, the differential clock signal path group constitutes a transfer clock from the memory controller to the _ 冲: 元: a given buffer unit, wherein each of the differential clock signals operates at the first data transfer rate. 22. The computer system of claim 2, wherein the parallel interconnection comprises one or more clock signal paths, each of the clock signal path groups forming a second clock signal from the memory control To the one or more memory pole sets, the second clock signal operates at the second data transfer rate. [23] The computer system of claim 16, wherein the parallel interconnection comprises: configuring a plurality of bidirectional data signal paths, each of the bidirectional data signal path groups forming a transfer data to the memory controller and The one of the 94122 49 200832406 or the special modules in the plurality of memory modules; the plurality of bidirectional data selection communication number paths, the group composition transmission data strobes to the memory controller and the one or more memory modules The special module room in the group '; and 'a plurality of unidirectional addresses and command signal paths, the group composition address and command information from the memory controller to the one or more body modules. The computer system of claim 16, wherein each of the individual serial interconnections comprises a plurality of downlink differential one-way signal paths, each of the downlink differential one-way signal path groups forming a transmission data and command information from ΧThe = body controller to the one or more buffer units. 25. In the computer system of claim 24, each of the individual serial interconnects includes a downlink unidirectional differential clock signal path, and the downlink unidirectional differential clock signal path group constitutes a serial serial clock signal. From the memory controller to each of the one or more buffer units. _ 26 · The computer system of claim 16 of the patent scope, wherein each individual serial interconnection comprises a complex rainbow line differential unidirectional subtraction path, and each of the uplink differential one-way signal path groups constitutes a transmission data and cyclic redundancy The code (crc) is greeted from one of the one or more buffer units to the memory controller. The computer of claim 16 of the patent scope, wherein each individual and column interconnection includes an uplink one-way differential clock signal path, and the uplink one-way + $ pulse Dfl 5 Tiger Road & group constitutes a serial serial clock signal From the one or more buffer units to the memory controller. 94122 50