TW201017779A - Manufacturing process for improvement on warpage of molded packaging parts in fields of semiconductors and photo-electrics - Google Patents
Manufacturing process for improvement on warpage of molded packaging parts in fields of semiconductors and photo-electrics Download PDFInfo
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- TW201017779A TW201017779A TW097139804A TW97139804A TW201017779A TW 201017779 A TW201017779 A TW 201017779A TW 097139804 A TW097139804 A TW 097139804A TW 97139804 A TW97139804 A TW 97139804A TW 201017779 A TW201017779 A TW 201017779A
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- warpage
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 230000006872 improvement Effects 0.000 title abstract description 5
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000008569 process Effects 0.000 claims abstract description 19
- 238000000465 moulding Methods 0.000 claims abstract description 15
- 230000005693 optoelectronics Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 2
- 238000003723 Smelting Methods 0.000 claims 2
- 238000001816 cooling Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000007731 hot pressing Methods 0.000 abstract 2
- 238000005538 encapsulation Methods 0.000 abstract 1
- 238000005520 cutting process Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 229920003023 plastic Polymers 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010330 laser marking Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 230000000153 supplemental effect Effects 0.000 description 1
- 230000008961 swelling Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000011179 visual inspection Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
Abstract
Description
201017779 六、發明說明： 【發明所屬之技術領域】 —本發明係錢於—種半導體及光電領域縣模壓後構裝 兀=鍾曲改善製程’尤其是指一種不僅可有效改善半導體於封 裝核壓過程後所產生的想曲現象之元件收縮不均勾，而發生内 力w成元件易文到外在環境如溫度、財、壓力等因素影 •響’在長時間後出現變形與破裂，大幅降低產品的生命週期'， • 錄大幅降低該模壓後之構裝製作成本，而雜整體施行使用 上更增實用魏特性的半導體及光電賴縣難後構裝元 件翹曲改善製程創新設計者。 【先前技術】 —按’近幾年來由於半導體及光電領域產品發展趨勢朝輕、 =、短、小之方向邁進，促使IC〔 Integrated Circuit〕之 設計朝向輸入/輸出〔1/0〕數變多、功能增加及尺寸變小之方 向^展；半導體構裝的設計需考慮電性功能、散熱性能、製造 可罪度及結構完整〔structural integrity〕，而所謂的半導 體構裝’即將半導體元件外加以包裝倾，目的為完成IC晶 片與”他必要之電路零件的組合，以傳遞電能與電路訊號、提 供散熱途徑、承载與結構保護等功能，良好的構裝品質，有助 於提昇散熱效率、減低熱應力衍生造成破壞、提高產品可靠产 與生命周期。 〇 口 *^ 半導體及先電領域構裝使用的材料包括陶瓷與塑膠，塑膠 201017779 構裝的散離、耐雛、密雌與可缝低_賴裝，但1 能提供小型化構裝、低成本、製造簡單、適合自動化生產等優 點且IW著材料與製程技術的進步大幅提升其可靠度之後，塑 膠構裝已成為當今使用最多的構裝技術。 /、中’該半導體1C及光電領域構裝之製程步驟依序如下·· 1.晶片切割〔DieSaw〕：其目的係將前製程加工完成之晶圓上 • 的晶粒切割分離，以利後續階段使 ·- 用。 2·黏晶〔Die Bond〕：其為將晶片固定在導線架之晶片座上的 製程步驟’通常使用高分子黏著劑黏結。 3. 銲線〔Wire Bond〕：其係將晶粒上的接點以極細的金線連接 到導線架之内接腳，進而藉此將IC晶 粒之電路訊號傳輸至外界。 4. 封膠〔Molding〕：其主要目的為防止濕氣由外部侵入、以機 藝械方式支持導線、内部產生熱量之去除及 提供能夠手持之形體’其過程為將導線架 置於框架上並預熱，再將框架置於壓模機 的構裝模上，再以樹脂充填並待之硬化。 5. 剪切〔Trim〕：其目的為將導線架上構裝完成之晶粒獨立分 開’並把不需要的連接用材料及部份凸出之 樹脂切除。 6·成形〔Form〕：其目的為將外引腳壓成各種預先設計好之形 201017779 狀’以便於裝置在電路板上使用。 7·印字〔Mark〕：其目的在於註明商品之規格及製造者等資訊， 主要以著墨轉印或雷射刻印的方式印於膠體 上。 8·檢驗〔Inspection〕：其目的為確定構裝完成之產品是否合 使用，項目包括諸如：外引腳之平整 • 性、共面度、腳距、印字是否清晰及 • 膠體是否有損傷等的外觀檢驗。 但是一般傳統之半導體及光電領域封裝模壓製程方式，由 於其_元件的觸脹雜不同，縣巾溫度賴化會造成模 壓後構裝元件產生龜曲現象，進而導致導腳不共面、比晶片 的破壞、構裝膠體的破裂、晶片座與膠體介面間的脫層，影響 與印刷電路板的組裝、降低其品質。 同時，對於模壓後之構裝製作成本，業者即在構裝之成型 籲 製程占別中，所需使用之切割半導體構裝元件的自動化送料切 割機〔Jig SHigulation〕，也可能由於該構裝體趣曲度太高， 將使得無法透過自動送料機系統〔Handier〕自動傳送，或盖 法讓構裝體建立足夠真空於切割平台上，所以業者將需另外將 此構裝讀概於_帶〔uv—細〕上，以能在手動〔τ叩 /刀機上蝴，且在切割過程中也能保持強勁的黏著力， 使得能牢牢_住魏元件避免飛片 ，而切割完成後再以紫外 、射使得其轉力下降，而令剝離過程不至於讓構裝元件產 201017779 生異常。 …:而’上述UV-膠帶〔uv-Tape〕雖可達到鍾曲構裝元件 之固定’使得其可以進行補成型之義功效，但於其實際操 作施行使Μ上卻發現，因需於賴賴另㈣附，膠帶 〔W Tape〕使仔造成其整體構裝製程的成本支出，對於業者 而吕係為-大貞擔，致令其整體在施行使壯仍存有改進之空 間。 二 緣疋，發明人有鑑於此，秉持多年該相關行業之豐富設計 開發及實際製作經驗，針龍有之結構及缺失料以研究改 良’因而發明出一種半導體及光電領域封裝模壓後構裝元件翹 曲改善製程’以期達到更佳實用價值性之目的者。 【發明内容】 本發明半導體及光電領域封裝模壓後構裝元件翹曲改善 製程，其主要係於該半導體構裝之製造中，於該構裝體先以壓 模之熱模進行加熱加壓，再換由冷模進行冷卻加壓，以讓構裝 體成形平整狀態，不會產生翹曲現象；藉此，不僅可有效改善 半導體於封裝過程中所產生的翹曲現象，且能大幅降低該半導 體製作成本’而在其整體施行使用上更增實用功效特性者。 【實施方式】 為令本發明所運用之技術内容、發明目的及其達成之功效 有更完整且清楚的揭露，茲於下詳細說明之，並請一併參閱所 揭之圖式及圖號： 201017779 首先，本發明於半導體及光電領域模壓後構裝製程中，請 參閱第-圖本發明之製雜作示細㈠卿，錢將該構裝 體（1)固定於固定冶具上，以壓模⑵之熱模⑻進行加熱加 壓’且其加熱溫度、加壓壓力及其加壓咖可錢行調整控 制’而該固定冶具需能有適當之軟硬度，以克服在麵⑵下 壓過程中，贱破壞構裝體⑴之球閘陣列封農〔BGABau Grid e201017779 VI. Description of the invention: [Technical field to which the invention pertains] - The invention relates to the invention of post-molding of a semiconductor and optoelectronic field, and the improvement process of the semiconductor is particularly effective in improving the semiconductor in the package nuclear pressure. After the process, the components of the phenomenon of the songs are not uniformly shrunk, and the internal forces are generated into the external environment, such as temperature, wealth, pressure, etc., and the deformation and cracking occur after a long time. The life cycle of the product', • significantly reduced the manufacturing cost of the molding after the molding, and the use of the semiconductors and the photovoltaics to improve the manufacturing process. [Prior Art] - In recent years, due to the development trend of products in the semiconductor and optoelectronic fields, the trend toward light, =, short, and small has increased the design of IC [Integrated Circuit] towards input/output [1/0]. The function is increased and the size is reduced. The design of the semiconductor package needs to consider electrical functions, heat dissipation performance, manufacturing sin and structural integrity, and the so-called semiconductor package is to add semiconductor components. The purpose of packaging is to complete the IC chip and the combination of the necessary circuit components to transmit electrical energy and circuit signals, provide heat dissipation, load bearing and structural protection, etc. Good construction quality helps to improve heat dissipation efficiency and reduce The thermal stress is degenerated to cause damage and improve the reliable production and life cycle of the product. 〇口*^ The materials used in the semiconductor and electric field construction include ceramics and plastics, and the plastic 201017779 structure is scattered, resistant to chicks, dense female and sewable. _ 赖, but 1 can provide small-scale construction, low cost, simple manufacturing, suitable for automated production and other advantages and IW materials and systems After the advancement of process technology has greatly improved its reliability, plastic packaging has become the most widely used assembly technology. /, The process steps of the semiconductor 1C and optoelectronic field are as follows: 1. Wafer cutting [DieSaw] 〕: The purpose is to separate the die on the wafer processed by the pre-process to facilitate the subsequent stages. 2. Die Bond: It is the wafer holder for fixing the wafer to the lead frame. The process step 'is usually bonded with a polymer adhesive. 3. Wire Bond: Connects the contacts on the die to the inner pins of the lead frame with a very thin gold wire, thereby using the IC The circuit signal of the die is transmitted to the outside world. 4. Molding: Its main purpose is to prevent moisture from intruding from the outside, mechanically supporting the wire, removing heat inside and providing a body capable of holding it. In order to place the lead frame on the frame and preheat it, the frame is placed on the mold of the molding machine, and then filled with resin and hardened. 5. Trim: The purpose is to place the lead frame Finished grain Separate 'and remove the unneeded connection material and partially protruding resin. 6. Forming: The purpose is to press the outer pin into various pre-designed shapes 201017779' to facilitate the device on the board 7. Use [Mark]: The purpose is to indicate the specifications of the product and the manufacturer and other information, mainly printed on the colloid by ink transfer or laser marking. 8. Inspection [Inspection]: Its purpose is to determine Whether the finished product is used or not, the project includes such things as: flatness of the outer pin, coplanarity, pitch, clearness of the print, and • visual inspection of the gel. However, the conventional semiconductor and optoelectronic fields In the package molding process, due to the different swelling and disintegration of the components, the temperature of the canopy will cause the tortuosity of the molded components after molding, which leads to the coplanarity of the guide pins, the destruction of the wafer, and the breakdown of the colloid. The delamination between the wafer holder and the colloid interface affects the assembly of the printed circuit board and reduces its quality. At the same time, for the manufacturing cost of the molded package, the manufacturer is in the process of forming the molding process, and the automatic feeding and cutting machine (Jig SHigulation) for cutting the semiconductor component is required, and may also be interesting due to the structure. The curvature is too high, which will make it impossible to automatically transfer through the automatic feeder system [Handier], or the cover method will allow the structure to establish enough vacuum on the cutting platform, so the operator will need to read this structure in addition to the _ belt [uv - fine), in order to be able to manually [τ叩 / knife on the butterfly, and also maintain a strong adhesion during the cutting process, so that the _ live Wei components to avoid flying, and after the completion of the cutting The shot causes the rotation force to drop, and the stripping process does not cause the component to produce an abnormality in 201017779. ...: And 'the above-mentioned UV-tape [uv-Tape] can achieve the fixed function of the bell-curtain component, so that it can perform the effect of supplemental molding, but it is found in the actual operation of the operation, but it is necessary to rely on Lai (4) attached, tape [W Tape] makes the cost of its overall construction process, and for the industry, Lu is a big burden, so that there is still room for improvement in its overall exercise. Eryuan, the inventor has in view of this, and has been rich in design and development and practical production experience of the relevant industry for many years, the structure and missing materials of the needle dragon have been researched and improved, thus inventing a packaged molded component in the semiconductor and optoelectronic field. Warping improves the process's purpose in order to achieve better practical value. SUMMARY OF THE INVENTION In the semiconductor and optoelectronic field, the package warping component warpage improvement process is mainly in the manufacture of the semiconductor package, and the structure is first heated and pressurized by a hot mold of a stamper. The cooling mold is cooled and pressurized to form the flat body in a flat state without warping; thereby, not only the warpage phenomenon of the semiconductor during the packaging process but also the semiconductor can be greatly reduced. The cost of production is 'and the utility model is more effective in its overall implementation. [Embodiment] For a more complete and clear disclosure of the technical content, the purpose of the invention and the effects thereof achieved by the present invention, the following is a detailed description, and please refer to the drawings and drawings: 201017779 First of all, in the semiconductor and optoelectronic field molding process, please refer to the first embodiment of the present invention (1), the money, the structure (1) is fixed on the fixed tool, to the die (2) The hot mold (8) is heated and pressurized 'and its heating temperature, pressurization pressure and its pressure coffee can be adjusted and controlled' and the fixed tool needs to have appropriate soft hardness to overcome the pressing process in the surface (2) In the middle, the ballast array of the damaging structure (1) is closed [BGABau Grid e
Array〕的球體⑻功能完整性，定冶具以龍材質為 佳。 而待將構賴⑴以鏡⑻進行蝴加職，請再一併 參閱第二圖本發明之製程動_賴（二)所*，其再換由該壓 模（2)之冷模(22)對構裝體（！）進行冷卻加壓。 如此一來’即能藉由壓模⑵之熱模⑻及冷模⑽對構 裝體⑴依序域，令該構錢⑴成形平整狀態，不會產生龜 曲現象’以便於業者對構裝體⑴進行切割之作業，達到節省 作業程序與成本之目的。 然而前述之實施例或圖式並非限定本發明之產品結構或 使用方式，任何賴技術倾巾具有财蝴者之適當變化或 修飾’皆應視為不脫離本發明之專利範脅。 错以上所述，本發明之元件組成與使用實施說明可知， ^發^與财簡她之下，本伽由於胁賴壓後構裝體 先以塵歡細物加熱祕，雜岭顧行冷卻加遷，以 讓構裝體卿平整狀態’不會產生_縣，使得其不僅可有 8 201017779 效改善半箱於封裝過針所產生的誠現象，且能大幅降低 該半導體f作成本在其整體施行使社更增實用功效特性 者。 綜上所述，本發明實施例確能達到所預期之使用功效，又 其所揭露之具體構造’不僅未曾見諸於同類產品中，亦未曾公 開於申請前，誠已完全符合專利法之規定與要求，爰依法提出 發明專利之申請，懇請惠予審查，並賜准專利，則實感德便。 201017779 【圖式簡單說明】 第一圖：本發明之製程動作示意圖（一） 第二圖：本發明之製程動作示意圖（二)The Array's sphere (8) is functionally perfect, and the sizing tool is preferably made of dragon material. However, the structure (1) is to be added to the mirror (8), please refer to the second diagram of the process of the present invention, which is replaced by the cold mold of the stamper (2). ) Cooling and pressurizing the structure (!). In this way, the hot body (8) and the cold mold (10) of the stamper (2) can be used to sequence the structure (1), so that the structure (1) is formed into a flat state without causing a tortuosity phenomenon. (1) The work of cutting is carried out to save operating procedures and costs. However, the foregoing embodiments or drawings are not intended to limit the structure or mode of use of the present invention, and any appropriate variations or modifications of the technical sprinklers are considered to be without departing from the patent scope of the present invention. In the above, the component composition and the implementation description of the present invention can be seen that, under the pressure of the hair and the financial simplicity, the gamma is cooled by the dusty material after the pressure is applied, and the cooling is cooled. Adding and moving, so that the structure of the body is flat, 'will not produce _ county, so that it can not only have 8 201017779 effect to improve the honest phenomenon caused by the half-box in the package needle, and can significantly reduce the cost of the semiconductor f in its The overall application of the exercise company to increase the utility characteristics. In summary, the embodiments of the present invention can achieve the expected use efficiency, and the specific structure disclosed therein has not only been seen in similar products, nor has it been disclosed before the application, and has fully complied with the provisions of the Patent Law. And the request, the application for the invention of a patent in accordance with the law, please forgive the review, and grant the patent, it is really sensible. 201017779 [Simple description of the diagram] First diagram: schematic diagram of the process of the invention (1) Second diagram: schematic diagram of the process of the invention (2)
【主要元件符號說明】 (1) 構裝體 (11) 球體 (2) 壓模 (21) 熱模 (22) 冷模[Explanation of main component symbols] (1) Structure (11) Sphere (2) Stamper (21) Hot mold (22) Cold mold
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097139804A TW201017779A (en) | 2008-10-16 | 2008-10-16 | Manufacturing process for improvement on warpage of molded packaging parts in fields of semiconductors and photo-electrics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097139804A TW201017779A (en) | 2008-10-16 | 2008-10-16 | Manufacturing process for improvement on warpage of molded packaging parts in fields of semiconductors and photo-electrics |
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| Publication Number | Publication Date |
|---|---|
| TW201017779A true TW201017779A (en) | 2010-05-01 |
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| TW097139804A TW201017779A (en) | 2008-10-16 | 2008-10-16 | Manufacturing process for improvement on warpage of molded packaging parts in fields of semiconductors and photo-electrics |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107891255A (en) * | 2017-12-19 | 2018-04-10 | 晋江联兴反光材料有限公司 | A kind of electro-deposition stress test piece and preparation method thereof |
| CN110491791A (en) * | 2019-06-28 | 2019-11-22 | 江苏长电科技股份有限公司 | A kind of mold and method improving ultra-thin plastic-sealed body product warpage |
| CN111774437A (en) * | 2020-07-28 | 2020-10-16 | 宁波江丰电子材料股份有限公司 | Pressurizing and shaping method for target material after welding |
| WO2023226416A1 (en) * | 2022-05-25 | 2023-11-30 | 上海闻泰电子科技有限公司 | Preparation method for chip, and chip |
-
2008
- 2008-10-16 TW TW097139804A patent/TW201017779A/en unknown
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107891255A (en) * | 2017-12-19 | 2018-04-10 | 晋江联兴反光材料有限公司 | A kind of electro-deposition stress test piece and preparation method thereof |
| CN107891255B (en) * | 2017-12-19 | 2024-05-17 | 晋江联兴反光材料有限公司 | Electrodeposition stress test piece and manufacturing method thereof |
| CN110491791A (en) * | 2019-06-28 | 2019-11-22 | 江苏长电科技股份有限公司 | A kind of mold and method improving ultra-thin plastic-sealed body product warpage |
| CN111774437A (en) * | 2020-07-28 | 2020-10-16 | 宁波江丰电子材料股份有限公司 | Pressurizing and shaping method for target material after welding |
| CN111774437B (en) * | 2020-07-28 | 2022-04-08 | 宁波江丰电子材料股份有限公司 | Pressurizing and shaping method for target material after welding |
| WO2023226416A1 (en) * | 2022-05-25 | 2023-11-30 | 上海闻泰电子科技有限公司 | Preparation method for chip, and chip |
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