TW201014160A - Miniaturized dual balance wave mixer circuit of tri-wringing wire type circuit construction - Google Patents

Miniaturized dual balance wave mixer circuit of tri-wringing wire type circuit construction Download PDF

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TW201014160A
TW201014160A TW097137430A TW97137430A TW201014160A TW 201014160 A TW201014160 A TW 201014160A TW 097137430 A TW097137430 A TW 097137430A TW 97137430 A TW97137430 A TW 97137430A TW 201014160 A TW201014160 A TW 201014160A
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circuit
signal
balanced
double
input
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TW097137430A
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TWI365597B (en
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Che-Chung Kuo
Huei Wang
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Univ Nat Taiwan
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P5/00Coupling devices of the waveguide type
    • H01P5/08Coupling devices of the waveguide type for linking dissimilar lines or devices
    • H01P5/10Coupling devices of the waveguide type for linking dissimilar lines or devices for coupling balanced lines or devices with unbalanced lines or devices
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03DDEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/02Transference of modulation from one carrier to another, e.g. frequency-changing by means of diodes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Transceivers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

Provided is a miniaturized dual balance wave mixer circuit of a tri-wringing wire type circuit construction adapted to mix high frequency millimeter wave signals with a miniaturized profile. The wave mixer circuit is characterized by employing the circuit layout of a tri-wringing wire type to dispose a pair of dual balance to imbalance voltage circuit units to realize miniaturization. Specifically, the configuration of miniaturized dual balance mixer circuit requires merely 20% of the conventional star type wave mixers.

Description

201014160 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種毫米波(mi 1丨imeter wave,龍趵 電路技術,特別是有關於一種三絞線式電路佈局架構之微 型化雙平衡式混波器電路’其功能為完全等效於傳統之星 型雙平衡式混波器(star DBM,其中dbm ~ double-balanced mixer),可對高頻之毫米波信號提供一 混波功能,但於積體電路的實現上可較傳統之星型雙平衡 ©式混波器更為微型化。 、 【先前技術】 混波器(mixer)為通訊電路系統中一個主要的電路構 件,可用以對一輸入之頻率信號提供一混波作用而輪出一 頻率降低或升高之中頻信號(intermediate frequ加 IF)。此混波過程為將一本地之振盪信號混合至輸入之頻 率尨號,藉此即可產生一降頻或升頻之輸出信號。 〇 於高頻通訊電路系統的應用中,雙平衡式混波器 (double-balanced mixer, DBM)為一種常用之混波器,其 f用之類型例如包括環型雙平衡式混波器(ring卯幻和 星型雙平衡式混波器(s t a r D B M,以下簡稱為”星型混波器 ")。但由於星型混波器具有較佳之操作特性,因此其應用 較為廣泛。星型混波器之名稱中的”星型”(starMf、緣自其 中之微線路(microstrip)所構成之電路架構的形狀有如 幅射之星狀。 然而於積體電路的實現上,星型混波器的一項缺點在 111049 5 201014160 於其架構中的雙式平衡對不平衡變壓電路單元(dual ba lun)具有頗大之體積而需要較大之電路佈局空間,使得 其晶片具有較大之體積尺寸而不符合輕薄短小之規格。 【發明内容】 鑒於以上所述先前技術之缺點,本發明之主要目的便 疋在於φς:供一種二絞線式電路佈局架構之微型化雙平衡 式混波器電路,其可於積體電路的實現上較傳統之星型混 波器更為微型化。 ❾ 於實體構造上’本發明之微型化雙平衡式混波器電路 至少包含以下之電路構件:(Α)一第一雙式平衡對不平衡 變壓電路單元,(Β) —第一雙式平衡對不平衡變壓電路單 元;以及(C)一混波處理電路單元。 本發明之微型化雙平衡式混波器電路於結構上的新 穎之處在於所採用之2個雙式平衡對不平衡變壓電路 元(dual balun)均係建基於一種三絞線式(trifiiar)之 電路佈局架構,其中採用—雙層式電路基板來配置6條分 佈式之傳輸線路(distributed transmission lines),且 令各層之的3條傳輸線路之間均構成—馬佳得式之平衡 對不平衡轉換器(Marchand balun)而將輸人信號經變壓 作用而轉換成2組共4個差分之輸出信號。 相較於傳統之星型混波器,本發明的優點在於其所採 =之三絞線式之電路佈局架構可顯著地令整體之混波器 型路以更為微型化的方式來實現。具體而言,此微 w衡式混波H電路所需的佈局面積僅為傳統之星 111049 6 201014160 型混波益的約20%。此優點顯見本發明較先前技術具有更 佳之進步性及實用性。 【實施方式】 以下即配合所附之圖式,詳細揭露本發明之三絞線式 電路佈局架構之微型化雙平衡式混波器電路之實施例。本 發明以下將簡稱為"微型化雙平衡式混波器電路π。 本發明的功能 第1圖即顯示本發明之微型化雙平衡式混波器電路 ❹10的輸入輸出功能模型(input/〇utput functi〇nal model)。如圖所示,本發明之微型化雙平衡式混波器電路 10係應用於處理一輸入之高頻信號RF,並利用一本地之 振盪信號L0來對該輸入之高頻信號RF提供一混波作用, 以藉此而輸出一頻率降低或升高之中頻信號201014160 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a millimeter wave (mi 1丨imeter wave), in particular to a miniaturized double balance of a tri-stranded circuit layout architecture The mixer circuit's function is completely equivalent to the traditional star double balanced mixer (star DBM, dbm ~ double-balanced mixer), which can provide a mixing function for high frequency millimeter wave signals. However, the realization of the integrated circuit can be more miniaturized than the traditional star-type double balanced© type mixer. [Prior Art] A mixer is a main circuit component in a communication circuit system, and can be used. Providing a mixing effect on an input frequency signal and rotating a frequency to decrease or increase an intermediate frequency signal (intermediate frequ plus IF). This mixing process is to mix a local oscillating signal to the input frequency apostrophe. In this way, a down-converted or up-converted output signal can be generated. In the application of high-frequency communication circuit systems, a double-balanced mixer (DBM) is a commonly used mixer. The types used for f include, for example, a ring-type double-balanced mixer (ring DB and star double-balanced mixer (star DBM, hereinafter referred to as "star mixer"). The wave device has better operational characteristics, so it is widely used. The shape of the "star" (starMf, the microstrip from the name of the star mixer) is shaped like a radiation. Star-shaped. However, in the realization of the integrated circuit, a disadvantage of the star-type mixer is that the double-balanced unbalanced transformer unit (dual ba lun) in its architecture has a large volume in the 111049 5 201014160 However, a larger circuit layout space is required, so that the wafer has a larger volume size and does not conform to the specifications of the light and thin. [Invention] In view of the above-mentioned shortcomings of the prior art, the main purpose of the present invention is that φς: for A miniaturized double balanced mixer circuit with a twisted-pair circuit layout architecture, which can be more miniaturized in the implementation of an integrated circuit than a conventional star-type mixer. The miniaturized double balanced mixer circuit of the invention comprises at least the following circuit components: (Α) a first dual balanced to unbalanced transformer circuit unit, (Β) - a first dual balanced to unbalanced transformer circuit And (C) a hybrid processing circuit unit. The novelty of the miniaturized double balanced mixer circuit of the present invention is the two dual balanced to unbalanced transformer circuit elements (dual) Balun) is based on a trifiiar circuit layout architecture in which two distributed circuit boards are used to configure six distributed transmission lines, and three transmission lines of each layer are used. The roads are composed of a Majiadian balanced-to-unbalance converter (Marchand balun) which converts the input signal into two groups of four differential output signals. Compared with the conventional star type mixer, the advantage of the present invention is that the circuit layout structure of the three-strand type can significantly realize the overall mixer mode in a more miniaturized manner. Specifically, the layout area required for this micro-Wave-type mixed-wave H circuit is only about 20% of that of the conventional star 111049 6 201014160. This advantage is evident in the fact that the present invention is more progressive and practical than prior art. [Embodiment] Hereinafter, an embodiment of a miniaturized double balanced mixer circuit of the three-stranded circuit layout structure of the present invention will be disclosed in detail in conjunction with the accompanying drawings. The present invention will hereinafter be referred to as " miniaturized double balanced mixer circuit π. Function of the Present Invention Fig. 1 shows an input/output function model (input/〇utput functi〇nal model) of the miniaturized double balanced mixer circuit 本10 of the present invention. As shown, the miniaturized double balanced mixer circuit 10 of the present invention is applied to process an input high frequency signal RF and utilizes a local oscillating signal L0 to provide a mixed frequency of the input high frequency signal RF. Wave action, thereby outputting a frequency to decrease or increase the intermediate frequency signal

(intermediate frequency);亦即於降頻應用中,IF = RF -L0 ;而於升頻應用中,則if = RF + L0。 本發明的構造 φ 如第2圖所示,於實體構造上,本發明之微型化雙平 衡式混波器電路10至少包含:(A)一第一雙式平衡對不平 衡變壓電路單元100; (β) 一第二雙式平衡對不平衡變壓 電路單元200;以及(C) 一混波處理電路單元3〇〇。以下即 首先分別說明此些電路構件的個別屬性及功能。 (Α)第一雙式平衡對不平衡變壓電路單元1〇〇 第一雙式平衡對不平衡變壓電路單元1〇〇具有一輸 入端L0、一第一輸出端L01( + )、一第二輸出端L〇K )、 111049 7 201014160 第一輸出端L02 ( + )、和一第四輸出端L02 (-);且其輸 入端L〇係連接至本地振盪信號輸入端L0,並分別從其4 個輸出端輪出4個經平衡對不平衡變壓轉換後的輸出信 號[L〇l( + ),L01 ㈠,L〇2( + ),L02(-)];其巾[L〇1 ⑴, L〇1( —)]為一對相位差為180度之振盪信號,而[L〇2( + ), L〇2(-)]亦同樣地為一對相位差為18〇度之振盪信號。 於具體實施上,此第一雙式平衡對不平衡變壓電路單 元100係採用如第3A圖所示之的電路架構,其包括6條 ❾分佈式之傳輸線路(distribu1:ed transmissi〇n : 一第一傳輸線路121、一第二傳輸線路122、一第三傳輸 線路123、一第四傳輸線路124、一第五傳輸線路125、 和一第六傳輸線路126。於具體實施上,此6條傳輸線路 (121、122、123、124、125、126)均為一 1/4 波長之微線 路,可構成一馬佳得式之雙式平衡對不平衡轉換器 (Marchand dual balun),其等效電路如第4A圖所示。由 ❹於馬佳得式之雙式平衡對不平衡轉換器為電子業界所習 用及熟知之電路技術,因此於此說明書中將不對其運作方 式作進一步詳細之說明。 於積體電路的實現上,此第一雙式平衡對不平衡變壓 電路單元100之電路佈局的最佳實施方式為採用一種如 第5A-5B圖所示之三絞線式(tri f i lar)之電路佈局架 構。如圖所示,此三絞線式之電路佈局架構係採用一雙層 式電路基板,例如為一雙層式電路基板110,來配置上述 之 6 條傳輸線路(121、122、123、124、125、126)。如第 Π1049 8 201014160 5β圖所示’此雙層式電路基板⑽具有2層電路佈局面’ 包括-第-層電路佈局自U1和一第二層電路佈局面 112’並心包括—接地面113。於具體實施上,此雙層 •式電路基板110例如係採用一商用〇15微米一)之 pHEMT (pseudoraorphic HEMT,其中 HEMT= HighEiectr〇n M〇bi lity Trans i stQr )製程所提供之雙金屬層之石中化嫁 (GaAs)基板來製作。 如第5A圖所示,於此雙層式電路基板11〇中第一 ©傳輸線路12卜第三傳輸線路123、和第五傳輸線路125 係利用一種三絞線式之電路佈局方式來配置於第一層電 路佈局面而第二傳輸線路122、第四傳輸線路^4、 和第六傳輸線路126亦為同樣地利用相同之三絞線式之 電路佈局方式來配置於第二層電路佈局面112。 於第一層電路佈局面lu上,第三傳輸線路123係分 成3個區段’並利用2個跨空之橋接線來將此3個區段串 ©聯成單一條傳輸纟路;❿串聯成-體後之第三傳輸線路 123的第一端123a即用以接收本地振盪信號[〇,而其第 二端123b則用以連通至第二層電路佈局面112上的第四 傳輸線路124。第一傳輸線路121亦被分成3個區段,並 利用2個跨空之橋接線來將此3個區段串聯成單一條傳輸 線路;而串聯成一體後之第一傳輸線路121的第一端121a 即用以輸出L01( + ) ’而其第二端121b則連接至一接地連 通枝131。再接著’第五傳輸線路125亦被分成3個區段, 並利用2個跨空之橋接線來將此3個區段串聯成單一條傳 9 111049 201014160 輸線路;而此串聯成-體後之第五傳輸線路125的第… 125a即用以輸出L〇2( + ),而其第二端12此則連接至一 $ 地連通柱132。 接 ' 於上述之三絞線式電路佈局架構中,第一傳輪綠% 12!和第五傳輸線路125之總長度均為1/4波長,而第_ 傳輸線路m之總長度則可略切1/4>皮長;而各二(intermediate frequency); that is, in down-conversion applications, IF = RF - L0; and in up-conversion applications, if = RF + L0. Structure φ of the present invention As shown in FIG. 2, in the physical configuration, the miniaturized double balanced mixer circuit 10 of the present invention comprises at least: (A) a first dual balanced to unbalanced transformer circuit unit 100 (β) a second dual balanced-to-unbalanced transformer circuit unit 200; and (C) a hybrid processing circuit unit 3〇〇. The individual properties and functions of such circuit components are first described below. (Α) The first dual-balanced-to-unbalanced transformer circuit unit 1〇〇 The first dual-balanced-to-unbalanced transformer circuit unit 1 has an input terminal L0 and a first output terminal L01(+), one The second output terminal L〇K), the 111049 7 201014160 first output terminal L02 (+), and the fourth output terminal L02 (-); and the input terminal L〇 is connected to the local oscillation signal input terminal L0, and respectively Four output signals [E〇l( + ), L01 (1), L〇2( + ), L02(-)] after balancing and unbalanced transformation are rotated from its 4 outputs; 〇1 (1), L〇1(—)] is a pair of oscillation signals with a phase difference of 180 degrees, and [L〇2( + ), L〇2(-)] is also a pair of phase differences of 18〇. Oscillation signal. In a specific implementation, the first dual balanced-to-unbalanced transformer circuit unit 100 adopts a circuit architecture as shown in FIG. 3A, which includes six distributed transmission lines (distribu1:ed transmissi〇n: a first transmission line 121, a second transmission line 122, a third transmission line 123, a fourth transmission line 124, a fifth transmission line 125, and a sixth transmission line 126. In a specific implementation, this 6 The strip transmission lines (121, 122, 123, 124, 125, 126) are all a 1/4 wavelength micro line, which can constitute a Ma Jiade type double balanced balun (Marchand dual balun), The equivalent circuit is shown in Figure 4A. Since the Ma Jiade-type dual balanced-to-balance converter is a circuit technology that is familiar and well-known in the electronics industry, the operation mode will not be further detailed in this specification. In the implementation of the integrated circuit, the best implementation of the circuit configuration of the first dual balanced unbalanced transformer circuit unit 100 is to adopt a twisted pair type as shown in FIG. 5A-5B ( Tri fi lar) circuit layout architecture. As shown in the figure, the three-stranded circuit layout structure uses a two-layer circuit substrate, such as a two-layer circuit substrate 110, to configure the above six transmission lines (121, 122, 123, 124, 125, 126). As shown in Fig. 1049 8 201014160 5β, 'this two-layer circuit substrate (10) has a two-layer circuit layout surface' including - the first layer circuit layout from U1 and a second layer circuit layout surface 112' Including a ground plane 113. In a specific implementation, the double-layer circuit substrate 110 is, for example, a commercially available EM15 micron-pHEMMT (pseudoragoric HEMT, wherein HEMT=HighEiectr〇n M〇bi lity Trans i stQr ) process A bimetal layered GaAs substrate is provided for fabrication. As shown in FIG. 5A, the first transmission line 12, the third transmission line 123, and the fifth transmission line 125 in the two-layer circuit substrate 11 are arranged by a three-strand circuit layout. The first layer circuit layout surface and the second transmission line 122, the fourth transmission line ^4, and the sixth transmission line 126 are also disposed on the second layer circuit layout surface by the same three-strand circuit layout. 112. On the first layer circuit layout surface lu, the third transmission line 123 is divided into three sections' and uses two cross-over bridges to join the three section strings into a single transmission loop; The first end 123a of the third transmission line 123 after receiving the body is used to receive the local oscillation signal [〇, and the second end 123b thereof is used to communicate to the fourth transmission line 124 on the second layer circuit layout surface 112. . The first transmission line 121 is also divided into three sections, and the two sections are connected in series to form a single transmission line by using two inter-vacant bridges; and the first transmission line 121 is integrated in series. The end 121a is for outputting L01(+)' and the second end 121b is connected to a ground communication branch 131. Then, the 'fifth transmission line 125 is also divided into three sections, and the two sections are connected in series to form a single strip transmission 9 111049 201014160 transmission line; The first 125a of the fifth transmission line 125 is for outputting L〇2(+), and the second end 12 thereof is connected to a ground connection post 132. In the above three-stranded circuit layout architecture, the total length of the first transmission green % 12! and the fifth transmission line 125 is 1/4 wavelength, and the total length of the first transmission line m can be omitted. Cut 1/4> skin length; and each two

=⑽、m、125)的寬度均為张而其間隔距離為J Λ於楚一第一傳輸線路121和第五傳輸線路125係分別延伸 ©於第三傳輸線路123的二個旁側,藉此而構成一馬佳 之平衡對不平衡轉換器(Marchand balun)。 " 路二一方:,第二層電路佈局㈣2上的第二傳輸線 =22、第四傳輸線路124、和第六傳輸線路126亦同樣 U於與上述完全相同之三絞線式電路佈局架構(於此 不再作重複之說明)。 (B)第一雙式平衡對不平衡變壓電路單元2⑽ 〇 第一雙式平衡對不平衡變壓電路單元2〇〇的内部實 體電路架構如第3B圖所示,其為完全相同於上述之第一 雙式平衡對不平衡變屢電路單元100,具有-輸入端RF、 ^ 一輸出端RF1⑴、一第二輸出端m㈠、一第三輸 端RF2( + )、和一第四輸出端叮2㈠;且其輸入端 糸連接至輸入之頻率信號RF,並分別從其 4個輸出端輸 4個、,·"平衡對不平衡變壓轉換後的輸出信號[RF1( + ), ()’、RF2( + )’ RF2㈠];其中[RFK + ),RF1(-)]為一 ’相位差為180度之輸出頻率信號,而[RF2( + ),哪㈠] 10 111049 201014160 亦同樣地為一對相位差為i8〇度之輸出頻率信號。 ^電路架構上,如第3B圖所示n 不平衡變愿電路單开9ηη·Α* 飞十銜對 %硌早Α 2〇〇 ,亦包括6條傳 輸線路221、一筮-搞认丄 乐得 一 I t 3線路222、一第三傳輸線路223、 第四傳輸線路224、-第五傳輸線路奶 輸線路226。 弟八傳 於積體電路的實現上,士μ笛_锸斗' τ位 WS^Wir 9ΠΠ u 此第一雙式平衡對不平衡變壓 早70 200上之6條傳輸線路(22卜222、223、224、 © 225、226)於電路佈局上亦係採用如第μ,圖所示之三 =線式之電路佈局架構。由於此第二雙式平衡對不平衡變 電路單it 2GG所採用之三絞線式之電路佈局架構完全 相同於上述之第一雙式平衡對不平衡變壓電路單元 100,因此於此將不對其作重複之說明。 (C)混波處理電路單元3〇〇 混波處理電路單元300係用以接收上述之第一雙式 ❹平衡對不平衡變壓電路單元100和該第二雙式平衡對不 平衡變壓電路單it 2GG所輸出之平衡對*平衡轉換後的 輸出信號[L01( + ),L01(-),L02( + ),L02(-)]和[RF1( + ), RFU-)’ RF2( + ),RF2(-)]’並對其提供一混波處理作用 而獲得所需之輸出中頻信號丨F。 於具體實施上,此混波處理電路單元3〇〇包括以下2 種實施方式:(C1)第4A圖所示之二極體切換式之電路架 構;以及(C2)第4B圖所示之電晶體切換式之電路架構。 (C1)二極體切換式之混波處理電路單元3〇〇 111049 11 201014160 f圖所示,此實施例之混波處理電路單元議 包括-個由4個二極體所構成之整流切換式之電 構。由於此4個二極體的組態完全相同於習知之星型錢 器,因此於此將不對其運作方式作詳細之說明。“ (C2 )電晶體切換式之混波處理電路單元3〇 〇 如第4A圖所示,此實施例之混波處理電路單元_ 包括4組電晶體電路單元;其中每一個電晶體電路單元均 包括一電晶體、一電阻器、和一電容器。 © 由於此4個電晶體電路單元的組態及運作方式完全 相同於習知之混波器,因此於此將不對其運作方式作詳細 之說明。 本發明的操作特性 第6A囷即顯示本發明中的2個三絞線式電路佈局架 構之雙式平衡對不平衡麵電路單元(⑽,)的植入 2耗(insertion loss)相對於卯之頻率的特性曲線圖。 ❹,可看出,於GHz至58 GHz的頻率範圍中,單一 时了紋線式電路佈局架構之雙式平衡對不平衡變壓電路 早疋之植入損耗的模擬結果約為7dBi 85仙,而其實 ,量測結果則為9 dB至u dB ;而振幅差距的模擬結果 和實際量測結果則均為i仳至2仳。 第6 B圖則顯示本發明中的2個三絞線式電路佈局架 冓之雙式平衡對不平衡變壓電路單元(100,200)所產生 ,出L號的相位差(phase di f ference)相對於叩之頻 ^的特性曲線圖。由圖可看出,於20 GHz至50 GHz的 12 111049 201014160 頻率範圍中,輸出信號的相位差的模擬結果約為-182度 至-178度,而其實際量測結果則為_183度至—I?〗度; 亦即相位差均在180±10度的範圍之内。 第7A圖顯示本發明之微型化雙平衡式混波器 之整體的轉換增益(conversi〇ngain)相對於即之頻率的 特性曲線圖。由圖可看出,本發明之微型化雙平衡式混波 器電路10㈣換增益約為-12dB的範圍之内。 第7B圖顯示本發明之微型化雙平衡式混波器電路^ ❹之整體的L〇對RF的隔離度(LO-RF isolation)和L0對 IF的隔離度(L(MF isGlatiQn)相對於之頻率的特性 曲線圖。由圖可看出,本發明之微型化雙平衡式混波器電 路1〇所提供之L0-RF和(L0-IF的隔離度均大於2〇dB。 本發明的優點The widths of =(10), m, and 125) are all Zhang and the separation distance is J. The first transmission line 121 and the fifth transmission line 125 are respectively extended from the two sides of the third transmission line 123. This constitutes a Ma Jia balanced to unbalance converter (Marchand balun). " The second side of the circuit: the second transmission line of the second layer circuit layout (4) 2 = 22, the fourth transmission line 124, and the sixth transmission line 126 are also identical to the above-mentioned three-stranded circuit layout structure (There will be no repeated explanation here). (B) The first dual-balanced-to-unbalanced transformer circuit unit 2(10) 〇 The first dual-balanced-to-unbalanced transformer circuit unit 2〇〇 has an internal physical circuit structure as shown in FIG. 3B, which is identical to the above The first dual balanced to unbalanced repeating circuit unit 100 has an input terminal RF, an output terminal RF1 (1), a second output terminal m (1), a third output terminal RF2 (+), and a fourth output terminal.叮 2 (1); and its input terminal 糸 is connected to the input frequency signal RF, and respectively output 4 from its 4 output terminals, ···“balance the output signal after unbalanced transformer conversion [RF1( + ), ( ), RF2( + )' RF2(1)]; where [RFK + ), RF1(-)] is an output frequency signal with a phase difference of 180 degrees, and [RF2( + ), which (1)] 10 111049 201014160 is also the same The ground is a pair of output frequency signals with a phase difference of i8 degrees. ^ Circuit architecture, as shown in Figure 3B, n unbalanced change circuit single open 9ηη·Α* fly ten title pair %硌早Α 2〇〇, also includes 6 transmission lines 221, a 筮- An I t 3 line 222, a third transmission line 223, a fourth transmission line 224, and a fifth transmission line milk line 226. The younger brother passed on the realization of the integrated circuit, the Shi whistle _ 锸 ' ' τ position WS ^ Wir 9 ΠΠ u This first double balance on the unbalanced transformation pressure 70 200 on the 6 transmission lines (22 222, 223, 224, © 225, 226) The circuit layout is also based on the circuit layout structure of the three-line type as shown in the figure μ. Since the second double-balanced-to-unbalanced variable circuit single-it 2GG adopts a twisted-pair circuit layout architecture which is identical to the first dual-balanced-to-unbalanced transformer circuit unit 100 described above, Do not repeat the description. (C) The mixing processing circuit unit 3 is configured to receive the first dual-balanced-to-unbalanced transformer circuit unit 100 and the second dual-balanced unbalanced transformer circuit. The balance of the output of the single it 2GG is *balanced output signal [L01( + ), L01(-), L02( + ), L02(-)] and [RF1( + ), RFU-)' RF2 ( + ), RF2(-)]' and provide a mixing process to obtain the desired output IF signal 丨F. In a specific implementation, the hybrid processing circuit unit 3 includes the following two embodiments: (C1) the circuit configuration of the diode switching type shown in FIG. 4A; and (C2) the electric power shown in FIG. 4B. Crystal switching circuit architecture. (C1) Dipole switching type mixing processing circuit unit 3〇〇111049 11 201014160 f shows that the mixing processing circuit unit of this embodiment includes a rectifying switching type composed of four diodes Electrical structure. Since the configuration of the four diodes is identical to the conventional star currency, the operation of this diode will not be described in detail here. "(C2) transistor switching type mixing processing circuit unit 3, as shown in Fig. 4A, the mixing processing circuit unit_ of this embodiment includes four sets of transistor circuit units; each of the transistor circuit units It includes a transistor, a resistor, and a capacitor. © Since the four transistor circuit units are configured and operated in exactly the same way as the conventional mixer, their operation will not be described in detail here. The operating characteristic of the present invention is shown in FIG. 6A, which shows the implantation loss of the double balanced-to-unbalanced surface circuit unit ((10),) of the two triple-stranded circuit layout structures in the present invention. The characteristic curve of the frequency. ❹, it can be seen that in the frequency range of GHz to 58 GHz, the simulation results of the double-balanced pair of balanced circuit layout architectures for the unbalanced transformer circuit early in the frequency range of GHz to 58 GHz About 7dBi 85 sen, in fact, the measurement results are 9 dB to u dB; and the simulation results of the amplitude difference and the actual measurement results are i 仳 to 2 仳. Figure 6 B shows the invention 2 twisted pair circuit layout The double-balanced pair is generated by the unbalanced transformer circuit unit (100, 200), and the phase difference of the L number is plotted against the frequency spectrum of the 叩. As can be seen from the figure, In the frequency range of 12 111049 201014160 from 20 GHz to 50 GHz, the simulation result of the phase difference of the output signal is about -182 degrees to -178 degrees, and the actual measurement result is _183 degrees to -I? degrees; That is, the phase difference is within the range of 180 ± 10 degrees. Fig. 7A is a graph showing the conversion gain (conversi〇ngain) of the entire miniaturized double-balanced mixer of the present invention with respect to the frequency. It can be seen that the miniaturized double balanced mixer circuit 10 (4) of the present invention has a gain of about -12 dB. Fig. 7B shows the miniaturized double balanced mixer circuit of the present invention. L〇 is the isolation of RF (LO-RF isolation) and the isolation of L0 from IF (L (MF isGlatiQn) is a characteristic curve with respect to the frequency. It can be seen from the figure that the miniaturized double balanced hybrid of the present invention The L0-RF and (L0-IF isolation) provided by the wave circuit 1〇 are both greater than 2〇dB. The advantages

-相較於傳統之星型本發明的優點在於採用一 種一纹線式之電路佈局架構來配i 2個雙式平衡對不平 ,變墨電路單元(1〇〇, )中的6條傳輸線路因此可顯 耆地以更為微魏的方式來實現。具^言,傳統之星型 混波器所需㈣局面㈣為1/2波長时方,財發明所 而的佈局面積難約為1/6波長的平方。換言之,本發明 佈局面積僅為傳統之星型混波器的約20%。此優點 顯見本發明較先前技術具有更佳之進步性及實用性。 H 本發明之較佳實施例而已,並非用以限 :塵1!之實質技術内容的範圍。本發明之實質技術内容 廣義地定義於下述之中請專利中。若任何他人所完 111049 13 201014160 成之技術實體或方法與下述之中請專利範圍所定義 Π、或是為一種等效之變更,均將被視為概括於本 發明之申請專利範圍之中。 + 【圖式簡單說明】 第1圖為一功能示意圖,用-出功能模型; —的輪入/輪 構;第2圖為-架構示意圖1以顯示本發明的基本架 © 第3A圖為-電_,用以顯示本 雙式平衡對不平衡變壓雷路木用之第— 了付W懸電路早几的微線路電 第3Β圖為一電路圖,用 架構, 雙式=對不平衡變㈣路單元線之第二 平衡單:式 實施例的等效電路;心皮處理電路單元之一種 第4B圖為一電路圖’用以顯 平衡變壓電路單元及 7用之雙式 種實施例的等效電路; 电峪早兀之另一 第5A圖為一平面結構示意圖 2個雙式平衡對不平衡變壓 用^顯示本發明中的 上所採用之三絞線式之電路佈電局^於積體電路之實現 第5B圖為一剖面結構示意圖,^ 之二絞線式之電路佈局架構的剖面形離了不第5A圖所示 第6A圖為一特性曲線圖 :, ,員不本發明所採用之 111049 201014160 三絞線式電路佈局架構之雙式平衡對不平衡變壓電路單 元的植入損耗相對於輸入信號頻率的特性曲線; 早 第6B圖為一特性曲線圖,用以顯示本發明所採用之 三絞線式電路佈局架構之雙式平衡對不平衡變壓電路單 兀之輸出信號的相位相對於輸人信號頻率㈣性曲線丨 第7A圖為一特性曲線圖,用以顯示本發明於整體上 7轉換增盈(conversic)n gain)相對於RF之頻率的特性曲 線, ❹ 帛7β圖為-特性曲線圖,用以顯示本發明於整體上 =對…的隔離度相對於RF之頻率的特性整曲體: 【主要元件符號說明】 10 本發明之微型化雙平衡式混波 100 第一雙式平衡對不平衡變壓電 110 雙層式電路基板 111 第一層電路佈局面 112 第二層電路佈局面 113 接地面 121 第一傳輪線路 121a 第一傳輸線路之第_ -端 121b 第一傳輸線路之第_ 二端 122 弟一傳輸線路 123 第二傳輪線路 123a 第二傳輪線路之第一 -端 123b 第二傳輪線路之第_ 二端 ❹ 111049 15 201014160 124 第四傳輸線路 125 第五傳輸線路 125a 第五傳輸線路之第一端 125b 第五傳輸線路之第二端 126 第六傳輸線路- 131 接地連通柱 132 接地連通柱 200 第二雙式平衡對不平衡變壓電路單元(dual balun) ❹221 第一傳輸線路 222 第二傳輸線路 223 第三傳輸線路 224 第四傳輸線路 225 第五傳輸線路 226 第六傳輸線路 300 混波處理電路單元 ❿ 16 111049- Compared with the conventional star type, the present invention has the advantage of adopting a one-line circuit layout architecture to match i 2 double balanced pairs, and 6 transmission lines in the ink circuit unit (1〇〇, ) Therefore, it can be realized in a more micro-wei manner. In other words, the traditional star-type mixer requires (4) the situation (4) is 1/2 wavelength, and the layout area of the invention is difficult to be about 1/6 wavelength square. In other words, the layout area of the present invention is only about 20% of that of a conventional star type mixer. This advantage is apparent from the fact that the present invention is more progressive and practical than the prior art. The preferred embodiment of the present invention is not intended to limit the scope of the technical content of the dust. The technical contents of the present invention are broadly defined in the following patents. If any other person's technical entity or method is defined by the scope of the patent, or an equivalent change, it will be considered to be within the scope of the patent application of the present invention. . + [Simplified description of the drawings] Fig. 1 is a functional diagram, the function model is used, the wheel/wheel structure is used, and the second diagram is the architecture diagram 1 to show the basic frame of the present invention. Electricity_, used to show the balance of the dual-balanced and unbalanced transformers for the use of the road - the third line of the micro-circuit electricity of the W-suspended circuit is a circuit diagram, with the architecture, double = unbalanced (4) The second balance of the unit cell line: the equivalent circuit of the embodiment; the 4B of the cardioid processing circuit unit is a circuit diagram 'for the balanced balance transformer unit and the double-type embodiment for 7 The equivalent circuit; the other 5A picture of the electric 峪 为 is a schematic diagram of a plane structure; 2 double-balanced versus unbalanced transformers ^ shows the circuit of the three-stranded circuit used in the present invention ^ The realization of the integrated circuit is shown in Fig. 5B as a cross-sectional structure. The cross-section of the circuit layout structure of the two-stranded type is not shown in Fig. 5A. Figure 6A is a characteristic graph: The 111049 201014160 three-stranded circuit layout architecture adopted by the invention is balanced by two The characteristic curve of the implant loss of the balanced transformer unit relative to the frequency of the input signal; FIG. 6B is a characteristic graph for showing the double balance imbalance of the three-strand circuit layout structure used in the present invention. The phase of the output signal of the transformer circuit unit is relative to the frequency of the input signal (four). 丨 Figure 7A is a characteristic graph showing the overall conversion of the invention to the conversic n gain relative to the RF. The characteristic curve of the frequency, ❹ β 7β is a characteristic curve for showing the characteristic of the present invention as a whole with respect to the isolation of the frequency with respect to the frequency of the RF: [Main component symbol description] 10 The present invention Miniaturized double balanced hybrid 100 First double balanced unbalanced piezoelectric 110 Double layered circuit substrate 111 First layer circuit layout surface 112 Second layer circuit layout surface 113 Ground plane 121 First transmission line 121a The first transmission end of the first transmission line _-end 121b the second transmission end of the first transmission line 122 the second transmission line 123 the second transmission line 123a the first transmission end of the second transmission line 123b Road number _ two end ❹ 111049 15 201014160 124 fourth transmission line 125 fifth transmission line 125a fifth transmission line first end 125b fifth transmission line second end 126 sixth transmission line - 131 ground connection column 132 ground Connecting column 200 second double balanced to unbalanced transformer circuit unit (dual balun) 221 221 first transmission line 222 second transmission line 223 third transmission line 224 fourth transmission line 225 fifth transmission line 226 sixth transmission line 300 Mixing processing circuit unit ❿ 16 111049

Claims (1)

201014160 十、申請專利範固: 1. ❹ ❹ -種微型化雙平衡式混波器電路,其至少具有一第一 信號輸入端、-第二信號輸入端、和一信號輸出端, 其中該帛一信號輪入端係用以接收一帛一輸入信 號、該第二信號輸入端係用以接收一第二輸入信號、 而該信號輸出端則係用以輸出一混波之信號; 此微型化雙平衡式混波器電路至少包含. 第雙式平衡對不平衡變壓電路單元,其具有 -個單端點之輸入介面和一個四端點之輸出介面:其 中該單端點之輸入介面係連接至該第—信號輸入 端,而該四端點之輸出介面則用以輸出四個平衡對不 平衡轉換後的輸出變壓信號; 第一雙式平衡對不平衡變壓電路單元,其具有 一個單端點之輸入介面和一個四端點之輸出介面丨其 中該單端點之輸入介面係連接至該第二信號輸入 端,而該四端點之輸出介面則用以輸出四個平衡對不 平衡轉換後的輸出變壓信號;以及 一混波處理電路單元’其可接收該第一雙式平 對不平衡變壓電路單元和該第二雙式平衡衡 變壓電路單元所輸出之變壓信號,並對其提供一、、 處理作用而獲得所需之混波信號; '見波 其中 於積體電路佈局h該第-雙式平衡對不 壓電路單元和該第二雙式平衡對不平衡變壓電路: 111049 17 201014160 元均刀別包括複數條分散式之傳輸線路,且此些分散 式之傳冑線路的電路佈局係建基於一種三絞線式之 電路佈局架構。 2. 如申叫專利範圍第丨項所述之微型化雙平衡式混波器 電路/其為應用處理25 GHz至45 GHz的輸入信號。 3. 如申明專利範圍第j項所述之微型化雙平衡式混波器 電路其中该第一雙式平衡對不平衡變壓電路單元係 建置於一多層式電路基板。 © 4· ”請專利範圍第3項所述之微型化雙平衡式混波器 電路’其中该多層式電路基板為一雙層式電路基板, 用以配置2層之分佈式傳輸線路而構成一對馬佳得式 之雙式平衡對不平衡轉換器(Mar chand _ i ba}仙)。 5.如申睛專利範圍第4項所述之微型化雙平衡式混波器 電路,其中5亥雙層式電路基板上的分佈式傳輸線路包 括〗/4波長之微線路。 珍6.如申清專利範圍第3項所述之微型化雙平衡式混波器 電路’其中該雙層式電路基板為—商用G. 15微米U «0之 pHEMT(pSeud〇ra〇rphicHEMT,其令 HEMT=High Electron Mobility Transistor)製程所用之雙金屬 層砷化鎵(GaAs)基板。 7.如申請專利範圍第i項所述之微型化雙平衡式混波器 電路其中該第—雙式平衡對不平衡變I電路單元係 建置於一多層式電路基板。 8.如申請專利範圍第7項所述之微型化雙平衡式混波器 111049 18 201014160 電路,其中該多層式電路基板為一雙層式電路基板, 用以配置2層之分佈式傳輸線路而構成一對馬佳得式 之雙式平衡對不平衡轉換器(Marchand dual balun)。 9·如申請專利範圍第8項所述之微型化雙平衡式混波器 ^•路,其中该雙層式電路基板上的分佈式傳輸線路包 括1/4波長之微線路。 10·如申請專利範圍第7項所述之微型化雙平衡式混波器 電路,其中該雙層式電路基板為一商用〇15微米(“ ❹ m)之 pHEMT (Pseudomorphic ΗΕΜΤ,其中 ΗΕΜΤ= High Electron Mobility Transistor)製程所用之雙金屬 層坤化鎵(GaAs)基板。 11.如申請專利範圍第丨項所述之微型化雙平衡式混波器 電路,其中該混波處理電路單元為一種二極體切換式 之混波處理電路。 12·如申請專利範圍第i項所述之微型化雙平衡式混波器 ❹ f路’其中該混波處理電路單元為一電晶體切換式之 混波處理電路。 13.:種微型化雙平衡式混波器電路,其至少具有一第一 U輸入為第一仏號輪入端、和一信號輸出端, 其中該第一信號輸入端係用以接收一第一輸入信 號、該第二信號輸入端係用以接收一第二輸入信號: 而該信號輸出端則係用以輸出一混波之信號; 此微型化雙平衡式混波器電路至少包含: 第一雙式平衡對不平衡變壓電路單元,其具有 111049 19 201014160 一個單端點之輸人介面和—個 中該單端點之輸入八^四鸲點之輪出介面;其 姐_^ "面係連接至該第一俨妒耠人 鈿,而該四端點之輸出 》唬輸入 千衡轉換後的輸出變壓信號; 岡十衡對不 一第二雙式平衡對不平衡變壓 一個單端點之發入八 單凡’其具有 早4點之輸入介面和一個 中該單端點之鈐λ人 例扣;丨面,其 早u之輸入介面係連接 ❹ =該四端點之輪出介面則用以輸出四個;= 平衡轉換後的輸出變㈣號n +衡對不 一混波處理電路單元,其 混波處理電路,可接㈣第其^種二極體切換式之 電路單元和該第二雙式平_式平衡對不平衡變屋 所輸出之變静蒙,並斜=對不平衡變虔電路單元 得所需之混波;混波處理作用而獲 其t 壓電局= 元均分別包括複數條Γ分料之平路衡H ^單 =之傳輸線路的電路佈局係建基 電路佈局架構。 禋一紋線式之 以.如申請專利範圍第13項 器電路,其為應用處理c化雙平衡式混波 號。 至45 GHz的輸入信 15.如申請專利範圍第13項 π攻之微型化雙平衡式混波 111049 20 201014160 . * 器電路’其中該第一雙式平衡對不平衡變壓電路單元 和該第二雙式平衡對不平衡變壓電路單元均係建 於-雙層式電路基板,用以配置2層之分佈式傳輸線 路而構成-對馬佳得式之雙^平衡對不平衡轉換器 (Marchand dual balun)。 16·如中請㈣第15賴叙微黯雙平衡式混波 斋電路,其中該雙層式電路基板上的分佈式傳輸線路 包括1/4波長之微線路。 © η·如巾請專利範圍第15項所述之微型化雙平衡式 器電路,其中該雙層式電路基板為一商用〇15微来 (//m)之 pHEMT (pSeud〇morphic ΗΕΜΤ,1 中服们= High Electron Mobility Transistor)t m ^ 金屬層砷化鎵(GaAs)基板。 18. —種微型化雙平衡式混波器電路,其至少具有一第一 信號輸入端、-第二信號輸入端、和一信號輸出端, ❹*中該第-信號輸入端係用以接收—第一輸入信 號、該第二信號輸入端係用以接收一第二輸入信號、 而該信號輸出端則係用以輸出一混波之信號;, 此微型化雙平衡式混波器電路至少包含^· 一第一雙式平衡對不平衡變壓電路單元,其具有 -個單端點之輸人介面和—個四端點之輸出介面了其 中該單端點之輸入介面係連接至該第一信號輸二 端,而該四端點之輸出介面則用以輪出四個平ς 平衡轉換後的輸出變壓信號; 111049 21 201014160 ‘ -第二雙式平衡對不平衡變_ -個單端點之輸入介面和一個四端點之輪出二:具有 :該早端點之輸入介面係連接至該第二二於其 平衡轉換後的輸出變I信號;以及四個+衡對不 一混波處理電路單元,装Α 一 波處理電路,可接收該第一雙二之混 ❹ :單元和該第二雙式平衡對 輸出之變麼信號,並對其提n === 所需之混波信號; 乍用而獲侍 其中 於積體電路佈局上,哕坌_ ㈣路單元和該第 括複數條分散式之傳輸線路,且此= ==構路的電路佈局係建基於—種三絞線式之 19.=:專項所述之微型化雙平衡式混波 =電路’其為應用處理25版至45呢的輸入信 2〇·如申請專利範圍第18項所、+、__ 器電路,1中該第n 之微型化雙平衡式混波 和該第二雙式i衡對不/衡對不平衡變愿電路單元 於-雙層式㈣基板,電路單元均係建置 路而構成-對馬佳得式之簪配/2層之分佈式傳輸線 传式之雙式平衡對不平衡轉換器 111049 22 201014160 (Marchand dual balun) ° 21. 如申請專利範圍第20項所述之微型化雙平衡式混波 器電路’其中該雙層式電路基板上的分佈式傳輸線路 包括1/4波長之微線路。 22. 如申請專利範圍第20項所述之微型化雙平衡式混波 器電路,其中該雙層式電路基板為一商用0.15微米 (#m)之 pHEMT (pseudomorphic HEMT,其中 HEMT= High Electron Mobility Transistor)製程所用之雙 φ 金屬層珅化鎵(GaAs)基板。201014160 X. Patent application: 1. 微型 ❹ A miniaturized double balanced mixer circuit having at least a first signal input terminal, a second signal input terminal, and a signal output terminal, wherein the 帛a signal wheel is used to receive a first input signal, the second signal input is used to receive a second input signal, and the signal output is used to output a mixed signal; The double balanced mixer circuit includes at least a second balanced-unbalanced transformer circuit unit having a single-ended input interface and a four-terminal output interface: wherein the single-end input interface is Connected to the first signal input terminal, and the output interface of the four terminals is used to output four balanced to unbalanced converted output voltage transformation signals; the first dual balanced to unbalanced transformer circuit unit has a single-ended input interface and a four-terminal output interface, wherein the input interface of the single-end is connected to the second signal input, and the output interface of the four-terminal is used to output four flat And an unbalanced converted output voltage transformation signal; and a hybrid processing circuit unit that can receive the output of the first dual-type unbalanced transformer circuit unit and the second dual-balance voltage transformer circuit unit Transforming the signal and providing a processing action to obtain the desired mixed-wave signal; 'seeing the wave in the integrated circuit layout h the first-dual balanced pair non-voltage circuit unit and the second double Balanced vs. Unbalanced Transformer Circuit: 111049 17 201014160 The dollar equalizer includes a plurality of distributed transmission lines, and the circuit layout of these distributed transmission lines is based on a three-stranded circuit layout architecture. 2. The miniaturized double balanced mixer circuit as described in the scope of the patent scope/application for processing input signals from 25 GHz to 45 GHz. 3. The miniaturized double balanced mixer circuit of claim j, wherein the first dual balanced unbalanced transformer unit is coupled to a multi-layer circuit substrate. © 4· ” The miniaturized double balanced mixer circuit described in the third paragraph of the patent scope, wherein the multi-layer circuit substrate is a two-layer circuit substrate for arranging two layers of distributed transmission lines to form a For the Ma Jiade type double balanced to unbalance converter (Mar chand _ i ba} sen.) 5. The miniaturized double balanced mixer circuit as described in claim 4 of the scope of the patent, 5 Hai double The distributed transmission line on the layered circuit substrate includes a microwire of 〖/4 wavelength. Jan. 6. The miniaturized double balanced mixer circuit as described in claim 3 of the patent application, wherein the double layer circuit substrate It is a bimetallic layer gallium arsenide (GaAs) substrate used in the process of commercial G. 15 micron U «0 pHEMT (pSeud〇ra〇rphic HEMT, which makes HEMT=High Electron Mobility Transistor). The miniaturized double balanced mixer circuit of the present invention, wherein the first-to-double balanced-to-unbalanced I-circuit unit is built on a multi-layer circuit substrate. 8. As described in claim 7 Miniature double balanced mixer 111049 18 201014160 The multi-layer circuit substrate is a two-layer circuit substrate for arranging two layers of distributed transmission lines to form a pair of Majiad type double balanced baluns (Marchand dual balun). The miniaturized double balanced mixer according to claim 8 is characterized in that the distributed transmission line on the double-layer circuit substrate comprises a 1/4 wavelength micro line. The miniaturized double balanced mixer circuit according to Item 7, wherein the two-layer circuit substrate is used in a commercial 15 μm ("❹ m) pHEMT (Pseudomorphic ΗΕΜΤ, where ΗΕΜΤ = High Electron Mobility Transistor) process A bimetallic layer of a gallium arsenide (GaAs) substrate. 11. The miniaturized double balanced mixer circuit of claim 2, wherein the mixing processing circuit unit is a diode switching type mixing processing circuit. 12. The miniaturized double balanced mixer described in claim i, wherein the mixing processing circuit unit is a transistor switching type mixing processing circuit. 13. A miniaturized double balanced mixer circuit having at least a first U input as a first nickname wheel input end and a signal output end, wherein the first signal input end is configured to receive a first An input signal, the second signal input end is configured to receive a second input signal: and the signal output end is configured to output a mixed wave signal; the miniaturized double balanced mixer circuit comprises at least: A dual balanced-to-unbalanced transformer circuit unit having a single-end input interface of 111049 19 201014160 and an input interface of the single-end input of eight-four points; its sister _^ &quot The facial system is connected to the first person, and the output of the four terminals is input to the output voltage transformation signal after the input of the kilometer balance; the tenth balance is different from the second double balance to the unbalanced transformation A single-end entry into the eight-single's has an input interface of 4 o'clock in the morning and a 钤 人 人 人 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨 丨The wheel interface is used to output four; = balanced output The variable (four) n + balance is not a mixed wave processing circuit unit, and the mixed wave processing circuit thereof can be connected to (4) the second type of diode switching type circuit unit and the second double type flat_balance pair unbalanced change The output of the house is changed to static and slanting, and the required mixing is obtained for the unbalanced circuit unit; the wave processing is used to obtain the flatness of the plurality of bismuth materials. The circuit layout of the transmission line of H ^ single = is the base circuit layout architecture. For example, in the application of the patent scope, the 13th circuit is an application processing c-double balanced wave number. Input signal to 45 GHz 15. For example, the patented range 13th π attack miniaturized double balanced wave 111049 20 201014160 . * the circuit 'where the first dual balanced to unbalanced transformer circuit unit and the first The two-double balanced-unbalanced transformer circuit unit is built on a two-layer circuit board to configure a two-layer distributed transmission line - a pair of Ma Jiade type double balanced to unbalance converter (Marchand) Dual balun). 16· For example, please refer to (4) the 15th recital double-balanced hybrid wave circuit, wherein the distributed transmission line on the double-layer circuit substrate includes a 1/4 wavelength micro line. © η·如巾, please note the miniaturized double-balanced circuit described in the fifteenth patent, wherein the two-layer circuit substrate is a commercially available 微15 micron (//m) pHEMT (pSeud〇morphic ΗΕΜΤ, 1 Medium = High Electron Mobility Transistor) tm ^ Metal layer gallium arsenide (GaAs) substrate. 18. A miniaturized double balanced mixer circuit having at least a first signal input, a second signal input, and a signal output, wherein the first signal input is for receiving a first input signal, the second signal input end is for receiving a second input signal, and the signal output end is for outputting a mixed wave signal; the miniaturized double balanced mixer circuit is at least The first dual balanced to unbalanced transformer circuit unit has a single-ended input interface and a four-terminal output interface, wherein the single-end input interface is connected to the The first signal is input to the two ends, and the output interface of the four terminals is used to rotate the output voltage transformation signals after four balanced conversions; 111049 21 201014160 ' -Second type balance to unbalance change _ - The input interface of the single-end and the round-out of the four-end: have: the input interface of the early end is connected to the output I signal after the second conversion of the balance; and the four + balance a mixed wave processing circuit unit The road can receive the first double-two ambiguity: the unit and the second double-balanced-to-output change signal, and the n-== required mixed-wave signal is applied thereto; In the integrated circuit layout, the 哕坌_(four) way unit and the multiplexed series of distributed transmission lines, and the circuit layout of the === path is based on a three-strand type 19.=: Specialized The miniaturized double-balanced mixed-wave=circuit is an input signal for applying 25th to 45th applications. For example, in the 18th item of the patent application, the +, __ circuit, the miniaturization of the nth in the 1st The double-balanced hybrid wave and the second double-type i-balance pair are not balanced with the unbalanced variable-changing circuit unit in the double-layer (four) substrate, and the circuit units are all constructed to form a road - the matching of the Ma Jiade type / A two-layer distributed transmission line-transmitted dual balanced-to-balance converter 111049 22 201014160 (Marchand dual balun) ° 21. The miniaturized double balanced mixer circuit as described in claim 20 The distributed transmission line on the two-layer circuit substrate includes a 1/4 wavelength micro line. 22. The miniaturized double balanced mixer circuit of claim 20, wherein the two-layer circuit substrate is a commercially available 0.15 micron (#m) pHEMT (pseudomorphic HEMT, wherein HEMT=High Electron Mobility Transistor) Double φ metal layer gallium antimonide (GaAs) substrate used in the process. 23 11104923 111049
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