201013865 70、货*»月說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝件及其晶片承載 件，尤指一種具有良好散熱性之導線架式半導體封裝件及 其所應用之導線架與該半導體封裝件之設計方法。 【先前技術】 傳統導線架式半導體封裝件係於一導線架之晶片座 上接置一半導體晶片，再利用打線及封膠作業，以形成包 ❹覆銲線及該半導體晶片之封裝膠體；其中用以包覆晶片= 封裝膠體多為散熱性差之環氧樹脂(Ep〇xy㈣幻類之 料’因此半導體晶片於運作時所產生之熱量將無法經由封201013865 70, goods * * month description: [Technical Field] The present invention relates to a semiconductor package and a wafer carrier thereof, and more particularly to a lead frame type semiconductor package having good heat dissipation and application thereof A lead frame and a method of designing the semiconductor package. [Prior Art] A conventional lead frame type semiconductor package is connected to a semiconductor wafer on a wafer holder of a lead frame, and then is used for wire bonding and sealing operations to form a packaged bonding wire and an encapsulant of the semiconductor wafer; Used to wrap the wafer = the encapsulant is mostly poorly dissipating epoxy resin (Ep〇xy (4) phantom material', so the heat generated by the semiconductor wafer during operation will not be sealed.
裝膠體有效散逸至外界，造成熱量逸散效率不佳 半導體晶片之性能。 〜響fJ 請參閱第1A及則，為解決前述傳統導線架 體封裝件的散熱問題，業界遂發展出一種四邊扁平無 (Q— Flat Non-leaded，㈣)半導體封裝件，其特徵在 置有外導腳’即未形成有如習知四邊形平 之外、rrge，㈣半導體封裝件中用以與外界電性連接 姊㈣政…兹 裝件之尺寸，同時該㈣半導 =封裝件1之導線架12的晶片座121底面及導 1 【：係外露出封裝膠體15,即如第圖所示為該叫 導肢封裝件1之底視圖，以使則 該導腳122外露底面（ 等㈣裝件1仔藉 材料16而電性連接至電直接透過銲錫 電路板17上之銲墊170，同時使該 Π1020 5 201013865〇1 ^ 曰曰乃庄121底面透過銲錫材料16而接置於該電路板17 之一接地面（ground plane) 171上，進而使接置於該晶片 座121上之半導體晶片Η運作所產生之熱量得以透過該 晶片座121而傳遞至該接地面171，以有效解決傳統導線 架式半導體封裝件散熱不佳問題。相關之qFN半導體封裝 件技術可參見美國專利第6, 143, 981、6, 198, 171、 6,208’020、6,400,〇〇4、6,433,277、6,583,499、 6’ 642, 609、6, 661，083、6, 696, 749、6, 967, 125、6, 979, 866 ❹ 及 7，030，474 號案。 然而，請配合參閱第ic圖，係為對應該第1A圖之 QBJ半導體封裝件側視圖，前述QFN半導體封裝件仍存在 者些許問題’主要係因為一般㈣半導體封裝件i外 封裝膠體15之晶片座]?】尨；1 1底面、導腳122底面均與該封 裝膠體15底面大致眘单 千因此，在將該QFN半導體封裝 件之晶片座1 21透過錄4尽& 士丨，p 、于錫材枓16而接置於電路板17之接 m上後’由於QFN丰遵辦44杜At ^ ^ ee ^ W Ν牛導體封裝件1與電路板17間 ❹之間隙（Gap)G極為細小（約 ⑵周圍佈有導腳122，=:厂8微米)，且該晶片座 之曰κ庙彳β 而…、法由目視方式檢視導線架 上= 並未透料錫材料連接於電：n㈣之晶片座實際上 響到半導' 板之接地面上時，將嚴重影 J千等肢日日片之散熱效率。 因此，如何提供— 座是否…透過銲_===; 111020 6 201013865 μ ^ + ^ ^ ·〜β %如片座热法確貫透過銲锡材料 地面上時，亦不致·|^變丰$ w ;龟路板之接 才π不致〜曰+導體封裝件散熱性 界為解決半導體封裝件散熱貫為目則業 【發明内容】 彳丄待考里之課題。 有鑑於上述習知技術之缺點，本發明之一曰 一種散熱型半導㈣裝件及其 2係提供 _半導體封裝件之導線竿曰片…法，即便 之接地面上，亦不影響該_ 妾至电路板 ❹ 散熱。 牛導粗封裝件之半導體晶片 本發明之又一目的係提供一 及其導線架與設計方法，得以由半導體封裝件 檢視出該㈣半導體封裝邊 板之接地面上。 ^線木疋否確貫連接至電路 本發明之另一目的係搓供一 及其導線架與設計方法，二半導體封襄件 僅從晶片座下方傳遞熱量之限制^知㈣半導體封裝件 ❿ =明之再-目的係提供—種散熱型半導體 ^導線架與設計方法，得以提升㈣半導體封 二 熱面積及效能。 政 為達上述目的’本發明揭露—種散熱型半導體 牛’係包括：導線架，該導線架具有—新曰曰“座及設於兮 新晶片座周圍之複數導腳，其中該些導腳包括有原始導: 及額外導腳，且該額外導腳透過連接部而連接至該新 座；半導體晶片，係接置於該新晶片座上；鲜線，電性連 ]Π〇2〇 7 201013865 ^ 牧极卞守租晶片及該導腳；以及封裝膠體，包覆該銲線、 半導體晶片及部分導線架，並至少使該新晶片座底面及導 腳底面外露出該封裝廢體。 該導線架之新晶片座尺寸係由原始導腳加上額外導 腳之總數，而依國際規範（JEDEC Μ〇_22〇)之規定而對應 出。 〜 該半導體封裝件為一 QFN半導體封裝件，該些額外導 腳之寬度總和係大於或等於原始晶片座之寬度，各該額外 ❹導腳之寬度係與該原始導腳寬度相同，且該額外導腳可選 擇相對佈設於該新晶片座單側、相鄰兩側、相對兩側4 側或四側。 摘外‘腳與新晶片座相連之連接部的底面係可選 擇與該新晶底面、原始導腳底面及額外導腳底面齊 ::且外露出封轉體，亦或可透過半❹〗㈤卜^⑻ 錢接部之部分厚度，僅使該新晶片座底面、原 始導腳底面及額料腳底面外露出封裝膠體。 :發明復揭露一種導線架’係包括：一新晶片座，以 二::：口周圍之複數導腳’其中該些導腳包括有 額外導聊’且該額外導—接至 該些額外導腳之宽声 之官P…L 和係大於或等於原始晶片座 之見度’各相外導腳之寬度係與該原始導腳 且该額外導腳係可選擇相 又同， 兩側、相對兩側、三側或四輪片座單側、相鄰 1Π020 8 201013865 ... 破减外導腳與新晶片座相連之連接部的底面係可選 擇與該新晶片座底面、原始導腳底面及額外導腳底面齊 '平，亦或可透過半蝕刻（half~etch)方式移除該連接部之 • 邛刀厚度，僅使遠新晶片座底面、原始導腳底面及額外導 腳底面齊平。 本發明復揭露一種QFN半導體封裝件之設計方法，係 包括.提供一原始QFN半導體封裝件，該原始半導體 封裝件具有一原始晶片座及設於該原始晶片座周圍之複 ❹數原始導腳，其中該原始QFN半導體封裝件之尺寸及原始 $腳數量與配置係符合國際規範（JEDEC M〇_22〇)之規 疋，將戎原始晶片座寬度除以原始導腳寬度以獲得一數 值，並取大於該數值之正整數而設為額外導腳個數；參照 國際規範（JEDECM0-220)調整該額外導腳個數，以使該原 始導腳及額外導腳之總數與配置符合國際規範（jedec 220)之規疋，並調整原始晶片座尺寸以形成新晶片 座；以及使該額外導腳透過連接部連接至該新晶片座。 ❹該導線架之新晶片座尺寸係由原始導腳加上額外導 聊之總數’而依國際規範（厕€ MG-22G)之規定而對應 出。 邮相車乂於驾知QFN半導體封裝件，本發明之散熱型半導 f封裝件及其導線架與設計方法，主要係提供-包含有新 二曰片座及δ又於该新晶片座周圍之複數導腳的導線架，其中 $些導腳包括有原始導腳及額外導腳，且該額外導腳透過 、接邛而連接至該新晶月座，並透過置晶、打線、封裝模 Π1020 9 201013865 沒开呆叩形成散熱型半導體封裝件後’以將該散熱型半導 體封裝件之新晶；ί座、連接部及額外導腳間隔鲜錫材料接 -置於電路板之接地面時，因該新晶片座透過連接部連接至 .額外導腳，故可自該散熱型半導體封裳件之外觀，檢視該 領外導腳是否透過該銲錫材料而接置於電路板之接地面 上，以維持散熱途逕之暢通，且由於該些額外導腳之寬戶 總和係大於或等於原始晶片座之寬度，因此即便半導體二 ^件之導線架晶月座未確實連接至電路板之接地面上，因 ❹導腳係接置於接地面上’故不影響該半導體封裝件 =放熱’再者由於透過晶片座、連接部及額外導腳之設 加大半‘體晶片之散熱面積，可改善習知㈣ 封裝件僅從晶片座下方值、择盈旦 等體 傳遞熱f之限制，得以提升半導體 封1件之散熱面積及效能。 【貫施方式】 式，猎由特定的具體實施例說明本發明之實施方 ©瞭解本發明之其他優點與功效。 〜“地 第一實施例： 裝件:==圖’係為本發明之散熱型彻封 線架露半;半導體封裳件2包括有:-導 裝勝體25。 導“片21、複數銲線23、以及-封 5玄導線架2 2句杯古· .. 有· 一新日日片座221以及設於該新 111020 10 周圍之複數導腳222，其中該些導腳222包括 有原始導腳222a及額外導腳222b，且該額外導腳222b 透過連接部223而連接至該新晶片座221。 該導線架22之新晶片座221尺寸係由原始導腳222a 加上額外導腳222b之總數，而依國際規範之規定而對應 出。 該些額外導腳222b之寬度總和（wl+w2+w3 + w4+w5 + w6+w7+w8)係大於或等於如第1B圖所示之原始晶片座121 之寬度（W)，各該額外導腳222b之寬度係與該原始導腳 222a寬度相同，且該額外導腳222b係可選擇佈設於該新 晶片座221相對兩側。 該額外導腳222b與新晶片座221相連之連接部223 的底面係與該新晶片座底面221、原始導腳222a底面及 額外導腳222b底面齊平，且外露出封裝膠體25。 另外，關於QFN半導體封裝件之相關尺寸，包含封裝 件整體尺寸、晶片座尺寸、導腳尺寸、導腳間距、導腳數 ❿量及配置等係由國際規範JEDECM0-220所規定。 以下即依國際規範JEDEC M0-220之表7A、表3及表 7B說明本發明之導線架設計方法。 若針對如第1B圖之原始導線架進行設計者，考量其 封裝件尺寸（DBSC*EBSC)為3mmx3nnn，原始導腳（電性終端 terminal)之數目（N)為 12，導腳間距（pi tch)為 0. 65mm。 由M0-220之表7A得知原始晶片座面積（NOM)最大為 D2xE2 = l. 65mmxl. 65mm，復由 M0-220 之表 3 可知，對應導 11 111020 201013865 Γ π叫π、pi tch)0. 65關之條件下，原始導腳（電性終端）之 寬度（_為〇· 3顔’而為設計新增之複數額外導腳之寬 -度總和大於或等於原始晶片座之寬度，故所需額外導腳數 .目至少彡1設置^關.3:5·5,取切誠值之接近整數 為6 ’亦即至少須設置6個額外導腳。 考量須維持QFN半導體封裝件之方正格局，即須設置 γ個額外導腳，以平均分崎縣晶片座四周，如此新設 计之導腳數目⑻變為12個原始導腳加上8個額外導腳， ❹合計2G_ ’並使該額外導腳透料接部連接至原始晶片 座’如第2A圖所示，於本實施例中該額外導腳係設於原 始晶片座之相對兩側，唯亦可如第2C圖所示設於原始晶 片座四側。 從M0-220之表7B可知，相較於原始QFN半導體封裝 件尺寸3咖*3咖之尺寸（導腳數目N = 12)’於導腳數目請 情況且導㈣距（pi teh)轉Q. 65mm之條件下，新設計之 QFN半導體封裝件尺寸⑽似職）變為 ❿〃再者，該新設計之㈣半導體封裝件之新晶片座尺寸 ^由原料腳加均料腳之總數，域㈣規範（麵c 220)之規定而對應出。例如，相較於原始封裝件尺寸The colloid is effectively dissipated to the outside world, resulting in poor heat dissipation efficiency of the semiconductor wafer. ~ 响 fJ Please refer to the 1A and the following, in order to solve the heat dissipation problem of the conventional lead frame package, the industry has developed a Q-flat Non-leaded (S) semiconductor package, which is characterized by The outer guide leg 'is not formed with a conventional quadrilateral flat, rrge, (4) the size of the semiconductor package for electrically connecting with the external 姊 (4), and the (four) semi-conductor = the lead of the package 1 The bottom surface of the wafer holder 121 of the frame 12 and the guide 1 are exposed to the outer surface of the package member 15 as shown in the figure, so that the guide leg 122 is exposed to the bottom surface (etc. The device 1 is electrically connected to the pad 170 on the solder circuit board 17 by means of the material 16, and the bottom surface of the Π1020 5 201013865〇1 ^ 曰曰乃庄 121 is placed on the circuit board 17 through the solder material 16. A ground plane 171 is disposed, so that heat generated by the operation of the semiconductor wafer mounted on the wafer holder 121 is transmitted to the ground plane 171 through the wafer holder 121 to effectively solve the conventional lead frame. Semiconductor package heat dissipation A good problem. The related qFN semiconductor package technology can be found in U.S. Patent Nos. 6, 143, 981, 6, 198, 171, 6, 208 '020, 6, 400, 〇〇 4, 6, 433, 277, 6, 583, 499, 6' 642, 609, 6, 661. , 083, 6, 696, 749, 6, 967, 125, 6, 979, 866 ❹ and 7,030, 474. However, please refer to the ic diagram for the QBJ semiconductor package corresponding to Figure 1A. Side view, the QFN semiconductor package still has some problems 'mainly because of the general (4) semiconductor package i outer package of the package 15 of the wafer holder] 尨; 1 1 bottom surface, the bottom surface of the guide pin 122 and the package colloid 15 The bottom surface is generally cautious. Therefore, after the wafer holder 1 21 of the QFN semiconductor package is recorded through the recording, the p, and the tin material 16 are placed on the circuit board 17 and connected to the circuit board 17 by QFN.丰遵办44杜At ^ ^ ee ^ W The gap between the yak conductor package 1 and the circuit board 17 (Gap) G is extremely small (about (2) around the guide pin 122, =: factory 8 microns), and The wafer holder is 曰 彳 而 而, and the method is visually inspected on the lead frame = the non-transparent tin material is connected to the electricity: n (four) wafer In fact, when it hits the ground plane of the semi-conducting 'board, it will seriously affect the heat dissipation efficiency of the J-thousands of the day. Therefore, how to provide the seat? Whether it is through the welding _===; 111020 6 201013865 μ ^ + ^ ^ · ~β % If the film is passed through the solder material on the ground, it will not be able to | ^^ become abundance $ w; the turtle board will not be connected to the 曰 曰 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体 导体The heat dissipation of the package is the goal of the industry. [Summary of the invention] In view of the above-mentioned shortcomings of the prior art, one of the present inventions, a heat-dissipating type semi-conductive (four) package, and a two-layer method thereof, provide a wire-chip method for a semiconductor package, even if it is on a ground plane, does not affect the妾 to the board ❹ heat dissipation. BACKGROUND OF THE INVENTION A further object of the present invention is to provide a leadframe and design method for viewing the ground plane of the (4) semiconductor package edge from a semiconductor package. ^ 疋 疋 确 确 确 确 确 确 确 确 确 确 确 确 确 确 确 确 另一 另一 另一 另一 另一 另一 另一 另一 另一 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其 及其Mingzhi--the purpose is to provide a kind of heat-dissipating semiconductor wire frame and design method, which can improve (4) the thermal area and efficiency of the semiconductor package. For the above purposes, the present invention discloses a heat-dissipating semiconductor cow comprising: a lead frame having a new seat and a plurality of guide pins disposed around the new wafer holder, wherein the guide pins Including the original guide: and an additional guide pin, and the additional guide pin is connected to the new seat through the connection portion; the semiconductor wafer is attached to the new wafer holder; the fresh wire, the electrical connection] Π〇 2〇7 201013865 ^ The grazing chip and the guiding pin; and the encapsulant, covering the bonding wire, the semiconductor wafer and a part of the lead frame, and at least exposing the package waste body to the bottom surface of the new wafer holder and the bottom surface of the guiding pin. The new wafer holder size is determined by the original guide pin plus the total number of additional leads, and is specified in accordance with international regulations (JEDEC Μ〇 _22〇). ~ The semiconductor package is a QFN semiconductor package, The sum of the widths of the additional lead pins is greater than or equal to the width of the original wafer holder, and the width of each of the additional lead pins is the same as the width of the original lead pin, and the additional lead pins can be selectively disposed on one side of the new wafer holder. Adjacent The sides of the two sides, the opposite sides of the four sides or four sides. The bottom of the connecting portion of the external foot connected to the new wafer holder can be selected to be flush with the bottom surface of the new crystal, the bottom surface of the original guiding foot and the bottom surface of the additional guiding foot: The sealing body may also be partially transparent to the bottom surface of the new wafer holder, the bottom surface of the original guide foot and the bottom surface of the front foot of the material, through a partial thickness of the half-inch (5) bu (8) money joint. The frame includes: a new wafer holder, with a plurality of guides around the two::: mouths, wherein the guides include additional guides and the additional guides are connected to the wide guides of the additional guides P...L and the system are greater than or equal to the original wafer holder visibility. The width of the outer guide legs of each phase is the same as the original guide pin and the additional guide legs can be selected, both sides, opposite sides, three sides or The four-wheeled pedestal is unilaterally adjacent to the adjacent Π 020 8 201013865 ... the bottom surface of the connecting portion of the broken outer guiding leg and the new wafer holder can be selected to be flush with the bottom surface of the new wafer holder, the bottom surface of the original guiding foot and the bottom surface of the additional guiding foot 'Flat, or can be removed by half-etch (half~etch) The thickness of the file is only flush with the bottom surface of the far-in wafer holder, the bottom surface of the original guide pin and the bottom surface of the additional guide pin. The present invention discloses a method for designing a QFN semiconductor package, which comprises providing an original QFN semiconductor package, the original The semiconductor package has an original wafer holder and a plurality of turns of the original guide pins disposed around the original wafer holder, wherein the size and original number of the original QFN semiconductor package and the configuration are in accordance with international standards (JEDEC M〇_22 〇), divide the original wafer holder width by the original guide width to obtain a value, and take a positive integer greater than the value to set the number of additional leads; adjust the reference with reference to international specifications (JEDECM0-220) The number of additional lead pins is such that the total number of the original lead pins and the additional lead pins are configured in accordance with international specifications (jedec 220), and the original wafer holder size is adjusted to form a new wafer holder; and the additional lead pins are passed through A connection is connected to the new wafer holder.新 The new wafer holder size of the lead frame is based on the original guide pin plus the total number of additional talks' in accordance with international regulations (total MG-22G). The post-driving vehicle is used to drive the QFN semiconductor package, and the heat-dissipating semi-conductor f package of the present invention, its lead frame and design method are mainly provided - including a new two-piece holder and δ and around the new wafer holder a lead frame of a plurality of lead pins, wherein the plurality of lead pins include an original lead pin and an additional lead pin, and the additional lead pin is connected to the new crystal lunar seat through the connecting pin, and passes through the crystal, wire, and package mold Π1020 9 201013865 After the heat-dissipating semiconductor package is not opened, the new crystal of the heat-dissipating semiconductor package is used; when the cradle, the connecting portion and the additional lead-spaced tin material are placed on the ground plane of the circuit board Since the new wafer holder is connected to the additional lead via the connecting portion, the appearance of the heat-dissipating semiconductor sealing member can be checked whether the external guiding pin is connected to the ground plane of the circuit board through the solder material. In order to maintain the smoothness of the heat dissipation path, and since the sum of the additional leads is greater than or equal to the width of the original wafer holder, even if the lead frame of the semiconductor component is not surely connected to the ground plane of the circuit board on, ❹The lead pin is placed on the ground plane' so it does not affect the semiconductor package=heat release. Furthermore, the heat dissipation area of the half-body wafer can be improved by the wafer holder, the connection portion and the additional lead pins. The package only reduces the heat dissipation area and performance of the semiconductor package by transferring the heat f from the lower value of the wafer holder or the selected body. [Embodiment] The practice of the present invention is illustrated by a specific embodiment to understand the other advantages and effects of the present invention. ~ "First embodiment: assembly: == diagram" is the heat-dissipating seal of the invention is half exposed; the semiconductor package 2 includes: - guide body 25. Welding wire 23, and - sealing 5 Xuan lead frame 2 2 sentence cup ancient ·.. · A new day seat 221 and a plurality of guide pins 222 located around the new 111020 10, wherein the guide legs 222 include The original lead 222a and the additional lead 222b are connected to the new wafer holder 221 through the connecting portion 223. The new wafer holder 221 of the lead frame 22 is sized by the total number of the original lead 222a plus the additional lead 222b and is specified in accordance with international regulations. The sum of the widths of the additional lead pins 222b (wl+w2+w3 + w4+w5 + w6+w7+w8) is greater than or equal to the width (W) of the original wafer holder 121 as shown in FIG. 1B, each of the additional The width of the lead 222b is the same as the width of the original lead 222a, and the additional lead 222b can be optionally disposed on opposite sides of the new wafer holder 221. The bottom surface of the connecting portion 223 of the additional lead leg 222b connected to the new wafer holder 221 is flush with the bottom surface of the new wafer holder bottom surface 221, the bottom surface of the original lead leg 222a and the bottom surface of the additional lead leg 222b, and the encapsulant 25 is exposed. In addition, the relevant dimensions of the QFN semiconductor package, including the overall package size, wafer holder size, pin size, pin pitch, number of leads, and configuration are specified by the international standard JEDECM0-220. The following is a description of the lead frame design method of the present invention in accordance with Table 7A, Table 3 and Table 7B of the international standard JEDEC M0-220. If you are designing the original lead frame as shown in Figure 1B, consider the package size (DBSC*EBSC) as 3mmx3nnn, the number of original leads (electrical terminal) (N) is 12, and the pitch of the leads (pi tch) ) is 0. 65mm. It is known from Table 7A of M0-220 that the original wafer holder area (NOM) is at most D2xE2 = l. 65mmxl. 65mm. The complex is represented by Table 3 of M0-220. The corresponding guide 11 111020 201013865 Γ π is called π, pi tch)0 Under the condition of 65 degrees, the width of the original guide pin (electrical terminal) (_ is 〇·3 颜 ”, and the sum of the width and degree of the additional extra guide pins is greater than or equal to the width of the original wafer holder. The number of additional lead pins required. At least 设置1 setting ^3.5·5, the approximate integer value of the cut-off value is 6 ', that is, at least 6 additional lead pins must be set. Consideration should be made to maintain the QFN semiconductor package. The square pattern, that is, γ additional guide pins must be set to average around the chip base of the Fizaki County. The number of new design guide pins (8) becomes 12 original guide pins plus 8 additional guide pins, and the total is 2G_ 'and The additional lead connecting portion is connected to the original wafer holder. As shown in FIG. 2A, in the embodiment, the additional lead pins are disposed on opposite sides of the original wafer holder, but can also be as shown in FIG. 2C. It is located on the four sides of the original wafer holder. It can be seen from Table 7B of M0-220 that compared with the original QFN semiconductor package size 3 coffee * 3 coffee Dimensions (number of guide pins N = 12)' Under the condition of the number of guide pins and the guide (four) distance (pi teh) to Q. 65mm, the newly designed QFN semiconductor package size (10) is changed. The new wafer size of the new design (4) semiconductor package is corresponding to the total number of raw material feet plus the average material foot, and the domain (4) specification (face c 220). For example, compared to the original package size
f W3mm’其原始晶片座尺寸為UWU5職，而在 4设计之封裝件尺寸變為5_*5_時，&，22〇之表7B 可知，該新設計之新晶片座之尺寸（D2*E2)將變更為 2. 了。 如此，即可利用該額外導腳連接至電路板之接地面 111020 12 201013865, u 、 ""*"丨&日日片座無法確實透過銲錫材料連接至接地面時， 仍可維持適當之散熱性。 該半導體晶片21具有相對之主動面21丨及非主動面 • ^ 並使该半導體晶片21以其非主動面212間隔一導熱 黏著層（未圖示）而接置於該新晶片座22〗上。 其後進行打線作業，以利用銲線23電性連接該半導 體晶片21主動面211及導腳222。 主2著’進行封裝模壓作業，以形成包覆該銲線23、 ❹半導體晶片21及部分導線架之封裝膠體25，且至少使該 Π片/ 221底面外露出封裝膠體25，以及使該原始Ϊ 、底面與額外導腳222b底面外露出該封裝膠體25 而為笔性終端’並經由切宏||作鞏，以报占士说 半導體封裝件。 W«以形成本發明之散熱型 體封驻I >閱第3圖’後續即可將本發明之散熱型半導 如銲錫姑:露出封装膠體25之原始導腳222a底面透過例 ©之外部裝¥，26之導電材料而電性連接至例如電路板27 新曰’並使該半導體封裝件外露出封裝膠體25之 /詈曰於2 221及額外導腳_亦得以透過該錦錫材料26 作時所吝路板27之接地面271 ’以供該半導體晶片21運 散，其中量日經由該電路板接地自271而進行逸 額外導腳2^ 221係透過連接部223而連接至 確實透過H从故可透過外觀檢視該額外導腳222b是否 、透過#錫材料26而接 上’以確保散熱途…s 接地面271 .....工之畅通，且由於被數額外導腳222b 111020 13 201013865 〜兄/又蟪和係大於或等於原始晶片座之寬度，因此即便晶 片座未確實連接至電路板之接地面上，亦不影響該半導體 封裝件之散熱，再者透過額外導腳222b及連接部223之 、又置加大可供半導體晶片散熱之面積，以改善習知qfn 半導體封裝件僅從晶片座下方傳遞熱量之限制，進而提升 半導體封裝件之散熱面積及效能。 弟一貫施例： 明參閱第4圖，係為本發明之散熱型半導體封裝件第 ❾二實施例之底面示意圖。 本實施例與前述實施例大致相同，主要差異在於導線 ^額外導腳422b除於第2A及％圖所示之設於該新晶 上相對兩側及四側外’亦可選擇設於相對新晶片座m 之相鄰兩側。 之 導 當然若其它情況許可下亦可選擇相對於新晶片座 I:::側投置額外導腳，且該額外導腳係可配合原始 腳而重新配置於該新晶片座周圍位置。 ©第三實施例： 及5β圖係顯不本發明之散埶型半導體 封裝件第三實施例夕+立园 ^ 月又…1千¥組 1她例之不思圖，其中第5Λ圖為底面干音 圖，第5β圖係為斟庙笙以固局展面不思 圓手為對應4 5A圖印,剖面之示意圖。 本貫施例與前述如第2Γ闇％ _ — 主m…苗所不之實施例大致相同， 主要差異在於導線牟Φ用、击&、 座521之μ 1外㈣522b及新晶片 之連接# 523係可透過半 除部分厚度，該移etch)方式移 私除Μ則由封裳膠體55填充，僅使該 113020 14 201013865 二曲w 521底面及額外導腳_底面外露 55,進而使本發明之韻型半導體封料 ^ = •統QFN半導體封裝件。 r蜆如叼傳 ， ^，本㈣之㈣料導體封料及其導 =:二係提供一包含有新晶片座及設於該新晶二 周圍之複數¥腳的導線架，其中該些導腳包 及額外導腳，且使該額外導腳透過連接部而 片座，並透過置晶、打绩、刼驻拆两从池 王β新明 導體封i乍業而形成散熱型半 ❹v I件後，以將該散熱型半導體封裝件之新晶 連接部及㈣導腳間隔銲錫㈣接置 時’因該新晶片座透過連接部連接至額外導腳== 裝件之外觀’檢視該額外導腳是否透過該 如錫材枓而接置於電路板之接地面上，以維持散敎途逕之 ^通’且由於該些額外導腳m和係大於或等於原始 之寬度，因此即便半導體封裝件之導線架新晶片座 I連接至電路板之接地面上，因該額外導腳係接置於 Ο接地面上’故不影響該半導體封裝件之散熱，再者由於透 過新晶片座、連接部及額外導腳之設置，加大半導體晶片 之散熱面積’可改善習知㈣半導體封裝件僅從晶片座下 =遞熱量之限制，得以提升半導體封裝件之散熱面積及 效此。 ^上述實施例僅為例示性說明本發明之原理及其功 效，1非用於限制本發明。任何熟習此項技藝之人士均可 在不違月本兔明之精神及範疇下，對上述實施例進行修飾 111020 】5 2 0 UU6 5因此，本發明之權利保護範圍，應如後述之申請 專利範圍所列。 【圖式簡單說明】 • f ΙΑ'ΙΒ及1C圖係為f知_半導體封 底面及側視示意圖； 第2A及2B圖係為本發明之散熱型半導 立 導線架第一實施例之示意圖； 裝件及其 圖； ❹ 第2C圖係為對應第2A圖之散熱型半 導線架另一設計態樣示意一 體封裝件及其 第 置於電 路板之之料料㈣封裳件接 例之示恩圖；以及 ;意4圖圓:為及本發明，型半導趙封裝件第二實施 明之散熱料導體封裝件第三 第5A及5B圖係為本發 實施例之示意圖。 【主 要元件符號說明】 1 QFN半導體封裝件 11 半導體晶片 12 導線架 121 晶片座 122 導腳 15 封裝膠體 16 銲鎖材料 17 電路板 ]]]〇20 ]6 201013865 ^ 1 ιυ 銲墊 171 接地面 2 散熱型半導體封裝件 21 半導體晶片 211 主動面 212 非主動面 22 導線架 221 新晶片座 222 導腳 ❹222a 原始導腳 222b 額外導腳 223 連接部 23 銲線 25 封裝膠體 26 銲錫材料 27 電路板 271 接地面 〇 421 新晶片座 422b 額外導腳 521 新晶片座 522b 額外導腳 523 連接部 55 封裝膠體 G 間隙 寬度 W, wl, w2, w3, w4, w5, w6, w7, w8 17 111020f W3mm's original wafer holder size is UWU5, and when the size of the package of 4 design becomes 5_*5_, &, Table 7B of 22〇, the size of the new wafer holder of the new design (D2* E2) will be changed to 2. In this way, the additional lead pin can be used to connect to the ground plane of the circuit board 111020 12 201013865, u, ""*"丨&day seat can not be reliably connected to the ground plane through the solder material, still maintain Proper heat dissipation. The semiconductor wafer 21 has an active surface 21丨 and an inactive surface. The semiconductor wafer 21 is placed on the new wafer holder 22 with a thermally conductive adhesive layer (not shown) spaced apart from the inactive surface 212. . Thereafter, a wire bonding operation is performed to electrically connect the active surface 211 and the lead pins 222 of the semiconductor wafer 21 by the bonding wires 23. The main body 2 performs a package molding operation to form an encapsulant 25 covering the bonding wire 23, the germanium semiconductor chip 21 and a portion of the lead frame, and at least exposes the bottom surface of the die/221 to the encapsulant 25, and makes the original Ϊ, the bottom surface and the outer surface of the additional lead 222b expose the encapsulant 25 to be a pen-like terminal' and pass through the cut-off to mark the semiconductor package. The heat-dissipating semi-conductor of the present invention, such as the solder, is exposed to the outside of the original guide leg 222a of the encapsulant 25 through the outside of the example. The electrically conductive material of the package 26 is electrically connected to, for example, the circuit board 27 and exposes the semiconductor package to the encapsulant 25, and the additional lead _ is also transmitted through the brocade material 26 The ground plane 271' of the circuit board 27 is used for the semiconductor wafer 21 to be transported, and the amount of the antenna is grounded from the 271 via the board. The additional lead 2^221 is connected through the connecting portion 223 to be surely transmitted. From then, it can be seen through the appearance of whether the additional lead 222b is connected to the #tin material 26 to ensure the heat dissipation path...s the ground plane 271 ..... smooth, and because of the number of additional guide legs 222b 111020 13 201013865 ~ Brother / 蟪 系 is greater than or equal to the width of the original wafer holder, so even if the wafer holder is not actually connected to the ground plane of the board, it does not affect the heat dissipation of the semiconductor package, and then through the extra lead 222b And the connecting portion 223 For cooling the area of the semiconductor wafer to improve the conventional semiconductor package qfn only from below the wafer holder of the heat transfer limitations, thereby enhancing the heat dissipation area and performance of the semiconductor package. </ RTI> The following is a schematic diagram of the bottom surface of the second embodiment of the heat dissipation type semiconductor package of the present invention. This embodiment is substantially the same as the previous embodiment. The main difference is that the lead wires 422b can be set to be relatively new except for the opposite sides and four sides of the new crystal shown in the 2A and % drawings. Adjacent sides of the wafer holder m. Of course, if it is otherwise possible, an additional lead can be placed relative to the new wafer holder I::: side, and the additional lead can be repositioned around the new wafer holder in conjunction with the original foot. ©Third Embodiment: And the 5β-picture system is not the same as the dilated semiconductor package of the present invention. The third embodiment is 夕+立园^月又...1 thousand ¥ group 1 her case is not considered, wherein the fifth picture is The bottom dry sound map, the 5th figure is the schematic diagram of the cross section of the temple. The present embodiment is substantially the same as the foregoing embodiment, such as the second Γ % _ _ main m... seedlings, the main difference is that the wire 牟Φ, the hit &, the seat 521 μ 1 outer (four) 522b and the new wafer connection # 523 is permeable to the partial thickness of the half, and the etch method is filled by the sealing body 55, so that only the bottom surface of the 113020 14 201013865 and the additional guide foot _ the bottom surface is exposed 55, thereby making the invention Rhyme-type semiconductor sealing material ^ = • QFN semiconductor package. r蚬如叼, ^, 本(4) (4) material conductor sealing material and its guide =: The second system provides a lead frame containing a new wafer holder and a plurality of foot pins disposed around the new crystal 2, wherein the guiding pins a package and an additional guide pin, and the additional guide pin is passed through the connection portion, and the heat dissipation type half-piece is formed by the crystal, the performance, the squatting and the detachment. Then, when the new crystal connection portion of the heat dissipation type semiconductor package and the (four) lead spacer solder (4) are connected, the additional guide is viewed by the connection of the new wafer holder through the connection portion to the additional lead pin == the appearance of the package. Whether the foot is placed on the ground plane of the circuit board through the tin material to maintain the diverging path and because the additional leads m and the system are greater than or equal to the original width, even the semiconductor package The new wafer holder I of the lead frame is connected to the ground plane of the circuit board, because the additional lead pin is placed on the grounding surface of the circuit board, so that the heat dissipation of the semiconductor package is not affected, and the new wafer holder and the connecting portion are transmitted through And additional pin settings to increase heat dissipation from semiconductor wafers Plot '(iv) can improve the conventional semiconductor package delivery from only the wafer holder = caloric restriction, efficiency can be improved and the heat dissipation area of the semiconductor package. The above embodiments are merely illustrative of the principles of the invention and its effects, and 1 is not intended to limit the invention. Anyone who is familiar with the art can modify the above embodiment without departing from the spirit and scope of the moon. 11120 】 5 2 0 UU6 5 Therefore, the scope of protection of the present invention should be as described later. Listed. [Simple diagram of the diagram] • f ΙΑ 'ΙΒ and 1C diagrams are f- _ semiconductor bottom and side view; 2A and 2B are schematic diagrams of the first embodiment of the heat-dissipating semi-conductive lead frame of the present invention ; 2C diagram is another design aspect of the heat-dissipating half-lead frame corresponding to the 2A figure, indicating the integrated package and the material placed on the circuit board (4) The present invention is a schematic diagram of a third embodiment of the present invention. The third embodiment of the present invention is a schematic diagram of the third embodiment of the present invention. [Main component symbol description] 1 QFN semiconductor package 11 semiconductor wafer 12 lead frame 121 wafer holder 122 lead pin 15 package colloid 16 solder lock material 17 circuit board]]]〇20 ]6 201013865 ^ 1 ιυ pad 171 ground plane 2 Heat-dissipating semiconductor package 21 semiconductor wafer 211 active surface 212 inactive surface 22 lead frame 221 new wafer holder 222 lead ❹ 222a original lead 222b additional lead 223 connecting portion 23 bonding wire 25 encapsulant 26 solder material 27 circuit board 271 Ground 〇 421 New wafer holder 422b Additional lead 521 New wafer holder 522b Additional lead 523 Connection 55 Encapsulant G Gap width W, wl, w2, w3, w4, w5, w6, w7, w8 17 111020