201007997 六、發明說明： 【發明所屬之技術領域】 本發明涉及一種光電半導體晶片。 【先前技術】 薄膜構造形式的光電半導體晶片例如已描述在文件 贾002/13281八1和£? 0905797八2中，其已揭示的有關光 電半導體晶片之薄膜構造形式的整個內容藉由參考而收納 於此處。 g 【發明内容】 本發明的目的是提供一種光電半導體晶片，其可成本 特別有利地製成。本發明的另一目的是提供一種機械穩定 性較佳的光電半導體晶片。此外，本發明的目的是提供一 種具有光電半導體晶片之光電組件。 依據光電半導體晶片之至少一實施形式，該光電半導 體晶片包括半導體本體。半導體本體可以是一種磊晶生長 之層結構，其可生長在一種生長基板上，該生長基板在該 Q 磊晶生長結束之後由已製成的半導體本體中去除或至少被 薄化。此光電半導體晶片可以是一種薄膜構造形式的半導 體晶片。半導體本體因此可具有一種20微米或更小的厚 度，此厚度特別是1 0微米或更小。 半導體本體例如包括一種活性區，其用來偵測或產生 電磁輻射。例如，此光電半導體晶片是一種像光二極體之 類的偵測器晶片、或是一種電致發光二極體晶片，例如， 發光二極體晶片或雷射二極體晶片。 201007997 半導體本體較佳是形成在III/V-半導體系統中。即， 其較佳是具有—種III/V-化合物-半導體材料。一種ΠΙ/ν-化合物-半導體材料具有：由第三族而來的至少一種元素， 例如’ B，Al，Ga，In、以及由第五族而來的一種元素，例如， N，P，As。此槪念“ΙΠ/ν_化合物-半導體材料”特別是包括 來自一兀、二兀或四元化合物之族群（gr0Up)，其包含來自 第三族群之至少一個元素和來自第五族群之至少一個元 素’例如’包括氮化物-和磷化物-化合物-半導體。此種二 元、三元或四元化合物可另外具有一種或多種摻雜物質以 及其它的成份。 半導體本體亦能以其它的材料系統，例如，II/VI-化合 物-半導體材料，來製成。 II/VI-化合物·半導體材料具有：由第二族而來的至少 一種元素，例如，Be, Mg，Ca, Sr、以及由第六族而來的一 種元素’例如，0, S, Se。II/VI-化合物-半導體材料特別是 包含二元、三元或四元化合物，其包含由第二族而來之至 少一種元素和由第六族而來之至少一種元素。此種二元、 三元或四元化合物例如可具有一種或多種摻雜物質以及其 它的成份。例如，ZnO，ZnMgO，CdS，ZnCdS，MgBeO 屬於 II/VI-化合物-半導體材料。 依據光電半導體晶片之至少一實施形式，光電半導體 晶片具有一種可導電之金靥層堆疊，其配置在半導體本體 上。 該金屬層堆叠由至少二個含有不同金屬的層所形成。 該層堆疊具有導電性，使電流可經由該層堆叠而施加至該 201007997 半導體本體中。 該金屬層堆疊可施加在半導體本體之上側上 層堆疊可以是一種所謂連接墊（bond pad)，其用來 觸線，可經由此一接觸線來接觸該半導體晶片。 堆疊因此位於該半導體本體之輻射通過面上。即 層堆疊施加在半導體本體之外表面之一部份上， 本體操作時電磁輻射經由外表面之此一部份而發 此外，該金屬層堆疊亦可另外位於該半導體 離該輻射通過面之下側上》該金屬層堆疊然後可 〇 該半導體晶片且給予該半導體晶片一額外的機械 即，該金屬層堆疊亦可用作背面接觸區。 依據光電半導體晶片之至少一實施形式，該 疊包括至少一含有鎳之第一層。此含有鎳之第一 佳是配置成與該半導體本體之磊晶生長之層相平 一層例如可由鎳構成或由磷化鎳（NiP)構成。又， 堆叠亦可包括一由鎳構成的層和另一由磷化鎳構 Λ 依據光電半導體晶片之至少一實施形式，該 ❹ 叠包括至少一含有金的第二層。即，該金屬層堆 層可由金構成或包含一種含金的化合物或含金的 第二層因此較佳是配置成同樣與該半導體本體之 之層相平行。 依據光電半導體晶片之至少一實施形式，該 置在該半導體本體和該第二層之間。即，可導電 堆叠包括該第一層和該第二層。該第一層含有鎳 含有金。此二層配置成互相平行且較佳是平行於 。該金屬 固定一接 該金屬層 ，該金屬 該半導體 出。 本體之遠 用來焊接 穩定性。 金屬層堆 層因此較 行。該第 該金屬層 成的層。 金屬層堆 疊之第二 合金。此 磊晶生長 第一層配 之金屬層 ，第二層 半導體本 -6- 201007997 體之磊晶生長的層而延伸。含有鎳的第一層配置成較含有 金的第二層更靠近該半導體本體。 依據光電半導體晶片之至少一實施形式，該光電半導 體晶片包括一個半導體本體和一個在該半導體本體的上側 上的導電的金屬層堆疊，其中該金屬層堆疊包括至少一含 有鎳之第一層和一含有金的第二層，該第一層配置在該半 導體本體和第二層之間。 此處所述的光電半導體晶片另外以下述認知爲基準， ^ 即：含有鎳的層是一種特別硬、可簡易地製成且可容易再 ❹ 生的層。此層例如可由鎳構成或另外含有磷。此層例如能 以磷化鎳來形成。由於含有鎳的層具有一特別硬的表面， 則可使該層例如被刮傷的危險性下降。 當晶圓複合物之各別的光電半導體晶片藉由所謂“晶 圓測試”來檢測其功能時，可導電的金屬層堆疊之刮傷例 如會在該光電半導體晶片的製程中發生於晶圓複合物中。 現在，若可導電的金屬層堆疊主要由較軟的金屬（例如，鋁 Φ 或金）所構成，則該層堆疊會在“晶圓測試”時刮傷。這例 如可藉由稍後的製程中之電子式圖像處理來使該金屬層堆 疊之可辨認性降低。 此外，已顯示的事實是：含有金的第二層由半導體本 體來觀看時是在含有鎳的第一層之後方，金屬層堆疊之可 接觸性藉由一接觸線來簡化。例如，藉由含有金的第二層 可使導電性的金屬層堆疊上之含有金之接觸線的黏合性獲 得改良。 最後，已顯示的事實是：含鎳之層在導電性的金屬層 201007997 堆疊中是半導體本體之一種機械穩定性優良且成本有利的 金屬層。此金屬層堆叠因此在光電半導體晶片被接觸時可 保護該半導體本體使不受機械上的負載。 整體而言，此處所描述的光電半導體晶片可達成一種 簡化-且成本有利之製程。此外，光電半導體晶片可受到保 護以特別良好地對抗機械上的負載。 依據光電半導體晶片之至少一實施形式，一第三層配 置在第一層和第二層之間，其中此第三層含有鈀。第三層 I 因此可由鈀構成。第三層直接鄰接於第一層和第二層。含 ❹ 有鈀之層之特徵是特別高的硬度。 依據光電半導體晶片之至少一實施形式，第二層是該 金屬層堆叠之遠離該半導體本體之覆蓋層。即，含有金的 第二層是該金屬層堆疊之封閉層，其在遠離該半導體本體 之此側上鄰接於該層堆疊。此種含有金之覆蓋層就該金屬 層堆叠之導線可接觸性而言特別有利。例如，含有金的金 屬線可特別簡易且機械穩定地固定在該金屬層堆疊之一含 Φ 有金的覆蓋層上。該金屬層堆疊在此種情況下可用作連接 墊，以用來與導線相接觸。 依據光電半導體晶片之至少一實施形式，含金的第二 層較含鎳的第一層還薄。層堆疊之層的厚度此處是指該層 在堆疊方向中之延伸度。層堆疊之堆叠方向較佳是垂直於 該半導體本體之晶晶生長之層而延伸。 層堆叠中所含有的含金的第二層較含鎳的第一層還薄 時，則此種層堆疊由於至少二種原因而特別有利：（一） 含鎳的較厚的第一層可特別良好地使該層堆疊受到機械上 201007997 的保護而免於刮傷，且使半導體本體不會受到機械上的損 傷（例如，裂開或折斷），否則此種損傷在與光電半導體晶 片接觸時會發生；（二）一種薄的、含有金的第二層在成本 上特別有利。 含有鎳的第一層所具有的厚度較佳是介於至少〇.4微 米和最多10.0微米之間。含有金之第二層之厚度較佳是介 於至少20奈米和最多200奈米之間，例如，介於至少30 奈米和最多50奈米之間。第三層之厚度例如介於1〇〇奈米 和2 0 0奈米之間。 依據光電半導體晶片之至少一實施形式”一種接觸層 配置在該半導體本體和該金屬層堆疊之間，其中該金靥層 堆叠直接與該接觸層相鄰。該接觸層上可特別容易地施加 該金屬層堆疊之多個層。此外，該接觸層可使金屬層堆疊 和半導體本體之間的電性接觸性獲得改良。最後，該接觸 層可使該金屬層堆疊在該半導體本體上的黏合性獲得改 良。 該接觸餍例如可以磊晶方式生長在該半導體本體上。 此外，該接觸層可藉由塗層方法（例如’濺鍍或物理氣相沈 積（PVD))而施加在半導體本體上。該接觸層例如可含有 金。例如，該接觸.層是一種由AuGe_，_ A^uZn或AuBe所形成 的層。此外，該接觸層亦可含有以下材料的至少一種或由 其構成：銅、鋁、銀。 依據光電半導體晶片之至少一實施形式，該金屬層堆 疊之至少一層以電鑛方式沈積而成。即，該至少一層是藉 由金靥沈積物之電化學沈積而施加在該金屬層堆疊之一層 201007997 或該接觸層上。此外，亦可將該金屬層堆叠之全部的層都 以電鑛方式沈積而成。在此種情況下，該金屬層堆畳完全 以電鍍方式產生。在以電鍍方式沈積該金屬層堆疊時，半 導體本體之不應被塗層的區域可以一種由光阻或SiN構成 的遮罩來覆蓋。在沈積過程之後，將該遮罩去除。該金屬 層堆疊可以電鍍方式沈積在一接觸層上，此一接觸層在沈 積之前例如藉由濺鍍而施加在半導體本體上。 依據光電半導體晶片之至少一實施形式，該金屬層堆 _ 叠之至少一層以無電流方式沈積而成。 p 例如，文件 “Last metal copper metallization for power device” ， Advanced Semiconductor Manufacturing Conference, 2007,第259頁至362頁中描述一種金屬層堆疊 之金屬層之無電流的沈積過程。該文件所揭示的內容藉由 參考而收納於此處。此外，文件“Low-cost electroless wafer bumping for 3 0 0 mm wafers” ，Business Briefing: Global Semiconductor Manufacturing Technology, 2003,第 1 至 5 頁 n 描述一種金屬層堆疊之金屬層之無電流的沈積過程。該文 件所揭示的內容藉由參考而收納於此處。 在金屬層堆疊之金靥層之無電流的沈積過程中，較佳 是使用一種具有銅、鋁或銀之胚層，其至少一部份例如在 隨後的各層之沈積中可被取代。 例如，該金屬層堆叠之至少一層以無電流的方式沈積 而成。此層可沈積在該層堆疊之位於此層下方的層上或沈 積於一接觸層上或直接沈積於半導體本體上。此外’該金 屬層堆叠之全部的層亦可以無電流的方式沈積而成° -10· 201007997 特別是亦可將該金屬層堆疊之至少一層以電鍍方式沈 積而成且至少另一層以無電流方式沈積而成。 此處所描述的光電半導體晶片另外亦與下述認知有 關：該金屬層堆叠之各層之電鍍及/或無電流之沈積容許該 光電半導體晶片以成本特別有利的方式來製成，此乃因該 種沈積技術能以較物理氣相沈積方法來進行的塗層方式更 有利地被實現。此外，藉由層堆疊之電鍍及/或無電流之沈 積可製成一種層堆疊，其層厚度較例如一種藉由物理氣相 _ 沈積方法來製成的金屬層堆疊的厚度大很多。例如，該層 堆疊可具有至少一含鎳之層，其厚度大於0.5微米。 依據光電半導體晶片之至少一實施形式，金屬層堆叠 包括：至少一含有鈀之層、至少一含有鎳之層、至少一含 有磷化鎳之層、至少一含有銅及/或鋁及/或銀之層、以及至 少一含金之層。該含金之層是該金屬層堆疊之遠離該半導 體本體之覆蓋層。該含有銅及/或鋁及/或銀之層是可選的 (optional)。含有磷化鎳之層因此較佳是含有至少7%且最多 φ 2 0 %之磷。 金屬層堆疊之上述構造就導電性、半導體本體上的黏 合性、特別是對該半導體本體之簡易的可製造性而言特別 有利，其中該半導體本體以磷化物-化合物半導體材料爲 主。 “以磷化物-化合物半導體材料爲主”在此處之意義 是指’該半導體本體或其至少一部份，特別是至少該活性 區，具有磷化物-化合物半導體材料，較佳是Ai„GamInmP 或 AsnGa-Ιηι·…P，其中 1 且 n + mS 1。因此， -11 - 201007997 此材料未必含有上述形式之以數學所表示之準確的組成。 反之’此材料可具有一種或多種摻雜物質以及其它成份。 然而’爲了簡單之故’上述形式只含有晶格（A1或As, Ga，In, P)之主要成份，這些主要成份之一部份亦可由少量的其它 物質來取代》 因此，由半導體本體來看時，該金屬層堆疊可由一種 層序列構成，此層序列具有以下各層：一由銅及/或鋁及/ 或銀構成的層或一包含這些材料中的至少一種的層、一由 磷化鎳構成的層、一由鈀構成的層以及一由金構成的層。 具有鎳和磷化鎳之層中此二層之位置亦可互換。 依據上述光電半導體晶片之至少一實施形式，該金屬 層堆疊包括多個層，其含有鈀、鎳、銅及/或鋁及/或銀和金。 含有金之層是該金屬層堆疊之遠離該半導體本體之層。 即，含金之第二層形成該金靥層堆疊之覆蓋層，其封閉其 遠離該半導體本體之外表面上的金屬層堆疊。此金屬層堆 叠未含磷。具有銅及/或鋁及/或銀之層是可選擇的 (optional) 0 上述具有多個層之金屬層堆叠就導電性、半導體本體 上的黏合性、特別是對該半導體本體之簡易的可製造性而 言特別有利，其中該半導體本體以氮化物-化合物半導體材 料爲主。 “以氮化物-化合物半導體材料爲主”在此處之意 義是指，該半導體本體或其至少一部份，特別是至少該 活性區，具有氮化物-化合物半導體材料，較佳是 AlnGamlnmN或由其所構成，其中0^11$1,0$111‘1且 -12- 201007997 n + mSl。因此，此材料未必含有上述形式之以數學所表示 之準確的組成。反之，此材料可具有一種或多種摻雜物質 以及其它成份。然而，爲了簡單之故，上述形式只含有晶 格（Al, Ga，In，N)之主要成份，這些主要成份之一部份亦可 由少量的其它物質來取代及/或補充。 此外，本發明提供一種光電組件。依據此光電組件之 至少一實施形式，此組件包括一終端載體，其具有至少二 個電性終端位置。該終端載體例如可以是一種載體架（亦稱 爲導線架），具有二個電性互相絕緣的終端位置，其用來與 該光電組件形成電性接觸。該載體架例如可以一種電性絕 緣之塑料或陶瓷材料來噴鍍。此外，該終端載體亦可以是 一種具有基體之電路板，該基體由電性絕緣的材料構成。 導電軌及/或電性終端位置在該基體上被結構化。 依據該光電組件之至少一實施形式，該光電組件包括 至少一如上所述之光電半導體晶片。即，該些光電半導體 晶片之特徵亦揭示在該光電組件中。 依據該光電組件之至少一實施形式，該光電半導體晶 片之金屬層堆叠藉由至少一接觸線而與至少二個電性終端 位置之至少一個形成導電性的連接。即，該金屬層堆疊例 如位於該光電半導體晶片之輻射通過面上。藉由導線接 觸，則該金屬層堆叠可導電地與該至少二個電性終端位置 之一形成導電性的連接。該光電半導體晶片可以其遠離該 金屬層堆叠之此側施加在該至少二個電性終端位置之另一 個電性終端位置上且與該另一個電性終端位置形成導電性 連接。例如，在該光電半導體晶片之半導體本體之遠離該 -13- 201007997 輻射通過面之下側上亦可存在一種金屬層堆疊，如先前的 多個實施形式所述。 依據光電組件之至少一實施形式，該組件包括：一終 端載體，其具有至少二個電性終端位置；以及至少一如上 所述之光電半導體晶片。該金屬層堆疊經由至少一接觸線 而與該至少二個電性終端位置之至少一個形成導電性連 接。 此處所述之光電組件另外與下述認知有關：此處之金 美 屬層堆疊特別適合用來達成導線接觸（導線連接）。在上述 Ο 之金屬層堆叠上可特別簡易且抗機械性地施加一接觸線。 經由此一接觸線可對該光電半導體晶片之η-側施加電流。 依據此處所述之光電組件之至少一實施形式，該金屬 層堆疊包括一遠離該半導體本體之覆蓋層，其中此覆蓋層 和該接觸線含有金或由金構成。即，該金屬層堆叠之覆蓋 層和該接觸線在本實施形式中是由相同的材料（較佳是金） 構成，其中該接觸線藉由該光電半導體晶片而導電性地與 _ 該終端載體之一終端位置相連接。就導電性和該接觸線可 簡易地固定至該金屬層堆疊之覆蓋面上而言，金是特別有 利的》 上述之光電半導體晶片以及光電組件以下將依據實施 例和所屬的圖式來詳述。 【實施方式】 各圖式和實施例中相同或作用相同的各組件分別設有 相同的參考符號。所示的各元件和各元件之間的比例未必 依比例繪出。反之，爲了清楚及/或較易理解之故各圖式的 -14- 201007997 —些元件已予放大地顯示出。 第1圖所示之光電半導體晶片之第一實施例中，該光 電半導體晶片1包括半導體本體2以及金屬層堆疊3,其施 加在該半導體本體2之輻射發出面2a上。該光電半導體晶 片目前是一種發光二極體晶片，其以薄膜形式的構造來形 成。 半導體本體以磷化物-化合物半導體爲主。 該金屬層堆疊3藉由一接觸層30而施加在該半導體本 ^ 體2之輻射發出面2a上。該接觸層30例如藉由物理氣相 沈積法而沈積在該半導體本體2之輻射發出面2a上。 該層堆疊3之各層以無電流方式或以電鍍方式依序施 加而成。該層堆疊3因此包括一由鈀構成的層31、一由鎳 構成的層32、一由磷化鎳構成的層33、一由銅及/或鋁及/ 或銀構成的層34以及一由金構成的層35。 含鈀之層31所具有的厚度較佳是介於至少100奈米且 最多500奈米之間，例如，介於100奈米和200奈米之間。 φ 含鎳之層32，33所具有的厚度dl較佳是介於至少0.25微 米且最多1〇.〇微米之間，其中此二層例如可具有相同的厚 度。含金之層35之厚度d2較佳是在30奈米至50奈米之 間。 該二層32和33是上述層堆叠之含鎳的第一層。即’ 此第一層目前是由二個部份層來形成，其中面向該半導體 本體2之層33例如由磷化鎳（NiP)構成，且遠離該半導體本 體之層32由鎳構成。 該層堆疊具有一種含金之層35，其形成上述之二個 -15- .201007997 層。第二層同時形成該層堆叠3之遠離該半導體本體2之 覆蓋層。 該層堆疊3之其它特徵是可簡易地製成、良好的可連 接性和含鎳之層32, 33之硬度。上述各層由半導體本體來 觀看時較佳是以圖中所示的順序施加而成且互相直接相 鄰。即，該層堆疊之各別的層直接相鄰且處於直接的接觸 中 〇 具有含磷之層33之層堆疊3就其與半導體本體相關的 & 黏合性和電性而言特別有利，該半導體本體以磷化物-化合 物半導體材料爲主。 此外，在輻射發出面2a上可配置多個接觸結構，例如， 接觸軌或接觸架，其導電性地與金屬層堆疊3相連接。該 些接觸結構可具有與金屬層堆疊相同的構造。此外，該些 接觸結構亦可包括不同的構造和其它材料。例如，各接觸 結構可包括一種銅層’其配置在該接觸層30上且以鎳來包 封。各接觸結構使經由該層堆疊3而注入的電流分佈在整 ❹ 個輻射發出面2a上。 請參閱第2圖，其顯示此處所述之光電半導體晶片之 第二實施例。與第1圖所示之光電半導體晶片不同，第2 圖之光電半導體晶片1包括半導體本體2，其以氮化物-化 合物半導體材料爲主。與第1圖不同，第2圖之層堆疊3 未包括含磷之層。此種層堆叠3就其與氮化物-化合物半導 體材料爲主之半導體本體2之黏合性和電性而言特別有 利。 在第1圖和第2圖所述的實施例中，該接觸層3〇都是 -16- .201007997 可選擇的（optional)。即，在此處所述之光電半導體晶片之 至少一些實施例中該層堆疊可直接施加在半導體本體2之 輻射發出面2a上。該層堆叠較佳是以電鍍方式及/或無電 流方式沈積在該半導體本體2上》 在上述二個實施例中，含金之第二層35所具有的厚度 d2較含鎳之第一層32，33者小很多。含鎳之層之厚度dl 因此至少是0.5微米。含金之層35之厚度d2可以是1〇〇 奈米或更小。 _ 請參閱第3圖，其顯示此處所述之光電組件之一實施 例之切面圖。本實施例中光電半導體晶片就和第1圖和第 2圖中一樣是施加在一終端載體5上，該終端載體5具有二 個電性終端位置51，52。此處之金屬層堆疊3不只可位於 該半導體本體2之輻射發出面2a上，且亦可位於半導體本 體2之遠離該輻射發出面2a之下側上。 配置在該輻射發出面2a上的金屬層堆疊3藉由一接觸 線4而與第二電性終端位置52導電性地相連接。反之，半 ^ 導體晶片以其下側施加在該終端載體5之第一終端位置51 上。 半導體本體2包括活性區21，其適合在對該半導體本 體2施加電流下用來產生電磁輻射。 本發明當然不限於依據各實施例中所作的描述。反 之，本發明包含每一新的特徵和各特徵的每一種組合’特 別是包含各申請專利範圍或不同實施例之各別特徵之每-種組合，當相關的特徵或相關的組合本身未明顯地顯示# 各申請專利範圍中或各實施例中時亦屬本發明。 -17- 201007997 本專利申請案主張德國專利申請案ίο 2008 035 254.3 之優先權，其已揭示的整個內容在此一倂作爲參考。 【圖式簡單說明】 第1圖和第2圖顯示此處所述之光電半導體晶片之第 一和第二實施例的切面圖。 第3圖顯示此處所述之光電組件之一實施例之切面圖。 【主要元件符號說明】201007997 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an optoelectronic semiconductor wafer. [Prior Art] An optoelectronic semiconductor wafer in the form of a thin film has been described, for example, in the documents of J. 00/13, 281, 1981 and vol. 0, 905, 797, the entire disclosure of which is incorporated herein by reference. Here. g SUMMARY OF THE INVENTION It is an object of the invention to provide an optoelectronic semiconductor wafer which can be produced particularly cost-effectively. Another object of the present invention is to provide an optoelectronic semiconductor wafer which is preferably mechanically stable. Furthermore, it is an object of the present invention to provide an optoelectronic component having an optoelectronic semiconductor wafer. According to at least one embodiment of the optoelectronic semiconductor wafer, the optoelectronic semiconductor wafer comprises a semiconductor body. The semiconductor body can be an epitaxially grown layer structure that can be grown on a growth substrate that is removed or at least thinned from the finished semiconductor body after the end of the Q epitaxial growth. The optoelectronic semiconductor wafer can be a semiconductor wafer in the form of a thin film construction. The semiconductor body can thus have a thickness of 20 microns or less, which is in particular 10 microns or less. The semiconductor body, for example, includes an active region for detecting or generating electromagnetic radiation. For example, the optoelectronic semiconductor wafer is a detector wafer such as a photodiode or an electroluminescent diode wafer such as a light emitting diode wafer or a laser diode wafer. 201007997 The semiconductor body is preferably formed in a III/V-semiconductor system. That is, it preferably has a III/V-compound-semiconductor material. A ΠΙ/ν-compound-semiconductor material having at least one element derived from a third group, such as 'B, Al, Ga, In, and an element derived from the fifth group, for example, N, P, As . This commemoration "ΙΠ/ν_compound-semiconductor material" especially includes a population (gr0Up) from a monoterpenic, diterpene or quaternary compound comprising at least one element from a third group and at least one from a fifth group The element 'for example' includes nitride- and phosphide-compound-semiconductor. Such di-, ternary or quaternary compounds may additionally have one or more dopant species and other components. The semiconductor body can also be fabricated from other material systems, such as II/VI-compound-semiconductor materials. The II/VI-compound·semiconductor material has at least one element derived from the second group, for example, Be, Mg, Ca, Sr, and an element derived from the sixth group 'e.g., 0, S, Se. The II/VI-compound-semiconductor material comprises, in particular, a binary, ternary or quaternary compound comprising at least one element from the second group and at least one element from the sixth group. Such binary, ternary or quaternary compounds may, for example, have one or more dopant species and other components. For example, ZnO, ZnMgO, CdS, ZnCdS, and MgBeO belong to the II/VI-compound-semiconductor material. In accordance with at least one embodiment of the optoelectronic semiconductor wafer, the optoelectronic semiconductor wafer has a stack of electrically conductive metal ruthenium layers which are arranged on the semiconductor body. The metal layer stack is formed from at least two layers containing different metals. The layer stack is electrically conductive so that current can be applied to the 201007997 semiconductor body via the layer stack. The metal layer stack can be applied to the upper side of the semiconductor body. The layer stack can be a so-called bond pad for the contact line through which the semiconductor wafer can be contacted. The stack is thus situated on the radiation passage surface of the semiconductor body. That is, the layer stack is applied to a portion of the outer surface of the semiconductor body, and the electromagnetic radiation is emitted through the portion of the outer surface during operation of the body. Further, the metal layer stack may be additionally located below the radiation passage surface of the semiconductor. The metal layer stack can then be used to stack the semiconductor wafer and impart an additional mechanism to the semiconductor wafer, i.e., the metal layer stack can also serve as a back contact region. According to at least one embodiment of the optoelectronic semiconductor wafer, the stack comprises at least one first layer comprising nickel. Preferably, the nickel-containing material is disposed to be level with the epitaxially grown layer of the semiconductor body. The layer may be composed of, for example, nickel or nickel phosphide (NiP). Further, the stacking may also comprise a layer of nickel and another layer of nickel phosphide, according to at least one embodiment of the optoelectronic semiconductor wafer, the stack comprising at least one second layer comprising gold. That is, the metal layer stack may be composed of gold or comprise a gold-containing compound or a gold-containing second layer and is therefore preferably arranged to be parallel to the layer of the semiconductor body. According to at least one embodiment of the optoelectronic semiconductor wafer, this is between the semiconductor body and the second layer. That is, the electrically conductive stack includes the first layer and the second layer. The first layer contains nickel containing gold. The two layers are arranged parallel to each other and preferably parallel to each other. The metal is fixed to the metal layer, and the metal is discharged. The distance of the body is used for welding stability. The metal layer stack is therefore more suitable. The layer of the first metal layer. A second alloy of metal layers stacked. The epitaxial growth of the first layer of the metal layer, the second layer of the semiconductor -6-201007997 body of the epitaxial growth layer extends. The first layer containing nickel is disposed closer to the semiconductor body than the second layer containing gold. According to at least one embodiment of the optoelectronic semiconductor wafer, the optoelectronic semiconductor wafer comprises a semiconductor body and a conductive metal layer stack on the upper side of the semiconductor body, wherein the metal layer stack comprises at least one first layer containing nickel and one A second layer containing gold disposed between the semiconductor body and the second layer. The optoelectronic semiconductor wafer described herein is additionally based on the recognition that the layer containing nickel is a layer which is particularly hard, can be easily fabricated, and can be easily regenerated. This layer may, for example, be composed of nickel or additionally contain phosphorus. This layer can be formed, for example, by nickel phosphide. Since the layer containing nickel has a particularly hard surface, the risk of scratching the layer, for example, is reduced. When the respective optoelectronic semiconductor wafers of the wafer composite are tested for their functions by a so-called "wafer test", the scratch of the conductive metal layer stack occurs, for example, in the wafer composite process in the process of the optoelectronic semiconductor wafer. In. Now, if the stack of electrically conductive metal layers consists primarily of a softer metal (eg, aluminum Φ or gold), the stack of layers will scratch during the "wafer test." For example, the recognizability of the metal layer stack can be reduced by electronic image processing in a later process. Furthermore, it has been shown that the second layer containing gold is viewed from the semiconductor body after the first layer containing nickel, and the contactability of the metal layer stack is simplified by a contact line. For example, the adhesion of the gold-containing contact line on the conductive metal layer stack can be improved by the second layer containing gold. Finally, it has been shown that the nickel-containing layer is a highly reliable and cost-effective metal layer of the semiconductor body in the conductive metal layer 201007997 stack. This metal layer stack thus protects the semiconductor body from mechanical loading when the optoelectronic semiconductor wafer is contacted. Overall, the optoelectronic semiconductor wafers described herein achieve a simplified and cost effective process. In addition, optoelectronic semiconductor wafers can be protected to particularly well combat mechanical loads. According to at least one embodiment of the optoelectronic semiconductor wafer, a third layer is disposed between the first layer and the second layer, wherein the third layer contains palladium. The third layer I can thus consist of palladium. The third layer is directly adjacent to the first layer and the second layer. The layer containing iridium with palladium is characterized by a particularly high hardness. According to at least one embodiment of the optoelectronic semiconductor wafer, the second layer is a cover layer of the metal layer stacked away from the semiconductor body. That is, the second layer containing gold is a closed layer of the metal layer stack that is adjacent to the layer stack on the side remote from the semiconductor body. Such a gold-containing cover layer is particularly advantageous in terms of wire contactability of the metal layer stack. For example, a gold-containing metal wire can be attached to a cover layer containing Φ gold on one of the metal layer stacks in a particularly simple and mechanically stable manner. The metal layer stack can be used as a connection pad in this case for contact with the wires. According to at least one embodiment of the optoelectronic semiconductor wafer, the second layer containing gold is thinner than the first layer containing nickel. The thickness of the layer of the layer stack here refers to the extent of the layer in the stacking direction. Preferably, the stacking direction of the layer stack extends perpendicular to the layer of crystal growth of the semiconductor body. When the second layer containing gold contained in the layer stack is thinner than the first layer containing nickel, the layer stack is particularly advantageous for at least two reasons: (1) The thicker first layer containing nickel can be The layer stack is particularly well protected from mechanical scratching by the 201007997, and the semiconductor body is not mechanically damaged (eg, cracked or broken), otherwise the damage is in contact with the optoelectronic semiconductor wafer. Will occur; (b) a thin, gold-containing second layer is particularly advantageous in terms of cost. The first layer containing nickel preferably has a thickness of between at least 〇.4 μm and at most 10.0 μm. The thickness of the second layer containing gold is preferably between at least 20 nm and at most 200 nm, for example between at least 30 nm and at most 50 nm. The thickness of the third layer is, for example, between 1 nanometer and 200 nanometers. According to at least one embodiment of the optoelectronic semiconductor wafer, a contact layer is arranged between the semiconductor body and the metal layer stack, wherein the metal layer stack is directly adjacent to the contact layer. The contact layer can be applied particularly easily. The plurality of layers of the metal layer stack. In addition, the contact layer can improve the electrical contact between the metal layer stack and the semiconductor body. Finally, the contact layer can bond the metal layer on the semiconductor body. The contact is grown, for example, epitaxially on the semiconductor body. Furthermore, the contact layer can be applied to the semiconductor body by a coating method such as 'sputtering or physical vapor deposition (PVD)). The contact layer may, for example, contain gold. For example, the contact layer is a layer formed of AuGe_, _A^uZn or AuBe. Further, the contact layer may also contain or consist of at least one of the following materials: copper, Aluminum, silver. According to at least one embodiment of the optoelectronic semiconductor wafer, at least one layer of the metal layer stack is deposited by electro-mineralization. It is applied to one layer of the metal layer stack 201007997 or the contact layer by electrochemical deposition of gold deposits. In addition, all the layers of the metal layer stack may be deposited by electro-mineralization. In this case, the metal layer stack is completely produced by electroplating. When the metal layer stack is deposited by electroplating, the region of the semiconductor body which should not be coated can be covered by a mask consisting of photoresist or SiN. After the deposition process, the mask is removed. The metal layer stack can be deposited on a contact layer by electroplating, and the contact layer is applied to the semiconductor body by sputtering, for example by sputtering. According to at least one of the optoelectronic semiconductor wafers. In an embodiment, at least one layer of the metal layer stack is deposited in a currentless manner. p For example, the document "Last metal copper metallization for power device", Advanced Semiconductor Manufacturing Conference, 2007, pages 259 to 362. The current-free deposition process of the metal layer of the metal layer stack. The contents disclosed in this document are incorporated by reference. In addition, the document "Low-cost electroless wafer bumping for 300 mm wafers", Business Briefing: Global Semiconductor Manufacturing Technology, 2003, pages 1 to 5 describes a currentless deposition process for a metal layer stacked metal layer. The disclosure of this document is hereby incorporated by reference. In the currentless deposition of the metal layer of the metal layer stack, it is preferred to use a layer of copper, aluminum or silver, at least one of which Parts can be substituted, for example, in the deposition of subsequent layers. For example, at least one layer of the metal layer stack is deposited in a currentless manner. This layer can be deposited on the layer of the layer stack below this layer or deposited on a contact layer or deposited directly on the semiconductor body. Furthermore, all of the layers of the metal layer stack can also be deposited in a current-free manner. In particular, at least one layer of the metal layer stack can be deposited by electroplating and at least one other layer can be formed in a currentless manner. Deposited. The optoelectronic semiconductor wafers described herein are additionally associated with the recognition that electroplating and/or currentless deposition of the layers of the metal layer stack allows the optoelectronic semiconductor wafer to be produced in a particularly cost-effective manner. The deposition technique can be more advantageously realized in a coating manner which is carried out in a physical vapor deposition method. Furthermore, a layer stack can be formed by plating of layer stacks and/or currentless deposition, the layer thickness of which is much greater than the thickness of a metal layer stack made, for example, by a physical vapor deposition method. For example, the layer stack can have at least one nickel-containing layer having a thickness greater than 0.5 microns. In accordance with at least one embodiment of the optoelectronic semiconductor wafer, the metal layer stack comprises: at least one layer comprising palladium, at least one layer comprising nickel, at least one layer comprising nickel phosphide, at least one comprising copper and/or aluminum and/or silver a layer, and at least one layer containing gold. The gold-containing layer is a cover layer of the metal layer stacked away from the body of the semiconductor. The layer containing copper and/or aluminum and/or silver is optional. The layer containing nickel phosphide thus preferably contains at least 7% and at most φ 20% of phosphorus. The above-described configuration of the metal layer stack is particularly advantageous in terms of electrical conductivity, adhesion on the semiconductor body, and particularly ease of manufacturability of the semiconductor body, wherein the semiconductor body is dominated by a phosphide-compound semiconductor material. By "phosphorus-compound semiconductor material-based" it is meant herein that the semiconductor body or at least a portion thereof, particularly at least the active region, has a phosphide-compound semiconductor material, preferably Ai„GamInmP. Or AsnGa-Ιηι·...P, where 1 and n + mS 1. Therefore, -11 - 201007997 This material does not necessarily contain the exact composition of the above form expressed mathematically. Conversely 'this material may have one or more dopants And other ingredients. However, 'for the sake of simplicity', the above form only contains the main components of the crystal lattice (A1 or As, Ga, In, P), and some of these main components can also be replaced by a small amount of other substances. When viewed from a semiconductor body, the metal layer stack can be formed by a layer sequence having the following layers: a layer of copper and/or aluminum and/or silver or a layer comprising at least one of these materials, a layer composed of nickel phosphide, a layer composed of palladium, and a layer composed of gold. The positions of the layers in the layer having nickel and nickel phosphide may also be interchanged. In at least one embodiment of the wafer, the metal layer stack comprises a plurality of layers comprising palladium, nickel, copper and/or aluminum and/or silver and gold. The gold-containing layer is a layer of the metal layer stacked away from the semiconductor body That is, the second layer containing gold forms a cover layer of the stack of gold layers that encloses a stack of metal layers away from the outer surface of the semiconductor body. The metal layer stack is not phosphorous. It has copper and/or aluminum and / or a layer of silver is optional. The above metal layer stack having a plurality of layers is particularly advantageous in terms of electrical conductivity, adhesion on the semiconductor body, and in particular, ease of manufacturability of the semiconductor body. Wherein the semiconductor body is mainly a nitride-compound semiconductor material. The term "nitride-compound semiconductor material" as used herein means that the semiconductor body or at least a portion thereof, particularly at least the active region, Having a nitride-compound semiconductor material, preferably of or composed of AlnGamlnmN, wherein 0^11$1, 0$111'1 and -12-201007997 n + mSl. Therefore, the material does not necessarily contain the above form. The exact composition represented by the school. Conversely, the material may have one or more dopants and other components. However, for the sake of simplicity, the above form only contains the main components of the crystal lattice (Al, Ga, In, N). A part of these main components may also be replaced and/or supplemented by a small amount of other substances. Furthermore, the invention provides an optoelectronic component. According to at least one embodiment of the optoelectronic component, the component comprises a terminal carrier having at least two Electrical terminal position. The terminal carrier can be, for example, a carrier frame (also referred to as a lead frame) having two electrically insulated terminal locations for electrical contact with the optoelectronic component. It can be sprayed with an electrically insulating plastic or ceramic material. Furthermore, the terminal carrier can also be a circuit board having a substrate which is composed of an electrically insulating material. The conductive rails and/or electrical termination locations are structured on the substrate. According to at least one embodiment of the optoelectronic component, the optoelectronic component comprises at least one optoelectronic semiconductor wafer as described above. That is, the features of the optoelectronic semiconductor wafers are also disclosed in the optoelectronic component. In accordance with at least one embodiment of the optoelectronic component, the metal layer stack of the optoelectronic semiconductor wafer is electrically conductively connected to at least one of the at least two electrical termination locations by at least one contact line. That is, the metal layer stack is located, for example, on the radiation passage surface of the optoelectronic semiconductor wafer. The metal layer stack is electrically conductively coupled to one of the at least two electrical termination locations by wire contact. The optoelectronic semiconductor wafer can be applied to another electrical termination location of the at least two electrical termination locations and to form a conductive connection with the other electrical termination location on the side remote from the stack of metal layers. For example, a metal layer stack may also be present on the underside of the semiconductor body of the optoelectronic semiconductor wafer remote from the radiation passage surface, as described in previous embodiments. According to at least one embodiment of the optoelectronic component, the component comprises: a terminal carrier having at least two electrical termination locations; and at least one optoelectronic semiconductor wafer as described above. The metal layer stack is electrically connected to at least one of the at least two electrical termination locations via at least one contact line. The optoelectronic components described herein are additionally related to the recognition that the gold-colored layer stacks herein are particularly suitable for achieving wire contact (wire connection). A contact line can be applied particularly easily and mechanically on the metal layer stack of the above. Current can be applied to the n-side of the optoelectronic semiconductor wafer via this contact line. In accordance with at least one embodiment of the optoelectronic component described herein, the metal layer stack includes a cover layer remote from the semiconductor body, wherein the cover layer and the contact line comprise gold or are comprised of gold. That is, the cover layer of the metal layer stack and the contact line are formed of the same material (preferably gold) in the embodiment, wherein the contact line is electrically conductive with the photo-semiconductor wafer One of the terminal locations is connected. Gold is particularly advantageous in terms of electrical conductivity and the fact that the contact line can be easily fixed to the cover of the metal layer stack. The above-mentioned optoelectronic semiconductor wafer and optoelectronic component will be described in detail below based on the embodiment and the associated drawings. [Embodiment] Each of the components in the drawings and the embodiments having the same or the same functions is provided with the same reference numerals. The components shown and the ratios between the components are not necessarily drawn to scale. Conversely, for the sake of clarity and/or ease of understanding, the components of the drawings - 14 - 201007997 - have been shown in an enlarged scale. In a first embodiment of the optoelectronic semiconductor wafer shown in Fig. 1, the optoelectronic semiconductor wafer 1 comprises a semiconductor body 2 and a metal layer stack 3 applied to the radiation emitting surface 2a of the semiconductor body 2. The optoelectronic semiconductor wafer is currently a light-emitting diode wafer which is formed in the form of a film. The semiconductor body is mainly composed of a phosphide-compound semiconductor. The metal layer stack 3 is applied to the radiation emitting surface 2a of the semiconductor body 2 by a contact layer 30. The contact layer 30 is deposited on the radiation emitting surface 2a of the semiconductor body 2, for example, by physical vapor deposition. The layers of the layer stack 3 are sequentially applied in a currentless manner or by electroplating. The layer stack 3 thus comprises a layer 31 of palladium, a layer 32 of nickel, a layer 33 of nickel phosphide, a layer 34 of copper and/or aluminum and/or silver, and a layer 34 Layer 35 of gold. The palladium-containing layer 31 preferably has a thickness of between at least 100 nm and at most 500 nm, for example between 100 nm and 200 nm. The φ nickel-containing layers 32, 33 preferably have a thickness dl of between at least 0.25 μm and at most 1 μm, wherein the two layers may have the same thickness, for example. The thickness d2 of the gold-containing layer 35 is preferably between 30 nm and 50 nm. The two layers 32 and 33 are the first layer of nickel containing the above layer stack. That is, the first layer is currently formed of two partial layers, wherein the layer 33 facing the semiconductor body 2 is composed of, for example, nickel phosphide (NiP), and the layer 32 away from the semiconductor body is made of nickel. The layer stack has a gold-containing layer 35 which forms the two -15-.201007997 layers described above. The second layer simultaneously forms a cover layer of the layer stack 3 remote from the semiconductor body 2. Other features of the layer stack 3 are the ease of fabrication, good bondability and hardness of the nickel-containing layers 32,33. When the above layers are viewed from the semiconductor body, they are preferably applied in the order shown in the drawing and directly adjacent to each other. That is, the individual layers of the layer stack are directly adjacent and in direct contact. The layer stack 3 having the phosphorus-containing layer 33 is particularly advantageous in terms of its <adhesiveness and electrical properties associated with the semiconductor body, The semiconductor body is mainly composed of a phosphide-compound semiconductor material. Furthermore, a plurality of contact structures, for example contact rails or contact holders, which are electrically conductively connected to the metal layer stack 3, can be arranged on the radiation emitting surface 2a. The contact structures may have the same configuration as the metal layer stack. In addition, the contact structures can also include different configurations and other materials. For example, each contact structure can include a copper layer' disposed on the contact layer 30 and encapsulated with nickel. Each contact structure distributes the current injected through the layer stack 3 over the entire radiation emitting surface 2a. Referring to Figure 2, there is shown a second embodiment of an optoelectronic semiconductor wafer as described herein. Unlike the optoelectronic semiconductor wafer shown in Fig. 1, the optoelectronic semiconductor wafer 1 of Fig. 2 includes a semiconductor body 2 mainly composed of a nitride-compound semiconductor material. Unlike the first figure, the layer stack 3 of Fig. 2 does not include a layer containing phosphorus. Such a layer stack 3 is particularly advantageous in terms of its adhesion and electrical properties to the semiconductor body 2 of the nitride-compound semiconductor material. In the embodiments described in Figures 1 and 2, the contact layer 3〇 is -16-.201007997 optional. That is, in at least some embodiments of the optoelectronic semiconductor wafer described herein, the layer stack can be applied directly to the radiation emitting face 2a of the semiconductor body 2. The layer stack is preferably deposited on the semiconductor body 2 in an electroplated and/or currentless manner. In the above two embodiments, the gold-containing second layer 35 has a thickness d2 that is greater than the first layer containing nickel. 32,33 are much smaller. The thickness dl of the nickel-containing layer is therefore at least 0.5 microns. The thickness d2 of the gold-containing layer 35 may be 1 奈 nanometer or less. _ See Figure 3, which shows a cross-sectional view of one embodiment of the optoelectronic component described herein. The optoelectronic semiconductor wafer in this embodiment is applied to a terminal carrier 5 having two electrical terminal positions 51, 52 as in Figs. 1 and 2. The metal layer stack 3 here can be located not only on the radiation emitting surface 2a of the semiconductor body 2, but also on the lower side of the semiconductor body 2 remote from the radiation emitting surface 2a. The metal layer stack 3 disposed on the radiation emitting surface 2a is electrically connected to the second electrical terminal location 52 by a contact line 4. On the other hand, the semi-conductor wafer is applied with its underside on the first end position 51 of the terminal carrier 5. The semiconductor body 2 comprises an active region 21 adapted to generate electromagnetic radiation when an electrical current is applied to the semiconductor body 2. The invention is of course not limited to the description made in accordance with the various embodiments. Conversely, the invention includes each novel feature and each combination of features, and in particular, each of the various combinations of the various features of the application or the various embodiments of the invention. The present invention is also in the scope of each of the patent applications or in the respective embodiments. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 and Fig. 2 show cutaway views of first and second embodiments of the optoelectronic semiconductor wafer described herein. Figure 3 shows a cross-sectional view of one embodiment of the optoelectronic component described herein. [Main component symbol description]
1 光 電 半 導 體晶片 2 半 導 體 本 體 2a 輻 射 發 出 面 2 1 活 性 區 3 金 屬 層 堆 疊 30 接 觸 層 31 接 觸 層 32 含 鎳 之 層 (第一層） 33 含 磷 化 鎳 之層（第一 層） 34 含 銅 之 層 35 含 金 之 層 (第二層， 覆蓋層） 4 接 una 觸 線 5 終 端 載 體 51 終 端 位 置 52 終 端 位 置 dl 第 — 層 的 厚度 d2 第 二 層 的 厚度 -18-1 Photoelectric semiconductor wafer 2 Semiconductor body 2a Radiation emitting surface 2 1 Active region 3 Metal layer stack 30 Contact layer 31 Contact layer 32 Nickel-containing layer (first layer) 33 Nickel phosphide-containing layer (first layer) 34 Copper Layer 35 gold-containing layer (second layer, cover layer) 4 una contact line 5 terminal carrier 51 terminal position 52 terminal position dl first layer thickness d2 thickness of second layer -18-