201007900 .九、發明說明： 【發明所屬之技術領域】 • 本發明係有關於嵌埋半導體元件之封裝基板及其製 .法，尤指一種具有細間距之線路層之嵌埋半導體元件之封 裝基板及其製法。 【先前技術】 • 隨著半導體封裝技術的演進，除了傳統打線式（Wire bonding)半導體封裝技術以外，目前半導體裝置 ©(Semiconductor device)已開發出不同的封裝型態，例如 直接在一封裝基板（package substrate)中嵌埋並電性整 合一例如具有積體電路之半導體晶片，此種封裝件可縮減201007900. IX. Description of the Invention: [Technical Field] The present invention relates to a package substrate for embedding a semiconductor device and a method for fabricating the same, and more particularly to a package substrate with embedded semiconductor elements having a fine pitch circuit layer And its method of production. [Prior Art] • With the evolution of semiconductor packaging technology, in addition to the conventional wire bonding semiconductor packaging technology, the semiconductor device (Semiconductor device) has developed different package types, such as directly on a package substrate ( Buried and electrically integrated into a package substrate, such as a semiconductor wafer having an integrated circuit, the package can be reduced
整體半導體裝置之體積並提昇電性功能，遂成為一種封裝 的趨勢。 X 請參閱第1A至IF圖，係為習知之嵌埋半導體元件之 封裝基板之製法示意圖；如第1A圖所示，提供一具有開 ⑩口 100之基板本體10，於該開口 1〇〇中容置有半導體晶 片11，並於該半導體晶片u與開口 1〇〇之間的間隙中填 入、、’《 5材料1 2 ’以將該半導體晶片11固定於該開口 1 〇 〇 中，該半導體晶片11係具有相對應之作用面lla及非作 用面lib於該作用面lla具有複數矩陣排列之電極塾 111;如第1B圖所示，於該基板本體1〇、半導體晶片^ 之作用面lla上形成有第一介電層13,且於該第一介電 層13中形成有複數第一開孔13〇，以分別對應各該電極 塾111 ;如第1C圖所示，於該些電極墊U1、第一開孔 110884 5 201007900 ' 130之孔壁及第—介電層u上形成有導電層u，且於該 導包層14上形成有阻層15，於該阻層^中形成有複數 - 開口區150，1 ψ，加八 、γ α|5刀之開口區150對應外露出該些電 -極塾111上之導電層14;如第D圖所示，於該些開口區 150中之導電層u 上-电錢形成有第一線路層16，並於該 些第一開孔130 # + 中形成有複數第一導電盲孔17，以分別The size of the overall semiconductor device and the enhancement of electrical functions have become a trend in packaging. X. Referring to FIGS. 1A to IF, it is a schematic diagram of a conventional method for embedding a semiconductor device embedded in a semiconductor device; as shown in FIG. 1A, a substrate body 10 having a 10-port 100 is provided, in the opening 1 A semiconductor wafer 11 is housed, and a gap between the semiconductor wafer u and the opening 1 is filled with a material of the material 1 in the opening 1 ,. The semiconductor wafer 11 has an electrode 塾 111 having a plurality of matrix arrays corresponding to the active surface 11a and the non-active surface lib; and as shown in FIG. 1B, the substrate body 1 and the surface of the semiconductor wafer a first dielectric layer 13 is formed on the lla, and a plurality of first openings 13 形成 are formed in the first dielectric layer 13 to respectively correspond to the respective electrodes 塾 111; as shown in FIG. 1C, The electrode pad U1 and the first opening 110884 5 201007900 '130 are formed with a conductive layer u on the hole wall and the first dielectric layer u, and a resist layer 15 is formed on the guide layer 14 in the resist layer Forming a complex-opening area 150,1 ψ, plus eight, γ α|5 knife opening area 150 corresponding to the exposed a conductive layer 14 on the electro-electrode 111; as shown in FIG. D, on the conductive layer u in the open regions 150, the first circuit layer 16 is formed by the electric money, and the first openings are formed in the first openings 130 # + is formed with a plurality of first conductive blind holes 17 to respectively
對應電性連接各兮雷技勒、 J . 該電極墊111，且於該些第一導電盲孔17 上形成有電性連接埶】7 _ 〇線請;如第ΓΕ=以電性連接該第-線路層16之Correspondingly, each of the electrode pads 111 is electrically connected, and an electrical connection is formed on the first conductive blind holes 17; 7 _ 〇 line; if the first ΓΕ = electrically connected First-line layer 16
1£及1£”圖所示，移除該阻層15及 圖所覆蓋之上導電層14,以露出該第一線路層16;如第1F 介電層13及第一線路層16上形成有增 二=該增層結構1δ係包括至少一第二介電請、 =該弟二介電層181上之第二線路層183、以及複數 形成於該第二介電層 路層16, 183之第-導=性連接該第一及第二線 之綠致ρ 82,該增層結構18最外層 %最外電性接觸墊184,且於該增層結構 數防“開孔19Q 19?防焊層19中並形成有複 = 以對應外露各該電性接觸墊184。 上可知，該第一線路層j 6係經 以電性連接該第一導 广連接墊⑹ 内圈之雷矩陣排列並位於 電生連接墊161引出之線路162倍你钟认工而 接墊161之間；惟，該電性連接墊161即佔用大背^連 線空間，使得該些電性連接墊161 二伤的佈 目前的先進製程，電性連接塾〗61=更小，例如 1之間距為1^130/^， 110884 6 201007900 屯性運接塾161之直技為1)=70"111，線寬（51)/線距(^2) 為20 # m /20 // m ’僅旎勉強通過一條線路a?，而難以佈 ,&更夕線路1 62，如此則矩陣排列並位於更㈣之電性連 接塾161無法在同一層中再引出線路162，使得位於内圈 的電性連接塾161必須再向上增層，並以疊孔（办⑽ .卜引出，導致線路增層的數目增加，因而增加製程 奴雜度及多層間的對位困難等問題。 的佑：Γ ;广於上述之問題’如何避免習知技術中線路層 ❹的佈線工間不足’進而造成增層結構 程複雜度及多層間的對位困難等問題，實已成為目：：： 解決之課題。 只已成為目則亟欲 【發明内容】 鑒於上述習知技術之缺失，本發明之 一種嵌埋半導體元件之刼祐受曰的係扣供 度。 件之封裝基板及其製法，能提高佈線密 ϋ姑宜纟月之主要目的係提供—種嵌埋半導體元件之封 β裝基板及其製法，鈐赂你说& 兀件之封 為達上層結構的層數，並簡化裳程。 2 ^的，本發明揭露一種嵌埋半導體元件之封 裝基板，係包括：其^ 士 午之封 a , , ^ ^ 基板本體，係具有至少-開口，·半導體 :片係固&於該開口中，且具 = 用面，於該作用面上設有複數電極塾；第一:::及作 於該基板本體及半導體B 电曰，係设 具有複數第—二片之作用面上’該第-介電層上 孔並封；Φ π及與其連通之第一開槽’且該4b第一門 孔亚對應路出各該電極塾；以及第—線路層，係設:該= 110884 7 201007900 一「刊倌τ，並於該第一開孔中設有第一導電盲孔 ' 从霉性 連接該些電極墊，其中’該第一導電盲孔直接作為電性連 . 接墊，以令該第一線路層之線路直接電性連接該第—導恭 盲孔。 一 依上述之嵌埋半導體元件之封裝基板，復包括有結合 材料，係設於該基板本體之開口與該半導體晶片之間的間 隙中，以將§亥半導體晶片固定於該基板本體之開口中j其 中，遠結合材料與第一介電層係為相同或不同材料丨該第 ©一線路層之線路之寬度係小於或等於該第一導電盲=之 々依上所述，復包括增層結構，係設於該第一介電層及 =、=層，，該增層結構係包括至少一具有第二開;。及 *汗g之第一介電層、設於該第二介電層之第二開槽中 之第二線路層、以及複數設於該第二曰 並電性連接該第'線路第-開孔中 峪層及第一線路層之第二導電盲 路層之料之寬度料於或#於該第二導電 結構之最外層線路復具有複數電性接 中呈有：：曰 最外層上設有防焊層，且該防焊層 H 開孔，以對應外露各該電性接㈣。 X月復包括一種嵌埋半導體 法，係包括：提供-其卞 <封裝基板之製 開口中固定有半導/曰本體’係具有至少一開口；於該 用面及非作用面， 乃，、有相對應之作 本體及半導體晶片之複數電極塾；於該基板 用面上形成有第一介電層，該第一 110884 8 201007900 形成有複數第—開孔及與其連通之第 該第-開孔並對應露出各該 〜且 ·形成有第-線路層，並於該歧第==弟-開槽中 -目孔’以對應電性連接各該電極墊，其中，該第一導：； 性連接該第一導電盲孔。 *、，泉路層之線路直接電 嵌埋半導1^件之封裝基板之製法，復包括 方、忒基板本體之開口與該半導 U有結合材料，以將該半導體θ Β γ中形成 0該結合材料與第一介於該開”’其中， %層係為相同或不同材料。 第-：m:第一線路層之製法’係包括:於該 "电禮弟—開孔之孔卷、笙__扣^ , L ^ ^ ^ ^ 土弟一開槽之侧壁及電極墊 =Γ=;㈣導電層上電鏟形成有金屬層，並 形::1成該第—導電盲孔’且於該第一開槽中 、，路層，以及移除未形成該第一線路層之全 屬層及導電層。 冰将！心金 響1笛依上所述’δ亥第一線路層之線路之寬度係小於或等於 该弟一導電盲孔之直徑。 =依上所述，復包括於該第一介電層及第—線路層上 :有增層結構，該增層結構係包括至少一具有第二開孔 =一開槽之第二介電層、形成於該第二介電層之第二開 s的第二線路層'以及複數形成於該第二介電層之第二 :孔中並電性連接該第一線路層及第二線路層之第二導 电盲孔，4第二線路層之線路之寬度係小於或等於該第二 9 110884 201007900 .導電盲孔之直徑，·該增層結構之最外層線路上^ •性接觸墊，又於該增層結構之最外層上带 设形成有電 ，該防焊層中形成有複數防焊層開焊層’且 _觸墊。 x對應外露該電性接 本發明之嵌埋半導體元件之封裝基板及复 係於第-介電層及第二介電層中分別形成有第二後要 及第二線路層，使該第-線路層之線 =路層 於該第-導電盲孔之直徑，且使該第二線:::: =等 ❹度係小於或等於該第二導電盲孔之直徑，而 俾能增加佈線密度，以降低增層結構的層數： 【實施方式】 一以下藉由特定的具體實施例說明本發明之电 式，熟悉此技藝之人士可由本％ ^方 瞭解本發明之其他優點及功Γ所揭^内容輕易地 參丰參Γ第2A圖至第2G圖’係提供本發明之—種嵌埋 +導體兀件之封裝基板之製法。 里 20 圖所示’提供一具有開口 2〇°之基板本體 20’於該開口 200中容置有半導體晶片2 _與半導體晶片21的間隙中填入有結合材料22:: 4半V胆日日片21固定於該基板本體2〇之開口 2〇〇中， 半‘體a日片21具有相對應之作用面21a &非作用= 21b於該作用面21a具有複數矩陣排列之電極塾Mi， 其中，忒基板本體20係可為絕緣板、金屬板或電路板等 110884 10 201007900 •其中之一者’該開口 2GG係可貫穿或未貫穿該基板本體 20 ° • 如第2B圖所示，於該基板本體2〇、半導體晶月21 . 之作用面21a上形成有第一介電層23a。 如第2C圖所示，於該第一介電層23a中形成有複數 第一開孔231a及與其連通之第一開槽232a，且該些第一 開孔231a並對應露出各該電極墊211，該第一開槽232a 或第一開孔231a係以電漿、反應式離子蝕刻或雷射加工 ❹而成。 如第2D圖所示，於該第一介電層23a、第一開孔231a 之孔壁、第一開槽232a之侧壁及電極墊211上形成導電 層24 ;該導電層24係利用物理氣相沈積（PVD)、化學氣 相沈積（CVD)、無電電鐘（eiectr〇iess piating)或化學沈 積（chemical deposition)方式形成，例如濺鍍 (Sputtering)、蒸鍍（Evaporation)、電弧蒸氣沈積（Arc ❹ apor deposition)、離子束減鍍（i〇n beam puttering)、雷射熔散沈積（Laser abiati〇n deposition) 或電衆促進之化學氣相沈積’該導電層24係為銅、錫、 錄、鉻、鈦、銅—鉻合金及錫_鉛合金所組成之群組之至少 一者所製成者。 如第2E圖所示，於該導電層24上電鍍形成有金屬層 25 ’並於該第一開孔231a中形成有第一導電盲孔261a， 且於該第一開槽232a中形成有第一線路層26a，以對應 電性連接各該電極墊211，其中，該第一導電盲孔261a 11 110884 201007900 ，直接作為電性連接墊。 如第2F、2F，及2F，，圖所+ ^ .芦之全;道 移除未形成該第一線路 .層“3之金屬層25及導電層24 .線路262a直接電性連接哕第 5X 、泉路層26a之 壤该弟一導電盲孔261a，並位於嗲 第一導電盲孔261a上，且兮筮. 位於该 且该弟一線路層26a之線敗9R9q 的寬度係小於或等於該第一導 ''' 2a _ 等電盲孔2 61 a之直徑.蚀贫 第一線路層26a嵌埋於第—介 杈，使該 ^ ;丨包層23a中，且該第一塞帝 我：=61?無習知之電性連接塾，俾以增加佈線空間a ❹使該些矩陣排列之電極塾211電性連接各該第—導電盲 孔261 a及線路262a ’相較於習知社摄 板之矩陣排列内部之電極墊2n ^ ± a之封裝基 a p, ± 电位墊211於電性連接之線路向外 展開％，具有較多之空間， 乐綠路層26a可將矩陣 排列並位於内圈之半導體s η 91 ^ 千等體曰曰片21之電極墊211向外展 開，進而能減少後續增層的層數。 如第2G圖所示，於該第一介電層如及第一線路層 ❹a上形成有增層結構27，該增層結構27係包括至少一 具有第二開孔231b及第二開槽_之第三介電層挪、 設於該第二介電層23b之第二開槽2咖中之第二線路層 挪、以及複數設於該第二介㈣现之第二開孔襲 中並電性連接該第—線路層26a及第二線路層_之第二 導電盲孔261b，該增層結構27之最外層線路復形成有電 性接觸墊274及防焊層28，且該防焊屬28中形成有複數 防焊層開孔280’以對應外露各該電性接觸墊274;其中， 該第二線路層26b之線路之寬度係小於或等於該第二導 110884 12 201007900 电目札厶61 b之直；，古方铱_ 。Λ k /u 弟一開枱232b或第二開孔23ib 係以電漿、反應式離子姓 ，爲一道㊉而成’該第二線路 層 2 6 b、弟-一 ^電言：?| _v、 ‘丁、 261b或電性接觸塾274係以電鍍 万式形成。 括.露—種嵌埋半導體元件之封裝基板，係包 枯.基板本體20，俾且右5 /卜«Η Λ 你具有至少一開口 2〇〇 ;半導體晶 21 ’係固.定於該開口 2 〇 〇 φ，θ目士』 ZOO中，且具有相對應之作用面21a 及非作用面21b，於該作用面21a上設有複數電極塾⑴； ❹第一介電層23a ’係設於該基板本體2〇及半導體曰片u 之作用面⑴上’該第—介電層-具有複數第：開孔 23la及與其連通之第一開槽灿，且該些第—開孔⑽ 並對應露出各該電極塾211 ;以及第一線路層心，係設 於該第一開槽232a中，並於該第一開孔23la中設有第一 導電盲孔261a，以電性連接各該電極墊211，其中，該第 一導電盲孔261a直接作為電性連接墊，以令該第一線路 層26a之線路262a直接電性連接該第一導電盲孔26la， ❿並位於該第一導電盲孔261a上。 依上述之嵌埋半導體元件之封裝基板，復包括有結合 材料22 ’係設於該基板本體2〇之開口 2〇〇與該半導體晶 片21之間的間隙中，以將該半導體晶片21固定於該基板 本體20之開口 200中，其中，該結合材料22與第一介電 層23a係為相同或不同材料。 依上述之結構’ έ亥第—線路層2 6 a之線路£ 6 2 a的寬 度係小於或等於該第一導電盲孔26丨a之直徑。 110884 13 201007900 ’ 依上所述，復包括增層結構27，係形成於該第—八 電層23a及第一線路層26a上，該增層結構27係包括^ 少一具有第二開孔231b及第二開槽232b之第二介電層 .2此、設於該第二介電層23b之第二開槽232b中之第二線 路層26b、以及複數設於該第二介電層2扑之第二開 231b中並電性連接該第一線路層26a及第二線路讣 之第二導電盲孔261b;該增層結構27之最外層線路具 電性接觸墊274及防焊層28’且該防焊層28中具有防 ❹層開孔290 ’以對應外露該電性接觸塾274。 依上述之結構，該第二線路層26b之線路之寬度係 於或等於該第二導電盲孔261b之直徑。 ,本發明之嵌埋半導體元件之封裝基板及其製法，主要 係於第-介電層及第二介電層中分別形成有第—線路層 及第二線路層，使該第一線路層之線路的寬度係小於或等 於該第一導電盲孔之直徑，且使該第二線路層之線路的寬 ^係小於或等於該第二導電盲孔之直徑，俾能增加佈線密 又，使该第一線路層嵌埋於第一介電層中，且第一導電盲 孔並無習知之電性連接墊，俾以增加佈線空間，使該些矩 陣排列之電極墊電性連接各該第一導電盲孔及線路，因此 第-線路層可將矩陣排列並位於内圈之半導體晶片的電 極墊向外展開’進而能減少後續增層的層數，並簡化製程。 上述實施例係用以例示性說明本發明之原理及其功 效’而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及㈣下，對上述實施例進行修 110884 14 201007900 應如後述之申請專利範 改。因此本發明之桓利保護犯圍 圍所列。 【圖式簡單説明】 元件之封裝基板 第1A至1F圖係為習知之喪埋半導體 及其製法的剖視示意圖； 第1E’圖係為第1E圖之上視圖； 第1E”圖係為第1E圖之局部立體剖視圖； 第2A至2G圖係為本發明之嵌埋半導體元件 ©板及其製法之剖視示意圖； 寸裝土 第2F’圖係為第2F圖之上視圖；以及 第2F”圖係為第2F圖之局部立體剖視圖。 【主要元件符號說明】 基板本體 1〇〇 、 200 開口 11、21 12、22 11 a、21 a 11b、21b Π1 ' 211 13 ' 23a 130 、 231a 232a 14 ' 24 25 半導體晶片 結合材料 作用面 非作用面 電極墊 第一介電層 第一開孔 第一開槽 導電層 金屬層 110884 15 201007900 15 阻層 150 開口區 Γ 16' 26a 第一線路層 .161 電性連接墊 17 、 261a 第一導電盲孔 162 、 262a 線路 18、27 增層結構 231b 第二開孔 © 232b 第二開槽 181 ' 23b 第二介電層 183 、 26b 第二線路層 182 、 261b 第二導電盲孔 184 、 274 電性接觸墊 19、28 防焊層 190 、 280 防焊層開孔 L 電性連接墊之間距 ❿D 電性連接墊之直徑 SI 線寬 S2 線距 16 110884The resist layer 15 and the conductive layer 14 overlying the layer are removed to expose the first wiring layer 16; as formed on the first F dielectric layer 13 and the first wiring layer 16, as shown in FIG. The second layer 183 of the build-up structure 1δ includes at least one second dielectric layer, the second circuit layer 183 on the second dielectric layer 181, and a plurality of layers formed on the second dielectric layer 16, 183 The first-conductivity-connected green and ρ 82 of the first and second lines, the outermost layer of the layered structure 18 is the outermost electrical contact pad 184, and the number of the layered structure is prevented from being "opening 19Q 19? The solder layer 19 is formed with a complex = corresponding to expose each of the electrical contact pads 184. As can be seen, the first circuit layer j 6 is electrically connected to the inner matrix of the first conductive connection pad (6) and is arranged on the line 162 of the electric connection pad 161. However, the electrical connection pad 161 occupies a large back connection space, so that the electrical connection pads 161 are wounded by the current advanced process, the electrical connection 61 61 = smaller, such as 1 The spacing is 1^130/^, 110884 6 201007900 The straightforward transport 塾161 is 1)=70"111, line width (51)/line spacing (^2) is 20 # m /20 // m ' It is only barely passed through a line a?, but it is difficult to cloth, and the circuit is 1 62, so that the matrix is arranged and located at the (4) electrical connection 161, the line 162 cannot be re-extracted in the same layer, so that the inner ring is located. The electrical connection 塾161 must be further layered up and led out by stacking holes (10). This leads to an increase in the number of circuit build-up layers, thus increasing the problem of process slaveness and difficulty in alignment between layers. Widespread from the above-mentioned question 'how to avoid the shortage of wiring work in the circuit layer in the conventional technology' Problems such as difficulty in alignment and multi-layer alignment have become the subject of the following:: The problem to be solved. Only the purpose of the invention is [invention] In view of the above-mentioned lack of the prior art, an embedded semiconductor component of the present invention The packaged substrate of the 曰 曰 。 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件 件It is said that the seal of the upper part is the number of layers of the upper structure, and the process is simplified. 2 ^, the present invention discloses a package substrate embedded with a semiconductor component, which comprises: a seal of a noon, a , ^ ^ The substrate body has at least an opening, a semiconductor: a sheet is fixed in the opening, and has a surface, and a plurality of electrodes are disposed on the active surface; first::: and the substrate body And the semiconductor B electromotive device is provided with a plurality of first and second plates on the active surface of the first dielectric layer and sealed; Φ π and a first slot connected thereto and the 4b first gate hole sub-correspondence Each of the electrodes is removed; and the first circuit layer is provided with: 11088 4 7 201007900 A "publication τ, and a first conductive blind hole in the first opening" is connected to the electrode pads from the mold, wherein the first conductive blind hole is directly used as an electrical connection. The first circuit layer is directly electrically connected to the first conductive hole. The package substrate embedded with the semiconductor component includes a bonding material disposed on the opening of the substrate body and the substrate In the gap between the semiconductor wafers, the semiconductor wafer is fixed in the opening of the substrate body, wherein the far bonding material and the first dielectric layer are the same or different materials, and the circuit of the first circuit layer Width system is less than or equal to the first conductive blind== according to the above, the complex includes a build-up structure, is disposed on the first dielectric layer and the =, = layer, and the build-up structure includes at least one Second open; And a first dielectric layer of the second sweat layer, a second circuit layer disposed in the second slot of the second dielectric layer, and a plurality of the second dielectric layer disposed on the second ground and electrically connected to the first line The width of the material in the hole and the second conductive blind layer of the first circuit layer is or is in the outermost circuit of the second conductive structure, and has a plurality of electrical connections: There is a solder resist layer, and the solder resist layer H is opened to correspondingly expose each of the electrical contacts (4). The X-ray includes an embedded semiconductor method, comprising: providing - a 半 卞 密封 密封 密封 密封 密封 密封 密封 密封 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定 固定Correspondingly, a plurality of electrodes are formed on the body and the semiconductor wafer; a first dielectric layer is formed on the surface of the substrate, and the first 110884 8 201007900 is formed with a plurality of first openings and the first phase connected thereto Opening the holes and correspondingly exposing each of the layers to form a first-line layer, and in the ambiguity ==-------------------------------------------- ; sexually connecting the first conductive blind hole. *,, the circuit of the spring road layer directly embeds the semiconductor substrate of the semi-conductor 1^, the composite substrate and the opening of the substrate body and the semi-conductive U have a bonding material to form the semiconductor θ Β γ 0 The bonding material is the same as or different from the first layer in the "", the % layer is the same or different material. The -:m: the first circuit layer manufacturing method includes: in the " electric court brother - opening Hole roll, 笙__扣^, L ^ ^ ^ ^ The side wall of the slotted hole and the electrode pad = Γ =; (4) The shovel on the conductive layer is formed with a metal layer, and the shape:: 1 into the first - conductive Blind hole 'and in the first slot, the road layer, and remove the entire genus layer and the conductive layer that does not form the first circuit layer. Ice will! Heart Jinsheng 1 flute on the said 'δ海第The width of the line of a circuit layer is less than or equal to the diameter of the conductive hole of the younger one. According to the above, it is included on the first dielectric layer and the first circuit layer: a buildup structure, the buildup layer The structure includes at least one second dielectric layer having a second opening = a slot, a second wiring layer formed on the second opening s of the second dielectric layer, and a plurality formed thereon The second dielectric layer is electrically connected to the second conductive blind via of the first circuit layer and the second circuit layer, and the width of the line of the second circuit layer is less than or equal to the second 9 110884 201007900. The diameter of the conductive blind hole, the contact pad on the outermost layer of the build-up structure, and the electric layer formed on the outermost layer of the build-up structure, the plurality of solder resists are formed in the solder resist layer a layer of open solder layer 'and a contact pad. x corresponding to the exposed package substrate of the embedded semiconductor device of the present invention and a second layer formed in the first dielectric layer and the second dielectric layer respectively And the second circuit layer, the line of the first circuit layer = the road layer is at the diameter of the first conductive hole, and the second line:::: = is less than or equal to the second conductive blind The diameter of the hole, and the 俾 can increase the wiring density to reduce the number of layers of the build-up structure: [Embodiment] Hereinafter, the electric form of the present invention will be described by a specific embodiment, and those skilled in the art can Understanding the other advantages and merits of the present invention is easy to participate in the 2A to 2G A method for manufacturing a package substrate of a buried/conductor element of the present invention is provided. In the figure 20, a substrate body 20 having an opening of 2 〇 is provided in which a semiconductor wafer 2 is accommodated. The gap between the semiconductor wafer 21 and the semiconductor wafer 21 is filled with a bonding material 22: 4 semi-V bipolar day 21 is fixed in the opening 2 of the substrate body 2, and the half-body a 21 has a corresponding action surface. 21a & inactive = 21b having an array of electrodes 塾Mi on the active surface 21a, wherein the 忒 substrate body 20 can be an insulating plate, a metal plate or a circuit board, etc. 110884 10 201007900 • One of the openings The 2GG system may or may not penetrate the substrate body 20°. As shown in FIG. 2B, the first dielectric layer 23a is formed on the active surface 21a of the substrate body 2 and the semiconductor crystal 21 . As shown in FIG. 2C, a plurality of first openings 231a and first slots 232a communicating therewith are formed in the first dielectric layer 23a, and the first openings 231a are correspondingly exposed to the electrode pads 211. The first slot 232a or the first opening 231a is formed by plasma, reactive ion etching or laser processing. As shown in FIG. 2D, a conductive layer 24 is formed on the first dielectric layer 23a, the hole wall of the first opening 231a, the sidewall of the first opening 232a, and the electrode pad 211; the conductive layer 24 utilizes physics. Formed by vapor deposition (PVD), chemical vapor deposition (CVD), electro-electric clock (eiectr〇iess piating) or chemical deposition, such as sputtering, evaporation, arc vapor deposition (Arc ❹ apor deposition), ion beam deplating, laser abiati〇n deposition, or electron-assisted chemical vapor deposition. The conductive layer 24 is made of copper or tin. Manufactured from at least one of the group consisting of chrome, titanium, copper-chromium alloy and tin-lead alloy. As shown in FIG. 2E, a metal layer 25' is formed on the conductive layer 24, and a first conductive via hole 261a is formed in the first opening 231a, and a first conductive via 261a is formed in the first opening 232a. A circuit layer 26a is electrically connected to each of the electrode pads 211, wherein the first conductive blind holes 261a 11 110884 201007900 directly serve as electrical connection pads. For example, 2F, 2F, and 2F, the figure is + ^. The whole of the road; the removal of the first line does not form the first line. Layer 3 of the metal layer 25 and the conductive layer 24. The line 262a is directly electrically connected to the 5X The spring road layer 26a is a conductive blind hole 261a, and is located on the first conductive blind hole 261a, and the width of the line 9R9q located in the circuit layer 26a is less than or equal to The first guide ''' 2a _ isoelectric blind hole 2 61 a diameter. The first line layer 26a is embedded in the first layer, so that the ^; cladding layer 23a, and the first Sai Di :=61? There is no known electrical connection 塾, 俾 to increase the wiring space a ❹ such that the array of electrodes 211 electrically connected to each of the first conductive blind holes 261 a and the line 262a ' compared to the custom The matrix of the camera is arranged inside the electrode pad 2n ^ ± a package base ap, the potential pad 211 is expanded outward in the electrically connected line, and has more space. The Le Green road layer 26a can arrange and locate the matrix. The inner ring of the semiconductor s η 91 ^ the electrode pad 211 of the slab 21 is flared outward, thereby reducing the number of layers of subsequent buildup. As shown in Fig. 2G, The first dielectric layer and the first circuit layer ❹a are formed with a build-up structure 27, and the build-up structure 27 includes at least one third dielectric layer having a second opening 231b and a second slot. a second circuit layer disposed in the second slot 2 of the second dielectric layer 23b, and a plurality of second openings formed in the second dielectric layer and electrically connected to the first circuit layer 26a and the second circuit layer _ the second conductive blind hole 261b, the outermost layer of the build-up structure 27 is formed with an electrical contact pad 274 and a solder resist layer 28, and the solder resist 28 is formed with a plurality of solder resists a layer opening 280 ′ to correspondingly expose each of the electrical contact pads 274 ; wherein the width of the second circuit layer 26 b is less than or equal to the second guide 110884 12 201007900 electric Sapporo 61 b straight;铱 _ 。 / k / u brother opened 232b or the second opening 23ib is made of plasma, reactive ion name, for a decade to make 'the second circuit layer 2 6 b, brother - one ^ electric words: ?_ _v, 'Ding, 261b or electrical contact 塾 274 is formed by electroplating. The package substrate of embedded semiconductor components is packaged. The body 20, 俾 and right 5 / Bu «Η Λ You have at least one opening 2 〇〇; the semiconductor crystal 21 ' is solid. It is set in the opening 2 〇〇 φ, θ 目 』 ZOO, and has a corresponding role The surface 21a and the non-active surface 21b are provided with a plurality of electrode electrodes (1) on the active surface 21a; and the first dielectric layer 23a' is disposed on the substrate (2) of the substrate body 2 and the semiconductor wafer u. a dielectric layer having a plurality of openings: 23a and a first slot connected thereto, and wherein the first openings (10) correspondingly expose the electrodes 211; and the first layer core is disposed a first conductive via 261a is disposed in the first opening 232a, and the first conductive via 261a is electrically connected to the electrode pad 211. The first conductive via 261a directly serves as an electrical connection pad. The line 262a of the first circuit layer 26a is directly electrically connected to the first conductive blind hole 26la, and is disposed on the first conductive blind hole 261a. The package substrate in which the semiconductor device is embedded is further provided with a bonding material 22' disposed in a gap between the opening 2 of the substrate body 2 and the semiconductor wafer 21 to fix the semiconductor wafer 21 to the semiconductor wafer 21 In the opening 200 of the substrate body 20, the bonding material 22 and the first dielectric layer 23a are the same or different materials. According to the above structure, the width of the circuit of the circuit layer 2 6 a is less than or equal to the diameter of the first conductive blind hole 26丨a. 110884 13 201007900 ' As described above, the multi-layer structure 27 is formed on the first-eighth electrical layer 23a and the first circuit layer 26a, and the build-up structure 27 includes a second opening 231b. And a second dielectric layer 26b disposed in the second trench 232b of the second dielectric layer 23b, and a plurality of second dielectric layers 2b disposed in the second dielectric layer 23b The second opening 231b is electrically connected to the first circuit layer 26a and the second conductive blind hole 261b of the second circuit; the outermost circuit of the layered structure 27 has an electrical contact pad 274 and a solder resist layer 28. 'The solder resist layer 28 has a tamper-resistant layer opening 290' to correspondingly expose the electrical contact 塾274. According to the above structure, the width of the line of the second wiring layer 26b is equal to or equal to the diameter of the second conductive blind via 261b. The package substrate for embedding a semiconductor device of the present invention, and the method for fabricating the same, mainly for forming a first circuit layer and a second circuit layer in the first dielectric layer and the second dielectric layer, respectively, so that the first circuit layer The width of the line is less than or equal to the diameter of the first conductive blind hole, and the width of the line of the second circuit layer is less than or equal to the diameter of the second conductive blind hole, and the wiring can be increased. The first circuit layer is embedded in the first dielectric layer, and the first conductive blind hole has no conventional electrical connection pads, so as to increase the wiring space, and the electrode pads of the matrix arrays are electrically connected to the first Conductive blind vias and traces, so the first-line layer can be arranged in a matrix and the electrode pads of the semiconductor wafer located on the inner ring are expanded outwards, thereby reducing the number of layers of subsequent build-up layers and simplifying the process. The above-described embodiments are intended to illustrate the principles of the invention and its functions, and are not intended to limit the invention. Anyone skilled in the art can apply the above-mentioned embodiments to repair the above-mentioned embodiments without departing from the spirit of the invention and (4). Therefore, the patent protection of the present invention is listed. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to 1F of a package substrate of a device are schematic cross-sectional views of a conventional buried semiconductor and a method for manufacturing the same; FIG. 1E' is a top view of FIG. 1E; 1A to 2G is a cross-sectional view showing the embedded semiconductor device © of the present invention and a method for manufacturing the same; the 2F' of the inch soil is a top view of the 2F; and 2F The figure is a partial perspective cross-sectional view of FIG. 2F. [Description of main component symbols] Substrate body 1〇〇, 200 openings 11, 21 12, 22 11 a, 21 a 11b, 21b Π 1 ' 211 13 ' 23a 130 , 231a 232a 14 ' 24 25 The surface of the semiconductor wafer bonding material is not functional Surface electrode pad first dielectric layer first opening first slotted conductive layer metal layer 110884 15 201007900 15 resist layer 150 open area Γ 16' 26a first line layer. 161 electrical connection pads 17 , 261a first conductive blind Holes 162, 262a Lines 18, 27 Additive structure 231b Second opening © 232b Second slot 181 '23b Second dielectric layer 183, 26b Second circuit layer 182, 261b Second conductive blind hole 184, 274 Electrical Contact pad 19, 28 solder mask 190, 280 solder mask opening L between electrical pads 直径D electrical connection pad diameter SI line width S2 line spacing 16 110884