TW201005894A - Pillar-to-pillar flip-chip assembly - Google Patents

Abstract

Disclosed is a pillar-to-pillar flip-chip assembly, primarily comprising a substrate, a chip on the substrate, a plurality of first copper pillars, a plurality of second copper pillars, and solder material. The first copper pillars are disposed on a plurality of bonding pads on an active surface of the chip. The second copper pillars are disposed on a plurality of connecting pads on the substrate and have a height approximately equal to the first copper pillars. When the solder material bonds the first copper pillars with the second copper pillars, the central points of the solder material are located at an equipartition plane of the gap between the chip and the substrate. Accordingly, the stress effect directly forced at the solder material can be reduced to avoid crack at soldering points. This configuration also can accord with the demands of lead-free soldering and high reliability by replacing solder balls and reducing Sn/Pb consumption.

Description

201005894 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device, and more particularly to a column-to-column flip chip structure. [Prior Art] Flip-chip bonding technology is to form a plurality of conductive bumps (or called protruding electrodes) on a pad of an active surface of a wafer to be bonded to a substrate by wafer flipping. Electrical connection. Compared with the electrical connection method using a wire bond, since the flip chip packaging technology provides a short electrical connection path between the wafer and the substrate, the integrated circuit of the higher operating frequency in the wafer can be made good. The transmission quality of high frequency signals. Therefore, flip chip bonding is an inevitable trend in advanced semiconductor devices, providing faster processing speeds and higher performance. However, after the conductive bumps are bonded, the wafer and the substrate are bonded in a point-to-point local connection. Once the bump is broken due to stress, the electrical signal transmission between the wafer and the substrate fails. At present, there are two types of bumps, tin-lead bumps and gold bumps. The tin-lead bumps do not meet the European ship-free requirements of RoHS. The gold bumps are too expensive. If the tin bump is directly replaced by the bump-free bump, there is a problem that the reliability is lowered. In addition, the tin-lead bumps need to be heated and reflowed into a spherical shape, and have no gap maintenance function at high temperatures. The gold bumps are bonded by a thermocompression to the bumps, and the bumps are deformed under high temperature pressing, and the gap is not maintained. Therefore, in the flip-chip bonding technology, neither the tin-lead bump nor the gold bump can effectively control the gap between the wafer and the substrate during the flip-chip bonding, and often along with the temperature of the process parameters. Or the change of pressure will produce a laminating gap with inconsistent control, which will affect the quality of the seal. As disclosed in U.S. Patent No. 6,229,220, the ibm company teaches a conventional flip-chip bonding structure to control a uniform flip-chip gap, and Fig. 1 is a schematic cross-sectional view of the flip-chip structure before flipping.覆 The flip chip structure mainly comprises a substrate 110, a wafer 12 〇 and a plurality of copper pillars 130. The substrate 110 is a wafer carrier and has an upper surface 111 and a corresponding lower surface 11 which is formed with a plurality of connection pads 114. The wafer 120 is formed by flip chip bonding on the upper surface 111 of the substrate 110. One of the active surfaces 121 of the wafer 120 is provided with a plurality of pads 122. The copper pillars 130 are disposed on the fresh crucibles 122 for controlling the flip chip gap. A solder material 150 is pre-formed at the top of each copper post. The connection pads 114 of the copper pillars 130 and the substrate 11 are electrically connected via the solder material 15 and then connected to the external electronic device through conductive traces inside the substrate 11 . As shown in Fig. 2, the solder material 15 is bonded to the copper pads 13 and the connection pads 114 after reflowing. The height of the copper pillars 130 is greater than the height of the connection pads 114. The connection pads 114 are directly exposed on the upper surface 111 of the substrate 11'. The solder material 15 is on the copper pillars 13 and Each of the soldering center points 丨51 between the connecting pads 11 4 is oppositely offset from the bisector separating surface p of the gap Hi between the wafer 1 2 〇 and the substrate 110, and the solder material 1 50 Closer to the substrate 丨i. As shown in FIG. 3, in the above conventional flip chip structure, when the substrate 1 1 0 201005894 generates warpage or thermal expansion and contraction, the connection ports 114 are compared with the copper columns 130. It is easy to bear the large thermal stress and it is easy to break or smash at the welding interface, which causes the failure of the signal transmission, which affects the reliability of the product. SUMMARY OF THE INVENTION In view of this, the main object of the present invention is to provide a column-to-column flip-chip structure, which can slow the difference between the substrate and the wafer warpage or the thermal expansion and contraction of the substrate to the solder material and the substrate connection pad. Stress action to avoid ® solder joint breakage. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a column-to-column flip-chip structure mainly comprises a substrate, a wafer, a plurality of first copper pillars, a plurality of second copper pillars, and a solder material. The substrate has an upper surface and a lower surface, the upper surface being provided with a solder resist layer and a plurality of connecting pads. The connecting pads are exposed outside the solder resist layer. The wafer is φ on the upper surface of the substrate, and one of the active faces of the wafer is provided with a plurality of pads. The first copper pillars are disposed on the pads. The second copper pillars are disposed on the connecting pads. The solder material is connected to the first copper pillars and the second copper pillars, wherein the first copper pillars are approximately equal to the second copper pillars so that the soldering center of the solder material is located on the wafer An equally spaced surface of the gap with the substrate. The object of the present invention and solving the technical problems thereof can be further realized by the following technical measures. In the column-to-column flip-chip structure, the height of the second copper pillars may be not less than one-half of the thickness of the a-half wafer. In the above column-column flip-chip structure, the second copper pillars may be tapered. In the column-column flip-chip structure, the heights of the second copper pillars protruding from the connection pads may be not less than a length or a diameter of the regions where the second copper pillars are disposed on the corresponding junctions. In the column-to-column flip-chip structure, the second copper pillars may not be in contact with the solder resist layer. In the column-to-column flip-chip structure, the wafer system may have a plurality of under bump metal layers formed between the first copper pillars and the pads. In the pillar-to-column flip-chip structure, an underfill may be further included to fill the gap between the wafer and the substrate. In the column-column flip-chip structure, a colloid may be further included to fill the gap between the wafer and the substrate and seal the wafer. • In the column-column flip-chip structure described above, the substrate may be a printed circuit board. In the column-column flip-chip structure, the solder resist layer may have a plurality of openings, the apertures of which are smaller than the connection ports but larger than the length or a diameter of the second columns, so that the solder resist layer The areas where the flails are not covered by the second copper pillars are partially exposed. In the column-column flip-chip structure, the second copper pillars may be pillars. In the column-column flip-chip structure, the second copper pillars may be flat and connected to each other, and the number of copper coils is more than 8 201005894 corner cylinders ^ in the column-to-column flip-chip structure The second copper pillars may have a plurality of wall faces facing a plurality of corners of the connecting pads. It can be seen from the above technical solution that the pillar-to-column flip-chip structure of the present invention has the following advantages and effects: 1. The substrate is provided with a plurality of second copper pillars having the same height as the first steel pillar on the wafer. The welding center point of the solder material is located at an equally spaced surface between the die and the substrate, which can slow the difference between the substrate and the wafer warpage or the thermal expansion and contraction of the substrate to the solder material and the substrate. Stress acts to avoid breakage of the defects. In addition, it can replace solder balls and meet the requirements of lead-free, high reliability and low manufacturing cost. 1. Increasing the gap between the wafer and the substrate by the height of the second copper pillar on the substrate until not less than the thickness of the wafer, so as to increase the maximum withstand stress of the soldering center point between the copper pillars, and contribute to the encapsulant or underfill Fill in the glue. 3. By the solder resist layer corresponding to the opening size of the second copper pillar, so that the solder resist layer partially exposes the region on the substrate where the connection pad is not covered by the second copper pillar, so that the excess solder material can be fixed in the second copper The perimeter of the column prevents the formation of tin beads. 4. The plurality of walls of the second copper pillar on the substrate are oriented toward the plurality of corners of the substrate connection pad to increase the preferred excess solder material adhesion area. 5. Using the second copper pillar on the substrate as a flat taper, the solder material is concentrated on the equally spaced surface of the gap between the wafer and the substrate at 9 201005894 to avoid diffusion contamination of the solder material on the substrate connection pad. [Embodiment]

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The components related to this case, and the components shown are not based on the actual number, shape and size ratio. Some size ratios and other related size ratios have been modified or simplified to provide a clearer description. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated. In accordance with a first embodiment of the present invention, a column-to-column flip-chip structure is illustrated in cross-section of Figure 4. The pillar-to-column structure 2 〇〇 mainly comprises a substrate 210, a wafer 220, a plurality of first copper iridium 230, a plurality of second copper pillars 240, and a solder material 250. The substrate 210 has an upper surface 211 and a lower surface 212, which can be a high-density double-sided conductive multilayer printed circuit board with conductive traces and plated through holes (not shown). )'. The substrate 210 can be a unit arranged in an array within a substrate strip. After the cutting, the substrate 2 10 as in the present embodiment is formed. The upper surface 211 is provided with a solder resist layer 213 and a plurality of connection pads 214. The connection pads 214 are exposed outside the solder resist layer 213. The solder resist layer 213 is commonly known as "Soldermask or Solderresist". The main component of the epoxy resin and the photosensitive resin is mainly applied to the surface of the printed circuit board 10 201005894 to form a covered conductive trace. It is protected from the insulating layer damaged by external moisture and pollutants. The solder resist layer 2 13 can be formed by screen printing, curtain coating, spray coating, roller coating or the like. Specifically, the solder resist layer 2 1 3 may have a plurality of openings 2 1 5 ' to expose the plurality of connection pads 214. As shown in FIG. 4, the wafer 220 is disposed on the upper surface 211 of the substrate 210. One active surface 221 of the wafer 220 is provided with a plurality of pads 222, and the pads 222 are used as The chip 220 signals the medium into which it is output. The wafer 220 is made of a semiconductor material, and the active surface 221 is provided with an integrated circuit component selected from a microcontroller, a microprocessor, a memory, a logic circuit, a special application integrated circuit (such as a display driving circuit), and the like. Or a combination of the above. Specifically, as shown in FIG. 6, the wafer 220 may have a plurality of under bump metallurgy layers (UBM layers) 223 formed on the first copper pillars 230 and the solders. Between the pads 222, the under bump metal layers 223 can be formed by sputtering, and are usually composed of three layers of conductive metal layers (not shown), that is, an adhesive layer and a wet layer. (wetting layer) and an oxidation barrier layer for enhancing the connection between the first copper pillars 230 and the pads 222. The active surface 22 of the wafer 220 may further cover an electrically insulating passivation layer 224. The protective layer 224 substantially covers the active surface 221 but exposes the pads 222 to provide protection to the active surface. The integrated circuit component on 221 and the active surface 221 are relatively flat 11 201005894. The under bump metal layer 223 is bonded to the surface of the peripheral portion of the opening of the protective layer 224.

As shown in Fig. 4, the first copper posts 230 are disposed on the pad 222. The second copper pillars 240 are disposed on the connections f. The above copper column refers to a pure copper column, a copper alloy column or a highly rigid conductive column harder than gold. As shown in FIG. 5, the heights H3 of the second pads 240 protruding from the connection pads 214 may be not less than a diameter D' of the second copper pillar 240 disposed on the corresponding connection pad 214 to form a specific column. shape. As shown in FIG. 5, in the present embodiment, the aperture or length of the openings 215 of the solder resist layer 213 is smaller than the connection pads 214 but larger than one or a diameter D of the second copper pillars 24 . As shown in FIG. 5, the openings 215 are generally visible; and the second copper pillars 240 are cylindrical, and the length of one of the openings 2丨5 is greater than the diameter D of the second copper pillars 240. Therefore, in a preferred form, the second copper pillars 24 are not in contact with the solder mask layer, so that the solder resist layer 213 partially exposes the connection pads 214 and the second copper pillars 240 are covered. Area 214A. The area 214A of each of the connection pads 214 as shown in FIG. 5 is not covered by the corresponding second copper pillars and is not covered by the solder resist layer 213. The region 214A is fixed with the excess solder material 25 in the first The two copper columns are 24 sides to prevent the generation of tin beads. Therefore, the celestial sheet 220 and the substrate 210 are both provided with raised columns. The first copper posts 23 and the second steel posts 240 are joined by the solder material 250 to mechanically bond them. Detailed and covered with some soldering > 214 degrees large copper column, the degree or the application is slightly length-shaped, shorter one is not shown, 213 is not shown, 240 can be used with the copper and the words, 12 201005894 as the sixth As shown in FIG. 7 , the solder material 25 can be preliminarily disposed at the top end of the first copper pillars 230, and after recrystallization, and then reflowing, the solder material 25 is melted and bonded. The first copper-copper 230 forms an electrical connection and a mechanical bond relationship with the second copper pillars 240 (as shown in FIG. 8). Generally, the solder material 25 can be selected from a lead-free phosphor, preferably a solder material with a tin content of 96.5%_silver 3%_copper 〇, and the highest temperature is about 217 degrees Celsius when the reflow temperature is reached. The wettability of the weld can be produced at 245 degrees Celsius, and the first steel column 230 and the second copper posts 24 must have a melting point higher than the above-mentioned reflow temperature. Moreover, as shown in FIG. 8 , the first copper pillars 23 概 are approximately equal to the first copper pillars 240 such that the soldering center point 25 1 of the solder material 25 位于 is located on the wafer 22 〇 An equally divided surface P of the gap H2 between the substrates 2A. From the arbitrary point of the partitioning surface p to the wafer 22, the shortest distance to the substrate 210 is the same, and when the substrate 21 has a difference in warpage of φ with respect to the wafer 220, the dividing surface The degree of curvature of P is about one-half of the difference in warpage. Therefore, the first copper pillars 230 and the second copper pillars 24 are vertically aligned with each other and have an equal height, and the height is about 30 to 9 〇 μΓη. Because the first copper pillars 230 and the second copper pillars 24A have high rigidity and low cost characteristics, the wafer 220 is stacked on the substrate 210 and can maintain a uniform flip-chip gap Η2, It is about twice the height of the copper column. Preferably, as shown in Fig. 8, the height Η3 of the second copper pillars 24 is not less than one-half of the thickness τ of the wafer 220. By increasing the height of the second copper pillars 24〇 on the substrate 21, the gaps H2 between the wafer 22 and the substrate 2i are not less than the thickness τ of the wafer 22, which can be improved in the copper pillars. The maximum stress that can be withstood between the weld center points 251. As shown in FIG. 9, when the substrate 21 is subjected to thermal stress and warped or has thermal expansion and contraction, the welding center point 25 1 of the bonding material 25 is still located at the aliquot separating surface ρ, which can be slowed down. The substrate 2丨〇 and the crystal

The difference in warpage of the sheet 220 or the thermal expansion and contraction of the substrate 21 affects the direct stress of the soldering center points 251 and the connecting pads 214 to prevent the solder material 250 from breaking at the soldering center point 251. Therefore, the present invention replaces the conventional solder balls, tin-lead bumps or gold bumps with the first copper pillars 23 〇 and the second copper pillars 240 and the solder material 25 等 corresponding to the contours. The problem of changing the flip-chip gap at high temperatures can meet the requirements of lead-free, high reliability and low manufacturing cost. In addition, the first copper pillars 230 and the second copper pillars 24 may be formed by electroplating. As shown in FIG. 4, the first copper pillars 230 and the second copper pillars 240 may have the same size and shape. For example, in the embodiment, the first copper pillars 230 and the first The two steel columns 240 can be cylindrical (as shown in Fig. 5), but can also be a polygonal column of various shapes without limitation. As shown in FIGS. 10A and 1B, the second copper pillars 2 40 may be octagonal cylinders having a plurality of wall surfaces 241 facing a plurality of corners of the connection pads 214. 214B, the plurality of wall surfaces 241 of the second steel column 24b on the substrate 210 face the corners 21 4B of the connection pads 214, so that the transport pads 214 have excessive excess soldering. Material solid 14 201005894 The area. In addition, the second copper posts 240' of the corner-shaped wall faces 241' facing the corners 214B do not have side corners facing the corners 214B of the connecting pads 214. When the second copper pillars 240 are subjected to stress in a certain direction, they are dispersed in the connecting pads 214, and the corners 214B of the connecting pads 214 are not directly pulled to cause peeling. As shown in FIG. 5, the second copper pillars 24 of the first embodiment are cylindrical, and have the same effect. The second copper pillars 240 are curved toward the corners of the connecting pads 214. The wall surface can also prevent the connection pads 214 from being peeled off by the corners. As shown in FIGS. 4 and 8, after the first copper pillars 230 and the second copper pillars 24 are joined by the solder material 250, the wafer 22 can be filled with a high-flow underfill 260. A gap H2' is formed between the substrate and the substrate 21 to fully integrate the wafer 22 and the substrate 2, and protect the gap H2 from moisture and dust. The increase in the height of the second copper pillars 24 on the substrate 210 of the present invention contributes to the control and filling effect of the filling speed of the underfill filler 260. Further, the pillar-to-column flip-chip structure 200 of the present embodiment is a miniaturized semiconductor package structure. As shown in FIG. 4, the pillar-to-column flip-chip structure 200 may further include a plurality of solder balls 27' disposed on the lower surface 212 of the substrate 210 to enable the pillar-on-column loading on the pillars. The structure 22 of the structure 2 is electrically connected to an external printed circuit board (PCB). The pillar-to-column structure 2 is a bare-as-type flip chip package structure (fiip_chip, and may have a type of Bau Grid Array package). 201005894 According to the second embodiment of the present invention For example, another column-to-column flip-chip structure is illustrated in the cross-sectional view of FIG. 5. The column-to-column flip-chip structure 300 mainly includes a substrate 21〇, a wafer 22〇, a plurality of first copper pillars 230, and a plurality of The second copper post 24〇 and a solder material 25〇. P. The same main elements as those of the first embodiment will be labeled with the same symbols, so that they can be understood and have the same functions and can achieve the above-mentioned effects, and will not be described in detail. In this embodiment, the second copper pillars 240 may be flat cones, such as a semi-conical or a pyramidal shape. Each of the second copper pillars 240 has a top surface 342 and a bottom surface 343. The diameter of the top surface 342 is smaller than the diameter of the bottom surface 343, so that the solder material 250 can be concentrated to the aliquot separating surface p of the gap H2 between the wafer 220 and the substrate 210 to prevent the solder material 250 from being The connection pads 214 of the substrate 210 Diffusion contamination, so that the amount of the solder material 250 can be controlled, and the first copper pillar 230 and the two copper pillars 240 of the flat cone are used to concentrate the solder material φ material 250 on the aliquot separating surface P'. The solder material 250 does not diffuse onto the connection 214 and contaminates the upper surface 211 of the substrate 210. In addition, the pillar-to-column structure 300 may further comprise a colloid 3 80 'filled a gap H2 between the wafer 220 and the substrate 210 and sealing the wafer 220, the first copper pillars 230 and the second copper pillars 240. Since the gap H2 between the wafer 220 and the substrate 210 is compared with the conventional one The gap is large, which can increase the maximum withstand stress of the welding center points 25 1 between the copper pillars, and contribute to the void-free filling of the sealant 380. The above is only the invention of the road. The preferred embodiment of the present invention is in addition to the Jjp 任何 in any form, and the technical scope of the present invention is subject to the scope of the patent. Anyone skilled in the art can utilize the technical content of the above-mentioned disclosure. Make changes or modifications to equivalent changes, etc. Example, but all without departing from the technical content of the present invention, based on the technical spirit of the present invention, any of the above swash simplified example embodiment taken Ο

The single modification, the equivalent change and the modification are all within the scope of the technical solution of the present invention. ' [Simple description of the drawing] Fig. 1 is a schematic cross-sectional view of a conventional flip-chip structure before flipping. Fig. 2 is a schematic cross-sectional view showing a conventional flip-chip structure after flipping. Fig. 3 is a cross-sectional view showing the warpage of the substrate after the flip chip is crystallized. Fig. 4 is a schematic cross-sectional view showing a column-to-column laminated structure according to a first embodiment of the present invention. Fig. 5 is an enlarged perspective view showing the second copper pillar in the pillar-to-column laminated structure according to the first embodiment of the present invention. 6 is a partially enlarged cross-sectional view showing a first copper pillar of a wafer in a column-on-clade structure according to a first embodiment of the present invention. FIG. 7 is a view showing the column pair according to the first embodiment of the present invention. Schematic diagram of the partial wear of the pillared crystal structure before the flip chip. Figure 8: The column-to-column cladding according to the first embodiment of the present invention 17 201005894

FIG. 9 is a partial cross-section after lamination in the structure: according to the first embodiment of the present invention, the substrate warpage is generated after the flip-chip. The first and the tenth are: the other one in the column-on-cladding structure according to the present invention. Larger stereoscopic representations and top views. Figure 11 is a cross-sectional view of a f-section of a second specific pillared crystal structure according to the present invention [Description of main components] Η1 gap between wafer and substrate Η2 gap between wafer and substrate Η3 height of second steel column D second steel column Diameter Ρ equally divided surface 晶片 wafer thickness 110 substrate 111 upper surface 114 connection pad 120 wafer 121 active surface 130 copper column 150 solder material 151 λ 2 point 200 column to column flip chip structure 210 substrate 211 upper surface 213 solder mask Layer 214 connection pad 214 corner 隅 215 opening 220 wafer 221 active face column pair; A partial cross-sectional view of the pillar-to-column junction of the column. Another column pair 112 of the second embodiment of the second embodiment of the second embodiment of the first embodiment of the first embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the second embodiment of the present invention First copper column 240 second copper column 240' second copper column 241 wall surface 250 welding material 251 welding center point 260 bottom filling glue 270 solder ball 3 0 0 column to column flip chip structure 342 top surface 343 bottom surface 380 sealant

19

Claims (1)

201005894, the scope of patent application: a column-to-column flip-chip structure, comprising: a substrate having an upper surface and a lower surface, the surface of the crucible is provided with a solder resist layer and a plurality of connection pads, and the connection pads are Exposed to the solder mask; a wafer is disposed on the upper surface of the substrate, and one of the active surfaces of the wafer is provided with a plurality of pads; a plurality of first copper pillars are disposed on the plurality of solder pads; a plurality of second copper pillars are disposed on the connecting pads; and a soldering material is connected to the first copper pillars and the second copper pillars The first copper pillars are approximately equal to the second copper pillars such that a soldering center point of the solder material is located at an equally spaced surface of the gap between the wafer and the substrate. 2. The column-to-column flip-chip structure according to claim 1, wherein the height of the second copper pillars is not less than one-half of the thickness of the wafer. 3. The column-to-column flip-chip structure as described in claim i, wherein the second copper pillars are flat cones. 4. The column-to-column flip-chip structure according to Item J of the patent application, wherein the height of the second copper pillars protruding from the connection pads is not less than a region where the second copper pillars are disposed on the corresponding connection pads. One length or _ diameter. 5. The column-to-column flip-chip structure of claim i, wherein the second copper pillars are not in contact with the solder resist layer. 6. The column-to-column flip-chip structure according to the invention of claim 2, wherein the wafer has a plurality of under bump metal layers formed on the first 20 201005894 copper pillars and the pads between. 7. A column-to-column flip-chip structure as described in claim 1 of the whistle patent, further comprising an underfill, filling a gap between the wafer and the substrate. 8 The pillar-to-column flip-chip structure according to the above-mentioned patent scope is further comprising a sealant, which fills the gap between the wafer and the substrate and seals the wafer. 9. The column-to-column flip-chip structure according to claim 1, wherein the substrate is a printed circuit board. 10. The column-to-column flip-chip structure according to claim 1, wherein the solder resist layer has a plurality of openings, and the aperture diameter is slightly smaller than the plurality of connection ports but larger than one of the second copper columns. The length or a diameter is such that the solder resist layer partially exposes the areas where the connection pads are not covered by the second copper pillars. The column-to-column flip-chip structure according to claim 1 or claim 1, wherein the second copper pillars are cylindrical. 12. The column-to-column flip-chip structure as described in claim 1 or 10, wherein the second copper pillars are polygonal cylinders. 13. The column-to-column flip-chip structure of claim 12, wherein the second copper pillars have a plurality of wall faces facing a plurality of corners of the connection pads. twenty one