201005893 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種封裝結構及其方法，特別是有關於一種具有基板 支柱之封裝結構及其方法。 【先前技術】 積體電路製造完成以後，還需要與其它元件相連接、散熱，並且需要 外殼加以保護，因此需要加以封裝。積體電路封裝的形式有簡單也有複雜， 且由於極大型積體電路(Ultra Large Scale Integration; ULSI)日趨積集化，因 此封裝的接腳也日漸增多。傳統的封裝是將積體電路之晶粒加以保護，並 提供電源、散熱，且連接至其它元件。現代的封裝則是轉變為使封裝後具 備下一層次組裝之相容性。 因應3C產品輕薄短小的趨勢，覆晶的技術已成為電子封裝技術中非常 重要的一環。而在覆晶的技術中，銲錫凸塊的製造技術攸關著半導體元件 的連接性能。 參考第1A圖至第1C圖，係為習知之録錫凸塊之結構及其製程。如第 1A圖所示’首先在晶圓1〇與保護層2〇之間形成銲墊3〇，並且形成凸塊底 層金屬層(Under Bump Metallurgy; UBM)22於保護層20及銲墊30上。接著， 如第1B圖所示，先形成一光阻層4〇在凸塊底層金屬層22上，且藉由光阻 層40的遮蔽之下，在銲墊3〇上以電鍍法或印刷法形成高鉛銲料5〇。接著， 先將光阻層40和位於其下方的部份凸塊底層金屬層22移除，再進行迴銲 (reflow)步驟’係於溫度約32〇〇c的迴銲溫度下，使銲錫凸塊6〇熔成球形， 如第1C圖所示β 接著，第ID圖至第IF圖，其為習知覆晶(flip chip)封裝之流程示意圖。 參考第1D圖，係將已具有銲錫凸塊60的晶圓10上下倒轉，並於鮮錫凸塊 201005893 60上使用助銲劑。接著，將鋒錫凸塊60覆蓋於基板70之上，如第1E圖所 示。然後’進行迴錄步驟，於溫度約320°C的迴鮮溫度下，使銲錫凸塊6〇 溶化後與基板70相互黏接。接耆，參考第1F圖，由於晶圓1〇與基板7〇 之間的應力差異太大，在接合面，即銲錫凸塊60之間容易發生裂痕，因此 會於各個桿錫凸塊60間填充底膠(under filling material)80，使其應力由全體 之底膠80所承受，因此每一個銲錫凸塊60上作用之應力較小，可提升可 靠度。在此，填膠步驟所使用的底膠80的材質可以是環氧樹脂(ep〇xy)。 然而，由於銲錫凸塊60與凸塊底層金屬層22之間的蝕刻選擇比不佳， 0 因此，相當難以控制凸塊底層金屬層22的蝕刻步驟。另外，在製作高速充 放電元件時，銲錫凸塊60之強度與電容密度的特性均不足以符合需求。另 外，銲錫凸塊60都是形成在晶圓1〇上，或是要進行重工(re_w〇rk)製程，則 要浪費晶圓10，使得製程成本提高。 【發明内容】 蓉於以上關題，本發_主要目的在於提供—種料電柱結獅成 在基板上’使得基板與晶圓結合時，可以自動對準，以增加製程良率。 〇 根據以上之目的’本發明揭露-種封裝結構，包含:提供-基板，具有 -正面及-背面，且於正面上具有第—UBM層；—圖案化之焊塾遮罩層_ mask layer)’形成在第一 ubM層上，且曝露出部份第—層之一表面； 複數個導電柱，形成在已曝露之部份第一麵層上；複數個錫球，形成在 複數個導餘上·，提供-晶圓，具有—正面及，具晶圓之該正面朝 向基板之正面置放；及-圖案化之第二⑽河層，形成在晶圓之正面上其 中部份圖案化之第二UBM層係電性連接於基。 根據上述之雖_ ’本㈣提供—種雜雜，包含:提供一基板， 具有-正面及-背面；形成一第—麵層在基板之正面上；形成一圖案化 201005893 、 之焊墊鮮層在第—顶Μ層上，且曝露出第—顶以層之部份表面；形成 複數個導電柱在已曝露之第-麵層之部份表面；形成複數個錫球在複數 個導電柱上；提供n具有-正面及m成—圖案化之第二麵 層在晶圓之正面上；及結合基板及晶圓，係將晶圓之正面朝向基板之正面 置放，使得晶圓上之部份圖案化之第二刪層與基板上之複數個锡球電性 連接。 本發明又提供-種封裝結構，包含:提供—基板，具有—正面及一背面， 且於正面上具有第-UBM層；-圖案化之焊塾遮罩層，職在第一迎河 Ο 層且曝露出部份第一腦1層之一表面；複數個導電柱，形成在已曝露之部 份第- UBM層之表面上；提供一晶Η，具有一正面及一背面，且晶圓之正 面朝向»之正面置放；-圖案化之第二UBM層，形成在晶圓之正面上； 及複數個錫球，形成在對應於基板之複數個導電柱之位置之圖案化之部份 第一 UBM層上’藉此晶圓上之複數個錫球係電性連接基板上之複數個導電 柱。 根據上述之封裝結構，本發明還揭露一種封裝方法’包含:提供一基板， 具有一正面及一背面；形成一第一 UBM層在基板之正面上；形成一圖案化 _ 之焊墊遮罩層在第一 UBM層上，且曝露出第一顶河層之部份表面；形成 複數個導電柱在已曝露之第一 UBM層之部份表面；形成複數個錫球在複數 個導電柱之上；提供一晶圓，具有一正面及一背面；形成一圖案化之第二 UBM層在晶圓之正面上且曝露出晶圓之部份正面；形成複數個錫球在已曝 露之晶圓之部份正面上，且複數個錫球對應於在基板上之複數個導電枉之 位置，結合基板及晶圓，係將晶圓之正面朝向基板之正面置放，使得晶圓 之部份複數個錫球與基板之複數個導電柱電性連接。 有關本發明的特徵與實作，茲配合圖示作最佳實施例詳細說明如下。 (為使對本發明的目的、構造、特徵、及其功能有進一步的暸解，茲配合 實施例詳細說明如下。） 201005893 【實施方式】 本發明在此雌討财向為—麵裝結構及其封裝方法，紐數個具 有支柱之基板與晶圓結合，然後進行封裝的方法。為了能徹底地瞭解本發 明’將在下列的描述中提麟盡的步驟及其域^ _地，本發明的施行 並未限定晶片封裝的方式之技藝者所熟習的特殊細節。另一方面，眾所周 知的晶片形成方式以及晶片薄料後段製程之詳細步舰未描述於細節 中’以避免造成本發明不必要之限制。然而，對於本發明的較佳實施例， 則會詳細描述如下，然而除了這些詳細描述之外，本發明還可以廣泛地施 Ο 行在其⑽實施财’且本發_不她定，其以之後的專利範圍為 準。 第2A圖至第2B圖係表示在晶圓上形成一圖案化⑽厘層之步驟示意 圖。在第2A圖t，係先提供一晶圓100，其具有一正面及一背面。接著， 在晶圓100上形成一第一 UBM層2〇〇。然後，在第一顶河層2〇〇上形成 -圖案化光阻層(未在圖中表示）；接著，進行顯影及姓刻，以移除部份第一 UBM層20以形成圖案化之第—聰^層2〇1且曝露出晶圓1〇〇之部份正 面，如第2B圖所示。 _ 接著’第2C圖至第21圖係表示在基板上形成導電柱之各步驟示意圖。 首先’提供-基板300，其具有-正面及一背面。在此，基板3〇〇之材料可 以是玻璃、石英、陶究、電路板或金屬薄板。接著，在基板3〇〇之正面上 依序形成一第二UBM層400及一焊墊遮罩層(s〇ider mask kyer)5〇〇，如第 2C圖所示。在此實施例中，焊墊遮罩層5⑽之材料為介電材料(她她 material)，而第一 UBM層2〇〇及第二ubM層4〇〇之材料為Tiw/Ni。接著， 在焊墊遮罩層500上形成一圖案化之光阻層(未在圖中表示）；然後進行顯 影及蝕刻步驟，並且以第二1]^層400為蝕刻終止層(触__1¥)， 移除部份焊墊遮罩層500，以形成一圖案化之焊墊遮罩層5〇1，且曝露出部 份第二UBM層400，如第2D圖所示。緊接著，將一導電層6〇〇形成以覆 201005893201005893 IX. Description of the Invention: [Technical Field] The present invention relates to a package structure and method thereof, and more particularly to a package structure having a substrate pillar and a method therefor. [Prior Art] After the integrated circuit is manufactured, it needs to be connected to other components, radiate heat, and needs to be protected by the outer casing, so it needs to be packaged. The form of the integrated circuit package is simple and complicated, and due to the increasing integration of the Ultra Large Scale Integration (ULSI), the number of pins of the package is also increasing. The traditional package protects the die of the integrated circuit and provides power, heat dissipation, and connection to other components. Modern packaging is transformed to provide the next level of assembly compatibility after packaging. In response to the trend of thin and light 3C products, flip chip technology has become a very important part of electronic packaging technology. In the flip chip technology, the solder bump manufacturing technique is related to the connection performance of the semiconductor device. Referring to FIGS. 1A to 1C, the structure of the conventional tin bumps and the process thereof are described. As shown in FIG. 1A, a pad 3 is formed between the wafer 1 and the protective layer 2, and an under bump metallurgy (UBM) 22 is formed on the protective layer 20 and the pad 30. . Next, as shown in FIG. 1B, a photoresist layer 4 is formed on the bump underlying metal layer 22, and under the shielding of the photoresist layer 40, electroplating or printing is performed on the pad 3. Form high lead solder 5〇. Next, the photoresist layer 40 and a portion of the bump underlying metal layer 22 underneath are removed, and then a reflow step is performed at a reflow temperature of about 32 〇〇c to make the solder bump. The block 6 is fused into a spherical shape, as shown in FIG. 1C, and then, from the ID to the IF, which is a schematic flow chart of a conventional flip chip package. Referring to Fig. 1D, wafer 10 having solder bumps 60 is inverted upside down and flux is applied to fresh tin bumps 201005893 60. Next, the front tin bump 60 is overlaid on the substrate 70 as shown in Fig. 1E. Then, the recording step is carried out, and the solder bumps 6〇 are melted at a temperature of about 320 ° C and adhered to the substrate 70. Referring to FIG. 1F, since the difference in stress between the wafer 1 and the substrate 7 is too large, cracks are likely to occur between the bonding surfaces, that is, between the solder bumps 60, and thus between the respective bar tin bumps 60 The under filling material 80 is filled so that the stress is absorbed by the entire underfill 80, so that the stress acting on each of the solder bumps 60 is small, which improves reliability. Here, the material of the primer 80 used in the filling step may be epoxy resin (ep〇xy). However, since the etching selectivity ratio between the solder bump 60 and the under bump metal layer 22 is poor, 0, it is quite difficult to control the etching step of the bump underlying metal layer 22. In addition, in the production of high-speed charge and discharge elements, the characteristics of the strength and capacitance density of the solder bumps 60 are insufficient to meet the demand. In addition, the solder bumps 60 are all formed on the wafer 1 or are subjected to a re_w〇 process, which wastes the wafer 10, resulting in an increase in process cost. SUMMARY OF THE INVENTION In the above issues, the main purpose of the present invention is to provide a material-like electric column lion on the substrate. When the substrate is bonded to the wafer, it can be automatically aligned to increase the process yield. In accordance with the above purposes, the present invention discloses a package structure comprising: a substrate provided with a front side and a back side and having a first UBM layer on the front side; a patterned solder mask layer _ mask layer) Forming on the first ubM layer and exposing a surface of a portion of the first layer; a plurality of conductive pillars formed on the exposed first surface layer; a plurality of solder balls formed in the plurality of leads Providing a wafer with a front surface and a front side of the wafer facing the front side of the substrate; and a patterned second (10) river layer formed on the front side of the wafer and partially patterned The second UBM layer is electrically connected to the base. According to the above, the present invention provides a substrate having a front surface and a back surface; a first surface layer is formed on the front surface of the substrate; and a patterned 201005893 layer is formed. And forming a plurality of conductive pillars on a surface of the exposed first surface layer; forming a plurality of solder balls on the plurality of conductive pillars on the first top layer Providing a second surface layer having n-front and m-patterned on the front side of the wafer; and bonding the substrate and the wafer to face the front side of the wafer toward the front side of the substrate so that the upper portion of the wafer The patterned second layer is electrically connected to a plurality of solder balls on the substrate. The invention further provides a package structure comprising: a substrate provided with a front surface and a back surface, and a first-UBM layer on the front surface; and a patterned solder mask layer on the first Yinghe layer And exposing a surface of one of the first brain layers; a plurality of conductive pillars are formed on the surface of the exposed portion of the UBM layer; providing a wafer having a front surface and a back surface, and the wafer The front side faces the front of the »; the patterned second UBM layer is formed on the front side of the wafer; and the plurality of solder balls are formed in a patterned portion corresponding to the positions of the plurality of conductive columns of the substrate On a UBM layer, a plurality of solder balls on the wafer are electrically connected to a plurality of conductive pillars on the substrate. According to the above package structure, the present invention further discloses a package method comprising: providing a substrate having a front surface and a back surface; forming a first UBM layer on the front surface of the substrate; forming a patterned ITO pad layer Forming a portion of the surface of the first top layer of the first UBM layer; forming a plurality of conductive pillars on a portion of the exposed first UBM layer; forming a plurality of solder balls on the plurality of conductive pillars Providing a wafer having a front side and a back side; forming a patterned second UBM layer on the front side of the wafer and exposing a portion of the front side of the wafer; forming a plurality of solder balls on the exposed wafer On the front side, a plurality of solder balls correspond to a plurality of conductive turns on the substrate, and the substrate and the wafer are bonded to face the front side of the substrate so that the plurality of wafers are plural The solder ball is electrically connected to a plurality of conductive columns of the substrate. The features and implementations of the present invention are described in detail below with reference to the preferred embodiments. (In order to further understand the object, structure, features, and functions of the present invention, the following detailed description will be given in conjunction with the embodiments.) 201005893 [Embodiment] The present invention is in this respect for the face-to-face structure and its package. The method is a method in which a substrate having a pillar is bonded to a wafer and then packaged. In order to be able to thoroughly understand the steps of the present invention, which will be described in the following description, and the description thereof, the present invention is not limited to the specific details of those skilled in the art of wafer packaging. On the other hand, the well-known wafer formation method and the detailed stepping of the wafer thinning process are not described in detail to avoid unnecessary limitation of the invention. However, the preferred embodiments of the present invention will be described in detail below, but in addition to these detailed descriptions, the present invention can be widely practiced in its (10) implementation, and the present invention is not limited to The scope of the patents that follow will prevail. 2A to 2B are schematic views showing the steps of forming a patterned (10) PCT layer on a wafer. In Figure 2A, a wafer 100 is provided which has a front side and a back side. Next, a first UBM layer 2 is formed on the wafer 100. Then, a patterned photoresist layer (not shown in the figure) is formed on the first top layer 2; then, development and surname are performed to remove part of the first UBM layer 20 to form a patterned The first - Cong ^ layer 2 〇 1 and exposed part of the front side of the wafer, as shown in Figure 2B. _ Next '2C to 21 are schematic views showing the steps of forming a conductive post on a substrate. First, the substrate 300 is provided with a front side and a back side. Here, the material of the substrate 3 may be glass, quartz, ceramics, a circuit board or a thin metal plate. Next, a second UBM layer 400 and a pad mask layer 5 依 are sequentially formed on the front surface of the substrate 3, as shown in FIG. 2C. In this embodiment, the material of the pad mask layer 5 (10) is a dielectric material, and the material of the first UBM layer 2 and the second ubM layer 4 is Tiw/Ni. Next, a patterned photoresist layer (not shown) is formed on the pad mask layer 500; then a development and etching step is performed, and the second layer 400 is used as an etch stop layer (touch __1) ¥), a portion of the pad mask layer 500 is removed to form a patterned pad mask layer 5〇1, and a portion of the second UBM layer 400 is exposed, as shown in FIG. 2D. Then, a conductive layer 6 is formed to cover 201005893
• 蓋，案化之焊塾遮罩層5〇1上及已曝露之第二UBM層400上，如第2E 圖所不β在此實施例中，導電層600之材料為銅。 ，接著’在導電層6〇〇上形成一圖案化之光阻層(未在圖中表示广然後， 進行顯影及侧’移除部份導電層6⑻，形成複數個導電柱601在第二腦^ 層400上，且同時曝露出部份第工⑽㈣4〇之表面，如第2F圖所示。然 後在複數個導電柱601上方形成複數個錫球7⑻，如第圖所示。在此， 形成錫球，方式包括:首先在複數個導電柱6〇1上以電鍵的方式形成一鲜锡 凸塊；接著，再侧鱗_叫财絲每_個觸凸塊航以形成複數 〇 個錫球700，其中錫球700的材料為Sn/Ag或是Sn。 接下來，係將先前第2B圖之具有圖案化之第一 ubm層2〇1之晶圓1〇〇 上下倒轉，使得晶圓100之正面朝向基板3⑻之正面，且使得位於基板1〇〇 上之複數個導電柱601上之複數個錫球7〇〇與晶圓1〇〇上之圖案化之第一 UBM層201對準，然後再進行迴銲步驟，使得複數個錫球7〇〇可以與晶圓 100上之部份圖案化之第—顶厘層2〇1结合在一起，如第2h圖所示。最 後，於晶圓100與基板300之間再灌入一底膠材料細加^ material)800，以包覆圖案化之第一 υβΜ層2(n、晶圓1〇〇之部份正面圖 案化之焊塾遮罩層501、複數個導電柱6〇卜複數個錫球7〇〇及部份第二 層400 ’以形成一封裝結構，如第21圖所示。 在本發明的技術中’還揭露另一實施例，如第2J圖至第2Μ圖所示。 在此，在晶圓100上形成圖案化之第一 UBM層2〇1及在基板上形成第二 UBM層4〇〇、圖案化之焊塾遮罩層5(U、複數個導電柱6〇1之步驟以及其 材料均與先前之實施例相同，在此不再贅述。不_是，在複數個導電柱 601形成之後，形成一圖案化之阻障層9〇1以形成在已曝露之第二層 400之表面以及覆蓋在複數個導電柱6〇1之表面上，如第2J圖所示。其形 成圖案化之阻障層901的步驟包括:先形成一阻障層(未在圖中表示)在圖案 化之焊墊遮罩層50卜已曝露之第二ubm層4〇之表面及複數個導電柱⑼】 201005893 - 上。接下來，形成一圖案化之光阻層(未在圖中表示)在阻障層上。然後，執 行-顯影及-侧步驟，以移除在圖案化之焊塾遮罩層5〇1上之阻障層， 以形成-圖案化之阻障層901在已曝露之第二聰^層4〇〇之部份表面且覆 蓋住整個導電柱601的表面上。 接著，同樣參考第2K目’仍然是利用電鍵的方式，在具有圖案化之阻 障層9〇1之複數個導電柱6〇1的表面上形成複數瓣錫凸塊(未在圖中表 示）’然後再利用迴銲步驟，使得每一懈錫凸塊形成錫球·，並且固接 在每一個導電柱601的表面上。 ❹ 同樣地，係將先前第2B圖之具有圖案化之第- UBM層201之晶圓1〇〇 上下倒轉，使得晶圓100之正面朝向第2K圖中之基板3⑻之正面，使得位 於基板100上之複數個導電柱601上之複數個錫球700與晶圓1〇〇上之圖 案化之第一 UBM層201對準，然後再進行迴銲步驟，使得複數個錫球7〇〇 可以與晶圓100上之部份圖案化之第一 UBM層201結合在一起，如第乩 圖所示。最後’於晶圓100與基板300之間再灌入一底膠材料(under fimng material)800’以包覆圖案化之第一 ubM層2⑴、圖案化之焊墊遮罩層5〇卜 具有圖案化之阻障層901之複數個導電柱6(n、複數個錫球7〇〇、晶圓1〇〇 ❹ 之σ卩伤該正面及第一 UBM層400 ’以形成一封裝結構，如第2m圖所示。 第3Α圖至第31圖係表示本發明之封裝結構之另一較佳實施例。先提 供一晶圓100，其具有一正面及一背面，且在正面上具有複數個焊墊(未在 圖中表示）。然後，在晶圓100之正面上形成一第一 UBM層2⑻，如第3Α 圖所示。然後，在第一 UBM層上形成一圖案化之光阻層(未在圖中表示）； 接著’執行一顯影及一蝕刻步驟，以移除部份第一 UBM層200，且曝露出 晶圓100之正面(主動面)上之複數個焊墊102及晶圓100之部份表面，如第 3Β圖所示。 接下來’同樣參考第3C圖，在晶圓100之已曝露之焊塾1〇2上形成複 201005893 數個鲜錫&塊(未在® Μ示）；然:後，再進行迴_步ιρ，使得複數個銲錫凸 塊熔化形成錫球700並且與晶圓1〇〇上之焊墊1〇2固接。 緊接著’參考第3〇圖，係提供—基板3〇〇，其具有一正面及一背面。 然後’在基板300上依序形成第二職^層4〇〇及焊塾遮罩層5〇〇。接著， 在焊塾遮罩層5〇0上形成一圖案化之光阻層(未在圖中表示），並且以第二 UBM層4GG縣侧終止層；織，妨顯影及侧細，移除部份焊塾 遮罩層500，以曝露出第二獅!層4〇〇之部份表面且形成一圖案化之焊墊 遮罩層501在第二顶厘層4〇〇上，如第犯圖所示。 〇 接下來帛3F圖至第3G圖係表示在基板上形成複數個銅柱之各步驟 示意圖在第3F圖中’係在圖案化之焊塾遮罩層5〇1及已曝露之第二现μ 層上形成-導電層6G0 ’此導電層6〇〇之材料可以是銅。接著，形成一圖案 化之光阻層(未在圖中表示)在導電層6⑻上；然後，進行顯影及侧步驟、 移除部份導電層600且曝露出部份第二邱河層4〇〇之表面，並且在第二 UBM層400上形成複數個銅柱6〇1，如第3(}圖所示。 緊接著，係將先前第3C圖之具有複數個錫球7〇〇之晶圓丨⑻上下倒轉， 使得晶圓100之正面朝向第3G目中之基板3〇〇之正面，且使得位於晶圓1〇〇 Ο 上之複數個錫球700與基板300上之複數個導電柱601對準，然後再進行 迴銲步驟’使得晶圓100上之複數個錫球700可以與基板3⑻上之複數個 導電柱601結合在一起，如第3Η圖所示。最後，於晶圓1〇〇與基板3〇〇之 間再灌入一底膠材料(under filling material)8〇〇，以包覆住圖案化之第一 UBM層2(U、複數個錫球700、晶圓1〇〇之部份正面、圖案化之焊塾遮罩 層5(U、複數個導電柱601及部份第二现^^層4〇〇，以形成一封裝結構， 如第31圖所示。 在本發明的技術中，還揭露另一實施例，如第3J圖至第3L圖所示。 在此’在晶圓100上形成複數個錫球700及在基板上形成第二層4〇〇、 11 201005893 ®案化之焊塾遮罩層5〇1及複數個導電柱601之步驟以及其材料均與先前 之實施例相同，在此不再贅述。與之前實施例不同的是，在複數個導電柱 601形成之後，將一圖案化之阻障層9〇1形成在已曝露之第二顶乂層4〇〇 之表面上以及覆蓋在複數個導電柱6〇1之表面，如第3J圖所示。在此，形 成圖案化之阻障層901的步驟包括:先形成一阻障層(未在圖中表示)在圖案 化之焊墊遮罩層50卜已曝露之第二ubM層4〇〇之表面及複數個導電柱6〇1 上。接下來，形成一圖案化之光阻層(未在圖中表示)在阻障層上。然後，執 行一顯影及一蝕刻步驟，以移除在圖案化之焊墊遮罩層5〇1上之阻障層， 以形成一圖案化之阻障層9〇1在已曝露之第二腦1層之表面上且覆蓋住整 — 個導電柱601表面。 同樣地’係將先前第3C圖之具有複數個錫球700之晶圓1〇〇上下倒轉， 使得晶圓1GG之正面朝向第3ί时之基板3()之正面，且使得位於基板⑽ 上之被阻障層901覆蓋之複數個導電柱6〇1與晶圓1〇〇上之複數個錫球· 接觸’然後再進行迴銲步驟，使得複數個導電柱6〇1可以與晶圓ι〇〇上複 數個錫球700結合在-起，如第3K圖所示。最後，於晶圓1〇〇與基板 之間再灌入-底膠材料(under fimng material)8〇〇，以包覆住圖案化之第一 層20卜晶® 100之部份正Φ、複數個錫球700、圖案化之焊墊遮罩 層5〇卜具有圖案化之阻障層9〇1之複數個導電柱6〇1及第二層伽， 以形成一封裝結構，如第3L圖所示。 根據上述實施例’可以得知，將導電柱⑼丨形成在 3⑽上時，若 在製程中出現問題，要進行重工(re_而k)或是要報廢，基板3gg相較於晶圓 1〇〇來說其成本較便宜。另外，將導電柱咖形成在基板3⑽端可以自動 對準於晶圓1G0 ’也使得製程良率可以增加。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發 月任何熟1相像技藝者，在不脫離本發明之精神和範圍内，當可作些許 之更動與此本發明之專州練範_視本說明書所附之巾請專利 12 201005893 範圍所界定者為準。 【圖式簡單說明】 第U圖至第1C圖係根據習知 之示意圖； 文術’表示銲錫凸塊之結構及其製程 第1D圖至第1F圖係根據習知之 示意圖； 街’表示覆晶(flip chip)封裝之流程 ❹• Cover, the case of the solder mask layer 5〇1 and the exposed second UBM layer 400, as shown in FIG. 2E. In this embodiment, the material of the conductive layer 600 is copper. Then, a patterned photoresist layer is formed on the conductive layer 6 (not shown in the figure, then developed and laterally removed from the partial conductive layer 6 (8) to form a plurality of conductive pillars 601 in the second brain ^ On layer 400, and at the same time exposing the surface of part of the work (10) (four) 4, as shown in Fig. 2F. Then, a plurality of solder balls 7 (8) are formed over the plurality of conductive pillars 601, as shown in the figure. The solder ball comprises the following steps: firstly forming a fresh tin bump on the plurality of conductive pillars 6〇1 by means of an electric key; and then, the side scales _ called the fins each _ a bump bump to form a plurality of tins. The ball 700, wherein the material of the solder ball 700 is Sn/Ag or Sn. Next, the wafer 1〇〇 of the patterned first ubm layer 2〇1 of the previous FIG. 2B is inverted upside down, so that the wafer The front side of the 100 faces the front side of the substrate 3 (8), and the plurality of solder balls 7 on the plurality of conductive pillars 601 on the substrate 1 are aligned with the patterned first UBM layer 201 on the wafer 1 And then performing a reflow step so that a plurality of solder balls 7 can be patterned with the portion of the wafer 100 - The top layer 2〇1 is bonded together, as shown in FIG. 2h. Finally, a primer material 800 is further poured between the wafer 100 and the substrate 300 to coat the first pattern. υβΜ layer 2 (n, a portion of the wafer 1 正面 front side patterned solder mask layer 501, a plurality of conductive columns 6 复 a plurality of solder balls 7 〇〇 and a portion of the second layer 400 ′ to form a The package structure is as shown in Fig. 21. In the technique of the present invention, another embodiment is also disclosed, as shown in Figures 2J to 2D. Here, a patterned first UBM is formed on the wafer 100. The layer 2〇1 and the step of forming the second UBM layer 4 on the substrate, the patterned solder mask layer 5 (U, the plurality of conductive pillars 6〇1, and the materials thereof are the same as in the previous embodiment, This is not described again. No, after a plurality of conductive pillars 601 are formed, a patterned barrier layer 9〇1 is formed to be formed on the surface of the exposed second layer 400 and over the plurality of conductive pillars 6〇. The surface of 1 is as shown in Fig. 2J. The step of forming the patterned barrier layer 901 includes: first forming a barrier layer (not shown) in the patterning The pad layer 50 has exposed the surface of the second ubm layer and a plurality of conductive columns (9) 201005893 - above. Next, a patterned photoresist layer (not shown) is formed in the barrier layer. Then, performing a development-and-side step to remove the barrier layer on the patterned solder mask layer 5〇1 to form a patterned patterned barrier layer 901 in the exposed second A portion of the surface of the layer 4 is covered and covers the entire surface of the conductive pillar 601. Next, referring to the 2Kth item, it is still a method of using a key, in a plurality of patterned barrier layers 9〇1. A plurality of tin bumps (not shown) are formed on the surface of the conductive post 6〇1 and then a reflow step is used to form each solder bump to form a solder ball and is fixed to each of the conductive pillars 601. on the surface. Similarly, the wafer 1〇〇 of the patterned first UBM layer 201 of the previous FIG. 2B is inverted upside down so that the front side of the wafer 100 faces the front side of the substrate 3 (8) in the FIG. 2K, so that the substrate 100 is located. The plurality of solder balls 700 on the plurality of conductive pillars 601 are aligned with the patterned first UBM layer 201 on the wafer 1 , and then the reflow step is performed, so that the plurality of solder balls 7 can be combined with The partially patterned first UBM layer 201 on the wafer 100 is bonded together as shown in the first figure. Finally, an under fimng material 800' is implanted between the wafer 100 and the substrate 300 to coat the patterned first ubM layer 2 (1), and the patterned pad mask layer 5 has a pattern. The plurality of conductive pillars 6 of the barrier layer 901 (n, the plurality of solder balls 7 〇〇, the σ of the wafer 1 卩 damage the front surface and the first UBM layer 400 ′ to form a package structure, such as 2m to 31. Another preferred embodiment of the package structure of the present invention is shown. First, a wafer 100 having a front side and a back side and having a plurality of soldering on the front side is provided. a pad (not shown). Then, a first UBM layer 2 (8) is formed on the front side of the wafer 100, as shown in Fig. 3. Then, a patterned photoresist layer is formed on the first UBM layer ( Not shown in the figure); then performing a development and an etching step to remove a portion of the first UBM layer 200 and exposing a plurality of pads 102 and wafers on the front side (active side) of the wafer 100 Part of the surface of 100, as shown in Figure 3. Next 'also refer to Figure 3C, on the exposed solder bump 1〇2 of the wafer 100 Forming a number of 201005893 pieces of fresh tin & block (not shown in ®); then: then, back to _step ιρ, so that a plurality of solder bumps are melted to form solder balls 700 and soldered to the wafer 1 Pad 1〇2 is fixed. Immediately following the reference to Figure 3, a substrate 3 is provided, which has a front side and a back side. Then, a second job layer is formed on the substrate 300. Solder mask layer 5 〇〇. Next, a patterned photoresist layer (not shown in the figure) is formed on the solder mask layer 5 〇 0, and the second UBM layer 4 GG county side termination layer; The surface of the second lion! layer 4 is exposed and a patterned pad layer 501 is formed on the second top layer. On the layer 4, as shown in the figure. 〇 Next, from 3F to 3G, the steps of forming a plurality of copper columns on the substrate are shown in Fig. 3F. The conductive layer 6G0 is formed on the mask layer 5〇1 and the exposed second layer. The material of the conductive layer 6〇〇 may be copper. Then, a patterned photoresist layer is formed ( Shown in the figure) on the conductive layer 6 (8); then, development and side steps, removing part of the conductive layer 600 and exposing a portion of the surface of the second Qiuhe layer 4, and on the second UBM layer 400 Forming a plurality of copper pillars 6〇1, as shown in the third figure (}. Next, the wafer crucible (8) having a plurality of solder balls 7〇〇 in the previous FIG. 3C is inverted upside down, so that the front side of the wafer 100 Facing the front side of the substrate 3 in the 3G, and aligning the plurality of solder balls 700 on the wafer 1 with the plurality of conductive pillars 601 on the substrate 300, and then performing the reflow step 'making A plurality of solder balls 700 on the wafer 100 can be combined with a plurality of conductive pillars 601 on the substrate 3 (8) as shown in FIG. Finally, an under filling material 8 〇〇 is implanted between the wafer 1 and the substrate 3 to cover the patterned first UBM layer 2 (U, a plurality of solder balls) 700, a portion of the front side of the wafer, the patterned solder mask layer 5 (U, a plurality of conductive pillars 601 and a portion of the second layer) to form a package structure, such as 31. In the technique of the present invention, another embodiment is also disclosed, as shown in FIGS. 3J to 3L. Here, a plurality of solder balls 700 are formed on the wafer 100 and formed on the substrate. The steps of the second layer 4 〇〇, 11 201005893 ® case of the solder mask layer 5 〇 1 and the plurality of conductive pillars 601 and the materials thereof are the same as those of the previous embodiment, and are not described herein again. After the plurality of conductive pillars 601 are formed, a patterned barrier layer 9〇1 is formed on the surface of the exposed second top layer 4〇〇 and covered by the plurality of conductive pillars 6〇1. The surface is as shown in Fig. 3J. Here, the step of forming the patterned barrier layer 901 includes: first forming a barrier layer (not shown) in the pattern The pad layer 50 is exposed on the surface of the second ubM layer 4 及 and a plurality of conductive pillars 6 〇 1. Next, a patterned photoresist layer (not shown) is formed. On the barrier layer, a development and an etching step are then performed to remove the barrier layer on the patterned pad layer 5〇1 to form a patterned barrier layer 9〇1 that has been exposed The surface of the second brain layer covers the entire surface of the conductive pillar 601. Similarly, the wafer 1 having the plurality of solder balls 700 of the previous 3C is inverted upside down, so that the wafer 1GG The front side faces the front side of the substrate 3 () at the 3rd, and the plurality of conductive pillars 6〇1 covered by the barrier layer 901 on the substrate (10) are in contact with the plurality of solder balls on the wafer 1' and then Then, the reflowing step is performed, so that the plurality of conductive pillars 6〇1 can be combined with the plurality of solder balls 700 on the wafer, as shown in FIG. 3K. Finally, on the wafer 1 and the substrate Refilling the under fimng material 8〇〇 to cover the patterned first layer 20 of the wafers 100, positive Φ, plural The ball 700 and the patterned pad layer 5 have a plurality of conductive pillars 6〇1 and a second layer of gamma having a patterned barrier layer 9〇1 to form a package structure, as shown in FIG. 3L. According to the above embodiment, it can be known that when the conductive pillar (9) is formed on the 3 (10), if a problem occurs in the process, rework (re_ and k) or scrap is to be performed, and the substrate 3gg is compared with the wafer 1 In other words, the cost is relatively low. In addition, the formation of the conductive pillars at the end of the substrate 3 (10) can be automatically aligned to the wafer 1G0 '. The process yield can be increased. Although the present invention is disclosed above in the preferred embodiment, However, it is not intended to limit any skilled person in the present invention. Without departing from the spirit and scope of the present invention, it is possible to make some changes to the state of the invention. The scope defined in the scope of patent 12 201005893 shall prevail. [Simple description of the drawings] Figures U to 1C are schematic diagrams according to the conventional ones; the technique ' indicates the structure of the solder bumps and the process thereof, and the processes from 1D to 1F are based on the conventional schematic diagram; Flip chip) package process❹
圖案化UBM層之步驟^^據本發明所揭露之技術，表*在晶圓上形成一 電^=1 _據本翻所揭露之技術，表示在基板上形成導 第2J圖至第2M 構之各步驟示意圖； 圖係根據本發明所揭露之技術，表示形成另一封襞結 第3A圖至第31圖係根據本發明所揭露之技術，表示形成封裳結構之 另一較佳實施例之各步驟示意圖；及 第3J圖至第3L圖係根據本發明所揭露之技術，表示形成另一封裴結 構之各步驟示意圖。 【主要元件符號說明】 10 晶圓 20 保護層 22 凸塊底層金屬層 30 銲墊 40 光阻層 50 高鉛銲料 60 銲錫凸塊 70 基板 80 底膠 100 晶圓 200 第一 UBM層 13 201005893 201 圖案化之第一 UBM層 300基板 400 第二UBM層 500焊墊遮罩層 501 圖案化之焊墊遮罩層 600導電層 601 導電柱 700錫球 800 底膠材料 901圖案化之阻障層Step of patterning the UBM layer According to the technique disclosed in the present invention, the table * forms an electric ^ 1 on the wafer. According to the technique disclosed in the present disclosure, it is shown that the second to fourth structures are formed on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing the formation of another closure according to the technique disclosed in the present invention. FIG. 3A to FIG. 31 are diagrams showing another preferred embodiment of forming a closure structure according to the disclosed technology. A schematic diagram of each step; and 3J through 3L are schematic diagrams showing the steps of forming another sealing structure in accordance with the teachings of the present invention. [Main component symbol description] 10 wafer 20 protective layer 22 bump underlying metal layer 30 pad 40 photoresist layer 50 high lead solder 60 solder bump 70 substrate 80 undercoat 100 wafer 200 first UBM layer 13 201005893 201 pattern First UBM layer 300 substrate 400 second UBM layer 500 pad mask layer 501 patterned pad layer 600 conductive layer 601 conductive column 700 solder ball 800 underlying material 901 patterned barrier layer