200952326 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種接收器中之放大電路，且特別是 有關於一種接收器中之前置放大器及其中校準偏移電壓之 方法。 【先前技術】 對於一般接收器中的前置放大器而言，其通常係由數 級串聯的放大電路所組成，藉以將輸入信號依序放大。具 體地來說’通常係先將小信號的差動信號輸入至前置放大 器中’然後依序藉由其中串聯的放大電路將其放大，進而 成為大信號的差動信號，以供後續電路來使用。 然而’在前置放大器中，每一級的放大電路都具有或 多或少的偏移電壓於其中，使得放大電路所輸出而放大的 差動信號間會有不同的共同電壓位準。如此一來，由前置 放大器所輸出而放大的差動信號便可能具有工作週期（duty cycle)失真的問題，而且使用此前置放大器的接收器其偏差 容忍度（skew tolerance)也可能因此減低。 【發明内容】 本發明的目的是在提供一種前置放大器及其中校準偏 移電壓之方法，藉以改善放大之後輸出的差動信號。 依照本發明一實施例，提出一種前置放大器。此前置 放大器包含複數個串聯之放大電路，且串聯之放大電路之 5 200952326 /其中之&含一差動對開關電路、一比較器以及 個能量儲存單元。#叙斟M 複數 差動對開關電路具有一對差動輪入端 及一對差動輪屮她 u. ^ 艰以 動翰出端。比較器係用以比較差動輸出端 位’以輸出一比較作號。於县袖+ 口號此量储存單元係根據比較信號久 =且選擇性地_於差動輸出端其中之…以調整差= 出端之電位。 wBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an amplifying circuit in a receiver, and more particularly to a preamplifier in a receiver and a method of calibrating an offset voltage therein. [Prior Art] For a preamplifier in a general receiver, it is usually composed of a series of amplifier circuits connected in series to sequentially amplify the input signals. Specifically, 'the differential signal of the small signal is first input into the preamplifier', and then amplified by the amplification circuit connected in series, and then becomes the differential signal of the large signal for subsequent circuits. use. However, in the preamplifier, each stage of the amplifying circuit has a more or less offset voltage therein, so that the differential signals output by the amplifying circuit and the amplified differential signals have different common voltage levels. As a result, the differential signal amplified by the output of the preamplifier may have a problem of duty cycle distortion, and the skew tolerance of the receiver using the preamplifier may also be reduced. . SUMMARY OF THE INVENTION An object of the present invention is to provide a preamplifier and a method for calibrating an offset voltage thereof, thereby improving a differential signal output after amplification. In accordance with an embodiment of the invention, a preamplifier is provided. The preamplifier comprises a plurality of series amplifying circuits, and the series amplifying circuit 5 200952326 / wherein the & includes a differential pair switching circuit, a comparator and an energy storage unit. #叙斟M plural The differential pair switch circuit has a pair of differential wheel inlets and a pair of differential wheels 屮 her u. ^ difficult to move out. The comparator is used to compare the differential output terminal ' to output a comparison number. In the county sleeve + slogan, this amount of storage unit is based on the comparison signal for a long time = and selectively - in the differential output terminal ... to adjust the difference = the potential of the output. w
照本發明另一實施例，提出一種在前置放大器中校 準偏移電壓之方法。此方法包含：將在前置放大器中複數 個串聯之放大電路之至少-者中—差動對開關電路之一對 差動輸出端之電位相互比較’以輸出一比較信號；以及根 據比較信號將複數個能㈣存單元各別且選擇性地輛接於 差動輸出端其令之一，以調整差動輪出端之電位。 根據本發明之技術内容，應用前述前置放大器及其中 校準偏移電壓之方法可去除其_的偏移電壓，使得前置放 大器所輸出之放大後的差動信號間具有相同的共同電壓位 準，而且工作週期失真以及接收器之偏差容忍度減低的問 題亦得以解決。 【實施方式】 第1圖係緣示依照本發明實施例之一種前置放大器的 示意圖。前置放大器100包括數級（如：N級）串聯的放大電 路102，其甲每一放大電路102均可為一電流模式邏輯In accordance with another embodiment of the present invention, a method of calibrating an offset voltage in a preamplifier is presented. The method includes: comparing at least one of a plurality of series-connected amplifying circuits in the preamplifier - the potential of one of the differential pair switching circuits to the differential output terminals to output a comparison signal; and A plurality of (four) memory cells are individually and selectively connected to one of the differential output terminals to adjust the potential of the differential wheel output terminal. According to the technical content of the present invention, the preamplifier and the method for calibrating the offset voltage thereof can be used to remove the offset voltage of the preamplifier, so that the amplified differential signals output by the preamplifier have the same common voltage level. And the problem of distortion of duty cycle and reduced tolerance tolerance of the receiver is also solved. [Embodiment] Fig. 1 is a schematic view showing a preamplifier according to an embodiment of the present invention. The preamplifier 100 includes a plurality of stages (e.g., N stages) of series amplifying circuits 102, each of which can be a current mode logic.
(current mode logic，CML)電路。小差動信號 yip 和 viN 係輸入至第1級的放大電路102中’且依序由串聯的放大 6 200952326 電路102進行放大。接著，放大過後的差動信號v〇p和 VON再由第Ν級的放大電路1〇2輸出。 第2圖係依照本發明實施例繪示一種如第1圖所示之 放大電路中主要電路的示意圖。在此值得注意的是，在第1 圖所示之放大電路102中，至少其中之一者可包括如第2 圖所不之電路。在一實施例中，如第2圖所示之電路係包 括在第1級的放大電路102中，藉以校準其中的偏移電壓。 ^ 放大電路102包括一差動對開關電路200(包括電晶體(current mode logic, CML) circuit. The small differential signals yip and viN are input to the amplifying circuit 102 of the first stage' and are sequentially amplified by the series amplification 6 200952326 circuit 102. Then, the amplified differential signals v〇p and VON are output again by the amplification circuit 1〇2 of the second stage. Fig. 2 is a schematic view showing a main circuit of an amplifying circuit as shown in Fig. 1 according to an embodiment of the present invention. It is to be noted here that at least one of the amplifying circuits 102 shown in FIG. 1 may include a circuit as shown in FIG. In one embodiment, the circuit as shown in Fig. 2 is included in the amplification circuit 102 of the first stage to thereby calibrate the offset voltage therein. ^ Amplifying circuit 102 includes a differential pair switching circuit 200 (including a transistor)
Ql、Q2、Q3和電阻R1、R2)、一比較器2〇2、數個能量儲 、 存單元（如：電容C1、C2、…和CN)、一第一開關ρι、一 ， 第二開關P2以及一對參考能量儲存單元（如：電容CA和 CB)。差動對開關電路2〇〇具有一對差動輸入端（即νπ和 VI2)以及一對差動輸出端（即N1和N2)。比較器係用以 比較差動輸出的電位，並因此輸出一比較信號 CMP 一 OUT。電容C2、和CN在一啟始狀態下係耦接 於接地端（GND)’而之後則根據比較信號CMP-〇UT各別 ® 且選擇性地轉接於差動輸出端N1和N2其中之-，以調整 差動輸出端N1和N2的電位。其中，電容ci、C2、…和 CN的電容值可依據實際的情況設計成均相同、部分相同或 甚至互不相同的電容值。以下為了方便說明起見，係假設 7有電容的電容值均相同。第一開關P1係耦接於差動輸出 端N1和N2之間，並於開啟時將差動輸出端N1和N2短路。 第一開關P2係耦接於差動輸入端vn和VI2之間，並於開 啟時將差動輸入端Vn和VI2短路◊電容CA* CB則是分 200952326 別輕接於差動輸出端N1和N2。 以下將以一實施例來說明前置放大器中偏移電壓校準 的操作情形。首先’若第一開關P1開啟而使得差動輸出端 N1和N2短路，則比較器202會根據比較器202中本身所 存在的自偏移（self_0ffset)電壓輸出比較信號CMP_〇UT。此 時’電容C1、C2、…和CN會根據比較信號CMP_〇UT， 各別且選擇性地耦接於差動輸出端N1和N2其中之一，藉 以調整差動輸出端N1和N2的電位，並因而校準比較器202 中本身所存在的自偏移電壓。 接著，若第一開關P1關閉而第二開關P2開啟，使得 差動輸入端VII和VI2短路，則比較器202會根據差動輪 出端N1和N2之間的偏移（〇ffset)電壓輸出比較信號 CMP—OUT。此時，電容m、C2、…和CN會根據比較信號 CMP—OUT各別且選擇性地耦接於差動輸出端Ni和N2其 中之，藉以再次調整差動輸出端N1和N2的電位，並因 而校準差動輸出端N1和N2之間的偏移電壓。 舉例來說，若是差動輸出端N1的電位大於差動輸出端 N2的電位，則電容C1、C2、…和CN(或其中數個）會根據 比較V號CMP—OUT切換而耦接於差動輸出端N1。因此， 由下列等式： CA X V(N\) + CBx ν(Ν2) = (ca + Cl + ...)x v(m *)+CBx V(N2) ° '寻知差動輸出端N1調整過後的電位（即乂⑼*))係小於 200952326 ’、原先的電位。換&之’差動輸出端ni的電位會根據柄接 於差動輸出端N1之電容的數目多募而變動。 之後，當第一開關P1和第二開關P2均關閉時，則差 動信號再分別由差動輸入端VI1 # VI2輸入。此時，由於 差動輸出端N1和N2的電位已由上述的步驟進行校準，因 此自差動輸出端^^和^^輸出而放大的差動信號之間，便 不再具有偏移電壓差。 第3圖和第4圖係繪示依照本發明實施例之一種在前 置放大器中校準偏移電魔之方法的流程圖。請同時參照第 2 3和4圖。首先，將差動輸出端Ni和N2短路（步釋3 00)。 接著，藉由比較器202將差動輸出端N1和N2的電位相互 比較（步驟302)。之後，根據比較器2〇2中本身所存在的自 偏移電壓輪出比較信號CMP_OUT(步驟3〇4)。然後，根據 比較信號CMP 一 OUT，將在啟始狀態麵接於接地端的電容 C1、C2、和CN ’各別且選擇性地耦接於差動輸出端N1 和N2其中之一（步驟3〇6)’藉以調整差動輸出端Ni和N2 的電位°接著’再藉由上述將電容Cl、C2、…和CN各別 且選擇性地耦接於差動輸出端N1和N2其中之一，對比較 器202中本身所存在的自偏移電壓進行校準（步驟3〇8)。其 中’可分別將電容CA和CB耦接於差動輸出端N1和N2， 使得差動輸出端N1和N2的啟始電位可各自儲存於電容 CA和CB中。 再者，將差動輸入端VII和VI2短路（步驟310)»接著， 藉由比較器202將差動輸出端N1和N2的電位相互比較（步 200952326 驟312)。之後’根據差動輸出端N1和N2之間的偏移電虔 輸出比較信號CMP_OUT(步驟314)β然後，再次根據比較 信號CMP_OUT，將電容Cl、C2、.··和Cn各別且選擇性 地輕接於差動輸出端N1和N2其中之一（步驟316)，藉以 再次調整差動輸出端N1和N2的電位。接著，藉由上述將 電容Cl、C2、…和CN各別且選擇性地耦接於差動輸出端 N1和N2其中之一，對差動輸出端N1和N2之間的偏移電 鲁 壓進行校準（步驟318)。如此一來，自差動輸出端川和？^2 ' 輸出而放大後的差動信號之間，便不再具有偏移電壓差。 由上述本發明之實施例可知，應用前述前置放大器及 其中校準偏移電壓之方法，可去除其中的偏移電壓，使得 前置放大器所輸出之放大後的差動信號間，具有相同的共 同電塵位準。此外’應用前述前置放大器及其中校準偏移 電壓之方法的接收器，其中根據放大後的差動信號而決定 的工作週期（duty cycle)不會有失真的問題，且接收器亦可 _ 保持良好的偏差容忍度（skew t〇leranc约。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何具有本發明所屬技術領域之通常知識者，在 不脫離本發明之精神和範圍内，當可作各種之更動與潤 飾’因此本發明之保護範圍當視後附之申請專利範圍所界 定者為準。 【圖式簡單說明】 第1圖係繪示依照本發明實施例之一種前置放大器的 200952326 示意圖。 第2圖係依照本發明實施例繪示一種如第1圖所示之 放大電路中電路的示意圖。 第3圖和第4圖係繪示依照本發明實施例之一種在前 置放大器中校準偏移電壓之方法的流程圖。 【主要元件符號說明】 100 前置放大器 ® 102 放大電路 200 差動對開關電路 * 202 比較器 300〜318 :步驟 11Ql, Q2, Q3 and resistors R1, R2), a comparator 2〇2, a plurality of energy storage and storage units (such as capacitors C1, C2, ..., and CN), a first switch ρι, a second switch P2 and a pair of reference energy storage units (eg capacitors CA and CB). The differential pair switching circuit 2 has a pair of differential input terminals (i.e., νπ and VI2) and a pair of differential output terminals (i.e., N1 and N2). The comparator is used to compare the potential of the differential output and thus output a comparison signal CMP_OUT. The capacitors C2 and CN are coupled to the ground (GND) in a starting state and then selectively switched to the differential outputs N1 and N2 according to the comparison signal CMP-〇UT®. - to adjust the potential of the differential output terminals N1 and N2. The capacitance values of the capacitors ci, C2, ..., and CN can be designed to be equal, partially identical, or even different capacitance values depending on the actual situation. For the sake of convenience of explanation, it is assumed that the capacitance values of the capacitors are the same. The first switch P1 is coupled between the differential output terminals N1 and N2, and shorts the differential output terminals N1 and N2 when turned on. The first switch P2 is coupled between the differential input terminals vn and VI2, and shorts the differential input terminals Vn and VI2 when turned on. The tantalum capacitor CA* CB is divided into 200952326 and is not connected to the differential output terminal N1 and N2. The operation of the offset voltage calibration in the preamplifier will be described below with an embodiment. First, if the first switch P1 is turned on to short-circuit the differential output terminals N1 and N2, the comparator 202 outputs a comparison signal CMP_〇UT according to the self-offset (self_0ffset) voltage existing in the comparator 202 itself. At this time, the capacitors C1, C2, ..., and CN are individually and selectively coupled to one of the differential output terminals N1 and N2 according to the comparison signal CMP_〇UT, thereby adjusting the differential output terminals N1 and N2. The potential, and thus the self-offset voltage present in comparator 202 itself. Then, if the first switch P1 is turned off and the second switch P2 is turned on, so that the differential input terminals VII and VI2 are short-circuited, the comparator 202 compares the voltage output according to the offset (〇ffset) between the differential wheel terminals N1 and N2. Signal CMP_OUT. At this time, the capacitors m, C2, ..., and CN are respectively coupled to the differential output terminals Ni and N2 according to the comparison signal CMP_OUT, thereby adjusting the potentials of the differential output terminals N1 and N2 again. The offset voltage between the differential outputs N1 and N2 is thus calibrated. For example, if the potential of the differential output terminal N1 is greater than the potential of the differential output terminal N2, the capacitors C1, C2, ..., and CN (or several of them) are coupled to the difference according to the comparison V-number CMP-OUT switching. The output terminal N1. Therefore, the following equation is used: CA XV(N\) + CBx ν(Ν2) = (ca + Cl + ...)xv(m *)+CBx V(N2) ° 'Finding differential output terminal N1 adjustment The potential afterwards (ie 乂(9)*)) is less than 200952326', the original potential. The potential of the & differential output terminal ni varies depending on the number of capacitors that the handle is connected to the differential output terminal N1. Thereafter, when both the first switch P1 and the second switch P2 are turned off, the differential signals are again input by the differential input terminals VI1 #VI2, respectively. At this time, since the potentials of the differential output terminals N1 and N2 have been calibrated by the above steps, there is no offset voltage difference between the differential signals amplified by the differential output terminals ^^ and ^^. . 3 and 4 are flow diagrams showing a method of calibrating an offset electric magic in a preamplifier in accordance with an embodiment of the present invention. Please also refer to Figures 2 3 and 4. First, the differential output terminals Ni and N2 are short-circuited (step 300). Next, the potentials of the differential output terminals N1 and N2 are compared with each other by the comparator 202 (step 302). Thereafter, the comparison signal CMP_OUT is rotated in accordance with the self-offset voltage existing in the comparator 2〇2 (step 3〇4). Then, according to the comparison signal CMP_OUT, the capacitors C1, C2, and CN' connected to the ground end in the start state are individually and selectively coupled to one of the differential output terminals N1 and N2 (step 3〇) 6) 'By adjusting the potentials of the differential output terminals Ni and N2, then' and then selectively coupling the capacitors C1, C2, ... and CN to one of the differential output terminals N1 and N2, The self-offset voltage present in the comparator 202 itself is calibrated (step 3〇8). The capacitors CA and CB can be coupled to the differential output terminals N1 and N2, respectively, so that the start potentials of the differential output terminals N1 and N2 can be stored in the capacitors CA and CB, respectively. Further, the differential input terminals VII and VI2 are short-circuited (step 310). » Next, the potentials of the differential output terminals N1 and N2 are compared with each other by the comparator 202 (step 200952326, step 312). Then, 'the comparison signal CMP_OUT is output according to the offset between the differential output terminals N1 and N2 (step 314) β. Then, according to the comparison signal CMP_OUT, the capacitances C1, C2, . . . , and Cn are individually and selectively selected. Lightly connected to one of the differential output terminals N1 and N2 (step 316), thereby adjusting the potentials of the differential output terminals N1 and N2 again. Then, by separately coupling and selectively coupling the capacitors C1, C2, ..., and CN to one of the differential output terminals N1 and N2, the offset between the differential output terminals N1 and N2 is electrically depressed. Calibration is performed (step 318). As a result, the self-differential output Chuanhe? ^2 ' The output and the amplified differential signal no longer have an offset voltage difference. According to the embodiment of the present invention, the offset voltage can be removed by applying the preamplifier and the method for calibrating the offset voltage, so that the amplified differential signals output by the preamplifier have the same commonality. Electric dust level. In addition, a receiver for applying the foregoing preamplifier and a method for calibrating the offset voltage thereof, wherein a duty cycle determined according to the amplified differential signal has no problem of distortion, and the receiver can also remain </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The scope of the present invention is defined by the scope of the appended claims. [FIG. 1] FIG. 1 illustrates an embodiment in accordance with the present invention. A schematic diagram of a preamplifier 200952326. Fig. 2 is a schematic diagram of a circuit in an amplifying circuit as shown in Fig. 1 according to an embodiment of the invention. Figs. 3 and 4 are diagrams showing an embodiment of the present invention. A flow chart of a method for calibrating the offset voltage in a preamplifier. [Main component symbol description] 100 Preamplifier® 102 Amplifier Circuit 200 Poor Moving pair switch circuit * 202 Comparator 300~318: Step 11