200950096 '九、發明說明： *【發明所屬之技術領域】 本發明涉及一種薄膜電晶體，尤其涉及一種基於奈米 碳管的薄膜電晶體。 【先前技術】 薄膜電晶體（Thin Film Transistor, TFT )係現代微電 子技術中的一種關鍵性電子元件，目前已經被廣泛的應用 於平板顯示器等領域。薄膜電晶體主要包括基板，以及設 © 置於基板上的閘極、絕緣層、半導體層、源極和汲極。其 中，閘極通過絕緣層與半導體層間隔設置，源極和汲極間 隔設置並與半導體層電連接。薄膜電晶體中的閘極、源極、 汲極均為導電材料構成，該導電材料一般為金屬或合金。 當於閘極上施加電壓時，與閘極通過絕緣層間隔設置的半 導體層中會積累載子，當載子積累到一定程度，與半導體 層電連接的源極汲極之間將導通，從而有電流從源極流向 汲極。當該薄膜電晶體應用於半導體電子器件時，閘極連 ® 接控制電路，汲極連接相應的被控制元件，如液晶顯示器 中的圖元電極，通過薄膜電晶體可以控制該元件的工作。 先前技術中，薄膜電晶體中形成半導體層的材料為非 晶矽、多晶矽或有機半導體聚合物等（R. E. I. Schropp，B. Stannowski, J. K. Rath, New challenges in thin film transistor research, Journal of Non-Crystalline Solids, 299-302，1304-1310 (2002))。以非晶矽作為半導體層的非 晶矽TFT的製造技術較為成熟，但非晶矽TFT中，由於半 6 200950096 *導體層中通常含有大量的懸掛鍵，使得載子的移動率很低 .(一般小於從而使TFT的響應速度也較慢。 以多晶矽作為半導體層的TFT相對於以非晶矽作為半導體 層的TFT ’具有較高的載子移動率（一般約為 10cm V s )，因此響應速度也較快。但多晶梦tft低二 製造成本較高’方法較複雜，大面積製造困難，且多晶石夕 TFT的關態電流較大。相較于傳統的無機TFT，採用有機 半導體複合物做半導體層的有機TFT具有成本低、製造溫 ❹度低的優點，且有機TFT具有較高的柔韌性。但由於有二 半導體於常溫下多為跳躍式傳導，表現出較高的電阻率、 較低的載子移動率（〇.lcm2V-is-i)，使得有機TFT的響廄 速度較慢。 ^ 奈米碳管具有優異的力學及電學性能。並且，隨著奈 米碳管螺旋方式的變化，奈米碳管可呈現出金屬性或半導 體性。半導體性的奈米碳管具有較高的載子移動率（一般 可達1000〜1500 ) ’係製造電晶體的理想材料。先 前技術中一般採用噴墨法形成無序的奈米碳管層作為半導 體層，或採用直接生長奈米碳管陣列法形成半導體層。 先前技術中採用直接生長奈米碳管陣列作為半導體層 的薄膜電晶體，具有以下缺點：第一，於半導體層中太^ 碳管的排列方向垂直於基底，奈米碳管的排列方向非2源 極到汲極的方向，從而無法有效應用奈米碳管軸嚮導電的 優勢，第二，採用直接生長奈米碳管陣列作為半導體層，、 由於奈米碳管垂直生長於基底表面，奈米碳管陣列中:奈 7 200950096 :=管管壁之間靠結合残緊密’這種半導體 較差，不利於製造柔性薄膜電晶體。 軔性 先前技術中採用喷墨形成的無序奈米碳管層 ;層？;膜電晶體，其半導體層中奈米碳管隨機分佈，： 米碳管沿源極到沒極排列，半導體層中奈米碳管 沒極的有效路徑較長，載子移動率較低；另外， ❹ :述無序的μ碳管射奈米碳管之㈣軸結劑相互社 口’因此，該奈米碳管層為-較為鬆散 不利於製造柔性薄膜電晶體。 系韌f生較差 電曰採用奈米碳管作為半導體層的薄臈 電曰曰體’由於其半導體層中的奈米碳 源極軸方向的載子移動率，無法充分發揮二= 動率高的優勢，使得先前技術中採用奈米碳管作： 2層的薄臈電晶體響應速度低；另外，先前技術中採用 不…卡碳管作為半導體層的薄膜電晶體 ❹ 的奈米碳管之間的結合性不好導致該半導體;=中 不利於製造柔性薄膜電晶體。 曰系韌性差， 塑ΛΓ"Ι’/Ζ—種具諸高的載切料，較高的 容】具有較好的繼的薄膜電晶體實為必要。 -種薄膜電晶體，其包括：一源極 與該源極間隔設置…半導體層，該半導體 及極電連接；以及-閘極，該間極通過一絕声 體層、源極及没極絕緣設置;其中，該半導體二2 8 200950096 兩個重疊设置的奈米碳管薄膜，每一奈米碳管薄膜包括複 •數個定向排列的奈米碳管，且相鄰的兩個奈米碳管薄膜中 的奈米碳管沿不同同方向排列。 與先則技術相比較，本技術方案實施例提供的採用至 少兩個重疊設置的奈米碳管薄膜作為半導體層的薄膜電晶 體及半導體器件具有以下優點：其一，由於奈米碳管具有 優異的半導體性，則由首尾相連定向排列的奈米碳管組成 的奈米碳管薄膜中的奈米碳管具有共同的排列取向，可以 ®發揮奈米碳管軸冑導電的優冑，使薄膜電晶體具有較大的 載子移動率，進而具有較快的響應速度。其二，由至少兩 個重疊定向排列的奈米碳管組成的奈米碳管層中，相鄰的 兩個奈米碳管薄膜中的奈米碳管沿不同同方向排列，由於 奈米碳管具有優異的力學性能，故採用該交又的奈米碳管 薄膜構成的奈米碳管層作為半導體層，可以提高薄膜電晶 體的柔韌性。 @ 【實施方式】 以下將結合附圖詳細說明本技術方案實施例提供的薄 膜電晶體。 請參閱圖1’本技術方案第一實施例提供一種薄膜電 晶體10，該薄膜電晶體10為頂閘型，其包括一閘極12〇、 一絕緣層130、一半導體層140、一源極151及一没極152， 並且’該薄膜電晶體10形成於一絕緣基板11〇表面。 所述半導體層140設置於該絕緣基板11〇表面；所述 源極151及汲極152間隔設置於所述半導體層14〇表面並 200950096 ，與該半導體層140電連接，且位於該源極151及汲極152 •之間的半導體層形成一通道156 ;所述絕緣層130設置於 該半導體層140表面；所述閘極120設置於所述絕緣層130 表面，並通過該絕緣層130與源極151、汲極152及半導 體層140電絕緣，所述絕緣層130設置於閘極120與半導 體層140之間。優選地，所述閘極可以對應通道156設置 於絕緣層130表面。 可以理解，所述源極151及汲極152可以間隔設置於 ❹該半導體層140的上表面位於絕緣層130與半導體層140 之間，此時，源極151、汲極152與閘極120設置於半導 體層140的同一面，形成一共面型薄膜電晶體。或者，所 述源極151及汲極152可以間隔設置於該半導體層140的 下表面，位於絕緣基板110與半導體層140之間，此時， 源極151、汲極152與閘極120設置於半導體層140的不 同面，半導體層140設置於源極151、汲極152與閘極120 之間，形成一交錯型薄膜電晶體。 ® 可以理解，根據具體的形成工藝不同，所述絕緣層130 不必完全覆蓋所述源極151、汲極152及半導體層140，只 要能確保半導體層140與相對設置的閘極120與半導體層 140、源極151、汲極152絕緣即可。如，當所述源極151 及汲極152設置於半導體層140上表面時，所述絕緣層130 可僅設置於源極151及汲極152之間，只覆蓋半導體層 140 ° 所述絕緣基板110起支撐作用，該絕緣基板110材料 200950096 不限，可選擇為玻璃、石英、陶瓷、金剛石等硬性材料或 塑膠、樹脂等柔性材料。本實施例中，所述絕緣基板11〇 的材料為玻璃。所述絕緣基板110用於對薄膜電晶體1〇 提供支撐’且複數個薄膜電晶體10可按照預定規律或圖形 集成於同一絕緣基板110上，形成TFT面板，或其他tft 半導體器件。 所述半導體層140包括至少兩個重疊的奈米碳管薄 =、，母、、奈米碳管薄膜包括複數個定向排列的半導體性的 ❹奈米碳管，且相鄰的兩個奈米碳管薄膜中的奈米碳管沿不 同方向排列。戶斤述半導體| 14〇中至少一層奈米碳管薄膜 中至少部分奈米碳管沿源極151至汲極152方向排列。優 =的’所述至少兩個奈米碳管薄膜中至少有—個奈米碳管 薄膜中的奈来碳管沿源極151指向汲極152的方向排列。 :，相鄰兩個奈米碳管薄膜中的奈米碳管的排列方向具有 一交又角度α’0<α例度，相鄰的奈米碳管薄膜之間通過 ❹凡德瓦爾力緊密結合’使得所述薄臈電晶體具有較好的 請參閱圖2,該奈米碳管薄膜為從超順排奈米碳管陣 =中直接拉取獲得，該奈米碳f薄膜進—步包括複數個首 :連的奈米碳管束諸，每個奈米碳管束片段具有大致 十且每個奈米碳管束片段由複數個相互平行的奈 2吕束構成，奈米碳管束諸兩端通過凡德瓦爾力相互 的擇優奈米碳管具，嚮導電特性，該直接拉伸獲得 Π排列的奈米碳管薄膜於奈米碳管的排列方向比 11 200950096 無序的奈米碳管薄膜具有更高的載子移動率。該奈米碳管 薄膜的厚度為0.5奈米〜1〇〇微米。奈米碳管薄膜中的奈米 碳管可以係單壁奈米碳管或雙壁奈米碳管。所述單壁^米 碳管的直徑為0.5奈米〜50奈米；所述雙壁奈米碳管二^ 徑為1.0奈米〜50奈米。優選地，所述奈米碳管的直徑小 於10奈米。 所述半導體層140的長度為1微米〜1〇〇微米，寬度為 1微米〜1毫米，厚度為0.5奈米〜1〇〇微米。所述通道156 €>的長度為1微米〜100微米，寬度為1微米〜i毫米。請參 閱圖3，本技術方案實施例中，該半導體層14〇包括交叉 重疊SX置的二層奈米碳管薄膜，該奈米破管薄膜中包括複 數個首尾相連定向排列的奈米碳管，二層奈米碳管薄膜中 的奈米碳管的排列方向具有一交又角度α為9〇度，每一 奈米碳管薄膜的厚度為5奈米。所述半導體層14〇的長度 為50微米，寬度為3〇〇微米，厚度為1〇奈米。所述通道 U 156的長度為40微米，寬度為300微米。 本實施例中，源極151、汲極152及閘極12〇為一導 電薄膜。該導電薄膜的材料可以為金屬、合金、ΙΤΟ、ΑΤΟ、 導電銀膠、導電聚合物以及導電奈米碳管等。該金屬或合 金材料可以為銘、銅、鎢、钥、金、铯、把或其合金。優 選地’該閘極12〇的面積與所述通道156的面積相當，使 用時有利於通道156積累載子’閘極120的厚度為〇·5奈 米〜100微米。本實施例中，所述閘極120的材料為金屬鋁， 厚度為5奈米；所述源極151、汲極152的材料為金屬铯， 12 200950096 所述金屬铯與奈米碳管具有較好的潤濕效果，厚度為5奈 .米。 所述絕緣層130材料為氮化矽、氧化矽等硬性材料或 苯並環丁烯（BCB)、聚酯或丙烯酸樹脂等柔性材料。該絕 緣層130的厚度為0.5奈米~1〇〇微米。本實施例中，所述 絕緣層130的材料為氮化矽，厚度為2〇〇奈米。 請參見圖4，本技術方案第一實施例的薄臈電晶體1〇 使用時，於閘極120上施加一電壓Vg，將源極151接地， ❹並於汲極152施加一電壓Vds，閘極電壓、於半導體層14〇 的通道156中產生電場，並於通道156表面處產生載子。 隨著閘極電壓Vg的增加，通道156轉變為載子積累層，當 Vg達到源極151和汲極152之間的開啟電壓時，源極151 與汲極152之間的通道156導通，從而會於源極i5i和汲 極152之間產生電流，電流由源極151通過通道流向 154 ’從而使得該薄膜電晶體1〇處於開啟狀態。由於所述 ◎半導體層140中僅包括半導體性的奈米碳管，而半導體性 的奈米碳管具有較高的載子移動率，且該半導體層140中 包括至少「層奈米碳管薄膜中的奈米碳管首尾相連地沿源 極151到;及極152的方向排列，而奈米碳管轴嚮導電性較 控向強’故載子由雜151經半導㈣14〇至沒極M2方 輸具有較短的傳輸路徑’故，由所述奈米碳管組成的 輕作為半導體層14G，可以使所述薄膜電晶體 虛：吞較大的載子移動率，進而提高薄膜電晶體10的響 龐祙疳。 13 200950096 由於本技術方案實施例半導體層14〇中的奈米碳管具 有較好的半導體性，且該半導體層中至少一層奈米碳管薄 膜中的奈米碳管沿從源極151至汲極152的方向排列，故 載子於具有較好軸向傳輸性能的奈米碳管中具有較高的移 動率’故由所述奈米碳管組成的奈米碳管薄膜作為半導體 層140,可以使所述薄膜電晶體1〇具有較大的載子移動 率，進而提高薄膜電晶體1〇的響應速度。本技術方案實施 例中’所述薄膜電晶體1〇的載子移動率高於1〇 © cm V s 1 ’開關電流比為1χ1〇2〜1χ1〇7。優選地，所述薄膜 電晶體10的載子移動率為1〇〜15〇〇 cm2v-is-i。 請參閱圖5,本技術方案第二實施例採用於第一實施 例相似的方法提供一種薄膜電晶體2〇，該薄膜電晶體2〇 為底閘型’其包括一閘極220、絕緣層230 —半導體層240、 一源極251及一汲極252 ’並且，該薄膜電晶體2〇設置於 一絕緣基板210表面。本技術方案第二實施例薄膜電晶體 20的結構與薄膜電晶體1〇基本相同，其區別在於第二實 ❿施例薄膜電晶體20為底閘型。 所述閘極220設置於該絕緣基板21〇表面，所述絕緣 層230設置於閘極220表面，所述半導體層240設置於該 絕緣層230表面，所述絕緣層230設置於閘極220與半導 體層240之間；所述源極251、汲極252間隔設置於該半 導體層240表面，並通過該半導體層24〇電連接；所述半 導體層240位於所述源極251和汲極252之間的區域形成 一通道256。優選地，該閘極220可以與源極251、汲極 14 200950096 252之間的通道256對應設置於絕緣基板210表面，且該 •閘極220通過該絕緣層230與源極251、汲極252及半導 體層240電絕緣。本技術方案第二實施例提供的薄膜電晶 體20中，閘極220、源極251、汲極252及絕緣層230的 材料與第一實施例中薄膜電晶體1〇的閘極120、源極151、 汲極152及絕緣層130的材料相同。第二實施例提供的薄 膜電晶體20中，通道256、半導體層240的形狀、面積與 第一實施例中薄膜電晶體1〇的通道156、半導體層240的 ©形狀、面積相同。 所述源極251及汲極252可以設置於該半導體層240 上表面，此時，源極251、沒極252與閘極220設置於半 導體層240的不同面，半導體層240設置於源極251、汲 極252與閘極220之間，形成一逆交錯結構的薄膜電晶體。 或者，所述源極251及汲極252也可以設置於該半導體層 240下表面與絕緣層130之間，此時，源極251、汲極a% ❹與閘極220設置於半導體層140的同一面，形成一逆共面 結構的薄膜電晶體。 與先前技術相比較，本技術方案實施例提供的採用至 少兩個重疊設置的奈米碳管薄膜作為半導體層的薄臈電晶 ，具有以下優點：其-’採用至少兩層交叉重疊的奈米碳 管薄膜作為半導體層，每個奈米碳管薄膜中的奈米碳管首 尾相連定向排列，且該半導體層中至少有—層奈米碳管薄 膜中奈米碳管首尾相連沿薄膜電晶體的源極到汲極的方向 排列，載子沿奈米碳管軸向運動，從源極向没極運動具有 15 200950096 ’較短的路徑’因此可以使薄膜電晶體具有較大的載子移動 *率和較快響應速度。其二’由至少兩個重疊定向排列的奈 米碳管組成的奈米碳管層中，至少兩個奈米碳管薄膜交又 設置’由於每一奈米碳管薄膜中奈米碳管首尾相連定向排 列’故採用該交叉設置的奈米碳管薄膜構成的半導體層具 有更好的柔韌性，可以應用於製造柔韌性較高的薄膜電晶 體。其三，由於碳奈米米管薄膜組成的半導體層較其他半 導體材料更耐高溫，因此，該薄膜電晶體以及使用該薄膜 ❹電晶體的半導體器件可以於較高溫度下工作。 综上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施例， 自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝 之人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本技術方案第一實施例TFT的剖視結構示意 圖。 圖2係本技術方案第一實施例TFT中作為半導體層的 奈米碳管薄膜的掃描電鏡照片。 圖3係本技術方案第一實施例TFT中兩層交又設置夺 米碳管薄膜的掃描電鏡照片。 不 圖4係本技術方案第一實施例工作時的薄膜電晶體的 結構示意圖。 圖5係本技術方案第二實施例TFT的剖視結構示意 16 200950096 圖。 【主要元件符號說明】 絕緣基板 110， 210 閘極 120， 220 絕緣層 130， 230 半導體層 140， 240 源極 151， 251 汲極 152， 252 © 通道 156， 256 17200950096 'IX. Description of the invention: * [Technical field to which the invention pertains] The present invention relates to a thin film transistor, and more particularly to a thin film transistor based on a carbon nanotube. [Prior Art] Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology and has been widely used in flat panel displays and the like. The thin film transistor mainly includes a substrate, and a gate, an insulating layer, a semiconductor layer, a source, and a drain which are disposed on the substrate. The gate is spaced apart from the semiconductor layer by an insulating layer, and the source and the drain are spaced apart from each other and electrically connected to the semiconductor layer. The gate, the source and the drain of the thin film transistor are all made of a conductive material, and the conductive material is generally a metal or an alloy. When a voltage is applied to the gate, carriers are accumulated in the semiconductor layer spaced apart from the gate through the insulating layer, and when the carrier is accumulated to a certain extent, the source drain connected to the semiconductor layer is turned on, thereby Current flows from the source to the drain. When the thin film transistor is applied to a semiconductor electronic device, the gate is connected to a control circuit, and the drain is connected to a corresponding controlled component, such as a pixel electrode in the liquid crystal display, and the operation of the component can be controlled by the thin film transistor. In the prior art, a material for forming a semiconductor layer in a thin film transistor is an amorphous germanium, a polycrystalline germanium or an organic semiconductor polymer (REI Schropp, B. Stannowski, JK Rath, New challenges in thin film transistor research, Journal of Non-Crystalline Solids). , 299-302, 1304-1310 (2002)). The fabrication technique of amorphous germanium TFT with amorphous germanium as the semiconductor layer is relatively mature, but in the amorphous germanium TFT, since the conductor layer usually contains a large number of dangling bonds, the carrier mobility is very low. Generally, the response speed of the TFT is also slower. The TFT having the polysilicon as the semiconductor layer has a higher carrier mobility (generally about 10 cm V s ) with respect to the TFT of the amorphous germanium as the semiconductor layer, and thus the response The speed is also faster. However, the polycrystalline dream tft is lower in manufacturing cost. The method is more complicated, the large-area manufacturing is difficult, and the off-state current of the polycrystalline silicon TFT is larger. Compared with the conventional inorganic TFT, the organic semiconductor is used. The organic TFT which is a semiconductor layer of the composite has the advantages of low cost and low temperature temperature, and the organic TFT has high flexibility. However, since two semiconductors are mostly skipped at normal temperature, they exhibit high resistance. Rate, low carrier mobility (〇.lcm2V-is-i), making the organic TFT slower. ^ Nano carbon nanotubes have excellent mechanical and electrical properties. And, with carbon nanotubes Spiral mode The change of the carbon nanotubes can be metallic or semiconducting. The semiconducting carbon nanotubes have a high carrier mobility (generally up to 1000~1500). The ideal material for making transistors. Generally, an inkjet method is used to form a disordered carbon nanotube layer as a semiconductor layer, or a direct growth carbon nanotube array method is used to form a semiconductor layer. In the prior art, a direct growth carbon nanotube array is used as a thin film of a semiconductor layer. The crystal has the following disadvantages: First, in the semiconductor layer, the arrangement direction of the carbon tubes is perpendicular to the substrate, and the arrangement direction of the carbon nanotubes is not in the direction of the 2 source to the drain, so that the carbon nanotube axis cannot be effectively applied. The advantage of conductivity, second, the direct growth of the carbon nanotube array as a semiconductor layer, because the carbon nanotubes grow vertically on the surface of the substrate, in the carbon nanotube array: Nai 7 200950096 : = between the tube wall The combination of residual and compact semiconductors is inferior to the fabrication of flexible thin film transistors. The prior art uses a disordered carbon nanotube layer formed by inkjet; a layer; a membrane transistor, half of which The carbon nanotubes in the body layer are randomly distributed, and the carbon nanotubes are arranged along the source to the immersion. In the semiconductor layer, the effective path of the carbon nanotubes is longer and the carrier mobility is lower. In addition, ❹: disorder The μ carbon tube emits the carbon nanotubes (4) the shafting agent mutual mutual interface 'Therefore, the carbon nanotube layer is - looser and not conducive to the manufacture of flexible thin film transistors. The toughness of the poor electricity is the use of carbon nanotubes The thin tantalum electrode body as the semiconductor layer cannot sufficiently exhibit the advantage of high mobility due to the carrier mobility of the nanocarbon source in the semiconductor layer, so that the carbon nanotubes in the prior art are used. For the two-layer thin germanium transistor, the response speed is low; in addition, the bonding between the carbon nanotubes of the thin film transistor using the carbon nanotube as the semiconductor layer in the prior art is not good, resulting in the semiconductor; Not conducive to the manufacture of flexible film transistors. The tanning system has poor toughness, and the plastic ΛΓ Ι Ζ Ζ Ζ 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 种 。 。 。 。 。 。 。 。 。 。 。 a thin film transistor comprising: a source spaced from the source; a semiconductor layer, the semiconductor and a very electrical connection; and a gate, the interpole being disposed through a sound insulator layer, a source and a non-polar insulation Wherein, the semiconductor two 2 8 200950096 two overlapping carbon nanotube films, each carbon nanotube film comprises a plurality of aligned carbon nanotubes, and two adjacent carbon nanotubes The carbon nanotubes in the film are arranged in different directions. Compared with the prior art, the thin film transistor and the semiconductor device using the at least two overlapping carbon nanotube films as the semiconductor layer provided by the embodiments of the present technical solution have the following advantages: First, since the carbon nanotubes are excellent The semiconducting nature of the carbon nanotubes in the carbon nanotube film consisting of the carbon nanotubes arranged in an end-to-end orientation has a common alignment orientation, and can be used to exert the advantages of the carbon nanotube shaft 胄 conductivity. The transistor has a large carrier mobility and thus a faster response speed. Second, in the carbon nanotube layer composed of at least two carbon nanotubes arranged in an overlapping orientation, the carbon nanotubes in the adjacent two carbon nanotube films are arranged in different directions, due to the nanocarbon Since the tube has excellent mechanical properties, the carbon nanotube layer formed by the carbon nanotube film of the cross can be used as a semiconductor layer to improve the flexibility of the thin film transistor. [Embodiment] Hereinafter, a thin film transistor provided by an embodiment of the present technical solution will be described in detail with reference to the accompanying drawings. Please refer to FIG. 1 '. The first embodiment of the present invention provides a thin film transistor 10 , which is a top gate type, and includes a gate 12 , an insulating layer 130 , a semiconductor layer 140 , and a source 151 and a gate 152, and 'the thin film transistor 10 is formed on the surface of an insulating substrate 11. The semiconductor layer 140 is disposed on the surface of the insulating substrate 11; the source 151 and the drain 152 are spaced apart from the surface of the semiconductor layer 14 and 200950096, and are electrically connected to the semiconductor layer 140 and located at the source 151. The semiconductor layer between the drain and the drain 152 is formed with a channel 156; the insulating layer 130 is disposed on the surface of the semiconductor layer 140; the gate 120 is disposed on the surface of the insulating layer 130, and passes through the insulating layer 130 and the source The pole 151, the drain 152 and the semiconductor layer 140 are electrically insulated, and the insulating layer 130 is disposed between the gate 120 and the semiconductor layer 140. Preferably, the gate may be disposed on the surface of the insulating layer 130 corresponding to the channel 156. It can be understood that the source 151 and the drain 152 may be disposed at intervals on the upper surface of the semiconductor layer 140 between the insulating layer 130 and the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed. On the same side of the semiconductor layer 140, a coplanar thin film transistor is formed. Alternatively, the source 151 and the drain 152 may be disposed on the lower surface of the semiconductor layer 140 between the insulating substrate 110 and the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed on Different sides of the semiconductor layer 140, the semiconductor layer 140 is disposed between the source 151, the drain 152 and the gate 120 to form a staggered thin film transistor. ® It is understood that the insulating layer 130 does not have to completely cover the source 151, the drain 152 and the semiconductor layer 140, as long as the semiconductor layer 140 and the oppositely disposed gate 120 and the semiconductor layer 140 are ensured, depending on the specific formation process. The source 151 and the drain 152 may be insulated. For example, when the source 151 and the drain 152 are disposed on the upper surface of the semiconductor layer 140, the insulating layer 130 may be disposed only between the source 151 and the drain 152, covering only the semiconductor layer 140°. The support material of the insulating substrate 110 is not limited to 110, and may be selected from a hard material such as glass, quartz, ceramic, diamond or the like, or a flexible material such as plastic or resin. In this embodiment, the material of the insulating substrate 11 is glass. The insulating substrate 110 is used to provide support for the thin film transistor 1' and a plurality of thin film transistors 10 can be integrated on the same insulating substrate 110 according to a predetermined pattern or pattern to form a TFT panel, or other tft semiconductor device. The semiconductor layer 140 includes at least two overlapping carbon nanotubes thinner, and the mother carbon nanotube film comprises a plurality of aligned semiconducting carbon nanotubes, and two adjacent nanometers. The carbon nanotubes in the carbon tube film are arranged in different directions. At least a portion of the carbon nanotube film in at least one of the 14 〇 is arranged in the direction of the source 151 to the drain 152. The carbon nanotubes in at least one of the at least two carbon nanotube films are arranged in the direction in which the source 151 is directed to the drain 152. : The arrangement direction of the carbon nanotubes in the adjacent two carbon nanotube films has an intersection angle α'0<α degree, and the adjacent carbon nanotube films are closely connected by the van der Waals force Combining 'to make the thin tantalum transistor have better, please refer to FIG. 2, the nano carbon tube film is obtained by directly pulling from the super-sequential carbon nanotube array=, the nano carbon f film is advanced The utility model comprises a plurality of first carbon nanotube bundles, each nano carbon nanotube bundle segment has approximately ten and each nano carbon nanotube bundle segment is composed of a plurality of mutually parallel neon 2 bundles, and the carbon nanotube bundle ends are respectively Through van der Valli's mutual selection of nano-carbon tubes, the direct-stretching of the carbon nanotube film in the orientation direction of the carbon nanotubes is obtained by the direct stretching of the van der Waals force. 11 200950096 Disordered carbon nanotube film Has a higher carrier mobility. The carbon nanotube film has a thickness of from 0.5 nm to 1 μm. The carbon nanotubes in the carbon nanotube film can be single-walled carbon nanotubes or double-walled carbon nanotubes. The single-walled carbon nanotube has a diameter of 0.5 nm to 50 nm; and the double-walled carbon nanotube has a diameter of 1.0 nm to 50 nm. Preferably, the carbon nanotubes have a diameter of less than 10 nm. The semiconductor layer 140 has a length of 1 μm to 1 μm, a width of 1 μm to 1 mm, and a thickness of 0.5 nm to 1 μm. The channel 156 €> has a length of 1 micron to 100 micron and a width of 1 micron to 1 millimeter. Referring to FIG. 3 , in the embodiment of the technical solution, the semiconductor layer 14 includes a two-layer carbon nanotube film which is overlapped and disposed on the SX, and the nano tube-breaking film includes a plurality of carbon nanotubes arranged in an end-to-end orientation. The arrangement of the carbon nanotubes in the two-layer carbon nanotube film has an intersection angle α of 9 ,, and the thickness of each carbon nanotube film is 5 nm. The semiconductor layer 14 has a length of 50 μm, a width of 3 μm, and a thickness of 1 μm. The channel U 156 has a length of 40 microns and a width of 300 microns. In this embodiment, the source 151, the drain 152 and the gate 12 are a conductive film. The material of the conductive film may be metal, alloy, tantalum, niobium, conductive silver paste, conductive polymer, and conductive carbon nanotubes. The metal or alloy material may be ingot, copper, tungsten, molybdenum, gold, rhodium, or alloys thereof. Preferably, the area of the gate 12A is comparable to the area of the channel 156, which facilitates the accumulation of the carrier by the channel 156. The thickness of the gate 120 is 〇·5 nm to 100 μm. In this embodiment, the material of the gate 120 is metal aluminum and has a thickness of 5 nm; the material of the source 151 and the drain 152 is a metal crucible, and 12 200950096 has a metal crucible and a carbon nanotube. Good wetting effect, thickness is 5 nanometers. The material of the insulating layer 130 is a hard material such as tantalum nitride or yttrium oxide or a flexible material such as benzocyclobutene (BCB), polyester or acrylic resin. The insulating layer 130 has a thickness of from 0.5 nm to 1 μm. In this embodiment, the insulating layer 130 is made of tantalum nitride and has a thickness of 2 nanometers. Referring to FIG. 4, when the thin germanium transistor 1 of the first embodiment of the present invention is used, a voltage Vg is applied to the gate 120, the source 151 is grounded, and a voltage Vds is applied to the drain 152. An extreme voltage, an electric field is generated in the channel 156 of the semiconductor layer 14 turns, and a carrier is generated at the surface of the channel 156. As the gate voltage Vg increases, the channel 156 transitions to a carrier accumulation layer, and when Vg reaches the turn-on voltage between the source 151 and the drain 152, the channel 156 between the source 151 and the drain 152 is turned on, thereby A current is generated between the source i5i and the drain 152, and the current flows from the source 151 through the channel to the 154' such that the thin film transistor 1 is turned on. Since the semiconductor layer 140 includes only a semiconducting carbon nanotube, the semiconducting carbon nanotube has a high carrier mobility, and the semiconductor layer 140 includes at least a “layer carbon nanotube film”. The carbon nanotubes in the end are connected end to end in the direction of the source 151; and the pole 152, and the axial conductivity of the carbon nanotube is stronger than the control direction, so the carrier is made up of 151 by semi-conducting (four) 14 〇 to the immersion The M2 square transmission has a short transmission path. Therefore, the light semiconductor layer 14G composed of the carbon nanotubes can make the thin film transistor virtual: swallow a large carrier mobility, thereby increasing the thin film transistor. 10 200950096 The carbon nanotubes in the semiconductor layer 14〇 of the embodiment of the technical solution have better semiconductivity, and the carbon nanotubes in at least one layer of the carbon nanotube film in the semiconductor layer follow The source 151 is arranged in the direction of the drain 152, so that the carrier has a high mobility in the carbon nanotube having better axial transmission performance, so the carbon nanotube film composed of the carbon nanotube As the semiconductor layer 140, the thin film can be made into a crystal 1〇 has a large carrier mobility, thereby increasing the response speed of the thin film transistor. In the embodiment of the technical solution, the carrier mobility of the thin film transistor is higher than 1〇© cm V s 1 The switching current ratio is 1χ1〇2~1χ1〇7. Preferably, the carrier mobility of the thin film transistor 10 is 1〇15±cm2v-is-i. Referring to FIG. 5, the second aspect of the present technology The embodiment provides a thin film transistor 2A using a method similar to that of the first embodiment. The thin film transistor 2 is a bottom gate type, which includes a gate 220, an insulating layer 230, a semiconductor layer 240, a source 251, and A thin film 252 ′′, the thin film transistor 2 〇 is disposed on the surface of an insulating substrate 210. The structure of the thin film transistor 20 of the second embodiment of the present technology is substantially the same as that of the thin film transistor 1 ,, the difference is the second real The thin film transistor 20 is a bottom gate type. The gate 220 is disposed on the surface of the insulating substrate 21, the insulating layer 230 is disposed on the surface of the gate 220, and the semiconductor layer 240 is disposed on the surface of the insulating layer 230. The insulating layer 230 is disposed on the gate 220 and the semiconductor layer 240 The source 251 and the drain 252 are spaced apart from each other on the surface of the semiconductor layer 240 and electrically connected through the semiconductor layer 24; the semiconductor layer 240 is formed in a region between the source 251 and the drain 252. A channel 256. Preferably, the gate 220 is disposed on the surface of the insulating substrate 210 corresponding to the channel 256 between the source 251 and the drain 14 200950096 252, and the gate 220 passes through the insulating layer 230 and the source 251. The gate electrode 252 and the semiconductor layer 240 are electrically insulated. The material of the gate electrode 220, the source electrode 251, the drain electrode 252 and the insulating layer 230 in the thin film transistor 20 provided in the second embodiment of the present invention is the same as the film in the first embodiment. The gate 120, the source 151, the drain 152, and the insulating layer 130 of the transistor are made of the same material. In the thin film transistor 20 provided in the second embodiment, the shape and area of the channel 256 and the semiconductor layer 240 are the same as those of the channel 156 and the semiconductor layer 240 of the thin film transistor 1 in the first embodiment. The source 251 and the drain 252 may be disposed on the upper surface of the semiconductor layer 240. In this case, the source 251, the gate 252 and the gate 220 are disposed on different surfaces of the semiconductor layer 240, and the semiconductor layer 240 is disposed on the source 251. Between the drain 252 and the gate 220, an inversely staggered thin film transistor is formed. Alternatively, the source 251 and the drain 252 may be disposed between the lower surface of the semiconductor layer 240 and the insulating layer 130. At this time, the source 251, the drain a% ❹ and the gate 220 are disposed on the semiconductor layer 140. On the same side, a thin film transistor with an inverse coplanar structure is formed. Compared with the prior art, the thin carbon nanotubes using at least two overlapping carbon nanotube films as the semiconductor layer provided by the embodiments of the present technical solution have the following advantages: - using at least two layers of overlapping nanometers The carbon nanotube film is used as a semiconductor layer, and the carbon nanotubes in each of the carbon nanotube films are arranged end to end, and at least the carbon nanotube film in the semiconductor layer is connected end to end along the thin film transistor The source is arranged in the direction of the drain, the carrier moves axially along the carbon nanotube, and the movement from the source to the pole has 15 200950096 'shorter path' so that the thin film transistor has a large carrier movement. * Rate and faster response speed. The second 'in the carbon nanotube layer composed of at least two carbon nanotubes arranged in an overlapping orientation, at least two carbon nanotube films are disposed at the same time as the end of the carbon nanotubes in each nano carbon tube film The semiconductor layer formed by the cross-set carbon nanotube film has better flexibility and can be applied to manufacture a film transistor with higher flexibility. Third, since the semiconductor layer composed of the carbon nanotube film is more resistant to high temperatures than other semiconductor materials, the thin film transistor and the semiconductor device using the thin film transistor can operate at a higher temperature. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application in this case. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the present invention are intended to be included in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view showing a TFT of a first embodiment of the present technical solution. Fig. 2 is a scanning electron micrograph of a carbon nanotube film as a semiconductor layer in the TFT of the first embodiment of the present technical solution. Fig. 3 is a scanning electron micrograph of a two-layered carbon nanotube film disposed in a TFT of the first embodiment of the present technical solution. FIG. 4 is a schematic view showing the structure of a thin film transistor in the first embodiment of the present technical solution. FIG. 5 is a cross-sectional structural diagram of a TFT according to a second embodiment of the present technical solution. 16 200950096 FIG. [Main component symbol description] Insulating substrate 110, 210 Gate 120, 220 Insulation 130, 230 Semiconductor layer 140, 240 Source 151, 251 Bottom 152, 252 © Channel 156, 256 17