200950095 •九、發明說明： •【發明所屬之技術領域】 本發明涉及一種薄膜電晶體，尤其涉及一種基於奈米 碳管的薄膜電晶體。 【先前技術】 薄膜電晶體（Thin Film Transistor，TFT )係現代微電 子技術中的一種關鍵性電子元件，目前已經被廣泛的應用 於平板顯示器等領域。薄膜電晶體主要包括基板，以及設 ❹置於基板上的閘極、絕緣層、半導體層、源極和汲極。其 中，閘極通過絕緣層與半導體層間隔設置，源極和汲極間 隔設置並與半導體層電連接。薄膜電晶體中的閘極、源極、 汲極均為導電材料構成，該導電材料一般為金屬或合金。 當於閘極上施加電壓時，與閘極通過絕緣層間隔設置的半 導體層中會積累載子，當載子積累到一定程度，與半導體 層電連接的源極汲極之間將導通，從而有電流從源極流向 汲極。當該薄膜電晶體應用於半導體電子器件時，閘極連 接控制電路，汲極連接相應的被控制元件，如液晶顯示器 中的圖元電極，通過薄膜電晶體可以控制該元件的工作。 先前技術中，薄膜電晶體中形成半導體層的材料為非 晶矽、多晶矽或有機半導體聚合物等（R. Ε· I. Schropp，B. Stannowski, J. K. Rath, New challenges in thin film transistor research, Journal of Non-Crystalline Solids, 299-302, 1304-1310 (2002))。以非晶矽作為半導體層的非 晶矽TFT的製造技術較為成熟，但非晶矽TFT中，由於半 200950095 -導體層中通常含有大量的懸掛鍵，使得載子的移動率很低 (一般小於1 )，從而使TFT的響應速度也較慢。 以多晶石夕作為半導體層的TFT相對於以#晶石夕作為半導體 層2的TFT ’具有較高的載子移動率（一般約為1〇 cm V s )’因此響應速度也較快。但多晶石夕TFT低溫製 造成本較高，方法較複雜，大面積製造困難，且多晶矽tft 的關態電流較大。相較于傳統的無機TFT，採用有機半導 體複合物做半導體層的㈣TFT具有成本低、製造溫产低 ©的優點，且有機TFT具有較高的柔勤性。但由於有機半導 體於常溫下多為跳躍式傳導，表現出較高的電阻率、較低 的載子移動率⑷cmw)，使得有機TFT的響應速1 初暢。 奈米碳管具有優異的力學及電學性能。並且， 米碳管螺旋方式的變化，奈米碳管可呈現出金屬性^ 體性。半導體性的奈米碳管具有較高的載子移動率（ ❹可達1_〜1500)，係製造電晶體的理想材料。先 前技術中-般採用喷墨法形成無序的奈米碳管層作為 體層j採用直接生長奈米碳管陣列法形成半導體層。 先前技術中採用直接生長奈米碳管陣列作 二 ==具有以下缺點I第-，於半導體層中= 碳&的排列方向垂直於基底，奈米碳管的排列方向非沿源 =沒Ϊ的方向，從而無法有效應用奈来碳管軸嚮導電的 優勢；第二’採用直接生長奈米碳管陣列作為半導體： 由於奈米碳管垂直生長於基底表面，奈米碳管陣列中二奈 200950095 米碳管管壁之間靠結合不夠 較差，不利於製造柔性薄膜電晶體㈣+導體層的柔勃性 先前技術中採用噴黑形# 體層的薄膜電晶體，其;===做為半導 有少量奈米碳管沿源極到沒極排列，半導“中 石源極収極时效路徑較長，載子料率較低·另夕^ ❹ ❾ r:序的奈米碳管層中奈米碳管之間通過枯劑： 合’因此，該奈米碳管層為—較為鬆散結 不利於製造柔性薄膜電晶體。 靭’差 =之’先前技術中採用奈米碳f作為何體層的薄膜 由於其半導體層中的奈米碳管排列方向限制了由 源極到汲極方向的載子移動率，無法充分發揮奈米碳管載 :移動率高的優勢’使得先前技術中採用奈米碳管作 導體層的薄膜電晶體響應速度低；料，先前技術中採用 奈米碳管作為半導體層的薄膜電晶體，由於其半導體層中 的奈米碳管之間的結合性不好導致該半導體層論性差， 不利於製造柔性薄膜電晶體。 有蓉於此’《供-種具有較高的载子移動率，較高的 響應速度’又具有較好的柔祕的薄膜電晶體實為必要。 【發明内容】 一種薄膜電晶體’其包括：一源極；一與該源極間隔 設置的汲極；一半導體層，該半導體層與該源極和汲極電 連接，以及一閘極，該閘極通過一絕緣層與該半導體層、 源極及汲極及絕緣設置；其中’所述半導體層包括一奈米 200950095 -碳官薄膜，該奈米碳管薄膜包含複數個首尾相連且擇優取 向排列的奈米碳管，至少部分奈米碳管的排列方向沿源極 向沒極延伸。 與先前技術相比較，本技術方案實施例提供的採用一 個奈米碳管薄膜作為半導體層的薄膜電晶體具有以下優 點：其一，由於奈米碳管具有優異的半導體性，則由擇優 取向排列的奈米碳管組成的奈米碳管薄膜具有均勻的半導 體性。並且，由於該半導體層中奈米碳管首尾相連，且至 ©少部分奈米碳管沿源極到汲極方向排列，因而，採用該奈 米碳管薄臈作為半導體層，可以發揮奈米碳管軸嚮導電的 優勢，使得沿源極到汲極具有較短的導電路徑，使得該薄 膜電晶體具有較大的載子移動率和較快響應速度。其二， 由首尾相連且擇優取向排列的奈米碳管組成的奈米碳管薄 膜具有較好的柔韌性及機械強度，故採用該奈米碳管薄膜 作為半導體層，可以應用於柔性的薄膜電晶體。 【實施方式】 ❹ 以下將結合附圖詳細說明本技術方案實施例提供的薄 膜電晶體。 請參閱圖1，本技術方案第一實施例提供一種薄膜電 晶體1〇,該薄膜電晶體1〇為頂閘型，其包括一閘極12〇、 一絕緣層130、一半導體層140、一源極151以及一汲極 152，並且，該薄膜電晶體1〇設置於一絕緣基板11〇上。 所述半導體層140設置於該絕緣基板11〇表面；所述 源極151及汲極152間隔設置於所述半導體層14〇表面並 200950095 - 與該半導體層140電連接，且位於該源極151及汲極152 •之間的半導體層形成一通道156 ;所述絕緣層130設置於 該半導體層140表面；所述閘極120設置於絕緣層130表 面，並通過該絕緣層130與源極151、汲極152及半導體 層140電絕緣，所述絕緣層130設置於閘極120與半導體 層140之間。優選地，該閘極120可以對應通道156設置 於所述絕緣層130表面。 可以理解，所述源極151及汲極152可以間隔設置於 ❹該半導體層140的上表面位於絕緣層130與半導體層140 之間，此時，源極151、汲極152與閘極120設置於半導 體層140的同一面，形成一共面型薄膜電晶體。或者，所 述源極151及汲極152可以間隔設置於該半導體層140的 下表面，位於絕緣基板110與半導體層140之間，此時， 源極151、汲極152與閘極120設置於半導體層140的不 同面，半導體層140設置於源極151、汲極152與閘極120 之間，形成一交錯型薄膜電晶體。 可以理解，根據具體的形成工藝不同，所述絕緣層130 不必完全覆蓋所述源極151、汲極152及半導體層140，只 要能確保半導體層140與相對設置的閘極120與半導體層 140、源極151、汲極152絕緣即可。如，當所述源極151 及汲極152設置於半導體層140上表面時，所述絕緣層130 可僅設置於源極151及汲極152之間，只覆蓋於半導體層 140之上。 所述絕緣基板110起支撐作用，該絕緣基板110材料 200950095 不限，可選擇為玻璃、石英、陶瓷、金剛石等硬性材料或 •塑膠、樹脂等柔性材料。本實施例中，所述絕緣基板11〇 的材料為玻璃。所述絕緣基板110用於對薄膜電晶體1〇 提供支撐，且複數個薄膜電晶體10可按照預定規律或圖形 集成於同一絕緣基板110上，形成薄膜電晶體面板或其 他薄膜電晶體半導體器件。 ^ *該半導體層140包括一個奈米碳管薄膜，該奈米碳管 薄膜包含複數個首尾相連且擇優取向排列的半導體性的奈 〇米碳管’至少部分奈米碳管的排列方向沿源極i5i向没極 152延伸。優選地’該奈米碳管薄膜中的奈米碳管均沿從 源極151指向汲極152的方向排列。 請參閱圖2,該奈米碳管薄膜為從超順排奈米碳管陣 列中直接拉取獲得，該奈米碳管薄膜進一步包括複數個首 尾相連的奈米碳管束片段，每個奈米碳管束片段具有大致 相等的長度且每個奈来碳管束片段由複數個相互平行的齐 ❹米碳管束構成，奈米碳管束片段兩端通過凡德瓦爾力相: 連接。由於奈米碳管具有軸嚮導電特性，該直接拉伸獲得 的擇優取向排列的奈来碳管薄膜於奈米碳管的排列方向比 無序的奈米碳管薄膜具有更高的載子移動率。該奈米碳管 ^的厚度為0.5奈米〜⑽微米。奈米碳管薄財的奈米 碳，可以係單壁奈米碳管或雙壁奈米碳管。所述單壁奈米 ，官的直控為0.5奈米〜5〇奈米；所述雙壁奈米碳管的直200950095 • Nine, invention description: • Technical field to which the invention pertains The present invention relates to a thin film transistor, and more particularly to a thin film transistor based on a carbon nanotube. [Prior Art] Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology and has been widely used in the field of flat panel displays. The thin film transistor mainly includes a substrate, and a gate, an insulating layer, a semiconductor layer, a source, and a drain which are disposed on the substrate. The gate is spaced apart from the semiconductor layer by an insulating layer, and the source and the drain are spaced apart from each other and electrically connected to the semiconductor layer. The gate, the source and the drain of the thin film transistor are all made of a conductive material, and the conductive material is generally a metal or an alloy. When a voltage is applied to the gate, carriers are accumulated in the semiconductor layer spaced apart from the gate through the insulating layer, and when the carrier is accumulated to a certain extent, the source drain connected to the semiconductor layer is turned on, thereby Current flows from the source to the drain. When the thin film transistor is applied to a semiconductor electronic device, the gate is connected to the control circuit, and the drain is connected to a corresponding controlled element, such as a picture element electrode in the liquid crystal display, and the operation of the element can be controlled by the thin film transistor. In the prior art, a material for forming a semiconductor layer in a thin film transistor is an amorphous germanium, a polycrystalline germanium or an organic semiconductor polymer (R. I·I. Schropp, B. Stannowski, JK Rath, New challenges in thin film transistor research, Journal Of Non-Crystalline Solids, 299-302, 1304-1310 (2002)). The fabrication technique of amorphous germanium TFT with amorphous germanium as the semiconductor layer is relatively mature, but in the amorphous germanium TFT, since the semi-200950095-conductor layer usually contains a large number of dangling bonds, the mobility of the carrier is very low (generally smaller than 1), so that the response speed of the TFT is also slow. The TFT having the polycrystalline as the semiconductor layer has a higher carrier mobility (generally about 1 〇 cm V s ) with respect to the TFT ‘ as the semiconductor layer 2, so the response speed is also faster. However, the low temperature system of polycrystalline slab TFT is higher, the method is more complicated, the manufacturing of large area is difficult, and the off-state current of polycrystalline 矽tft is larger. Compared with the conventional inorganic TFT, the (tetra) TFT using the organic semiconductor composite as the semiconductor layer has the advantages of low cost, low manufacturing temperature and low yield, and the organic TFT has high flexibility. However, since the organic semiconductor is mostly skipped at normal temperature, it exhibits a high resistivity and a low carrier mobility (4) cmw, so that the response speed of the organic TFT is initially smooth. Nano carbon tubes have excellent mechanical and electrical properties. Moreover, the change in the spiral mode of the carbon nanotubes, the carbon nanotubes can exhibit metallic properties. Semiconducting carbon nanotubes have a high carrier mobility (❹1~~1500) and are ideal materials for making transistors. In the prior art, an ink jet method is used to form a disordered carbon nanotube layer as a bulk layer. A semiconductor layer is formed by a direct growth carbon nanotube array method. In the prior art, the direct growth carbon nanotube array is used as the second == has the following disadvantages I - in the semiconductor layer = the arrangement direction of carbon & is perpendicular to the substrate, and the arrangement direction of the carbon nanotubes is not along the source = no The direction of the inability to effectively apply the advantages of the axial conduction of the carbon nanotubes; the second 'using a direct growth carbon nanotube array as a semiconductor: Since the carbon nanotubes grow vertically on the surface of the substrate, the carbon nanotube array is in the second layer. 200950095 The surface of the carbon tube wall is not well combined, which is not conducive to the manufacture of flexible film transistor (4) + the flexibility of the conductor layer. In the prior art, a thin film transistor with a black layer is used, which is === A small number of carbon nanotubes are arranged along the source to the immersed pole. The semi-conductive "middle stone source has a longer aging aging path and a lower carrier material rate. Another eve ^ ❹ : r: the order of the carbon nanotube layer The carbon nanotubes pass through the slag: "Therefore, the carbon nanotube layer is - looser junction is not conducive to the manufacture of flexible thin film transistors. Tough's poor = 'the prior art uses nanocarbon f as the body layer Thin film due to nanocarbon in its semiconductor layer The arrangement direction limits the carrier mobility from the source to the drain, and does not fully exploit the advantages of the carbon nanotube loading: high mobility, which makes the response speed of the thin film transistor using the carbon nanotube as the conductor layer in the prior art. Low; material, a thin film transistor using a carbon nanotube as a semiconductor layer in the prior art, the semiconductor layer is poorly bonded due to poor bonding between the carbon nanotubes in the semiconductor layer, which is disadvantageous for manufacturing a flexible thin film. Crystal. It is necessary to have a thin film transistor with a good carrier mobility and a high response speed, and it has a good flexibility. [Summary] A thin film transistor The method includes: a source; a drain spaced from the source; a semiconductor layer electrically connected to the source and the drain, and a gate through the insulating layer and the semiconductor a layer, a source and a drain and an insulating arrangement; wherein the semiconductor layer comprises a nanometer 200950095 - carbon official film, the carbon nanotube film comprising a plurality of nanocarbons connected end to end and preferentially oriented The arrangement direction of at least a portion of the carbon nanotubes extends along the source pole. The thin film transistor using the carbon nanotube film as the semiconductor layer provided by the embodiment of the present technical solution has the following advantages: First, since the carbon nanotubes have excellent semiconductivity, the carbon nanotube film composed of the preferred orientation of the carbon nanotubes has uniform semiconductivity, and since the carbon nanotubes in the semiconductor layer are connected end to end, And © a small number of carbon nanotubes are arranged along the source to the drain. Therefore, the use of the carbon nanotube thin layer as a semiconductor layer can take advantage of the axial conduction of the carbon nanotubes, so that the source is to the source. The electrode has a short conductive path, so that the thin film transistor has a large carrier mobility and a fast response speed. Second, a carbon nanotube film composed of a carbon nanotube composed of end-to-end and preferential orientations has a carbon nanotube film. The flexibility and mechanical strength are good, so the carbon nanotube film is used as a semiconductor layer, and can be applied to a flexible thin film transistor. [Embodiment] The thin film transistor provided by the embodiment of the present technical solution will be described in detail below with reference to the accompanying drawings. Referring to FIG. 1 , a first embodiment of the present invention provides a thin film transistor 1 , which is a top gate type, including a gate 12 , an insulating layer 130 , a semiconductor layer 140 , and a semiconductor transistor The source electrode 151 and the drain electrode 152 are disposed on the insulating substrate 11A. The semiconductor layer 140 is disposed on the surface of the insulating substrate 11; the source 151 and the drain 152 are spaced apart from the surface of the semiconductor layer 14 and are electrically connected to the semiconductor layer 140 and located at the source 151. The semiconductor layer between the drain and the drain 152 is formed with a channel 156. The insulating layer 130 is disposed on the surface of the semiconductor layer 140. The gate 120 is disposed on the surface of the insulating layer 130 and passes through the insulating layer 130 and the source 151. The drain 152 and the semiconductor layer 140 are electrically insulated, and the insulating layer 130 is disposed between the gate 120 and the semiconductor layer 140. Preferably, the gate 120 may be disposed on the surface of the insulating layer 130 corresponding to the channel 156. It can be understood that the source 151 and the drain 152 may be disposed at intervals on the upper surface of the semiconductor layer 140 between the insulating layer 130 and the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed. On the same side of the semiconductor layer 140, a coplanar thin film transistor is formed. Alternatively, the source 151 and the drain 152 may be disposed on the lower surface of the semiconductor layer 140 between the insulating substrate 110 and the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed on Different sides of the semiconductor layer 140, the semiconductor layer 140 is disposed between the source 151, the drain 152 and the gate 120 to form a staggered thin film transistor. It can be understood that the insulating layer 130 does not need to completely cover the source 151, the drain 152 and the semiconductor layer 140, as long as the semiconductor layer 140 and the oppositely disposed gate 120 and the semiconductor layer 140 are ensured, The source 151 and the drain 152 may be insulated. For example, when the source 151 and the drain 152 are disposed on the upper surface of the semiconductor layer 140, the insulating layer 130 may be disposed only between the source 151 and the drain 152 to cover only the semiconductor layer 140. The insulating substrate 110 serves as a support. The insulating substrate 110 material is not limited to 200950095, and may be selected from a hard material such as glass, quartz, ceramic, diamond, or a flexible material such as plastic or resin. In this embodiment, the material of the insulating substrate 11 is glass. The insulating substrate 110 is used to provide support for the thin film transistor 1 , and the plurality of thin film transistors 10 can be integrated on the same insulating substrate 110 according to a predetermined pattern or pattern to form a thin film transistor panel or other thin film transistor semiconductor device. ^ * The semiconductor layer 140 comprises a carbon nanotube film comprising a plurality of semi-conducting and preferentially oriented semiconducting carbon nanotubes. At least a portion of the carbon nanotubes are arranged along the source. The pole i5i extends toward the poleless 152. Preferably, the carbon nanotubes in the carbon nanotube film are arranged in a direction from the source 151 to the drain 152. Referring to FIG. 2, the carbon nanotube film is directly drawn from the super-sequential carbon nanotube array, and the carbon nanotube film further comprises a plurality of end-to-end carbon nanotube bundle segments, each nanometer. The carbon tube bundle segments have substantially equal lengths and each of the carbon nanotube bundle segments is composed of a plurality of mutually parallel Qiqimian carbon tube bundles, and the carbon nanotube bundle segments are connected at both ends by a van der Waals force phase: Since the carbon nanotubes have axial conductivity characteristics, the preferred orientation of the carbon nanotube film obtained by direct stretching has a higher carrier movement in the arrangement direction of the carbon nanotubes than the disordered carbon nanotube film. rate. The carbon nanotubes have a thickness of from 0.5 nm to (10) microns. The carbon carbon of the carbon nanotubes can be a single-walled carbon nanotube or a double-walled carbon nanotube. The single-walled nanometer, the direct control of the official is 0.5 nm to 5 〇 nanometer; the double-walled carbon nanotube is straight
徑為1.0奈米〜5〇奈米。優選地，所述奈米碳管 於10奈米。 J 11 200950095 /所述半導體層140的長度為1微米〜1〇〇微米，寬度為 1微米〜1毫米，厚度為〇·5奈米〜100微米。所述通道156 的長度為1微米〜100微米，寬度為丄微米〜χ毫米。本技 術方案實施例中，所述半導體層14〇的長度為5〇微米，寬 度為300微米，厚度為5奈米。所述通道的長度為4〇微米， 寬度為300微米。該半導體層14〇包括沿源極151至及極 152方向設置的！層奈米碳管薄膜1奈米碳管薄膜的厚 度為5奈米。 本實施例中，源極151、汲極152及閘極12〇為一導 電薄膜。該導電薄膜的材料可以為金屬、合金、銦錫氧化 物（ιτο)、錄錫氧化物（ΑΤ〇)、㈣銀膠、_電聚合物以 及導電奈米碳管等。該金屬或合金材料可以為鋁、銅、鎢、 钥、金、鎚、把或其合金。優選地，該間極12〇的面積與 所述通道156的面積相#，㈣時有利於通道156積累載 子’閘極120的厚度為0.5奈米〜1〇〇微米。本實施例中， 所述閘極120的材料為金屬，厚度為5奈米。所述源極 151、汲極152的材料為金屬铯，所述金屬鉋與奈来碳管具 有較好的潤濕效果，厚度為5奈米。 ^ 、所述絕緣層13G材料為氮切、氧切等硬性材料或 苯並環丁烯（BCB)、聚S旨或丙烯酸樹料柔性材料。該絕 緣層㈣的厚度為0.5奈㈣⑼微米。本實施例中，所述 絕緣層130的材料為氮化矽。 請參見圖3,本技術方案第—實施例的薄膜電晶體1〇 使用時，於閘極m上施一電屢Vg，將源極151接地，並 12 200950095 ο •於汲極152上施加一電壓Vds，閘極電壓Vg於半導體層14〇 .的通道156中產生電場，並於通道156表面處產生載子。 隨著閘極電壓Vg的增加，通道156轉變為載子積累層，當 Vg達到源極151和汲極152之間的開啟電壓時，源極151 與沒極152之間的通道156導通，從而會於源極ι5ι和沒 極152之間產生電流，電流由源極151通過通道156流向 154,從而使得該薄膜電晶體1〇處於開啟狀態。由於所述 奈米碳官薄膜中僅包括半導體性的奈米碳管，而半導體性 的奈米碳管具有較高的載子移動率，且該半導體層14〇中 的奈米碳管首尾相連沿源極151到汲極152的方向排列， 而奈米碳管軸向的導電性較徑向強，故載子由源極ΐ5ι經 半導體層140至汲極152方向傳輸具有較短的傳輸路徑’ 所以由所述奈米碳管組成的奈米碳管薄膜作為半導體層 140,可以使所述薄膜電晶體1〇具有較大的載子移動率， 進而提高薄膜電晶體10的響應速度。 ❹ 由於本技術方案實施例半導體層140中的奈米碳管具 有較好的半導體性，奈米碳管薄膜中的奈米碳管 ς 極151至祕152的方向排列，故載子於具有較好轴向傳、 輸性能的奈米碳管中具有較高的載子移動率，故由所述奈 米碳管組成的奈米碳管薄膜作為半導體層14〇,可以使= 述薄膜電晶體1G具有較大的載子移動率，進而提高薄 晶體1〇的響應速度。本技術方案實施射，所述薄膜電晶 體1:的載子移動率高於10 cm2V-V。開關電流比:曰 lxioMxiG7。優選地，所述薄膜電晶體1G的載子移動率 13 200950095 •為 10〜1500 cm2V_1s_1。 . 請參閱圖4，本技術方案第二實施例採用與第一實施 例相似的方法提供一種薄膜電晶體20，該薄膜電晶體20 為底閘型，該薄膜電晶體20包括一閘極220、絕緣層230 一半導體層240、一源極252及一汲極252，並且，該薄膜 電晶體20設置於一絕緣基板210表面。本技術方案第二實 施例薄膜電晶體20的結構與薄膜電晶體10基本相同，其 區別在於第二實施例薄膜電晶體20為底閘型。 ❹ 所述閘極220設置於該絕緣基板210表面，所述絕緣 層230設置於閘極220表面，所述半導體層240設置於該 絕緣層230表面，所述絕緣層230設置於閘極220與半導 體層240之間；所述源極252、汲極252間隔設置於該半 導體層240表面，並通過該半導體層240電連接；所述半 導體層240位於所述源極251和汲極252之間的區域形成 一通道256。優選地，該閘極220可以與源極252、汲極 252之間的通道256對應設置於絕緣基板210表面，且該 W閘極220通過該絕緣層230與源極252、汲極252及半導 體層240電絕緣。本技術方案第二實施例提供的薄膜電晶 體20中，閘極220、源極252、汲極252及絕緣層230的 材料與第一實施例中薄膜電晶體10的閘極120、源極151、 汲極152及絕緣層130的材料相同。第二實施例提供的薄 膜電晶體20中，通道256、半導體層240的形狀、面積與 第一實施例中薄膜電晶體10的通道156、半導體層240的 形狀、面積相同。 14 200950095 • 所述源極252及汲極252可以設置於該半導體層240 .上表面，此時，源極252、汲極252與閘極220設置於半 導體層240的不同面，半導體層24〇設置於源極252、汲 極252與閘極220之間，形成一逆交錯結構的薄膜電晶體。 或者，所述源極252及汲極252也可以設置於該半導體層 240下表面與絕緣層13〇之間，此時，源極252、汲極252 與閘極220設置於半導體層14〇的同一面，形成一逆共面 結構的薄膜電晶體。 ❹ 與先前技術相比較’本技術方案實施例提供的採用一 奈米碳管薄膜作為半導體層的薄膜電晶體具有以下優點： 其一’由於奈米碳管具有優異的半導體性，則由定向排列 的奈米碳管組成的奈米峻管薄膜具有均勻的半導體性。並 且，由於奈米碳管首尾相連，且從源極連接至汲極，載子 沿奈米碳管轴向運動，從源極向汲極運動具有較短的路 徑，因而，採用奈米碳管薄膜作為半導體層，可以使薄臈 ❹電晶體具有較大的載子移動率較快響應速度。其二，由於 奈米碳管具有優異的力學性能，則由定向排列的奈米碳管 組成的奈米碳管薄膜具有較好的柔韌性及機械強度，故採 7該奈米碳管薄膜作為半導體層，可以應用於柔性薄膜電 阳體。其二，由於碳奈米米管薄膜組成的半導體層較其他 半導體材料更耐高溫，因此，該薄膜電晶體可以於較高溫 度下工作。 β综上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟’以上所述者僅為本發明之較佳實施例， 15 200950095 ’自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝 *之人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本技術方案第一實施例薄膜電晶體的剖視結構 示意圖。 圖2係本技術方案第一實施例薄膜電晶體中奈米碳管 薄膜的掃描電鏡照片。 © 圖3係本技術方案第一實施例薄膜電晶體工作時的結 構示意圖。 圖4係本技術方案第二實施例薄膜電晶體的剖視結構 示意圖。 【主要元件符號說明】 絕緣基板 110 ， 210 閘極 120 ， 220 絕緣層 130 ， 230 ❹半導體層 140 ， 240 源極 151 ， 251 汲極 152 ， 252 通道 156 ， 256 16The diameter is 1.0 nm ~ 5 〇 nanometer. Preferably, the carbon nanotubes are at 10 nm. J 11 200950095 / The semiconductor layer 140 has a length of 1 μm to 1 μm, a width of 1 μm to 1 mm, and a thickness of 〇·5 nm to 100 μm. The channel 156 has a length of 1 micrometer to 100 micrometers and a width of 丄 micrometers to χ millimeters. In the embodiment of the technical solution, the semiconductor layer 14 has a length of 5 μm, a width of 300 μm, and a thickness of 5 nm. The channel has a length of 4 μm and a width of 300 μm. The semiconductor layer 14 includes electrodes 151 to 152 in the direction of the source! The layer of the carbon nanotube film 1 carbon nanotube film has a thickness of 5 nm. In this embodiment, the source 151, the drain 152 and the gate 12 are a conductive film. The material of the conductive film may be a metal, an alloy, an indium tin oxide (ITO), a tin oxide (yttrium), a (iv) silver paste, an electropolymer, and a conductive carbon nanotube. The metal or alloy material may be aluminum, copper, tungsten, molybdenum, gold, hammer, or alloys thereof. Preferably, the area of the interpole 12〇 is opposite to the area of the channel 156, and (4) is advantageous for the channel 156 to accumulate the carrier. The thickness of the gate 120 is 0.5 nm to 1 μm. In this embodiment, the material of the gate 120 is metal and has a thickness of 5 nm. The material of the source electrode 151 and the drain electrode 152 is a metal crucible, and the metal planer and the carbon nanotube have a good wetting effect and have a thickness of 5 nm. ^, the insulating layer 13G material is a hard material such as nitrogen cutting or oxygen cutting or benzocyclobutene (BCB), polystyrene or acrylic tree flexible material. The thickness of the insulating layer (4) is 0.5 nanometers (four) (9) micrometers. In this embodiment, the material of the insulating layer 130 is tantalum nitride. Referring to FIG. 3, when the thin film transistor of the first embodiment of the present invention is used, an electric Vg is applied to the gate m, the source 151 is grounded, and 12200950095 is applied to the drain 152. The voltage Vds, the gate voltage Vg, generates an electric field in the channel 156 of the semiconductor layer 14 and generates a carrier at the surface of the channel 156. As the gate voltage Vg increases, the channel 156 transitions to a carrier accumulation layer, and when Vg reaches the turn-on voltage between the source 151 and the drain 152, the channel 156 between the source 151 and the gate 152 is turned on, thereby A current is generated between the source ι5ι and the gate 152, and the current flows from the source 151 through the channel 156 to the 154, thereby causing the thin film transistor 1 〇 to be turned on. Since the nano carbon official film includes only a semiconducting carbon nanotube, the semiconducting carbon nanotube has a high carrier mobility, and the carbon nanotubes in the semiconductor layer 14 are connected end to end. Arranged in the direction of the source 151 to the drain 152, and the axial conductivity of the carbon nanotube is stronger than that of the radial direction, so that the carrier has a shorter transmission path from the source ΐ5 through the semiconductor layer 140 to the drain 152. Therefore, the carbon nanotube film composed of the carbon nanotubes as the semiconductor layer 140 can make the thin film transistor 1 较大 have a large carrier mobility, thereby increasing the response speed of the thin film transistor 10. ❹ Since the carbon nanotubes in the semiconductor layer 140 of the embodiment of the present technical solution have good semiconductivity, the carbon nanotubes in the carbon nanotube film are arranged in the direction of the 151 to the secret 152, so the carrier is more The carbon nanotubes having a good axial transmission and transmission performance have a high carrier mobility, so that the carbon nanotube film composed of the carbon nanotubes is used as the semiconductor layer 14〇, so that the thin film transistor can be made. 1G has a large carrier mobility, which in turn increases the response speed of thin crystals. According to the technical solution, the carrier mobility of the thin film transistor 1: is higher than 10 cm2V-V. Switching current ratio: 曰 lxioMxiG7. Preferably, the carrier mobility of the thin film transistor 1G is 13 200950095 • 10 to 1500 cm 2 V_1 s_1. Referring to FIG. 4 , a second embodiment of the present invention provides a thin film transistor 20 according to a method similar to that of the first embodiment. The thin film transistor 20 is a bottom gate type, and the thin film transistor 20 includes a gate 220 . The insulating layer 230 includes a semiconductor layer 240, a source 252 and a drain 252, and the thin film transistor 20 is disposed on a surface of the insulating substrate 210. The structure of the thin film transistor 20 of the second embodiment of the present technical solution is substantially the same as that of the thin film transistor 10, except that the thin film transistor 20 of the second embodiment is of the bottom gate type. The gate 220 is disposed on the surface of the insulating substrate 210, the insulating layer 230 is disposed on the surface of the gate 220, the semiconductor layer 240 is disposed on the surface of the insulating layer 230, and the insulating layer 230 is disposed on the gate 220 Between the semiconductor layers 240, the source 252 and the drain 252 are disposed on the surface of the semiconductor layer 240 and electrically connected through the semiconductor layer 240. The semiconductor layer 240 is located between the source 251 and the drain 252. The area forms a channel 256. Preferably, the gate 220 is disposed on the surface of the insulating substrate 210 corresponding to the channel 256 between the source 252 and the drain 252, and the W gate 220 passes through the insulating layer 230 and the source 252, the drain 252, and the semiconductor. Layer 240 is electrically insulated. In the thin film transistor 20 provided by the second embodiment of the present invention, the material of the gate 220, the source 252, the drain 252 and the insulating layer 230 is the same as the gate 120 and the source 151 of the thin film transistor 10 in the first embodiment. The materials of the drain 152 and the insulating layer 130 are the same. In the thin film transistor 20 provided in the second embodiment, the shape and area of the channel 256 and the semiconductor layer 240 are the same as those of the channel 156 and the semiconductor layer 240 of the thin film transistor 10 in the first embodiment. 14 200950095 • The source 252 and the drain 252 may be disposed on the upper surface of the semiconductor layer 240. At this time, the source 252, the drain 252 and the gate 220 are disposed on different sides of the semiconductor layer 240, and the semiconductor layer 24〇 The source 252, the drain 252 and the gate 220 are disposed to form an inversely staggered thin film transistor. Alternatively, the source 252 and the drain 252 may be disposed between the lower surface of the semiconductor layer 240 and the insulating layer 13A. At this time, the source 252, the drain 252 and the gate 220 are disposed on the semiconductor layer 14 On the same side, a thin film transistor with an inverse coplanar structure is formed.薄膜 Compared with the prior art, the thin film transistor using a carbon nanotube film as a semiconductor layer provided by the embodiment of the present technical solution has the following advantages: It is arranged by orientation because of the excellent semiconductivity of the carbon nanotubes. The nanotube film composed of the carbon nanotubes has uniform semiconductivity. Moreover, since the carbon nanotubes are connected end to end and connected from the source to the drain, the carriers move axially along the carbon nanotubes, and have a shorter path from the source to the drain. Therefore, the carbon nanotubes are used. As a semiconductor layer, the thin film can make the thin germanium transistor have a large carrier mobility and a fast response speed. Second, because of the excellent mechanical properties of the carbon nanotubes, the carbon nanotube film consisting of aligned carbon nanotubes has good flexibility and mechanical strength, so the carbon nanotube film is used as the carbon nanotube film. The semiconductor layer can be applied to a flexible film electrical anode. Second, since the semiconductor layer composed of the carbon nanotube film is more resistant to high temperatures than other semiconductor materials, the thin film transistor can operate at a higher temperature. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and 15 200950095 'supplied to limit the scope of the patent application in this case. Equivalent modifications or variations made by those skilled in the art of the present invention in accordance with the spirit of the present invention are intended to be within the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view showing a thin film transistor of a first embodiment of the present technical solution. Fig. 2 is a scanning electron micrograph of a carbon nanotube film in a thin film transistor of the first embodiment of the present technical solution. Fig. 3 is a schematic view showing the structure of the thin film transistor of the first embodiment of the present technical solution. Fig. 4 is a cross-sectional view showing the structure of a thin film transistor of a second embodiment of the present invention. [Main component symbol description] Insulating substrate 110, 210 Gate 120, 220 Insulation layer 130, 230 ❹ Semiconductor layer 140, 240 Source 151, 251 Bungee 152, 252 channel 156, 256 16