1377680 101年01月.31日梭正替换頁 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種薄膜電晶體，尤其涉及一種基於奈米碳 管的薄膜電晶體。 【先前技術】 [0002] 薄膜電晶體（Thin F i lm Trans i stor，TFT )係現代 微電子技術中的一種關鍵性電子元件，目前已經被廣泛 的應用於平板顯示器等領域。薄膜電晶體主要包括閘極 、絕緣層、半導體層、源極和汲極。其中，源極和汲極 間隔設置並與半導體層電連接，閘極通過絕緣層與半導 體層及源極和汲極間隔絕緣設置。所述半導體層位於所 述源極和汲極之間的區域形成一通道區域。薄膜電晶體 中的閘極、源極、汲極均由導電材料構成，該導電材料 一般爲金屬或合金。當於'閘極上施加一電壓時，與閘極. 通過絕緣層間隔設置的半導體層中的通道區域會積累載 流子，當載流子積累到一定程度，與半導體層電連接的 源極與汲極之間將導通，從而有電流從源極流向汲極。 於實際應用中，對薄膜電晶體的要求係希望得到較大的 開關電流比。影響上述開關電流比的因素除薄膜電晶體 的製備工藝外，薄膜電晶體半導體層中半導體材料的載 子移動率爲影響開關電流比的最重要的影響因素之一。 [0003] 先前技術中，薄膜電晶體中形成半導體層的材料爲非晶 矽、多晶矽或有機半導體聚合物等（R. E. I.1377680 The first replacement page of the Japanese version of the present invention. The invention relates to a thin film transistor, and more particularly to a thin film transistor based on a carbon nanotube. [Prior Art] [0002] Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology and has been widely used in flat panel displays and the like. The thin film transistor mainly includes a gate, an insulating layer, a semiconductor layer, a source, and a drain. Wherein, the source and the drain are spaced apart from each other and electrically connected to the semiconductor layer, and the gate is insulated from the semiconductor layer and the source and the drain by an insulating layer. The semiconductor layer is located in a region between the source and the drain to form a channel region. The gate, source and drain of the thin film transistor are each composed of a conductive material, which is typically a metal or an alloy. When a voltage is applied to the gate, the gate region in the semiconductor layer spaced apart by the insulating layer accumulates carriers, and when the carrier accumulates to a certain extent, the source electrically connected to the semiconductor layer The drain will be turned on so that current flows from the source to the drain. In practical applications, the requirements for thin film transistors are expected to result in larger switching current ratios. Factors Affecting the Switching Current Ratio In addition to the preparation process of the thin film transistor, the carrier mobility of the semiconductor material in the thin film transistor layer is one of the most important factors affecting the switching current ratio. [0003] In the prior art, a material for forming a semiconductor layer in a thin film transistor is an amorphous germanium, a polycrystalline germanium or an organic semiconductor polymer (R. E. I.
Schropp, B. Stannowski, J. K. Rath, New challenges in thin film transistor research, 單編號 A0101 第3頁/共20頁 1013033222-0 1377680 101年01月31日核Ϊ5替換頁Schropp, B. Stannowski, J. K. Rath, New challenges in thin film transistor research, single number A0101 Page 3 of 20 1013033222-0 1377680 January 31, 101 Nuclear Replacement 5 Replacement Page
Journal of Non-Crystalline Solids, 299-302, · 1304-131 0 (2002))。以非晶矽作爲半導體層的非晶矽 薄膜電晶體的製造技術較爲成熟’但於非晶矽薄膜電晶 趙中’由於半導體層中通常含有大量的懸掛鍵，使得載 流子的遷移率很低（一般小於lcm2v-is-l )，從而導致 薄膜電晶體的響應速度較慢。以多晶石夕作爲半導體層的 薄膜電晶體相對於以非晶矽作爲半導體層的薄膜電晶體 ’具有較高的載子移動率（一般約爲l〇cm2v-ls-l)，故 響應速度也較快。但多晶矽薄膜電晶體低溫製造成本較 尚，方法較複雜，大面積製造困難，且多晶石夕薄膜電晶 體的關態電流較大》相較於上述傳統的無機薄膜電晶體 ，採用有機半導體聚合物做半導體層的有機薄膜電晶體 具有成本低、製造溫度低的優點，且有機薄膜電晶體具 有較高的柔韌性。但由於有機半導體於常溫下多爲跳躍 式傳導，表現出較高的電阻率 '較低的載子移動率，使 得有機薄膜電晶體的響應速度較慢。 [0004] 奈米碳管具有優異的力學及電學性能◊並且，隨著奈米 碳管螺旋方式的變化，奈米碳管可呈現出金屬性或半導 體性。半導體性的奈米碳管具有較高的載子移動率（一 般可達1 000~ 1 500cm2V ls_1)，係製造晶體管的理想材 料。先前技術中已有報道採用半導體性奈米碳管形成的 奈米碳管層作㈣膜電晶體的半導體層。先前技術中的 奈米碳官層中’奈米破管爲無序排列或垂直於基底排列 ，形成一無序奈米碳管層或一奈米碳管陣列。然而，於 上述無序奈米破管層中，奈米碳管隨機分佈。載流子於 第4頁/共20頁 09Y1191〇f 單编號 Αοιοι 1013033222-0 1377680 101年01月· 31日修正替換頁 上述無序奈米碳管層中的傳導路徑較長，不利於獲得具 有較高載子移動率的薄膜電晶體。另外，上述無序奈米 碳管層爲通過喷墨法形成，奈米碳管層中的奈米碳管之 間通過粘結劑相互結合，故，該奈米碳管層爲一較爲鬆 散結構，柔韌性較差，不利於製造柔性薄膜電晶體。於 上述奈米碳管陣列中，奈米碳管排列方向垂直於基底方 向。由於奈米碳管具有較好的載流子軸向傳輸性能，而 徑向方向的傳輸性能較差，故垂直於基底方向排列的奈 米碳管同樣不利於獲得具有較高載子移動率的薄膜電晶 體。故上述兩種奈米碳管的排列方式均不能有效利用奈 米碳管的高載子移動率。故，先前技術中採用無序奈米 碳管層或奈米碳管陣列作半導體層的薄膜電晶體不利於 獲得具有較高載子移動率及較高的響應速度的薄膜電晶 體，且先前技術中的薄膜電晶體的柔韌性較差。 [0005] 有鑒於此，提供一種具有較高的載子移動率，較高的響 應速度，及較好的柔韌性的薄膜電晶體實為必要。 【發明内容】 [0006] 一種薄膜電晶體，包括一源極、一汲極、一半導體層及 一閘極，該汲極與該源極間隔設置，該半導體層與該源 極和汲極電連接，該閘極通過5絕緣層與該半f體層、 源極及汲極絕緣設置，其中，該半導體層包括至少兩個 沿相同方向重疊的奈米碳管薄膜，每一奈米碳管薄膜包 括多個首尾相連且沿同一方向排列的奈米碳管，且至少 部分奈米碳管的排列方向沿源極至汲極方向延伸。 [0007] 相較於先前技術，本技術方案實施例提供的採用至少兩 09711910#單編號 A〇101 第5頁/共20頁 1013033222-0 1377680 101年01月.31日梭年替换頁 個沿相同方向重疊設置的奈米碳管薄膜作爲半導體層的 · 薄膜電晶體具有以下優點：其一，由於奈米碳管薄膜中 的奈米碳管首尾相連且排列方向沿源極至汲極方向排列 ，故載流子由源極經半導體層至汲極方向傳輸可具有較 短的傳輸路徑，從而有利於獲得具有較大的載子移動率 的薄膜電晶體，進而有利於提高薄膜電晶體的響應速度 。其二，由於採用該至少兩個奈米碳管薄膜重疊設置作 爲半導體層，且每一奈米碳管薄膜中奈米碳管之間通過 凡德瓦爾力首尾相連，則奈米碳管薄膜具有較好的韌性 及機械強度，可以用於製造柔性的薄膜電晶體。 【實施方式】 [0008] 以下將結合附圖詳細說明本技術方案實施例提供的薄膜 電晶體。 [0009] 請參閱圖1，本技術方案第一實施例提供一種薄膜電晶體 10，該薄膜電晶體10爲頂栅型，其包括一半導體層140、 一源極151、一汲極152、一絕緣層130及一閘極120。所 述薄膜電晶體10形成於一絕緣基板110表面。 [0010] 上述半導體層140設置於上述絕緣基板110表面。上述源 極151及汲極152間隔設置於上述半導體層140表面。上 述絕緣層130設置於上述半導體層140表面。上述閘極 120設置於上述絕缘層130表面，並通過該絕緣層130與 該半導體層140及源極151和汲極152絕緣設置。所述半 導體層140位於所述源極151和汲極152之間的區域形成 一通道1 56。 [0011] 所述源極151及汲極152可以間隔設置於所述半導體層 09711910#單编號删1 第 6 頁 / 共 20 頁 1013033222-0 1377680 « *» |7^1 年.01.月.31 日 1 4 0的上表面位於所述絕緣層1 3 〇與半導體層1 4 〇之間， 此時，源極151、沒極152與閘極120設置於半導體層140 的同一側，形成一共面型薄膜電晶體10 «或者，所述源 極151及沒極152可以間隔設置於所述半導體層140的下 表面’此時’源極151、汲極152與閘極120設置於半導 體層140的不同側，位於所述絕緣基板"ο與半導體層 140之間，形成一交錯型薄膜電晶體1〇。可以理解，所述 源極151及汲極152的設置位置不限。只要球保上述源極 151及汲極152間隔設置，並與上述半導體層14〇電連接 ，使半導體層140中至少部分奈米碳管沿源極丨51至汲極 152方向排列即可。 [0012] 所述絕緣基板110起支律作用，其材料可選擇爲玻璃、石 英、陶瓷、金剛石、矽片等硬性材料或塑料 '樹脂等柔 性材料。本實施例中，所述絕緣基板11〇的材料爲玻璃。 所述絕緣基扳110用於對薄膜電晶體10提供支撑。所述絕 緣基杈110也可選用大規模集成電路中的基板，且多個薄 膜電晶體10可按照預定規律或圖形集成於同一絕緣基板 110上’形成薄膜電晶體面板或其它薄膜電晶體半導體器 件。 [0013] 所述半導體層140中包括至少兩個重疊的奈米碳管薄膜， 每一奈米碳管薄膜包括多個擇優取向排列且首尾相連的 半導體性奈米碳管，相鄰的兩個奈米碳管薄膜中的奈米 碳管沿同一方向排列。所述奈米碳管薄膜中至少部分奈 米碳管的排列方向沿源極151至汲極152方向延伸。優選 地，上述奈米碳管薄膜中的奈米碳管的排列方向均沿從 09711910^^^ A〇101 第7頁/共20頁 1013033222-0 1377680 101年01月31日修年替換頁 源極151指向汲極152的方向延伸。相鄰的奈米碳管薄膜 ， 之間通過凡德瓦爾力緊密結合。 [0014] 請參閱圖2，該奈米碳管薄膜進一步包括多個奈米碳管束 片段，每個奈米碳管束片段具有大致相等的長度且每個 奈米碳管束片段由多個相互平行的奈米碳管束構成，奈 米碳管束片段兩端通過凡德瓦爾力相互連接。該奈米碳 管薄膜的長度及寬度不限，可根據實際需求製備。上述 半導體層140中的奈米碳管薄膜的層數不限。該奈米碳管 薄膜的厚度爲0. 5奈米〜1〇〇微米。奈米碳管薄膜中的奈来 碳管可以係單壁奈米碳管或雙壁奈米破管。所述單壁奈 米碳管的直徑爲0.5奈米〜50奈米；所述雙壁奈米碳管的 直徑爲1.0奈米~50奈米。優選地，所述奈米碳管的直徑 小於10奈米。 [0015] 上述半導體層140的長度爲1微米〜1〇〇微米，寬度爲1微 米~1毫米，厚度爲0.5奈米〜1〇〇微米《所述通道156的長 度爲1微米〜100微米，寬度爲丨微米〜丨毫米。本技術方案 實施例中，所述半導體層140的長度爲5〇微米，寬度爲 300微米，厚度爲25奈米。所述通道156的長度爲4〇微米 ，寬度爲300微米。該半導體層ι4〇包括沿源極151至汲 極152方向重疊設置的5層奈米碳管薄膜。每一奈米碳管 薄膜的厚度爲5奈米。 [0016] 所述半導體層中的奈米碳管薄膜可通過從奈米碳管陣列 中直接拉取並進-步處理獲得。該奈米碳管薄膜具有枯 性，可以直接_於絕緣基板11〇表面。具體地根據源 極15〗及汲極152與半導體層14〇設置的相對位置不同， 09711910严編號 1013033222-0 1377680 |101年_01月-31日梭正替换頁飞 可以先於絕緣基板110上粘附奈米碳管薄膜，後將源極 151及汲極152沿奈米碳管薄膜中奈米碳管排列方向形成 於奈米碳管薄膜表面，並使源極151及汲極152間隔設置 ;也可先將源極151及汲極152分別間隔形成於絕緣基板 110表面，再沿源極151至沒極152的方向舖設奈半碳管 薄膜，覆蓋該源極151及沒極152。本技術方案實施例中 ，所述源極151和汲極152沿奈米碳管薄膜t奈米碳管的 排列方向間隔設置於奈米碳管薄膜的兩端，並分別與所 述奈米碳管薄膜電接觸。 [0017] 所述源極151、汲極152及間極120由導電材料組成。優 選地’所述源極151、汲極152及閘極120均爲一層導電 薄膜。該導電薄膜的厚度爲〇. 5奈米〜1〇〇微米。該導電薄 膜的材料可以爲金屬、合金、銦錫氧化物（ITO)、録錫 氧化物（ΑΤΟ)、導電銀膠、導電聚合物或導電性奈米碳 管等。該金屬或合金材料可以爲铭、銅、鶴、錮、金、 鈦、蝕 '鈀、鉋或其合金。本實施例中，所述源極151、 汲極152及閘極120的材料:爲金屬鈀膜，厚度爲5奈米。所 述金屬鈀與奈米碳管具有較好的潤濕效果◊上述源極151 及汲極152之間的距離爲1微米-100微米。 [0018]所述絕緣層130材料爲氮化梦、氧化碎等硬性材料或笨並 環丁烯（BCB)、聚酯或丙烯酸樹脂等柔性材料。該絕緣層 130的厚度爲5奈米〜1〇〇微米。本實施例中，所述絕緣層 130的材料爲氮化矽。可以理解，根據具體的形成工藝不 同，上述絕緣層13 0不必完全覆蓋上述源極151、汲極 152及半導體層140，只要能保證半導體層14〇、源極 09711910#.^^^ Α0101 第 9 頁 / 共.20 頁 1013033222-0 1377680 I 101年01月31日修年替換頁 和汲極152與相對設置的閘極120絕緣即可。 ， [0019] 請春目 m。 . . 参見圖3，使用時，所述源極151接地，於所述沒極152 上施加-電墨Vds ’於所述閘極12〇上施—電壓Vg，閘極 12〇電壓Vg於半導體層14〇中的通道156區域中產生電場 ，並於通道156區域靠近閘極120的表面處i生感應載流 子隨著閘極電壓Vg的增加，所述通道156靠近閘極12〇 ^表面處逐漸轉變魏流子積累層，當載流子積累到一 疋程度時，就會於源極151和没極1 52之間産生電流。由 於半導體性的奈米碳管具有較高的軸向载子移動率，且 奈米碳管薄膜中的奈米碳管首尾相連並沿從源極151至没 極152的方向排列，故載流子由源極151經半導體層14〇 至汲極152方向傳輸具有較短的傳輸路徑，從而使獲得的 薄膜電晶體10具有較大的載子移動率及較高的響應速度 [0020] 由於本技術方案實施例半導體層140中的奈米碳管具有較 好的半導體性，由奈求碳管組成的奈米碳管薄嫉沿從源 極151至汲極152的方向排列，故載流子於具有較好軸向 傳輸性能的奈米碳管中具有較高的遷移率，故由所述奈 米碳管組成的奈米碳管薄膜作爲半導體層14〇，可以使所 述薄膜電晶體10具有較大的載子移動率，進而提高薄膜 電晶體10的響應速度。本技術方案實施例中，所述薄膜 電晶體10的載子移動率高於l〇cm2/V_1sM。開關電流比 爲1. OxlO2〜1.OxlO6。 [0021] 請參閱圖4，本技術方案第二實施例提供一種薄膜電晶體 20，該薄膜電晶體20爲背栅型，其包括一閘極220、一絕 n07110in#單编號A0101 第10頁/共20頁 09711910? 1013033222-0 1377680 « * 101年.01·月.31日接正雜頁 緣層230、一半導體層240、一源極251及一汲極252。該 薄膜電晶體20設置於一絕緣基板21〇上。 [0022] 本技術方案第二實施例薄膜電晶體2〇的結構與第一實施 例中的薄膜電晶體10的結構基本相同，其區別在於：上 述閘極220設置於所述絕緣基板21〇表面；上述絕緣層 230設置於該閘極220表面；上述半導體層240設置於該 絕緣層230表面，通過絕緣層230與閘極220絕緣設置； 上述源極251及汲極252間隔設置並與上述半導體層240 電接觸，該源極251、汲極252及半導體層240通過絕緣 層230與上述閘極220電絕緣。所述半導體層24〇位於所 述源極251和汲極252之間的區域形成一通道256 » [0023] 所述源極251及汲極252可以間隔設置於該半導體層240 的上表面，此時，.源極251、汲極252與閘極220設置於 半導體層140的不同面，形成一逆交錯型薄膜電晶體2〇。 或者，所述源極251及没極252可以間隔設置於該半導體 層240的下表面，位於絕緣層230與半導、體層240之間， 此時，源極251、>及極252與閘極22〇設置於半導體層240 的同一面’形成一逆共面型薄膜電晶體2〇。 [0024] 本技術方案實施例提供的採用至少兩個沿同一方向重疊 設置的半導體性奈米碳管薄膜作爲半導體層的薄膜電晶 體及半導體器件具有以下優點：其一，由於奈米碳管薄 膜中的奈米碳管首尾相連且排列方向沿源極至汲極方向 排列，故載流子由源極經半導體層至汲極方向傳輸可具 有較短的傳輸路徑，從而有利於獲得具有較大的載子移 動率的薄膜電晶體，進而有利於提高薄膜電晶體的響應 隱靡Θ減删1 第11頁/共” 1〇13〇33222-〇 1377680 101年01月31日梭年替換頁 速度。其二，由於採用該至少兩個奈米碳管薄膜重疊設 < 置作爲半導體層，且每一奈米碳管薄膜中奈米碳管之間 通過凡德瓦爾力首尾相連，則奈米碳管薄膜具有較好的 韌性及機械強度，可以用於製造柔性的薄膜電晶體。其 三，由於奈米碳管薄膜中的奈米碳管的結構於高溫下不 會受到影響，故由該奈米碳管薄膜組成的半導體層於高 溫下仍具有較高的載子移動率。故該薄膜電晶體可應用 於高溫領域。其四，由於奈米碳管具有較高的導熱係數 ，且沿同一方向排列的奈米碳管更有利於熱量沿該方向 的傳導，故，所述奈米碳管薄膜可以有效地將薄膜電晶 體工作時所産生的熱量導出，從而有利於解决薄膜電晶 體集成於大規模集成電路中的散熱問題。 [0025] 綜上所述，本發明確已符合發明專利之要件，遂依法提 出專利申請。惟，以上所述者僅為本發明之較佳實施例 ，自不能以此限制本案之申請專利範圍。舉凡習知本案 技藝之人士援依本發明之精神所作之等效修飾或變化， 皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0026] 圖1係本技術方案第一實施例薄膜電晶體的剖視結構示意 圖。 [0027] 圖2係本技術方案第一實施例薄膜電晶體中奈米碳管薄膜 的掃描電鏡照片® [0028] 圖3係本技術方案第一實施例工作時的薄膜電晶體的結構 示意圖。 09711910^^^^* A〇101 第12頁/共20頁 1013033222-0 1-377680 101年.01月.31日修正_頁 [0029] 圖4係本技術方案第二實施例薄膜電晶體的剖視結構示意 圖。 【主要元件符號說明】 [0030] 薄膜電 晶體 :10, 20 [0031] 絕緣基板： 110， 210 [0032] 閘極： 120, 220 [0033] 絕緣層 :130， 230 [0034] 半導體層： 140， 240 [0035] 源極： 151， 251 [0036] 汲極： 152, 252 [0037] 通道： 156, 256 0971191G^單编號 A〇101 第13頁/共20頁 1013033222-0Journal of Non-Crystalline Solids, 299-302, · 1304-131 0 (2002)). The fabrication technique of amorphous germanium thin film transistor with amorphous germanium as the semiconductor layer is relatively mature, but in the amorphous germanium thin film electro-crystal Zhao, the mobility of the carrier is caused by the fact that the semiconductor layer usually contains a large number of dangling bonds. Very low (generally less than lcm2v-is-l), resulting in a slower response of the thin film transistor. A thin film transistor having a polycrystalline as a semiconductor layer has a higher carrier mobility (generally about l〇cm2v-ls-l) relative to a thin film transistor having an amorphous germanium as a semiconductor layer, so the response speed Also faster. However, the low-temperature manufacturing cost of the polycrystalline germanium film transistor is relatively complicated, the method is complicated, the large-area manufacturing is difficult, and the off-state current of the polycrystalline silicon thin film transistor is larger. Compared with the above-mentioned conventional inorganic thin film transistor, organic semiconductor polymerization is used. The organic thin film transistor which is a semiconductor layer has the advantages of low cost and low manufacturing temperature, and the organic thin film transistor has high flexibility. However, since the organic semiconductor is mostly jump-type conduction at normal temperature, it exhibits a high resistivity 'lower carrier mobility, resulting in a slower response of the organic thin film transistor. [0004] The carbon nanotubes have excellent mechanical and electrical properties, and the carbon nanotubes may exhibit metallic or semi-conducting properties as the nanocarbon tube spirals. Semiconducting carbon nanotubes have a high carrier mobility (typically up to 1 000~1 500 cm2 V ls_1) and are ideal for making transistors. It has been reported in the prior art that a carbon nanotube layer formed of a semiconducting carbon nanotube is used as a semiconductor layer of a (tetra) film transistor. In the prior art, the carbon nanotubes of the nanocarbon layer are disorderly arranged or arranged perpendicular to the substrate to form an unordered carbon nanotube layer or a carbon nanotube array. However, in the above-mentioned disordered nanotube layer, the carbon nanotubes are randomly distributed. The carrier is on page 4/total 20 pages 09Y1191〇f single number Αοιοι 1013033222-0 1377680 101 January 31, 31 revised replacement page The above-mentioned disordered carbon nanotube layer has a long conduction path, which is not conducive to obtaining Thin film transistor with higher carrier mobility. In addition, the disordered carbon nanotube layer is formed by an inkjet method, and the carbon nanotubes in the carbon nanotube layer are bonded to each other by a binder, so that the carbon nanotube layer is relatively loose. The structure and the flexibility are poor, which is not conducive to the manufacture of flexible film transistors. In the above carbon nanotube array, the arrangement of the carbon nanotubes is perpendicular to the direction of the substrate. Since the carbon nanotubes have good carrier axial transmission performance and poor transmission performance in the radial direction, the carbon nanotubes arranged perpendicular to the substrate direction are also disadvantageous for obtaining a film having a higher carrier mobility. Transistor. Therefore, the arrangement of the above two kinds of carbon nanotubes cannot effectively utilize the high carrier mobility of the carbon nanotubes. Therefore, a thin film transistor using a disordered carbon nanotube layer or a carbon nanotube array as a semiconductor layer in the prior art is disadvantageous for obtaining a thin film transistor having a high carrier mobility and a high response speed, and the prior art The thin film transistor in the middle is inferior in flexibility. In view of the above, it is necessary to provide a thin film transistor having a high carrier mobility, a high response speed, and good flexibility. SUMMARY OF THE INVENTION [0006] A thin film transistor includes a source, a drain, a semiconductor layer, and a gate, the drain is spaced apart from the source, the semiconductor layer and the source and the gate are electrically Connecting, the gate is insulated from the half-f body layer, the source and the drain by a 5 insulating layer, wherein the semiconductor layer comprises at least two carbon nanotube films stacked in the same direction, each carbon nanotube film The invention comprises a plurality of carbon nanotubes connected end to end and arranged in the same direction, and at least part of the carbon nanotubes are arranged in a direction extending from the source to the drain. [0007] Compared with the prior art, the embodiment of the present technical solution provides at least two 09711910# single number A 〇 101 page 5 / total 20 pages 1013033222-0 1377680 101 years January 31. The thin film transistor in which the carbon nanotube film is disposed in the same direction as the semiconductor layer has the following advantages: First, since the carbon nanotubes in the carbon nanotube film are connected end to end and arranged in the direction of the source to the drain Therefore, carriers can be transported from the source through the semiconductor layer to the drain to have a shorter transmission path, thereby facilitating obtaining a thin film transistor having a larger carrier mobility, thereby facilitating improvement of the response of the thin film transistor. speed. Secondly, since the at least two carbon nanotube films are overlapped and disposed as a semiconductor layer, and the carbon nanotubes in each of the carbon nanotube films are connected end to end by van der Waals force, the carbon nanotube film has Better toughness and mechanical strength can be used to make flexible thin film transistors. [Embodiment] Hereinafter, a thin film transistor provided by an embodiment of the present technical solution will be described in detail with reference to the accompanying drawings. Referring to FIG. 1 , a first embodiment of the present invention provides a thin film transistor 10 , which is a top gate type, and includes a semiconductor layer 140 , a source 151 , a drain 152 , and a first embodiment . The insulating layer 130 and a gate 120. The thin film transistor 10 is formed on the surface of an insulating substrate 110. [0010] The semiconductor layer 140 is provided on a surface of the insulating substrate 110. The source 151 and the drain 152 are spaced apart from each other on the surface of the semiconductor layer 140. The insulating layer 130 is provided on the surface of the semiconductor layer 140. The gate 120 is disposed on the surface of the insulating layer 130, and is insulated from the semiconductor layer 140 and the source 151 and the drain 152 by the insulating layer 130. The semiconductor layer 140 is located in a region between the source 151 and the drain 152 to form a channel 156. [0011] The source 151 and the drain 152 may be spaced apart from the semiconductor layer 09711910# single number deletion 1 page 6 / total 20 pages 1013033222-0 1377680 « *» |7^1 year.01. month The upper surface of the 1400 is located between the insulating layer 13 〇 and the semiconductor layer 14 4 , and the source 151 , the gate 152 and the gate 120 are disposed on the same side of the semiconductor layer 140. A common-surface type thin film transistor 10 «Or, the source 151 and the gate 152 may be spaced apart from the lower surface of the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed on the semiconductor layer. The different sides of 140 are located between the insulating substrate " and the semiconductor layer 140 to form a staggered thin film transistor. It can be understood that the positions at which the source 151 and the drain 152 are disposed are not limited. As long as the ball source 151 and the drain electrode 152 are spaced apart from each other and electrically connected to the semiconductor layer 14A, at least a part of the carbon nanotubes in the semiconductor layer 140 may be arranged in the direction from the source 丨51 to the drain 152. [0012] The insulating substrate 110 functions as a branch, and the material thereof may be selected from a hard material such as glass, quartz, ceramic, diamond, cymbal or plastic or a soft material such as plastic resin. In this embodiment, the material of the insulating substrate 11 is glass. The insulating base plate 110 is used to provide support for the thin film transistor 10. The insulating substrate 110 can also be selected from a substrate in a large-scale integrated circuit, and the plurality of thin film transistors 10 can be integrated on the same insulating substrate 110 according to a predetermined pattern or pattern to form a thin film transistor panel or other thin film transistor semiconductor device. . [0013] The semiconductor layer 140 includes at least two overlapping carbon nanotube films, each of which comprises a plurality of preferentially oriented and end-to-end semiconductor carbon nanotubes, two adjacent The carbon nanotubes in the carbon nanotube film are arranged in the same direction. At least a portion of the carbon nanotubes in the carbon nanotube film are arranged in a direction extending from the source 151 to the drain 152. Preferably, the arrangement direction of the carbon nanotubes in the above carbon nanotube film is from 09711910^^^ A 〇 101 page 7 / total 20 pages 1013033222-0 1377680 101 January 31 replacement year source The pole 151 extends in the direction of the drain 152. Adjacent to the carbon nanotube film, tightly coupled by van der Waals force. [0014] Referring to FIG. 2, the carbon nanotube film further includes a plurality of carbon nanotube bundle segments, each of the carbon nanotube bundle segments having substantially equal lengths and each of the carbon nanotube bundle segments being parallel to each other. The carbon nanotube bundle is formed, and the ends of the carbon nanotube bundle are connected to each other by Van der Waals force. The length and width of the carbon nanotube film are not limited and can be prepared according to actual needs. The number of layers of the carbon nanotube film in the above semiconductor layer 140 is not limited. The thickness of the carbon nanotube film is 0.5 nm to 1 μm. The carbon nanotubes in the carbon nanotube film can be single-walled carbon nanotubes or double-walled nanotubes. The single-walled carbon nanotube has a diameter of 0.5 nm to 50 nm; and the double-walled carbon nanotube has a diameter of 1.0 nm to 50 nm. Preferably, the carbon nanotubes have a diameter of less than 10 nanometers. [0015] The semiconductor layer 140 has a length of 1 μm to 1 μm, a width of 1 μm to 1 mm, and a thickness of 0.5 nm to 1 μm. The length of the channel 156 is 1 μm to 100 μm. The width is 丨 micron ~ 丨 mm. In the embodiment of the technical solution, the semiconductor layer 140 has a length of 5 μm, a width of 300 μm, and a thickness of 25 nm. The channel 156 has a length of 4 μm and a width of 300 μm. The semiconductor layer ι4 〇 includes a 5-layer carbon nanotube film which is disposed in an overlapping manner in the direction from the source 151 to the drain 152. Each nano carbon tube film has a thickness of 5 nm. [0016] The carbon nanotube film in the semiconductor layer can be obtained by directly drawing from a carbon nanotube array and performing further processing. The carbon nanotube film has a dryness and can be directly applied to the surface of the insulating substrate 11. Specifically, according to the relative position of the source 15 and the drain 152 and the semiconductor layer 14 , the 09711910 is strictly numbered 1013033222-0 1377680 | 101 years _ 01-31, the shuttle replacement page can be preceded by the insulating substrate 110 After adhering the carbon nanotube film, the source 151 and the drain 152 are formed on the surface of the carbon nanotube film along the arrangement of the carbon nanotubes in the carbon nanotube film, and the source 151 and the drain 152 are spaced apart. Alternatively, the source 151 and the drain 152 may be formed on the surface of the insulating substrate 110 at intervals, and then the carbon nanotube film may be laid in the direction from the source 151 to the gate 152 to cover the source 151 and the gate 152. In the embodiment of the technical solution, the source electrode 151 and the drain electrode 152 are disposed at two ends of the carbon nanotube film along the arrangement direction of the carbon nanotube film t-carbon nanotubes, and respectively respectively. The tube film is in electrical contact. [0017] The source 151, the drain 152 and the interpole 120 are composed of a conductive material. Preferably, the source 151, the drain 152 and the gate 120 are each a conductive film. The thickness of the conductive film is 0.5 nm to 1 μm. The material of the conductive film may be metal, alloy, indium tin oxide (ITO), tin oxide (barium oxide), conductive silver paste, conductive polymer or conductive carbon nanotube. The metal or alloy material may be ingot, copper, crane, ruthenium, gold, titanium, etched palladium, planer or alloy thereof. In this embodiment, the material of the source electrode 151, the drain electrode 152 and the gate electrode 120 is a metal palladium film and has a thickness of 5 nm. The metal palladium has a good wetting effect with the carbon nanotubes, and the distance between the source 151 and the drain 152 is from 1 micrometer to 100 micrometers. [0018] The material of the insulating layer 130 is a hard material such as nitriding, oxidized or the like, or a flexible material such as stupid cyclobutene (BCB), polyester or acrylic resin. The insulating layer 130 has a thickness of 5 nm to 1 μm. In this embodiment, the material of the insulating layer 130 is tantalum nitride. It can be understood that, according to a specific forming process, the insulating layer 130 does not have to completely cover the source 151, the drain 152, and the semiconductor layer 140, as long as the semiconductor layer 14 and the source 09711910#.^^^ Α0101 are ninth. Page / Total .20 Page 1013033222-0 1377680 I On January 31, 101, the replacement page and the drain 152 are insulated from the oppositely disposed gate 120. [0019] Please spring M. Referring to FIG. 3, in use, the source 151 is grounded, and an electric ink Vds' is applied to the gate 152 to apply a voltage Vg to the gate 12?, and the gate 12 〇 voltage Vg is An electric field is generated in the region of the channel 156 in the semiconductor layer 14A, and at the surface of the channel 156 near the gate 120, the induced carrier is increased as the gate voltage Vg increases, and the channel 156 is close to the gate 12〇^ The surface of the ferrite accumulation layer is gradually changed. When the carrier accumulates to a certain extent, a current is generated between the source 151 and the gate 152. Since the semiconducting carbon nanotube has a high axial carrier mobility, and the carbon nanotubes in the carbon nanotube film are connected end to end and arranged in the direction from the source 151 to the dipole 152, the current carrying current The sub-source 151 has a shorter transmission path through the semiconductor layer 14 to the drain 152, so that the obtained thin film transistor 10 has a large carrier mobility and a higher response speed [0020] Embodiments of the Invention The carbon nanotubes in the semiconductor layer 140 have good semiconductivity, and the carbon nanotubes composed of the carbon nanotubes are arranged in the direction from the source 151 to the drain 152, so that the carriers are The carbon nanotubes having better axial transmission performance have higher mobility, so that the carbon nanotube film composed of the carbon nanotubes is used as the semiconductor layer 14〇, so that the thin film transistor 10 can have The larger carrier mobility, which in turn increases the response speed of the thin film transistor 10. In the embodiment of the technical solution, the carrier mobility of the thin film transistor 10 is higher than l〇cm2/V_1sM. The switch current ratio is 1. OxlO2~1.OxlO6. [0021] Referring to FIG. 4, a second embodiment of the present invention provides a thin film transistor 20, which is a back gate type, which includes a gate 220, a gate n07110in#, a single number A0101, page 10 / Total 20 pages 09711910? 1013033222-0 1377680 « * 101 years. 01. month. 31. The porch edge layer 230, a semiconductor layer 240, a source 251 and a drain 252. The thin film transistor 20 is disposed on an insulating substrate 21A. [0022] The structure of the thin film transistor 2 of the second embodiment of the present invention is substantially the same as that of the thin film transistor 10 of the first embodiment, and the difference is that the gate 220 is disposed on the surface of the insulating substrate 21 The insulating layer 230 is disposed on the surface of the gate 220. The semiconductor layer 240 is disposed on the surface of the insulating layer 230, and is insulated from the gate 220 by the insulating layer 230. The source 251 and the drain 252 are spaced apart from the semiconductor. The layer 240 is in electrical contact, and the source 251, the drain 252, and the semiconductor layer 240 are electrically insulated from the gate 220 by an insulating layer 230. The semiconductor layer 24 is located in a region between the source 251 and the drain 252 to form a channel 256. [0023] The source 251 and the drain 252 may be spaced apart from the upper surface of the semiconductor layer 240. The source 251, the drain 252 and the gate 220 are disposed on different faces of the semiconductor layer 140 to form an inverted staggered thin film transistor 2A. Alternatively, the source 251 and the gate 252 may be spaced apart from the lower surface of the semiconductor layer 240 between the insulating layer 230 and the semiconductor layer 240. At this time, the source 251, the gate 252, and the gate 252 and the gate The pole 22 is disposed on the same surface of the semiconductor layer 240 to form an inverse coplanar thin film transistor. [0024] The thin film transistor and the semiconductor device using at least two semiconductor carbon nanotube films stacked in the same direction as a semiconductor layer provided by the embodiments of the present invention have the following advantages: First, due to the carbon nanotube film The carbon nanotubes are connected end to end and arranged in the direction of the source to the drain, so that carriers can be transported from the source through the semiconductor layer to the drain to have a shorter transmission path, thereby facilitating the acquisition of a larger The carrier mobility of the thin film transistor, which in turn is beneficial to improve the response of the thin film transistor to conceal the deletion 1 page 11 / total "1〇13〇33222-〇1377680 101 January 31st shuttle page replacement page speed Secondly, since the at least two carbon nanotube films are overlapped and disposed as a semiconductor layer, and the carbon nanotubes in each of the carbon nanotube films are connected end to end by Van der Waals force, the nanometer is The carbon tube film has good toughness and mechanical strength and can be used to manufacture flexible thin film transistors. Third, since the structure of the carbon nanotubes in the carbon nanotube film is not affected at high temperatures, The semiconductor layer composed of the carbon nanotube film still has a high carrier mobility at high temperatures. Therefore, the thin film transistor can be applied to a high temperature field. Fourth, since the carbon nanotube has a high thermal conductivity, The carbon nanotubes arranged in the same direction are more favorable for the conduction of heat in the direction. Therefore, the carbon nanotube film can effectively extract the heat generated when the thin film transistor is operated, thereby facilitating the solution of the thin film electricity. The heat dissipation problem of the crystal integrated in the large-scale integrated circuit. [0025] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above is only a preferred implementation of the present invention. For example, it is not intended to limit the scope of the patent application of the present invention. Any equivalent modifications or variations made by those skilled in the art to the spirit of the present invention are intended to be included in the scope of the following claims. 1 is a cross-sectional structural view of a thin film transistor according to a first embodiment of the present technical solution. [0027] FIG. 2 is a nanometer in a thin film transistor of the first embodiment of the present technical solution. Scanning Electron Micrograph of Tube Film® [0028] FIG. 3 is a schematic structural view of a thin film transistor in operation of the first embodiment of the present technical solution. 09711910^^^^* A〇101 Page 12 of 20 1013033222-0 1 -377680 101.01月.31日修正_页[0029] Fig. 4 is a cross-sectional structural view of a thin film transistor of a second embodiment of the present technical solution. [Main element symbol description] [0030] Thin film transistor: 10, 20 [0031] Insulating substrate: 110, 210 [0032] Gate: 120, 220 [0033] Insulation: 130, 230 [0034] Semiconductor layer: 140, 240 [0035] Source: 151, 251 [0036] 汲Pole: 152, 252 [0037] Channel: 156, 256 0971191G^Single number A〇101 Page 13/Total 20 pages 1013033222-0