200947958 ZDU3^Twi.aoc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種數位通訊網路，且特別是有關於 一種單線串列菊鍊式(daisy chain)數位通訊網路及其通訊 方法。 【先前技術】 包含一主控裝置（master device )與多個從屬裳置 « (slavedevice)之數位通訊網路具有三種拓撲結構。從屬 裝置通常用以接收來自主控裝置的指令，並且依此執行特 定功能。 ^ 圖1繪示一典型的星狀結構。於星狀佈線結構中，多 數個接收裝置Rl-Rn經由個別的通訊通道與主控裝置 通訊。接收器的識別碼(ID)或位址一般來說不是必要的。 圖2繪示一典型的匯流排結構。多個接收裝置汉^此 共用一共同通訊通道220。而接收裝置的ID或位址是必要 _ 的，如此，主控裝置210所傳送的資料才能到達正確的接 收裝置。一般而言，最初在建立通訊網路時，必須當場為 母個接收裝置指定或設定一個獨有的裝置ID。 ’ 圖3繪示一典型菊鍊式結構。主控裝置31〇與多數個 接收裝置Rl-Rn呈現菊鍊式連結。每個接收裝置僅連接一 個上游接收裴置與一個下游接收裝置。每個接收裝置接收 來自上游裝置的資料，並且在必要時，將資料傳送到下游 裝置。一般來說，菊鍊式結構需要個別接收器的仍或位 址，如此，主控裝置310才能與特定的接收裝置通訊。 5 200947958 z^u^Hiwi.uoc/n 此外，還有更多的數位通訊網路分類。比如，平行資 料傳輸相對於串列資料傳輸，晶片選擇線(chip select iine) 定址相對於網路協定定址，以及隱含時脈（自我時脈）傳 輸相對於分離時脈線傳輸。 很多高速通訊系統利用時脈線來協助接收器以正確 時序讀取資料。圖4繪示一串列資料脈波4〇1。_列資料 脈波401在不同的同步時脈會有不同的解譯。在同步時脈 402,資料被接收且被解譯為”〇11〇111〇〇1〇〇”，而在另一同 步時脈404，資料則被解譯為”〇1〇11〇1〇”。 一些知名的串列資料匯流排通訊標準包括内部整合 電路（Inter-Integrated Circuit, I2C )、系統管理匯流排 (System Management Bus，SMBus )、工業標準 RS-485 (Recommended Standard 485 )、低電壓差動訊號傳輸 (Low-Voltage Differential Signaling，LVDS)、通用串列匯 流排（Universal Serial Bus 2.0，USB 2.0 )以及單線 (1-Wire)。PC與SMBus的特徵是雙線（資料與時脈）通 訊及7位元位址空間。工業標準RS 485、LVDS、及USB 2 〇 的特徵則是雙線（資料與時脈）通訊及差動訊號傳輸。 1 Wire為美國美信集成產品公司（Maxim Integrated Pnxiucts，Inc·)的商標，其特徵為單線通訊與48位元位址空 間。 【發明内容】 有鑑於此’本發明提供一種單線串列菊鍊式數位通訊 網路及其通訊方法，其在大規模發光二極體(light-emitting 6 200947958 diode，LED)照明系統中，利用最少數量的資料通訊線達到 控制多數個發光二極體照明器的開/關狀態、色彩、咬亮 度’並且省去個別接收器身分ID或位址的需求。由於$ 需要個別接收器的身分ID或位址，可使用量產的相同元 件，不需要逐一設定位址。 本發明是有關於一種單線串列菊鍊式數位通訊網路， 其包含數個接收器。每個接收器的設計和功能皆相同，並 ❹ 且不需要裝置位址、裝置識別碼、或晶片選擇線即可運作。 本發明也為上述之數位通訊網路提出—種通訊方 法。其特色之一為單線雙向通訊’並且可簡化數位通訊網 路之安裝與維護。 本發明提供一種數位通訊網路。此系統包含多數個接 收器，它們是用來接收來自一微處理器之命令與控制資 料，並且回報給該微處理器。每個接收器包含一第一傳輸 埠與一第二傳輸埠。其中第一個接收器的第一傳輸埠耦接 _ 微處理器。除了第一個接收器，每一接收器的第—傳輸埠 耦接前一接收器之第二傳輸埠。每一接收器接收來自第一 傳輪埠的位元訊號（bitpattern)，並且解碼該位元訊號為 —資料位元或閂鎖位元（latchbit)。若該位元訊號被解碼 為一資料位元，接收器會儲存N個最新的資料位元，並且 以位元訊號的形式輸出第(N+1)個最新資料位元到第二傳 輪埠。其中，N是預設正整數。假若位元訊號被解碼為一 閃鎖位元，接收器會將上述N個最新資料位元視為一資料 字紐 (dataword)並加以處理，且以位元訊號的形式輪出 7 200947958 z)v:mwi.u〇c/n 該閂鎖位元到該第二傳輸璋。 於本實施例中，位元訊號包含一頻率校正碼與一資料 傳送碼。每個接收盜藉著頻率校正碼區分背景雜訊與位元 訊號，並且利用頻率校正碼同步一本地時脈信號。每個接 收器將資料傳送碼解碼為一資料位元或一閂鎖位元。 於本實施例中，同步化之前，可根據一電阻器之電阻 來決定本地時脈信號頻率。此電阻器可為一外部電阻器。 ❹ 上述接收器之電阻器有著相同的電阻。而同步化之後，本 地時脈信號被用來解譯資料傳送碼，並且再次傳送接收器 儲存的一位元訊號到第二傳輸埠。 於本實施例中，數位通訊網路亦支援一回報協定 (report feedback protocol)。於回報期間，第一傳輸埠與第 =傳輸埠的角色互換。-特定命令字組啟動上述回報協 定，並且由另一個命令字組中止該回報協定。 於本實施例中，每個接收器包含一旁路電路。該旁路 f路墟於第—傳輸埠及第二雜埠之間。旁路電路比較 接收器的電源供應電壓與一參考電壓。當電源供應電壓低 於參考電壓’旁路電路直接連接第—傳輸埠及第二傳輸 埠’使得接收器仍然能傳送位元訊號於其傳輸埠間。而位 元訊號本身之電能將供應旁路電路所需之電力。 【實施方式】 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉本發明之幾個實施例，並配合所附圖式， 作詳細說明如下。 8 200947958 色之一是不需要接收器身分ID或位址。 本f明揭示—種單線串列騎錢位通訊網路， ，其特200947958 ZDU3^Twi.aoc/n IX. Description of the Invention: [Technical Field] The present invention relates to a digital communication network, and more particularly to a single-line daisy chain digital communication network and Its communication method. [Prior Art] A digital communication network including a master device and a plurality of slave devices « (slavedevice) has three topologies. The slave device is typically used to receive commands from the master device and to perform specific functions accordingly. ^ Figure 1 depicts a typical star-like structure. In the star-shaped wiring structure, a plurality of receiving devices Rl-Rn communicate with the master device via individual communication channels. The receiver's identification number (ID) or address is generally not necessary. Figure 2 illustrates a typical bus bar structure. A plurality of receiving devices share a common communication channel 220. The ID or address of the receiving device is necessary, so that the data transmitted by the master device 210 can reach the correct receiving device. In general, when a communication network is initially established, a unique device ID must be specified or set for the parent receiving device on the spot. Figure 3 illustrates a typical daisy chain structure. The master device 31 is daisy-chained with a plurality of receiving devices Rl-Rn. Each receiving device is connected to only one upstream receiving device and one downstream receiving device. Each receiving device receives data from the upstream device and, if necessary, transmits the data to the downstream device. In general, the daisy chain structure requires the address or address of the individual receiver so that the master device 310 can communicate with a particular receiving device. 5 200947958 z^u^Hiwi.uoc/n In addition, there are more digital communication network classifications. For example, parallel data transmission versus serial data transmission, chip select iine addressing relative to network protocol addressing, and implicit clock (self clock) transmission versus separate clock transmission. Many high-speed communication systems use the clock line to assist the receiver in reading data at the correct timing. Figure 4 shows a series of data pulses 4〇1. _ column data Pulse 401 will have different interpretations at different synchronization clocks. At sync clock 402, the data is received and interpreted as "〇11〇111〇〇1〇〇", while at the other sync clock 404, the data is interpreted as "〇1〇11〇1〇" . Some well-known serial data bus communication standards include Inter-Integrated Circuit (I2C), System Management Bus (SMBus), Industry Standard RS-485 (Recommended Standard 485), Low Voltage Differential Low-Voltage Differential Signaling (LVDS), Universal Serial Bus 2.0 (USB 2.0), and single-wire (1-Wire). The PC and SMBus are characterized by two-wire (data and clock) communication and a 7-bit address space. The industry standard RS 485, LVDS, and USB 2 〇 are characterized by two-wire (data and clock) communication and differential signal transmission. 1 Wire is a trademark of Maxim Integrated Pnxiucts, Inc., which features single-line communication and 48-bit address space. SUMMARY OF THE INVENTION In view of the above, the present invention provides a single-line tandem daisy-chain digital communication network and a communication method thereof, which are least utilized in a large-scale light-emitting 6 (200947958 diode, LED) illumination system. The number of data communication lines reaches the control of the on/off status, color, bite brightness of most of the LED illuminators and eliminates the need for individual receiver IDs or addresses. Since the identity ID or address of an individual receiver is required, the same components of mass production can be used, and it is not necessary to set the addresses one by one. The present invention is directed to a single-line tandem daisy-chain digital communication network that includes a plurality of receivers. Each receiver is designed and function identically and does not require a device address, device identification code, or wafer selection line to operate. The present invention also proposes a communication method for the above-mentioned digital communication network. One of its features is single-wire two-way communication' and simplifies the installation and maintenance of digital communication networks. The invention provides a digital communication network. The system includes a plurality of receivers for receiving command and control data from a microprocessor and reporting back to the microprocessor. Each receiver includes a first transmission port and a second transmission port. The first transmission of the first receiver is coupled to the _ microprocessor. In addition to the first receiver, the first transmission port of each receiver is coupled to the second transmission port of the previous receiver. Each receiver receives a bit pattern from the first rim and decodes the bit signal as a data bit or a latch bit. If the bit signal is decoded into a data bit, the receiver stores the N most recent data bits, and outputs the (N+1)th latest data bit to the second pass in the form of a bit signal. . Where N is a preset positive integer. If the bit signal is decoded into a flash lock bit, the receiver treats the N most recent data bits as a data word and processes it, and rotates it in the form of a bit signal. 7 200947958 z)v :mwi.u〇c/n The latch bit is to the second transfer port. In this embodiment, the bit signal includes a frequency correction code and a data transmission code. Each receiving pirate distinguishes the background noise from the bit signal by the frequency correction code, and synchronizes a local clock signal with the frequency correction code. Each receiver decodes the data transfer code into a data bit or a latch bit. In this embodiment, the local clock signal frequency can be determined according to the resistance of a resistor before synchronization. This resistor can be an external resistor.电阻 The resistors of the above receivers have the same resistance. After synchronization, the local clock signal is used to interpret the data transmission code and retransmit the one-bit signal stored by the receiver to the second transmission port. In this embodiment, the digital communication network also supports a report feedback protocol. During the return period, the first transmission 互换 is interchanged with the role of the transmission 埠. - The specific command block initiates the above reward agreement and the return agreement is aborted by another command block. In this embodiment, each receiver includes a bypass circuit. The bypass f road is between the first-transport and the second chowder. The bypass circuit compares the power supply voltage of the receiver with a reference voltage. When the power supply voltage is lower than the reference voltage, the bypass circuit is directly connected to the first transmission port and the second transmission port 埠 so that the receiver can still transmit the bit signal between its transmissions. The power of the bit signal itself will supply the power required by the bypass circuit. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention. 8 200947958 One of the colors is that no receiver ID or address is required. This f reveals a kind of single-line tandem riding money communication network,
個接队衣Κ間的雙向通訊方法。 裝置與其他接收裝置間的通訊不受影響。 參 ® 5繪示本發明一實施例的一種數位通訊網路。此系 統包含一微控制器501所控制之數個接收器5〇2。比如， 每個接收器502可以控制數個發光二極體照 示）。上述接收器502被連接為一菊鍊形式。每個接收 502包含一第一傳輸埠P1及一第二傳輸埠卩2。其中第三 個接收器的第一傳輸埠P1耦接微控制器5〇1。除了第一個 接收器以外，每個接收器502的第一傳輸埠P1耦接前一 個接收器的第二傳輸缂P2。每個接收器502在功能與結構 上是完全一致的。微控制器50丨只藉由在菊鍊的順序位置 > 識別各個接收器。 微控制器501與接收器502所用的通訊協定内含於位 元訊號的時序本質。微控制器501傳送位元訊號到第一個 接收器的第一傳輸埠P1。每個接收器502藉由其第一傳輸 埠P1接收位元訊號並將其解碼，而後，若有必要，傳送 該位元訊號到下一個接收器502。另一做法為微控制器501 啟動回報協定（report feedback protocol)，使接收器502 接收第二傳輸埠P2的位元訊號，然後傳送此位元訊號到 9 200947958 第一傳輸埠PI，再傳送此位元訊號到微控制器501。在此 二情形中，接收器502對於位元訊號之動作如同解碼器與 重複器(repeater)。每個第一傳輸埠pi與第二傳輸埠P2只 有一條傳輸線’達成雙向單線通訊。 圖6繪示一典型位元訊號601之波形。位元訊號601 包含一頻率校正碼602與一資料傳送碼603。資料傳送碼 603的持續期間相同於頻率校正碼6〇2的持續期間。每個 eTwo-way communication method between the pick-ups. Communication between the device and other receiving devices is not affected. Reference numeral 5 shows a digital communication network according to an embodiment of the present invention. The system includes a plurality of receivers 5〇2 controlled by a microcontroller 501. For example, each receiver 502 can control a plurality of LEDs). The receivers 502 described above are connected in a daisy chain form. Each receiving 502 includes a first transmission port P1 and a second transmission port 2. The first transmission port P1 of the third receiver is coupled to the microcontroller 5〇1. In addition to the first receiver, the first transmission port P1 of each receiver 502 is coupled to the second transmission port P2 of the previous receiver. Each receiver 502 is identical in function and structure. The microcontroller 50 识别 identifies each receiver only by the sequential position > in the daisy chain. The communication protocol used by microcontroller 501 and receiver 502 is inherent in the timing nature of the bit signals. Microcontroller 501 transmits the bit signal to the first transmission port P1 of the first receiver. Each receiver 502 receives the bit signal by its first transmission 埠P1 and decodes it, and then transmits the bit signal to the next receiver 502 if necessary. Another method is that the microcontroller 501 starts a report feedback protocol, so that the receiver 502 receives the bit signal of the second transmission port P2, and then transmits the bit signal to the 9 200947958 first transmission port PI, and then transmits the bit signal. The bit signal is sent to the microcontroller 501. In both cases, the receiver 502 acts like a decoder and repeater for the bit signal. Each of the first transmission port pi and the second transmission port P2 has only one transmission line 'to achieve two-way single-wire communication. FIG. 6 illustrates a waveform of a typical bit signal 601. The bit signal 601 includes a frequency correction code 602 and a data transmission code 603. The duration of the data transmission code 603 is the same as the duration of the frequency correction code 6〇2. Each e
接收器502藉由驗證頻率校正碼6〇2以區分非信號背景雜 訊及位元訊號601。因為接收器5〇2之本地時脈頻率很可 月b會不同於微控制器5〇1的時脈頻率，所以每個接收器5〇2 也利用頻率校正碼6〇2同步其本地時脈信號，。每接收一 個位το訊號，就會重新執行一次同步，因此消除了累積時 間誤差的可能性。 次資料傳送碼603用以遞送資料或命令。每個接收器5〇2 將資料傳送碼’解碼成—資料位元或—特別的閃鎖位 =。關於上述同步、解碼與圖6波形的更多細節將於以下 “ f 7緣不一接收器502之部份電路。每個接收器502 碼緩衝器7〇1、一鍊暫存器、-輸出編 衝Ϊΐϋ’ Μ數㈣料暫存器711_714。輸入解碼緩 緩衝第i輸淳Ρ1。鍊暫存11702減輸入解碼 耦接於於入姑、資料暫存器711_714。輸出編碼緩衝器703 埠^ H碼緩衝_、鍊暫存117G2、以及第二傳輸 旱2圖7各元件將在以下詳細討論。 200947958 ZDUD4IWI.d〇c/n 、圖8繪示本實施例中每個接收器502所執行之通訊方 法流程圖。該流程開始於步驟805。輸入解碼緩衝器701 解碼位兀訊號601。起先，輪入解碼緩衝器7〇1必須驗證 位兀訊號601為有效信號。輸入解碼緩衝器7〇1接收來自 第一傳輸埠P1的一個信號（步驟8〇5)並且在一預設期間 内計數該信號之脈波(pulse)個數（步驟81〇)。比如該預 设期間可為一微秒。接下來，輸入解碼緩衝器7〇1檢查該 ❹ 脈波之個數是否大於或等於一預設數字。比如，該預設數 字可為3 (步驟815)。若上述之脈波個數大於或等於預設 數字，輸入解碼緩衝器701認定目前接收的信號為一有效 頻率校正碼602，並且接收緊隨著目前信號的下一個信號 做為資料傳送碼603 (步驟820)。如果上述之脈波個數小 於預設數字，目前信號則被視為非信號雜訊，流程就回到 步驟805。 接著，接收器502利用頻率校正碼6〇2同步其本地時 _ 脈信號（步驟825)。並用預設數量的連續脈波邊緣來定 義頻率校正碼.602之持續期間。上述的脈波邊緣可為上升 邊緣（rising edge)或下降邊緣（falling edge)。比如在本 實施例，其持續期間被四個連續下降邊緣所定義。而圖6 之波开> 604為頻率校正碼602之範例波形。在本發明之其 他實施例，頻率校正碼602的持續期間也可以由預設數^ 之連續上升邊緣所界定。 接收器502藉由調整本地時脈信號頻率來同步本地時 脈信號，使得本地時脈信號在頻率校正碼6〇2之持續期間 200947958 ,Receiver 502 distinguishes between non-signal background noise and bit signal 601 by verifying frequency correction code 6〇2. Since the local clock frequency of the receiver 5〇2 is very different from the clock frequency of the microcontroller 5〇1, each receiver 5〇2 also synchronizes its local clock with the frequency correction code 6〇2. signal,. Each time a bit το signal is received, the synchronization is re-executed, thus eliminating the possibility of accumulated time errors. The secondary data transmission code 603 is used to deliver data or commands. Each receiver 5〇2 decodes the data transfer code' into a data bit or a special flash lock bit. More details on the above-mentioned synchronization, decoding and waveforms of Fig. 6 will be described below as follows: "F 7 is not part of the circuit of the receiver 502. Each receiver 502 code buffer 7 〇 1, a chain register, - output Ϊΐϋ Ϊΐϋ Μ Μ Μ 四 四 四 四 四 四 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 711 H code buffer_, chain temporary storage 117G2, and second transmission drought 2 The components of Fig. 7 will be discussed in detail below. 200947958 ZDUD4IWI.d〇c/n, Fig. 8 shows that each receiver 502 is executed in this embodiment. The flow of the communication method begins in step 805. The input decode buffer 701 decodes the bit signal 601. Initially, the round-in decoding buffer 7〇1 must verify that the bit signal 601 is a valid signal. The input decode buffer 7〇 1 receiving a signal from the first transmission port P1 (step 8〇5) and counting the number of pulses of the signal within a predetermined period (step 81〇). For example, the preset period may be a micro Second, next, the input decode buffer 7〇1 checks the pulse Whether the number is greater than or equal to a preset number. For example, the preset number may be 3 (step 815). If the number of pulses described above is greater than or equal to a preset number, the input decoding buffer 701 determines the currently received signal. Is an effective frequency correction code 602, and receives the next signal immediately following the current signal as the data transmission code 603 (step 820). If the number of pulses described above is less than the preset number, the current signal is regarded as a non-signal. The noise, the flow returns to step 805. Next, the receiver 502 synchronizes its local time_pulse signal with the frequency correction code 6〇2 (step 825) and defines the frequency correction code with a preset number of consecutive pulse edges. The duration of the pulse wave may be a rising edge or a falling edge. For example, in the embodiment, the duration is defined by four consecutive falling edges, and the wave of FIG. 6 is open. 604 is an example waveform of the frequency correction code 602. In other embodiments of the invention, the duration of the frequency correction code 602 may also be defined by a continuous rising edge of the preset number ^. Adjusting the local clock signal frequency to synchronize the local clock signal so that the local clock signal is in the duration of the frequency correction code 6〇2 200947958,
z.JU^*ttwi.u〇C/D 内擁有一預設數量的脈波。比如，該預設數量可為16。而 圖6之波形608為同步後的本地時脈信號之範例波形。而 調整本地時脈頻率之技術細節已廣為人知’在此就不加以 討論。z.JU^*ttwi.u〇C/D has a preset number of pulse waves. For example, the preset number can be 16. Waveform 608 of Figure 6 is an example waveform of the synchronized local clock signal. The technical details of adjusting the local clock frequency are well known and will not be discussed here.
接著，輸入解碼緩衝器701接收資料傳送碼603 (步 驟830)。因為頻率校正碼602與資料傳送碼603有相同 的持續期間，所以資料傳送竭603之持續期間可以用同步 本地時脈信號來量測。而資料傳送碼6〇3根據它的脈波數 被解碼（步驟840)。若資料傳送碼6〇3沒有脈波，如圖6 所示之波形605,輸入解碼緩衝器7〇1認定資料傳送碼6〇3 為一數值1之資料位元。若資料傳送碼603有一個脈波， 如圖6所示之波形606，輸入解碼緩衝器7〇1認定資料傳 送碼603為一數值〇之資料位元。若資料傳送碼6〇3有二 個脈波，如圖6所不之波形6〇7，輸入解碼緩衝器7〇1認 定資料傳送碼603為一特殊閂鎖位元。 若資料傳送碼6G3被認定為—資料位元，不論其值為 1或0’流程進到步驟835。輸入解碼緩衝器7〇1提供已解 ，的資料，元到鍊暫存器702。鍊暫存器7〇2有一預設數 置的位=單兀（bit cells)。比如，此預設數量可為9。每 個位το皁兀用來儲存—資料位元。每#接收最新的資料位 兀，鍊暫存器702移動儲存在每個位元單元的資料位元到 下一個位元單元，然後儲存最新資料位元於第-個位元單 兀。由此可知，鍊暫存器7〇2儲存 器-之最新資料位元。先前存在最後:元== 12 200947958 ^jw^mwi.uoc/n =也就疋第10個最新資料位元或稱為最舊（least recent) ^才^位元’會被移出鍊暫存H 702 ’並且存進輸出編碼緩 衝器703。在本發明的其他實施例，鍊暫存器702可包含 較多或較少的位元單元。 輸出編碼緩衝器703接收來自鍊暫存器702之最舊資 料位兀，利用同步的本地時脈信號作為時序參考，將最舊 資料位元重建為位元訊號，而後輸出此位元訊號到第二傳 參 輸琿P2在傳送最舊資料位元之後，流程回到步驟8仍以 接收下一個位元訊號。 一若輸入解碼緩衝器701在步驟840將位元訊號解碼為 4鎖位元’流程則進到步驟845。該_位元行進路徑 不同於資料位元’是由輸入解碼緩衝器期直接輪出問鎖 t兀f輸出編碼緩衝器703 ’而非鍊暫存器7G2。輸出編碼 緩衝器7〇3利用同步的本地時脈信號作為時序參考，將閃 鎖位元重建為位元訊號（步驟叫，然後輸出此位元訊 號到第二傳輸埠P2。 每當微控制器501傳送資料位元到第一個接收器 502,該資料位元變為第一個接收器之最新資料位元。第二 個接收H的最舊資料位元變為第二個魏㈣最新資料位 元。而第二個接收器的最舊資料位元變為第三個接收器 最新資料位元。依此類推。實際上’所有接收器5〇2 暫存器702串接成-長仔列，可視為—個整體的移 器（shift register)。 在本實施例之通訊方法協定’ 9個資料位元構成—字 13 200947958 ZDU34iwr.aoc/n 組（word )該通訊方法具有一順向協定（f〇rward pr〇t〇c〇i) 以及一回報協定（report feedback pr〇t〇c〇1)。該順向協定 被微控制器501用來傳送控制資訊或命令到接收器5〇2。 比如，微控制器501可控制數千個接收器5〇2。如圖7所 示，每個接收器502可控制四個LED照明器。當微控制器 501尚要傳送控制字組給全部照明器時，微控制器會 分幾，批次送出控制字組。該控制字組可包含給照明器之 控制資訊，> LED電流設定或脈衝寬度調變（ρ— M〇dulati〇n, PWM )明暗等級(dimming level)設定。 在第一個批次，微控制器5〇1傳送控制字組給最後一 個接收器所控制的第一個照明器，然後傳送控制字組給倒 數第二個接收器所控制的第一個照明器。依此類推。直到 =微控制器別送出控制字組給第一個接收器所控制的 哭。器1此時’控制字組佔滿全部接收器之鍊暫存 ^字ί。收11的鍊暫存15皆儲存它的第—個照明器的控 接著，微控制器501 S送ϋ鎖 器702的子組。第一個接收器崎 的车W物… 識別儲存在鍊暫存器702 組若命令字組， =7到第—資料暫存器 845)。藉著這個方式，瞻元沿著整個= 200947958 ^JUJ^iwi.uO〇/n 收器，使得在每-接收器之控制字組從鍊暫存器7〇2被移 到第一資料暫存器711。 w在第二個批次，微控制器501發送控制字組到每個接 收器502所控制的第二個照明器，這些控制字組被儲存到 每個接收器502的第二資料暫存器712。接下來的批次以 相同方式進行。最後’全部LED照㈣之控料組都被存 進其對應的資料暫存器。 β 喃協定是用來讓接收器5〇2報告重要訊息給微控制 器5(U。比如，報告訊息可為LED照明器之錯誤狀態。微 f制1§ 501藉由傳送一連串的報告命令字組來啟動回報協 定。上述報告命令字組的個數等於接收器的健也就是 每健收器都會收到自己的命令字組。而後微控制器5〇ι j出-閃鎖位元。每個接收器識別儲存在鍊暫存器7〇2的 字組’並且認賴字組為報告命令字組（步驟8則。因 此流程行進到步驟855。 識別報告命令字組之後，每個接收器SG2載入一報告 字組到其鍊暫存器7〇2 (步驟855)，然:後將其第—傳輸& P1與第二傳輸埠P2的角色互換（步驟。交換角色 意味著耦接輸入解碼緩衝器701到第二傳輸埠p2，以及耦 接輸出編碼緩衝器7〇3到第一傳輸埠ρι，使 5〇2接收來自第二傳輸槔P2的位元訊號，並且遞送位元；; 號到第-傳輸埠Pi。這樣就反轉了菊鍊的傳輸方向。 菊鍊的最後-個接收器具有一個特別任務，也就是啟 動報告子組的逆向傳輸。數位通訊網路的使用者可拉高戋 15 200947958 zou^iwi.aoc/n 拉低一個接收裝置的輸入腳位（inPut Pin)到一預設電壓 準位，使得該接收器知道它是最後一個接收器。在交換其 二個傳輸埠（I/O ports)的角色之後’每個接收器檢查自 己是否為菊鍊之最後接收器（步驟865)。若為最後一個， 則該最後接收器輸出該報告字組以及一個隨後的終止命令 字組’這兩個字組是經由鍊暫存器702與輸出編碼緩衝器 703傳送到第一傳輸埠P1 (步驟870)。 ❹ 如同在順向協定之中位元訊號的行進，最後一個接收 器的傳輸觸發前面接收器的傳輸。每個接收器提供一報告 字組，而最後一個接收器提供一報告字組與一終止命令字 組。這一連串報告字組與終止命令字組經過上述的虛擬移 位暫存器佇列到達微控制器501。微控制器5〇1接收的第 一個報告字組來自最靠近它的第一個接收器5〇2。微控制 器501接收的第二個報告字組來自第二個接收器5〇2，依 此類推。藉由接收的次序，微控制器501知道每個報告字 _ 組的真正來源。在輸出終止命令字組之後，最後的接收器 再:欠交換其二個傳輸淳的角色，也就是將輸入解碼緩衝器 7〇1耦接回第一傳輸埠ρι，以及將輸出編碼緩衝器7〇3耦 接回第二傳輸琿P2，以恢復原先的傳輸方向（步驟880)。 然後流程返回步驟_重·始順向協定。 a,如果在步驟865的檢查顯示該接收器並非最後-個， 味該器，始等待來自菊鍊的下-個接收器的位元訊 8;。广收益收到來自第二傳輸埠 Ρ2的位元訊號（步驟 f子已解喝的資料位元於鍊暫存器702,做為最新 200947958 ^DUD4twr.aoc/n 資料位元，並輸出來自鍊暫存器7〇2的最舊資料位元到前 一個（上游）接收器。接著，接收器檢查儲存於鍊暫存器 702之全部資料位元是否構成來自最後接收器的終止命令 字組（步驟874)。若終止命令字組尚未進入鍊暫存器7〇2, 則回報協定依然有效，流程返回步驟872以接收來自後一 個（下游）接收器的下一個位元訊號。若終止命令字組已 進入鍊暫存器702，則接收器經由輸出編碼緩衝器7〇3輸 ❹ 出終止命令字組到第一傳輸槔P1 (步驟876)。接著，接 收器再次交換其第一傳輸埠P1與第二傳輸埠打的角色以 恢，原先的傳輸方向（步驟88〇)。現在，接收器的回報 協定結束，流程返回步驟805以重新開始順向協定。 從以上討論可知，在菊鍊之中的每個接收器5〇2的順 序’其巧用如同該接收器的隱含位址。因此本實施例的通 訊方法提供-種不需要位址或身份識別碼（此禮㈣加 code)之雙向傳輸方式。 ^每個接收器用頻率校正碼602同步其本地時脈信 號。起先，同步之前，可根據一電阻器之電阻來決定本地 時脈信號頻率。每個接收器可以製作成積體電路晶片的形 式而上述電阻器可為一輕接到該晶片的外部電阻器R， 如圖五所示。在此情形令，使用者能藉由控制外部電阻器 R之電阻輕易調整初始的本地時脈頻率。為了使時間偏差 最小化，每個接收器502的外部電阻器汉最好擁有相同的 電阻值。 每個接收盗502包含一時脈產生器，用來提供本地時 17 200947958 25054twf.doc/n 脈信號。圖9繪示本實施例的時脈產生器之電路。該時脈 產生器包含一電流產生器910、二電流鏡92〇與93〇、一正 迴授振盡器940以及一信號整形器950。電流產生器91〇 搞接外部電阻器R。電流鏡920編接電流產生器91〇。電 流鏡930耦接電流鏡920。正迴授振盪器94〇耦接電流鏡 930。信號整形器950耦接正迴授振盪器940。 電流產生器910包含一運算放大器opa ^ VIp為一定 Φ 值參考電壓。運算放大器OPA之虛擬短路(viTtual short circuit)使在ROUT之電壓相等於VIP。因此，電流產生器 910提供與外部電阻器r之電阻成反比的參考電流IREF。 電流鏡920根據參考電流iref提供一電流鏡電流iMl。 電流鏡930根據電流鏡電流IM1提供另一電流鏡電流 IM2。電流鏡930也根據電流鏡電流IM]L提供一控制電壓 VBN，並根據電流鏡電流IM2提供另一控制電壓VBP。正 迴授振盪器940提供一週期信號pS，其頻率取決於控制電 壓VBN與VBP (細節於稍後探討）。信號整形器950之反 相器951與952將週期信號Ps整形成本地時脈信號CLK。 正迴授振盪器940包含七個三態反相器941-947。三 態反相器941-947完全相同，以串聯方式連接。以第一個 二態反相器941為例。圖1〇纟會示三態反相器941之電路， 其包含四個金屬氧化半導體場效電晶體（metal 〇xide semiconductor field effect transistor，MOSFET)。MP1 與 MP2 為 p 通道 MOSFET’MNl 與 MN2 為 n 通道 MOSFET。 電阻器R之電阻值決定了 IREF、IM1與IM2的電流 18 200947958 厶U y» t W ·! · U〇 g/π 大小，而電流鏡電流IM1與IM2分別決定了控制電壓VBN 與VBP的準位。控制電壓VBP決定流經MOSFET MP1 之電流’而控制電壓VBN決定流經]viOSFET MN2之電 流。流經MP1與_2之電流決定了三態反相器941的輸 出切換速率。上述三態反相器941-947是完全相同的。所 以’外部電阻器R之電阻值可決定本地時脈信號CLK的 頻率。在本發明的其他實施例中，正迴授振盪器940可包 φ 含較多或較少的三態反相器。 本實知例的接收器也具備容錯能力（fault t〇ierance)。 备一接收器突然損壞或失去它的供電，該接收器仍然能夠 在其傳輸埠P1與P2之間傳遞位元訊號，以維持同一菊鍊 的其他接收器的通訊。這是因為每個接收器包含一旁路電 路所致。 圖11繪示本實施例的旁路電路。該旁路電路耦接於 第一傳輸埠P1與第二傳輸埠P2之間。該旁路電路包含二 極體D1與D2、電容器CB、電阻器R1與R2、旁路開關 1101以及比較器11〇2。二極體1)1之陽極耦接第一傳輸埠 P1 ’ 一極體D2之陽極耦接第二傳輸埠p2。二極體D2之 陰極耦接二極體D1之陰極。電容器CB具有兩端，上端 耗接-極體D1與D2之陰極，下端接地。電容器CB上端 提供-電容器電壓VC。電壓轉換器蘭包含電阻器R1 與R2 ’並且提供一參考電壓VR£F。VRE]p和電容器電壓 vc成正比，而fu與R2的電阻值預設了 對的 比率。比較益1102耦接電壓轉換器11〇3，用來比較參考 200947958 · »· ·· a..v»oc/ii 電壓^VRE F與接收器之電源供應電s νρ s。旁路開關㈣ 耦接第-傳輸埠P1'第二傳輸埠P2以及比較器贈。旁 路開關1101根據比較器1102的輸出而導通或阻斷第一傳 輸埠P1與第二傳輸埠P2。 々在軸蚊顧，來自第—傳輪埠pl的位元訊號對 電谷器CB充電，並且電容器提供電容器電壓％。二 極體D1防止電容器CB放電並且維持％之電壓準位，而 豢 vc之電壓準位也維持VREF的電壓準位。在正常情況下， 電源供應 vps高財考電壓VREF，比較旨11〇2的 輸出在一邏輯低準位。相應之下，旁路開關11G1阻斷第- 傳輸埠P1與第二傳輸埠P2。傳輸埠P1與^未短路，順 向協定就如前述的方式執行。比較H 11G2之電力是由從第 -傳輸埠:P1經過二極體D1的位元職之電能所提供。 ▲接收器損壞或喪失其電力時，電源供應電壓vps 會降，並低於參考電壓VREFe比較器1102的輸出上升到 一邏輯高準位，並且觸發旁路開關1101導通第一傳輸埠 P1與第二傳輸埠P2。現在’第一傳輸埠ρι與第二傳輸埠 P2被短路。雖然接收器本身不能處理位元訊號，但是來自 第一傳輸埠P1之位元訊號能夠不受阻擾地傳到第二傳輸 埠P2。 如圖11所示，旁路電路是對稱的。於回報協定期間， 二極體D2取代二極體D1對電容器CB充電，並且提供電 力給比2器1102。旁路電路在回報協定期間也能正常動 作。如前所述，旁路電路完全由位元訊號提供電力；因此， 200947958 « * ττ 即使，收器的電力十斷，旁路電路依然可正常運作。 ’本發明之實施例提供—種數位通訊網路及 八I訊方法。上述數位通訊網路的通訊方法為雙向，並且 Ϊϋ接收器指派唯—位址或識別碼。單線傳輸槔減少了 女裝…維護成本。時脈產生器根據電阻器之電阻決定本地 時脈頻率。藉由選擇合適的電阻值給每個接收器的時脈電 ^二系統就能調整整體的通訊時脈速度。此外，當接收器 ❷ #壞或遭受電力中斷，旁路電路仍可提供容錯能力。 —雖然本發明已揭露如上幾個實施例’然其並非用以限 ，本發明’，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作些許之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1纷示一種星狀結構的傳統數位通訊網路。 圖2緣示一種匯流排結構的傳統數位通訊網路。 | 圖3繪示一種菊鍊結構的傳統數位通訊網路。 圖4緣示一同步時脈信號如何協助一接收器對傳送的 資料正確解碼。 圖5繪示本發明一實施例的一種數位通訊網路。 圖6繪示本發明一實施例的位元訊號之波形。 圖7續'示本發明一實施例的接收器之部份結構。 圖8為本發明一實施例的一種通訊方法之流程圖。 圖9為本發明一實施例的一種時脈產生器之電路圖。 圖10為圖9的時脈產生器的三態反相器之電路圖。 21 x.Joc/n 200947958 圖11繪示本發明一實施例的接收器之旁路電路。 【主要元件符號說明】 110 :主控裝置 Rl-Rn :接收裝置 210 :主控裝置 220 :共同通訊通道 P :(平行）資料線 q :(平行）位址線 310 :主控裝置 401 :串列資料脈波 402、 404 :同步時脈 403、 405 :解譯資料 501 :微控制器 502 :接收器 P1 :第一傳輸埠 P2 :第二傳輸埠 _ R:外部電阻器 601 :位元訊號 602 :頻率校正碼 603 :資料傳送碼 604 :頻率校正碼之範例波形 605 :沒有脈波之資料傳送碼 606 :有一脈波之資料傳送碼 607 :有二脈波之資料傳送碼 22 200947958 z^u^iwi.doc/n 608:已同步的本地時脈信號之範例波形 701 :輸入解碼緩衝器 702 :鍊暫存器 703 :輸出編碼緩衝器 711 :第一資料暫存器 712 :第二資料暫存器 713 :第三資料暫存器 714 :第四資料暫存器 805-885 :本發明一實施例之通訊方法流程圖各步驟 910 :電流產生器 920、930 :電流鏡 940 :正迴授振盪器 941-947 :三態反相器 950 :信號整形器 95卜952 :反相器 CLK :本地時脈信號 VIP :定值參考電壓 OPA :運算放大器 IREF :參考電流 ROUT :輸出端 IM1、IM2 :電流鏡電流 VBN :控制電壓 VBP :控制電壓 PS :週期信號 23 200947958 z—JU-iHiwi.uOC/nNext, the input decode buffer 701 receives the material transfer code 603 (step 830). Since the frequency correction code 602 has the same duration as the data transmission code 603, the duration of the data transmission 603 can be measured by the synchronized local clock signal. The data transfer code 6〇3 is decoded based on its pulse number (step 840). If the data transmission code 6〇3 has no pulse wave, as shown in the waveform 605 shown in FIG. 6, the input decoding buffer 7〇1 determines that the data transmission code 6〇3 is a data bit of a value of 1. If the data transmission code 603 has a pulse wave, as shown in the waveform 606 shown in Fig. 6, the input decoding buffer 〇1 asserts that the data transmission code 603 is a data bit of a value 。. If the data transmission code 6〇3 has two pulses, as shown in Fig. 6 of the waveform 6〇7, the input decoding buffer 7〇1 determines that the data transmission code 603 is a special latch bit. If the material transfer code 6G3 is recognized as a data bit, the process proceeds to step 835 regardless of the value of 1 or 0'. The input decode buffer 7〇1 provides the decoded data to the chain register 702. The chain register 7〇2 has a preset number of bits = bit cells. For example, this preset number can be 9. Each bit τ soap is used to store data bits. Each # receives the latest data bit, and the chain register 702 moves the data bit stored in each bit cell to the next bit cell, and then stores the latest data bit in the first bit cell. It can be seen that the chain register 7〇2 stores the latest data bit. Pre-existing last: yuan == 12 200947958 ^jw^mwi.uoc/n = also the 10th latest data bit or the oldest (least recent) ^ only ^ bit will be removed from the chain temporary H 702 'and stored in the output code buffer 703. In other embodiments of the invention, chain register 702 may include more or fewer bit cells. The output code buffer 703 receives the oldest data bit from the chain register 702, uses the synchronized local clock signal as a timing reference, reconstructs the oldest data bit into a bit signal, and then outputs the bit signal to the first After the second transmission parameter P2 transmits the oldest data bit, the flow returns to step 8 to receive the next bit signal. If the input decode buffer 701 decodes the bit signal into a 4-bit bit in step 840, the flow proceeds to step 845. The _bit travel path is different from the data bit ’ by the input decode buffer period and directly outputs the code buffer 703 ' instead of the chain register 7G2. The output code buffer 7〇3 uses the synchronized local clock signal as a timing reference to reconstruct the flash lock bit into a bit signal (step call, and then output the bit signal to the second transfer port P2. Whenever the microcontroller 501 transmits the data bit to the first receiver 502, the data bit becomes the latest data bit of the first receiver. The second oldest data bit receiving the H becomes the second Wei (four) latest data. Bit. The oldest data bit of the second receiver becomes the latest data bit of the third receiver. And so on. In fact, 'all receivers 5〇2 register 702 are connected in series to - long The column can be regarded as a whole shift register. In the present embodiment, the communication method protocol '9 data bits constitutes - word 13 200947958 ZDU34iwr.aoc/n group (word) the communication method has a forward direction The agreement (f〇rward pr〇t〇c〇i) and a return agreement (report feedback pr〇t〇c〇1). The forward protocol is used by the microcontroller 501 to transmit control information or commands to the receiver 5〇. 2. For example, the microcontroller 501 can control thousands of receivers 5〇2. As shown in Figure 7, each of the receivers 502 can control four LED illuminators. When the microcontroller 501 still has to transmit a control block to all of the illuminators, the microcontroller will send the control blocks in batches. The block can contain control information for the illuminator, > LED current setting or pulse width modulation (ρ—M〇dulati〇n, PWM) dimming level setting. In the first batch, the microcontroller 5〇1 transmits the control block to the first illuminator controlled by the last receiver, then transmits the control block to the first illuminator controlled by the penultimate receiver, and so on. Until = micro control The device does not send the control block to the crying controlled by the first receiver. At this time, the control word group fills the chain of all the receivers temporarily stored ^^. The chain temporary storage 15 stores the first of them. Control of a luminaire Next, the microcontroller 501 S sends a subgroup of the shackle 702. The first receiver is the car of the squad... The identification is stored in the chain register 702 group if the command word group, =7 to First - data register 845). In this way, Zhanyuan moves along the entire = 200947958 ^JUJ^iwi.uO〇/n receiver, so that the control block of each receiver is moved from the chain register 7〇2 to the first data temporary storage. 711. w In the second batch, the microcontroller 501 sends a control block to the second illuminator controlled by each receiver 502, which is stored in the second data register of each receiver 502. 712. The next batch is done in the same way. Finally, the control group of all LED photos (4) is stored in its corresponding data register. The beta protocol is used to allow the receiver 5〇2 to report important messages to the microcontroller 5 (U. For example, the report message can be the error state of the LED illuminator. The microf 1 § 501 by transmitting a series of report command words The group starts the reward agreement. The number of command word groups in the above report is equal to the health of the receiver, that is, each receiver receives its own command word group, and then the microcontroller 5〇ι j out-flash lock bit. The receivers identify the block ' stored in the chain register 7〇2 and recognize the block as the report command block (step 8). Therefore the flow proceeds to step 855. After identifying the report command block, each receiver SG2 loads a report block into its chain register 7〇2 (step 855), but then swaps its first transmission & P1 with the role of the second transmission 埠 P2 (step. Exchange role means coupling Inputting the decoding buffer 701 to the second transmission 埠p2, and coupling the output encoding buffer 〇3 to the first transmission 埠ρι, so that 〇2 receives the bit signal from the second transmission 槔P2, and delivers the bit; The number to the first transmission pi. This reverses the direction of the daisy chain. The last receiver of the daisy chain has a special task, that is, the reverse transmission of the report subgroup. The user of the digital communication network can pull up the 200915 200947958 zou^iwi.aoc/n to lower the input pin of a receiving device Bit (inPut Pin) to a preset voltage level, so that the receiver knows that it is the last receiver. After swapping the roles of its two I/O ports, 'each receiver checks if it is The last receiver of the daisy chain (step 865). If it is the last one, the last receiver outputs the report block and a subsequent termination command block 'the two blocks are encoded via the chain register 702 and output. Buffer 703 is transmitted to first transmission port P1 (step 870). 传输 As with the advancement of the bit signal in the forward protocol, the transmission of the last receiver triggers the transmission of the previous receiver. Each receiver provides a report word. The group, and the last receiver provides a report block and a terminating command block. The series of report blocks and the terminating command block arrive at the microcontroller 501 via the virtual shift register queue described above. The first report block received by the microcontroller 5〇1 is from the first receiver 5〇2 closest to it. The second report block received by the microcontroller 501 is from the second receiver 5〇2, By the order of reception, the microcontroller 501 knows the true source of each report word_group. After outputting the termination command block, the last receiver re-exchanges its two transmission ports, also That is, the input decoding buffer 〇1 is coupled back to the first transmission 埠ρι, and the output encoding buffer 〇3 is coupled back to the second transmission 珲P2 to restore the original transmission direction (step 880). Then the flow returns Step_Heavy·Start Forward Agreement. a. If the check in step 865 shows that the receiver is not the last one, taste the device and wait for the bit signal 8 from the next receiver of the daisy chain; The wide revenue receives the bit signal from the second transmission port 2 (the data bit that has been decompressed in step f is in the chain register 702, as the latest 200947958 ^DUD4twr.aoc/n data bit, and the output is from the chain The oldest data bit of the register 7〇2 is passed to the previous (upstream) receiver. Next, the receiver checks whether all of the data bits stored in the chain register 702 constitute a termination command block from the last receiver ( Step 874). If the terminating command block has not yet entered the chain register 7〇2, the reward agreement is still valid, and the flow returns to step 872 to receive the next bit signal from the latter (downstream) receiver. The group has entered the chain register 702, and the receiver outputs the termination command block to the first transmission port P1 via the output code buffer 7〇3 (step 876). Then, the receiver exchanges its first transmission port P1 again. The role with the second transmission is recovered to the original transmission direction (step 88A). Now, the receiver's reward agreement ends, and the flow returns to step 805 to restart the forward agreement. From the above discussion, it is known in the daisy chain. Every The sequence of the receiver 5〇2 is used as the implicit address of the receiver. Therefore, the communication method of the embodiment provides a two-way transmission method that does not require an address or an identification code (this gift (four) plus code). Each receiver synchronizes its local clock signal with a frequency correction code 602. Initially, prior to synchronization, the local clock signal frequency can be determined based on the resistance of a resistor. Each receiver can be fabricated in the form of an integrated circuit chip. The resistor can be an external resistor R that is lightly connected to the chip, as shown in Figure 5. In this case, the user can easily adjust the initial local clock frequency by controlling the resistance of the external resistor R. In order to minimize the time offset, the external resistors of each receiver 502 preferably have the same resistance value. Each receiver 502 includes a clock generator for providing local time 17 200947958 25054twf.doc/n pulse signal 9 shows the circuit of the clock generator of the embodiment. The clock generator includes a current generator 910, two current mirrors 92〇 and 93〇, a positive feedback booster 940, and a signal shaping. The current generator 91 is connected to the external resistor R. The current mirror 920 is coupled to the current generator 91. The current mirror 930 is coupled to the current mirror 920. The positive feedback oscillator 94 is coupled to the current mirror 930. Signal shaping The current generator 910 is coupled to the positive feedback oscillator 940. The current generator 910 includes an operational amplifier opa ^ VIp which is a reference voltage of a certain Φ value. The virtual short circuit of the operational amplifier OPA makes the voltage at ROUT equal to VIP. The current generator 910 provides a reference current IREF that is inversely proportional to the resistance of the external resistor r. The current mirror 920 provides a current mirror current iM1 based on the reference current iref. Current mirror 930 provides another current mirror current IM2 based on current mirror current IM1. Current mirror 930 also provides a control voltage VBN based on current mirror current IM]L and another control voltage VBP based on current mirror current IM2. The positive feedback oscillator 940 provides a periodic signal pS whose frequency depends on the control voltages VBN and VBP (details are discussed later). The inverters 951 and 952 of the signal shaper 950 form the periodic signal Ps into a local clock signal CLK. The positive feedback oscillator 940 includes seven tri-state inverters 941-947. The tristate inverters 941-947 are identical and are connected in series. Take the first two-state inverter 941 as an example. FIG. 1A shows a circuit of a three-state inverter 941, which includes four metal 〇xide semiconductor field effect transistors (MOSFETs). MP1 and MP2 are p-channel MOSFETs MN1 and MN2 are n-channel MOSFETs. The resistance value of resistor R determines the current of IREF, IM1 and IM2 18 200947958 厶U y» t W ·! · U〇g/π size, while current mirror currents IM1 and IM2 determine the control voltage VBN and VBP respectively. Bit. The control voltage VBP determines the current flowing through the MOSFET MP1 and the control voltage VBN determines the current flowing through the viOSFET MN2. The current flowing through MP1 and _2 determines the output switching rate of the tristate inverter 941. The above three-state inverters 941-947 are identical. Therefore, the resistance value of the external resistor R determines the frequency of the local clock signal CLK. In other embodiments of the invention, the positive feedback oscillator 940 may include more or less tristate inverters. The receiver of this embodiment also has fault tolerance. In the event that the receiver suddenly fails or loses its power supply, the receiver can still transmit bit signals between its transmission ports P1 and P2 to maintain communication with other receivers of the same daisy chain. This is because each receiver contains a bypass circuit. Figure 11 illustrates the bypass circuit of the present embodiment. The bypass circuit is coupled between the first transmission port P1 and the second transmission port P2. The bypass circuit includes diodes D1 and D2, a capacitor CB, resistors R1 and R2, a bypass switch 1101, and a comparator 11〇2. The anode of the diode 1)1 is coupled to the first transfer port P1. The anode of the body D2 is coupled to the second transfer port p2. The cathode of the diode D2 is coupled to the cathode of the diode D1. The capacitor CB has two ends, and the upper end consumes the cathodes of the polar bodies D1 and D2, and the lower end is grounded. The upper end of the capacitor CB is supplied with a capacitor voltage VC. The voltage converter blue includes resistors R1 and R2' and provides a reference voltage VR£F. VRE]p is proportional to the capacitor voltage vc, and the resistance values of fu and R2 are preset to the ratio. Comparison benefit 1102 is coupled to voltage converter 11〇3 for comparison with reference 200947958 · »· ·· a..v»oc/ii voltage ^VRE F and receiver power supply s νρ s. The bypass switch (4) is coupled to the first transmission 埠P1' second transmission 埠P2 and the comparator gift. The bypass switch 1101 turns on or blocks the first transfer port P1 and the second transfer port P2 in accordance with the output of the comparator 1102. In the axillary mosquito, the bit signal from the first pass pl is charged to the battery CB, and the capacitor provides the capacitor voltage %. Diode D1 prevents capacitor CB from discharging and maintains a voltage level of %, while the voltage level of 豢 vc also maintains the voltage level of VREF. Under normal conditions, the power supply vps high financial test voltage VREF, compares the output of 11〇2 to a logic low level. Correspondingly, the bypass switch 11G1 blocks the first transmission port P1 and the second transmission port P2. The transmission ports P1 and ^ are not short-circuited, and the forward agreement is performed as described above. The power of the H 11G2 is compared by the power of the bit from the first transmission port: P1 through the diode D1. ▲When the receiver is damaged or loses its power, the power supply voltage vps will drop, and the output of the comparator 1102 rises to a logic high level lower than the reference voltage VREFe, and the bypass switch 1101 is turned on to turn on the first transmission 埠P1 and the first Two transmissions 埠 P2. Now the 'first transmission 埠ρι is shorted to the second transmission 埠 P2. Although the receiver itself cannot process the bit signal, the bit signal from the first transmission port P1 can be transmitted to the second transmission port P2 without being disturbed. As shown in Figure 11, the bypass circuit is symmetrical. During the return agreement, diode D2 replaces diode D1 to charge capacitor CB and provides power to comparator 1102. The bypass circuit also operates normally during the return agreement. As mentioned earlier, the bypass circuit is fully powered by the bit signal; therefore, 200947958 « * ττ Even if the power of the receiver is ten, the bypass circuit can still operate normally. The embodiment of the present invention provides a digital communication network and an eight-in-one method. The communication method of the above digital communication network is two-way, and the receiver assigns a unique address or an identification code. Single-line transmission reduces the cost of maintenance for women. The clock generator determines the local clock frequency based on the resistance of the resistor. The overall communication clock speed can be adjusted by selecting the appropriate resistor value for each receiver's clock system. In addition, the bypass circuit can still provide fault tolerance when the receiver 坏# is bad or suffers a power interruption. </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> The scope of the invention is defined by the scope of the appended claims. [Simple description of the diagram] Figure 1 shows a traditional digital communication network with a star structure. Figure 2 illustrates a conventional digital communication network with a bus bar structure. Figure 3 illustrates a traditional digital communication network with a daisy-chain structure. Figure 4 illustrates how a synchronized clock signal assists a receiver in correctly decoding the transmitted data. FIG. 5 illustrates a digital communication network according to an embodiment of the invention. FIG. 6 is a diagram showing waveforms of bit signals according to an embodiment of the invention. Figure 7 is a continuation of a portion of the structure of a receiver in accordance with an embodiment of the present invention. FIG. 8 is a flowchart of a communication method according to an embodiment of the present invention. FIG. 9 is a circuit diagram of a clock generator according to an embodiment of the present invention. 10 is a circuit diagram of a tri-state inverter of the clock generator of FIG. 9. 21 x.Joc/n 200947958 FIG. 11 illustrates a bypass circuit of a receiver according to an embodiment of the present invention. [Main component symbol description] 110: main control device Rl-Rn: receiving device 210: main control device 220: common communication channel P: (parallel) data line q: (parallel) address line 310: main control device 401: string Column data pulse 402, 404: synchronization clock 403, 405: interpretation data 501: microcontroller 502: receiver P1: first transmission 埠 P2: second transmission 埠 _ R: external resistor 601: bit signal 602: Frequency correction code 603: Data transmission code 604: Example of frequency correction code Waveform 605: Data transmission code without pulse wave 606: Data transmission code with pulse wave 607: Data transmission code with two pulse waves 22 200947958 z^ U^iwi.doc/n 608: Example waveform 701 of synchronized local clock signal: input decoding buffer 702: chain register 703: output code buffer 711: first data register 712: second data The register 713: the third data register 714: the fourth data register 805-885: the communication method flowchart of the embodiment of the present invention, each step 910: the current generator 920, 930: the current mirror 940: the positive return Oscillator 941-947: Tristate Inverter 950: Signal Shaper 95 Bu 952: Inverter C LK : Local clock signal VIP : Fixed reference voltage OPA : Operational amplifier IREF : Reference current ROUT : Output terminal IM1 , IM2 : Current mirror current VBN : Control voltage VBP : Control voltage PS : Periodic signal 23 200947958 z—JU-iHiwi .uOC/n
MP1、MP2 : p 通道 MOSFET MN1、MN2 : n 通道 MOSFET 1101 :旁路開關 1102 ··比較器 1103 :電壓轉換器 Dl、D2 :二極體 R1 :電阻器 φ R2 :電阻器 VPS :電源供應電壓 VREF :參考電壓 CB :電容器 VC :電容器電壓MP1, MP2: p-channel MOSFET MN1, MN2: n-channel MOSFET 1101: bypass switch 1102 ·· Comparator 1103: voltage converter Dl, D2: diode R1: resistor φ R2: resistor VPS: power supply voltage VREF: reference voltage CB: capacitor VC: capacitor voltage
24twenty four