TW200947881A - Data processing device and data processing method - Google Patents

Abstract

Provided are a data processing device and a data processing method that are configured to improve a tolerance to a data error. A demultiplexer (25) conforms to an allocation rule to allocate code bits of an LDPC code to symbol bits for the expression of symbols. When a code bit of 10 x 2 bits and the (i+1)-th bit from the most significant symbol bit of the 10 x 2 bits of successive two symbols are bi and yi, respectively, the demultiplexer (25) carries out the following replacement by allocating, for example, b0 to y8, b1 to y6, b2 to y0, b3 to y1, b4 to y2, b5 to y3, b6 to y4, b7 to y5, b8 to y7, b9 to y10, b10 to y11, b11 to y12, b12 to y13, b13 to y16, b14 to y14, b15 to y15, b16 to y9, b17 to y18, b18 to y19, and b19 to y17, respecively. The present invention can be applied to a transmission system or the like to transmit the LDPC code, for instance.

Description

200947881 IX. Description of the Invention: [Technical Field] The present invention relates to a data processing apparatus and a data processing method, and more particularly to a data processing apparatus and a data processing method which can improve fault tolerance for, for example, data errors. [Prior Art] The LDPC code has a high degree of error correction capability, and has been widely used in recent years for transmission methods including, for example, DVB (Digital Video Broadcasting)-S.2 satellite digital broadcasting in Europe (refer to ◎ For example, Non-Patent Document 1). Moreover, the LDPC code is also reviewed for use in the next generation of terrestrial digital broadcasting. According to recent research, the LDPC code system is the same as the turbo code, and as the code length increases, the performance close to the Shannon limit is obtained. Moreover, since the LDPC code has a property that the minimum distance is proportional to the code length, it has a good probability of error in the characteristics of the block, and further, as an advantage, it is also said that the decoding characteristic of the turbo code or the like is hardly observed. Error floor phenomenon. Ο Hereinafter, the LDPC code of this type will be specifically described. Further, the LDPC code is a linear code and is not necessarily binary, but is described here as a binary. The biggest feature of the LDPC code is that the parity check matrix (parity check matrix) defining the LDPC code is loose. Here, the loose matrix refers to a matrix in which the number of matrix elements "1" is very small (most of the elements are matrices of 0). Fig. 1 is a diagram showing an example of a check matrix LDP of an LDPC code. 133671.doc 200947881 In Figure 1, the check matrix Η 'the weight of each row (row weight) (the number of "1") (weight) is "3", and the weight of each column (column weight) is "6". The encoding is performed by the LDPC code (LDPC encoding), for example, according to the checking matrix Η, and the generating matrix g is multiplied for the binary information bits, thereby generating a codeword (LDPC code). . Specifically, the encoding apparatus that performs LDPC encoding first calculates a generating matrix G in which the equation GHt = 成立 is established between the transposed matrix Ητ of the check matrix ’. Here, in the case where the generation matrix G is a unitary matrix, the encoding apparatus _ multiplies the bit matrix (vector u) of the information bits composed of the Κ bit by the generation matrix G, and generates a Ν bit. The code word c (= uG). The code word (LDPC code) generated by the encoding device is received on the receiving side via a specific communication channel. The LDPC code decoding system Gallager called Probabilistic Decoding (Probabilistic Decoding) algorithm, which can be used by variable nodes (also known as message nodes ❹ (also known as message nodes ❹ ( The message node))) and the check node are composed of a message propagation algorithm on the so-called Tanner graph (belief pr〇pagati〇n). Here, the variable node and the check node are also hereinafter simply referred to as nodes. Figure 2 is a diagram showing the decoding procedure of the LDPC code. In addition, the value "0" of the third code bit of the LDPC code (1 code word) received by the receiving side represented by the logarithmic probability ratio (1〇g likelih〇〇d rati〇) is suitably hereinafter. The real value of the degree of similarity is called the received value ^ and the message output from the check node is set to Uj, and the message output from the variable node is set to 133671.doc 200947881 is Vi 0. First, the solution of the chat C code ^, as shown in FIG. 2, the receiving (four) code, the message (check node message) 4 initial step: the whole counter of the counter which is the repetitive processing is determined and "〇", and the processing proceeds to step S12. The received value UQi obtained by initializing the variable k of the + as the LDPC code is performed (1 = by the receiving point), to the message (variable f) νι_, ΐ^ (variable section of the message " The operation of the message Uj is performed as shown in the line (7).

[Number 1J dy — 1

Vj=U〇j+ J Ui j=1” • · (l) [Number 2]

Tanh dcH (2) Ο V-^r ) 〇 (row) and ) and (2) ^ and dc are respectively used to check the vertical and ° (column) of the matrix h, the number of "lj can be arbitrarily selected The parameters, for example, in the case of the code (3, 6), dv = 3, dc = 6. Number of cases, eight; 可变 (1) variable node operation and (2) check node operation, Ί鱼Μ The message input from the branch of the message to be outputted (edge: edge): as the object of the operation, the node: ^2 or 1 to d.·1 Moreover, the definition defined by the proof of (2) is pre-made in the form of a function R(Vl, V2) which is not a function of 2 inputs, and is as shown in equation (4) 133671.doc 200947881 is shown to be used continuously (regressively). [Equation 3] x=2tanh~1 (tanh (vt/2)tanh(v2/2) ] =R(Vl [number 4] uj(vi, R (v2 , R (v3, · · -R (vdc_2i )))) (4) In step S12, the variable k is further incremented by ri", and proceeds to step (1). In step S13, whether the variable k is greater than a specific The number of decoding times C is repeated. In step S13, when it is determined that the variable k is not greater than c, (4) S12 is returned, and the following repetition is repeated. In the same step, in step (1), when it is determined that the change μ is larger than c, the process proceeds to step 4', and the operation shown in the equation (5) is performed to obtain and output the UVi, LDpc shape of the decoded wire as the final output. The solution is finished. [5]

Dv • · · (5)

Vj=U〇j+ X Uj j=1 The node operation is different, and the interest is Uj. The check matrix of code length 12) Here, the operation of equation (5) and the variable of equation (1) are from all branches connected to the variable node. Figure 3 shows the (3, 6) LDPC code ( The coding rate 1/2 is the case of Η. The check matrix η in Fig. 3 is the same as the map ,, respectively, the weight of the row is 3', and the weight of the column is 6. Fig. 4 shows the check matrix η of Fig. 3. Tanner diagram. I33671.doc 200947881 Here, in Fig. 4, the check node is represented by "+", and the variable node is represented by "=". The check node and the variable node correspond to the check matrix and The line between the check node and the variable node is a branch (We: edge) which is equivalent to the element of the check matrix "1. That is, when the element of the first row of the jth column of the check matrix is ! The branch is connected by branching from the upper i-th variable node ("the node of ~") and the upper J-th check node (the node of "+"). The branching system represents the code corresponding to the variable node. The bit 兀 has a constraint condition corresponding to the check node. The sum of the LDPC code and the sum of the > γ i code method (Sum Product ©

Alg〇rithm), repeating variable node operations and check node operations. Figure 5 shows the variable node operation performed at the variable node. At the I variable node, the message (10) corresponding to the branch to be calculated is obtained by: the message of the remaining branch of the phase = variable node - and the variable node operation received from the equation (1). The message corresponding to the other branches is also obtained in the same manner. Figure 6 shows the check node operation performed by the check node. The check node operation system of the equation (7) can use the type of heart ❹ 〇 _ 丨 丨 (丨 b丨)} xsign (small sign (b) relationship to rewrite the Lie s (four) X) is based on X time Yu Yu <〇时为卜/, [数6] 133671.doc 200947881 rdc-1

Uj=2tanh—1 丌 tanh V; =2tanh_ =2tanh' exp exp

In tanh

Vi x TT sign tanh

Vi Γ /dI1-JtanhiIVil dc-1 x Π sign(Vj) (6) ❿ Further, in Xg〇, if the function is defined as the formula φ(χ) = ln(tanh(x/2)) ' Established, so the formula (◦ can be transformed into the formula (7). [7] dc-1

Uj = 0_1( Σ x Π sign(Vj) • · · (7) On the checkpoint, the checkpoint operation of equation (2) is based on equation (7). 6. The message corresponding to the branch to be calculated is obtained by (4) the check node operation from the message of the remaining branch connected to the check node ~ '3, ^5 (7). The other branch information is also obtained in the same manner. In addition, the function φ(1) of the equation (7) can also be expressed as (6)=in ((4) difficult _ _ _ _ _ _ 。). When the functions (6) and ΦΛχ are mounted on the hardware, the LUT_um· lookup table is used, but both are the same LUT. 133671.doc 200947881 [Non-Patent Document 1] DVB-S.2: ETSI ΕΝ 302 307 Vl. 1.2 (2006-06) [Summary of the Invention] [Problems to be Solved by the Invention] The LDPC code is a specification for satellite digital broadcasting. The DVB-S.2 or next-generation terrestrial digital broadcast specification is adopted in DVB-T.2. Further, the LDPC code is intended to be used in the next-generation CATV (Cable Television) digital broadcasting specification DVB-C.2. For digital playback in accordance with the specifications of DVB such as DVB-S.2, the LDPC code is used as a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). The symbol is mapped to a signal point and sent. In the symbolization of the LDPC code, the replacement of the code bits of the LDPC code is performed in units of code bits of 2 bits or more, and the replaced code bit is used as the bit of the symbol. The replacement of the code bits for the symbolization of the LDPC code is proposed in various ways, but the proposal is required to improve the fault tolerance of the error compared to the way that has been proposed. The present invention has been made in view of such a situation, and it is possible to improve the error tolerance of errors in data such as LDPC codes. [Technical means for solving the problem] One aspect of the present invention is a data processing device or a data processing method, which is provided with a replacement mechanism or a replacement step, and stores an LDPC (Low) of N bits in a row direction and a longitudinal direction. Density Parity Check: low density 133671.doc -12- 200947881 parity check) the code bit of the aforementioned LDPC code read by the memory unit of the code bit in the preceding direction and read in the preceding direction The m-bit is taken as one symbol, and the specific positive integer is set to b. The memory mechanism stores the mb bit in the foregoing direction and memorizes the N/(mb) bit in the preceding direction, the LDPC code. The code bit is written in the wale direction of the memory means and then read in the course direction, and the code bits of the mb bits read in the direction of the memory mechanism of the memory mechanism are taken as b In the case of the foregoing symbol, the replacement mechanism or replacement step replaces the code bit of the mb bit in accordance with an allocation rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol. Replaced code bit The foregoing symbol bit; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the foregoing symbol bit groups according to the error probability. As a group of symbol bits, and defining a rule of the foregoing code bit group of the foregoing code bit element and the foregoing symbol element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated The combination of the bit groups is a group set; and the foregoing code bit group of the group set and the bit code element of the foregoing symbol bit group and the bit number of the foregoing symbol bit. The foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 10 bits, and the aforementioned integer b is 2, the foregoing code bits When the 10-bit element is mapped to one of 210, that is, 1024 signal points as one of the preceding symbols, the code bit of 10x2 bits read in the foregoing direction of the memory mechanism The group is divided into 5 groups of the preceding code bits; the group of 10x2 bits 133671.doc -13- 200947881 of the preceding two symbols is divided into 5 symbol group The foregoing allocation rule is as follows: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the symbol bit of the fifth good symbol bit group of the error probability 1 bit; assign 1 bit of the code bit of the 2nd good code bit group of the error probability to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; The error probability is the 4th bit of the code bit of the 3rd good code bit group. It is assigned to the 4 bit of the symbol bit of the first good symbol bit group of the error probability. The 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the 4th bit of the symbol bit of the second good symbol bit of the error probability; the error probability The 2 bits of the code bit of the 3rd good code bit group are allocated to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; the error probability 3rd good code 1 bit of the code bit of the bit group, assigned to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability 4th good code bit group 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the code bit of the 5th good code bit group of the error probability 2 bits, assigned to the 2nd bit of the symbol bit of the third good symbol bit group of the error probability; 1 bit of the code bit of the 5th good code bit group of the error probability, Assigned to the 1-bit of the symbol bit of the 4th good symbol bit group of the error probability; and assigns the 3 bits of the code bit of the 5th good code bit group of the error probability to the error Symbol bits of the symbol bit group of the element of good character Rate 5 3 yuan. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2; the aforementioned m bits are 10 133671.doc • 14- 200947881 is located at 478, and the integer 15 is 2, and the 1st bit of the code bit is mapped as one of the 24 signal points determined by 1〇24QAM as one of the aforementioned symbols 7L; the memory mechanism includes In the case where two 纵 纵 〇χ 〇χ 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 The iQ bit is set to the bit bi from the most significant bit, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are counted from the most significant bit. The i bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: ® assigns the bit % to the bit yS, assigns the bit b! to the bit y6, and assigns the bit b2 to the bit yG, assigning the bit h to the bit y!, assigning the bit center to the bit 兀 y2, assigning the bit bs to the bit y; j, assigning the bit b6 to the bit y4, and allocating the bit b7 Giving bit ys Assigning the bit bs to the bit, assigning the bit b9 to the bit y1Q, assigning the bit biG to the bit yii, and assigning the bit bn to the bit yis 'Assigning the bit bu to the bit is 3 Assigning the bit to the bit yu, assigning the bit bM to the bit y14, assigning the bit bi5 to the bit 兀 y! 5, assigning the bit b10 to the bit, and allocating the bit bi7 to the bit The element yw assigns the bit bu to the bit yi9 ' to assign the bit to the bit yi7. The foregoing LDPC code is an LDPC code whose code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64800 bits, the m-bit is 10 bits, and the aforementioned integer b is 2, the foregoing code In the case where one bit of the bit is mapped to one of 21Q, that is, 1024 signal points, as the preceding symbol, the aforementioned code of 10x2 bits read in the foregoing direction of the memory mechanism The bit system group is divided into five preceding code bit groups; the first two symbols of the preceding symbol are 1〇><2 bits of the preceding symbol bit group are divided into five symbol bit groups Group; prior to 133671.doc •15-200947881 The allocation rules are as follows: assign 1 bit of the code bit of the first good code bit group of the error probability to the 5th good symbol of the error probability. 1 bit of the symbol bit of the metagroup; assign 1 bit of the code bit of the 2nd good code bit group of the error probability to the symbol of the 5th good symbol bit group of the error probability 1 bit of the meta-bit; assign 4 bits of the code bit of the 3rd good code bit group of the error probability to the symbol of the first good symbol group of the error probability 4 bits of the bit; 3 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the 3 bits of the symbol bit of the second good symbol bit group of the error probability Yuan; the 4th bit of the code bit of the 3rd good code bit group 错误 of the error probability is assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; The 1st bit of the code bit of the 4th good code bit group is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 5th good 1 bit of the code bit of the code bit group, assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 5th good code bit group of the error probability The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 4th good symbol bit group of the error probability; and the code point of the 5th good code bit group of the error probability Μ The 2 bits of the element are allocated to the 2 bits of the symbol bit of the 5th good symbol group of the error probability. The foregoing LDPC code is a LDPC code having a code length 规定 of 64,800 bits and a coding rate of 2/3 as defined by the specification of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. 133671.doc -16- 200947881 In the case of memory 64800/(10x2) bits in the wale direction, the 10x2 bit code bits read from the course of the memory mechanism are from the most significant bit. Calculating that the i+th bit is set to the bit bi, and that the iq + 1 bit of the symbol of the 10x2 bit of the two consecutive symbols is set to the bit yi from the most significant bit, According to the foregoing allocation rule, the following substitutions are respectively made: the bit bG is allocated to the bit ys, the bit bi is allocated to the bit element, the bit is allocated to the bit yG, and the bit h is assigned to the bit force, Assigning the bit 匕 to the bit 'allocating the bit h to the bit' assigns the bit b6 to the bit, assigns the bit h to the bit ys, and assigns the bit bs to the bit yi. Assigning bit b to bit yu, assigning bit biG to bit yi2, assigning bit bn to bit yM, assigning bit b!2 to bit yi5, assigning bit by to bit Element y0, assigning bit unit bu to bit element, assigning bit element to bit element yi 3, assigning bit element bi 6 to bit element y 〗 8, and assigning bit element b ^ 7 to bit y 9 'Assign the bit bu to the bit yi0 and the bit bi9 to the bit 7. The foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 1 〇 bit, and the integer b is 2, the foregoing code bit element When the one bit is mapped as one of the two symbols, that is, one of 1024 signal points, the code bit system of the bit read in the row direction of the memory mechanism group

1 bit of the symbol bit of the group F. The error probability first good code bit group is assigned to the error probability 5th good symbol bit element; the error probability 2nd good code bit group 133671 .doc 17 200947881 2 bits of the code bit, assigned to the 2 bit of the symbol bit of the first good symbol group of the error probability; the second probability of the error probability group 4 bits of the code bit, assigned to the 4th bit of the symbol bit of the second good symbol bit group of the error probability; the code bit of the second good code bit group of the error probability 2 bits, allocated to the 2 bits of the symbol bit of the 3rd good symbol bit group of the error probability; the 2 bits of the code bit of the 2nd good code bit group of the error probability are allocated Give the 2nd bit of the symbol bit of the 4th good symbol bit group of the error probability; assign the 3 bit of the code bit of the 2nd good code bit group of the error probability to the error probability 5th a good symbolic element 3 a 3-bit symbol of the group of bits; assigning the 1st bit of the code bit of the 3rd good code bit group of the error probability to the error probability 1st 1 bit of the symbol bit of a good symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the first good symbol of the error probability 1 bit of the symbol bit of the metagroup; 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the symbol of the 3rd good symbol bit group of the error probability 2 bits of the meta-bit; and 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the symbol of the 4th good symbol bit of the error probability 2 yuan of yuan. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. In the case where the memory is 16200/(10x2) bits in the wale direction, the code bits of the l〇x2 bits read from the course direction of the memory device in the first 133671.doc -18-200947881 are The most significant bit counts that the i+th bit is set to the bit bi ' and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are set from the most significant bit and the first +1 bit is set. The bit yi, according to the foregoing allocation rule, respectively performs the following substitutions: assigning the bit bQ to the bit ys, assigning the bit b] to the bit yQ, and assigning the bit h to the bit yi, the bit h Assigned to a bit, assigning bit b4 to bit 'Assign bit b5 to bit ye, bit b6 to bit Y5', assign bit t>7 to bit y0, place bit Bg is assigned to bit y7, bit b>9 is assigned to bit y?, bit b1G is assigned to bit yi2, bit bn is assigned to bit y13, bit b!2 is assigned to bit Yi8, assigning bit bi3 to bit 7!9, assigning bit to bit yiQ, assigning bit ^5 to bit y!6, assigning bit bw to bit, and allocating bit bi7 The bit yn is assigned, the bit bu is assigned to the bit yis, and the bit bi9 is assigned to the bit. The foregoing LDPC code is a LDPC code of a code length N defined by the specification of DVB_S2 or DVB_T 2 of 64800 bits; the aforementioned bit position is 1 unit, and the aforementioned integer b is 2 'the hard element of the above code bit as i In the case where the preceding symbols are mapped to 210, that is, one of 24 跋 ± ± ι 乜唬 ± ± , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The meta-group group area is: the foregoing code bit group; the two consecutive symbols of the purchase of the above-mentioned symbols are divided into 5 symbol group groups; The rule stipulates that if r is the probability of the first bit of the code bit group of the good code bit group, it is the symbol bit of the fifth good symbol bit group assigned to the error probability. Li Wei, the 1st bit of the code bit of the 2nd good code bit group of the error probability, ^ ' is the symbol error probability 4th good symbol bit 133671.doc -19- 200947881 group symbol 1 bit of the bit; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the first good symbol bit group of the error probability 4 bits of the symbol bit of the group; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the symbol bit of the 2nd good symbol bit group of the error probability 4 bits of the element; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the 4 bit of the symbol bit of the 3rd good symbol bit group of the error probability Assigning 1 bit of the code bit of the 3rd good code bit group of the error probability to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 4 good code bit group © the 2 bits of the code bit element, assigned to the 2 bit of the symbol bit of the 4th good symbol bit group of the error probability; and the error probability is 4th good The 3 bits of the code bit of the code bit group are assigned to the 3 bits of the symbol bit of the 5th good symbol bit group of the error probability. The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the above-mentioned code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the aforementioned symbols; the memory mechanism contains 20x2 bits in the horizontal direction. In the case of a longitudinal row, in the case of memory 64800/(10x2) bits in the longitudinal direction, the code bits of 1 〇χ 2 bits read out in the direction of the memory mechanism are counted from the most significant bit. The i+Ι bit is set to the bit\, and the symbol of the 10x2 bit of the preceding two symbols is calculated from the most significant bit, and the i+th bit is set to the bit yi, according to the foregoing allocation. Rules, respectively, replace the following: assign bit bG to bit y8, bit b] to bit y6, bit 133671.doc -20- 200947881 b2 to bit yG, bit b3 Assigned to bit y! 'Assign bit b4 to bit y2, bit b5 to bit ys, bit b6 to bit 丫4, bit #>7 to bit ys, will The element t»8 is assigned to the bit y7, the bit b9 is assigned to the bit yi G, the bit b1G is assigned to the bit yi 1, and the bit b is assigned to the bit yi2 'the bit b!2 is assigned to The bit yi3 assigns the bit b13 to the bit yM, the bit b!4 to the bit yi5, and the bit b15 to the bit y9' to assign the bit b!6 to the bit y, 6, The bit b 7 is assigned to the bit yn, the bit bls is assigned to the bit yu, and the bit bi9 is assigned to the bit force 9.前述 The foregoing LDPC code is an LDPC code with a code length N defined by the specifications of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 1 unit, and the aforementioned integer b is 2, the foregoing When one bit of the code bit is mapped as one of the two symbols, that is, one of 1024 signal points, one of the above-mentioned courses in the direction of the memory mechanism is read. The 2-bit symbol group is divided into three groups of the aforementioned bit-bit groups; the preceding symbol-bit group of the two consecutive symbols is divided into five symbols. The bit group; the foregoing allocation rule is as follows: assigning the 4 bits of the code bit of the code bit group with the wrong probability probability to the symbol of the error probability κ good symbol bit group 4 bits of the meta-bit; assign the 3 bits of the code bit of the error probability A-good code bit group to the symbol bit of the 2nd good symbol bit group of the error probability Bit; assign the i bit ' of the code bit of the first good bit of the error probability group to the bit error of the third good symbol bit group of the error probability; The probability of the third-good code bit group, the 3-bit element, is assigned to the 3-bit symbol of the symbol bit of the error probability q-th good symbol group; Code bit group 133671.doc -21 200947881 The 4 bits of the code bit group are assigned to the 4th bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability is 2nd good 1 bit of the code bit of the code bit group, assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 3rd good code bit group with the error probability One bit of the code bit of the group, one bit allocated to the symbol bit of the second good symbol bit group of the error probability; the code bit of the third good symbol bit group of the error probability 2 bits, 2 bits assigned to the symbol bit of the 3rd good symbol bit group of the error probability; and 1 bit of the code bit of the 3rd good code bit group of the error probability , assigned to the error probability 4th good symbol bit © 1 unit of the symbol group of the meta-group. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 4/5 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. In the case where 16200/(10x2) bits are memorized in the wale direction, the code bits of 10x2 bits read out from the direction of the memory mechanism are counted from the highest w effective bits. The +1 bit is set to the bit bi, and the symbol of the 10x2 bit of the preceding two symbols is calculated from the most significant bit, and the i+th bit is set to the bit yi, according to the foregoing allocation rule. Replacing the following respectively: assigning bit bG to bit yG, assigning bit b! to bit y!, assigning bit b2 to bit y2, and assigning bit b3 to bit y3, Bit b4 is assigned to bit y4, bit b5 is assigned to bit y6, bit b6 is assigned to bit y7, bit b7 is assigned to bit y8, bit b8 is assigned to bit ys>, will 133671.doc -22- 200947881 Bit TLb9 is assigned to bit yIQ 'Assign bit 1)1() to bit, bit b" is assigned to bit yi2' to assign bit 匕2 to bit bit Yuan Bu 3 is assigned to bit force 8 ' to assign bit to bit yi?, bit ^5 is assigned to bit 兀 ys, bit 兀 is allocated to bit yM, and bit bi7 is assigned to bit Yw, the bit bls is assigned to the bit yis, and the bit bi9 is assigned to the bit. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB_S.2 or DVB_T 2 of 64800 bits; the aforementioned m bit is 1 〇 bit and the aforementioned ❹ integer b is 2, and the hard bit of the above code bit is In the case where one of the two symbols, i.e., one of 24 k 24 k-points, is mapped to the i-th symbol, the code-bit group of the heart bit read in the row direction of the memory mechanism is The group is divided into three groups of the aforementioned code bit groups; the group of the preceding symbol bit groups of the (7) heart bits of the consecutive two preceding symbols is divided into five groups of symbol bits; The following is the case: the error probability is the first good element of the k-bit group of the K-members, and the error probability is the 4th good symbol-bit group, and the error is the first reading; The bit position of the code bit group is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 2nd good code bit group of the error probability is 4 bits of the element, assigned to the 4th bit of the symbol bit of the 1st good symbol bit group of the error probability; the code of the 2nd good code bit group of the error probability 4 bits of the bit, the distribution of the knife is matched, and the probability of the second block of the bit error block is 4 digits of the symbol bit. The spleen is twisted and the error probability is 2nd. The 3 bits of the code bit group of the code bit group are allocated for the knife, and the 0. 0 error probability is the 3rd good symbol group of the symbol bit. The box probability is 2nd. The code bit group, and the code bit το 3 bits 疋 'assigned to the error probability 4th good symbol bit 133671.doc -23· 200947881 group of the symbol bit 3 bits; error probability 1 bit of the code bit of the 3rd good code bit group, 1 bit allocated to the symbol bit of the 3rd good symbol bit group of the error probability; and the error probability is 3rd. The 3 bits of the code bit of the code bit group are assigned to the 3 bits of the symbol bit of the 5th good symbol bit group of the error probability. The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 4/5 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the above-mentioned code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the aforementioned symbols; the memory mechanism contains 20x2 bits in the horizontal direction. In the case of a wales, in the case of a memory of 64800/(10x2) bits in the wale direction, the code bits of the 10x2 bits read out in the course direction of the memory mechanism are i+ from the most significant bit. The Ι bit is set to the bit bi, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are set from the most significant bit to the i-th bit as the bit yi, according to the foregoing allocation rule. The following replacements are respectively made: bit p 〇 is assigned to bit y8, bit b 1 is assigned to bit y6, bit ◎ b2 is assigned to bit y 〇, and bit b3 is assigned to bit y! Bit b4 is assigned to bit y2, bit b5 is assigned to bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y7 , Bit b9 is assigned to bit yi 〇, bit bi 〇 is assigned to bit y!!, bit b! 1 is assigned to bit y! 2, bit b! 2 is assigned to bit y! 3 Assigning bit b! 3 to bit y 14, assigning bit b! 4 to bit y 16, assigning bit b 15 to bit y 17, assigning bit b! 6 to bit y9 The bit b! 7 is assigned to the bit y! 5, the bit b! 8 is assigned to the bit y! 8, and the bit b 1 9 is assigned to the bit y 1 9 . 133671.doc -24- 200947881 The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 16200 bits; the aforementioned m bit is 10 bits, and the aforementioned integer b is 2, and when 10 bits of the code bit are mapped to one of 21 (), that is, 1024 signal points as one of the symbols, read in the course direction of the memory means. The group of 10x2 bits of the preceding code bit group is divided into 4 groups of the aforementioned code bit groups; the preceding symbol bit group group of 10x2 bits of two consecutive symbols is divided into 5 symbol bit groups. The foregoing allocation rule is defined as follows: assigning the 1-bit of the code bit of the first good code bit group® of the error probability to the symbol of the fifth-perfect symbol group of the error probability 1 bit of the bit; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to 4 bits of the symbol bit of the first good symbol bit group of the error probability The third bit of the code bit of the second good symbol bit group of the error probability is assigned to the three bits of the symbol bit of the second good symbol bit group of the error probability The second bit of the code bit of the second good symbol bit group of the error probability is assigned to the two bit of the symbol bit of the third good symbol bit group of the error probability; The 4th bit of the code bit of the second good code bit group W is allocated to the 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 2nd good. 2 bits of the code bit of the code bit group, assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability 3rd good code bit group 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 4th good code bit group of the error probability 1 bit, assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; and the 4th good code bit of the error probability 133671.doc •25- 200947881 Group code The 2 bits of the bit are allocated to the 2 bits of the symbol bit of the symbol group of the 3rd good symbol of error probability. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 5/6 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. In the case where 16200/(10x2) bits are memorized in the wale direction, the code bits of the 10x2 bits read in the course direction of the memory mechanism are counted from the highest valid bit to be i+Ι The bit is set to the bit bi, and the symbolic element of the 10x2 bit of the preceding two symbols is set from the most significant bit to the i-th bit as the bit yi, according to the foregoing allocation rule, respectively The following substitutions are made: the bit bQ is assigned to the bit y8, the bit b! is assigned to the bit yG, the bit b2 is assigned to the bit y!, and the bit b3 is assigned to the bit y2, the bit is allocated B4 is assigned to bit y3, bit b5 is assigned to bit y4, bit b6 is assigned to bit y5, bit b7 is assigned to bit y6, bit b8 is assigned to bit y7, 〇 The element b9 is assigned to the bit y9, the bit b!〇 is assigned to the bit y 1 〇, the bit wbi! is assigned to the bit yn, and the bit b! 2 is assigned to the bit y 12, the bit b is 13 is assigned to the bit y 16, the bit b! 4 is assigned to the bit y 1 7 , the bit b 1 5 is assigned to the bit y 18 , and the bit b ! 6 is assigned to the bit y 1 9 Bit b! 7 is assigned to bit y14, bit b18 is assigned to bit y15, and bit b19 is assigned to bit y13. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; the m-bit is 10 bits, and the aforementioned integer b is 2, the foregoing code bits When the 10-bit element is mapped as one of the preceding symbols and 133671.doc -26-200947881 is 21 () or any of 1 024 signal points, it is read in the foregoing direction of the memory mechanism. The group of the preceding code bit groups of 10×2 bits is divided into 5 groups of the aforementioned code bit groups; the group of the preceding symbol bit groups of 10 consecutive 2 bits of the preceding two symbols is divided into 5 symbol bits. The above-mentioned allocation rule is defined as follows: assigning 1 bit of the code bit of the first good code bit group of the error probability to the symbol of the 5th good symbol bit group of the error probability 1 bit of the bit; 1 bit of the code bit of the 2nd good code bit group of the error probability is assigned to the symbol bit of the 4th good symbol bit of the error probability Bits; 4 bits of the code bits of the 3rd good code bit group of the error probability are assigned to the 4th bit of the symbol group of the first good symbol bit group of the error probability The 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the 4th bit of the symbol bit of the second good symbol bit group of the error probability; The 4th bit of the code bit of the 3rd good code bit group is allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the error probability 3rd good code 2 bits of the code bit of the bit group, assigned to the 2 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability 4th good code bit group 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; and the code bit of the 5th good code bit group of the error probability 3-bit, assigned to the 3-bit symbol of the symbol element of the 5th good symbol group of the error probability. The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and the 10 bits of the above-mentioned code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the first 133671.doc -27·200947881 symbols, and the memory mechanism is included in the course. Direction memory 〇x2 bits of 2 纵 ,, in the case of memory 64800/(10x2) bits in the waling direction, 丨〇x 2 bits read in the course direction of the above 5 mnemonic mechanisms The i-th bit of the meta-bit is set to the bit bi from the most significant bit, and the symbol of the 10x2 bit of the two consecutive symbols is counted from the most significant bit. The +1 bit is set to the bit yi 'in accordance with the foregoing allocation rule', and the following replacement is performed: assigning the bit bQ to the bit yg, assigning the bit b] to the bit %, and assigning the bit t > Bit yQ, assigning a bit to bit yi, assigning bit b4 to a bit, assigning bit h>5 to bit ys, and assigning bit b6 to bit y4 'bit t» 7 assigned to the bit Ys, the bit bs is allocated to the bit y7, the bit h is assigned to the bit y1Q 'the bit blG is assigned to the bit yn, the bit b ! is assigned to the bit y 〗 2, the bit b 2 is assigned to bit y 丨 3, bit b 3 is assigned to bit yM, bit bM is assigned to bit yi5, bit bls is assigned to bit y 1 6 , bit b ! 6 is assigned The bit y 1 7 is assigned a bit b ! 7 to the bit y9, the bit bls is assigned to the bit yi8, and the bit b19 is assigned to the bit yi9. The foregoing LDPC code is MPEG-S.2 or DVB-T.2, and the code length © N is a 16200-bit LDPC code; the aforementioned πι bit is 10 bits, and the aforementioned integer b is 2 'the aforementioned code When one bit of the bit is mapped to one of 21Q, that is, 1024 signal points, as one of the above symbols, the aforementioned 10x2 bits read in the row direction of the essay mechanism are as described above. The code bit group is divided into five groups of the aforementioned code bits; the preceding two symbols of the symbol ><2 bits of the preceding symbol bit group are divided into five symbol bits Group; the foregoing allocation rule is as follows: assigning the error probability first good code bit 133671.doc -28- 200947881 group code bit 2 bits to the error probability 5th good symbol bit 2 bits of the symbol bit of the metagroup; assign 1 bit of the code bit of the 2nd good code bit group of the error probability to the symbol of the 3rd good symbol bit group of the error probability 1 bit of the meta-bit; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the symbol of the first good symbol bit group of the error probability 4 bits of the bit; assign 4 bits of the code bit of the 3rd good code bit group of the error probability to 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability Yuan; assigns the 3 bits of the code bit of the 3rd good code bit group® of the error probability to the 3 bit of the symbol bit of the 3rd good symbol bit group of the error probability; The 3 bits of the code bit of the 3rd good code bit group are assigned to the 3 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 4th good. 1 bit of the code bit of the code bit group, 1 bit allocated to the symbol bit of the 4th good symbol bit group of the error probability; and the 5th good code bit group with the error probability The 2 bits of the group of code bits are assigned to the 2 bits of the symbol bit of the 5th good symbol bit group of the error probability. ^ The foregoing LDPC code is a LDPC code with a code length N of 16200 bits and a coding rate of 8/9 as specified in the specification of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the foregoing The integer b is 2, and the 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 memories of 10x2 bits in the horizontal direction. In the case of wales, in the case of storing 16200/(10x2) bits in the wale direction, the code bits of the 10x2 bits read in the course direction of the memory mechanism are counted from the most significant bit by the i + Ι The bit is set to the bit bi, and the i+i bit of the consecutive 1st 133671.doc -29-200947881 symbol 10x2 bit is set from the most significant bit to the bit yi According to the foregoing allocation rule, the following replacements are respectively performed: assigning the bit bQ to the bit y8, assigning the bit b] to the bit y9, assigning the bit b2 to the bit y4, and allocating the bit b3 to the bit Yuan y, assigning bit b4 to bit y!, assigning bit 1 > 5 to bit y; 2 ' assigning bit b6 to bit y3, assigning bit b? to bit ys, will The bit bs is allocated to the bit y6, the bit h is assigned to the bit y7, the bit b1() is assigned to the bit y]G, the bit b!! is assigned to the bit y〗 i, and the bit is allocated b] 2 is assigned to bit yi 2, bit b is assigned to bit 7 丨 3, bit bw is assigned to bit y14, bit b15 is assigned to ◎ bit yi5, bit b! 6 is assigned to bit y16, bit b17 is assigned to bit y!7, bit bls is assigned to bit y18, and bit bi9 is assigned to bit. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; the m-bit is 1 bit, and the aforementioned integer b is 2, the foregoing code When one bit of the bit is mapped as one of the two symbols, that is, one of 1024 signal points, the code of 1Qx2 bits read in the course direction of the memory mechanism is used. Bit group

1 bit of the code bit group, 1 bit of the symbol bit bit of the group; 4 bits of the code bit element of the group, sub-string «: F : assign the first good code bit group of the error probability to The error probability fifth good symbol bit element; the error probability second good symbol bit group is assigned to the error probability fourth good symbol bit 疋; the error probability third good code bit group is assigned to Error probability first good symbol bit 133671.doc -30- 200947881 group of 4 bits of the symbol bit; 4th bit of the code bit of the 3rd good code bit group of the error probability, 4 bits assigned to the symbol bit of the second good symbol bit group of the error probability; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the error probability 3 4 bits of the symbol element of the good symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the 4th good symbol of the error probability 1 bit of the symbol bit of the bit group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the 5th good symbol of the error probability 1 bit of the symbol bit of the bit ® group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the 4th good symbol bit group of the error probability 1 bit of the symbol bit; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the symbol bit of the 4th good symbol group of the error probability 1 bit; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the 1 bit of the symbol bit of the 5th good symbol bit group of the error probability . The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 8/9 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. In the case where 64800/(10x2) bits are memorized in the wale direction, the code bits of the 10x2 bits read in the course direction of the memory mechanism are counted from the most significant bit to the i+1th bit. The element is set to the bit bi, and the symbol of the 10x2 bit of the preceding two symbols is calculated from the most significant bit, and the i+th position 133671.doc -31 - 200947881 is set to the bit yi, According to the foregoing allocation rule, the following substitutions are respectively made: the bit bG is assigned to the bit ys 'the bit h is assigned to the bit y9, the bit t>2 is assigned to the bit y0, and the bit t>3 is assigned To the bit yG, the bit b4 is assigned to the bit y! 'The bit b5 is assigned to the bit y2, the bit b6 is assigned to the bit Y3, and the bit I)·; is assigned to the bit y4, The element bs is assigned to the bit y5, and the bit b9 is assigned to the bit y? 'The bit b1() is assigned to the bit yiQ, the bit b" is assigned to the bit yu, and the bit bu is assigned to the bit Yu, the bit b13 is assigned to the bit 7!3, the bit bw is assigned to the bit, the bit b15 is assigned to the bit yi5 'the bit b!6 is assigned to the bit yls' and the bit b17 is allocated The bit ◎ yu ' assigns the bit bls to the bit yn and the bit b19 to the bit y19. The foregoing LDPC code is an LDPC code whose code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64800 bits; the aforementioned m bit is a bit, and the aforementioned integer b is 2, the foregoing code bit element When the 10-bit is mapped as one of the two symbols, that is, 1024 signal points, the above-mentioned code position of 1〇x2 bits read in the direction of the above-mentioned memory mechanism The meta-group is divided into three groups of the aforementioned code-bits; the group of the two-character (7) heart-bits of the preceding symbols is divided into five groups of symbols; The allocation rule is defined as follows: 2 bits of the code bit of the first good code bit group of the error probability are assigned to 2 bits of the symbol bit of the 5th good symbol bit group of the error probability. The fourth bit of the code bit 7L of the second good code bit group of the error probability is assigned to the 4 bit of the 7L bit TG of the first good symbol bit group of the error probability; The 3rd bit of the code bit το of the 2nd good code bit group 2 is assigned to the 4th bit of the 4th bit of the error probability 2nd good symbol bit group; the error probability is 2nd good Code bit group 133671.doc -32· 200947881 The 4 bits of the code bit group are assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the error probability is 2nd 4 bits of the code bit of the good code bit group, 4 bits assigned to the symbol bit of the 4th good symbol bit group of the error probability; the 2nd good code bit of the error probability 1 bit of the code bit of the group, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability 1 bit of the element, 1 bit assigned to the symbol bit of the 2nd good symbol bit group of the error probability; and 1 of the code bits of the 3rd good code bit group of the error probability The bit is assigned to one bit of the symbol bit of the fifth-perceived symbol bit group of the error probability. The foregoing LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2, and 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes 20 vertical memories of 10x2 bits in the horizontal direction. In the case where 64800/(10x2) bits are memorized in the wale direction, the code bits of 10x2 bits read out in the course direction of the memory device are counted from the most significant bit. The Ι bit is set to the bit bi, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are set from the most significant bit to the i-th bit as the bit yi, according to the foregoing allocation rule. The following replacements are respectively made: bit bit bG is assigned to bit y8, bit b! is assigned to bit y9, bit b2 is assigned to bit yQ, bit b3 is assigned to bit yi, bit is allocated B4 is assigned to bit y2, bit b5 is assigned to bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y6, 133 671.doc -33- 200947881 bit t>9 is assigned to bit y7, bit biQ is assigned to bit yiQ, bit bn is assigned to bit 7Lyu, bit 2 is assigned to bit, bit is allocated ^3 is assigned to the bit yM, the bit b]4 is assigned to the bit yis, the bit bi5 is assigned to the bit y10 'the bit is assigned to the bit yn, and the bit bi7 is assigned to the bit y!8 'The bit bls is assigned to the bit yis, and the bit bi9 is assigned to the bit edge 3. The aforementioned LDPC code is a code length (four) 16200-bit LDPC code specified by the specification of DVB-S.2 or DVB-T.2; the aforementioned m-bit is a bit, and the aforementioned integer b is 2' of the aforementioned code bit. Bits are mapped as one of the preceding symbols

In the case where two, that is, 4096 signals, one of the l=t current points, the group of the above-mentioned code bit groups read out in the aforementioned direction of the memory mechanism is divided into 4 preceding groups of code bits; 2 consecutive symbols of the preceding symbols. The foregoing symbol bit group of the bit is divided into 6 symbol bit groups; the foregoing allocation rule is as follows: the code bit of the code bit group of the error probability β is better. 'Assigned to the error probability with 1 bit of the symbol bit of the good symbol bit group; assign the error probability 2nd good code bit group, 'and the code bit TL 1 bit 70 ' to the error Probability 5th good symbol bit

The group is 70-bit 70-bit one-bit; the fourth-order TL of the error probability third good code bit group and the code bit 7L is assigned to the symbol of the error probability κ good symbol group 4 bits of the meta-bit; 2 bits of the code bit of the 3rd good code bit group of the error probability, the twist and match, ·, the error probability 2nd good symbol bit group 2 bits of the it bit; 4 bits of the code bit of the 3rd good code bit group of the error probability, and the 3rd good symbol group of the error probability 4 bits of the symbol bit; assign the code bit group with the wrong probability probability to the error probability 4th good symbol bit 133671.doc •34- 200947881 3 bits of the symbol bit of the group Assigning 1 bit of the code bit of the 3rd good code bit group of the error probability to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; 4 2 bits of the code bit of the good code bit group, 2 bits assigned to the symbol bit of the 2nd good symbol bit group of the error probability; the 4th good code position of the error probability Metagroup 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the code bit of the 4th good code bit group of the error probability 2 bits, 2 bits assigned to the symbol bit of the 5th good symbol bit group of the error probability; and 3 bits of the code bit of the 4th good code bit group of the error probability , assigned to the 3-bit symbol of the symbol element of the 6th good symbol group of the error probability. The foregoing LDPC code is a LDPC code having a code length 16 of 16200 bits and a coding rate of 2/3 as defined by the specification of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 vertical memories of 12x2 bits in the horizontal direction. ^, in the case of memory 16200/(12x2) bits in the wale direction, the iq+1 of the 12x2 bit coded from the direction of the memory mechanism is counted from the most significant bit. The bit is set to the bit bi, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the most significant bit to the i-th bit as the bit yi, according to the foregoing allocation rule. Replace the following: Assign bit bG to bit y!. Assigning bit b! to bit y8, assigning bit b2 to bit y, assigning bit b3 to bit, assigning bit b4 to bit y2, and assigning bit b5 to bit Y3, assigning bit b6 to bit 133671.doc -35- 200947881 y"4, assigning bit b7 to bit y5, assigning bit b8 to bit y6, and assigning bit t»9 to bit Element y7, assigning bit b 1 〇 to bit y9, assigning bit b JJ to bit y! 2 ' assigning bit b 2 to bit y! 3, assigning bit b! 3 to Bit yi 6 ' assigns bit b! 4 to bit y 17, assigns bit bi 5 to bit y 1 8 ' assigns bit b ! 6 to bit y2G 'distributes bit b 7 The bit element 'is allocated the bit element yil to the bit yil, the bit b19 to the bit y22, the bit b2 〇 to the bit y23, and the bit b2 1 to the bit y2 I, the bit 1 > 22 is assigned to bit yi5, and bit b23 is assigned to bit yi9. The foregoing LDPC code is a LDPC code of a 64800-bit code length specified by the specification of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, the foregoing code When 12 bits of the bit are mapped as one of the two symbols, that is, 4096 signal points, the 12 bits read in the direction of the memory mechanism are >< 2 bits The group of the preceding code bit groups is divided into four groups of the aforementioned code bit groups; the group of consecutive two 刚 2 χ 2 bits of the preceding symbol is divided into six symbol bit groups; Before

The allocation rule is to specify one bit of the code bit of the group, and the following: assign the first good code bit group of the error probability to the sixth bit symbol group of the error probability and the bit of the symbol bit. The first bit of the code bit 7L of the second good code bit group of the error probability is assigned to the sixth bit symbol group with the wrong probability, and the 7L bit 70 is the bit; The 4th bit of the 3th good code bit group is assigned to the 4th bit of the symbol bit of the error probability 1st good symbol bit group. The bit error probability 3 good code bit group code bit 4彳fr ; , heart position 70, assigned to the error probability 2nd good symbol bit group 4 bit number, the error probability 3 good code bit group 133671.doc -36- 200947881 group of 2 bits of code bit, assigned to the 2nd bit of the symbol bit of the 3rd good symbol bit group of the error probability; The 3 bits of the code bit of the 3rd good code bit group are assigned to the 3 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 3rd. 1 bit of the code bit of the good code bit group, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the 4th good code bit of the error probability 2 bits of the code bit of the group, assigned to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; the code of the 4th good code bit group of the error probability 1 bit of the bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 3 bits of the code bit of the 4th good code bit group of the error probability Yuan, assigned to the 3-bit symbol of the symbol element of the 5th good symbol group of the error probability; and the 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to The error probability is 6th in the 6th good symbol group. The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the foregoing The integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 memory 12x2 bits in the horizontal direction. In the case of wales, in the case of memory 64800/(12x2) bits in the wale direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bit i+Ι The bit is set to the bit bi, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the most significant bit to the i-th bit, and the bit yi is set according to the foregoing allocation rule. The following substitution is made: 133671.doc -37- 200947881 assigning bit bG to bit y1Q, assigning bit 匕 to bit yil, assigning bit fc>2 to bit yG, assigning bit h to Bit y丨, bit b4 is assigned to bit, bit bs is assigned to bit y3, bit b6 is assigned to bit 丫4 'bit 1>7 is assigned to bit ys 'Assign bit bg to bit y6, bit b 9 to bit y7', assign bit b! 〇 to bit y 8, assign bit b 11 to bit yls, place bit bu Assigned to bit yi3, bit b13 is assigned to bit y!4', bit is assigned to bit y15, bit b15 is assigned to bit y 1 s, bit b i6 is assigned to bit, The bit b 17 is allocated to the bit y2 〇 'the bit bu is allocated to the bit y16, the bit bi9 is assigned to the bit, 位 the bit b2 〇 is assigned to the bit 3, and the bit bu is allocated to Bit yi7 assigns bit t»22 to the bit and bit b23 to bit yi9. The foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 12 bits, and the aforementioned integer b is 2, the foregoing code bits When the 12-bit element is mapped as one of 212 or 4096 signal points as the preceding symbol, the aforementioned 2 x 2 bits read in the direction of the memory mechanism are as described above. The code bit system group is divided into four groups of the aforementioned code bit groups; the preceding symbol bit groups of the two consecutive symbols are divided into six symbol bit groups; The foregoing allocation rule is defined as follows: assigning 1 bit of the code bit of the code bit group with a good error probability to the i bit of the symbol bit of the 6th good symbol bit group of the error probability The third bit of the code bit of the second good code bit group of the error probability is assigned to the three bits of the symbol bit of the symbolic group with the wrong probability probability; the error probability 4 bits of the code bit of the 2nd good code bit group ^ 'Assigned to the error probability 2nd good symbol bit 133671.doc -38- 200947881 Group symbol bit 4 bits; the 3 bits of the code bit of the second good symbol bit group of the error probability are assigned to the 3 bits of the symbol bit of the third good symbol bit group of the error probability; The 2 bits of the code bit of the second good symbol bit group of the error probability are assigned to the 2 bits of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 2nd. 2 bits of the code bit of a good code bit group, 2 bits assigned to the symbol bit of the 5th good symbol bit group of the error probability; 2nd good code bit of the error probability 2 bits of the code bit of the group, assigned to the 2nd bit of the symbol bit of the 6th good symbol bit of the error probability; the code of the 3rd good code bit group of the error probability 1 bit of the bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 1 bit of the code bit of the 4th good code bit group of the error probability The element is assigned to the 1st bit of the symbol bit of the first good symbol bit group of the error probability; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error The 1st bit of the symbol bit of the symbolic third-good symbol bit group; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 4th good 1 bit of the symbol bit of the symbol group; assign the 2 bits of the code bit of the 4th good code bit group of the error probability to the 5th good symbol group of the error probability 2 bits of the symbol bit of the group; and 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to the symbol of the 6th good symbol group of the error probability 1 bit of the bit. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, the 12-bit of the aforementioned code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the first 133671.doc -39-200947881 symbols; the memory mechanism is included in the course direction Memory 24 bits of 2X2 bits, in the case of memory 16200/(12x2) bits in the wale direction, the 12x2 bit code bits read in the direction of the memory mechanism are most valid. The i+th bit is set to the bit bi ' from the bit count and the i+1th bit of the 12x2 bit of the consecutive two preceding symbols is set from the most significant bit to the bit Yi, according to the foregoing allocation rules, respectively perform the following replacement: assign bit bG to bit y1 (), bit b! to bit yQ, bit b2 to bit yi, bit bs Allocated to bit y2, bit b4 is assigned to bit ys, bit bs is assigned to bit h, bit b6 is assigned to bit Y5, bit is assigned to bit y0, bit b8 is assigned Minute The allocation bit y7 assigns the bit b9 to the bit ys, the bit biQ to the bit y9, the bit to the bit y, and the bit bl2 to the bit y]2, the bit Bi3 is assigned to bit yi4, bit b]4 is assigned to bit yis, bit bi5 is assigned to bit y]6, bit bU is assigned to bit y22, bit bp is assigned to bit y 18. Assign bit b ! 8 to bit y23, assign bit b 9 to bit yi 7, assign bit b2 〇 to bit y19, assign bit bn to bit, place bit The unit b22 is allocated to the bit yzl, and the bit b23 is assigned to the bit yn. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; Where the m-bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of 212 symbols or 4096 signal points as the preceding symbols, The group of code bit groups of 12x2 bits read in the foregoing row direction of the memory mechanism is divided into three groups of the aforementioned code bits; two consecutive symbols of the first symbol are 133671.doc •40·200947881 yuan The aforementioned symbolic group The group is divided into 6 symbol bit groups; the foregoing allocation rule is as follows: assigning the 1 bit of the code bit of the first good code bit group of the error probability to the 5th good symbol of the error probability One bit of the symbol bit of the meta-bit group; assigning the 1-bit of the code bit of the first good code bit group of the error probability to the sixth-best symbol group of the error probability 1 bit of the symbol bit; assign 4 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the first good symbol bit group of the error probability 4 bits; assign the 3 bits of the code bit of the 2nd good code bit group® of the error probability to the 3 bit of the symbol bit of the 2nd good symbol bit group of the error probability And assign 4 bits of the code bit of the 2nd good code bit group of the error probability to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; 2 The 3 bits of the code bit of the good code bit group are assigned to the 3 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 2nd The 2 bits of the code bit of the good code bit group are assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the 3rd good code bit of the error probability is assigned 1 bit of the code bit of the group, assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 1 bit of the code bit of the 3rd good code bit group of the error probability , assigned to the 1-bit of the symbol bit of the 5th good symbol bit group of the error probability; and the 3 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the error The probability of the sixth best symbolic bit group of the three-bit symbol. 133671.doc -41 - 200947881 The foregoing LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; the aforementioned m bits are 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of the above symbols to any one of 4096 signal points determined by 4096QAM; the memory mechanism is stored in the horizontal direction memory 24 vertices of 12x2 bits, in the case of memory 64800/(12x2) bits in the wale direction, the 12x2 bit code bits read from the direction of the memory mechanism are from the most significant bit The i+1th bit is set to the bit bi, and the symbolic bits of the 12x2 bits of the two consecutive symbols are counted from the most significant bit, and the i+th unit is set to the bit yi. According to the foregoing allocation rule, the following replacements are respectively performed: assigning the bit bG to the bit yi〇, assigning the bit b! to the bit y8, assigning the bit to the bit y〇, and assigning the bit b3 to Bit y 1, assigning bit b4 to bit y2, assigning bit b5 to bit y3, assigning bit b6 to bit y4, and assigning bit b7 to bit ys, bit b 8 is assigned to bit y6, bit b9 is assigned to bit y7, bit b 1 〇 is assigned to bit y9, bit b!! is assigned to bit y 12, bit b 12 is assigned to bit Element y 1 3, assign bit BIT 3 to ◎ bit y14, bit b14 to bit yi6, bit bi5 to bit y 17, assign bit b! 6 to bit y 8. Assign bit b! 7 to bit y20, bit b18 to bit y15, bit b19 to bit y!!, bit b2() to bit y22, Bit b21 is assigned to bit y 19, bit b22 is assigned to bit y21, and bit t > 23 is assigned to bit y23. The foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 12 bits, and the aforementioned integer b is 2, the foregoing code bits When 12 bits of the element are mapped as one of the aforementioned symbols, 133671.doc -42-200947881 is one of 212 or 4096 signal points, and 12x2 is read in the foregoing direction of the memory mechanism. The foregoing group of code bit groups of the bit is divided into three groups of the aforementioned code bit groups; the preceding symbol bit group group of 12x2 bits of two consecutive symbols is divided into six symbol bit groups. The foregoing allocation rule is as follows: the 2 bits of the code bit of the first good code bit group of the error probability are assigned to the symbol bit of the first good symbol bit group of the error probability. 2 bits; the 3 bits of the code bit of the first good code bit group of the error probability are assigned to the 3 bits of the symbol bit of the second good symbol bit ® group of the error probability; Assigning 4 bits of the code bit of the first good symbol bit group of the error probability to 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability The 4th bit of the code bit of the first good symbol bit group of the error probability is assigned to the 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; 1 1 bit of the code bit of the good code bit group, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability first good code bit The 4 bits of the code bit of the metagroup are assigned to the 4th bit of the symbol bit of the 6th good symbol bit group of the error probability; the code of the 2nd good code bit group of the error probability 1 bit of the bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; 2 bits of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 2-bit element of the symbol bit of the first good symbol group of the error probability; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error The 1st bit of the symbol bit of the 2nd good symbol bit group; and the 2 bit of the code bit of the 3rd good code bit group of the error probability are assigned to the error probability Good bit 5 of symbol 133671.doc -43- 200947881 Meta Group 2 of bits of the symbol bits. The foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 4/5 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 vertical memories of 12x2 bits in the horizontal direction. In the case of storing 16200/(12x2) bits in the wale direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bit by the i+th position. The element is set to the bit bi, and the symbol of the 12x2 bit of the consecutive 2 symbols is set from the most significant bit to the i+1th bit as the bit yi, according to the foregoing allocation rule, respectively The following substitutions are made: the bit is assigned to the bit y, the bit b 1 is assigned to the bit y 1, the bit b2 is assigned to the bit y2, the bit b3 is assigned to the bit y3, the bit is allocated B4 is assigned to bit y4, bit b5 is assigned to bit y5, bit b6 is assigned to bit y6, bit b7 is assigned to bit y7, bit b8 is assigned to bit y8, bit is set B9 is assigned to the bit y 1 〇, the bit b! 〇 is assigned to the bit y 11, the bit b ! ! is assigned to the bit y! 4, and the bit b ! 2 is assigned to the bit y 1 6, Assigning bit b 1 3 to bit y! 7, assigning bit b 14 to bit y 18, assigning bit b 15 to bit y! 9, assigning bit b 16 to bit y22 , assigning bit b 1 7 to bit y23, assigning bit bi 8 to bit y9, assigning bit b! 9 to bit y2〇, and assigning bit b2〇 to bit y 12, The bit b21 is assigned to the bit y 13, the bit b22 is assigned to the bit yi5, and the bit b23 is assigned to the bit y21. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; the aforementioned m bit is 12 bits, and the aforementioned 133671.doc -44-200947881 integer b is 2, and 12 bits of the code bit are mapped as one of 212 symbols, that is, 4096 signal points, as one of the symbols, and 12x2 is read in the direction of the preceding direction of the memory mechanism. The foregoing group of code bit groups of the bit is divided into five groups of the aforementioned code bit groups; the preceding symbol bit group group of 12x2 bits of two consecutive symbols is divided into six symbol bit groups. The foregoing allocation rule is as follows: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the symbol bit of the fifth good symbol bit group of the error probability 1 bit; assigning 1 bit of the code bit of the 1st good code bit group® of the error probability to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; Assigning 1 bit of the code bit of the second good symbol bit group of the error probability to the 1st bit of the symbol bit of the first good symbol bit group of the error probability And assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the 3 bit of the symbol bit of the first good symbol bit group of the error probability; 3 4 bits of the code bit of the good code bit group, 4 bits assigned to the symbol bit of the 2nd good symbol bit group of the error probability; 3rd good code position of the error probability The 3 bits of the code bit of the group w are assigned to the 3 bits of the symbol bit of the 3rd good symbol group of the error probability; the error probability 3rd good code bit group 4 bits of the code bit, assigned to the 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability 2 The bit element is allocated to the 2-bit element of the symbol bit group of the fifth-perfect symbol bit group of the error probability; the 1-bit element of the code bit element of the fourth-perfect code bit group of the error probability is assigned to The error probability is the third good symbol bit group of the 1-bit element; the error probability is the 5th good code bit group 133671.doc -45- 200947881 group of code bits 1 bit Assigning to the 1-bit of the symbol bit of the fifth-good symbol bit group of the error probability; and assigning the 3-bit of the code bit of the fifth-perfect code bit group of the error probability to the error probability The 3rd bit of the symbol bit of the 6th good symbol group. The aforementioned LDPC code is DVB-S.2 or DVB-T.2, and the code length N is 64,800 bits, and the coding rate is 4/5. 1) () code; the aforementioned melon bit is in place. And the aforementioned integer b is 2', and 12 bits of the aforementioned code bit are mapped as one of the 4096 signal points determined by 4096QAM as the preceding symbols; the memory mechanism contains 12x2 bits in the horizontal direction. In the case of the memory of 64800/(12x2) bits in the longitudinal direction, the 12x2 bit code bits read in the direction of the memory mechanism are counted from the most significant bit. The first +1 bit is set to the bit bi, and the symbol bits of the 12x2 bits of the two consecutive symbols are set from the most significant bit to the i + 1 bit as the bit yi, according to The foregoing allocation rules are respectively replaced by: assigning the bit bQ to the bit yiG, assigning the bit bi to the bit y8, assigning the bit to the bit yQ, and assigning the bit to the bit yi, The bit center is assigned to the bit yz, the bit bs is assigned to the bit ys 'The bit is allocated to the bit 〇, the bit b7 is assigned to the bit ys, and the bit is assigned to the bit % The bit t > 9 is not assigned to the bit y7 'the bit b is assigned to the bit y 9, the bit b 1 1 is assigned to the bit y! 2, and the bit b ! 2 is assigned to the bit y 3, the bit b ^ 3 is assigned to the bit yM, the bit b! 4 is assigned to the bit y15, the bit b15 is assigned to the bit y 1 6, and the bit b ! 6 is assigned to the bit y 8, assigning the bit bi 7 to the bit y 〗 9, assigning the bit bls to the bit y2G, assigning the bit b19 to the bit yi7, and assigning the bit b2 给 to the bit yn, the bit B2 ! is assigned to bit yn, bit 133671.doc -46 - 200947881 element b22 is assigned to bit y22, bit b23 is assigned to bit y23. The aforementioned LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is an LDPC code of 16,200 bits; the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212 as one of the aforementioned symbols. In the case of any one of 4096 signal points, the group of code bit groups of 12x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; The aforementioned symbol bits of the 12x2 bits of the preceding symbol The group is divided into six groups of symbol bits; the first allocation rule is as follows: assign the first bit of the code bit of the first good code bit group of the error probability to the error probability number 6 1 bit of the symbol bit of a good symbol group; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the first good symbol of the error probability The 4th bit of the symbol group of the metagroup; the 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the symbol of the 2nd good symbol group of the error probability 3 bits of the meta-bit; assign the 3 bits of the code bit of the 2nd good code bit group of the error probability to the 3rd good symbol bit of the error probability ❿ the symbol bit of the group 3 bits; the 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the 3 bits of the symbol bit of the 4th good symbol bit group of the error probability; The error probability is the 3rd bit of the code bit of the 2nd good code bit group, and is assigned to the 3 bit of the symbol bit of the 5th good symbol bit group of the error probability; The 2 bits of the code bit of the 2nd good code bit group are allocated to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; the error probability is 3rd good. 1 bit of the code bit of the code bit group, assigned to the 5th good symbol bit of the error probability 133671.doc • 47- 200947881 1 bit of the symbol bit of the group; the error probability is 4th 1 bit of the code bit of the good code bit group, assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 4th good code bit of the error probability 1 bit of the code bit of the group, assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group of the error probability; the code bit of the 4th good code bit group of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; and 1 bit of the code bit of the 4th good code bit group of the error probability The element is assigned to the 1-bit of the symbol bit of the sixth-best symbol group of the error probability. ® The aforementioned LDPC code is an LDPC code with a code length N of 16200 bits and a coding rate of 5/6 as specified in the specifications of DVB-S.2 or DVB-T.2; the aforementioned m bits are 12 bits, and the foregoing The integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 memory 12x2 bits in the horizontal direction. In the case of wales, in the case of memory 16200/(12x2) bits in the wale direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bit i+Ι The bit element is set to the bit bi, and the symbol bit of 12x2 bits of the consecutive two preceding W symbols is set from the most significant bit to the i+1th bit as the bit yi, according to the foregoing allocation rule. The following substitutions are made respectively: assigning bit bG to bit y 1 〇, assigning bit b 1 to bit y , assigning bit b 2 to bit y 1, and assigning bit b3 to bit y2 Bit b4 is assigned to bit y3, bit b5 is assigned to bit y4, bit b6 is assigned to bit y5, bit b7 is assigned to bit y6, bit b8 is assigned to bit y7 , Assigning bit b9 to bit y8, assigning bit b!〇 to bit y9, assigning bit b!] 133671.doc -48- 200947881 to bit yn ' assign bit b丨2 to bit Yuan yiz, assign bit 丨8 to 兀 y!3, assign bit bM to bit, assign bit to bit 7!6, assign bit b!6 to bit yis, place bit The element bn is assigned to the bit element y2 〇 'the bit bls is assigned to the bit element 2, the bit element is assigned to the bit element, the bit element is assigned to the bit element 3, and the bit element is assigned to the bit element 9 Bit b22 is assigned to bit yn, and bit 匕3 is assigned to bit 5.

The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; the aforementioned m bit is 12 bits and the aforementioned integer b is 2 'the aforementioned code bit element When the 12-bit element is mapped to 2's or one of the side signal points as the above-mentioned symbol, the aforementioned code position of the called bit read in the foregoing direction of the memory mechanism The meta-group is divided into three groups of the aforementioned code-bit groups; the preceding symbol-bit group of the two consecutive symbols of the 符2χ2 bits is divided into six #元位元 groups; As follows: the code bit group with the first good error probability and the one bit of the 'horse bit element are assigned to the 1-bit element of the symbol bit group of the 4th good symbol bit group of the error probability; the error probability The 1st bit of the code bit of the U-th good code bit group is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; the error probability 2nd good code The 4th bit of the megabyte of the bit group is assigned to the 4th bit of the symbol bit of the first good symbol group of the error probability; the second good code position of the error probability The 4th bit of the mother group το of the metagroup is assigned to the 4th bit of the symbol bit of the 2nd good symbol group of the error probability; the 2nd good code bit group of the error probability, the horse 4 bits of the bit, assigned to the 3rd bit of the error probability group, the 4th bit of the symbol bit; the 2nd good code bit group with the error probability 133671.doc •49- 200947881 2 bits of the code bit, assigned to the 2 bit of the symbol bit of the 4th good symbol bit group of the error probability; the code bit of the second good code bit group of the error probability 4 bits, assigned to the 4th bit of the symbol bit of the 5th good symbol bit group of the error probability; the 1st bit of the code bit of the 3rd good code bit group of the error probability is allocated Assigning 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; and assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the error probability 6 Good 3 bits of the symbol bit of the symbol group. The foregoing LDPC code is a LDPC code having a code length ©N of 64800 bits and a coding rate of 5/6 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the foregoing The integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 memory 12x2 bits in the horizontal direction. In the case of wales, in the case of memory 64800/(12x2) bits in the wale direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bit i+Ι The bit element is set to the bit bi, and the symbol element of the 12x2 bit of the consecutive two preceding symbols is set from the most significant bit to the i-th place w element as the bit yi, according to the foregoing allocation rule. The following replacements are respectively made: the bit bG is assigned to the bit y! 〇, the bit b! is assigned to the bit y6, the bit b2 is assigned to the bit y, and the bit b3 is assigned to the bit y! Bit b4 is assigned to bit y 2, bit b 5 is assigned to bit y 3 , bit b 6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned Giving bit y7 Bit bit b9 is assigned to bit y8, bit b 1 〇 is assigned to bit y9, bit b!! is assigned to bit y 12, bit b! 2 is assigned to bit y 13, bit is placed Element b 13 allocates 133671.doc -50- 200947881 gives bit y 1 4, assigns bit bi 4 to bit y 1 5, assigns bit b 1 5 to bit y 16, assigns bit b 16 The bit y 17, the bit bi7 is assigned to the bit y! 8, and the bit bi8 is assigned to the bit y2. The bit b! 9 is assigned to the bit y21, the bit b2G is assigned to the bit yu, the bit b21 is assigned to the bit y22, the bit b22 is assigned to the bit yi9, and the bit t > 23 is assigned Give bit y23. The foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 12 bits, and the aforementioned integer b is 2, the foregoing code bits When the 12-bit element is mapped as one of the aforementioned symbols into 212 or 4096 signal points, the aforementioned code bits of 12x2 bits read in the foregoing direction of the memory mechanism The meta-group is divided into five groups of the aforementioned code-bit groups; the preceding symbol-series group of 12x2 bits of the preceding two symbols is divided into six groups of symbol bits; The rule is as follows: the 2 bits of the code bit of the first good code bit group of the error probability are assigned to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; The 1st bit of the code bit of the 2nd good code bit group is assigned to the 6th good symbol bit of the error probability.

The 1 bit of the symbol bit of the Q group; the 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the symbol of the first good symbol bit group of the error probability 4 bits of the meta-bit; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the symbol bit of the symbol group 2 with the second probability of error probability Bits; 4 bits of the code bits of the 3rd good code bit group of the error probability are assigned to the 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; The 4th bit of the code bit of the 3rd good code bit group is assigned to the 4th good symbol bit of the error probability 133671.doc -51 - 200947881 4 bits of the symbol bit of the group; The 2 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the 2 bits of the symbol bit of the 5th good symbol bit group of the error probability; the error probability is 4th. 1 bit of the code bit of the good code bit group, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the 5th good code bit of the error probability 1 bit of the code bit of the group, 1 bit assigned to the symbol bit of the 5th good symbol bit group of the error probability; and the code of the 5th good code bit group of the error probability One bit of the bit is assigned to one bit of the symbol bit of the sixth good symbol bit group of the error probability. © The LDPC code is DVB-S.2 or DVB-T.2, the code length N is 16200 bits, and the coding rate is 8/9 LDPC code; the m-bit is 12 bits, and the foregoing The integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 memory 12x2 bits in the horizontal direction. In the case of wales, in the case of memory 16200/(12x2) bits in the wale direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bit i+Ι The bit is set to the bit bi, and the symbol bits of the 12x2 bits of the two consecutive 13 symbols are counted from the most significant bit, and the i + Ι bit is set to the bit yi, according to the foregoing allocation rule. The following replacements are respectively performed: assigning the bit bQ to the bit y ] 〇, assigning the bit b! to the bit yn, assigning the bit b2 to the bit y22, and assigning the bit b3 to the bit y〇, The bit b4 is assigned to the bit y 1, the bit b5 is assigned to the bit y2, the bit b6 is assigned to the bit y3, the bit b7 is assigned to the bit y4, and the bit b8 is assigned to the bit Y5, assigning bit b9 to bit y6, assigning bit b! 〇 to bit y7, assigning bit b!] 133671.doc -52- 200947881 to bit y8, assigning bit b ϊ 2 The bit y9 is assigned, the bit b 13 is assigned to the bit yi2, the bit b14 is assigned to the bit yi3, the bit bi5 is assigned to the bit y! 4, and the bit b! 6 is assigned to the bit y丨5. Assign bit bi 7 to bit y! 6, assign bit b! 8 to bit y! 7, assign bit b! 9 to bit y 18, and assign bit b2 to bit The element yi9 assigns the bit b2i to the bit y2, assigns the bit b22 to the bit y21, and assigns the bit b23 to the bit y23. The foregoing LDPC code is an LDPC code of a code length N specified by the specification of DVB-S.2 or DVB-T.2 of 64800 bits; the aforementioned m bit is 12 bits, and the aforementioned ® integer b is 2, the foregoing code When the 12-bit of the bit is mapped to one of 212, that is, 4096 signal points as one of the preceding symbols, the aforementioned code position of the 12x2 bit read in the foregoing direction of the memory mechanism The meta-group is divided into five groups of the aforementioned code-bit groups; the preceding symbol-series group of 12 consecutive 2-bit symbols is divided into six symbol-bit groups; The method is as follows: assigning the 2 bits of the code bit of the first good symbol bit group of the error probability to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability; The error probability is the 1st bit of the code bit of the 2nd good code bit group, and is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; the error probability is 3rd good. 4 bits of the code bit of the code bit group, assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the error probability is 3rd 4 bits of the code bit of the good code bit group, 4 bits assigned to the symbol bit of the 2nd good symbol bit group of the error probability; the 3rd good code bit of the error probability 4 bits of the code bit of the group, assigned to the 4th bit of the symbol bit of the 3rd good symbol group of the error probability; the error probability 3rd good code bit group 133671.doc - 53- 200947881 The 4-bit code element of the group is assigned to the 4-bit symbol of the symbol element of the 4th good symbol group of the error probability; the error probability is the 3rd good code bit group 2 bits of the code bit, assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; 1 of the code bit of the 4th good code bit group of the error probability The bit is allocated to the 1-bit of the symbol bit of the fifth-perceived symbol bit group of the error probability; the 1-bit element of the code bit of the fifth-perfect code bit group of the error probability is assigned to The error probability is 5th of the symbolic bit of the 5th good symbol group; and the 1st bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability The sixth good symbol is the one-bit of the meta-bit of the meta-group. The foregoing LDPC code is a LDPC code having a code length N of 64,800 bits and a coding rate of 8/9 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 vertical memories of 12x2 bits in the horizontal direction. In the case where 64800/(12x2) bits are memorized in the wale direction, the 12x2 bit code bits read out in the course direction of the memory device are counted from the highest w effective bit. The +1 bit is set to the bit bi, and the symbol bits of the 12x2 bits of the preceding two symbols are set from the most significant bit, and the i+th bit is set to the bit yi, according to the foregoing allocation rule. Replacing the following respectively: assigning the bit b〇 to the bit y 1 〇, assigning the bit b! to the bit y! 1, assigning the bit b2 to the bit y22, and assigning the bit b3 to the bit Element yG, assigning bit b4 to bit y 1, assigning bit b5 to bit y2, assigning bit b6 to bit y3, assigning bit b7 to bit y4, assigning bit b8 to Bit y5 , assign 133671.doc •54· 200947881 bit b9 to bit y6, assign bit b!〇 to bit y7, and bit b丨! Assigned to bit y8, bit b! 2 is assigned to bit y9, bit bi3 is assigned to bit yi2, bit b14 is assigned to bit y13, bit b15 is assigned to bit y! 4 , assign bit b! 6 to bit y! 5, assign bit b! 7 to bit y! 6, assign bit b! 8 to bit y! 7, assign bit b! The bit y 1 8 is assigned to the bit yi9, the bit b21 is assigned to the bit y2G, the bit b22 is assigned to the bit y2 1, and the bit b23 is assigned to the bit y23. The foregoing LDPC code is a LDPC code of a 64800-bit code length specified by the specification of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, the foregoing code When the 12-bit of the bit is mapped to one of 212, that is, 4096 signal points as one of the preceding symbols, the aforementioned code position of the 12x2 bit read in the foregoing direction of the memory mechanism The meta-group is divided into five groups of the aforementioned code-bit groups; the preceding symbol-series group of 12 consecutive 2-bit symbols is divided into six symbol-bit groups; The system provides the following: assigning the 2 bits of the code bit of the first good symbol bit group of the error probability to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability; Assigning 1 bit of the code bit of the second good symbol bit group of the error probability to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; 4 bits of the code bit of the good code bit group, assigned to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability The 4th bit of the code bit of the 3rd good code bit group is allocated to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the error probability 3rd good code The 4 bits of the code bit of the bit group are assigned to the 3rd good symbol bit of the error probability 133671.doc -55- 200947881 The 4th bit of the symbol bit of the group; the error probability is 3rd good 4 bits of the code bit of the code bit group, 4 bits assigned to the symbol bit of the 4th good symbol bit group of the error probability; the 3rd good code bit group with the error probability 2 bits of the code bit group, 2 bits assigned to the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 4th good code bit group of the error probability 1 bit, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; 1 bit of the code bit of the 5th good code bit group of the error probability, 1 bit assigned to the symbol bit of the 5th good symbol bit group of the error probability; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the wrong bit 6 good probability of symbol bits of the symbol bit group of 1 yuan element. The foregoing LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and the aforementioned integer b is 2, and 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 vertical memories of 12x2 bits in the horizontal direction. In the case where 64800/(12x2) bits are memorized in the wale direction, the 12x2 bit code bits read in the course direction of the preceding memory device are counted from the most significant bit i+ The Ι bit is set to the bit bi, and the symbolic bits of the 12x2 bits of the consecutive two preceding symbols are set from the most significant bit to the i-th bit as the bit yi, according to the foregoing allocation rule. The following substitutions are made respectively: assigning the bit bQ to the bit y! 〇, assigning the bit b! to the bit y η, assigning the bit b2 to the bit ys, and allocating the bit b3 to the bit yG, Assigning a bit to bit y 1, assigning bit b5 to bit y2, and assigning bit b6 to bit 133671.doc -56- 200947881

Y3, the bit b7 is assigned to the bit Υ4, the bit b8 is assigned to the bit y5, the bit t>9 is assigned to the bit y6, and the bit b 1 Q is assigned to the bit y?, the bit is b 1 1 is assigned to the bit, the bit bu is allocated to the bit yi, the bit bu is allocated, the -σ bit yn is assigned, the bit b" is assigned to the bit, and the bit by is assigned to the bit y 〗 5, assign bit bie to bit yie, assign bit bi? to bit y 〖7, assign bit bls to bit yis, assign bit bi9 to bit, assign bit To the bit, the bit bzi is assigned to the bit 2, the bit b22 is assigned to the bit 3, and the bit b23 is assigned to the bit. In one aspect of the present invention, the memory means of the code bit of the LDPC code of the N-bit 70 in the log direction and the wale direction is written in the preceding direction in the direction of the row. The m-bit το of the code bit το of the aforementioned LDPC code is read as one symbol, and the specific positive integer is set to b; the memory mechanism is 〇 115 bits in the foregoing direction, and is in the preceding directional direction Memory N/(mb) bits. Further, the code bit of the LDpc code is written in the wale direction of the memory mechanism, and then read in the course direction, and the code bit read in the direction of the memory mechanism of the memory mechanism is used as b of the aforementioned symbols. In this case, the code bit element of the mb bit is replaced according to the allocation rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol, and the replaced code bit is used as the foregoing. Symbol bit. The foregoing allocation rule is to group the group (4) of the aforementioned code bits it into a group of code bits according to the error probability, and group H into groups of the above-mentioned symbol bits according to the error probability as the group of symbol bits. And (4): the foregoing symbol bit group of the foregoing listening element, and the aforementioned symbol bit 133671.doc -57- of the preceding symbol bit of the aforementioned m-bit assigned to the code bit it group 200947881 The combination of the meta-groups is a group set; and the foregoing code bit group of the group set, and the foregoing code bit of the foregoing symbol bit group and the number of bits of the foregoing symbol bit. For example, the foregoing LDPC code is an LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16,200 bits; the m-bit is 10 bits, and the aforementioned integer b is 2, the foregoing code When the 10-bit of the bit is mapped to one of the 21 () 1024 signal points as one of the symbols, the 10x2 bits read in the direction of the memory mechanism are as described above. The code bit system group is divided into five groups of the aforementioned code bit groups; the preceding symbol bit group group of the last 10 symbols of the above 10x2 bits is divided into five symbol bit groups. Further, in this case, according to the allocation rule, the 1-bit of the code bit of the code-bit group of the first-good error probability is assigned to the symbol of the fifth-perfect symbol group of the error probability. 1 bit of the meta-bit; 1 bit of the code bit of the 2nd good code bit group of the error probability, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability The error probability is the 4th bit of the code bit of the 3rd good code bit group, and is assigned to the 4th bit of the symbol bit of the first good symbol group of the error probability; w 3 good code bit group 4 bits of the code bit, assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; error probability 3rd good code position 2 bits of the code bit of the metagroup, allocated to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; the code margin of the 3rd good code bit group of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the 4th good symbol group of the error probability; the code of the 4th good code bit group of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the symbolic group of the error probability 4th 133671.doc -58- 200947881; the code of the 5th good code bit group of the error probability 2 bits of the bit, assigned to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; 1 bit of the code bit of the 5th good code bit group of the error probability , assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; and the 3 bits of the code bit of the 5th good code bit group of the error probability are assigned to the error The probability is the 5th good symbol of the 5th good symbol group. For example, the aforementioned LDPC code is a LDPC code having a code length N of 16200 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and The integer b is 2, and the 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism contains 20 bits of memory in the horizontal direction. In the case of a wales, in the case of a memory of 16200/(10x2) bits in the wale direction, the code bits of the 10x2 bits read out in the course direction of the memory mechanism are counted from the most significant bit. The 1-bit element is set to the bit bi, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are calculated from the most significant bit, and the 〇i+Ι bit is set to the bit yi, according to the foregoing allocation rule. Replacing the following: assigning bit bQ to bit y8, assigning bit b! to bit y6, assigning bit b2 to bit yG, and assigning bit b3 to bit y! Bit b4 is assigned to bit y2, bit b5 is assigned to bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y7, The bit b9 is assigned to the bit y! 〇, the bit b! 〇 is assigned to the bit yi!, the bit bn is assigned to the bit y!2, and the bit b12 is assigned to the bit yn, the bit is allocated b! 3 is assigned to bit y! 6, the bit b 丨 4 is assigned to bit y 1 4, bit b 1 5 133671.doc -59- 200947881 is assigned to bit Tcy15 'Assign bit 疋bu to bit The element %, the bit is assigned to the bit y18, the bit bl8 is assigned to the bit yi9, and the bit bi9 is assigned to the bit y17. Further, the data processing device may be an independent device or an internal block constituting one device. [Embodiment] [Effects of the Invention] According to the present invention, fault tolerance for errors can be improved. Fig. 7 is a view showing an example of a configuration in which one embodiment of the transmission system to which the present invention is applied (the system refers to a logically aggregated plurality of devices, regardless of whether or not the devices of the respective structures are in the same casing). In Fig. 7, the transmission system is constituted by a transmitting device 接收 and a receiving device 12. The transmitting device 11 performs, for example, transmission of a television broadcast program (playback transmission). In other words, the transmitting device 11 encodes the target data to be transmitted as image data or audio data of a television broadcast program, for example, into an LDPC code, and transmits it via a communication channel 13 such as a satellite line, a ground wave, or a cATV network. The receiving device 12 is, for example, a pacer or a television receiver that receives a television broadcast program, an STB (Set Top Box), and receives an LDPC code transmitted from the transmitting device via the communication channel 13 and decodes it into a target data. Output. Here, the LDPC code used in the transmission system of Fig. 7 is known to be extremely high in the AWGN (Additive White Gaussian Noise) 133671.doc -60-200947881 channel. However, in the communication channel 13 of the ground wave or the like, a burst error or erasure may occur. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, D/U (Desired to Undesired Ratio) is OdB (not required = echo power and required = main path) In a multipath environment with equal power, there is a delay based on the echo (path outside the main path), and the power of the specific symbol becomes 0 (erase). Moreover, even if it is a flutter (a delay is 0 and a communication channel with an echo of the Doppler frequency is added), a specific time is generated by the Edubull frequency when D/U is OdB. The power of all the symbols of OFDM becomes the case of 〇 (erasing). Further, since the receiving device 12 side receives the wiring condition of the receiving unit (not shown) such as an antenna from the transmitting device 11 to the receiving device 12 or the power supply of the receiving device 12, the cluster may also occur. Make a mistake. On the other hand, in the decoding of the LDPC code, in the row of the check matrix, even the variable node corresponding to the code bit of the LDPC code, since the code bit associated with the LDPC code is performed as shown in FIG. 5 described above, Since the variable node operation of the equation (1) is added (the received value uGi), if the error is generated in the code bit used for the variable node operation, the accuracy of the obtained message is lowered.

Then, in the decoding of the LDPC code, in the check node, since the check node operation of the equation (7) is performed by using the message obtained by the variable node connected to the check node, if the complex number is connected, When the variable node (corresponding to the LDPC 133671.doc -61 · 200947881 code bit) has more errors (including erasure), the number of check nodes becomes larger, and the decoding performance deteriorates. That is, for example, if the check node is connected to more than two variable nodes of the check node and becomes erased at the same time, the probability that the probability of returning a value of 0 to all variable nodes and the probability of 1 is an equal probability message. In this case, the check node that sends back the information of the equal probability does not contribute to the decoding process once (the variable node operation of the set and the check node operation), and as a result, the number of repetitions of the decoding process is required, and the decoding is performed. The performance is deteriorated. Further, the power consumption of the receiving device 12 that performs decoding of the LDPC code increases. © Therefore, in the transmission system of Figure 7, it is desirable to maintain the performance of the AWGN communication channel while improving fault tolerance for burst errors or erasures. Fig. 8 is a view showing an example of the configuration of the transmitting device 11 of Fig. 7. In Fig. 8, the transmitting apparatus 11 is composed of an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and a quadrature modulation unit 27. The target data is supplied to the LDPC encoding unit 21. The LDPC encoding unit 21 performs LDPC encoding on the object data supplied to the location, and performs the LDPC encoding on the check matrix corresponding to the parity bit of the LDPC code, that is, the parity matrix, and outputs the target data as the information bit. LDPC code. In other words, the LDPC encoding unit 21 performs LDPC encoding of the LDPC code specified by the specification of DVB-S.2 or DVB-T.2, and outputs the LDPC code obtained as a result.

Here, the specification of DVB-T.2 is intended to adopt the LDPC code specified by the specification of DVB-S.2. The LDPC code specified by the specification of DVB-S.2 is IRA 133671.doc -62-200947881 (Irregular Repeat Accumulate) code, and the parity matrix of the check matrix of the LDPC code becomes a ladder structure. The isomorphic matrix and the ladder structure will be described later. Further, the IRA code system is described, for example, in "Irregular Repeat-Accumulate Codes" H. Jin, A. Khandekar, and RJ McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000. The LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver © 22. The bit interleaver 22 is a data processing device for interleaving data, which is composed of a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25. The parity interleaver 23 performs co-located interleaving, interleaving the parity bits of the LDPC code from the LDPC encoding section 21 to the positions of other parity bits, and supplies the parity interleaved LDPC code to the vertical twist interleaver 24. The whirch twist interleaver 24 performs wobble interleaving for the LDPC code from the co-located interleaver 23, and supplies the LDPC code obtained by twisting the wobble to the demultiplexer 25. In other words, the LDPC code is mapped to the mapping unit 26, which will be described later, and the code bits of two or more bits of the LDPC code are mapped to signal points representing one symbol of the quadrature modulation and transmitted. In the vertical twist interleaver 24, in order to make the complex digital bit 133671.doc • 63-200947881 corresponding to the LDPC code of any one of the check matrices used in the LDPC encoding unit 21, it is not included in one character. The element 'as a rearrangement process of rearranging the code bits of the LDPC code from the co-located interleaver 23 to perform, for example, a wobble twist interleaving which will be described later. The demultiplexer 25 performs a replacement process for replacing the position of the code bit of 2 or more of the LDPC code of the symbol with respect to the LDPC code from the vertical twist interleaver 24, thereby obtaining the LDPC which has enhanced the fault tolerance for the AWGN. code. Then, the demultiplexer 25 supplies the code bits of 2 or more of the 2 LDPC codes obtained by the replacement processing to the mapping unit 26 as symbols. The mapping unit 26 maps the symbols from the demultiplexer 25 to the signals determined by the modulation method of the quadrature modulation (multi-value modulation) performed by the quadrature modulation unit 27. That is, the mapping unit 26 maps the LDPC code from the demultiplexer 25 to the 1Q plane GQ defined by the I axis indicating the I component in phase with the carrier and the Q axis indicating the Q component orthogonal to the carrier. The signal point determined by the modulation method on the constellation. Here, as a modulation method of the quadrature modulation performed by the quadrature modulation unit 27, there is, for example, a modulation method including a modulation method defined by a specification of DVB-T, that is, for example, QPSK (Quadrature Phase Shift Keying) : Quadrature phase key shift) or 16QAM (Quadrature Amplitude Modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc. The quadrature modulation unit 27 preliminarily sets the orthogonal modulation by a certain modulation method in accordance with, for example, the operation of the operator of the transmission device 11. Further, in the quadrature modulation unit 27, for example, 4PAM (Pulse Amplitude Modulation) and other orthogonal modulation can be performed. The symbol mapped to the signal point by the mapping unit 26 is supplied to the orthogonal modulation unit 133671.doc 20094788121. The quadrature modulation unit 27 performs orthogonal modulation of the carrier in accordance with a signal point (a symbol mapped to the signal point) from the mapping unit 26, and the resulting modulated signal is transmitted via the communication channel 13 (FIG. 7). ) Transfer. Next, Fig. 9 shows an inspection matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of Fig. 8. The check matrix Η is an LDGM (Low-Density Generation Matrix) structure, and the information matrix Ha corresponding to the part of the information bit in the code bit of the LDPC code and the co-located corresponding to the parity bit can be used. The matrix Ητ is expressed as the equation H=[HA|HT] (the elements of the information matrix HA are set to the left side element, and the elements of the parity matrix Ητ are set to the matrix of the right side element). Here, the number of bits of information bits and the number of bits of the parity bits in the code bits of one LDPC code (1 code word) are respectively referred to as information length K and parity length, and one LDPC code. The number of bits of the code bit is called the code length Ν (=Κ+Μ). The information about the L D P C code of a certain code length is determined by the coding rate. Moreover, check the matrix of the matrix Η series X behavior. Then, the matrix of the information matrix, the parity matrix Ητ is the matrix of ΜχΜ. Figure 10 is a diagram showing the parity matrix Ητ of the check matrix LDP of the LDPC code specified by the specifications of DVB-S.2 (and DVB-T.2). The parity matrix of the inspection matrix LDP of the LDPC code defined by the specification of DVB-S.2 is as shown in Fig. 10, and the elements which become 1 are arranged in a so-called stepped structure. The column weight of the co-located matrix Ητ is 1 for the first column and 2 for the remaining columns. Moreover, the row weight is 1 for the last row, and the rest is 133671.doc •65· 200947881 Behavior 2. As described above, the LDPC code in which the parity matrix Ητ is the ladder structure check matrix η can be easily generated using the check matrix Η. That is, the LDPC code (1 codeword) is represented by the column vector c, and the row vector obtained by transposing the column vector is represented as c1^ and the information bit in the column vector c of the LDPC code is represented by the column vector Α. Part of it, and the column vector τ represents the part of the parity bit. In this case, the column vector c can be used as the column vector A of the information bit and the column vector τ as the parity bit, with the formula C=[A|T] (the elements of the column vector a are set to the left The element 'the element of the column vector T is set to the column vector of the right element). Check matrix Η and column vector C=[A|T] as LDPC code must conform to

HcT=0' as the column vector T constituting the parity bit of the column vector C=[A|T] conforming to the formula HcT=〇 can be obtained by checking the parity matrix Ητ of the matrix h=[Ha|Ht] In the case of the ladder structure shown, the equation HcT=〇i row vector

The elements of the second column of HcT are sequentially obtained by making the elements of each column 〇. Figure 11 is a diagram showing the check matrix 行 and row weight of the LDpc code specified by the specifications of DVB-S.2 (and DVB-T.2). That is, Fig. 11 is a check matrix LDP of LDPC 规定 prescribed by the specification of DVB-S.2. Separately, regarding the check matrix Η from the first row, the row weight is X, and for the next 行3 rows, the row weight is 3, and for the subsequent Μ-1 row, the row weight is 2, about the last 1 Line, the row weight is 1. 133671.doc •66- 200947881 Here, KX+K3+M-1 + 1 is equal to the code length N. In the specification of DVB-S.2, the number of lines KX, K3 and Μ (co-located length), and the weight of the line X are as shown in Fig. 11A. That is, Fig. 11 is a line number KX, Κ3&, and row weight X of each coding rate of the LDPC code defined by the specification of DVB-S.2. In the specification of DVB-S.2, there are LDPC codes with a length of 64,800 bits and 16,200 bits. Then, as shown in Fig. 11A, the LDPC code with a code length of 64,800 bits is specified with 11 coding rates (nominal rate) of 1/4, 1/3, 2/5, 1/2. , 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10. For an LDPC code with a code length N of 16,200 bits, one encoding rate is specified. 4. 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9. Regarding the LDPC code, it is known that the code bit corresponding to the row having the larger row weight of the check matrix has a lower error rate. In the check matrix 规定 specified in the specification of DVB-S.2 shown in FIG. 11, the more the start side (left side), the greater the weighting tendency of the row, and therefore the LDPC code corresponding to the check matrix ,, The more the beginning of the code bit 'the stronger the error (there is fault tolerance for the error), the more the last bit of the code bit, the weaker the tendency toward error. Next, Fig. 12 shows an arrangement on the IQ plane of 16 symbols (corresponding signal points) in the case where 16QAM is performed by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 12A shows the symbol of 16QAM. In 16QAM, 1 symbol represents 4 bits, and there are 16 (= 24) symbols. Then, the 16 symbols are arranged in a square shape of 4x4 in the 1-direction XQ side 133671.doc -67-200947881 centering on the origin of the IQ plane. Now, if the bit string represented by the 1 symbol is counted from the most significant bit, the bit of the 1 + 1 bit is represented as the bit yi, then the 4 symbol of the 16QAM symbol is The most significant bits can be represented as bits yG, yi, y2, in order. In the case where the modulation method is 16QAM, the 4 bits of the code bit of the lDPC code are taken as (the symbol is converted into the symbol yG to y3 (the symbol value). Fig. 12B shows the 16QAM respectively. The 4-bit (hereinafter also referred to as the symbol bit) represented by the symbol is the bit boundary of the bit. Here, the symbol bit ^ (in Figure 12 is the dice, 丨, 2, 3) The bit boundary line means that the symbol bit % becomes the symbol of 〇 and the boundary of the symbol that becomes 1. As shown in Fig. 12B, the 4 symbol bits 7〇 to y3 represented by the symbol of 16QAM are shown. The highest-order bit element y., only the Q-axis of the IQ plane becomes the bit boundary line 关于 yi for the second (the second from the most significant bit), only The i-axis of the axis of the IQ plane becomes the bit boundary. Moreover, regarding the third symbol bit W, the left i-th lamp, the second book, and the third row and the fourth of the 4X4 symbols The second line between the lines becomes the bit boundary. Further, regarding the fourth symbol element ^, 4χ4 symbols from the !, the !! column and the second column, and the third column and the fourth column The two places between the columns become the bit boundary. The symbolic element L that is represented is the more symbols that are farther away from the bit boundary. The more the error: the error is low (the probability of error is low). The more symbols there are near the boundary of the bit, the more likely it is to make mistakes (high probability of error). 'If the bit that is not easy to make mistakes (to the wrong) is called "strong position" and the position of the error (for the wrong position) is called "weak position 133671.doc 200947881 yuan", then the symbol of 16QAM The 4 symbol bits y〇 to y3, the highest bit yQ and the second symbol yi become strong bits, the third symbol y2 and the fourth symbol y3 Fig. 13 to Fig. 15 show the arrangement on the IQ plane of 64 symbols (corresponding signal points) in the case where 64QAM is performed by the quadrature modulation unit 27 of Fig. 8. At 64QAM, 1 symbol The element represents 6 bits, and there are 64 (=26) symbols. Then, the 64 symbols are centered on the origin of the IQ plane, and are arranged in a square shape of 8x8 in the X direction of the I direction. The symbol element of the symbol is from the most significant bit and can be expressed as a bit in order. In the case of modulation mode is 64QAM, L The 6-bit code bit of the DPC code is used as the symbol of the 6-bit symbol bit y 〇 to y5. Here, Fig. 13 shows the symbol y y to the symbol of 64QAM, respectively. The highest-order symbol y〇 and the second-character yii bit boundary in y5; FIG. 14 shows the position of the third symbol y2 and the fourth symbol y3, respectively. The boundary line, Fig. 15 shows the bit boundary of the fifth symbol bit y4 and the sixth symbol bit y5, respectively. As shown in Fig. 13, respectively, the highest bit symbol y 〇 And the second symbol bit yi has a bit boundary of one. Moreover, as shown in FIG. 14, the bit boundaries for the third symbol bit y2 and the fourth symbol bit y3 are respectively two; as shown in FIG. 15, respectively, regarding the fifth symbol bit. The bit boundary of the element y4 and the sixth symbol bit y5 is four. Therefore, with respect to the symbolic elements y〇 to y5 of the symbol of 64QAM, the highest-order symbol y〇 and the second-character yi are the strong bits, and the third symbol 133671.doc -69 - 200947881 yuan y2 and the fourth symbol element y3 become the next strong position. Then, the fifth symbol bit y4 and the sixth symbol bit y5 become weak bits. From Fig. 12, it can be further seen from Fig. 13 to Fig. 15 that with respect to the symbol bit of the symbol of the quadrature modulation, there is a tendency that the higher bit becomes a strong bit and the lower bit becomes a weak bit. Here, as illustrated in Fig. 11, regarding the LDPC code outputted by the LDPC encoding section 21 (Fig. 8), there are code bits which are strong against errors and code bits which are weak to error. Further, as illustrated in FIGS. 12 to 15, the symbol bits of the symbol of the quadrature modulation performed by the quadrature modulation unit 27 have strong bits and weak bits. Therefore, if the error bit of the LDPC code is assigned to the weak symbol bit of the orthogonally modulated symbol, the fault tolerance for the error as a whole is lowered. Therefore, an interleaver is proposed which interleaves the code bits of the LDPC code by assigning the error bit of the LDPC code to the strong bit (symbol bit) of the quadrature modulated symbol. yuan. The multiplexer 25 of Fig. 8 performs the processing of the interleaver. ® Figure 16 is a diagram illustrating the processing of the multiplexer 25 of Figure 8. That is, Fig. 16A shows an example of the functional configuration of the demultiplexer 25. The multiplexer 25 is composed of a memory 31 and a replacement unit 32. The LDPC code from the LDPC encoding unit 21 is supplied to the memory 31. The memory 3 1 contains a memory mb bit in the row (horizontal) direction, and memorizes the memory capacity of the N/(mb) bit in the column (longitudinal) direction, and is supplied thereto. The code bits of the LDPC code are written in the wale direction, read out in the horizontal direction of the horizontal 133671.doc -70-200947881, and supplied to the replacement unit 32. Here, N (= information length K + co-located length M) is the code length of the LDPC code as described above. Further, m denotes the number of bits of the code bit which becomes the 1-element LDPC code; b is a specific positive integer which is used to make m a multiple of an integral multiple. The demultiplexer 25 is as described above, and the code bit of the LDPC code is used as a symbol (symbol), and the multiple b is the number of symbols obtained by the demultiplexer 25 by the so-called one-time symbolization. . Fig. 16A shows an example of the configuration of the demultiplexer 25 in the case where the modulation method is 64QAM. Therefore, the number of bits m of the code bit which becomes the one symbol LDPC code is 6 bits. Further, in Fig. 16 A, the multiple b is 1, so that the memory 3 1 has a memory capacity in which the direction of the X direction is Ν / (6 χ 1) χ (6 χ 1). Here, the course direction of the memory 3 1 is a 1-bit memory area extending in the wale direction, and is hereinafter referred to as a wales as appropriate. In Fig. 16A, the memory 3 1 is composed of 6 (= 6X 1) vertical lines. ® is demultiplexed in the multiplexer 25, and the writing of the LDPC code in the vertical direction of the memory 3 1 from the top to the bottom (the wale direction) is performed from the left to the right. Then, if the code bit is written to the bottom of the rightmost vertical line, the first column of all the wales constituting the memory 3 1 is read in units of 6 bits (mb bits) in the course direction. The bit is output and supplied to the replacement unit 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 6-bit memory of the memory 31, and obtains the 6-bit obtained as a result of the symbol 133671.doc -71 - 200947881 64QAM The symbol bits (10), y2, y3, y4, y5 are output. That is, the code bit mb of the mb bit (here, the 6-bit 兀) is read from the 己 体 3 3 in the course direction, and the code bit of the bit read from the memory 3 从 is The highest digit (4), 1, ..., mb-1) is expressed as the bit b, and then the (10) element coded in the horizontal direction is the same. The valid bit 7C ' can be sequentially represented as G, bl, b2, b3, b4, b5. The code bit system in the direction of the bit b〇 shown in FIG. 11 becomes the code bit element for the error strong, and the code bit element in the direction of the bit element b becomes the code bit element for the error weak. .替换 The replacement unit 32' is configured to assign a strong bit in the symbol bit ydy5 of the 64qaM2^ symbol to the code bit from the 6-bit code bit b to the b5 of the memory 31 to the error weak bit. 'Replacement processing for replacing the position of the code bit bG to bs from the 6 bits of the memory 31 can be performed. Here, as an alternative to how to replace the 6-bit code bits from the memory 31, to h, and assign them to the 6-symbol bits % to 1 of the symbol, there are various ways to propose from each company. . Fig. 16B shows a first alternative, and Fig. 16C shows a second alternative. Fig. 16D shows a third alternative. 16B to 16D (the same applies to the figure π described later), the line segment connecting the bit (4) A means that the code bit b { is assigned to the symbol bit of the symbol to be replaced by the position of the symbol bit %. ). As a first alternative of Fig. 16B, it is proposed to adopt one of the three types of alternatives as the second alternative of Fig. 16C, and it is proposed to adopt either one of the two types of alternatives. 13367l.doc -72· 200947881 As a third alternative of Fig. 16D, it is proposed to sequentially select six types of replacement methods for use. Fig. 17 is a diagram showing the multiplexing in the case where the modulation method is 64QAM (hence, the number of bits m of the LDPC code mapped to one symbol is 6 bits as in Fig. 16) and the multiple 匕 is 2. The configuration example of the device 25 and the fourth alternative. When the multiple 13 is 2, the memory 31 has a memory capacity of Ν/(6χ2)χ(6χ2) in the direction of the X direction, and the memory capacity is composed of ΐ2 (=6χ2) vertical lines. ^ ® 17 indicates the order in which the LDPC codes of the memory 31 are written. In the solution of the multi-tools 25, as illustrated in FIG. 16, the code bits of the LDPC code are written from the top to the bottom (the wale direction) of the wales constituting the memory 31 from the left-to-right direction. . <,,: If the writing of the code bit is completed to the bottom of the rightmost vertical line, the first column of all the wales constituting the memory 31 is 12 bits (mb bits) in the course direction. The unit extracts the code bit and supplies it to the replacement unit μ. ◎ The replacement unit 32 is a replacement process in which the position of the 12-bit code bit from the memory 31 is replaced by the fourth alternative, and the 12-bit obtained as a result is represented as a 64QAM22 symbol (3). The η bit of the symbol, that is, the 6-symbol y〇, yi, y2, y3, y4, y5 representing the 1 symbol of 64QAM and the 6-symbol bit representing the next i-symbol ^ ^ Seven and output. Here, Fig. 17B shows a fourth alternative of the replacement processing by the replacing unit 32 of Fig. 17A. In addition, when the multiple b is 2 (the same applies for the case of 3 or more), in the replacement processing, the mb bit of the mb bit is allocated to the bit of the consecutive b symbols. 133671.doc • 73- 200947881 Symbol Bit. Including the Fig. 17, for the sake of convenience of explanation, the bit number from the most significant bit of the symbol bit of the mb bit TL of the continuous character 7L is expressed as a bit (symbol bit). • Moreover, what kind of replacement method is appropriate, that is, how to improve the error rate of the AWGN communication channel is different depending on the coding rate or code length and modulation mode of the LDPC code. Next, the co-interleaving by the parity interleaver 23 of Fig. 8 will be explained with reference to Figs. 18 to 2B. Fig. 18 is a Tanner diagram (part) showing a check matrix of an LDPC code. 0 If the check node is as shown in FIG. 18, two or more of the variable nodes (corresponding code bits) connected to the check node are simultaneously erased and the like, and the pair is connected to the check node. For all variable nodes, the probability of returning the value 丄 and the probability of 丄 are equal probability messages. Therefore, if the complex variable nodes connected to the same check node become erased at the same time, the decoding performance deteriorates. However, the LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 of Fig. 8 is the IRA code. The parity matrix Ητ of the inspection matrix η is a stepped structure as shown in Fig. 1A. ❹ Fig. 19 shows a parity matrix ^ which is a step structure and a Tanner graph corresponding to the parity matrix Ητ. That is, Fig. 19A shows the parity matrix ht which becomes the staircase structure; Fig. 19B shows the 仏(10) map corresponding to the parity matrix of Fig. 19A. In the case where the co-located matrix Ητ is a ladder structure, in the Tanner graph of the co-located matrix Ητ, the information is obtained by using the contiguous code bit (the parity bit) of the LDpc code corresponding to the row of the element having the value of the co-located matrix of 1. The variable section 133671.doc •74·200947881 points are connected to the same check node. Therefore, if the adjacent parity bit becomes an error at the same time due to a cluster error or erasure, etc., it is connected to a complex variable node corresponding to the complex parity bit that becomes the error (using the parity bit to obtain a message) The check node of the variable node sends the probability of the value 与 and the probability of 1 to the equal probability message back to the variable node connected to the check node, so the decoding performance is degraded. Then, when the length of the cluster (the number of bits that become the error due to the burst) is large, the decoding performance is further deteriorated. Therefore, the parity interleaver 23 (Fig. 8) performs the co-interleaving in which the parity bits of the LDPC code from the LDPC encoding unit 21 are interleaved to the positions of the other parity bits in order to prevent deterioration of the above decoding performance. Fig. 20 is a diagram showing the parity matrix Ητ of the check matrix LDP of the LDPC code corresponding to the co-located interleaver 23 of Fig. 8. Here, the information matrix HA of the inspection matrix 对应 corresponding to the LDPC code defined by the specification of DVB-S.2, which is output by the LDPC encoding unit 21, is a loop structure. w The loop structure refers to a structure in which a row is consistent with the loops of other rows, and also includes, for example, in each P row, the position of each of the columns of the P row is the initial row of the row P, and is only the same as the division. The value obtained by the value q is proportional to the structure of the position after the cyclic shift in the row direction. Hereinafter, the P row of the loop structure is appropriately referred to as the number of rows of the loop structure. The LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 is as shown in Fig. 11, and has two types of LDPC codes of code length N of 64,800 bits and 16,200 bits. 133671.doc -75- 200947881 Now, if you look at the LDPC code in which the code length N of the two types of LDPC codes of 64800 bits and 16200 bits is 64800 bits, the code length N is 64800 bits. The coding rate of the LDPC code of the element is 11 as illustrated in FIG. Regarding the 11 LDPC codes whose code length N is 64800 bits, respectively, in either of the specifications of DVB-S.2, the number of rows P of the unit of the cyclic structure is the divisor of the parity. One of the approximate number of one and the other is 360. Further, regarding the LDPC codes in which the code lengths of the 11 coding rates are respectively 64,800 bits, the collocation system uses the value q which is different depending on the coding rate, and becomes [Expression]\4=9><?=9><360 is a value other than the prime number represented by 360. Therefore, the value 9 is also the same as the number of rows P of the unit of the cyclic structure, and the other one of the divisors of the same length, and the other number of the divisor except the number of rows in the unit of the cyclic structure. Obtain (the product of the divisor of the same position and the product of q is the same length M). As described above, when the information length is set to K, and the integer of 0 or more and less than P is set to X, and the integer of 0 or more and less than q is set to y, it will be from the LDPC as a parity interleaving. LDPC code of the encoding unit 21 Κ+qx+y+1 code bits in the same bit of the K+1 to K+M (=N) code bits, interleaved to the K+Py+ The position of x+1 code bits. According to the co-located interleaving, since the variable nodes (corresponding co-located bits) connected to the same check node are only separated by the number of rows P of the unit of the loop structure, that is, only 360 bits apart, When the length is less than 360 bits, the multiple of the variable nodes connected to the same check node can be prevented from becoming an error at the same time, and the result can improve the error of the 133671.doc -76-200947881 error. In addition, the LDPC code of the K + qx + y + 1 code bits interleaved to the position of the K + Py + x + 1 code bits is the same as the original check matrix 将The LDPC codes of the check matrix (hereinafter also referred to as the conversion check matrix) obtained by the +qx+y+l row replacement for the row replacement of the K+Py+x+l row are identical. Further, in the parity matrix of the conversion check matrix, as shown in Fig. 20, a pseudo-loop structure in which P rows (360 rows in Fig. 20) are used as a unit appears.于此 Here, a quasi-cyclic structure means that part of the exclusion is a structure of a cyclic structure. For the check matrix of the LDPC code specified in the specification of DVB-S.2, the conversion check matrix obtained by the row replacement corresponding to the co-interlace is part of the 360 columns χ 3 60 lines in the right corner portion thereof (the shift described later) The bit matrix) lacks only one element of 1 (the element that becomes 0), and therefore has a non-(complete) loop structure and becomes a pseudo-loop structure. Further, the conversion check matrix of Fig. 20 is a replacement for the original check matrix Η, in addition to the row substitution corresponding to the co-interleaving, and the column for the conversion matrix ❹ check matrix to be described later. ) The matrix after. Next, the whirling twist interleaving as the rearrangement processing by the whirling twist interleaver 24 of Fig. 8 will be described with reference to Figs. 21 to 24 . In the transmitting apparatus 11 of Fig. 8, in order to improve the frequency utilization efficiency, as described above, two or more bits of the code bit of the LDPC code are transmitted as one symbol. In other words, for example, when two bits of a code bit are used as one symbol, as a modulation method, for example, QPSK is used, and four bits of the code bit are used as one symbol 133671.doc -77-200947881 In the case of the modulation method, for example, 16QAM is used. When the octet or more of the code bit is transmitted as one symbol, if the symbol is erased or the like, the code bits of the symbol are all erroneous (erased). Therefore, in order to improve the decoding performance, the number of variable nodes (corresponding code bits) connected to the same check node is reduced to become the probability of erasure, and the code bit corresponding to one pay element must be avoided. The variable nodes are connected to the same check node. On the other hand, as described above, the inspection matrix H of the LDPC code defined by the DVB-S.2 _ specification output by the LDPC encoding unit 21, the information matrix 11 includes the cyclic structure, and the parity matrix Ητ has a staircase structure. Then, as shown in Fig. 2A, the check matrix of the LDPC code after the co-interleaving is the conversion check matrix, and the cyclic structure also appears in the parity matrix (correctly, as described above, the pseudo-loop structure). Figure 21 shows a conversion check matrix. That is, Fig. 21A shows a conversion check matrix of the check matrix H of the LDPC code whose code length is 648 bits and whose coding rate (1) is 3/4. ^ In Fig. 21A, in the conversion check matrix, the position of the element having a value of 1 is represented by (·). Figure 218 shows the [1)1> (: code, that is, the bit-interleaved LDPC code of the conversion check matrix of Fig. 21) as the object, and represents the demultiplexer 25 (the processing of Figure 2 is extended. The modulation mode is set to 16QAM, and the 4 wales of the § 己 体 31 31 , , , , , , , , , , , , , i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i The 4th line of the memory 31 is written in the direction of the wales in the J direction, and is read in 4 bit units to become the ^ symbol. The 成为 becomes the 4-bit code of the 1 symbol. The bit ^()31,;6233 may become corresponding to the i-column of the post-conversion check matrix of FIG. 21A in the case of the code bit 7G 0, corresponding to the code bit B, U2, B3 respectively. The variable node is connected to the same check node. The case where the code bit of the 4-bit symbol of the 1 symbol is corresponding to the code bit located in any one of the columns of the post-conversion check matrix If the symbol is erased, the same check node corresponding to the code bit B〇, b], b2, b< variable node respectively cannot be obtained. The result of the message, the decoding performance will be degraded. The encoding rate other than the encoding rate of 3/4 is also the same, and the complex digital bit corresponding to the complex variable node connected to the same check node may be used as a symbol of 16QAM. Therefore, the longitudinal twist interleaver 24 performs the twisting of the LD heart from the parity of the same position, and the twist line is twisted = wrong so as to correspond to any of the arrays located in the conversion check matrix. The complex digital bit is not included in one symbol. Fig. 22 is a diagram illustrating the whirling of the wagger. That is, Fig. 22 shows the memory 31 of the demultiplexer 25 (Figs. 16, 17). As illustrated in Fig. 16, there is a memory bit in the wale (longitudinal) direction, and the memory capacity of the %N/(mb) bit is recorded in the horizontal (horizontal) direction, 133671.doc -79· 200947881 by mb vertical Then, the whirch twist interleaver 24 controls the memory 3 to control the writing position of the LDPC code in the wale direction and the read position in the course direction. Row twisting interleaving. That is, in the longitudinal twisting interleaver 24, respectively for the plural longitudinal It is preferable to change the start writing position of the writing of the start code bit so that the complex digital bit which is read as one symbol in the course direction does not become one corresponding to any one of the columns in the conversion check matrix. The code bit (rearranges the code bits of the LDPC code so that the complex digital bits corresponding to any one of the columns in the check matrix are not included in the same symbol). Here, Fig. 22 shows the modulation mode. The configuration example of the memory 31 in the case where the multiple b is 16QAM and the multiplication b described in Fig. 16. Therefore, the number of bits m of the code bit which is the one symbol LDPC code is 4 bits, and the memory 3 1 is composed of 4 (= mb) wales. The whirch twist interleaver 24 (instead of the demultiplexer 25 of FIG. 16) is a wales from the left to the right direction, and the code bits of the LDPC code are made from the four wales constituting the memory 3 1 from top to bottom. Write in the direction (longitudinal direction). Then, if the writing of the code bit to the rightmost vertical line ends, the vertical twisting interleaver 24 is from the first column constituting all the wales of the memory 3 1 and is 4 bits in the horizontal direction (mb bit) The unit reads the code bit, and outputs the LDPC code as the reticular twisted interleaving to the replacement portion 32 of the demultiplexer 25 (FIG. 16, FIG. 17). Wherein, in the reticular twist interleaver 24, The address of the position at the beginning (topmost) of each wales is set to 0, and the address of each position in the walody direction is represented by an integer in ascending order. For the leftmost wales, the start write position is set as the address 133671. .doc -80- 200947881 , about U from the second ordinate, the start of the write position is set to address 2 立 'About the third traverse' will start the write position as the address is 4's on the 4th In the wales, the write start position is set to the position where the address is 7. The beginning of the write position is the address. In the wales of the position other than the position, write the code to the right position - j=* 兀 write to the bottom position, return to the beginning (the address is the position), and write until the position before the start of the write position... : Afterwards, the next (right) wales are written. ❹ 进行 By performing the wobble interleaving as above, the LDpcu^ with a code length N of 64800 for the specification of dvB S 2 can avoid the complex number corresponding to the same-check node. The complex digital bit of the variable node is used as one symbol of 16QAM (including the same symbol), and the decoding performance of the erased communication channel can be improved. Fig. 23 is a LDpc code for a coding rate of 648 〇〇 for a code length of DVB-S.2, and a memory 3 1 for a wobble interleave according to each modulation mode. The number of wales and the address at which to start writing. Since the multiple b is 1 ' and the modulation method is, for example, qPSK, the number of bits of the i symbol is „! is 2 bits. According to Fig. 23, the memory 31 is stored in the horizontal direction 2x 1 (= mb) 2 wales of the bit, remembering 64800/(2x1) bits in the waling direction. Then, in the 2 wales of the memory 31, the writing position of the first waling is set as the address. For the position of the second position, the write position of the second vertical line is set to the position of the address 2. In addition, the first to the first of FIG. 16 are used as an alternative to the replacement processing of, for example, the demultiplexer 25 (FIG. 8). 3 In any of the alternatives, etc. 133671.doc • 81 · 200947881 When the multiple b becomes 1. Since the multiple b is 2, and the modulation method uses, for example, QPSK, the i symbol is 7L. In the case of 2 bits, 'According to Fig. 23, the memory 3 i contains 4 vertical lines of 2x2 bits in the horizontal direction, and 64800/(2x2) bits in the vertical direction. Then, the memory In the four wales of 31, the start write position of the first wales is set to the position of 〇, and the start position of the second traverse is set as the address. In the position of 2, the start position of the 3rd wales is set to the position where the address is *, and the start write position of the 4th traverse is set to the position of the address 7. In addition, as, for example, the demultiplexer 25 ( The replacement method of the replacement processing of FIG. 8) adopts the fourth alternative of FIG. 17, etc., and the multiple b becomes 2. Since the multiple b is 1, and the modulation method is, for example, 16QAM, the number of 1-bit symbols In the case where the melon is 4 bits, according to Fig. 23, the memory 31 contains 4 wales of 4x1 bits in the course direction and 64800/(4XI) bits in the walith direction. Then, the memory In the four wales of 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is ◎ 2 and the start of the third vertical line is written. The position is set to the position of 4, and the write position of the 4th traverse is set to the position of the address 7. Since the multiple b is 2, and the modulation method is, for example, 16qam, the number of 1 symbol In the case where the claw is 4 bits, according to FIG. 23, the memory 31 contains 8 vertical lines of 4x2 bits in the course direction, in the vertical direction. Memory 64800/(4x2) bits. Then, in the 8 wales of the memory 31, the first wales are written at the beginning of the 133671.doc -82 * 200947881, and the address is 0. 2 The starting position of the vertical string is set as the address of the address ' 'The starting position of the 3rd vertical line is set to the position where the address is 2, and the writing position of the 4th vertical line is set as the decay & % - The address is the position of 4, the beginning of the 5th ordinate is written as the position where the address is 4, 'the start position of the 6th waling is set to the position where the address is 5', and the writing position of the 7th waling is set as the starting position. The address is at the position of 7, and the start position of the eighth vertical line is set to the position where the address is 7. Since the multiple b is 1, and the modulation method is, for example, 64qam, if the position of the 1 symbol is τ, the number of the claws is 6 bits, and according to the diagram η, the memory 31 is stored in the horizontal direction. Longitudinal, remembers 64800/(6XI) bits in the wale direction. Then, in the six wales of the memory 31, the start position of the (10)th line is not the address of the address ', and the start position of the second row is set to the address of the address 2, the third wales The start write position is set to the position where the address is $, the start position of the *th vertical line is set to the address of the address 9, and the start write position of the fifth vertical line is set to the position of the address of 10, the sixth vertical The start of the line write position is set to the address of 13. Since the multiple b is 2', for example, 64qam is used as the modulation method, and therefore, the number of bits m of one symbol is 6 bits, and according to FIG. 23, the memory 31 contains 6 χ 2 bits in the horizontal direction. 12 vertical lines, remembering 64800/(6x2) bits in the wale direction. Then, in the 12 wales of the memory 31, the beginning of the ρ vertical line is written as the bit S of the address, and the start position of the second traverse is set to the position where the address is 0. The start of the write position is set to the address of 2, the start position of the 4th run is set to the address of 2, and the vertical jump is opened 133671.doc •83-200947881 The address of the address is 3, the write position of the sixth vertical line is set to the address of 4, the write position of the 7th vertical line is set to the position where the address is 4, and the write position of the 8th vertical line is set. The address is the position of 5, the start position of the ninth vertical line is set to the position where the address is 5, and the first write position of the first vertical line is "the position of the address is 7, the third vertical position" The start write position is set to the position where the address is 8, and the start write position of the 12th vertical line is set to the position where the address is $. Since the multiple b is 1, and the modulation method is, for example, 256QAM, if the number of bits 1 of the 1-symbol is 8 bits, according to FIG. 23, the memory 31 contains 8x1 bits in the horizontal direction. The 8 vertical lines are 64800/(8XI) bits in the vertical direction. Then, among the eight wales of the memory 31, the start write position of the first walt is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address, the third vertical The start of the write position is set to the address of 2, the start write position of the 4th vertical is set to the address of 4, and the write position of the 5th vertical is set to the address of 4, the sixth The start position of the wales is set to the position where the address is 5, the start write position of the seventh wales is set to the position of the address 7, and the start write position of the eighth traverse is set to the position of the address 7. ❹ Since the multiple b is 2, and the modulation method is, for example, 256QAM, if the number of bits m of one pay is 8 bits, according to FIG. 23, the memory 31 contains 8x2 bits in the horizontal direction. 16 vertical lines of the Yuan, remembering 64800/(8x2) bits in the longitudinal direction. Then, among the 16 wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start of the write position is set to the address of 2, 133671.doc •84- 200947881 The start position of the 4th vertical line is set to the address of 2, and the write position of the 5th vertical line is set as the address. For the position of 2, the start position of the 6th wales is set to the position where the address is 3, the start write position of the 7th ordinate is set to the position where the address is 7, and the start write position of the 8th walt is set as the position. The address is the position of 15, the write position of the ninth wales is set to the address of the address of 16, the start position of the first wales is set to the position of the address of 20, and the write position of the eleventh waling is set. The address of the address is 22, the write position of the 12th wales is set to the address of 22, and the write position of the 13th traverse is set to the address of 27, and the beginning of the 14th vertical line is written. The position is set to the position of 27, the start position of the 15th traverse is the position where the address is 28, and the start position of the 16th traverse is set to the address of 3 2 Home. Since the multiple b is 1, and the modulation method is, for example, 1〇24QAM, when the number of bits of the 1-symbol m is 1〇, the memory 31 is stored in the horizontal direction according to FIG. The 纵 丨〇 纵 记忆 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Write at the beginning of the first vertical line

Then, the position of the 10 wales of the memory 31 is set as the address of 〇, the write position of the 2nd ordinate is set to the address of 3, and the write position of the 3rd row is set as the address. For the position of 6, the write position of the fourth vertical line is set to the position of the address of 8, the start position of the fifth vertical line is set to the position of the address of 11, and the write position of the sixth vertical line is set as the position. The address is 13, the start position of the 7th ordinate is set to the address of 15, the start position of the 8th traverse is set to the address of the address, and the write position of the 9th traverse is set. The address is the location of 18, and the first write position of the first wales is set to the position where the address is 20. 133671.doc •85- 200947881 Since the multiple b is 2, and as a modulation method, for example, 1〇24QAM is used, if the number of bits of 1st 7L is i 〇 bit, if according to FIG. 23, the memory 31 It is a memory of 64800/(l〇x2) bits stored in the longitudinal direction of 2 纵 记忆 记忆 记忆 记忆 记忆 记忆. Then, in the 20 wales of the hexadecimal body 31, the start writing position of the ith wales is set to the position where the address is ', and the writing position of the second waling is set to the position of the address 1, the first 3 The starting position of the vertical line is set to the position where the address is 3, and the writing position of the 4th vertical line is set to the position where the address is 4, and the 5th vertical line is opened.

The initial write position β is also the position where the address is 5, the start position of the sixth vertical line is set to the address of the address 6, and the start write position of the seventh vertical line is set to the position of the address of 6, the eighth vertical The start write position of the line is set to the address of 9, the start write position of the ninth vertical line is set to the address of the address 13, and the start write position of the first job line is set to the position of the address 14, the u vertical The start write position of the line is set to the address of 14, the start write position of the 12th vertical line is set to the position where the address is μ, and the start write position of the 13th vertical line is set as the address to be the position, the μ The starting write position of the mediastinum is set to the position of the address 21, and the beginning of the 15th vertical line is written.

The position is set to the address of 23, the start write position of the 16th vertical line is set to the address of 25, and the start write position of the 7th vertical line is set to the position of the address h, the 18th vertical line The start write position is set to the position where the address is %, the start write position of the βth column is set to the address of 28, and the start write position of the 2nd line is set to the position of 30. Since the multiple b is 1, and the modulation method is, for example, 4〇96qam, the number of bits of the 1 symbol is „! is 12 bits. According to Fig. 23, the memory 31 is included in the memory of 12χ1. 12 vertical lines of Yuan, Yusaki 133671.doc -86 - 200947881 Direction memory 64800/(12x1) bits. Then, in the 12 vertical lines of § 体 体 31, the writing position of the first waling is set. The address of the address is 〇, the write position of the second traverse is set to the address of 〇, the write position of the third traverse is set to the position of address 2, and the write position of the fourth trajectory is started. The address is set to the position of 2, the write position of the 5th vertical line is set to the position where the address is 3, and the write position of the 6th vertical line is set to the position where the address is 4, and the start of the 7th vertical line is written. The position is set to the position of 4, the start position of the 8th ordinate is set to the address of 5, and the write position of the ninth walt is set to the position of 5, the first 〇 之The start write position is set to the position of the address 7, the start position of the U walt is set to the address of 8, and the start position of the 12th traverse is set to the address of 9 Since the multiple b is 2, and the modulation method is, for example, 4〇96QAM, the number of bits of 1 is „! is 12 bits, and according to the figure, the memory 31 is contained in the horizontal direction. Column direction memory 12><2 bits of 24 wales memory 64800/(12x2) bits in the wale direction. ❹ Then, in the wales of the memory 31, the writing position of the first vertical line is set to the position of the address, and the writing position of the second vertical line is set to the position of the address of 5, the third vertical The start write position of the line is set to the position where the address is $, the start write position of the fourth vertical line is set to the position of the address of 8, and the start write position of the red vertical line is set to the position of the address of 8, the sixth vertical The start position of the line is set to: The address of the address is 8 'The start position of the 7th vertical line is set as the address (4), and the write position of the 8th vertical line is set to the address of 1〇, the 9th position The starting write position of the mediastinum is set to the position where the address is 10, the start of the first vertical line is set to the position where the address is 12, and the start of the 11th vertical line is set as the address 133671.d〇 ( -87- 200947881 is the position of 13, the writing position of the 12th waling is set to the address of "the position, the writing position of the 13th waling is set to the position of 丨7, the 14th waling The start write position is set to the address of 19, the start position of the 15th traverse is set to the address of 21, and the write position of the 16th traverse is set to the address of 22 The write position of the 17th wales is set to the address, the write position of the 18th ordinate is set to the address of 26, and the write position of the first trajectory is set to the address of 37. The position of the start position of the 2nd wales is set to the address of 39, the start write position of the 21st wales is set to the address of 40, and the write position of the 22nd walt is set as the address. For the "position", the write position of the 23rd wales is set to the address of 41, and the write position of the traverse is set to the address of 41. Figure 24 is for the specification of DVB_S.2 The predetermined code length N is an LDPC code of a coding rate of l62 oo, and the number of wales of the memory 31 and the address of the start write position necessary for the reticular interleaving are expressed in each modulation mode. 1, and as a modulation method, for example, QpsK is used. Therefore, in the case where the number of bits of the symbol element is 2 bits, according to FIG. 24, the memory system contains 2 vertical bits of 2x1 bits in the horizontal direction. Line, in the vertical direction, remember 1620 〇 / (2xl) bits. Then, in the two wales of memory 31, respectively, the 丨 丨 丨The write position is set to the position of the address, and the start position of the second vertical line is set to the position of the address 〇. Since the multiple b is 2, and the modulation method is, for example, QpSK, the number of bits of the i symbol is m. In the case of 2 bits, according to Fig. 24, the memory system contains 4 vertical lines of 2x2 bits in the horizontal direction, and 133671.doc -88-200947881 recalls 16200/(2x2) in the longitudinal direction. Then, in the four wales of the memory 31, the start write position of the ninth wales is set as the address of the 〇, and the start write position of the second trajectory is set to the position of the address of 2, The write position of the third vertical line is set to the position where the address is 3, and the start write position of the *th vertical line is set to the position where the address is 3. Since the multiple b is 1, and the modulation method is, for example, 16qam, when the number m of the 1-bit το is 4 bits, according to FIG. 24, the memory 31 contains 4 χ 1 bits in the horizontal direction. The four wales are in the traverse direction ^ memory 16200 / (4 X 1) bits. Then, among the four wales of the memory 31, the start write position of the (10)th line is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address of 2, the third vertical line The start write position is set to the position where the address is 3, and the start write position of the *th vertical line is set to the position where the address is 3. Since the multiple b is 2, and the modulation method is, for example, 16qam, the 1st/〇 position το „! is 4 bits, and according to FIG. 24, the memory 〇 31 is stored in the horizontal direction memory. 8 vertical lines of the Μ bit, in the longitudinal financial memory of 1620 〇 / (4 χ 2) bits. :, after the ' δ recalled body 31 of the eight wales, respectively, the beginning of the first line of writing position suction position The address is the location of the 〇 第 第 第 写 写 写 写 写 写 写 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The position of the 5th vertical line of the position is set to the position of the address in the address of 7 and the start position of the 6th vertical line is set as the address 'The start position of the 7th vertical line is set as the address is In the position of 2〇, the writing position of the 8th waling is set to the position of the address 21. The 133671.doc -89- 200947881 Since the multiple b is 1, and the modulation method is, for example, 64Qam, the position of 1 symbol In the case where the number m is 6 bits, according to the figure, the memory 31 contains 6 vertical lines of 6x1 bits in the horizontal direction and 16200/(6x1) in the vertical direction. Then, among the six wales of the memory 31, the start write position of the ninth wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address. The start position of the third wales is set to the position of the address 2, the fourth

The write start position of the wales is set to the position where the address is 3, the start write position of the 5th ordinate is set to the position of the address 7, and the start write position of the sixth traverse is set to the position of the address 7. W, since the multiple b is 2, and the modulation method is, for example, 64qam, if the number of bits of the 1 symbol is 6 bits, according to FIG. 24, the memory 31 contains 6x2 bits in the horizontal direction. The 12 vertical lines of the element store 16200/(6x2) bits in the longitudinal direction. Then, in the 12 vertical lines of the memory 31, the start write position of the p vertical line is set to the position where the address is 0, and the start write position of the second vertical line is set to the position where the address is 0. The third vertical line The starting write position is set to the address. Position, ❹ The start position of the 4th rowth is set to the position where the address is 2, and the start position of the 00th traverse is set to the position where the address is 2'. The start position of the 6th waling is set as the address. For the position of 2, the write position of the 7th wales is set to the position where the address is 3, the start write position of the 8th ordinate is set to the position where the address is 3, and the write position of the ninth walt is set as the position. The address is the position of 3, the start position of the first line is set to the position where the address is 6 'the start position of the uth vertical line is set to the position where the address is 7'. The write position of the 12th vertical line is set as the bit position. The address is 7 position. 133671.doc -90- 200947881 Since the multiple b is 1, and the modulation method is, for example, 256QAM, if the number of bits of the 1 symbol is 8 bits, according to Fig. 24, the memory 31 is included in The column direction stores 8 vertical lines of 8x1 bits, and stores 16200/(8x1) bits in the wale direction. Then, in the eight wales of the memory 3 1 , the erroneous start write position is set to the address of 0, and the start position of the second traverse is set to the address of 0, the third The start position of the wales is set to the position of 〇, the write position of the 4th traverse is set to the address of 1, and the write position of the 5th traverse is set to the position of the address of '7' The start position of the 6 wales is set to the position where the address is 20, the start write position of the 7th wales is set to the position of 汕, and the start write position of the 8th ordinate is set to the position of the address 21. Since the multiple b is 1, j_ is used as the modulation method, for example, 1〇2 is used, so if the number of the 1st 7G is 10 bits, the memory 31 is included in the course direction according to FIG. The 10 vertical lines of the memory bit store 16200/(1〇X1) bits in the longitudinal direction. Q ”, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, At the position, the start position of the third vertical stroke is set to the position where the address is 2, the start write position of the fourth vertical line is set to the position where the address is 2, and the start write position of the fifth vertical line is set as the address is 3 夕 里 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 松 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 In the class of Yi Yi, write the position s and make the address 4, the 9th vertical

The start write position is set to the position where the address A is located at 5, and the start write position of the first vertical line is set to the position where the address is 7. 133671.doc -91 · 200947881 Since the multiple b is 2, and as a modulation method, for example, 1〇24qam is used, the number of 1s is 7L! ^, in the case of a bit, according to the figure, the memory 31 is 3 (9) wales of i (four) bits are memorized in the horizontal direction, and 16200/(10x2) bits are memorized in the wales.

Then, in the 2G wales of the memory 31, the start position of the first wales is set as the address of the 〇 position, and the start position of the second traverse is set as the address of the ' position. The start write position of the line is set to the position of the address, the start write position of the 4th vertical is set to the address of 2, and the write position 6 of the 5th vertical start is set to the position of 2, the first The start position of the 6 wales is set to the position where the address is 2'. The write position of the 7th ordinate is set to the address of 2, and the write position of the 8th traverse is set to the address of 2 & Set, the ninth vertical line: the initial write position is set to the address of 5, the beginning of the first line of the write position and the address is 5 position 'the start position of the ii vertical line is set to address 5 The position of the beginning of the 12th wales is set to the position where the address is 5, the start write position of the first Π 设 is set to the position of the address, the κ 纵: the initial write position is set as the address For the position of 7th, the start position of the 15th walt is the position where the address is 7, the start position of the 16th traverse is set to the position of the address 7, and the write position of the 17th wal is set as the start position. The address of the address is 7 and the start write position of the 18th vertical order is set to the address of 8, and the write position of the wales is set to the address of 8 at the beginning of the wales, and the address of the 20th ordinate is the address. It is a position of 10. X is a multiple of b, and as a modulation method, for example, 4G96QAM is used. In the case where the number of bits 111 is 12 bits, according to FIG. 24, the memory 31 contains 12x1 bits in the horizontal direction. 12 vertical lines, in the vertical line 13367] .doc -92- 200947881 Direction memory 16200 / (12 χ 1) bits. Then, in the 12 wales of the suffix 3 1 , the start write position of the 丨 丨 设 is set as the address of the 〇, and the start write position of the 2nd row is set as the address of the ,, The write position of the third vertical line is set to the position of the address, the write position of the fourth vertical line is set to the position of the address 2, and the write position of the fifth vertical line is set to the position of the address of 2. 'The start position of the sixth vertical line is set to the position where the address is 2, and the write position of the seventh vertical line is set to the address of ^.

The write position of the 8th vertical line is set to the position where the address is 3, the start write position of the 9th vertical line is set to the position where the address is 3, and the start write position of the first line is set to the address of 6 The position, the start position of the uth ordinate is set to the position of the address 7, and the start position of the 12th traverse is set to the position of the address 7. Since the multiple b is 2, and the modulation method is, for example, 4〇96qam, the number of 1-bit symbols is 12 bits, and according to Fig. 24, the memory 31 is stored in the horizontal direction (2)] The 24 vertical lines of the bit store 16200/(12x2) bits in the wale direction. Then, among the 24 townships + and k mediastinums of the memory 3, the start position of the first wales is set as the address of the 笛 position, and the start position of the second wales is set as the address. For the position of the 〇, the opening position of the third vertical line is set to the position of the 〇, the start position of the fourth traverse is the position where the address is 〇, and the position of the fifth ray is written. The address written as the address of the 〇 第 第 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写 写The write position is the position where the address is 1, and the ninth vertical line::: writes τ as the address of the address, the beginning of the first line of the write position, and the position of the third line is 1; the beginning of the 11th vertical line is written. The location is set to address 133671.doc •93- 200947881 is the position of 2, the write position of the 12th wales is set to the address of 2, and the write position of the 13th trajectory is set to the location of 2 The write position of the 14th vertical line is set to the position where the address is 3, the start write position of the 5th vertical line is set to the position where the address is 7, and the start write position of the 16th vertical line is set as the address. The position of the 9th position is set to the position where the address is 9 at the beginning of the 17th wales, the write position at the beginning of the 18th ordinate is set to the position of the address 9, and the start of the 19th traverse is set as the address. For the position of 10, the start position of the 2nd wales is set to the address of 10, and the write position of the 21st traverse is set to the position of 1 '. The start position of the 22nd wales is set. The address of the address is 1 〇, the write position of the twentieth wales is set to the address of 10, and the write position of the 24th traverse is set to the address of the address 11. Next, the transmission processing performed by the transmitting apparatus u of Fig. 8 will be described with reference to the flowchart of Fig. 25. The LDPC encoding unit 21 waits for the supply of the target data, and encodes the target data into an LDPC code in step S1, and supplies the LDPC code to the bit interleaver 22'. The processing proceeds to step S102. In step S102, the bit-parent-alternator 22 performs bit interleaving on the LDPC code from the LDPC encoding unit 21, and supplies the symbolized symbol of the LDPC code interleaved to the mapping unit 26. The processing proceeds to step S103. That is, in step S102, in the bit interleaver 22, the parity interleaver 23 performs the co-located interleaving by LDPC code from the LDPC encoding unit 21, and supplies the LDPC code of the co-located interleaving to the whirling twist interleaver. 24 〇^ 33671.do, -94· 200947881 The whirling torsion interleaver 24 takes the LDPC code from the co-located interleaver 23 as a target, performs wobble interleaving, and supplies it to the demultiplexer 25. The demultiplexer 25 replaces the code bits of the LDPC code which are longitudinally twisted and interleaved by the wobble interleaver 24, and performs the symbol bit of the replaced code bit as a symbol (representing the symbol Replacement processing of bits). Here, the replacement processing by the demultiplexer 25 may be performed in accordance with the first to fourth alternatives shown in Figs. 16 and 17, or may be performed in accordance with the distribution rule. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits of the symbol, which will be described later in detail. The symbols obtained by the replacement processing of the demultiplexer 25 are supplied from the demultiplexer 25 to the mapping unit 26. In step S103, the mapping unit 26 maps the symbols from the demultiplexer 25 to the signal points determined by the modulation method of the quadrature modulation by the quadrature modulation unit 27, and supplies them to the orthogonal modulation. In the variable portion 27, the processing proceeds to step S104. The quadrature modulation unit 27 performs the orthogonal modulation of the carrier in accordance with the signal point from the mapping unit 26 in step S104, and the processing proceeds to step S105 to transmit the modulated signal obtained as a result of the quadrature modulation. And finally processed. Further, the transmission processing of Fig. 25 is repeated in the pipeline. As described above, by performing the co-located interleaving or the wobble interleaving, the fault tolerance for erasing or bursting errors in the case where the complex digital bit of the LDPC code is transmitted as one symbol can be improved. Here, in FIG. 8, for convenience of explanation, the parity interleaver 23 which is a block which performs the co-located interleaving, and the block 133671.doc-95-200947881 vertical twist interleaver 24 which performs the wobble interleaving are individually formed. However, the co-location can also be performed by the body position t (10) and the longitudinal torsion interleaver 24 and the longitudinal torsion interleaving - both by the writing and reading of the code bit: the memory, by A matrix in which the address of the code bit is written (the address written) is converted into an address. The address of the reading position of the weight code (reading so 'if the multiplication is obtained in advance, the matrix obtained by the matrix of different parental errors and the matrix obtained by the matrix representing the twisting of the wales are obtained. Perform co-location interleaving, and 1 borrowed and escaped and further interleaved the co-located ©

The Pc code is the result of the twisting and interlacing. Further, the demultiplexer 25 may be integrally formed in addition to the co-interleaver 23 and the whirteen (four) interleaver 24. The replacement processing performed by the decryption processor 25 can also be expressed by converting the write address of the memory 31 of the memory c code into the read address. = If this is obtained by pre-determining a matrix representing the co-located interlacing, a matrix representing the two-interlaced matrix, and a matrix obtained by the matrix representing the replacement process, then the matrix is uniformly interleaved, the longitudinal twist is interleaved, and In addition, in the case of the in-place interleaving and the longitudinal twisting interleaving, only the middle or both sides may not be performed. Next, with reference to FIG. 26 to FIG. 28, a simulation of the measurement error rate (bit error rate) for the transmission device of FIG. 8 is described. FIG. 26, 133671.doc-96-200947881 The simulation system adopts D. /U is a channel of OdB with flutter. Figure 26 is a diagram showing the model of the communication channel used for the simulation. That is, Fig. 26A shows a model of the flutter used in the simulation. Further, Fig. 26B shows a model of the chattering channel of the flutter represented by the model of Fig. 26A. Further, in Fig. 26B, Η represents the model of the flutter of Fig. 26A. Further, Fig. 26Β' Ν indicates ICI (Inter Carrier Interference), and in the simulation, the expected value E[N2] of the power is approximated by AWGN. 27 and 28 show the relationship between the error rate obtained by the simulation and the Doppler frequency fd of the flutter. Further, Fig. 27 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 16QAM and the coding rate (1) is (3/4), and the alternative is the first alternative. Further, Fig. 28 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 64QAM and the coding rate (r) is (5/6), and the alternative is the first alternative.进步 Progress and Lu, in Fig. 27 and Fig. 28, the thick line indicates the relationship between the error rate and the Doppler frequency fd in the case of performing the co-interleaving, the longitudinal torsional interleaving and the replacement processing, and the thin line indicates that only the co-interlacing is performed. The relationship between the error rate in the case of the twisting interleaving and the replacement processing in the replacement processing and the Doppler frequency fd. In any of Figs. 27 and 28, it can be seen that the case where all of the co-located interleaving, the waleping, the parental error, and the replacement processing are performed is more than the case where the replacement processing is performed, and the error rate is increased (smaller). 133671.doc • 97- 200947881 Next, the LDPC encoding unit 21 of Fig. 8 will be further explained. As illustrated in Fig. 11, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and 8/9 (Fig. 11B). The LDPC encoding unit 2 1 encodes the LDPC code of each encoding rate of 64800 bits or 16200 bits according to the code check matrix 准备 prepared according to each code length N and each coding rate ( Error correction code). FIG. 29 shows an example of the configuration of the LDPC encoding unit 21 of FIG. The LDPC encoding unit 21 is composed of an encoding processing unit 60 1 and a storage unit 602. The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, a coded parity calculating unit 615, and a control unit 616, and supplies them. The LDPC code of the target data to the LDPC ® encoding unit 21 supplies the LDPC code obtained as a result to the bit interleaver 22 (Fig. 8), that is, the coding rate setting unit 611 is based on, for example, the operation of the operator. , to set the code length N and coding rate of the LDPC code. The initial value table reading unit 612 reads out the check matrix initial value table described later in accordance with the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602. 133671.doc 98 face 200947881 The check matrix generation unit 613 is based on the check matrix initial value table read by the initial value table read unit 6丨2, and is executed every 36 lines in the row direction (the number of rows of the cycle structure unit P) In the period, the element corresponding to the information matrix HA2 1 of the code length N set by the coding rate setting unit 61 1 and the information length κ (= code length N_colocated length M) of the coding rate is arranged to generate the inspection matrix ^ And stored in the memory department. The information bit reading unit 614 reads (takes) the information bits of the information length K from the target material supplied to the LDPC encoding unit 21. The horse-synchronizing transfer unit 615 reads the check matrix H generated by the check matrix generation unit 613 from the storage unit 602, and calculates the parity bit of the information bit read by the information bit read unit 614 based on the specific expression. Generate a codeword (LDpc code). The control unit 616 controls each block constituting the encoding processing unit 6〇. The memory unit 602' stores a complex check matrix initial value table and the like corresponding to the complex coding rates shown in Fig. 2 for the two code lengths N of 648 及 and 162 分别, respectively. Further, the storage unit 〇2 temporarily stores the data necessary for the processing of the coding unit 601. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21 of Fig. 29. In step S201, the coding rate setting unit 611 determines (sets) the code length N and the coding rate r at which the LDpc is encoded. In step S202, the initial value table reading unit 612 reads out a predetermined check matrix initial value table corresponding to the code length N determined by the coding rate disparity unit 611 and the coded heart from the storage unit 6〇2. In step S203, the inspection matrix generation unit 613 reads the inspection matrix initial value table read from the storage unit 6〇2 by the initial value table readout 612, and obtains (generate 133671.doc -99-200947881). The coding rate setting is <1, and the inspection matrix H of the LDPC code of the code length coding rate determined by the 66疋 unit 6U is supplied to the storage unit 602 and stored. In step S204, the information bit reading unit 6 reads the information length κ corresponding to the code length Ν and the coding rate r determined by the encoding rate unit 611 from the supply LDPC encoding suppression target (4). = 资讯 资讯 资讯 资讯 , , , , , 读出 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 读出 读出 读出 读出 读出 读出 + The parity calculation unit 615.

In step S205, the encoding parity calculating unit 615 sequentially calculates the parity bits of the codeword c conforming to the equation (8).

HcT = 〇 • (8) In the equation (8), c denotes a column vector as a codeword (LDpc code), and γ denotes a transposition of the column vector c. Here, as described above, in the case where the column vector A represents the portion of the information bit in the column vector C of LDP (^|(1 code word), and the column vector indicates the portion of the parity bit, the column vector ( : can be represented by the column vector A as the information bit and the column vector τ as the parity bit, and expressed by the formula c=[A丨τ]. Check the matrix Η and the column vector as the LDPC code C=[A| T] must conform to the formula 〇HcT=0 ' as the column vector τ constituting the parity of the column vector c=[a|t] according to the formula Hct=〇, which can be obtained by checking the parity matrix of the matrix h=[Ha1Ht] When Ητ is the step structure shown in FIG. 1A, the elements of the first column of the row vector HeT of the formula Hct=〇 are sequentially obtained by sequentially making the elements of the respective columns 〇. 615. If the same bit τ is obtained for the information bit A, the code word c=[A|T] 133671.doc •100- 200947881 represented by the information bit Α and the parity bit 作为 is used as the information. The LDPC encoding result of the bit A is output. Further, the code word c is 64800 bits or 16200 bits. Thereafter, in step S206, the control unit 616 determines whether or not the LDPC is finished. In step S206, if it is determined that the LDPC encoding is not finished, that is, for example, if there is still object data to be LDPC-encoded, the processing returns to step S201, and the processing of steps S201 to S206 is repeated as follows. S206, in the case where it is determined that the LDPC code is terminated, that is, for example, when there is no object data to be LDPC-encoded, the LDPC codec unit 21 ends the processing. As described above, the code length N and each code rate are prepared. The check matrix initial value table of r, the LDPC encoding unit 21 generates an LDPC code 'of a specific code rate r of a specific code length N by using a check matrix initial value table corresponding to the specific code length N and a specific coding rate r Checking the matrix Η is performed. Checking the matrix initial value table will check the information matrix HA corresponding to the code length N and the information length K of the code length r according to the LDPC code (the LDPC code defined by the check matrix )) The position of the element of 1 (Fig. 9) is expressed in units of 360 lines (the number of rows P of the cyclic structure), and is prepared one by one according to the code length N and the inspection matrix of each coding rate r. Figure 58 shows DVB- The initial value table of several check matrices specified in the specification of S.2. That is, Fig. 31 shows that the code rate r of the code length Ν of 16,200 bits is 2/3 as defined by the specification of DVB-S.2. Check the initial value table of the check matrix of the matrix 。. Figure 32 to Figure 34 show the code length Ν 133671.doc -101 - 200947881 for the code length of DVB-S.2 is 64800 bits, the encoding rate r is 2/3 Check the initial table of the check matrix of the matrix. Further, Fig. 33 is continued from Fig. 32, and Fig. 34 is continued from Fig. 33. Fig. 35 is a table showing the check matrix initial value of the check matrix 编码 for the code rate r of 16200 bits, which is defined by the specification of DVB-S.2, which is 3/4. Fig. 36 to Fig. 39 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code rate 64 of 64,800 bits with a code length r of 3/4 as defined by the specification of DVB-S.2. In addition, Fig. 37 is continued from Fig. 36, and Fig. 38 is continued from Fig. 37. Moreover, Fig. 39 is continued from Fig. 38. Fig. 40 is a table showing the check matrix initial value of the check matrix 编码 for the code rate r of 16200 bits, which is defined by the specification of DVB-S.2, which is 4/5. Fig. 41 to Fig. 44 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits and the code rate r of 4/5 as defined by the specification of DVB-S.2. In addition, FIG. 42 is a diagram continued from FIG. 41, and FIG. 43 is a diagram connected to FIG. Moreover, Fig. 44 is a view subsequent to Fig. 43. Fig. 45 is a table showing the check matrix initial value of the check matrix 编码 of the code rate r of 5/6 with a code length 16 of 16200 bits as defined by the specification of DVB-S.2. Fig. 46 to Fig. 49 are diagrams showing the check matrix initial value table of the check matrix 编码 for the coding rate r of the code length r of 64,800 bits as defined by the specification of DVB-S.2. Further, Fig. 47 is a view continuing from Fig. 46, and Fig. 48 is a view continuing from Fig. 47 of 133671.doc-102-200947881. Moreover, Fig. 49 is continued from Fig. 48. Fig. 50 is a table showing the check matrix initial value of the check matrix 编码 for the coding rate r of the code length r of 16200 bits as defined by the specification of DVB-S.2. Fig. 51 to Fig. 54 are diagrams showing the check matrix initial value table of the check matrix η for the coding rate 1_ of 8/9 whose code length ν is 04800 bits, which is defined by the specification of DVB_S.2. Further, Fig. 52 is continued from Fig. 51, and Fig. 53 is continued from Fig. 52. Moreover, Fig. 54 is continued from Fig. 53. Fig. 55 to Fig. 58 are diagrams showing the check matrix initial value table of the check matrix η for the coding rate 9/1 码 of the code length 64 64800 bits prescribed by the specification of DVB_S.2. Further, Fig. 56 is continued from Fig. 55, and Fig. 57 is continued from Fig. 56. Further, Fig. 58 is continued from Fig. 57. The inspection matrix generation unit 613 (FIG. 29) obtains the inspection matrix 如 by using the inspection matrix initial value table as follows. That is, Fig. 59 shows a method of obtaining the inspection matrix 从 from the inspection matrix initial value table. Further, the check matrix initial value table of Fig. 59 indicates that the code length specified for the specification of DVB-S.2 shown in Fig. 31 is 162 bits of the coding rate "Check matrix of 2/3" Check the matrix initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix fjA (Fig. 9) according to the code length N of the LDpc code and the information length K of the coding rate r, for every 360 lines (cycle construction) The table of the number of rows of the unit p), in the i-th column, check the number of the 1+36 (^(^) line i of the matrix 133671.doc -103- 200947881 number (check the matrix Η The number of rows in the column of 1 column is set to the number of the row weights of the row of the l+36〇x(il) row. This is because the check matrix 对应 corresponds to the co-located length μ The parity matrix Ητ (Fig. 9) is determined as shown in Fig. 19, so that the information matrix ηα corresponding to the information length κ (Fig. 9) can be obtained from the inspection matrix initial value table. The number of tables k + Ι differs according to the information length κ. The relationship of equation (9) holds between the information length K and the number of columns k + i of the check matrix initial value table. K = (k + l) x360 . (9) Here, the 360 of the equation (9) is the number of rows of the unit of the loop structure described in Fig. 20. In the check matrix initial value table of Fig. 59, the rows from the !! column to the third column are arranged. 3 The value 'from the 4th column to the k+1th column (the 30th column in Fig. 59) is arranged with three numerical values. Therefore, the row of the inspection matrix H obtained from the inspection matrix initial value table of Fig. 59 is obtained. The weight is from the 1st line to the 1+36〇χ(3-1)-1 behavior 13 from the 1+3 6〇x(3-l) line to the third behavior 3. The initial value of the check matrix in Fig. 59 The first column of the table is 〇, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the inspection matrix η, the column number is 〇, 2084 The elements of 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and other elements are 0). 133671.doc 200947881 Moreover, the check matrix initial value table of Figure 59 The second column is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108, which is shown in the 361th of the inspection matrix η (=1+36〇χ(2) -1)) Line, the column number is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799 '3529, 373, 971, 4358, 3108. The elements are 1. For the above 'check matrix initial value table Will check The matrix of the matrix of the matrix is represented by every 360 lines. Check the line other than the l+36〇x(il) line of the matrix ,, that is, the line from the 2 + 36 〇 x (il) line to the 36 〇 xi line will be determined by checking the matrix initial value table. The element of the 1st line of the l+36〇x(il) is cyclically shifted in the downward direction (the direction below the line) in the same direction length M. That is, for example, the 2+36〇x(il) line only shifts the l+36〇x(il) line downward by only M/360 (=q), followed by the 3 + 36〇χ ( Μ) The line is rotated by 2xM/36〇(=2xq) in the downward direction of the l+36〇x(il) line (the second + 36〇x(i-1) line is only cyclically shifted downward. Bit M/36〇(=q)). Now, if the value of the jth row (jth from the left) of the i-th column (the first one from the top) of the check matrix initial value table is expressed as hi, 3, and the wth row of the matrix H will be checked. The number of the element of the jth is indicated as Hw, and then the number 11 of the element of the first row of the row other than the l+36〇x(ii) of the matrix 检查 is called the formula ( 10) Find.

Hw.j=mod{hiJ+m〇d((w-l), P)xq, M) • (10) where 'mod(x,y) means the remainder after dividing y by X. 133671.doc -105· 200947881 and 'P is the number of rows of the above-mentioned cyclic structure, for example, the specification of DVB-S.2 is 360 as described above. Further, q is a value obtained by dividing the parity length Μ/360 by the number of rows P (= 360) of the unit of the cyclic structure. The check matrix generation unit 613 (FIG. 29) specifies the column number 0 of the first +3 6 〇 x (il) row of the check matrix 藉 by checking the matrix initial value table. Further, the check matrix The generating unit 613 (FIG. 29) obtains the column number Hw_j of the element of the w-th row of the row other than the ΐ+36〇χ(Μ) row of the inspection matrix 按照 according to the equation (10), and generates a borrowed The element of the column number obtained above is regarded as the inspection matrix 1 of 1. However, DVB-C.2, which is a specification for the next-generation CATV digital broadcast, is estimated to have a high coding rate of, for example, 2/3 to 9/10, and a modulation method such as i〇24QAM or 4096QAM. In the modulation mode or signal point modulation mode, the communication channel 13 (Fig. 7) generally reduces the fault tolerance of the error, so it should be applied to improve the fault tolerance. As a countermeasure for improving fault tolerance for errors, for example, there is a replacement process performed by the demultiplexer 25 (Fig. 8). In the replacement process, as an alternative to replacing the code bit of the LDPC code, for example, the above-described first to fourth alternatives are provided, but the proposed method for the error tolerance is more than the proposed method including the second to fourth alternatives. The way to improve. Therefore, in the demultiplexer 25 (Fig. 8), as illustrated in Fig. 25, the replacement processing can be performed in accordance with the division rule of 133671.doc 200947881. Hereinafter, the replacement processing according to the allocation rule will be described, and the replacement processing by the alternative method (hereinafter also referred to as the current method) which has been proposed will be described before. Referring to Fig. 60 and Fig. 61, the replacement processing in the case where the demultiplexer 25 assumes that the replacement processing is performed in the current manner will be described. Fig. 60 is a diagram showing an example of replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. That is, FIG. 60A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and the further modulation method is 16QAM, and the multiple b is 2, and the current mode is replaced. An example. In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the 16 signal points determined by 16QAM as one symbol. Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (Figs. 16 and 17) is stored in the horizontal direction memory >< 2 (= Mb) 8 wales of bits, remembering 64800/(4x2) bits in the wales. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 3 The code bits of 1 are read in the horizontal direction, read in units of 4×2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits 150, 1 , 132, 133, 134, 135, 136, 137 read from the 4x2 (= mb) bits of the memory 31 to the continuous 2 (= b) 133671.doc - 107 - 200947881, for example, as shown in FIG. 60A. The symbol yhyhyhyhyhyhyhyhyTi of the 4x2 (= mb) bit of the symbol is replaced by the code bits b〇 to b7 of the 4<2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y7, the code bit b! to the symbol bit y!, and the code bit b2 to the symbol bit y4, respectively. The code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y3, and the code bit b6 is assigned to the symbol bit Y6, the numerator b7 is assigned to the symbol y〇, and is replaced. Fig. 60B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits τ and a coding rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) stores 6x2 (= mb) bits in the horizontal direction. The 12 vertical lines memorize 64800/(6x2) bits in the wale direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 64800 bit code bit (1 code word) is finished, the write 133671.doc -108 - 200947881 The code bits of the memory element 31 are read in the horizontal direction, read in units of 6x2 (= mb) bits, and supplied to the replacement unit 3 2 (Figs. 16 and 17). The replacing unit 32 is a code bit G, bi, b2, b3, b4, b5, b6, b7, b8, b9, b6, b7, b7, b8, b9, bi6, which are read from the 6><2 (=11115) bits of the memory 31, Bii ', for example, as shown in Fig. 60B, the symbol bits 60'71'72^3, 丫4,75, 丫6,77, assigned to 6x2 (= mb) bits of consecutive 2 (=b) symbols.丫 8, 79, 71. In the manner of 丫11, the code bits b〇 to bn of 6><2 (=1111)) bits are replaced. That is, the replacing unit 32 respectively assigns the code bit bQ to the symbol bit yn, assigns the code bit b to the symbol bit y7, and assigns the code bit b2 to the symbol bit y3, The code bit b3 is assigned to the symbol bit y1. , the code bit b4 is assigned to the symbol bit y6, the code bit b5 is assigned to the symbol bit y2, the code bit b6 is assigned to the symbol bit y9, and the brown bit b7 is assigned to the symbol bit The element y5, Q y assigns the code bit b 8 to the symbol bit yj, the code bit b9 to the symbol bit y8, and the code bit b 1 g to the symbol bit y4, the code bit Yuan b]! Assigned to the symbol y〇, and replaced. Fig. 60C shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 256QAM, and the multiple 匕 is 2. 133671.doc -109- 200947881 In the case where the modulation mode is 256QAM, the 8 (=m) bits of the code bit are mapped to one of the 256 signal points determined by 256QAM as one symbol. Further, when the code length N is 04800 bits and the multiple 匕 is 2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains the 8x2 (-mb) bit in the horizontal direction. 16 vertical lines of the Yuan, remembering 648〇〇/(8χ2) bits in the longitudinal direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the 6 memory. The code bits of 3 1 are read in the horizontal direction, read in units of 8 χ 2 (= mb), and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the symbol bits of 8x2 (= mb) bits of consecutive 2 (= b) symbols to the code bit map 60C read from the 8x2 (= mb) unit of the memory 3丨. In other words, the code bits bG to b15 of 8x2 (= mb) bits are replaced. That is, the replacing unit 32 assigns the code bit bo to the symbol bit yi 5 , the code bit b to the symbol bit y J , and the code bit b 2 to the symbol bit y 分别 . 3. The code bit b3 is assigned to the symbol bit y3, the code bit b4 is assigned to the symbol bit y 8, the code bit b5 is assigned to the symbol bit yn, and the code bit b6 is assigned to the symbol The meta-bit y9, 133671.doc • 110· 200947881 assigns the code bit b7 to the symbol bit y5, assigns the code bit b8 to the symbol bit y! 〇, and assigns the code bit b9 to the symbol bit Element y6, assigning code bit b 1 〇 to symbol bit y 4 ' assigning code bit b π to symbol bit y 7, assigning code bit b 12 to symbol y 12 ' The code bit b 13 is assigned to the symbol bit y 2 , the code bit b ! 4 is assigned to the symbol bit y 14, and the code bit b ! 5 is assigned to the symbol bit y 〇 for replacement. Fig. 61 is a diagram showing an example of a replacement process of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. That is, FIG. 61A shows an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and a further modulation method is 16QAM, and the multiple b is 2. . In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the 16 signal points determined by 16QAM as one symbol. Further, when the code length N is 16,200 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) contains 4x2 (= mb) bits in the horizontal direction. The 8 wales store 16200/(4x2) bits in the wales. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 16200 bit code bit (1 code word) is finished, the write 133671.doc -111 - 200947881 The code bits entered in the memory 31 are read in the horizontal direction and read out in 4x2 (= mb) bit units and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is to read the code bits of 4x2 (= mb) bits from the memory 31, 1) (), 1)], 132, 133, 134, 1) 5, 1) 6, 1) 7, For example, the symbol bits yQ, yi, y2, y3, y4, y5, y6, y< which are assigned to 4x2 (= mb) bits of consecutive 2 (=1?) symbols are shown in Fig. 61. The code bits b〇 to b7 of 4x2 (= mb) bits. That is, the replacing unit 32 performs the replacement of the symbol bits bQ to t»7 to the symbol bits y〇 to y7 as in the case of the above-described Fig. 60A. Fig. 61B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code whose code length is 16200 bits and the coding rate is 3/5 3/5. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 16,200 bits and the multiple 匕 is 2, the memory 31 (FIG. 16, FIG. 17) of the demultiplexer 25 is included in the horizontal direction to hide 6x2 (-mb) bits. 12 vertical lines of the yuan, memory 162 〇〇 / (6 χ ◎ bit in the longitudinal direction. In the solution of the lithograph 25, the code bits of the LDPC code are written in the vertical direction of the memory 3, if 16200 When the writing of the symbol bit (1 code word) of the element is completed, the code bit written in the memory 31 is in the course direction, read out in units of 6x2 (= mb) bits, and supplied to the replacement unit 32. (Fig. 6, Fig. 7) The replacement unit 32 is to read the code bit 1 from the memory 31i6x2 (= mb) bit 〇 '151, 1) 2, 133, 1) 4, 1) 5 , 136, 137, 1) 8, 159, 1) 10, 1 > 11, for example, the allocation shown in Figure 616 is 1336*71.doc -112· 200947881 to 6x2 (= mb) of consecutive 2 (=b) symbols The bit elements of the bit are 乂0'乂1'乂2, 丫3,74, 丫5, 丫6,77, 丫8,79,71. In the manner of 711, replace 6<2(; = 11115) bits 兀b 〇 to b 11. That is, the replacing unit 32 performs the replacement of the code bits b〇 to bu to the symbol bits y〇 to yu in the same manner as in the case of Fig. 60B described above. 61C is a diagram showing an example of replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length of 1 φ 162 bits and a coding rate of 3/5, and a further modulation method is 256 qam, and the multiple b is 1. . In the case where the modulation mode is 256QAM, the 8 (=111) bits of the code bit are mapped to one of the 256 signal points determined by 256QAM as one symbol. Step σ, the code length N is 16,200 bits, and the multiple b is 1, the memory 3 解 of the multiplexer 25 (Fig. 16, Fig. 17) is stored in the horizontal direction memory 8xl (= mb) The 8 vertical lines of the bit 'memorize the ι62〇〇/(8χΐ) bit in the wale direction. ❹ ; 夕 工 25 25 ' LDPC code code bit is written in the longitudinal direction of the memory 3 1 If the writing of the 16200 bit code bit (j code word) is finished, it is written in the memory 31 The code bits are in the horizontal direction, are arranged in 8xi (= mb) bit units, and are supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to read the code bits of the 8-bit from the memory 31 by 'bi'b2, b3, b4, b5, b6, b7, for example, as shown in Fig. 61 (: assigned to 々) The symbol of the 8x1 (= mb) bit of the symbol y <), yi, y2, y3, y4, y5, y6, y7 'replaces the 8Xl (= mb) bit of the code bit b to B7. That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y7, assigns the code bit b! to the symbol bit y3, and assigns the mbit b2 to the symbol bit y7, respectively, 133671.doc-113-200947881 Symbol bit y 1, assign code bit b3 to symbol bit y5, assign code bit b4 to symbol bit y2, assign code bit b5 to symbol bit y6, and code bit B6 is assigned to the symbol bit y4, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Next, the replacement processing according to the distribution rule (hereinafter also referred to as the replacement processing of the new replacement method) will be described. 62 to 64 are diagrams illustrating a new alternative. In the new alternative, the replacement unit 32 of the demultiplexer 25 replaces the code bits of the mb bits in accordance with a predetermined allocation rule. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits. The distribution rule defines: a combination of a code bit group of a code bit element and a symbol bit group of a symbol bit of a code bit element of the code bit group; that is, a group; The code bit group of the group set, and the bit number of the symbol bit group and the bit number of the symbol bit group (hereinafter also referred to as the group bit number). Here, the code bit system is as described above, and there is a difference in the error probability, and the symbol bit is also different in the error probability. The code bit group is grouped according to the error probability to distinguish the groups of code bits, and the symbol bit group is grouped according to the error probability to distinguish the group of symbol bits. 133671.doc -114- 200947881 Figure 62 shows that the LDPC code is an LDPC code with a code length n of ι 6200 bits and a coding rate of 2/3. The code is further modulated by 1〇24QAM and the multiple b is 2. Bit group and symbol bit group. In this case, the code bits 兀~ to !^9 of the 21〇x2 (= mb) bits read from the memory 31 are grouped into 5 codes according to the difference in error probability as shown in FIG. 62. Bit groups Gbl, Gb2, Gb3, Gb4, Gb5. Here, the code bit group Gbi is a group in which the subscript i is smaller, and the error probability of the code bit belonging to the code bit group Gbi is better (smaller). As shown in FIG. 62A, respectively, the code bit group 〇1)1 belongs to the code bit b0, the code bit 兀 group Gbz is the code bit bl, and the code bit group Gh is the code bit 匕!^2 belongs to, the code bit group Gw is the code bit 匕3, and the code bit group Gb 5 is the code bit bi4 to b]9. When the modulation method is 1024QAM and the multiple b is 2, the symbol bits y❶ to yi9 of the l〇x2 (=mb) bits are different according to the error probability, and can be grouped into five groups as shown in FIG. 62B. The symbol bit group l5Gy2, Gy3, Gy4, Gy5.于此 The 'single bit group Gyi is the same as the code bit group, and the subscript} is smaller as the group having the better error probability of the symbol bit of the symbol bit group Gyi. In FIG. 62B, respectively, the symbol element group Gyi is a symbol element y〇, and the yi'yi〇'yii belongs to the 'character bit group group symbol element y2, y3'y] 2' Yi3 belongs to the 'character bit group Gy:} is the symbol element y4, y5, yu, yi5 belongs to, the symbol element group Gw is the symbol element y6, y7'yi6, y" belongs, symbol The bit group Gy5 is a symbol bit 78, 丫9, 丫18, 丫19 belongs to. 133671.doc -115- 200947881 Fig. 63 shows that the LDPC code is for the code length N is 16,200 bits, and the coding rate is 2. The LDPC code of /3 further modulates the allocation rule in the case where the 々Quda and the mode are 1024QAM and the multiple b is 2. The allocation rule in Fig. 63 stipulates that the code bit το group Gb 丨 and the symbol bit The combination of the group Gys is used as a group, and the group number is set. Then, the number of group bits of the group set is defined as 1 bit. Here, the group set and its group bit are as follows. The number is also referred to as a group aggregation information. Then, for example, a group of code bits is called a group of symbol bits, such as a group set, and a chain of the group set is known as a; & B, a public σ l group bit number is 1 bit Record © is the group collection information (Gh, Gy5, 1). The distribution rule in Figure 63, in addition to the group collection information, also specifies group collection information, called, sentence, (Gb3, Gy2, 4), (Gb3, Gy3, 2), Pei (1), (% ^^), (Gb5, Gy3, 2), (Gb5, Gy4, l), (Gb5, Gy5, 3). For example, group collection information (Gb^ GhD means that the unit of the code bit belonging to the code bit group Gh is assigned to the 1-bit element of the symbol bit belonging to the symbol bit group Gy. 0 Therefore, the allocation rule in Fig. 63 The rule is as follows: According to the group set information (Gb), Gy5, l), assign the 1-bit ' of the code bit of the error probability i-th good code bit group Gb! to the error probability of the $good character One bit of the symbol bit of the meta-bit group Gy5; according to the group set information (Gb2, Gy4, l) '1 bit of the code bit of the second good code bit group Gh of the error probability , assigned to the error probability 4th, the 1st bit of the symbol bit of the good symbol bit group Gy4; 133671.doc -136- 200947881 According to the group set information (Gb3, Gyi, 4) 'The error probability 3rd good code position The 4 bits of the code bit of the group Gb3 are assigned to the 4th bit of the symbolic probability of the good symbol bit group Gyi; according to the group set information (Gb3, Gy2, 4), Assigning 4 bits of the code bit of the error probability third good code bit group G1>3 to the 4 bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; The group set information (Gb3, Gy3, 2) assigns the 2nd bit of the code bit of the error probability 3rd good code group to the Gb3 of the group Gb3 to the symbol group 3 of the error probability group Gy3 2 bits of the symbol bit; according to the group set information (Gb^Gy^l), the bit position of the code bit of the 3rd good code bit group Gt>3 of the error probability is assigned to the error probability The fourth good symbol group Gy4 symbol element bit; according to the group set information (Gb^Gy-1), the error probability fourth good code bit group Gin code position The element of the element is assigned to the 1st bit of the symbol bit of the 4th good symbol group Gy4 of the error probability; ◎ according to the group set information (Gbs, Gy3, 2), the error probability is 5th Good 2 bits of the code bit of the code bit group Gh, allocated to the 2nd bit of the symbol bit of the 3rd good symbol bit group Gy of the error probability; According to the group set information (Gb^Gy ^l), assigning the 码 bit of the code bit of the 5th good code bit group Gh of the error probability to the 丨 bit of the symbol bit of the 4th good symbol bit group Gw of the error probability And according to the group set information (Gb5, Gy5, 3), assign the 3 bits of the code bit of the 5th good code bit group Gh of the error probability to the error probability of the $th good symbol bit group Group 3 of the symbol of Gy5. 133671.doc -117· 200947881 As described above, the code bit group is grouped according to the error probability to group the code bit groups, and the symbol bit group is grouped according to the error probability to group the symbol bit groups. group. Therefore, the allocation rule can also be said to combine the error probability of the specified code bit with the error probability of the symbol bit to which the code bit is assigned. Thus, the allocation rule that specifies the combination of the error probability of the code bit element and the error probability of assigning the symbol bit of the code bit element is determined by, for example, the simulation of the BER, to improve the fault tolerance for the error (for the noise Fault tolerance). In addition, even if the allocation of the code bits of a certain code bit group is changed in the bit of the same symbol bit group, (almost) does not affect the error for the error © wrong. Therefore, in order to improve the fault tolerance for errors, the group set information of the BER (Bit Error Rate) is specified, that is, the code bit group of the specified code bit group and the code bit group are allocated. The combination of the symbol group of the symbol bit of the code bit (group set), the code bit group of the group set, and the code bit and the symbol bit of the symbol bit group respectively The number of bits (the number of group bits) of the element is used as an allocation rule, and according to the allocation rule, the code bit is allocated to the symbol bit to replace the code bit. ® Among them, according to the allocation rule, the specific allocation method of which code bits are assigned to which symbols must be determined before the transmitting device 11 and the receiving device 12 (Fig. 7). Figure 64 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 63. That is, FIG. 64A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and a further modulation method is 1024QAM, and a multiple b is 2, and the code according to the allocation rule of FIG. 63 is used. The replacement of the bit 1 133671.doc -118- 200947881 example.

The LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 2/3. In the case where the modulation mode is 1024QAM and the multiple b is 2, in the solution state 25, the x direction in the wale direction The code bits written in the memory 31 whose direction is (Ι62〇〇/(1〇χ2))χ (10x2) bits are in the course direction, read out in units of 10 2 (mb) bits, and supplied to Replacement unit 32 (Fig. 16, Fig. 17).

The replacement unit 32 assigns the code bits ^ to bi9 ' from the (four) (four) t H) x 2 (= mb) bits according to the allocation rule of FIG. 63, for example, the picture "A" is assigned to consecutive 2 (= b) characters. Yuan 丨 ο. mb) bit element bit % to , replace l 〇 x 2 (= mb) bit code bit b. to b19. That is, the replacement part 32 is the code bit bQ Assigned to the symbol bit y8, the code bit b is assigned to the symbol y6, the code bit b2 is assigned to the symbol yo, and the code bit b3 is assigned to the symbol yJ, the code Bit b4 is assigned to symbol bit y2, code bit b5 is assigned to symbol bit y3, code bit b6 is assigned to symbol bit y4, and code bit b7 is assigned to symbol bit y5. The code bit b8 is assigned to the symbol bit y7, the mom bit b9 is assigned to the symbol bit y 1 〇, the code bit bi 〇 is assigned to the symbol bit y, J, and the code bit bu is allocated. The symbol bit 丫 12, 133671.doc -119- 200947881 assigns the code bit b 1 2 to the symbol bit y 1 3 , and assigns the code bit b ! 3 to the symbol bit y ! 6 The code bit b14 is assigned to the symbol bit yi4, and the code bit b! 5 is assigned to the symbol bit y 1 5 Assigning code bit b! 6 to symbol bit y 9, assigning code bit b! 7 to symbol bit yi 8, assigning code bit b ! 8 to symbol bit y! 9, will The code bit b! 9 is assigned to the symbol bit y! 7, and is replaced. Fig. 64B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the modulation method is further 1024QAM, the second example of the replacement of the code bits according to the allocation rule of Fig. 63 in the case where the multiple b is 2. If the replacement unit 32 is in accordance with the allocation rule of Fig. 63, it is directed to the memory 3 1 according to Fig. 64B. The coded bits b〇 to b] 9 of the read 10 X 2 (= mb) bits are respectively replaced by the following: The meta-bit b 〇 is assigned to the symbol y 18, and the code bit b! Assigned to the symbol bit y6, the code bit b2 is assigned to the symbol bit y, the code bit b3 is assigned to the symbol y 11, and the code bit b4 is assigned to the symbol y2, The code bit b5 is assigned to the symbol bit y 12, the code bit b6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y5, and the code bit b 8 is assigned to the symbol bit Yuan y 7, 133671.doc -120- 200947881 assigning the code bit bg The symbol bit y丨〇' assigns the code bit b 1 q to the symbol bit yi ' assigns the code bit b 1 ! to the symbol bit y3 , and assigns the code bit b 12 to the symbol bit y 13 'Assign the code bit b 13 to the symbol bit yi 6 ' Assign the code bit bi4 to the symbol bit yi9, and assign the code bit b 1 5 to the symbol bit yi 5, the code bit The element b 16 is assigned to the symbol bit y9, the code bit b 1 7 is assigned to the symbol bit y8, the code bit b 1 8 is assigned to the symbol bit y 丨 4, and the code bit bi9 is assigned. Give the symbol bit y17. Here, the code bit bi shown in Figs. 64A and 64B is assigned to the symbol bit yi in accordance with the allocation rule of Fig. 63 (according to the allocation rule). 65 is a diagram showing an LDPC code in which an LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method is 1〇24QAM, and a multiple of b is a code bit group and a symbol. Bit group. In this case, the code bits bQ to b!9 of the l〇x2 (= mb) bits read from the memory 31 are grouped into 5 according to the difference in error probability as shown in FIG. 65 A_. One code bit group GbuGbhGbhGb^Gbs. In FIG. 65A, respectively, the code bit group (the code bit element, the belonging, the code bit group Gh code bit h belongs to, the code bit group Gb3 is the bit bit to! ^ 2 belongs, the code bit group & Gb4 code bit, 3 belongs, the code bit group Gb5 is the code bit b 14 to b 19. The modulation mode is 1024QAM, and the multiple b is 2, 1 〇x2(=mb) 133671.doc *121 - 200947881 The symbol of the bit 丫. To 719 is based on the difference in error probability, as shown in Figure 65B, the group can be divided into 5 symbol group Gyi , Gy2, Gy3, Gy4, Gy5. In Fig. 65B, as in Fig. 62B, respectively, the symbol bit group Gyi is a symbol 7(), 7^1(), 711 belongs to the 'character bit The meta-group (5 is the symbol element y2, y3, yi2, yi3 belongs to the 'character bit group Gy3 system symbol element y4, y5, yi4, yls belongs to the 'character bit group Gy4 character The meta-bits y6, y7, yi6, yi7 belong to, and the symbol-based bit group Gy5 is represented by y8, y9, yi8, yi9. Figure 66 shows that the LDPC code is code length 1^ is 64800 bits, coding The rate is 2/3❹ LDPC code, and the further modulation method is 1〇24QAM, multiple 1) The allocation rule in the case of 2. The allocation rule in Fig. 66 specifies group information (gn gwJ), (Gb2, Gy5, l), (Gb3, Gy丨, 4), (Gb3, Gy2, 3). , (Gb3, Gy3, 4), (Gb4, Gy4, l), (Gb5, Gy2, l), (Gb5, Gy4, 3), (Gb5, Gy5, 2). That is, the distribution rule in Fig. 66 The rules are as follows: According to the group set information (Gb, Gy5, 1), the 1st bit of the code bit of the first good code bit group Gb of the error probability is assigned to the error probability 5th good. 1 bit of the symbol bit of Gys symbol group; according to the group set information (Gb2, Gy5, l) 'The error probability 2nd good code bit group Gbz of the code bit 1 The bit element is assigned to the bit element of the symbol bit of the error probability $th good bit group Gys; according to the group set information (Gb^Gyi/), the error probability is the third good code bit The 4 bits of the code bit of the group Gb3 are allocated to the 4th bit of the symbol bit of the Gyi symbol group with the wrong probability probability; 133671.doc •122· 200947881 According to the group collection information (Gb3 , Gy2, 3), will be the probability of error 3 The 3 bits of the code bit of the good code bit group Gb3 are allocated to the 3 bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information (Gb3, Gy3, 4), assigning 4 bits of the code bit of the 3rd good code bit group Gb3 of the error probability to the 4th bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability According to the group set information (Gb4, Gy4, l), the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is assigned to the error probability 4th good ® good character bit 1 bit of the symbol bit of the meta group Gy4; according to the group set information (Gb5, Gy2, l), the 1st bit of the code bit of the coded bit group Gb5 of the 5th good error probability is allocated Give the 1st bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information (Gb5, Gy4, 3), the error probability 5th good code bit group Gb5 The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and according to the group set information (Gb5, Gy5, 2), the error will be Probability 5th The code bits of the code bit group Gb5 ❿ 2 of bits, the error probability is allocated to good fifth symbol bit group Gy5 symbol bits of the element 2 of bits. Figure 6 7 shows an alternative to the code bits in accordance with the allocation rules of Figure 66. That is, FIG. 67A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and further modulation is 1024QAM, and the multiple b is 2, according to the allocation rule of FIG. 66. The first example of the replacement of the code bit.

The LDPC code is an LDPC 133671.doc -123 - 200947881 code with a code length N of 64800 bits and a coding rate of 2/3. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is used. The memory bit written in the memory 31 of the (64800/(10χ2)) χ (1〇χ2) bit in the wale direction X direction is in the course direction, and is l〇x2 (= mb) bits. The unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits 13() to 1319 read from the 1 (^2 (=1111)) bits of the memory 3 according to the allocation rule of FIG. 66, for example, as shown in FIG. 67. (=b) The symbol yQ to yi9 of the l〇x2 (= mb) bit of the symbol is replaced by the imaginary 匕〇 x2 (= mb) bit 匕〇 匕〇 to b19. That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y8, assigns the code bit b 1 to the symbol bit y9, and assigns the code bit b2 to the symbol bit y, respectively. The code bit b3 is assigned to the symbol bit yi, the code bit b4 is assigned to the symbol bit y2, the code bit b 5 is assigned to the symbol bit y 3 , and the code bit b6 is assigned to the symbol bit Element y4, assigning code bit b7 to symbol bit y5, assigning code bit b8 to symbol bit y 1 〇, and assigning code bit b9 to symbol bit y 11, placing code bit b ! 〇 assigned to the symbol bit y 12, the code bit b!! is assigned to the symbol yi4, the code bit b! 2 is assigned to the symbol y 1 5 , and the code bit b! 3 Assigned to the symbol element y 6, 133671.doc -124· 200947881 assigns the megabyte b! 4 to the symbol y7, and assigns the code bit b! 5 to the symbol y! 3, the code Bit b ϊ 6 is assigned to symbol bit y 18, code bit bi 7 is assigned to symbol bit y 1 9, and code bit bi 8 is assigned to symbol bit y 16, and code bit b is 19 is assigned to the symbol element yi 7, and is replaced. 67B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 〇2/3, and further modulation is 1024QAM, and the multiple b is 2, and the code position according to the allocation rule of FIG. 66 is used. The second example of the replacement of Yuan. According to FIG. 67B, the replacing unit 32 performs the following replacement for the code bits b〇 to b19 of the 1 〇x2 (= mb) bits read from the memory 3 in accordance with the allocation rule of FIG. 66: The code bit bG is assigned to the symbol bit y 19 , the code bit b! is assigned to the symbol bit ys», the code bit b2 is assigned to the symbol bit y 15, and the code bit b3 is assigned to The symbol bit y 1, the code bit b4 is assigned to the symbol bit ys, the code bit b5 is assigned to the symbol bit y3, the code bit b6 is assigned to the symbol bit y4, and the code bit is assigned B7 is assigned to the symbol bit y2, the code bit b8 is assigned to the symbol bit yi2, the code bit b9 is assigned to the symbol bit y 11, and the code bit bi 〇 is assigned to the symbol bit y 〇, 133671.doc -125- 200947881 assigning the tilde b π to the symbol y14, assigning the code bit bi2 to the symbol y〇', assigning the code bit b]3 to the symbol Element y6, assigning code bit b! 4 to symbol bit y 7, assigning code bit b 1 5 to symbol bit y 1 3 ' assigning bit bit bi6 to symbol bit yi8 ' The code bit b 7 is assigned to the symbol bit y 8, and the code bit b! 8 points To the symbol bit y 6 Shu, Ma bits allocated to bi9 symbol bit y! 7. ^ Fig. 68 shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 1024QAM, and the code bit group and the symbol in the case of the multiple ^^ Bit group. In this case, the code bits of the l〇x2 (= mb) bits read from the memory 31 are different from the error probability, and can be grouped into 4 codes as shown in FIG. 68A. The bit group 〇1)1,01)2,01»3, 〇1. In Fig. 68A', respectively, the code bit group Gb! belongs to the code bit %, the code bit group Gt> 2 is the code bit ratio to the ^^3, and the code bit group Gt> The code © bit bw belongs to, and the code bit group Gh is the code bit to bl9. When the modulation method is 1024QAM and the multiple b is 2, the symbol bits 7() to >^9 of the i〇x2(=mb) bit are based on the difference in error probability, as shown in Fig. 68B. The group is divided into five symbol element groups Gyi, Gy2, Gy3, Gy4, Gy5. 68B, as in FIG. 62B, respectively, the symbol bit group Gyi is represented by the position 7LyG, y丨, y1G, yn belongs to, and the symbol bit group ^ is the symbol bit y2'y3 , y! 2, yi3 belongs to, symbolic element group Gy3 system symbol element 133671.doc • 126- 200947881 y4, ys, yi4, yi5 belongs to, symbolic element group Gy* system symbol element y6 , y7, yi6, yi7 belong to the 'character bit group Gys system symbol bit>%乂9,718,:719 belongs. Fig. 69 is a diagram showing an allocation rule in the case where the LDPC code is an LDPC code whose code length N is 16,200 bits and the coding rate is 3/4, and the modulation mode is 1024QAM and the multiple b is 2. In the distribution rule of Figure 69, there is a group set information (Gb2, Gyl52) '(Gb2, Gy2, 4) ' (Gb2, Gy3, 2) > (Gb2, Gy4, 2) s ® (Gb2, Gy5, 3) > (Gb3, Gyi, l) ' (Gb4, Gyi, l) ^ (Gb4, Gy3, 2) > (Gb4, Gy4, 2). That is, the allocation rule in FIG. 69 is defined as follows: According to the group set information (Gb^Gy^l), the 1-bit of the code bit of the code bit group Gb i of the first good error probability is allocated. Give the 1st bit of the symbol bit of the symbol 5th good symbol group Gy5 of the error probability; according to the group set information (Gb2, Gy), 2), the 2nd good q-mabit group of the error probability The 2 bits of the code bit of the group Gb2 are allocated to the 2 bits of the symbol bit of the first good symbol bit group Gy of the error probability; according to the group set information (Gb2, Gy2, 4), The 4th bit ' of the code bit of the second good stone horse bit group Gb>2 of the error probability is assigned to the 4 bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; According to the group set information (Gb2, Gy3, 2), the 2 bits of the code bit of the second good code bit group Gt > 2 of the error probability are assigned to the third good symbol bit group of the error probability. Group 2 of the symbolic bits of Gy3; according to the group set information (Gb2, Gy4, 2), the error probability is the second best 133671.doc -127-200947881 code bit group Gb2 code bit 2-bit, The second bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability is assigned; according to the group set information (Gb2, Gy5, 3), the error probability second good code bit group Gb2 The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; according to the group set information (Gb3, Gyi, l), the error probability The 1st bit of the code bit of the 3rd good code bit group Gb3 is allocated to the 1st bit of the symbol bit of the first good symbol bit group Gy! of the error probability; (Gb4, Gy, l), assigning the 1st bit of the code bit of the 4th good result code bit group Gb4 of the error probability to the symbol of the first good symbol bit group Gy! 1 bit of the meta-bit; according to the group set information (Gb4, Gy3, 2), the 2 bits of the code bit of the 4th good code bit group Gb4 of the error probability are assigned to the third error probability. 2 bits of the symbol bit of the symbol group Gy3; and according to the group set information (Gb4, Gy4, 2), the code bit of the 4th good code bit group Gb4 of the error probability 2 bits, divided The distribution error probability is 4 〇 The 2 symbol of the symbol element of the good symbol group Gy4. Figure 70 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 69. That is, FIG. 70A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 1024QAM, and the multiple b is 2, according to the allocation rule of FIG. 69. The first example of the replacement of the code bit. The LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 3/4. In the case where the modulation mode is 1024QAM and the multiple b is 2, in 133671.doc -128-200947881, the solution is 25 In the longitudinal direction, the direction of the horizontal direction is (162 〇〇 / (1 〇χ 2)) χ (10x2) bits of the § 体 体 3 1 written code position in the course direction, i 〇 x 2 ( The =mb) bit unit is read and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads the l〇x2〇=mb) bit from the memory 31 in accordance with the allocation rule of Fig. 69. The code bits ^ to bl9, for example, as shown in Fig. 7A, are assigned to the symbolic bits % to ^ of the i〇x2 (= mb) bits of consecutive 2 (= b) symbols, to replace 10x2 (= Mb) The bit position of the bit element b◦ to bl9. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit 匕 to the symbol bit y 〇, and assigns the code bit to the symbol yi yi, The bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit, the code bit 1 > 5 is assigned to the symbol bit y4, and the code bit t»6 is assigned to the symbol The meta-bit y5 assigns the code bit b7 to the symbol bit y6, the code bit bS to the symbol bit y?, and the code bit h to the symbol bit y9, and the code bit b 1 〇 is assigned to the symbol element y ] 2, the mother bit bii is assigned to the symbol element yi3, the code bit element bu is assigned to the symbol element yi8, and the medit bit b]3 is assigned to the symbol bit Yuan yi9, assigning code bit bH to symbol bit yio, 133671.doc -129- 200947881 assigning code bit b 1 5 to symbol bit y 1 6 , assigning code bit b16 to symbol bit The element yi4 assigns the code bit b17 to the symbol bit yn, assigns the code bit b 8 to the symbol bit y 15, and assigns the code bit b19 to the symbol yu, and replaces it. 70B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and further modulation is 1024QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 69 is used. The second example of replacement. According to FIG. 70B, the replacing unit 32 performs the following replacement for the 10 x 2 (= mb) bits of the 10 x 2 (= mb) bits from the memory 3 1 in accordance with the allocation rule of FIG. 69. : assigning the m-bit bG to the symbol bit ys>, assigning the code bit b! to the symbol bit y 1 〇, and assigning the code bit b2 to the symbol bit y 1, the code bit b3 Assigned to symbol bit y 13, assign code bit b4 to symbol bit y3, assign code bit b5 to symbol bit y4, assign code bit b6 to symbol bit y8, code The bit b7 is assigned to the symbol bit y 17, the code bit b8 is assigned to the symbol bit y7, the code bit b9 is assigned to the symbol bit y5, and the code bit b! 〇 is assigned to the symbol bit Element y 12, assigning the code bit b!! to the symbol bit y 2, 133671.doc -130- 200947881 assigning the code bit b 1 2 to the symbol bit y! 8, the code bit b 1 3 is assigned to the symbol bit y! 9, the code bit b 14 is assigned to the symbol bit y, the code bit b] is assigned to the symbol bit y 丨 6, and the code bit b! 6 Assigned to the symbol bit y丨4, the code bit b 17 is assigned to the symbol bit y6, and the code bit b 18 is divided To the symbol bit y 5 Shu, the code bit b 19 to the symbol bit y Shushu. 71 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 2. Group. In this case, the code bits b 〇 to b 19 of the 1 〇 x 2 (= mb) bits read from the memory 3 1 are group-divided into groups according to the difference in the probability of mismatch, as shown in FIG. 71 a. 4 code bit groups GbnGbzfbhGtu. In FIG. 71A, respectively, the 'code bit group Gbi code bit % belongs to, the code bit group Gh is the code bit ratio to belong to, the code bit group Gb3 is the code bit 匕 to !^4 belongs to The code bit group Gw is associated with the code bits bi5 to bi9. When the modulation method is 1024QAM and the multiple b is 2, the pay unit of the i〇X2 (= mb) bit ^^ to 丫^ is based on the difference in error probability, and can be grouped into 5 as shown in the figure. The symbol element group (^1, (^2, (^3, (^4, (^5. in Figure 71B, is the same as Figure 62B, respectively, the symbol element group Gyi system 兀Bit 丫(), 71 belongs to 1(), 711 belongs to, symbol element group (3" symbol element 疋 y2, y3'yi2, yi3 belongs to, symbol element group Gy3 system symbol bit Y4, y5, yi4, y〗 5 belongs to, the symbol element group Gy4 is a symbol element 133671.doc -131- 200947881 Y6, y7, yi6, yi7 belongs to the 'character bit group Gys symbolic element Figure 72 shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 3/4. The further modulation method is i〇24QAM, and the multiple b is 2. The allocation rule below. The distribution rule in Figure 72 specifies group information, (Gb2, Gy4, l), (Gb3, Gy!, 4), (Gb3, Gy2, 4), (Gb3, Gy3, 4) ), (Gb3, Gy4, l), (Gb4, Gy4, 2), (Gb4, Gy5, 3).

That is, the allocation rule in FIG. 72 is defined as follows: According to the group set information (Gb^Gy5, !), the unit of the code bit of the code bit group Gh with the error probability j is assigned to Error probability: $1 of the symbolic group of Gy5 of the good symbol group; 'The second best of the error probability' is assigned to the first probability of the fourth probability of error probability; According to the group collection information (Gb2 , Gy4, 1) code bit group Gb2 code bit 1 bit good symbol bit group Gy* symbol bit

According to the group set information (Gb3, Gyi, 4), the 4th bit of the code bit of the error probability 3rd good 3 code bit group Gb3 is assigned to the error probability 2 good symbol bit group Gyi 4 bits of the symbol bit; according to the group set information (Gb3, Gy2, 4), the 4th bit of the code bit of the error probability W good 3 code bit group Gb3 is assigned to the error profile / The good symbol is the 4th bit of the symbol group of Gya; the information (10)* Maer group., and the 4 bits of the code bit of Gb3 are assigned to the good symbol group Gy3. The 4th bit of the symbol bit; the third leg of the sheep 133671.doc -132- 200947881 According to the group set information (Gb3, Gy4, l), the error probability is the 3rd good code bit group Gb3 code 1 bit of the bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb4, Gy4, 2), the error probability is 4th 2 bits of the code bit of the good code bit group Gb4, allocated to the 2 bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and according to the group set information (Gb4 , Gy5, 3), will be the fourth probability of error Code bits of the code bit group Gb4 of three yuan, assigned to an error probability of 5 © symbol bit of the symbol bits of good Gy5 group of three yuan. Figure 73 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 72. That is, FIG. 73A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and the further modulation method is 1024QAM, and the multiple b is 2, according to the allocation rule of FIG. 72. The first example of the replacement of the code bit. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 3/4. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is decoded in the W direction. The code bits written in the memory 31 of the column direction (64800/(10χ2)) χ (1〇χ2) bits are in the course direction, read out in l〇x2 (= mb) bit units, and supplied To the replacement unit 32 (Figs. 16 and 17), the replacement unit 32 reads the code bits 13 from the 10><2 (=1111) bits of the memory 3 1 in accordance with the allocation rule of Fig. 72. Up to 1319, for example, as shown in Fig. 73, the symbol bits y〇 to y19 assigned to consecutive 2 (=b) symbols 10 < 2 (= mb) bits are replaced by 1 〇 x 2 ( =mb) The bitwise of the bit to b19. 133671.doc -133- 200947881 That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y8, assigns the code bit b! to the symbol bit y6, and assigns the code bit b2 to the symbol The bit position y〇, the code bit b3 is assigned to the symbol bit y!, the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit y3, and the code bit is B6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y 1 〇, The code bit b! 〇 is assigned to the symbol bit y 11, the code bit b η is assigned to the symbol bit y 12 , the code bit b b 2 is assigned to the symbol bit y 1 3 , and the code is assigned The bit bi 3 is assigned to the symbol bit y μ , the code bit b b 4 is assigned to the symbol bit y 1 5 , the code bit b ! 5 is assigned to the symbol bit y 9 , and the code bit is assigned b ! 6 is assigned to the symbol bit y 1 6 , the code bit b b 7 is assigned to the symbol bit y 1 7 , the code bit b 8 is assigned to the symbol bit yi 8 , and the code bit is assigned b ! 9 is assigned to the symbol y 1 9 and replaced. 73B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and the further modulation method is 1024QAM, and the multiple b is 2, 133,671.doc • 134-200947881. The second example of the replacement of the code bits of the distribution rule. According to Fig. 73B, the replacing unit 32 is directed to the code bit 15 of the bit read from the suffix 31 in accordance with the allocation rule of Fig. 72. To 1) 19, the following substitutions are respectively made: the code bit b〇 is assigned to the symbol bit 719, the code bit b is assigned to the symbol bit y6, and the code bit b2 is assigned to the symbol bit. Y〇, the code bit bs is assigned to the symbol bit yi2, 码 the code bit t>4 is assigned to the symbol bit y2, and the code bit t>5 is assigned to the symbol bit & The bit h is assigned to the symbol bit y4, the code bit t>7 is assigned to the symbol bit yi 5, the code bit bS is assigned to the symbol bit y?, and the code bit 1>9 is assigned to The symbol bit yi 〇, the code bit b ! Q is assigned to the symbol yi yi 1, the megabyte h is assigned to the symbol y!, ◎ the code bit bu is assigned to the symbol bit 713, the code bit b13 is assigned to the symbol bit y14, the code bit b14 is assigned to the symbol bit y5, and the code bit b! 5 is assigned to the symbol bit y9, and the code bit b! Assigned to the symbol bit" 8, assigns the code bit b! 7 to the symbol yi ya 7, assigns the code bit bi 8 to the symbol yi yi 6, assigns the code bit b19 to the symbol bit Yuan y8. 133671.doc -135- 200947881 Figure 74 shows that the LDPC code is code length >^ is 162〇 〇 bit, LDPC code with a coding rate of 4/5, the code bit group and the symbol bit group in the case where the step b is 1024QAM, and the multiple b is 2. In this case, the memory is from the memory. 31 reads 21 〇 x 2 (= mb) bits of the code bits 至 ^ to, 9 based on the difference in error probability, as shown in Figure 74A can be grouped into 3 code bit groups Gb ^ GbhGh. 74A, respectively, the code bit group 〇 131 is a code bit, belongs to the hopper, the code bit group Gh> 2 code bit bl5 belongs to, and the code bit group is a code bit b! 6 to b 1 9 belongs to β ◎ modulation mode is 1024QAM, and when multiple b is 2, the symbol bits yQ to yi9 of l〇x2 (= mb) bits are based on the difference in error probability, as shown in Fig. 74B. The non-group can be divided into 5 symbol bit groups (}71, (372, (^3, (374, (;^5. In Figure 74B, the same as Figure 62B, respectively, the symbol bit group The group character 7L bit 丫^^丫^ with the "affiliated 'bit element group ^" is the symbol element y2, y3, yi2, yu belongs to the 'character bit group Gy3 system symbol bit y4 , y5, yM, y! 5 belongs to, the symbol element group Gy4 is a symbol element y6, y7, yi6 , y" belongs to, the symbol element group Gy5 is a symbol element 〇丫8, 丫9, 丫18, 丫19 belongs. Figure 75 shows that the LDPC code is code length N is 16,200 bits, and the coding rate is 4. /5 LDPC code 'further modulation mode is 1〇24qAM, multiple b*2 in the case of allocation rules. The distribution rule 'in Figure 75' specifies group group information (Gbi, Gyi, 4), (Gb!, Gy2, 3) ' (Gbl5Gy3, l) ' (Gbi, Gy4, 3) ' (Gbi, Gy5, 4 ) ' (Gb2, Gy3, l), (Gb3, Gy2, l), (Gb3, Gy3, 2), (Gb3, Gy4, l). 133671.doc , 136- 200947881 That is to say, the distribution rules in Figure 75 are as follows: According to the group collection information (Gb^Gy!〆)', the error probability is the first good stone horse group Gb! The 4-bit of the bit is assigned to the 4-bit symbol of the symbol element Gy of the error probability third-order group; according to the group set information (Gbl5Gy2, 3), the error probability is the first good The 3 bits of the code bit of the Gem group Gbl are assigned to the 3rd bit of the symbol bit of the 2nd good symbol bit group Gy2; according to the group set information (Gbi'Gy ^l), assigning the 1st bit of the code bit of the error probability i-th goodness of the mother bit group Gth to the 1st bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability According to the group collection information (Gbl5Gy4, 3), the 3rd digit of the code bit of the error probability i-th good mother bit group Gb is assigned to the error probability 4th good symbol group Gy4's 3-bit symbol; according to the group set information (Gb, Gy5, 4) 'The 4th bit of the code bit of the wrong probability i-good stone horse group Gh 'Assigned to the 4th bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; © . According to the group set information (Gb2, Gy3, l), the error probability is 2nd good code position 1 bit of the code bit of the meta-group Gbz, assigned to the 1-bit of the symbol bit of the symbol 3 of the symbol group Gy3 of the error probability; according to the group collection information (Gt»3, Gy2, l), the first bit of the code bit of the third good symbol bit group Gh of the error probability is assigned to the one bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; According to the group set information (Gb3, Gy3, 2), the 2 bits of the code bit of the 3rd good code bit group G1 > 3 of the error probability are assigned to the error probability 3rd 133671.doc -137- 200947881 2 bits of the symbol element of Gy3 of the good symbol group; and the code position of the code group Gb3 of the 3rd good error probability according to the group set information (Gb3, Gy4, l) The 1st bit of the element is assigned to the 1st bit of the symbol bit of the symbolic group of the fourth bit of the error probability group Gy4. Figure 76 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 75. That is, FIG. 76A shows that the LDPC code is a DPC code having a code length N of 16,200 bits and a coding rate of 4/5, and further modulation is 1024QAM, and the multiple b is 2, according to the distribution rule of FIG. 75. The first example of the replacement of the code bits. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bit written in the memory 31 of the direction (162〇0/(1〇χ2))χ(1〇χ2) bit is in the course direction, and is read in l〇x2 (=mb) bit units. And supplied to the replacement unit 32 (FIG. 16, FIG. 17). The replacing unit 32 allocates the code bit b from the l〇x2 (= mb) bit of the memory 3 to the bi9 according to the allocation rule of FIG. 75, for example, as shown in FIG. 76A to the continuous 2 (=b). The symbol symbol y〇 to yi9 of the 〇x2 (= mb) bit of each symbol is replaced by the code bit 1)() to b19 of the l〇x2 (= mb) bit. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y, respectively, the code bit b 1 to the symbol bit y!, and the code bit b2 to the symbol bit y2. The code bit b3 is assigned to the symbol bit y3, 200947881 assigns the code bit b4 to the symbol bit y4, the code bit b5 is assigned to the symbol bit y6, and _ assigns the code bit b6 to the symbol The bit element, the code bit b7 is assigned to the symbol bit y8, the code bit b8 is assigned to the symbol bit y9, the m-bit b9 is assigned to the symbol bit y], and the code bit bi 〇 Assigned to the symbol bit y! 1, the code bit b]! Assigned to the symbol y! 2,

The code bit b! 2 is assigned to the symbol bit y 1 6 , the code bit b 3 is assigned to the symbol bit y 8 , and the code bit b ! 4 is assigned to the symbol y ] 9 , the code bit bi 5 is assigned to the symbol bit y5, the code bit b! 6 is assigned to the symbol bit y 1 4 , and the code bit b! 7 is assigned to the symbol bit y 1 7 The code bit b! 8 is assigned to the symbol bit y 15, and the code bit b! 9 is assigned to the symbol bit y 13, and replaced. 76B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and further modulation is 1024QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 75 is used. The second example of replacement. According to FIG. 76B, the replacing unit 32 performs the following replacement for the code bits bG to b! 9 of the 10x2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 75: The code bit bG is assigned to the symbol bit y!2, 133671.doc -139- 200947881, the code bit b1 is assigned to the symbol bit yi, and the code bit b2 is assigned to the symbol bit y 19, The code bit b3 is assigned to the symbol bit y3, the code bit t>4 is assigned to the symbol bit y4, the code bit b5 is assigned to the symbol bit y9, and the mate b6 is assigned to the symbol The bit y7 assigns the code bit b7 to the symbol bit y8, the code bit b8 to the symbol bit y6, and the code bit b9 to the symbol bit y 1 〇, the code bit b 1 〇 assigned to symbol yi yi 6, assign code bit b 1 ! to symbol y 〇 , assign code bit b ! 2 to symbol y 11 , assign code bit b 13 To the symbol bit y 18, the code bit bi 4 is assigned to the symbol bit y 2 , the code bit b b 5 is assigned to the symbol bit y5 , and the code bit b b 6 is assigned to the symbol bit Element y 1 7, assign code bit b ! 7 to symbol bit y 1 4, and code bit b 8 The symmetry bit y! 5 assigns the code bit b ! 9 to the symbol y 1 3 . 77 is a diagram showing that an LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code bits bQ to b19 of the l〇x2 (= mb) bits read from the memory 31 are based on the difference in error probability, as shown in Fig. 77A, the group area 133671.doc -140- 200947881 is divided into 3 code bit groups Gb^Gb^Gbs. In Fig. 77A, respectively, the code bit group Gb is the code bit b〇 and ..., the code bit group Gba is the code bit 匕 to !^5, and the code bit group Gb3 is the numerator The elements b16 to b19 belong. When the modulation method is 1024QAM 'when the multiple b is 2, the symbol yG to yi9 of the i〇X2 (= mb) bit is based on the difference of the error probability, as shown in Fig. 77B, the group cannot be divided into 5 characters. The meta-bit group MG^, G is, G^, Gy4, Gy5. In Fig. 77B, as in Fig. 62B, respectively, the symbol bit group Gyi is 7L bits yo'y^y. ,% belongs to, the symbol element group Gy2 is the symbol element 疋 y2, y3, y 〗 2, yn belongs to the 'character bit group Gy3 line symbol element belongs to the 'character bit group Gy4 character The meta-bit y^y^y^'yw belongs to the 'character-bit group Gy5-like symbol s, y9, yi8, yi9 belongs. Fig. 78 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method of 1 〇 24QAM, a multiple bg2. The distribution rule in Fig. 78 specifies group information (GbhGyd), (Gb2, Gyi, 4), (Gb2, Gy2, 4), (Gb2, Gy3, 3), (Gb2, Gy4, 3), ( Gb3, Gy3, l), (Gb3, Gy5, 3). That is, the allocation rule in FIG. 78 is defined as follows: According to the group set information (Gbl5Gy4, l), the 1-bit of the code bit of the error probability bit i-th good code bit group Gb! is assigned to the error. The probability of the *good symbol group G y4 symbolic bit 1 bit; according to the group collection information (Gb^Gy5,;!), the error probability is the first good 133671.doc • 141 - 200947881 code bit group Gb, one bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; according to the group set information (Gb2, Gyi, 4), assigning 4 bits of the code bit of the second good code bit group Gb2 of the error probability to the symbol bit of the first good symbol bit group Gy! Bits; according to the group set information (Gb2, Gy2, 4), the 4th bit of the code bit of the second good code bit group Gb2 of the error probability is assigned to the second good symbol bit of the error probability. 4 bits of the symbol bit of the group Gy2; according to the group set information (Gb2, Gy3, 3), the 3 bit of the code bit of the code bit group Gb2 of the second good error probability is divided into three bits. Give the 3rd bit of the symbol element of the symbol 3 of the error probability group Gy3 of the error probability; according to the group set information (Gb2, Gy4, 3), the code bit group Gb2 with the second good error probability The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb3, Gy3, l), the error probability 1 bit of the code bit of the third good code bit group Gb3, assigned to 1 bit of the symbol bit of the symbol 3 of the symbol group Gy3 with the wrong probability; and information according to the group set (Gb3, Gy5, 3), assigning the 3 bits of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol bit of the 5th good symbol bit group Gy5 of the error probability 3 bits. Figure 79 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 78. That is, FIG. 79A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5. Further modulation is 1024QAM, and the multiple b is 2, according to the allocation rule of FIG. The replacement of the code bit is 133671.doc -142- 200947881 1 case. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the walrier. The code bits written in the memory 31 of the direction (64800/(10χ2)) χ (1〇χ2) bits are in the course direction, read out in l〇x2 (= mb) bit units, and supplied to Replacement unit 32 (Fig. 16, Fig. 17).

The replacing unit 32 assigns the code bits b to 10 from the 1 0 X2 (= mb) bits of the memory 3 1 according to the allocation rule of FIG. 78, for example, as shown in FIG. 79 A to the continuous 2 (= b) Symbols 10 of the symbol < 2 (= mb) bits y 〇 yi yi9 to replace the code bits b 〇 to bi 9 of 10 x 2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit b! to the symbol bit y 6, and assigns the code bit b2 to the symbol bit y, respectively. The code bit b3 is assigned to the symbol bit y 1, the code bit b4 is assigned to the symbol bit y2, the code bit b 5 is assigned to the symbol bit y 3 , and the code bit b6 is assigned to the symbol The meta-bit y4 assigns the code bit b7 to the symbol bit y5, the code bit b 8 to the symbol bit y 7, and the code bit b9 to the symbol bit y 1 〇, the code Bit b! 〇 is assigned to symbol y! 1, and megabyte b!! is assigned to symbol y! 2, 133671.doc -143- 200947881 assigning code bit bi 2 to symbol Element y 13, assigning code bit b 13 to symbol bit y 14, assigning code bit bi 4 to symbol bit y 1 6, assigning code bit b! 5 to symbol bit y 17 , the code bit b! 6 is assigned to the symbol bit y 9, the code bit b! 7 is assigned to the symbol bit y 15, and the code bit b! 8 is assigned to the symbol bit y 1 8. The code bit b ! 9 is assigned to the symbol bit y 1 9 and replaced. 79B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and further modulation is 1024QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 78 is used. The second example of replacement. According to FIG. 79B, the replacing unit 32 performs the following replacement for the code bits bG to bi 9 ' of the 10 x 2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 78: The code bit bG is assigned to the symbol bit y 19, the code bit b] is assigned to the symbol bit y 6, the code bit b2 is assigned to the symbol bit y 17, and the code bit b3 is assigned to the symbol The meta-bit y5 assigns the code bit b4 to the symbol bit y2, the code bit b5 to the symbol bit y3, and the code bit b6 to the symbol bit y11, the code bit The element b7 is assigned to the symbol bit y 1, and the code bit b8 is assigned to the symbol bit y 13, 133671.doc -144- 200947881. The code bit b9 is assigned to the symbol bit yi4, and the code bit 151 is used. () is assigned to the symbol bit y4, the code bit b 11 is assigned to the symbol bit y 丨 2, the code bit b 12 is assigned to the symbol y7, and the code bit b ] 3 is assigned to the symbol Meta-bit yi. , the code bit b 14 is assigned to the symbol bit y 16, the code bit b 15 is assigned to the symbol bit y 〇, the code bit b 16 is assigned to the symbol y9, and the code bit b is 1 7 is assigned to the symbol bit yi 5, the code bit big is assigned to the symbol bit y18, and the code bit b 19 is assigned to the symbol bit y8. 80 is a diagram showing that the LDPC code is a code bit length of 16,200 bits, and an LDPC code having a code rate of 5/6 is further modulated by 1〇24QAM, and a multiple of b is 2. Meta-bit group. In this case, the code position 兀bolbb of the l〇x2 (= mb) bit read from the memory 31 is grouped into 4 code bits according to the difference in error probability as shown in FIG. 8A. Groups Gbl5Gb2, Gb3, Gb4. 80A' respectively, the code bit group Gb1 belongs to the code bit %, the code bit group Gb2 is the code bit element to ^^5 belongs to, the code bit group Gb3 is the code bit 7Gb!6 Affiliation, code bit group code bit, 7 to b〗 9 belongs. When the modulation mode is 1024QAM and the multiple b is 2, the symbolic % to y!9 of the l〇X2 (=mb) bit is based on the difference in error probability, as shown in Figure 80B, the group cannot be grouped as (10) The symbolic meta-groups are as if they are ashamed. 80B' is the same as FIG. 62B, respectively, the symbol bit group (3yi 133671.doc • 145-200947881 system symbol bit 丫0, 丫1, 71., 丫11 belongs, symbol element Group 〇 72 is a symbol element y2, y3, y! 2, yi3 belongs to, symbol element group Gy3 is a symbol element y4, y5, y] 4, y 〗 5 belongs to the 'character bit group The group Gy4 is a symbol element y6, y7, yi6, y" belongs to, the symbol element group Gy5 is a symbol element 丫8, >^9, 丫18, 719 belongs. Figure 81 shows that the LDPC code is code length. An allocation rule in the case where N is 16200 bits and the LDPC code having a coding rate of 5/6 is further modulated by 1〇24QAM and the multiple b is 2.

The distribution rule in Figure 81 specifies group aggregation information, Q (Gb2, Gyls4), (Gb2, Gy2, 3), (Gb2, Gy3, 2), (Gb2, Gy4, 4), (〇b2, Gy5). , 2), (Gb3, Gy5, l), (Gb4, Gy2, l), (Gb4, Gy3, 2). That is, the allocation rule in Figure 81 is as follows: According to the group collection information (Gb^Gy^l), the error probability is the first! A good code position is 1 bit of the code bit of the group Gth, and is assigned to the 1st bit of the symbol bit of the symbol 5th good symbol group Gys; according to the group collection information (Gb2, Gyi, 4), assigning the 2nd good code bit of the error probability to the 4th bit of the code bit of the group Gh, and assigning it to the error probability ι 良 ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ ❹ 4 bits; according to the group set information (Gb2, Gy2, 3), assign the 3 bits of the code bit of the second good code bit group Gb2 of the error probability to the second good symbol of the error probability 3 bits of the symbol group of the meta group Gyz; according to the group set information (Gb2, Gy3, 2), the 2nd bit of the code bit of the second good code bit π group Gb2 of the error probability is allocated Give the error probability the 3rd good symbol group Gy3 of the symbol bit 2; yi 133671.doc •146- 200947881 According to the group collection information (Gb2, Gy4, 4), the error probability is 2 4 bits of the code bit of the good code bit group Gb2, assigned to the 4 bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; According to the group set information (Gb2 Gy5, 2), assigning the 2 bits of the code bit of the second good symbol bit group Gb2 of the error probability to the 2 bits of the symbol bit of the 5th good symbol bit group Gy5 of the error probability According to the group set information (Gb3, Gy5, l), the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the error probability 5th good® good sign bit 1 bit of the symbol bit of the meta group Gy5; according to the group set information (Gb4, Gy2, l), the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is allocated Giving a 1-bit element of the symbol bit of the second-perfect symbol bit group Gy2 of the error probability; and, according to the group set information (Gb4, Gy3, 2), the fourth-best code group of the error probability The 2 bits of the code bit of Gb4 are allocated to the 2 bits of the symbol bit of the symbolic group of the third symbol of the error probability Gy3. Figure 82 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 81. That is, FIG. 82A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and further modulation is 1024QAM, and the multiple b is 2, and the allocation according to FIG. The first example of the replacement of the ruled code bits. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The memory bit written in the memory 31 of the direction (16200/(10χ2)) χ (1〇χ2) bits is in the horizontal direction, with 133671.doc -147- 200947881 l〇x2(=mb) bits The unit is read and supplied to the 铥1 芏 replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits from the memory block l=x2 (= mb) bits to the pad 9, according to the allocation rule of FIG. 81, for example, as shown in FIG. 82A to consecutive 2 (=b) The symbol bits yQ to yi9 of the l〇x2 (=mb) bits of the symbol are replaced by the code bits b (^b19) of the 10x2 (= mb) bits. That is, the replacement unit 32 respectively sets the code bit b 〇 is assigned to the symbol bit y8, the megabyte b 1 is assigned to the symbol y 〇, the code bit b 2 is assigned to the symbol yj, and the modulo b3 is assigned to the symbol y2 , assigning the mbit b4 to the symbol y3, assigning the code bit b5 to the symbol y4, assigning the code bit b6 to the symbol y5, and assigning the code bit b7 to the symbol bit Element y6, assign code bit b 8 to symbol bit y7, assign code bit b9 to symbol bit y9, assign code bit b! 〇 to symbol bit y! 〇, place code bit The element b! i is assigned to the symbol bit yti, the code bit b] 2 is assigned to the symbol bit y! 2, the code bit b i 3 is assigned to the symbol bit y 丨 6, and the code bit is B14 is assigned to the symbol bit 丫17, the code bit b15 is assigned to the symbol 丫18, and the code bit b is allocated The symbol bit y 19, 133671.doc -148- 200947881 assigns the code bit b ! 7 to the symbol bit y 1 4 , assigns the code bit b ! 8 to the symbol bit y 15, and sets the code bit The element b 1 9 is assigned to the symbol bit y 1 3 and is replaced. Fig. 82B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and the modulation mode is 1024QAM. In the case where the multiple b is 2, the second example of the replacement of the code bits according to the allocation rule of Fig. 81. According to Fig. 82B, the replacement unit 32 is directed to the memory from the memory 3 according to the allocation rule of Fig. 81. The code bits 13〇 to b19 of the read 1 〇x2 (= mb) bits are respectively replaced by: assigning the code bit bG to the symbol bit y 18, and assigning the code bit b! The symbol bit y〇, the code bit b2 is assigned to the symbol bit y 12, the code bit b3 is assigned to the symbol bit y2, and the code bit t>4 is assigned to the symbol bit y3, The code bit b5 is assigned to the symbol bit y 15, 码 the code bit b6 is assigned to the symbol bit y9, the code bit b7 is assigned to the symbol bit y6, and the code bit b 8 is assigned to the symbol Bit y 7, assigning code bit b9 to the sign bit Y5, assigning the code bit b 1 〇 to the symbol bit yi 〇, assigning the code bit bu to the symbol bit y 11, and assigning the code bit b! 2 to the symbol bit y 1, the code Bit b! 3 is assigned to symbol bit y! 6, 133671.doc -149- 200947881 assigning code bit b 14 to symbol bit y 17 ' assigning code bit b 15 to symbol bit y 8. The code bit b16 is assigned to the symbol bit yi9, the code bit b 17 is assigned to the symbol bit y 14 '. The code bit b 18 is assigned to the symbol bit y4, and the code bit b 19 Assigned to the symbol y 13 . 83 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 2. Meta group. 10 In this case, 'the code bits 1 to 1319 of the l〇x2 (= mb) bits read from the memory 31 are based on the difference in error probability, and can be grouped into five groups as shown in FIG. 83a. The code bit group 〇 1) 1, 〇 1) 2, 0153, 0134, 01) 5. In Fig. 83 A 'respectively, 'the code bit group Gb! is the code bit %%, the code bit group Gh is the code bit element ^^ belongs to, the code bit group 〇 153 is the code bit element to !^5 belongs to, code bit group ο, system code bit...6 belongs to, code bit group Gh>5 series code bit! ^7 to b19 belong. When the modulation method is 1024QAM and the multiple b is 2, 1〇x2(=mb) © the symbol yG to y of the 兀9 is based on the difference in error probability, as shown in Figure 83b. Call up for 5 groups of symbols. 83B is the same as FIG. 62B, respectively, the symbol element group ~ the system element bit yG, y!, yi Q, yi 1 belongs to, the symbol element group symbol 兀 y2, Y3, yi2, y] belongs to 3, the symbol meta-group Gy3 is a symbol element y^y^yM'y, 5 belongs to, the symbol-bit group is skillful 4 system symbol element belongs to, the symbol element The meta group 〇y5 is a symbol element 133671.doc -150- 200947881 78, 丫9,3^18, 丫19 belongs. Fig. 84 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and a further modulation method is i 〇 24QAM, and the multiple b is 2. The allocation rule in Fig. 84 specifies group information (Gb2, Gy4, l), (GbhGyM), (Gb3, Gy2, 4), (Gb3, Gy3, 4), (Gb3, Gy4, 2), ( Gb4, Gy4, l), (Gb5, Gy5, 3). That is, the allocation rule in Fig. 84 is defined as follows: According to the group set information (Gb!, Gy5, 1) '1 bit of the code bit of the first good code bit group G b 1 of the error probability 'Assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; According to the group set sfL(Gb2, Gy4, l) 'The error probability is 2nd good code bit Group 1b of the code bit G2; 2 is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb3, Gyi, 4 ] '4 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are assigned to 4 bits of the symbol bit of the error probability jth good symbol bit group Gy! According to the group set information (Gb:}, Gy2, 4) 'Assign the 4th bit of the code bit of the 3rd good code bit group Gb of the error probability to the error probability 2^ the good sign bit 4 bits of the symbol bit of the meta group Gy2; according to the group set information (Gb3, Gy3, 4), the 4th bit of the code bit of the 3rd good code bit group Gba of the error probability is allocated Give the probability of error 3 The 4th bit of the symbol element of the good symbol group Gy3; according to the group set information (Gb3, Gy4, 2), the error probability is the third best 133671.doc -151 - 200947881 code bit group The 2 bits of the code bit of the group Gb3 are allocated to the 2 bits of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb4, Gy4, l), 1 bit of the code bit of the 4th good code bit group Gb4, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; The set information (Gb5, Gy5, 3) assigns the 3 bits of the code bit of the 5th good code bit group Gb5 of the error probability to the symbol of the 5th good symbol bit group Gy5 of the error probability. 3 bits of the bit. Figure 85 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 84. That is, Fig. 85A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and further modulation is 1024QAM, and the multiple b is 2, according to the distribution rule of FIG. The first example of the replacement of the code bits. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bit written in the direction of (64800/(10χ2)) χ ◎ (1〇χ2) bit memory 31 is in the course direction, read in V 1 0x2 (= mb) bit units, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bit b to read from the 1 0 X2 (= mb) bit of the memory 3 1 to b! 9, according to the allocation rule of FIG. 84, for example, as shown in FIG. (=b) 10 of the symbol < 2 (= mb) bits of the symbol bits yG to yi9 to replace the code bits b〇 to bi9 of the l〇x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b丨 to the symbol bit y6, and assigns the code bit b2 to the symbol bit y8, respectively, 133671.doc - 152 - 200947881 The symbol bit y〇, the code bit b3 is assigned to the symbol bit y 1, the code bit b4 is assigned to the symbol bit y2, and the code bit b 5 is assigned to the symbol bit y 3, The code bit b6 is assigned to the symbol bit y4, and the code bit b7 is assigned to the symbol bit y5.

The code bit b8 is assigned to the symbol bit y7, the code bit b9 is assigned to the symbol bit y 1 〇, and the code bit b! 〇 is assigned to the symbol bit y 11, and the code bit b! ! is assigned to the symbol bit y 12, the code bit b 12 is assigned to the symbol bit yi 3 , the code bit b ! 3 is assigned to the symbol bit y 1 4 , and the code bit bi 4 is assigned to Symbol bit y 1 5, assign code bit b ! 5 to symbol bit y 1 6, assign code bit b! 6 to symbol bit y! 7, assign code bit b! 7 To the symbol bit y9, the code bit b 8 is assigned to the symbol bit y 1 8, and the code bit b 19 is assigned to the symbol bit yi9 for replacement. 85B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and a further modulation method is 1024QAM, and a multiple of b is 2, and the code bit according to the allocation rule of FIG. 84 is used. The second example of replacement. 133671.doc -153- 200947881 According to FIG. 85B, the replacing unit 32 is in accordance with the allocation rule of FIG. 84 for the code bits b〇 to b! 9 of the 10×2 (= mb) bits read from the memory 31. The following replacement is performed respectively: the code bit b〇 is assigned to the symbol bit y 18, the code bit b! is assigned to the symbol bit y 16, and the code bit b2 is assigned to the symbol bit y〇 , the code bit b3 is assigned to the symbol bit y 1, the code bit b4 is assigned to the symbol bit y 14, the code bit b5 is assigned to the symbol bit y5, and the code bit b6 is assigned to the symbol The bit y4, the code bit b7 is assigned to the symbol y3, the code bit b8 is assigned to the symbol y15, and the code bit b9 is assigned to the symplec y1 〇, the code bit is The element b! is assigned to the symbol bit y 12, the code bit b!! is assigned to the symbol bit y 11, the code bit b! 2 is assigned to the symbol bit y 1 3, and the code bit is b! 3 is assigned to the symbol bit y2, the code bit b! 4 is assigned to the symbol bit y 7, the code bit b! 5 is assigned to the symbol bit y6, and the code bit b! 6 is assigned Assigning the bit element bi 7 to the symbol bit y 9, assigning the code bit b! 8 Symbol bit y 8, the code bit b! 9 assigned to the symbol bit y 1 9. 86 is a diagram showing an LDPC code which is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9 133671.doc -154 to 200947881, and a further modulation method of 1024QAM and a multiple of b. Group and symbol bit groups. In this case, the code bits 1 > 〇 to bu of the l〇x2 (= mb) bits read from the memory 31 are grouped into 5 codes according to the difference in error probability as shown in Fig. 86A. The bit group GbhGbhGbhGb^Gbs. In Fig. 86A, respectively, the code bit group 〇|31 code bit b〇 and the 'code bit group Gb> 2 code bit t>2 belong to the 'code bit group Gb3' The code bit 匕 to 卜 6 belongs to, the code bit group Gh is the code bit b17, and the code bit о group Gbs is the code bits b18 and b19. When the modulation mode is 1024QAM and the multiple b is 2, the i〇x2 (= mb) bit is a few bits 7 () to 丫 19 based on the difference in error probability, as shown in Figure 86B. It is a group of 5 symbol bits Gyi, Gy2, Gy3, Gy4, Gy5. 86B, the same as FIG. 62B, respectively, the symbol bit group symbol 疋 bit 7 (), : 171 (), : ^1 belongs to, the symbol bit group (372 system symbol) The bit belongs to, the symbol element group 〇 y3 is the symbol element ❹ y4 'y5, y»4, yi5 belongs to, the symbol element group Gy4 is the symbol element y^y^ywy " belongs to the symbol The bit group Gy5 is represented by the symbol bits y8, y9, yi8, yi9. Figure 87 shows the LDPC code S code length Ny62 〇〇 bit, LDPC code with a coding rate of 8/9, further modulation mode is 1 〇24qam, the allocation rule in the case of multiple μ 2. In the allocation rule of Figure 87, 栩~ now has group collection information (GbhGysJ), (Gb2, Gy3, l), (Gb3, Gy) 41 _ ') , (Gb3, Gy2, 4), (Gb3, Gy3, 3), (Gb3, Gy4, 3), (Gb heart, i), (Gb5, Gy5, 2). 133671.doc ' 155 - 200947881 ie ' The allocation rule in Fig. 87 is defined as follows: According to the group set information (Gbl, Gy5, 2), the 2 bits of the code bit of the error probability i-th good code bit group Gb are assigned to the error probability. 2 bits of the symbolic element of the symbolic group Gys; The aggregate information (Gb^GhD, the unit of the code bit of the error probability second good code bit group Gb2 is assigned to the error probability 3 = the symbol bit of the good symbol bit group Gys丨位; 义 According to the group set information (Gb3, Gyi, 4), the 4th bit of the code bit of the 3rd good code bit group Gh of the error probability is assigned to the error probability ^丨^10 The 4-bit element of the symbol element group Gy!; the meaning of the group probability information (Gb3, Gy2, 4), the error probability of the third good code bit group Gb3 of the code bit 4 bit, assigned to the error probability '^ 2^ The 4th bit of the symbol bit of Gyz of the symbol group Gyz; according to the group set information (Gb3, Gy3, 3), the error probability is 3rd a good code bit 3 3 bits of the code bit of the group Gh, assigned to the 3 bit of the symbol bit of the 3rd good symbol bit group Gys of the error probability; according to the group set information (Gb3, Gy4,3) 'Assign the error probability to the 3 bit of the code bit of the 3rd good weight bit group Gb3 of the error probability; 4Funity bit of the good symbol bit group Gy* 3-bit; according to group The group set information (Gb4, Gy4, 1}, assigns the i-bit of the code bit of the 4th good code bit group Gb4 of the error probability to the error: the 4th good symbol bit group Gy* The unit of the symbol bit; and according to the group set information (Gb5, Gy5, 2), assign the error probability to the error probability of the code bit of the code bit group Gb5 of the good bit group Gb5 ^ $ 133671.doc -156- 200947881 The 2nd bit of the symbolic element of the good symbolic group Gy5. Figure 88 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 87. That is, FIG. 88A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and the modulation method is 1024QAM, and the multiple b is 2, according to the allocation rule of FIG. 87. The first example of the replacement of the code bits. The LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 8/9. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is decomposed in the longitudinal direction and the horizontal direction is X. The code bits written in the memory 31 of the column direction (16200/(10χ2)) χ (1〇χ2) bits are in the course direction, read out in l〇x2 (= mb) bit units, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to 10, which are read from the memory of the memory 31, to b! 9, according to the allocation rule of FIG. 87, for example, as shown in FIG. (=b) The symbol y of the 〇x2 (= mb) bit of the symbol 1x2 (= mb). To y19, replace i with x1 x2 (= mb) bits of code bits 1) () to b19. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit b! to the symbol bit y9, and assigns the code bit b2 to the symbol bit y4, The bit b3 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to the symbol bit Y3, 133671.doc -157- 200947881 assign code bit b7 to symbol bit y5, assign code bit b8 to symbol bit y6, assign code bit b9 to symbol bit y7, put code The bit b丨〇 is assigned to the symbol bit y 1 〇, the code bit b!丨 is assigned to the symbol bit y 11, and the code bit b! 2 is assigned to the symbol bit y 1 2, Bits b! 3 are assigned to symbol bits y 1 3, code bits b ! 4 are assigned to symbol bits y 1 4 , and code bits bi 5 are assigned to symbol bits y 15, and code bits are assigned The element bi 6 is assigned to the symbol bit y 16, the code bit b! 7 is assigned to the symbol bit yi 7, the code bit b 8 is assigned to the symbol bit y 1 8 , and the code bit b is ! 9 is assigned to the symbol y 1 9 and replaced. 88B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and further modulation is 1024QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 87 is used. The second example of replacement. According to FIG. 88B, the replacing unit 32 performs the following replacement for the code bits bG to b19' of the 10×2 (=mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 87: The code bit bG is assigned to the symbol bit y 18, the code bit b is assigned to the symbol bit y9, the code bit b2 is assigned to the symbol bit y4, and the code bit b3 is assigned to the symbol bit The element y 11, 133671.doc -158- 200947881 assigns the code bit b4 to the symbol bit y 1, assigns the code bit b5 to the symbol bit y2, and assigns the code bit b6 to the symbol bit y 14. The code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y6, the code bit b9 is assigned to the symbol bit y7, and the code bit b! The symbol bit yi 〇, the code bit element bii is assigned to the symbol bit y 〇,

◎ assigning the code bit b! 2 to the symbol bit y 16, assigning the code bit b! 3 to the symbol bit y 1 3, and assigning the m-bit b! 4 to the symbol bit y3, The code bit b ! 5 is assigned to the symbol bit y 1 5 , the code bit bi 6 is assigned to the symbol bit y 12 , and the code bit b ! 7 is assigned to the symbol bit y 17, the code bit is The element b丨8 is assigned to the symbol bit y 8, and the code bit b! 9 is assigned to the symbol bit y 1 9 . 89 is a diagram showing that an LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 8/9, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code bits b〇 to b19 of the 1 0><2 (= mb) bits read from the memory 3 1 are group-divided into groups according to the difference in error probability as shown in FIG. 89A. 5 code bit groups 01^, 052, 0133, 0匕4, 0135. In FIG. 89A, respectively, the code bit group 01^ is a code bit b〇 and 1^ belongs to, the code bit group Gb2 is a code bit b2, and the code bit group Gb3 is code 133671.doc -159- 200947881 Bits are transferred to ^6, the code bit group Gb4 is the code bit bi7, and the code bit group Gbs is the code bits 1^8 and b19. When the modulation mode is 1024QAM and the multiple 5 is 2, the symbol bits 7〇 to 丫19 of the 1〇x2 (=mb) bit are different according to the error probability, and can be grouped as shown in FIG. 89b. 5 symbolic group Gyi, Gy2, Gy3, Gy4, Gy5. In Fig. 89B, as in Fig. 62B, respectively, the symbol bit group character το bit 丫〇, >^, 丫1(), 丫11 belongs to, the symbol bit group 〇72 character The 元 y y y ya y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y y Yn belongs to, the symbol element group Gy5 is a symbol element 丫 8, 79, 718, 丫 19 belongs. Fig. 90 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and a further modulation method of 1 〇 24QAM, and a multiple of 1) is 2. In the distribution rule of FIG. 90, group aggregation information (Gbi, Gy5, 2), (Gb2, Gy4, l), (Gb3, Gyi, 4), (Gb3, Gy2, 4), (Gb3, Gy3, 4), (Gb3'Gy4, l), (Gb3, Gy5, l), (Gb4, Gy4, l), (Gb5, Gy4, l), ® (Gb5, Gy5, l) 〇, ie, Figure 90 The allocation rule is as follows: According to the group set information (Gbi, Gys, 2), the 2 bits of the code bit of the first good code bit group Gb of the error probability are assigned to the fifth error probability. 2 bits of the symbol bit of the symbol group Gy5; according to the group set information (Gb2, Gy4, l), the error probability 2nd good mother bit group Gb2 of the code bit 1 Bit, assigned to the error probability of the fourth good 133671.doc -160- 200947881 good symbolic bit group Gy# symbolic bit position; according to the group collection information (Gb3, Gyi, 4), Assigning 4 bits of the code bit of the 3rd good code bit group Gbs of the error probability to the 4th bit of the symbolic element of the error probability 'good symbol bit group Gy! Group collection information (Gb3, Gy2, 4), error probability 3rd good code The 4 bits of the code bit of the meta-group Gb3 are assigned to the error probability = 4 bits of the symbol bit of the good symbol bit group Gys; according to the group set information (Gb3, Gy3, 4), Assigning 4 bits of the code bit of the 3rd good code bit group Gh of the error probability to the 4 bit of the symbol bit of the error probability ^^good symbol bit group Gys; The set information (GbhGy^l) assigns the first bit of the code bit of the error probability third group of code bits to the symbol bit of the group Gh, and assigns the symbol bit of the fourth bit symbol group Gy4 with the wrong probability. The first bit of the code bit of the group Gh of the error probability is assigned to the symbol of the error probability ^ according to the group set information (Gb3, Gys, l) The unit of the symbol bit of the bit group Gy5; according to the group set information (Gb4, Gy4, l), the code of the fourth probability of the error probability is the bit of the code bit of the group Gh, Assigned to the 1-bit of the symbol bit of the fourth-best symbol group Gy4 of the error probability; according to the group set information (Gb5, Gy4, 1}, the error probability is 5th good code position το The unit of the code bit of the group Gbs is allocated to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and according to the group set information (Gb5, Gy5, 1}, The unit of the code bit of the 5th good code bit group Gb5 of the error probability is assigned to the error probability $ 133671.doc -161 - 200947881 The symbol bit of the good symbol bit group Gy5 1 bit. Figure 91 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 90. That is, FIG. 91A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and the further modulation method is 1024QAM, and the multiple b is 2, according to the distribution rule of FIG. The first example of the replacement of the code bits. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 8/9. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bit written in the direction of (64800/(10χ2)) χ © (1〇χ2) bit memory 31 is in the horizontal direction, read in l〇x2 (= mb) bit units, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to b19 read from the 1 〇 x 2 (= mb) bits of the memory 3 1 according to the allocation rule of FIG. 90, for example, as shown in FIG. 91A for consecutive 2 (=b). The symbol bits yG to yi9 of the l〇x2 (= mb) bits of the symbol are replaced by the code bits 1?() to 1319 of the l〇x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit to the symbol bit y8, the code bit b! to the symbol bit y 9, and the code bit b2 to the symbol y6. The code bit b3 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, the code bit b 5 is assigned to the symbol bit y 2 , and the code bit b6 is assigned to The symbol bit y3, 133671.doc -162- 200947881 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit y5, and the code bit b9 to the symbol bit Y7, assigning the code bit 131() to the symbol bit force, assigning the code bit b 1 1 to the symbol bit y丨1, and assigning the code bit b12 to the symbol bit 丫12, The code bit b13 is assigned to the symbol bit y13, the code bit b14 is assigned to the symbol bit y14, the code bit b 1 5 is assigned to the symbol bit y J 5 , and the code bit b16 is assigned to the symbol Meta-bit 718, assigning code bit b ! 7 to symbol bit yt 6, assigning code bit b 8 to symbol bit y 1 7 , assigning code bit b 1 9 to symbol bit Yuan y丨9, and replace it. 91B is a diagram showing that the LDPC code has a code length N of 64,800 bits, a coding rate of q 8/9 tLDPC^, a further modulation method of 1024QAM, and a multiple b of 2 in accordance with the allocation rule of FIG. Replace the second case. According to FIG. 91B, the replacement unit μ performs the following replacement for the code bits b〇 to 吣 of the u〇x2 (= mb) bits read from the memory according to the allocation rule of FIG. 9B: The code bit b〇 is assigned to the symbol bit yi9, the code bit b! is assigned to the symbol bit y9, the code bit t>2 is assigned to the symbol bit y7, and the code bit I)3 is assigned. For the symbol bit 丫丨丨, 133671.doc -163- 200947881 assign the code bit b4 to the symbol bit y 1, assign the code bit bs to the symbol bit y2, and assign the code bit b 6 For the symbol bit y 3 , the code bit b 7 is assigned to the symbol bit yi 2 , the code bit b 8 is assigned to the symbol bit y 5 , and the code bit bg is assigned to the symbol bit y6 , the code bit biQ is assigned to the symbol bit y13, the code bit b 11 is assigned to the symbol bit y , the code bit b 12 is assigned to the symbol bit y4 , and the code bit b 13 is allocated The symbol bit yi 5 is assigned to the symbol bit bi4 to the symbol bit yi4, the code bit b 15 is assigned to the symbol bit y 丨 0, and the mash bit b 16 is assigned to the symbol y y丨8, assign the code bit b] 7 to the symbol y! 6, and the code bit b!8 Dispensing symbol bit y17, the code bit b 19 to the symbol bit y8. Figure 92 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coded rate of 9/10, and a further modulation method is 1〇24QAM, and the multiples b is 2, and the code bit group and the symbol are Meta-bit group. In this case, the code bits of the 1 〇x2 (= mb) bits read from the memory 3 1 and the !^9 are grouped into three according to the difference in error probability as shown in FIG. 92A. Code bit group. In Fig. 92A, 'the code bit group 〇\ system code bit % and 1^ respectively belong to, the code bit group Gb2 belongs to the code bit b2 to b17, and the code bit group Gb3 133671.doc • 164. 200947881 belongs to code bits b18 and bi9. When the modulation mode is 1024QAM and the multiple b is 2, the symbolic bits 丫() to 719 of the 'l〇x2(=mb) bits are different according to the error probability, as shown in Fig. 92B, the group can be divided into 5 symbolic group Gyi, Gy2, Gy3, Gy4, Gy5. 92B is the same as FIG. 62B, respectively, the symbol bit group Gyi is associated with the symbol bit, and the symbol bit group 〇乂 2 is the symbol bit y2, y3, y 2, yn The sub-character group Gy3 is represented by the symbol y4, y5, yM, y, and belongs to the symbolic group. The symbolic group of Gy4 is represented by y6'y7, yu, yi7, and the symbol is located. The meta-group Gy5 is a symbol element 丫8, 丫9, 丫18,719 belongs. Fig. 93 is a diagram showing an LDPC code which is an LDPC code having a code length n of 64,800 bits and an encoding rate of 9/10, and a further modulation method of 1 〇 24qA] vi and a multiple (four) 2 . In the distribution rule of Figure 93, group aggregation information (Gb^Gy%!), (Gb2, Gyi, 4), (Gb2, Gy2, 3), (Gb2, Gy3, 4), (Gb2, Gy4, 4), (Gb2, Gy5, l), (Gb3, Gy2, l), (Gb3, Gy5, l). That is, the allocation rule in FIG. 93 is defined as follows: According to the group aggregation information (GbuGysJ), the 2 bits of the code bit of the error probability bit j-good code bit group Gbi are assigned to the error probability 5th. 2 bits of the symbol element of the good symbol group Gys; according to the group collection information (Gb^Gy!〆), the code bit of the second good symbol group Gh of the error probability 4-bit, assigned to the 4-bit element of the symbol bit GY of the symbolic group with good error probability; according to the group set information (Gb2, Gy: 2, 3), the error probability is 2 Good 133671.doc -165- 200947881 The 3-bit code of the code bit group Gb2 is allocated to the 3rd bit of the symbol bit of the second good symbol group Gy2 of the error probability; The group set information (Gb2, Gy3, 4) assigns the 4 bits of the code bit of the second good code bit group Gb2 of the error probability to the symbol group 3 of the error probability group Gy3. 4 bits of the symbol bit; according to the group set information (Gb2, Gy4, 4), the 4th bit of the code bit of the 2nd good code bit group Gb2 of the error probability is assigned to the wrong The 4th bit of the symbol bit of the 4th good symbol bit group Gy4; the error probability 2nd good code bit group Gb2 according to the group set information (Gb2, Gy5, l) 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; according to the group set information (Gb3, Gy2, l), the error probability is 3: 1 bit of the code bit of the good code bit group Gb3, assigned to the 1st bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; and according to the group set information ( Gb3, Gy5, l), assigning the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol bit of the 5th good symbol bit group Gy5 of the error probability 1 bit. ® Figure 94 is an alternative representation of the code bits in accordance with the allocation rules of Figure 93. That is, FIG. 94A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and the further modulation method is 1024QAM, and the multiple b is 2, according to the distribution rule of FIG. The first example of the replacement of the code bit. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 9/10. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is solved at 133671.doc -166-200947881. The code bits written in the memory 31 of the (648〇〇/(ι〇χ2)) χ (l〇x2) bit in the wale direction x direction are in the course direction, i〇u (= The mb) bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the i〇x2 (= mb) bit from the memory 31 in accordance with the allocation rule of Fig. 93. The code bit % to b! 9, such as the symbol bit y assigned to the l〇x2 (= mb) bit of consecutive 2 (= b) symbols as shown in Fig. 94a. To h, replace the code bits of 10x2 (= mb) bits to b19. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit b! to the symbol bit y9, and assigns the code bit b2 to the symbol bit y, respectively. The code bit b3 is assigned to the symbol bit yi, the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit y3, and the code bit 1 > 6 is assigned to the symbol bit Element y4, assigning code bit b7 to symbol bit y5, assigning code bit 1)8 to symbol bit y6, and assigning bit 1)9 to symbol bit y7, the code bit b1G is assigned to the symbol bit 丫1〇, the code bit bn is assigned to the symbol bit “!”, the code bit b is assigned to the symbol y12, and the code bit b 1 3 is assigned to the symbol The meta-bit y is 4, and the stone-horse bit bw is assigned to the symbol bit 715, 133671.doc • 167- 200947881 The code bit b! 5 is assigned to the symbol bit y 16, and the code bit b! 6 is assigned to the symbol bit y 17, the code bit b! 7 is assigned to the symbol bit y] 8, the code bit b! 8 is assigned to the symbol bit y 19, and the code bit b 1 9 Assigned to the symbol bit y 1 3, and replaced. Figure 94B shows that the LDPC code has a code length N of 64,800 bits. The second example in which the coding rate is 9/10 LDPC code, the modulation method is 1024QAM, and the multiple b is 2, and the replacement of the code bits according to the allocation rule of Fig. 93. If the replacement unit 32 is used according to Fig. 94B According to the allocation rule of FIG. 93, the following replacement is performed for the code bits 1)() to b19' of the 10<2 (= mb) bits read from the memory 31: bG is assigned to symbol bit y8, code bit b! is assigned to symbol bit y9, code bit b2 is assigned to symbol bit y, and code bit b3 is assigned to symbol y 11 , the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit y3, the code bit b6 is assigned to the symbol bit y!2, and the code bit b7 is assigned to the symbol The meta-bit y5 assigns the code bit b8 to the symbol bit y 17, assigns the code bit b9 to the symbol bit y7, and assigns the code bit b! 〇 to the symbol bit y 1 〇, 133671 .doc -168- 200947881 assigns the megabyte b!! to the symbol yj, assigns the code bit b] 2 to the symbol y4, and assigns the code bit b! 3 to the symbol y ! 6, assign the code bit b ! 4 to the symbol bit y 1 5, The code bit b! 5 is assigned to the symbol bit y! 4, the code bit b! 6 is assigned to the symbol bit y6, the code bit b 17 is assigned to the symbol bit yi 9, and the code bit is The b 18 is assigned to the symbol bit y 13, and the code bit b 19 is assigned to the symbol bit y 18. Figure 95 is a diagram showing that the LDPC code is a code bit group and a symbol bit in the case where the code length N is 16,200 bits and the LDPC code having a code rate of 2/3 is further modulated by 4096QAM and the multiple b is 2. Meta group. In the case of hai, the 12 bits read from the memory 3 1 < 2 (= mb) bits of the code bits b 〇 to bn are grouped according to the difference in error probability, as shown in Fig. 95A 4 megabytes group GbhGbsAbhGtu. In Fig. 95A, respectively, the code bit group Gb!·code bit b. Affiliation, the code bit group Gbz code bit b belongs, the code bit group Gb3 code bit 匕 to ... 5 belongs to the 'code bit group Gb4 code bit bi6 to b23 belong. When the modulation method is 4096QAM 'when the multiple b is 2, the 12x2 (= mb) bits of the symbol bits 丫❹ to 丫 23 are based on the difference in error probability, as shown in Fig. 95B, the group can be divided into 6 groups. The symbol element group Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In Fig. 95B, 'respectively' symbolic unit group 〇 yi is a symbol element y〇, yi, yi2, yi3 belongs to the 'character bit group Gy2 system symbol element y2, y3, yi4, y 〗 5 belongs, the symbol element group Gy3 system symbol element 133671.doc -169- 200947881 y4, y5, yu, yi7 belongs to, the symbol element group Gy4 system symbol element y6, y7, yis, Yi9 belongs to, the symbol element group Gy5 is a symbol element y8, y9, y: ?G, y2i belongs to, the symbol element group Gy6 is a symbol element yi〇, y 丨i, y22, y23 belongs to . Fig. 96 is a diagram showing an LDPC code which is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and a further modulation method of 4096QAM and a multiple b of 2. The distribution rule in Figure 96 specifies that group aggregation information (Gbi, Gy6, 1}, (Gb2, Gy5, l) ^ (Gb3, Gyl54) > (Gb3, Gy252) ' (Gb35Gy3, 4) ' © ( Gb3, Gy4, 3), (Gb3, Gy5, l), (Gb4, Gy2, 2), (Gb4, Gy4, l), (Gb4, Gy5, 2), (Gb4, Gy6, 3). The allocation rule in FIG. 96 is defined as follows: According to the group set information (GbbGy^l), the 1st bit of the code bit of the 7th good code bit 7L group Gth of the error probability is assigned to the sixth error probability. 1 bit of the symbol bit of the symbol group Gy6; according to the group set information (Gb^Gy^l), the code bit of the second good code bit group Gb2 of the error probability is 1 Bit, assigned to the error probability of the fifth good © the good symbol bit group Gy5 symbolic bit 1 bit; according to the group set information (Gb3, Gy, 4), the error probability is 3rd good 4 bits of the code bit of the code bit group Gh, assigned to the 4th bit of the symbol bit of the first good symbol bit group Gy of the error probability; according to the group set information (Gb3, Gy2, 2), 2 bits of the code bit of the code bit group Gb3 with the third probability of error probability Yuan 'is assigned to the wrong, good two good symbol group Gy2 symbolic bit 2 yuan; Ang 艮 133671.d〇, • 170- 200947881 According to the group collection information (Gb3, Gy3, 4) And assigning 4 bits of the code bit of the 3rd good code bit group Gb3 of the error probability to the 4th bit of the symbol bit of the symbol 3 of the symbol group Gy3 of the error probability; The group set information (Gb3, Gy4, 3) assigns the 3 bits of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol of the 4th good symbol bit group Gy4 of the error probability. 3 bits of the meta-bit; according to the group set information (Gb3, Gy5, l), the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the 5th good error probability 1 之 符 位 G G G G G G G G G ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 2 bits, allocated to the 2nd bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information (Gb4, Gy4, l), the error probability is 4th good Code bit 1 bit of the code bit of the group Gb4, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb4, Gy5, 2), Assigning 2 bits of the code bit of the 4th good code bit group Gb4 of the error probability to the 2 bit of the symbol bit of the fifth good symbol bit group Gy5 of the error probability; The group set information (Gb4, Gy6, 3) assigns the 3 bits of the code bit of the 4th good code bit group Gb4 of the error probability to the symbol 6 of the error probability group Gy6 The three bits of the yuan. Figure 97 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 96. That is, FIG. 97A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the further modulation method is 4096QAM, and the multiple 133671.doc -171 - 200947881 b is 2. The first example of the replacement of the code bits according to the distribution rule of Fig. 96. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the wales. The code bit written in the memory 31 of the direction (162〇0/(12χ2)) χ (12x2) bits is in the course direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 reads the code bits 1)() from the 12><2 (=1111) bits of the memory 3 1 to 匕23 according to the allocation rule of Fig. 96, for example, as shown in Fig. 97. The symbol bits yG to y23 ' of consecutive 12 (=b) symbols of 12><2 (= mb) bits are replaced by the code bits b of 12 < 2 (= mb) bits. To b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 1 〇, the code bit b! to the symbol bit y 8, and the code bit b2 to the symbol bit, respectively. y, assigning the code bit b3 to the symbol bit y 1, assigning the code bit b4 to the symbol bit y2, assigning the code bit b 5 to the symbol bit y 3, and the code bit b6 Assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y 5 , the code bit b8 is assigned to the symbol bit y6 , and the code bit b9 is assigned to the symbol bit y7 , The code bit b! 〇 is assigned to the symbol bit y 9, 133671.doc -172- 200947881 assigns the code bit bi! to the symbol bit y 12, and assigns the code bit b! 2 to the symbol bit y 1 3, assign code bit b! 3 to symbol bit y 16, assign code bit b ! 4 to symbol bit y 1 7 , assign code bit b ! 5 to symbol bit y 1 8, assign code bit b! 6 to symbol bit y2 〇, assign code bit b! 7 to symbol bit y 14, assign code bit bi 8 to symbol y! 1,

The code bit bi 9 is assigned to the symbol bit y22, the code bit b2 is assigned to the symbol y23, the code bit b21 is assigned to the symbol y21, and the code bit b22 is assigned to the symbol The bit y 1 5 is assigned to the symbol bit y 1 9 by the code bit b23. 97B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and further modulation is 4096QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. 96 is used. The second example of replacement. According to Fig. 97B, the replacing unit 32 performs the following for the code bits b〇 to b23 of the 12><2 (= mb) bits read from the memory 31 in accordance with the allocation rule of Fig. 96; Substitute: assign code bit b 0 to symbol bit 2 2 ' assign code bit b! to symbol bit y 8, assign code bit b 2 to symbol bit 1 2, place code bit The element b 3 is assigned to the symbol bit y 1, 133671.doc -173 - 200947881, the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit 1 5 , and the code bit is assigned B6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit ys, the code bit b8 is assigned to the symbol bit y6, and the code bit b9 is assigned to the symbol bit 1 8 The megabyte b! 〇 is assigned to the symbol bit 9, the code bit b ! i is assigned to the symbol bit 1 3 , the code bit b 1 2 is assigned to the symbol bit 7, and the code bit b13 is used. Assigned to the symbol bit yi6, the code bit b 1 4 is assigned to the symbol bit 1 7 '. The code bit bi 5 is assigned to the symbol bit y 〇, and the code bit b 16 is assigned to the symbol Bit 2 0 ' assigns code bit bi 7 to symbol bit 1 4 and divides bit bit b 1 8 Assigning the bit element bi 9 to the symbol bit y 1 0, assigning the code bit b 2 〇 to the symbol bit 1 9 ' assigning the code bit b2 ! to the symbol Bit 2 1, assigning code bit b 2 2 to symbol bit 兀 3 ' assigns code bit b 2 3 to symbol bit 2 3 . Figure 98 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 2. Group. In this case, the code bits 133671.doc -174-200947881 TLbo to b23 of the 1 2 X2 (= mb) bits read from the memory 3 1 are grouped according to the error probability, as shown in FIG. 98A. It is divided into 4 code bit groups Gbi, Gb2, Gb3, Gb4. In FIG. 98A, respectively, the code bit group belongs to the code bit %%, the code bit group Gbs is the code bit b, belongs to, the code bit group Gb3 is the code bit ! to ^5 Affiliation, the code bit group Gb4 is associated with the code bits bi6 to b23. The modulation mode is 4096QAM, and the multiple b is 2, and the 12x2 (= mb) bit symbol y. To y23, according to the difference in error probability, as shown in Fig. 98B, the group can be divided into 6 symbol group (^1, (^2, (^3, (^4, (^5, (^6) In Fig. 98B, as in the case of Fig. 95B, respectively, the symbol bit group Gyi is a symbol bit 丫(), 丫^12^13 belongs to, and a symbol bit group (^2 character) The meta-bits 72, 73, 丫 14, 715 belong to each other, and the symbol-bit group 〇 is the symbol element y4, y5, yi6, yi? belongs to, the symbol-bit group Gy4 is the symbol element y6, y7, Yis, yi9 belongs to, the symbol element group Gy5 is the symbol element ys, y9, y2 〇, y2i belongs to the 'character bit group Gy6 system symbol element 丫 1 〇, 丫 11, 乂 22, 丫23 belongs to Fig. 99. The LDPC code is an LDPC code whose code length N is 64800 bits and the coding rate is 2/3, and the modulation rule is 4096QAM, and the multiple b is 2. Assignment rules, specifying group collection information (Gbi, Gy6, l), (Gb2, Gy6, l) ' (Gb3, Gy, 4) ' (Gb3, Gy2, 4) > (Gb3, Gy3, 2) > (Gb3, Gy4, 3), (Gb3, Gy5, l), (Gb4, Gy3, 2), (Gb4, Gy4, l), (Gb4, Gy5, 3), (Gb4, Gy6, 2). That is, The allocation rule of 99 is defined as follows: According to the group collection information (Gb, Gy6, l), the error probability is the first good 133671.doc -175·200947881 code bit group Gb! The element 'is assigned to the error probability of the sixth bit of the symbolic group of Gy6, which is the first bit of the error element; according to the group set information (Gb2, Gy6, 1), the error probability is the second best code. Bit 1 of the code bit of group Gb2, assigned to the 1st bit of the symbol bit of the sixth bit of the error probability Gy6; according to the group set information (Gb3, Gyi, 4) 'Assign the error probability 3rd good code bit 7L group Gb3 code bit 4 bits' to the error probability ^^好好符元元元组Gyi的符元位4位元According to the group collection information (still 3, 2, 4), the 4th bit of the code bit of the 3rd good sound code bit 7L group Gb3 of the error probability is assigned to the second good symbol of the error probability. The 4th bit of the symbol group of the meta group Gyz; and according to the group set information (Gb3, Gy3, 2), the 2 bit of the code bit of the error probability 3rd good code bit group Gb3 is allocated Give wrong Overview: Good = the first symbol bit group of symbol bits Gys 2 of bits;, according to the group set information (Gb3, Gy4,3), the third error probability

The good symbol element group Gy* is the 3 digits of the symbol bit; 乂 gives the error probability 4th good according to the group collection information, the error should be you... I. Recovery + 3rd good code bit group Phase m is less than s

According to the group aggregation information (G^GyU), the 1st bit of the code bit of the error probability 4th 133671.doc -176- 200947881 code bit group Gb4 will be assigned to the 4th good symbol of the error probability. 1 bit of the symbol bit of the bit group Gy4; according to the group set information (Gb4, Gy5, 3), the 3 bit of the code bit of the coded bit group Gb4 of the 4th good error probability, 3 bits assigned to the symbol bit of the fifth-perfect symbol group Gy5 of the error probability; and the fourth-order symbol group with the error probability according to the group set information (Gb4, Gy6, 2) The 2 bits of the code bit of the group Gb4 are allocated to the 2 bits of the symbol bit of the symbolic group of the sixth symbol of the error probability Gy6. ® Figure 100 is an alternative representation of the code bits in accordance with the allocation rules of Figure 99. That is, FIG. 100A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 4096QAM, and the multiple b is 2, according to the distribution rule of FIG. The first example of the replacement of the code bit. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is disposed in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(12χ2)) χ (12x2) bits are in the course direction, read out in units of 12x2 (= mb) bits, and supplied to the replacement unit 32 ( Figure 16, Figure 17). The replacing unit 32 reads the code bits 1)() from the 12><2 (=1111) bits of the memory 3 1 to 匕23 according to the allocation rule of FIG. 99, for example, FIG. The symbol bits yG to y23 assigned to the consecutive 2 (=b) symbols of 12 > 2 (= mb) bits are replaced with the code bits bG to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 1 〇, respectively, and assigns the code bit b! to the symbol bit y 11, respectively, 133671.doc -177- 200947881 B2 is assigned to the symbol bit y〇, the code bit b3 is assigned to the symbol bit y 1, the code bit b4 is assigned to the symbol bit y2, and the code bit b5 is assigned to the symbol bit y3, The code bit b6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y6, and the code bit b9 is assigned to the symbol bit Y7, assigning the code bit b 1 〇 to the symbol bit y 8, assigning the code bit b!! to the symbol bit yi2, and assigning the code bit b! 2 to the symbol bit yi3, the code Bits b! 3 are assigned to symbol bits y 14, code bits b! 4 are assigned to symbol bits y 1 5, and code bits b! 5 are assigned to symbol bits y 18, which are code bits The element b! 6 is assigned to the symbol bit y 9, the code bit b! 7 is assigned to the symbol bit y2 〇, and the code bit b! 8 is assigned to the symbol bit y 16, the code bit b !9 is assigned to the symbol bit y22, the code bit b2Q is assigned to the symbol bit y23, and the code bit b2! is assigned to the symbol Yuan y 17, the code bit b22 to the symbol bit assigned 1, the code bit b23 to the symbol bits allocated y 19, -178-

133671.doc 200947881 and replaced. 100B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and further modulation is 4096QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 100B, the replacing unit 32 performs the following replacement for the code bits bG to b23 of the 12x2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 99: The element bG is assigned to the symbol element y23,

The code bit b! is assigned to the symbol bit y 11, the code bit b2 is assigned to the symbol bit y8, the code bit b3 is assigned to the symbol bit y 1, and the code bit b4 is assigned to the symbol The meta-bit y2 assigns the m-bit b5 to the p-bit y3, the code-bit b6 to the symbol y4, the code-bit b7 to the symbol y5, and the code-bit b8 The symbol bit y 13, the code bit b9 is assigned to the symbol y! 8, the code bit bi 〇 is assigned to the symbol y 〇, and the code bit b! 1 is assigned to the symbol bit Element y 12, assign code bit b! 2 to symbol bit y6, assign code bit b! 3 to symbol bit y! 4, assign code bit b ! 4 to symbol bit y 1 5, assign code bit b! 5 to symbol bit y7, assign code bit bi 6 to symbol bit y9, 133671.doc -179- 200947881 assign code bit b 1 7 to symbol Bit y22' assigns code bit b! 8 to symbol bit y 16 ' assigns code bit b 19 to symbol y2 〇 ' assigns code bit b2 〇 to symbol y10, The code bit b21 is assigned to the symbol bit yi 7, the code bit b22 is assigned to the symbol bit y21, and the code bit is assigned to the symbol bit b23 y 1 9. Figure 101 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and a further modulation method is 4096QAM, and a multiple of b is 2, and a code bit group and a symbol bit are used. Meta group. In this case, the code bits b〇 to bn of the 12×2 (= mb) bits read from the memory 3 1 are grouped into 4 codes according to the difference in error probability as shown in FIG. 1 〇 1A. The bit group GbhGbhGbhGbu. In FIG. 101A, respectively, the code bit group Glh is a code bit b〇, the code bit group Gb2 is a code bit b! to b16, and the code bit group Gb3 is a code bit 1^. 7 belongs to, the code bit group Gb4 is the code bit b18 to b23. When the modulation mode is 4096QAM and the multiple b is 2, the 12x2 (= mb) 〇 bit symbol yG to y23 is based on the difference in error probability, as shown in Figure 1 〇i B can be grouped into The 6-character byte group 〇71, 〇72,0丫3, 0丫4, 0丫5, 0丫6. In FIG. 101B, as in the case of FIG. 95B, respectively, the symbol bit group 〇 71 is a symbol bit 丫 () belongs to 1, 712, 713, and the symbol bit group (^2 is a symbol bit). Yuanxiao 273, 丫14715 belongs to the symbolic element group (3 is the symbol element y4, y5, yi6, yi7 belongs to, the symbol element group Gy4 is the symbol element y6, y7, y! 8 , yi9 belongs to, the symbol element group Gy5 is a symbol element 133671.doc -180- 200947881 y8, y9, y2 〇, y2i belongs to the 'character bit group Gy6 system symbol element 丫10, 丫11 Figure 102 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 3/4, and the allocation rule is further modulated by 4096QAM and the multiple b is 2. The distribution rule in Figure 102 specifies group aggregation information (〇bl5Gy6,l), (Gb2,Gyi,3), (Gb2,Gy2,4), (Gb2,Gy3,3), (Gb2,Gy4, 2), (Gb2, Gy5, 2), (Gb2, Gy6, 2), (Gb3, Gy4, l), ^ (Gb45Gyl5l) ^ (Gb4, Gy3, l) ^ (Gb45Gy4, l) ' (Gb4, Gy5 , 2) ^ (Gb4, Gy6j 1). That is, the distribution rules in Figure 102 are as follows: According to the group collection information (Glh, Gy6, l), assigning 1 bit of the code bit of the first good code bit group Gb of the error probability to the symbol bit of the symbol 6th good symbol bit group Gy6 Bits; according to the group set information (Gb2, Gyi, 3), the 3 bits of the code bit of the 2nd good ◎ code bit group Gh of the error probability are assigned to the symbol element with the wrong probability probability 3 bits of the symbol bit of the group Gy; according to the group set information (Gb2, Gy2, 4), the code bit of the 2nd good error probability is allocated to the 4 bit of the code bit of the group Gh, Give the 4th bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information (Gb2, Gy3, 3), the error probability second good code bit group Gh The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability; according to the group set information (Gb2, Gy4, 2), the error probability 2nd good 133671.doc -181 - 200947881 2 bits of the code bit of the code bit group Gh, assigned to the 2 bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability ; according to The group set information (Gb2, Gy5, 2) assigns the 2 bits of the code bit of the second good code bit group Gb2 of the error probability to the error probability 5th good symbol bit group Gy5 2 bits of the meta-bit; according to the group set information (Gb2, Gy6, 2) 'Assign the 2nd bit of the code bit of the 2nd good code bit group Gh of the error probability to the 6th good error probability 2 bits of the symbol bit of the symbol group Gy6; according to the group collection information (Gt^Gy4,! And assigning the 丨 bit of the code bit of the third good 位 code bit group Gh of the error probability to the one bit of the symbol bit of the symbol bit group Gy4 with the wrong probability probability; According to the group set information (Gb4, Gyi, l), the 1st bit of the code bit of the 4th good code bit group GW of the error probability is assigned to the error probability ^^good symbol bit group Gy 】1 bit of the symbol bit; according to the group set information (Gb4, Gy3, l), assign the error bit of the code bit of the 4th good code bit group Gh of the error probability to the error probability The i-bit of the symbolic bit of the first good symbol group Gys; 〇 the code bit of the error-probable fourth-order code bit group Gh according to the group set information (Gb^Gki) The 1-bit element is assigned to the i-bit of the symbol bit of the fourth-perfect symbol bit group Gy# of the error probability; according to the group set information (Gb4, Gy5, 2), the error probability is 4th good. 2 bits of the code bit of the code bit group GW, allocated to the 2 bit of the symbol bit of the symbol 5th good symbol bit group Gys; and according to the group set information (Gb 4, Gy6, l), assigning the 1st bit of the code bit of the code bit group Gb4 of the error probability 4th 133671.doc -182- 200947881 to the error probability 6th good symbol bit group One bit of the symbol of Gy6. Figure 103 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 102. Also, "Figure 103 indicates that 1^? (: code is code length) ^ is 16200 bits, and the encoding rate is 3/4 LDPC code. The further modulation method is 4096QAM, and the multiple b is 2. The first example is the replacement of the code bits according to the allocation rule of Fig. 102. The LDPC code is an LDPC © code with a code length N of 16,200 bits and a coding rate of 3/4, and the modulation mode is 4096QAM and the multiple b is 2. In the case of the multiplexer 25, the code bits written in the memory 31 of the (16200/(12χ2)) χ (12x2) bits in the wale direction X direction are in the course direction, The 12x2 (= mb) bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the 12 x2 (= mb) bit from the memory 31 in accordance with the allocation rule of Fig. 102. The code bits be to b23 of the element, for example, the symbol bits y〇 to y23 assigned to 12x2 (=mb) bits of consecutive 2 (=b) symbols as shown in Fig. 1 〇3 A, ❹ to replace 12x2 (= mb) the bit elements b 〇 to b 23 of the bit. That is, the replacing unit 32 assigns the code bit bG to the symbol bit yi 〇, respectively, and assigns the code bit b! to the symbol bit y. 〇, the code bit b2 is assigned to the symbol bit y 1, the code bit b3 Assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, and the code bit b 5 is assigned to the symbol bit y 4, 133671.doc -183 - 200947881 assigns the code bit b6 to The symbol bit y5 assigns the code bit b7 to the symbol bit y6, the code bit b8 to the symbol bit y7, and the code bit b9 to the symbol bit y8, and the code bit b ! 〇 assigned to the symbol bit ys», assign the code bit b丨! to the symbol y 1 〗, assign the code bit b12 to the symbol yi2, and assign the code bit b! 3 to Symbol bit y 14, assigning code bit b! 4 to symbol bit y 1 5, assigning code bit b! 5 to symbol bit y 1 6, assigning code bit b ! 6 to The symbol bit y22 assigns the code bit b! 7 to the symbol bit y 18, assigns the code bit b! 8 to the symbol bit y23, and assigns the code bit b! 9 to the symbol bit Y 17, assigning the code bit b2G to the symbol bit y 1 9, assigning the code bit b21 to the symbol bit y2 〇, and assigning the code bit b22 to the symbol bit y2 1, the code bit B23 is assigned to the symbol bit y 1 3 and is replaced. Figure 103B shows that the LDPC code is a length N of 16,200 The second example in which the LDPC code of the coding rate is 3/4, the modulation mode is 4096QAM, and the multiple b is 2, and the replacement of the code bits according to the allocation rule of FIG. 102 is used. If it is replaced according to FIG. 103B The unit 32 performs the following replacement for the 12 x 2 (= mb) bit code bits bG to b23, -184-133671.doc 200947881 read from the memory 31 according to the allocation rule of FIG. 102: The code bit bG is assigned to the symbol bit y23, the code bit b is assigned to the symbol bit y 8, the code bit b2 is assigned to the symbol bit y 1, and the code bit b3 is assigned to the symbol Bit y 15, assigning code bit b4 to symbol bit y3, assigning code bit b5 to symbol bit y4, and assigning code bit b6 to symbol bit y5,

The code bit b7 is assigned to the symbol bit y6, the code bit b8 is assigned to the symbol bit y2, the code bit b9 is assigned to the symbol bit y7, and the code bit bi 〇 is assigned to the symbol bit Element y9, assigning code bit b!! to symbol bit y 11, assigning code bit b! 2 to symbol bit y 1 2 ' assigning code bit b 丨 3 to symbol y 14. The code bit b! 4 is assigned to the symbol bit y 16, the code bit b!5 is assigned to the symbol bit y22, and the code bit bi 6 is assigned to the symbol bit y, the code Bit b! 7 is assigned to symbol bit y 18, code bit b! 8 is assigned to symbol bit y ] 〇, code bit b! 9 is assigned to symbol bit y 21, and code bit is assigned The element b2G is assigned to the symbol bit y 19 ', and the code bit b2! is assigned to the symbol bit y2 〇, and the code bit b22 is assigned to the symbol y 1 7, -185- 133671.doc 200947881 Bit b23 is assigned to symbol bit y丨3. Figure 104 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 2. Group. In the case of shai, the code bits b〇 to t> of 12x2 (= mb) bits read from § 忆 recall 3 1 are grouped according to the difference in error probability, as shown in Fig. 1A. It is a group of 3 code bits Gb^Gb^Gh. In FIG. 104A, respectively, the code bit group Gb! belongs to the code bit ^ and b 〗, the code bit group Gbs is the code bit 匕 to 匕7, the code bit group ❹ Gb3 code The bits bi8. to b23 belong. When the modulation method is 4096QAM and the multiple b is 2, the symbol bits y〇 to yn of the i2x2 (= mb) bits are different according to the error probability, as shown in Fig. 1〇4Β, the group can be divided into 6 The symbol element group 〇71, 〇%, 0 is, 0卩4, (^55(^6. Fig. 104B, which is the same as the case of Fig. 95B, respectively, the symbol bit group Gyi is The symbol element 丫〇, 丫1, 丫12,:^3 belongs to, the symbol element group (}^ 符元元元7273,714, 丫15 belongs to, the symbol element group 〇73 符Meta-location y4, y5, y〗 6, yi7 belongs to, symbolic element group Gy* is a symbol element ❹ y6, y7, yis, yi9 belongs to, symbol element group Gys system symbol element y8 , y9, y2〇, y2i belongs to the 'character bit group Gy0 system symbol element 丫10, 丫11, 丫22, 丫23 belongs to Fig. 105 shows that the LDPC code is code length N is 64800 bits. The coding rate is 3/4 LDPC code, and the further modulation mode is 1024QAM, and the multiple ^^ is 2 in the case of the allocation rule. The allocation rule in Figure 105 specifies the group aggregation information 133671.doc -186- 200947881 ( Gbi,Gy5,l) ' (Gb!,Gy6,l) ' (Gb2,Gyi,4) > (Gb2,Gy2,3) ' (Gb2, Gy3, 4), (Gb2, Gy4, 3), (Gb2, Gy5, 2), (Gb3, Gy2, l), (Gb3, Gy4, ", (Gb3, Gy5, l), (Gb3, Gy6, 3) That is, the allocation rule in FIG. 105 is defined as follows: According to the group set information (Gb^Gy^l), the code bit of the first good code bit group Gb! , assigned to the 1-bit of the symbol bit of the fifth-perfect symbol group Gy5 of the error probability;

According to the group set information (Gb, Gy6, l), the 1st bit of the code bit of the error probability jth good code bit group Gb! is assigned to the 6th good symbol bit group of the error probability. One bit of the symbol bit of the group Gy6; according to the group set information (Gb2, Gyi, 4), the 4th bit of the code bit of the second good code bit group Gb2 of the error probability is assigned to the error Probability of the second good symbol group Oy, the 4th bit of the symbol bit; according to the group set information (Gb2, Gy2, 3) Hard probability 2nd good 7ΓΤ ΦΘ code bit group Gbz The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the second good symbol group 〇 y2 of the error probability; according to the group set information (Gb2, Gy3, 4), the error probability The 4th good code bit 4 4 bits of the code bit of the group Gb2 is allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group Gys of the error probability; according to the group set information (Gb2 , Gy4, 3), assigning the error probability second good code bit, the 3 bit of the code bit of the group Gb2, to the error probability (the symbol of the second good symbol bit group Gy*) 3-bit According to the group set information (Gb2, Gy5, 2), the 2 bits of the code bit of the error probability code bit group Gb2 are assigned to the error probability and then 133671.doc • 187-200947881 2 bits of the symbol bit of the bit group Gy5; according to the group set information (Gb3, Gy2, l), the 1 bit of the code bit of the code bit group Gb3 of the 3rd good error probability, Assigned to the 1-bit of the symbol bit of the second-perfect symbol bit group Gy2 of the error probability; according to the group set information (Gb3, Gy4, l), the error probability third good symbol bit group The 1 bit of the code bit of Gb3 is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb3, Gy5, l), the error will be 1 bit of the code bit of the probability good third bit group Gb3, assigned to the 1st bit of the symbol bit of the error element 5th good symbol group Gy5; The group set information (Gb3, Gy6, 3) assigns the 3 bits of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol 6 of the error probability group Gy6 Meta-location Fig. 106 is a diagram showing an alternative of the code bits according to the allocation rule of Fig. 105. That is, Fig. 106A shows that the LDPC code is an LDPC having a code length N of 64,800 bits and a coding rate of 3/4. The code is further modulated by 4096QAM, and the multiple ❹ b is 2, and the code bit is replaced according to the allocation rule of FIG. 105. The first example is LDPC code is code length N is 64800 bits, and the coding rate is For the 3/4 LDPC code, if the modulation mode is 4096QAM and the multiple b is 2, in the demultiplexer 25, the X direction in the wale direction is (64800/(12χ2)) χ (12x2) bits. The code bits written by the memory 31 are read in the horizontal direction, read in units of 12x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). 13367], doc-188-200947881 The replacement unit 32 reads the code bits 13() of the 12><2 (=11113) bits from the memory 31 according to the allocation rule of FIG. 105 to 523, for example, FIG. 〇6 persons are assigned to symbolic bits y〇 to y23 of 12x2 (= mb) bits of consecutive 2 (=b) symbols to replace the code bits of 12><2(=mb) bits Yuan b〇 to b23. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 1 〇, the code bit b! to the symbol bit y 8, and the code bit b2 to the symbol y. Oh,

分配 Assigning code bit b3 to symbol bit y 1, assigning code bit b4 to symbol bit y2, assigning code bit b5 to symbol bit y3, and assigning bit bit b6 to symbol Bit y4, code bit b7 is assigned to symbol bit y5, code bit b8 is assigned to symbol bit y6, code bit b9 is assigned to symbol bit y7, and code bit b is Q Assigned to the symbol bit y 9, assigns the code bit bi! to the symbol bit y 12, assigns the code bit b! 2 to the symbol y 1 3, and assigns the code bit b! 3 to The symbol bit y 14, assigns the code bit b 1 4 to the symbol yi yi 6, assigns the code bit b ϊ 5 to the symbol y 17, and assigns the code bit b ! 6 to the symbol Bit y 1 8 assigns code bit bi 7 to symbol bit y2 〇, and assigns code bit b 8 to symbol y 15, 133671.doc -189- 200947881 code bit bi 9 Assigned to the symbol bit y 11, the code bit b2() is assigned to the symbol bit y22, the code bit b21 is assigned to the symbol bit y 19, and the code bit b22 is assigned to the symbol bit y2 1. The code bit b23 is assigned to the symbol bit y23 and replaced. Figure 106B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and further modulation is 4096QAM, and the multiple b is 2, the code bit according to the allocation rule of Fig. 105 The second example of replacement. According to FIG. 106B, the replacing unit 32 performs the following replacement for the code bits bG to b23 of the 12×2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 105: Yuan b. Assigned to the symbol bit y]1, the code bit b! is assigned to the symbol y8, the code bit b2 is assigned to the symbol y18, and the coded bit b3 is assigned to the symbol y 1, assign code bit b4 to symbol bit y7, assign code bit b5 to symbol bit y3, assign code bit b6 to symbol bit y4, assign code bit b7 to symbol The meta-bit y 12 assigns the code bit b8 to the symbol bit y6, the code bit b9 to the symbol bit y2, and the code bit b! 〇 to the symbol bit y 9, the code The bit b! i is assigned to the symbol bit y 5, 133671.doc -190- 200947881. The code bit b 1 2 is assigned to the symbol bit y 1 6 , and the code bit b 1 3 is assigned to the symbol bit Yuan yi 4, assigning the tilde b 1 4 to the symbol y 1 3 , assigning the code bit bi5 to the symbol yi7, and assigning the code bit b 16 to the symbol y 〇, The code bit b 1 7 is assigned to the symbol bit y20, and the code bit b 18 is assigned to the symbol bit y 15, ❹ 分配 The code bit b 19 is assigned to the symbol bit y 1 〇, the code bit is The element b2G is assigned to the symbol bit y23, the code bit b2i is assigned to the symbol bit y19, and the code bit b22 is used. Dispensing symbol bit y21, the code bit b23 to the assigned symbol bit y22. Figure 107 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the code bit group and the symbol bit in the case where the modulation mode is 4096QAM and the multiple b is 2. Group. In this case, the code bits b〇 to bn of the 12 X 2 (= mb) bits read from the memory 31 are grouped into three groups according to the difference in error probability as shown in FIG. 7A. Code bit group Gb 1 , Gb2., Gb3. In Fig. 107A, respectively, the code bit group code bits b〇 to b17 belong to, the code bit group Gb2 is the code bit b! 8 belongs to, and the code bit group Gb3 is code bits b19 to b23. Own. When the modulation mode is 4096QAM and the multiple b is 2, the symbol bits yQ to y23 of the I2x2 (= mb) bits are different according to the error probability, and can be grouped into 6 groups as shown in FIG. The symbol bit group is 71, 〇72, 〇, 〇%, 〇75, 〇76. 133671.doc • 191- 200947881 In Fig. 107B, as in the case of Fig. 95B, respectively, the symbol bit group 0 > ^ system symbol bit) ^, 71, 丫 12, 713 belongs to the symbol element group Group 〇 72 system symbol bits 72, 73714, 丫 15 belongs to, symbol element group 〇 73 system symbol y4, ys, yi6, yi7 belongs to, symbol element group Gy4 system symbol element Y6, y7, y] 8, yi9 belongs to, symbolic bit group Gys symbolic element y8, y9, y2G, y2i belongs to, symbolic element group Gy6 system symbol element bitmap 108 represents LDPC code It is an allocation rule in the case where the code length N is 16200 bits and the coding rate is 4/5 LDPC code, and the modulation mode is 4096QAM, and the multiple b is 2. In the distribution rule of Figure 108, there is a group collection information (Gb,, Gyi, 2) ^ (Gb^Gya^) ^ (Gb,, Gy3, 4) ' (Gb]sGy4j4) ^ (Gb^Gys,! ) ' (Gbi, Gy6, 4) ' (Gb2, Gy5, l) ' (Gb3, Gy1}2) ' (Gb3, Gy2, l), (Gb3, Gy5, 2). That is, the allocation rule in FIG. 108 is defined as follows: According to the group set information (Gb^GyiJ), the 2 bits of the code bit of the error probability first bit group Gb! are assigned to the error. Probability is good. The good symbol is the 2 digits of the symbolic group of Gy!; according to the group collection information (Gb^Gy2.), the probability of error is the first! 3 bits of the code bit of the good code bit group Gb! 'is assigned to the 3rd bit of the symbol bit of the second good symbol group Gy2 of the error probability; according to the group set information (Gb 〗 〖, Gy3, 4), assign the 4-bit ' of the code bit of the error probability i-th good code bit group Gb! to the error probability 3^ the good symbol bit group Gy3 4 bits of the yuan; • J92· 133671 .doc 200947881 According to the group set information (Gbl5Gy4, 4), the 4th bit of the code bit of the first good code bit group Gb丨 of the error probability is assigned to the error. The 4th bit of the symbol bit of the 4th good symbol bit group Gy4; the code bit of the coded bit group Gth with the first probability of error probability according to the group set information (Gbl5Gy5, l) 1 bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; according to the group set information (Gbl5Gy6, 4), the error probability first good code bit The 4 bits of the code bit of the meta-group Gb! are assigned to the 4th bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability; according to the group set information (Gb2, Gy5) l), assigning one bit of the code bit of the second good symbol bit group Gb2 of the error probability to one bit of the symbol bit of the fifth-perfect symbol bit group Gy5 of the error probability; According to the group set information (Gb3, Gyl52), the 2 bits of the code bit of the 3rd good code bit group Gb 3 of the error probability are assigned to the symbol group Gy with the first probability of error probability! 2 bits of the symbol bit; according to the group set information (Gb3, Gy2, l), the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the error probability 2 1 bit of the symbol bit of the good symbol bit group Gy2; and the code bit of the 3rd good code bit group Gb3 according to the group set information (Gb3, Gy5, 2) The 2 bits of the element are allocated to the 2 bits of the symbol bit of the symbolic group of the fifth symbol of the error probability Gy5. Figure 109 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 108. That is, FIG. 109A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 4096QAM, and the multiple 133671.doc • 193·200947881 b is 2. The first example of the replacement of the code bits according to the allocation rule of Fig. 8 is used. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5. In the case where the further modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction x course. The memory bit in the direction of (162 〇〇 / (12 χ 2)) χ (12 x 2) bits is written in the horizontal direction, read in units of 12x2 (= mb) bits, and supplied to the replacement. Part 32 (Fig. 16, Fig. 17). The replacing unit 32 allocates the code bits b from the 12x2 (= mb) bits of the memory 31 〇 to bn according to the allocation rule of FIG. 1 to 8, for example, as shown in FIG. b) The symbol y23 of the I2x2 (= mb) bit of the symbol is replaced by the tiling b's to b23 of the 12<2 (= mb) bits. That is, the replacing unit 32 separates the code bits b. Assigned to the symbol bit y〇, the stone horse bit b] is assigned to the symbol bit y!, the code bit b2 is assigned to the symbol bit y2, and the code bit b3 is assigned to the symbol bit y3 , 码 assign code bit b4 to symbol bit y4, assign code bit b5 to symbol bit y5, assign code bit b6 to symbol bit y6, and assign code bit b7 to symbol Bit y7, assigning code bit 1)8 to symbol bit y8, assigning mbit b9 to symbol bit y 1 〇', assigning code bit b 〇 to symbol bit y 11 ' 133671.doc -194- 200947881 assigning code bit b η to symbol bit yi 4, assigning mbit b! 2 to symbol bit y 1 6, assigning code bit b丨3 to symbol The bit y 17, assigns the code bit b 14 to the symbol bit y 1 8 , assigns the code bit bi 5 to the symbol bit y 19 , and assigns the code bit b ! 6 to the symbol bit y 22 , the code bit bi7 is assigned to the symbol bit y23, and the code bit b! 8 is assigned to the symbol bit y9,

The code bit b 1 9 is assigned to the symbol bit y2Q, the code bit b2G is assigned to the symbol bit y 1 2 , the code bit b21 is assigned to the symbol bit y 13, and the code bit b22 is assigned The symbol bit y 15, the code bit b23 is assigned to the symbol bit y2 1, and replaced. FIG. 109B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 4/5, and further modulation is 4096QAM, and the multiple b is 2, the code bit according to the allocation rule of FIG. The second example of replacement. According to Fig. 109B, the replacing unit 32 performs the following for the code bits b〇 to b23 of the 12><2 (= mb) bits read from the memory 31 in accordance with the allocation rule of Fig. 108; Substitute: assign code bit bQ to symbol bit y3, assign code bit b to symbol bit y 1, assign code bit b2 to symbol bit ys, and assign code bit b3 to The symbol bit y2, 133671.doc -195- 200947881 assigns the code bit b4 to the symbol bit y 11, assigns the code bit b5 to the symbol bit y22, and assigns the code bit b6 to the symbol bit The element y6 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit y5, and the mbit b9 to the symbol bit y 1 〇, and the code bit b! G is assigned to the symbol bit y7, the m-bit b!! is assigned to the symbol bit yi4, the code bit b! 2 is assigned to the symbol bit y〇, and the code bit b] is assigned to the symbol Meta-bit y! 7, assigning code bit bi 4 to symbol bit y 1 8, assigning code bit b! 5 to symbol bit y 19, assigning code bit b! 6 to symbol Bit y is 6, and the code bit b!7 is assigned to the symbol y23, and the code bit b! 8 The symbol bit y 9, the code bit b ! 9 is assigned to the symbol y20, the code bit b2G is assigned to the symbol y21, and the code bit b21 is assigned to the sym y y 13. The code bit b22 is assigned to the symbol bit y 1 5 and the code bit b23 is assigned to the symbol bit y 1 2 . Figure 110 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and the code bit group and the symbol bit in the case where the modulation b is 4096QAM and the multiple b is 2. Group. In this case, the code bits of the 12x2 (= mb) bits read from the memory 31 are 133671.doc -196-200947881 yuan b〇 to bu according to the difference in error probability, as shown in FIG. 11A. The group is divided into 5 code bit groups. In FIG. 110A, respectively, the code bit group Gbi code bit % and the ratio belong, the code bit group Gb2 is the code bit b2, and the code bit group Gb3 is the code bit h to bu. The code bit group ο, the code bit unit bi9 belongs to, the code bit group Gb> 5 is the code bit b2. To b23 belongs. When the modulation method is 4096QAM ′ when the multiple b is 2, the symbol y of the I2x2 (= mb) bit is y. To YU, according to the difference of error probability, as shown in Figure 1 1 0B ® , the group can be divided into 6 symbolic groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 110B, as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit group, and the symbol bit group Gy2 is a symbol bit 丫2, that is, 丫14,丫15 belongs to, the symbol element group (373 system symbol bit y4, ys, yi6, yi7 belongs to the 'character bit group Gy4 system symbol element yhy^ymyi9 belongs to the 'character bit group Gy5 The symbol element y8, y9, y2 〇, y: n belongs to the 'character bit group Gy6 line symbol element yi 〇, yn, y22, y23 belongs to Fig. 111 shows that the LDPC code is the code length n is 64800-bit, LDPC code with a coding rate of 4/5, further modulation method is 4096QAM, and the allocation rule is when the multiple b is 2. The distribution rule in Figure 111 specifies the group collection information (Gbl5Gy5, l) ' (Gbl5Gy6,l) ^ (Gb2,Gy,,l) ' (Gb3,Gyl53) ' (Gb3,Gy2,4) ' (Gb3,Gy3,3) > (Gb3,Gy4,4) ' (Gb3, Gy5,2) ' (Gb4, Gy3, l), (Gb5, Gy5, l), (Gb5, Gy6, 3). 133671.doc -197- 200947881 That is, the distribution rules in Figure 111 are as follows: Group collection information (Gb丨, Gys, l), will be wrong, the number of the first good code group Gb! 1 bit, assigned to the error y y good symbol group Gy5 symbol bit 1 bit; ; '5th good according to group collection information (Gb丨, Gy0, l), will be wrong The 1st bit of the code bit of the Gb! of the first good maze group of the ancestors is assigned to the 1st bit of the symbol bit of the good symbolic group Gy6; μ 6th good According to the group set information (Gb2, Gyi, l), the i-bit of the code bit of the error probability second code bit group Gh is assigned to the symbol of the symbol bit group Gy i with the wrong probability. 1 bit of the meta-bit; and according to the group set information (Gb^GyiJ) 'Assign the 3rd bit of the code bit of the error probability 3rd sound bit group Gh>3 to the good one ^ Error probability The first good character is located in the group Gy〗 3 bits; According to the group collection information (Gb3, Gy2, 4), the error probability third good code group The 4 bits of the code bit of Gb3 are assigned to the error probability, the 4th bit of the symbol bit of the Gya symbol group Gya; the meaning according to the group set information (Gb3, Gy3, 3) 'The error probability is the third best ❹ code bit group The 3 bits of the code bit of the group Gh are allocated, and the error probability is the 3rd good symbol bit group Gys 3 bits of the symbol bit; according to the group collection information (Gb3, Gy4 4), the error probability of the first "good ===4 bits of the code bit of the group Gb3, is assigned to the error (4) the money is good, the bit group Gy* is the 4th bit of the symbol bit According to the group collection information (still 3, 5, 2), the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the error probability 5th 133671.doc 200947881 The 2 bit of the symbol bit of the symbol group Gys; according to the group set information (Gl^Gy3, 〗), the code of the 4th good error probability is 1 bit of the group of code bits The element is assigned to the i-bit of the symbol bit of the third-perceived bit group Gys of the error probability; according to the group set information (Gb^Gh,;!), the error probability is the fifth good code position. 11 bit of the code bit of the group Gbs, assigned to the 1st bit of the symbol bit of the error probability $th good symbol bit group Gys; ❹ and according to the group set information (Gb5, Gy0, 3), will be wrong The code bits of the code bit group 5 good Gh within 3 bits allocated to the first well of the 6-bit symbol error probability of symbol bits Gy0 group of 3 yuan. Figure 112 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure ni. That is, FIG. 112A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and the further modulation method is 4〇96QAM, and the multiple b is 2, according to the figure. The first example of the replacement of the code bits of the allocation rule.

❹ The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 4/5. In the case where the modulation is 4096QAM and the multiple b is 2, the multiplexer 25 is in the traversing direction, and the horizontal direction is X. The code bit written in the memory 31 of the column direction (64800/Q2χ2)) χ (12χ2) bit is read in the horizontal direction in units of 12x2 (= mb) bits and supplied to the replacement unit 32 (Fig. 16, 17) ° The replacement unit 32 divides the code bits b from the 12x2 (= mb) bits of the memory 3 1 to bn according to the allocation rule of FIG. 111, for example, as shown in FIG. 112A to consecutive 2 ( =b) Symbols of 12x2 (= mb) bits of the symbol ... to y23, 133671.doc -199· 200947881 to replace the code bits b〇 to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 1 〇, the code bit bi to the symbol bit y 8, and the code bit b2 to the symbol y. 〇, assigning the code bit b3 to the symbol bit y 1, assigning the code bit b4 to the symbol bit y2, and assigning the code bit b5 to the symbol bit y3,

The code bit b6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y5, the code bit b 8 is assigned to the symbol bit y 6, and the code bit b9 is assigned to the symbol Bit y7, assigning code bit b! 〇 to symbol bit y 9, assigning code bit bi 1 to symbol bit y 12, and assigning code bit b! 2 to symbol bit y 1 3,

The code bit b]3 is assigned to the symbol bit y 14, the code bit b ! 4 is assigned to the symbol bit y 1 5 , and the code bit b ! 5 is assigned to the symbol bit y 16 The code bit b! 6 is assigned to the symbol bit y 18, the code bit b b 7 is assigned to the symbol bit y 1 9, and the code bit bi 8 is assigned to the symbol bit y2 〇, the code bit is The element b ! 9 is assigned to the symbol bit y 1 7 , the code bit b2G is assigned to the symbol bit y21 , and the code bit t » 21 is assigned to the symbol bit y 11, 133671.doc -200- 200947881 The code bit b22 is assigned to the symbol bit y22, and the code bit b23 is assigned to the symbol bit y23 for replacement. Figure 112B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5. Further modulation is 4096QAM, and the multiple b is 2, the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 112B, the replacing unit 32 performs the following for the code bits bG to b23 of the 12<2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 111, respectively. Replace: assign code bit b〇 to symbol bit 22, assign code bit b! to symbol bit y8, assign code bit b2 to symbol bit y 13, and place code bit b 3 Assigned to the symbol bit 1 6 , the code bit b4 is assigned to the symbol bit y2 , the code bit b5 is assigned to the symbol bit y3 , and the code bit b6 is assigned to the symbol bit y4 .

Q assigns the code bit b7 to the symbol bit y5, assigns the code bit b 8 to the symbol bit y 6, assigns the code bit b9 to the symbol bit y7, and assigns the code bit b 1 〇 For the symbol bit 2 1, assign the code bit b η to the symbol bit yi 2, assign the code bit b! 2 to the symbol bit 〇, and assign the code bit b 1 3 to the symbol bit Element 1 9 assigns the code bit b 1 4 to the symbol bit 1 5 ' 133671.doc -201 - 200947881 assigns the code bit b15 to the symbol bit, and assigns the code bit b!6 to the symbol The meta-bit 18 assigns the code bit b17 to the symbol bit M, the code bit b 18 to the symbol bit 2, and the code bit bi9 to the symbol y17, and the code bit b2Q is assigned to the symbol bit 9, the code bit b21 is assigned to the symbol bit ii, the m-bit b22 is assigned to the symbol bit y丨ο, and the code bit b is assigned to the symbol bit twenty three. ❿ Figure 113 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 5/6. The further modulation method is 4〇96QAM, and the multiples ^^ are in the case of the code bit group. And the symbol element group. In this case, the code bits TLbo to by of the 12><2 (=1111) bits read from the memory 31 are grouped into 4 according to the difference in error probability as shown in Fig. One code bit group Gbi, Gb2, Gb3, Gb4. In FIG. 113A, respectively, the code bit group is called the code bit element ^, the code bit group Gh is the code bit element to...8, the code bit group Gb3 © the code bit bit!^ 9 belongs to, the code bit group Glu is the code bit to 匕〗. When the modulation mode is 4096QAM and the multiple 1 is 2, the 12x2 (= mb) bit symbol bits yG to 丫23 are based on the difference in error probability, and can be grouped into a record as shown in the USB. Meta-bit group ~ gamma you you you. In Fig. 3B, as in the case of Fig. 95B, respectively, the symbol bit, the group Gyi, the symbol bit, the heart, the ^, the element, the group, the symbol, the bit, the heart, the heart, the The meta-group ^ system symbol bit 133671.doc -202- 200947881 y4, ys, yi6, yi7 belongs to, the symbol element group Gy4 is the symbol element y6, y?, yi8, yi9 belongs to, the symbol element The meta group Gy5 is a symbol element y8, y9, y2 〇, y2i belongs to, and the symbol element group Gy6 is a symbol element 71 〇, 711, 乂 22, 丫 23 belongs. Figure 114 is a diagram showing an LDPC code which is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and a further modulation method of 4096QAM and a multiple b of 2. In the allocation rule of Figure 114, there is a group set information® (Gbi, Gy6, l) ' (Gb2, Gyi, 4) ' (Gb2, Gy2, 3) ' (Gb2, Gy353) ' (Gb2, Gy4, 3 ), (Gb2, Gy5, 3), (Gb2, Gy6, 2), (Gb3, Gy5, l), (Gb4, Gy2, l), (Gb4, Gy3, l) ' (Gb4, Gy4, l), (Gb4, Gy6, l). That is, the allocation rule in FIG. 114 is defined as follows: According to the group set information (Gbi'Gy^l), the 1 bit of the code bit of the coded bit group Gb! Give the 1st bit of the symbol bit of the 6th good symbol group Gy6 of the error probability; ❿ According to the group set information (Gb: 2, Gyi, 4) 'The error probability 2nd good code bit The 4 bits of the code bit of the group Gh are assigned to the 4th bit of the symbol bit of the symbolic bit group Gy! of the error probability first; according to the group set information (Gt>2, Gy2 3), assigning the 3-bit ' of the code bit of the second good symbol bit group Gb2 of the error probability to the error probability 2nd ^3 of the symbol bit of the symbol group Gy2 According to the group set information (Gb2, Gy3, 3), the 3 bits of the code bit of the second good code bit group Gb2 of the error probability are assigned to the error probability third good symbol bit 3 digits of the symbol bit of the group Gy3; 133671.doc -203- 200947881 According to the group collection information (still 2 you 4, 3), the code point of the second good code bit group Gb2 of the error probability 3 yuan of the yuan' The error probability, the 4th symbol of the symbol 4 of the 4th good symbol group Gy#; the meaning of the second set of error probability according to the group collection information (still 2, 5, 3) , the 3 bits of the code bit of the group Gb2 are allocated to the 3 bits of the symbol bit of the error probability $th good symbol bit group Gy5;

According to the group set information (Gb2, Gy6, 2), the 2 bits of the code bit of the error probability second good 4 code bit group Gb2 are assigned to the error probability 'the second good symbol bit group Gy0 is a 2-bit symbol; according to the group collection information (called you (1)', the error probability third good code bit, the group Gb3 code bit! bit, assigned to the error probability of $ good丨 丨 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The second good symbol bit group GY2 of the symbol bit;

According to the group set information (Gb4, Gy3, i), the i-bit of the code bit of the fourth-perfect code bit group Gb4 of the error probability is assigned to the symbolic group Gy3 of the error probability. The bit element of the symbol bit; according to the group set information (Gb4, Gy4, i), the code bit of the 4th good error probability, the i bit of the code bit of the group Gb4, is assigned to the error probability '^ The fourth good symbol group Gy* symbol element bit; and according to the group set information, the error probability fourth good code bit group Gb4 code bit i bit , assigned to the symbol bit of the 6th good symbolic group of the error probability Ο%. 133671.doc • 204- 200947881 Figure 115 is an example of an alternative representation of the code bits in accordance with the allocation rules of Figure 114. That is, FIG. 115A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and the modulation method is 4096QAM, and the multiple b is 2, according to the allocation rule of FIG. The first example of the replacement of the code bit. The LDPC code is an LDPC code having a code length N of 1 6200 bits and a coding rate of 5/6. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is disposed in the longitudinal direction X horizontally. The memory block in which the column direction is (16200/(12χ2)) χ 〇 (12x2) bits is written in the horizontal direction, read in 12x2 (= mb) bit units, and supplied to the replacement. Part 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to b23 read from the 12<2 (= mb) bits of the memory 3 1 according to the allocation rule of Fig. 114, for example, as shown in Fig. 115A to the continuous 2 (= b) The symbol bits yG to y23 of the symbol 12<2 (= mb) bits are replaced by the code bits b of 12x2 (= mb) bits. To b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit yi〇, the code bit b! to the symbol bit y 〇, and the code bit b2 to the symbol bit, respectively. y 1, assign code bit b3 to symbol bit y2, assign code bit b4 to symbol bit y3, assign code bit b 5 to symbol bit y4, and assign code bit b6 to The symbol bit y5 assigns the code bit b7 to the symbol bit y6, 133671.doc -205 - 200947881 assigns the code bit b8 to the symbol bit y7 ' assigns the code bit bg to the symbol bit Y8 'Assign code bit b 1 〇 to symbol bit y 9 ' Assign code bit b!! to symbol bit yi〗 ' Assign code bit b12 to symbol y12 ' The element b 13 is assigned to the symbol element y 13 '. The code bit element !? is assigned to the symbol element yi4. The code bit element b15 is assigned to the symbol element 乂16. The stone element b is assigned to the symbol Meta-bit y 18 assigns code bit b ! 7 to symbol bit y2 分配 assigns code bit b 1 8 to symbol bit y 2 2 assigns code bit b 19 to symbol y 21 Assigning the code bit b2G to the symbol bit y23 assigning the mate b2 i to the symbol The element y, 9 assigns the code bit b22 to the symbol bit y丨7 and assigns the code bit b23 to the symbol bit yi5 for replacement. Fig. 115B shows that the LDPC code is code length n is 16,200 bits, coding The second example of replacing the LDPC code of 5/6, the further modulation mode is 4〇96QAM, and the multiple of ^^ is the replacement of the code bit according to the allocation rule of Fig. 114. If it is replaced according to Fig. 115B The unit 32 performs the following replacement for the code bits ^ to b23 of the 丨 2 x 2 (= mb) bits read from the memory 3 i according to the allocation rule of FIG. 114: assigning the code bit bG to The symbol bit 22, 133671.doc 200947881 assigns the code bit b! to the symbol bit y, assigns the mbit b2 to the symbol y 1, and assigns the code bit b3 to the symbol bit Y9, the code bit b4 is assigned to the symbol bit y3, the code bit b5 is assigned to the symbol bit y 18, the code bit b6 is assigned to the symbol bit y6, and the mate b7 is assigned to the symbol The meta-bit y4 assigns the m-bit b8 to the symbol y7,

The code bit b9 is assigned to the symbol bit y8, the code bit b! 〇 is assigned to the symbol bit 1 3 , the code bit b!! is assigned to the symbol bit y 11, and the code bit b is 2 is assigned to the symbol bit y2, the code bit b! 3 is assigned to the symbol bit 1 2, the code bit b ! 4 is assigned to the symbol bit y 1 4 , and the code bit b ! 5 Assigned to the symbol bit 1 6 , the code bit b 6 is assigned to the symbol bit 5 , the code bit b 丨 7 is assigned to the symbol bit y2 〇 , and the code bit bi 8 is assigned to the symbol Bit y 1 〇, assign code bit b 9 to symbol bit 2 1, assign code bit b2G to symbol bit 1 9, assign code bit b21 to symbol y23, The code bit b22 is assigned to the symbol bit 17, and the code bit b23 is assigned to the symbol bit i5. Figure 116 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of -207-133671.doc 200947881 5/6, and a further modulation mode is 4096QAM, and a multiple of ! Meta-groups and symbol-bit groups. In this case, 'the code bits b〇 to 1> 23 of the 12x2 (= mb) bits read from the memory 31 are grouped into 3 codes according to the difference in error probability as shown in Fig. 116A. The bit group Gb^Gb^Gh. In FIG. 116A, respectively, the 'code bit group Gb! code bit elements 〜 and ^ belong to, the code bit group Gt> 2 is the code bit t»2 to b!9 belongs to, the code bit group The Gb3 code bits b2 to b23 belong. When the modulation mode is 4096QAM and the multiple b is 2, the 12x2 (= mb) © bit symbol bits 丫() to 丫23 are based on the difference in error probability, as shown in Figure 116B. 6 symbolic group Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In Fig. 116B, as in the case of Fig. 95B, respectively, the symbol bit group 〇7 is a symbol element 丫(), 丫1, 712, 713 belongs to, the symbol bit group 〇> The symbol element 72, 丫3, 714, 丫15 belongs to, the symbol element group (3丫3 system symbol element y4, y5, yi6, yn belongs to, the symbol element group Gy4 system symbol element y6 , y7, yu, yi9 belongs to, the symbol element group Gy5 is a symbol element y8, y9, y2 〇, y2i belongs to the 'character bit group Gy6 system symbol element ❹ yi〇, y] i, Y22, y23 belong to Fig. 117 is an allocation rule in the case where the LDPC code is an LDPC code whose code length N is 64800 bits and the coding rate is 5/6, and the further modulation method is 4〇96qAm, and the multiple b is 2. In the allocation rule of Figure 117, there is a group set information (Gbi5Gy4,l) '(Gb!,Gy6,l) ^ (Gb2sGy,,4) ' (Gb2jGy2,4) ' (Gb2,Gy3,4) ' ( Gb2, Gy4, 2) ^ (Gb2, Gy5, 4) > (Gb3, Gy4, l) ' 133671.doc -208. 200947881 (Gb3, Gy6, 3). That is, the distribution rule in Figure 117, As follows: According to the group collection information (GbbGy4, 〗), the code position of the error probability i-th good code bit group Gb! i bit, assigned to the error probability * * good symbol bit group Gy "the symbol bit of the bit element; according to the group set information (Gb ^ Gwj), the wrong probability of the first good code The unit of the code bit of the bit group Gb丨 is allocated to the bit element of the symbol bit of the symbol 6th good symbol group Gye of the error probability; ◎ according to the group set information (Gb^Gy !〆), the 4 bits of the code bit of the second good code bit group Gh of the error probability are assigned to the 4 bit of the symbol bit of the symbol cell group Gy with the wrong probability probability. According to the group set information (Gb2, Gy2, 4), the 4th bit of the code bit of the second good code bit group Gh of the error probability is assigned to the second good symbol bit group with the wrong probability. 4 bits of the symbol bit of Gy2; according to the group set information (Gb2, Gy3, 4) 'Assign the 4th bit of the code bit of the 2nd good weight bit group Gb2 of the error probability to the error Probability 3rd good symbol group Gys 4th bit of the symbol bit; according to the group set information (Gb2, Gy4, 2), the error probability second good code bit group Gh code 2 bits of the element, assigned to the 2nd bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb2, Gys, 4) 'The error probability is 2nd good The 4 bits of the code bit of the code bit group Gh are allocated to the 4 bit of the symbol bit of the error probability number 戸 符 符 位 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; GyU), the error probability 3rd good 133671.doc -209- 200947881 code bit group Gb3 code bit! bit, assigned to the error probability third good symbol bit group Gy* The bit position of the meta-bit; and assigning the error probability to the 3 bits of the code bit of the 3rd good code bit group Gb3 of the error probability according to the group set information (Gb3, Gy0, 3) The 6th good symbol element group Gy6 is a 3-bit symbol. Figure 118 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 117. That is, FIG. 118A shows that the LDPC code is an LDPC code with a code length of 648 bits and a coding rate of 5/6, and the step-by-step modulation method is 4〇96QAM, and the multiple b is 2, according to FIG. The first example of the replacement of the code bits of the distribution rule. The LDPC code is a code length Ng 648 〇〇 bit, and the coding rate is 5/62 LDpc code. In the case where the modulation mode is 4096QAM and the multiple b is 2, in the case of the solution, the direction of the X direction is in the direction of the X direction. The code bits written for the memory 31 of (648 〇〇 / (ΐ 2 χ 2)) χ (12 x 2) bits are in the course direction, read out in 2 (-mb) bit units, and supplied to the replacement portion 32. (Figure 6, Figure 17). The replacing unit 32 assigns the code bits b() of the 12x2 (-mb) bits read from the memory 31 to the bn according to the allocation rule of FIG. 117, for example, as shown in FIG. U8A, for consecutive 2 (=b) The symbol y of the 12x2 (= mb) bit of the symbol. To y23, to replace the code bits b〇 to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit force, assigns the code bit b! to the symbol bit y6, and assigns the code bit h to the symbol bit y, respectively. 133671.doc -210· 200947881 assigning code bit b3 to symbol bit y 1, assigning code bit b4 to symbol bit y2, and assigning code bit b 5 to symbol bit y 3, The code bit b6 is assigned to the symbol bit y4, the code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y8 , assign the code bit b! ο to the symbol bit y9,

The code bit b η is assigned to the symbol bit y! 2, the code bit b12 is assigned to the symbol bit yn, the code bit bi3 is assigned to the symbol bit y14, and the code bit b 4 is assigned. To the symbol bit y 1 5, assign the code bit b! 5 to the symbol y! 6, assign the code bit b! 6 to the symbol y! 7, and the code bit b! Assigned to the symbol bit y! 8, assigns the code bit b! 8 to the symbol bit y2, assigns the code bit b! 9 to the symbol y 2!, and assigns the code bit b2G to The symbol bit y 11, the code bit b21 is assigned to the symbol bit y22, the code bit b22 is assigned to the symbol bit y 1 9, and the code bit b23 is assigned to the symbol bit y23. replace. Figure 118B shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and 5/6, and the further modulation method is 4096QAM, -211 - , and the coding rate is a multiple b of 133671.doc 200947881. The second example of the replacement of the code bits of the distribution rule. According to FIG. 118B, the replacement unit 32 performs the following replacement for the code bits bG to b23 of the i2x2 (= mb) bits read from the s replied body 3 according to the allocation rule of FIG. U7: The code bit b〇 is assigned to the symbol bit 22, the mom bit b! is assigned to the symbol bit y6, the code bit is assigned to the symbol bit yi 3 , and the code bit b3 is assigned to the symbol bit The element yn, the code bit element t>4 is assigned to the symbol bit y2, the code bit element t>5 is assigned to the symbol bit element ^, the code bit element W is assigned to the symbol bit element", and the code bit element is t>7 is assigned to the symbol bit y5, the code bit t»8 is assigned to the symbol bit y9, the code bit 1>9 is assigned to the symbol bit y8, and the code bit b 〇 is assigned to The symbol bit y7 assigns the code bit bn to the symbol bit 712, assigns the code bit bu to the symbol bit y〇, and assigns the code bit b]3 to the symbol bit y2〇, The code bit 1^4 is assigned to the symbol bit yi5, the code bit hh 5 is assigned to the symbol bit yi 6, and the code bit b ! 6 is assigned to the symbol bit yi, and the code bit 匕7 Assigned to the symbol bit yl8, the code bit b!8 is assigned to the symbol bit y] 4, the code bit Yuan!^9 is assigned to the symbol element y2i, 133671.doc • 212- 200947881 The code bit b2G is assigned to the symbol bit yn, the code bit b21 is assigned to the symbol bit 丫10, and the code bit is b] 2 is assigned to the symbol bit y 19, and the code bit b23 is assigned to the symbol y23. Figure 119 shows that the LDPC code is an LDPC code with a length N of 16200 bits and a coding rate of 8/9. The further modulation mode is 4096QAM, and the code bit group and the symbol bit group in the case where the multiple b is 2. In this case, the code of the 12X2 (= mb) bit read from the memory 3 1 Bits _B to bn are grouped into 5 code bit groups Gb^GbhGbhGbhGbs according to the difference in error probability as shown in Fig. 119A. In Fig. 119A, respectively, 'code bit group Gb! The code bit element 1 > 〇 and b! belong, the code bit group Gb2 is the code bit b2, the code bit group Gb3 is the code bit t>3 to b2〇, the code bit group Gb4 is The code bit element b21 belongs to, and the code bit group Gbs is the code bit b22 and b23. The modulation mode is 4096QAM, and the multiple b is 2, the I2x2 (= mb) ^ bit symbol bit y〇 To y23 based on the difference in error probability As shown in FIG. 119B, the ungroupable group is divided into six symbol bit groups Gyi, Gy2, G is, Gw, Gy5, G%. In Fig. 119B, as in the case of Fig. 95B, respectively, the symbol bit The group Gyi is a symbol element 7(), 71, 5^2, 713 belongs to, and the symbol element group (^2 is a symbol element 丫2, ^3, >^4,>^5 belongs to The symbol element group 〇73 is the symbol element y4, y5, yi6, yi? belongs to, the symbol element group Gy4 is the symbol element y6, y7, yi8, yi9 belongs to, the symbol element group Gy5 is a symbol element ys, y9, y2 〇, y2i belongs to, the symbol element group Gy6 is a symbol element bit 1 〇, 丫 11, 丫 22, 丫 23 belongs. 133671.doc -213- 200947881 FIG. 120 shows an LDPC code which is an LDPC code having a code length n of 16,200 bits and an encoding rate of 8/9, and a further modulation method of 4096QAM and a multiple b of 2. In the allocation rule of Fig. 120, a group set information (Gbl5Gy6, 2) '(Gb2, Gy6, l) ^ (Gb3, Gy, 4) > (Gb3, Gy2, 4) ' (Gb3, Gy3, 4), (Gb3, Gy4, 4), (Gb3, Gy5, 2), (Gb4, Gy5 l), (Gb5, Gy5, l) ' (Gb5, Gy6, l) 〇, that is, the distribution in Figure 120 The rule is as follows: According to the group set information (Gb^Gy6.) 'Assign the 2 bits of the code bit of the error probability first good code bit group Gb' to the error probability sixth good symbol 2 bits of the symbol bit of the bit group Gy6; according to the group set information (Gb2, Gy6, l), the 1 bit of the code bit of the second good code bit group Gb2 of the error probability, Assigned to the 1-bit of the symbol bit of the sixth-perfect symbol bit group Gy6 of the error probability; according to the group set information (Gb3, Gyi, 4), the error probability third good symbol bit group The 4 bits of the code bit of Gbs are allocated to the 4th bit of the symbol bit of the symbol i-good symbol group Gy!; according to the group set information (Gb3, Gy2, 4), Error probability 3rd good code bit group Gb3 code bit 4 bits, assigned to error Rate the 4th bit of the second good symbol group Gys symbol; according to the group collection information (Gb3, Gy3, 4), the error probability 3rd good code bit group Gbs The 4 bits of the code bit are assigned to the 4th bit of the symbolic element of the 3rd good symbol group Gy3; 々 According to the group collection information (Gb3, Gy4, 4), the error will be optimistic 3 good 133671.doc -214- 200947881 code bit tl group Gb3 code bit 4 yuan, assigned to the error probability 4th good symbol group Gy4 4 bits of the meta-bit; according to the group set information (Gb3, Gys, 2), the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability are assigned to the 5th error probability. 2 bits of the symbol bit of the symbol group Gy5; according to the group set information (Gb4, Gys, l), the code number of the 4th good error probability is the code bit of the group Gtu The bit element is assigned to the 1-bit element of the symbol bit of the fifth-perceived bit group Gys of the error probability; according to the group set information, the code bit of the error probability fifth good code bit group Gbs The element of the element is assigned to the 1st bit of the symbol bit of the symbolic group Gys of the 5th good probability group; and the error probability is 5th according to the group set information (Gb^Gy^l) The good code position 〖 bit of the code bit of the group Gbs is allocated to the 丨 bit of the symbol bit of the sixth symbol of the error probability group Gy6. Figure 121 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 12A. That is, FIG. 121A shows that the LDPC code is an LDPC code with a code length of 162 〇〇 bit encoding rate of 8/9, and the further modulation method is 4 〇 96 qam, and the multiple b is 2, according to FIG. The first example of the replacement of the code bits of the distribution rule of 〇. The LDPC code length n is 16200 bits, and the LDPC code with an encoding rate of 8/9 is 4096QAM and the multiple b is 2. In the multiplexer 25, the direction of the x direction is in the direction of the x direction. The code bits written for the memory 31 of (ΐ62〇〇/(ι2χ2))χ (12×2) bits are in the course direction, read out in units of 12×2 (-mb) bits το, and supplied to the replacement unit 3 Figure 16, Figure 133671.doc -215· 200947881 17). The replacing unit 32 assigns the code bits bG to b23 read from the 12><2 (= mb) bits of the memory 31 in accordance with the allocation rule of Fig. 120, for example, as shown in Fig. 121A to consecutive 2 (=b). The symbolic bits y〇 to y23 of the symbol 12<2 (= mb) bits are substituted for the code bit b of the 12<2 (= mb) bits. To b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 1 〇, the code bit b 1 to the symbol bit y 11, and the code bit b2 to the symbol bit, respectively. Y22, the code bit b3 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to The symbol bit y3 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit y5, and the code bit b9 to the symbol bit y6, and the code bit b ! 〇 assigned to symbol y 7, assigning code bit b η to symbol y 8, assigning code bit b! 2 to symbol ys», assigning code bit b 丨 3 To the symbol bit y 12, the code bit b 4 is assigned to the symbol bit y 1 3 , the code bit b b 5 is assigned to the symbol bit y 1 4 , and the code bit bi 6 is assigned to The symbol bit y 15, the code bit b! 7 is assigned to the symbol yi 6, 133671.doc -216- 200947881 The code bit b 18 is assigned to the symbol yi ya 7, * the code bit b! 9 is assigned to the symbol bit yi 8, and the code bit b 2 〇 is assigned to the symbol bit y 19 ' b 21 to the symbol bit y 2 billion, the code bit b22 to the symbol bit Y2i, Mary the bit b 3 to the symbol〗 bits Y23, and replaced. FIG. 121B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 〇8/9, and further modulation is 4096QAM, and the multiple b is 2, and the code position according to the allocation rule of FIG. The second example of the replacement of Yuan. According to FIG. 121B, the replacing unit 32 performs the following replacement for the code bits bQ to b23 of the 12x2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 120: B〇 is assigned to the symbol bit y23, the code bit b! is assigned to the symbol bit y!!, the code bit b2 is assigned to the symbol bit y22, ◎ the mbit b3 is assigned to the symbol bit Element y!9, assign code bit b4 to symbol bit y 1, assign code bit b5 to symbol bit y! 8, assign code bit b6 to symbol bit y3, place code bit The element b7 is assigned to the symbol bit y4, the code bit b8 is assigned to the symbol bit y9, the code bit b9 is assigned to the symbol bit y6, and the code bit b! 〇 is assigned to the symbol bit y7 , 133671.doc -217- 200947881 assigning code bit b 11 to symbol bit y 8, assigning code bit b12 to symbol bit y5, and assigning code bit b 3 to symbol bit y 5, the code bit b14 is assigned to the symbol bit 713, the code bit b 1 5 is assigned to the symbol bit y 〇, and the code bit b 16 is assigned to the symbol bit y 丨 2, The code bit b 17 is assigned to the symbol bit yi 6, and the code bit bi 8 is assigned to the symbol The meta-bit yi 7 assigns the code bit b19 to the symbol bit y2, 0 assigns the code bit b2G to the symbol bit y14, and assigns the code bit b2i to the symbol bit y20, and the code bit B22 is assigned to the symbol bit y2 i, and the code bit b 2 3 is assigned to the symbol bit y 1 〇. Figure 122 shows the LDPC code with an LDP C code of 640 bits and a octave rate of 8/9, and a further modulation method of 4096QAM and a multiple of b. Group and symbol bit groups. In this case, the code bits 〇 b 〇 b to bn of the 12 > 2 (= mb) bits read from the memory 31 are group-divided into 5 according to the difference in error probability as shown in Fig. 122A. The code bit group 〇 1) 1, 01 > 2, 01) 3, 0134, 0135. In FIG. 122A, respectively, the code bit group Gb 1 belongs to the code bit b〇 and b 1 , the code bit group Gb2 belongs to the code bit b2, and the code bit group Gb3 is the code bit b3. To b2〇, the code bit group Gb4 is the code bit b21, the code bit group Gb5 is the code bit b22 and b23 belongs to the modulation mode is 4096QAM, and the multiple b is 2, 12x2 (= Mb) 133671.doc -218- 200947881 The bit yG to yn of the bit is based on the difference in error probability. As shown in Fig. 122B, the group can be divided into 6 symbol group Gyl5Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 122B, as in the case of FIG. 95B, respectively, the symbol bit group Gyi belongs to the symbol bit group, and the symbol bit group (^2 is the symbol element 丫2, 73, 714, 715 belongs to, and the symbol The meta-bit group 〇丫3 is a symbol element y4, y5, yi6, yi7 belongs to, the symbol element group Gy4 is a symbol element y6, y7, yi8, yi9 belongs to, the symbol element group Gy5 The symbol element y8, y9, y2 〇, y2i belongs to, the symbol element group Gy6 is the symbol element >^1〇, 711, 丫22, 丫23 belongs to Fig. 123 is the table LDPC code is The code length N is 64800 bits, the coding rate is 8/9 LDPC code, and the further modulation mode is 4096QAM, and the multiple b is 2. The allocation rule in FIG. 123 specifies group group information ( GbbGy6, 2), (Gb2, Gy6, l), (GbhGyM), (Gb3, Gy2, 4), (Gb3, Gy3, 4), (Gb3, Gy4, 4), (Gb3, Gy5, 2), ( Gb4, Gy5, l), (Gb5, Gy5, l), (Gb5, Gy6, l). That is, the distribution rule in Figure 123 is as follows: According to the group collection information (Gb!, Gy6, 2), Assign the error probability to the second bit of the code bit of the good code bit group Gb Error probability 6th good symbol group Gy6 symbol element 2 bits; according to group set information (Gb^Gy^l) 'The error probability 2nd good code bit group Gt> 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability; according to the group set information (Gb3, Gy, 4), The probability of error is the third best 133671.doc -219- 200947881 The 4th bit of the code bit of the code bit group Gb3 is assigned to the symbol bit of the wrong probability bit group Gy 4 bits; according to the group set information (Gb3, Gy2, 4), assign the error probability "4 bits of the code bit of the good code bit group Gb3" to the error probability; 2 the good symbol bit 4 bits of the symbol group of the meta-group Gys; according to the group set information (Gb3, Gy3, 4), the 4th bit of the code bit of the 3rd good code bit group Gb3 of the error probability is allocated Give the 4th bit of the symbol bit of the symbolic group of the third good symbol bit Gy] of the error probability;

Q According to the group set information (10) (10) "10 error probability ^ good 4 bits of the code bit group Gb3, assigned to the error probability (the symbol of the third good symbol group Gy * 4 bits of the bit; according to the group set information (Gb3, Gys, 2) 'Assign the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability to the error probability, the first good 2 bits of the symbol bit of the symbol bit group Gys;

According to the group set information (Gb4, Gy5, l), the code bit of the 4th good code bit of the error probability 1 group bit of the group Gh is assigned to the 5th good symbol bit group Gy5 with the error probability. 1 bit of the symbol bit; according to the group set information (Gb^Gy5, 〗), the 1st bit of the code bit of the 5th good code bit group Gb5 of the error probability is assigned to the error probability 5: 1 bit of the symbol element Gy5 of the good symbol group; and according to the group set information (Gb^Gy^l), the code point of the 5th good code bit group Gbs of the error probability The 1 bit of the element is assigned to 1 bit of the symbol bit of the symbolic group of the sixth symbol of the error probability Gy6. Figure 124 is a diagram showing an alternative of the code bits according to the allocation rule of Figure 123. 133671.doc - 220 - 200947881 That is, Figure 124A shows that the LDPC code is an LDPC having a code length N of 64,800 bits and an encoding rate of 8/9. The first example of the replacement of the code bits according to the allocation rule of FIG. 123 in the case where the code is further modified to 4096QAM and the multiple b is 2. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 8/9. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(12χ2)) χ (12x2) bits are in the course direction, read out in units of Ο 12x2 (= mb) bits, and supplied to the replacement unit 32. (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits be to b23 read from the 12><2 (= mb) bits of the memory 31 in accordance with the allocation rule of Fig. 123, for example, as shown in Fig. 124A to the continuous 2 (=b). The symbolic bits y〇 to y23 of the symbol 12<2 (= mb) bits are replaced with the code bits b 〇 b b of the 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y! 分别, 分配 assigns the code bit b! to the symbol bit y!!, and assigns the code bit b2 to the symbol bit. Element y22, assigning code bit b3 to symbol bit y〇, assigning code bit b4 to symbol bit y 1, assigning code bit b5 to symbol bit y2, and allocating code bit b6 For the symbol bit y3, the code bit b7 is assigned to the symbol bit y4, and the code bit b8 is assigned to the symbol bit y5, 133671.doc -221 - 200947881 assigning the code bit b9 to the symbol bit Element y6, assigning code bit b! 〇 to symbol bit y 7, assigning code bit bn to symbol bit y 8, assigning code bit bi 2 to symbol bit ys >, code Bit b! 3 is assigned to symbol bit y 1 2, code bit b 4 is assigned to symbol bit y 1 3, mom bit bi 5 is assigned to symbol bit y 14, and code bit is assigned The element b 16 is assigned to the symbol bit y 15, the code bit b! 7 is assigned to the symbol bit y 16, and the code bit b! 8 is assigned to the symbol bit y 17, the code bit b! 9 is assigned to the symbol bit y 1 8, the code bit b2 〇 is assigned to the symbol y 19 , and the code bit b21 Dispensing y2〇 bit symbols, the code bit b22 to the symbol bit assigned y2 1, the code bit b23 to the symbol bits allocated Y23, and replaced. Figure 1248 shows the [0?0: code is an LDPC code with a code length of 1^ of 64 800 bits and a coding rate of 8/9. The further modulation is 4096QAM, and the multiple b is 2, according to Figure 123. The second example of the replacement of the code bits of the allocation rule. According to Fig. 124B, the replacing unit 32 performs the following replacement for the code bits bQ to b23' of the 12><2 (= mb) bits read from the memory 31 in accordance with the allocation rule of Fig. 123; : assigning the code bit bG to the symbol bit y23, assigning the code bit b! to the symbol bit y 1!, -222-133671.doc 200947881 assigning the code bit b2 to the symbol bit y22, The code bit b3 is assigned to the symbol bit y 19 , the code bit b4 is assigned to the symbol bit y 1, the code bit b5 is assigned to the symbol bit y 18 , and the code bit b6 is assigned to the symbol The meta-bit y3 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit ys>, and the code bit b9 to the symbol bit y6, ❹

The code bit b! 〇 is assigned to the symbol bit y 7, the code bit bn is assigned to the symbol bit y 8, the code bit b! 2 is assigned to the symbol bit y5, and the code bit b is 3 is assigned to the symbol bit y 1 5, the code bit bi 4 is assigned to the symbol bit y 1 3 , and the code bit bi 5 is assigned to the symbol bit y 〇, the code bit b 6 Assigned to the symbol bit y 1 2, the code bit b! 7 is assigned to the symbol y! 6, and the code bit b ! 8 is assigned to the symbol y 1 7 , the code bit b ! 9 is assigned to the symbol bit y2, the code bit b2G is assigned to the symbol bit y 1 4 , the code bit b21 is assigned to the symbol bit y2 〇, and the code bit b22 is assigned to the symbol y2 1. The code bit b23 is assigned to the symbol bit y 10. The coding rate is a multiple b is 2. Figure 125 shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and 9/10, and a further modulation method is 4096QAM, 133671.doc -223 - 200947881. Group and symbol bit groups. In this case, the code bits bQ to bn of the i12x2 (== mb) bits read from the memory 31 are group-divided into 5 code bit groups as shown in FIG. 125A according to the difference in error probability. Gb], Gb2, Gb3, Gb4, Gb5. In FIG. 125A, respectively, the code bit group GBI is a code bit ～ and belongs to, the code bit group Gbz is a code bit h, and the code bit group Gb3 is a code bit t gt; 3 to B2〇 belongs to, the code bit group oh is the code bit b2l, and the code bit group G1>5 is the code bit b22 and b23. When the modulation method is 4096QAM and the multiple b is 2, the symbol y of the I2x2 (= mb) ® bit is y. To yn, according to the difference in error probability, as shown in FIG. 125B, the group can be divided into 6 symbol bit groups (^1, (^2, (373, (^4, (^5, (^6). In Fig. 125B, as in the case of Fig. 95B, respectively, the symbol bit group Gy! is a symbol element 丫(), 71, 丫12, >^3 belongs to the symbol element group ( :^2 is a symbol element 丫2,73,714, 丫15 belongs to, a symbol element group (3丫3 system symbol y4, ys, yi6, yi7 belongs to, symbol element group Gy4 character The meta-location y6, y?, yis, yi9 belongs to, the symbol-bit group Gy5 is the symbol element ys, y9, y2G, y2! belongs to the 'character-bit group Gy6-based symbol-bit ❹ 丫 1 126, 711, 丫22, 丫23 belong to Fig. 126 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 9/10, and the modulation mode is 4096QAM, and the multiple b is 2. The allocation rule. The distribution rule in Figure 126 specifies group information (Gbi, Gy6, 2) ' (Gb2, Gy5, l) ' (Gb3, Gyi, 4) ' (Gb3, Gy2, 4), ( Gb3, Gy3, 4), (Gb3, Gy4, 4), (Gb3, Gy5, 2), (Gb4, Gy6, l) ' 133671.doc -224- 200947881 (Gb5, Gy5, l), (Gb5, Gy6 , l) That is, the allocation rule in Figure 126 is defined as follows: According to the group set information (Gb^Gy6.), the 2 bits of the code bit of the code bit group Ghh of the i-th good error probability are assigned to The error probability is 6th good symbol bit group Gy0 symbol bit 2 bit; according to the group set information (Gb^Gy^l), the error probability second good code bit group Gb2 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; according to the group set information (Gb3, Gy!, 4), the error probability The 4th bit of the code bit of the 3rd good code bit group Gt>3 is assigned to the 4th bit of the symbol bit of the error probability jth good symbol bit group Gy!; Set information (Gb3, Gy2, 4) 'Assign the 4 bits of the code bit of the 3rd good code bit group Gbs of the error probability to the symbol of the second good symbol bit group Gy2 with the wrong probability. 4 bits of the bit; according to the group set information (Gb3, Gy3, 4), the 4th bit of the code bit of the 3rd good code bit group Gbs of the error probability is assigned to the third probability of error probability The 4th bit of the symbol bit of the symbol group Gy3; according to the group set information (Gt»3, Gy4, 4), the code bit of the 3rd good code bit group Gb3 of the error probability The 4th bit is assigned to the 4th bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gt>3, Gy5, 2), the error probability is 3rd. 2 bits of the code bit of the good code bit group Gb3, assigned to the 2 bit of the symbol bit of the symbol 5th good symbol bit group Gy5; according to the group set information (Gb^ Gy6, 〗), the error probability is 4th good 133671.doc • 225- 200947881 code bit group Gb4 code bit 1 bit, assigned to the error probability 6th good symbol bit group Gy6 1 bit of the symbol bit; according to the group set information (Gb5, Gy5, l), the 1st bit of the code bit of the 5th good code bit group Gb5 of the error probability is assigned to the error probability 5th 1 bit of the symbol element of the good symbol group Gy5; and the code bit of the 5th good code bit group Gb5 according to the group set information (Gb5, Gy6, l) 1 Yuan, assigned to the sixth well of the error probability of the symbol bit group Gy6 symbol bits of one yuan. Figure 127 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 126. That is, FIG. 127A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and further modulation is 4096QAM, and the multiple b is 2, and the allocation rule according to FIG. The first example of the replacement of the code bits. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(12χ2)) χ (12×2) bits are in the course direction, read out in the unit of 12×2 (= mb) bits, and supplied to the replacement unit 32. (Fig. 16, Fig. 17). The replacing unit 32 reads out from the memory 3 1 according to the allocation rule of FIG. 126 ><2 (= mb) bits of code bits b 到 b 23, for example, 12 cc assigned to consecutive 2 (= b) symbols as shown in FIG. 127A> <2 (= mb) bit symbol bits yG to y23 to replace the code bits b〇 to b23 of 12 x 2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 1 〇, respectively, and assigns the code bit b! to the symbol bit y 11, respectively, 133671.doc -226-200947881, and the code bit b2 Assigned to the symbol bit ys, the code bit b3 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, and the code bit b5 is assigned to the symbol bit y2, Code bit b6 is assigned to symbol bit y3, code bit b7 is assigned to symbol bit y4, 玛ma bit b8 is assigned to symbol bit y5 ', and code bit b9 is assigned to symbol bit Y6, assign code bit b! 〇 to symbol bit y7, assign code bit b ] ί to symbol bit y9 ' assign mom bit bi 2 to symbol bit yi 2 put code bit b! 3 is assigned to the symbol bit yi 3 The code bit b14 is assigned to the symbol bit yi4 The code bit bi 5 is assigned to the symbol bit yi 5 ❹ The code bit b! 6 is assigned to the symbol bit Element y〗 6 Assign code bit b! 7 to symbol bit yi 7 Assign code bit b! 8 to symbol bit yi8 Assign code bit b 19 to symbol bit yi 9 Put the code bit The element b2〇 is assigned to the symbol bit y2, and the code bit b2 1 is assigned to the symbol bit Y22. The code bit b22 is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y21 - 227 - 133671.doc 200947881 for replacement. 127B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and further modulation is 4096QAM, and the multiple b is 2, and the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 127B, the replacing unit 32 performs the following replacement for the code bits b〇 to b23 of the 12×2 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 126: The bit bQ is assigned to the symbol bit y23, the code bit b! is assigned to the symbol bit y 11, the code bit b2 is assigned to the symbol bit y21, and the code bit b3 is assigned to the symbol bit y 13, assigning the code bit b4 to the symbol bit y 1, assigning the code bit b5 to the symbol bit y2, assigning the code bit b6 to the symbol bit y 18, and allocating the code bit b7 To the symbol bit y4, the code bit b 8 is assigned to the symbol bit y 5 , the code bit b9 is assigned to the symbol bit y6 , and the code bit bi 〇 is assigned to the symbol bit y 7 . The code bit b!丨 is assigned to the symbol bit y9, the code bit b!2 is assigned to the symbol bit y2〇, and the code bit b!3 is assigned to the symbol bit y 〇, the code bit is The element b 1 4 is assigned to the symbol bit y 1 4 '. The code bit b ! 5 is assigned to the symbol bit y 1 5, 133671.doc -228 - 200947881 The code bit b 16 is assigned to the symbol bit y 16 ' assign code bit b 1 7 to symbol y 1 7 ' to place code bit b 18 is assigned to the symbol bit y 3 , and the code bit b 1 9 is assigned to the symbol bit y 1 9 '. The code bit b 2 G is assigned to the symbol bit y 1 2 '. The code bit b 2 1 is assigned to the symbol bit y 2 2 ' The code bit b 2 2 is assigned to the symbol bit y 1 0 ' The code bit b23 is assigned to the symbol bit ys. 〇 In the above, the new replacement method will be described with respect to the case where the modulation method is 1024QAM and the case of 4096QAM. The arrangement of the symbols (corresponding signal points) for each modulation method will be described below. Fig. 128 is a diagram showing the arrangement on the IQ plane of 1024 symbols (corresponding signal points) in the case where 1024Q AM is performed by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 128 shows a method of arranging the arrangement of symbols of 1024QAM inductively from the configuration of the symbol of 256QAM of DVB-T.2. Further, in Fig. 128, (i, q) indicates the coordinates (I coordinate and Q coordinate) on the IQ plane of the symbol. Further, C256(i, q) is a symbol at the position of the coordinates (i, q) among the numbers of the specific symbol (hereinafter also referred to as the symbol number) of the 256 symbols of the 256QAM. Yuan (attached to Fu Yuan) symbol number. Hereinafter, the symbol of 256QAM located at the position of the coordinate (i, q) is also referred to as the C256 (i, q) symbol. Further, C1 024(i, q) is a symbol number representing a symbol located at a position of coordinates (i, q) among 1024 symbols of 1024QAM. Hereinafter, the symbol of position 2 1024QAM located at seat 133671.doc - 229 - 200947881 q) is also referred to as ^(four)^, q) symbols. Now, if all 256 symbols of 256QAM are moved in parallel in the first quadrant of the ... plane, the c256(i, q) symbols of the 256qam after the parallel movement become the Ci24 of the 1024qam (i , q) = C256 (i, phantom symbol. Further, if 256 symbols of 256QAM that have been moved in parallel in the first quadrant are symmetrically moved for the I axis, then the C256 (i) of the 256qaM after the symmetric movement 'q) symbols become the first Cl〇24(i,_q) = C256(i, q)+256 symbols of i〇24QAM. ❹ and 'If 256QAM of 256QAM has been moved in parallel in the first quadrant The verb 60' moves symmetrically about the Q axis, and the C256(i,q) symbols of the 256QAM after the symmetric movement become the C1024(-i,q) = C256(i, q)+256x2 of 1〇24Qam. Further, if the 256 symbols of 256QAM that have been moved in parallel in the first quadrant are symmetrically moved to the origin, the C256(i,q) symbols of the 256qam after the symmetric movement become 1〇. Cq 024 (-i, -q) = C256 (i, q) + 256 x 3 symbols β 〇 of 24qAM In addition to the above Xth symbol, the value of 2 is expressed as the symbol Value For example, if C256(i, q)=25, the symbol value of the C256(i, q) symbol is 00011 〇〇1 B (B indicates that the value before it is 2 carry). Moreover, for example, in the case of C1024(i,q)=823, the symbol value of the second c.24(i, q) symbols is 1100110111B 〇 and 'for example, the second quadrant (i <〇,Q>0), C1〇24(-i,q)=C256(i, 133671.doc -230- 200947881 q)+256x2 symbols (i, q>0) are located so that they are parallel The C256(i,q) symbols of the 256 symbols of 256QAM moving in the first quadrant are moved to the position where the Q axis is linearly symmetric, and the C1024(-i,q)=C256( The symbol value of i, q)+256x2 symbols is the high-order 2 bit of the value of C256(i, q) expressed by the 2-bit, and the value of 2 of 256x2, that is, the value of 1 0B is added by the 2-bit. . In 1024QAM, the number m of 1 symbol is 10, and the symbol of 1 symbol is represented by the most significant bit (y〇, yi, · · · , ym-i)= ® (y〇,yi , y2, y3, y4, y5, y6, y7, ys, y9) ° For example, in the case of Ci〇24(i,q) = 823, the symbol value of Ci(24, i, q) symbols, That is, the 10-bit symbol element (y〇, yi, y2, y3, y4, y5, y6, y7, y8, y9) is (1,1,0,0,1,1,0,1, 1). Then, as illustrated in FIG. 62 to FIG. 94, respectively, the symbol bit y0, yi belongs to the symbol bit group Gy!, and the symbol bit y2, y3 belongs to the symbol bit group Gy2. The symbol bit y4, y5 belongs to the symbol bit group Gy3, the symbol bit y6, y7 belongs to the symbol bit group Gy4, the symbol bit y8, y9 belongs to the symbol bit group Gy5 . Further, the subscript j belongs to the symbol element of the smaller symbol group Gyj, and the better the error probability (the fault tolerance is strong). Fig. 129 is a diagram showing the arrangement on the IQ plane of 4096 symbols (corresponding signal points) in the case where 4096QAM is performed by the quadrature modulation unit 27 of Fig. 8. Further, in Fig. 129, C4096(i, q) represents the symbol number of the symbol located at the position of the coordinates (i, q) among the 4096 symbols of 4096QAM. Hereinafter, the symbol of 4096QAM located at the position of the coordinates (i, q) is also referred to as C4〇96(i,q) 133671.doc -231 - 200947881 symbols. Now, the 1024 symbols of 1024QAM described in FIG. 128 are all moved in parallel in the first quadrant on the IQ plane, and then the C1Q24 of the 1024QAM after the parallel movement (i, the symbols become the 4th of the 4Q96Q) —,q)= Ci〇24(i, q) symbols. If the 1024 symbols το ' of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically for the I axis, then the c] 〇 24 (i, q) symbols of the 1〇24qAM after the symmetric movement become 4第96qam's C4096(i,-q) = C1 024(i,q)+l〇24 symbols. Moreover, if the 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are symmetrically moved about the Q axis, the Cl024(i, q) symbols of the 1〇24qAM after the symmetric movement become 4〇96QAM. The first C4096(-i,q)= Ci〇24(i,q)+l〇24x2 symbols. Further, if 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically to the origin, the C 1024 (i, q) symbols of the 1024QAM after the symmetric movement become the C4 of 4096QAM. 96(_i,_q)= Ci〇24(i,q)+1024><3 symbols. The symbol bits of the symbols of 1024QAM (Fig. 128) and 4096QAM (Fig. 129) are also the same as those described in Fig. 12 and the like, and there are strong bits and weak bits. Figs. 130 to 133 show the results of the simulation of the BER (Bit Error Rate) in the case where the replacement processing of the new replacement method has been performed and the case where the replacement processing has not been performed. That is, FIG. 130 shows an LDPC code having a code length N of 16,200, a coding rate of 2/3, 133671.doc, 232, 200947881, 3/4, 3/5, 5/6, and 8/9, respectively. As the modulation method, the BER in the case of 1024QAM is adopted. Figure 131 is a diagram showing an LDPC code having a code length N of 64,800, a coding rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10, and 1024QAM as a modulation method. The BER in the case. FIG. 132 is a diagram showing an LDPC code having a code length N of 16,200, a coding rate of 2/3, 3/4, 3/5, 5/6, and 8/9 as a target, and 4096QAM is used as a modulation method. BER. ® Figure 133 shows the LDPC code with a code length N of 64800 and a coding rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10 as the modulation method. BER in the case of 4096QAM. Further, in FIGS. 130 to 133, the multiple b is 2. Further, in Figs. 130 to 133, the horizontal axis represents Es/N 〇 (signal power to noise power ratio per symbol), and the vertical axis represents BER. Further, the solid line indicates the BER in the case where the replacement processing of the new replacement method has been performed, and the dotted line indicates the BER in the case where the replacement processing is not performed. From Fig. 130 to Fig. 133, the replacement processing of the new alternative is compared with the case where the replacement processing is not performed, and the BER is increased, so that the error tolerance for the error is known. Further, in the present embodiment, for convenience of explanation, in the multiplexer 25, the replacing unit 32 performs replacement processing on the code bit read from the memory 31, but the replacement processing can be controlled by the memory. The writing or reading of the code bits of the body 31 is performed. That is, the replacement process can be performed from the memory 3 1 by, for example, controlling the address of the read code bit (read 133671.doc -233 - 200947881 out address), in the order of the replaced code bit. The reading of the code bits is performed. Next, Fig. 134 is a block diagram showing the L configuration example of the last name 1 12 of the receiving device 12 of Fig. 7. In Fig. 134, the receiving device 12 receives the data processing device from the transmitting device u (the modulated signal of Fig. 4), and is composed of a quadrature demodulating unit 51, a demapping unit W, an deinterleaver 53 and an LDPC decoding unit 56. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device and performs quadrature demodulation, and supplies the signal point (the 〇 value in each of the 1 and Q-axis directions) obtained as a result to the demapping unit 52. The mapping unit 52 performs demapping to cause the signal point from the orthogonal demodulation unit 5 to become a symbol of the LDPC code symbolized, and supplies it to the deinterleaver 53. The anti-parent 53 is composed of The device (MUX) 5 4 and the vertical twist reverse deinterlace 55 are configured to perform deinterlacing of the symbol bits from the symbols of the demapping unit 52. That is, the multiplexer 54 is derived from the demapping portion 52. The symbol 〇 of the symbol is used as the object 'to perform the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the multiplexer 25 of FIG. 8, that is, to perform replacement processing by replacement processing The position of the code bit (symbol bit) of the LDPC code is returned to the original position. The LDPC code obtained as a result thereof is supplied to the whirling torsional deinterleaver 55. The whirling torsional deinterleaver 55 takes the LDPC code from the multiplexer 54 as the object 'to perform the wobble interleaving corresponding to FIG. The longitudinal torsion and de-interlacing of the longitudinal twisting and interlacing of the 133671.doc-234-200947881 rearrangement processing (the reverse processing of the longitudinal torsional interleaving) is performed as the vertical processing by the rearrangement processing The row is twisted and interleaved to change the code bits of the aligned LDPC code, and returns to the inverse alignment processing of the original arrangement, for example, the longitudinal twist de-interlacing. Specifically, the vertical twist reverse deinterleaver 55 is used by referring to FIG. 22 and the like. The memory 31 shown in the figure is similarly constructed as a memory for deinterleaving, written into the code bits of the LDPC code and further read for longitudinal twist reverse deinterlacing. The writing of the code bit is performed by using the read address from the reading of the code bit of the memory 31 as the write address, and in the course direction of the memory for deinterleaving. The reading of the code bit will be for the memory 3 1 The write address at the time of writing of the bit is used as the read address, and is performed in the wale direction of the memory for deinterleaving. The LDPC code obtained by the result of the wobble deinterlacing is reversed from the wales. The interleaver 55 is supplied to the LDPC decoding unit 56. Here, in the LDPC code supplied from the demapping unit 52 to the deinterleaver 53, the ❹ co-interlace, the wobble interleave, and the replacement processing are applied in this order, but in the opposite direction. The interleaver 53 performs only the inverse replacement processing corresponding to the replacement processing and the vertical twist reverse de-interlacing corresponding to the directional twist interleaving, so that the co-deverse interleaving corresponding to the co-located interleaving (the inverse processing of the co-located interleaving) is not performed, that is, The parity bit of the LDPC code whose alignment is changed by the co-located interleaving is returned to the parity deinterlacing of the original arrangement. Therefore, from the deinterleaver 53 (the whirling torsional deinterleaver 55), the LDPC decoding unit 56 is supplied with the inverse replacement processing and the vertical twist deinterlacing, and the 133671.doc -235-200947881 is not subjected to the co-deinterlacing. LDPC code. The LDPC decoding unit 56 performs the LDPC code from the deinterleaver 53 by performing at least the conversion check matrix obtained by the LDPC encoding of the LDPC encoding unit 21 of FIG. The LDPC decodes and outputs the data obtained as a result of the decoding of the target data. Figure 135 is a flow chart showing the reception processing performed by the receiving device 12 of Figure 134. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device u in step Slu, and the processing proceeds to step SU2 to perform orthogonal demodulation of the modulated signal. The orthogonal demodulation unit 5 1 supplies the point obtained by the result of the orthogonal demodulation to the demapping unit 52, and the processing proceeds from the step sm to the step s113, and the demapping unit 52 performs the positive The signal point of the demodulation unit becomes the demapping of the symbol it, and is supplied to the deinterleaver 53, and the processing proceeds to step S114. ❹ The step sm' deinterleaver 53 performs deinterlacing from the 7L bit 7L of the symbol from the demapping unit 52, and the processing proceeds to step S1b. In step S114, in the deinterleaver 53, the multiplexer 54 performs the inverse replacement processing on the symbol bit from the symbol of the bucket 52 as the object ', and the obtained LDPC code is supplied to the vertical bit. The line reverses the inverse staggered state 55. The whirling torsional deinterlacer 55 supplies the object to the LDPC decoding unit 56 by performing the wander reverse deinterlace. The LDPC code from the multiplexer 54 is used as 'the Ldpc 133671'doc • 236, 200947881 obtained as a result in step S115, and the LDPC decoding unit 56 uses the check matrix for LDPC encoding by the LDPC encoding unit 21 of FIG. Η, at least performing a LDPC decoding of the LDPC code from the directional reverse deinterleaver 55 by performing a conversion check matrix equivalent to the interleave interlace row replacement, and using the data obtained as a result as the decoding result of the target data Output, processing is over. Further, the reception processing of FIG. 135 is repeated. Further, FIG. 134 is also the same as the case of FIG. 8. For convenience of explanation, the multiplexer 54 for performing the reverse replacement process and the reticular reverse deinterleaver 55 for performing the slant reverse twisting are separately formed, but the multiplexer 54 The longitudinal torsional deinterlacer 55 can also be constructed integrally. Further, in the case where the transmitting device 11 of Fig. 8 does not perform the whirling interleaving, the receiving device 12 of Fig. 134 does not need to provide the whirling reverse interleaver 55. Next, the LDPC decoding performed by the LDPC decoding unit 56 of Fig. 134 will be further explained. As described above, the LDPC decoding unit 56 of FIG. 134 performs at least the conversion check matrix obtained by the row replacement of the parity interleave by using the check matrix 用于 for the LDPC encoding by the LDPC encoding unit 21 of FIG. The LDPC decoding of the LDPC code of the slant reverse deinterleaver 55 is performed by the inverse replacement processing and the vertical twist deinterleave, and the eccentric deinterlacing is not performed. Here, an LDPC decoding has been proposed, which performs LDPC decoding by using a conversion check matrix, and can suppress the circuit scale while suppressing the operating frequency to a sufficiently achievable range (refer to Japanese Laid-Open Patent Publication No. 2004-343170, for example). . 133671.doc -237- 200947881 Thus, LDPC decoding with respect to the previously proposed utilization conversion check matrix is first described with reference to FIGS. 136 to 139. Figure 136 is a diagram showing an example of a check matrix LDP of an LDPC code having a code length N of 90 and a coding rate of 2/3. Further, in Fig. 136 (the same applies to Figs. 137 and 138 which will be described later), 0 is represented by a period (.). In the check matrix of Figure 136, the co-located matrix becomes a stepped structure. Fig. 137 is a diagram showing the inspection matrix 获得 obtained by the row replacement of the equation (11) and the row replacement of the equation (12) in the inspection matrix 图 of Fig. 136. Column permutation: 6s+t+1st column—5t+s+1st column• · · (11) Line permutation: 6x+y+61st line—5y+x+61st line • · · (12) where 'in formula (11 ) and (12), s, t, X, and y are respectively 〇$s <5, 〇^t <6, 0Sx <5, 0 St An integer in the range of <6. If it is replaced according to the formula (11), the substitution is performed by dividing the first, seventh, third, fourth, and fifth columns of the first, seventh, third, fourth, and fifth columns by the remainder of the six. The 2nd, 8th, 14th, 2nd, and 26th columns with 6 remainders are replaced by the 6th, 7th, 8th, 9th, and 10th columns, respectively. Further, if the row is replaced by the equation (12), the 61st row and the later (colocated matrix) are replaced by the following cases: the 61st, 67th, 73rd, 79th, and 85th lines divided by the 6th remainder are replaced by the Lines 61, 62, 63, 64, 65, divided by 6 and 2, the 62nd, 68th, 74th, 80th, and 86th lines are replaced by the 66th, 67th, 68' 69, 70th line 0 133671.doc • 238 200947881 Thus, the matrix obtained by performing column and row permutation for the check matrix of FIG. 136 is the check matrix Η' of FIG. Here, even if the column replacement of the inspection matrix is performed, the arrangement of the code bits of the LDPC code is not affected. Moreover, the row permutation of the equation (12) is equivalent to the information length of the co-interleaving in which the K+qx+y+1 code bits are interleaved to the position of the K+Py+x+1 code bits. K is 60, and the number of rows P of the unit of the cyclic structure is 5 and the co-located interleaving when the number q (=M/P) of the co-located length M (here, 30) is 6. For the check matrix of FIG. 137 (hereinafter referred to as a replacement check matrix as appropriate) H', the LDPC code multiplied by the check matrix of FIG. 136 (hereinafter referred to as the original check matrix) H is performed with equation (12). For the matrix after the same permutation, the 0 vector is output. That is, if the column vector obtained by the row permutation of the equation (12) is expressed as c' in the column vector c of the LDPC code (1 Ma word) which is the original inspection matrix, the nature of the matrix is checked. Look, HcT becomes a 0 vector, so ITc'T also becomes a 0 vector. According to the above, the conversion check matrix H' of Fig. 137 is based on the LDPC code c of the original check matrix ◎ array, and the check matrix of the LDPC code c' obtained by the row replacement of the equation (12). Therefore, in the LDPC code c of the original check matrix, the row substitution of the equation (12) is performed, and the LDPC code c' of the row replacement is decoded (LDPC decoding) by using the conversion check matrix H' of FIG. The decoding result is subjected to the inverse permutation of the row permutation of the equation (12), whereby the decoding result in the case where the LDPC code of the original inspection matrix 利用 is decoded by the inspection matrix 可获得 can be obtained. Fig. 138 shows the change of the check matrix Η' by the 133 671.doc - 239 - 200947881 in the interval of the matrix of 5x5. In Fig. 138, the 'conversion check matrix Η is represented by a combination of the following matrix: a unit matrix of 5x5; a matrix of one or more of the unit matrix 1 is 0 (hereinafter suitably referred to as a quasi-unit matrix); A matrix or a quasi-unit matrix is subjected to a cyclic shift matrix (hereinafter referred to as a shift matrix as appropriate), a sum of 2 or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter suitably referred to as sum Matrix); and a matrix of 5 x 5 。. The conversion check matrix H' of Fig. 138 can be composed of a unit matrix of 5x5, a quasi-unit matrix, a shift matrix, and a matrix and a unitary matrix. Therefore, the 5x5 matrix constituting the conversion ❿ check matrix H' is hereinafter referred to as a constituent matrix as appropriate. The decoding of the LDpc code represented by the check matrix represented by the constituent matrix of ΡχΡ can utilize ρ architectures for simultaneous check node operations and variable node operations. Figure 139 is a block diagram showing a configuration example of a decoding apparatus that performs such decoding. That is, Fig. 139 shows a decoding apparatus for decoding LDPC codes by using the conversion check matrix Array H' of Fig. 138 obtained by performing at least the row of the equation (12) on the original check matrix H' of Fig. 136. The structure example. The decoding device of FIG. 139 includes: a branch data storage memory 300 composed of six 卩抒〇3001 to 3006, a selector 301 for selecting 卩1?03001 to 3006, and a check node calculation unit 3〇2, 2 The cyclic shift circuits 3〇3 and 308, and the branching data storage memory 304 composed of 18, are selected? The selector 305 of the 03041 to 30418, the received data storage 306 storing the received information, the variable node calculation unit 3〇7, the decoded word 133671.doc • 240·200947881, the calculation unit 309, the received data rearrangement unit 310, and the decoding Data rearrangement unit 3U. First, a description will be given of a method of storing data for the memory 3's and 3'' of the branch data storage. The branch data storage memory 300 is composed of six FIF0300j 3006 which are divided by the number of columns 30 of the conversion check matrix H' in Fig. 138 and which are divided by the number of columns 5 of the matrix. FiF〇3〇〇y (y=1, 2, · · ·, 6) is composed of the § recall area of the complex number of segments. The memory area of each segment can be read or written simultaneously corresponding to the constituent matrix. 5 branches of the number of columns and the number of rows. Further, the number of segments of the FIF〇3〇〇yi memory region is the maximum number of the number of the column of the conversion check matrix of Fig. 138 (Hamming weight), that is, 9. In FIF0300, the data corresponding to the position of the first column to the fifth column of the conversion check matrix 图 of FIG. 138 (the message V from the variable node) is stored in a form in which the columns are horizontally packed ( In the form of neglecting 〇). That is, if the i-th row of the j-th column is denoted as (j, i) 'the first-stage memory area of the FIFO 300] is stored corresponding to the conversion check matrix H' from (1, 1) to (5, 5). ) The position of the unit of the 5x5 unit moment q array. In the second segment memory region, a shift matrix corresponding to the conversion check matrix H1 from (1, 21) to (5, 25) is stored (the shift of the unit matrix of 5x5 to the right is only cyclically shifted by three) Information on the location of the matrix 1). The memory areas from the third to the eighth segments are also stored in correspondence with the conversion check matrix η. Then, the 9th segment memory region stores a shift matrix corresponding to the conversion check matrix H from (1, 86) to (5, 90) (substituting 1 of the 1st column in the unit matrix of 5×5 with 〇, And only the data of the position of 1 of the shift matrix of one rear is shifted to the left. The FIF030 〇 2 ′ stores the information corresponding to the position of the conversion check matrix η of Fig. 138, 133671.doc -241 - 200947881, the sixth column to the tenth column. That is, in the first slave 5 area of the chat (1) (9) 2, there is a sum matrix corresponding to the composition conversion check matrix H, from (6, 1) to (i〇, 5) (will be 5) <The unit matrix of 5 is shifted only to the right by the first shift matrix of the first shift matrix and the sum of the sum of the second shift matrix of the unit matrix to the right only cyclically shifted by 2) Information on the location of the matrix 1 . Further, the second-stage memory area stores information corresponding to the position of the second shift matrix constituting the sum matrix of the conversion check matrix ( from (6'1) to (1〇, 5). That is, with respect to a constituent matrix having a weight of 2 or more, a unit matrix having a weight of iipxp 〇, one or more of the elements 1 is a quasi-unit matrix of 〇 or a cyclic shift of the unit matrix or the quasi-unit matrix When the form of the complex sum in the rear shift matrix represents the constituent matrix, the data corresponding to the position of the early bit matrix, the quasi-unit matrix or the shift matrix of the weight 1 is corresponding to the unit matrix, The message of the unit matrix or the shifting matrix is stored in the same address (the same FIF0 in FIF03001 to 3006). Hereinafter, the data is stored in the memory area from the third to the ninth segments in association with the conversion check matrix H'. ◎ FIFO3OO3 to 3〇〇6 are also assigned to the conversion check matrix H, and the data is stored. The branch data storage memory 304 is composed of 18 FIFOSO^ to 304丨8 which are divided by the number of rows constituting the matrix, divided by the conversion check matrix H, and the number of rows 90. The FIFO 304x (x=l, 2, · · ·, 18) is composed of a plurality of memory areas, and the number of rows and rows corresponding to the conversion check matrix H' can be simultaneously read or written in the memory area of each segment. The number of 5 branches of the message. 133671.doc -242- 200947881 In FIFCno^, corresponding to the conversion check matrix H of Figure 138, the information of the position of the ith row to the fifth row (the message from the check node is stored as each row is longitudinally padded) The form (in the form of neglecting 〇). That is, in the first segment memory area of the FIFO 304, one of the unit matrix of 5x5 corresponding to the conversion check matrix H from (1, 1) to (5, 5) is stored. The data of the position. The memory area of the second segment is stored corresponding to the composition of the conversion check matrix H, from the sum matrix of (6, ^ to (1 〇, 5) (the cyclical matrix of 5 x 5 is only cyclically shifted to the right) The data of the position of the first shift matrix of the first shift matrix and the sum of the first shift matrix and the second shift matrix that cyclically shifts the unit matrix to the right only. The segment memory area stores data corresponding to the position of the second shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (1〇, 5). That is, the weight is 2 In the above constituent matrix, a unit matrix of pxp having a weight of 1 and a quasi unit matrix having one or more of the elements 1 is 0. Or when the unit matrix or the quasi-unit matrix is cyclically shifted, the sum of the complex moments in the Q matrix represents the constituent matrix, corresponding to the unit matrix, the quasi-unit matrix or the shift matrix of the weight 1 The location data (corresponding to the information belonging to the unit matrix, the quasi-unit matrix or the branch of the shift matrix) is stored in the same address (the same FIFO in FIF〇3〇41 to 3〇4丨8) 〇, Regarding the memory areas from the 4th and 5th segments, the data is also stored in correspondence with the conversion check matrix 。. The number of segments of the memory area of the 11th, 3rd, and 41st is a conversion check matrix Η 'from the 1st line to the first line The maximum number of 1 in the direction of 5 rows (Hamming weight) is 5. 133671.doc -243- 200947881 FIFO3042 and 3043 are also assigned to the conversion check matrix Η' to store data, respectively, the length (number of segments) 5) FIF 〇 3044 to 30412 are also assigned to the conversion check matrix H' to store data, respectively, the length is 3. The Ting 〇 30413 to 30418 are also assigned to the conversion check matrix H' to store data, respectively The length is 2. The operation of the decoding device of Fig. 139 is explained. The branch data storage memory 300 is composed of six FIFCs OChl 3006, and the five messages D3 11 supplied from the previous stage cyclic shift circuit 308 belong to the conversion check. The information of the matrix H' (Matrix data) D312, selects the FIFO for storing data from the ® scare 03001 to 3006, and sequentially stores the five messages D311 in the selected FIFO. Moreover, the branch data is stored. The memory 300 sequentially reads out five messages D300! from the FIFC^Oth when the data is read, and supplies it to the selector 301 of the next stage. The branch data storage memory 300 is sequentially read from FIF03002 to 3006 after the reading of the message from FIF0300!, and is supplied to the selector 301. The selector 301 selects the signal according to the selection signal D301. Five messages of the FIFO of the data are now read out in FIF03001 to 3006, and supplied to the check node calculation unit 302 as the message D302. The check node calculation unit 302 is composed of five check node calculators 302! to 3025, and uses the message 0302 (03021 to D3025) supplied by the selector 301 (the message of the equation (7) according to the equation (7). The check node operation is performed, and the five messages 0303 (03031 to D3035) (the message Uj of the equation (7)) obtained as a result of the check node operation are supplied to the cyclic shift circuit 303. 133671.doc -244- 200947881 The cyclic shift circuit 303 is to cyclically shift the information of several original unit matrices in the conversion check matrix by the five messages 03031 to 03035 obtained by the check node calculation unit 302 (Matrix data). The D305 is cyclically shifted, and the result is supplied to the branch data storage memory 304 as a message D304. The branch data storage memory 304 is composed of 18 卩卩〇3041 to 30418, in accordance with the anterior segment. The five messages D304 supplied by the cyclic shift circuit 303 belong to the information D305 of the conversion check matrix H', and the FIFO storing the data is selected from the 卩 030 03041 to 30418, and the five messages D304 are sequentially stored together. In the choice of FIFO. Also, points When the data storage memory 304 is reading data, the five messages D306! are sequentially read from the FIFO 304! and supplied to the selector 305 of the next stage. The branch data storage memory 304 is from the FIFC^O. After the reading of the data is completed, the messages are sequentially read from the FIFOs 3042 to 30418 and supplied to the selector 305. The selector 305 selects the data currently read from the stuns 3041 to 30418 according to the selection signal D307. The five messages of the FIFO are supplied to the variable node calculation unit 307 and the decoded word calculation unit 309 as the message D308. On the other hand, the received data rearrangement unit 310 transmits the LDPC code D313 received through the communication channel. The line of the equation (12) is replaced and rearranged, and supplied to the received data memory 306 as the received data D3 14. The received data memory 306 is received from the received data D3 from the received data rearrangement unit 3 10 The received LLR (Logarithmic Probability Ratio) is calculated and memorized, and the received LLR is supplied to the variable node calculation unit 307 and the 133671.doc -245-200947881 decoded word calculation unit 309 as the reception value D309. Variable node calculation unit 307 It consists of five variable node calculators 3〇7ι to 3〇75 'using the message D3〇8 (D308 to D3〇85) supplied by the selector 305 (message Uj of the equation (1)) and receiving from The data is obtained by the five received values D309 (the received value of the equation (1)) supplied from the memory 3〇6, and the variable node operation is performed according to the equation (1). The message D3 1 〇 obtained by the result of the calculation (D3101 to D31〇5) (message Vi of the equation (1)) is supplied to the cyclic shift circuit 3〇8. The cyclic shift circuit 308 is based on the information 〇3101 to 〇31〇5 calculated by the variable node calculation unit 307, based on the information of the unit matrix of the original branch in the conversion check moment and the cyclic shift 0. The result is cyclically shifted, and the result is supplied to the branch data storage memory 3 as the message D3 11. By patrolling the above operation once, the LDPC code can be decoded once. The decoding apparatus of Fig. 139 decodes the LDPC code only a specific number of times, and obtains the final decoding result in the decoding word calculation unit 309 and the decoded data rearrangement unit 311, and outputs the result. That is, the decoded word calculation unit 309 is composed of five decoded word calculators 3〇9ι to 3〇95, and the five messages D3〇8 (d3〇8i © to D3085) output by the selector 3〇5 ( The message Uj) of the equation (5) and the five received values D309 (received value (丨) of the equation (5)) supplied from the received data memory 3〇6 are used as the final segment of the plurality of decodings according to the equation (5). The decoding result (decode word) is calculated, and the decoded data D3 15 obtained as a result is supplied to the decoded data rearrangement unit 3丨i. The decoded data rearrangement unit 3 11 performs the inverse permutation of the line replacement of the equation (12) by using the decoded data D315 supplied from the decoded word calculating unit 3 to 9 to rearrange the order and as the final decoding. The result is D3i6 and is output. 133671.doc -246· 200947881 For example, by applying a column permutation and a square or both sides to the inspection matrix (original inspection matrix), it is converted into a unit that can be ρχρ, and the element 1 There is one or more quasi-unit matrices of 0, a shift matrix of a unit matrix or a quasi-unit matrix, a quasi-unit matrix of a unit matrix, or a sum matrix of shift matrices, ρ xp The combination of the 0 matrix 'is a check matrix (conversion check matrix) which can be represented by a combination of the matrixes, and the LDPC code can be decoded by using an architecture of ρ check node operations and variable node operations simultaneously (architecture). By doing this, P nodes are simultaneously operated, and the operating frequency can be lowered to an achievable range, and a lot of repeated decoding is performed. The receiving apparatus 12iLDPC decoding unit 56 constituting the diagram 134 is the same as the decoding apparatus of Fig. 139, and performs LDPC decoding by performing p check node operations and variable node operations simultaneously. In other words, if the check matrix of the LDPC code outputted by the LDPC encoding unit 21 of the transmitting device of FIG. 8 is set as the check matrix h of the ladder structure, for example, if the parity matrix shown in FIG. The co-interleaver 23 of the transmitting device 11 interleaves the Κ+qx+y+1 code bits to the position of the K+Py+x+1 code bits, and sets the information length κ as 60. The number of rows P of the unit of the loop structure is set to 5, and the number q of the isotope length μ (=M/P) is set to 6. Since the co-located interleaving is replaced by the line corresponding to the above equation (12), the LDPC decoding unit 56 does not need to perform the line replacement of the equation (12). Therefore, in the receiving apparatus 12 of Fig. 134, the LDPC decoding unit 56 is supplied with the 133671.doc -247-200947881 LDPC code which is not subjected to the co-interverse deinterlacing, as described above, from the vertical twist reverse deinterleaver 55, that is, the supply has been performed. The LDPC code in the state of the line replacement of the equation (12) is processed by the LDPC decoding unit 56 in the same manner as the decoding device of Fig. 139 except that the line replacement of the equation (12) is not performed. That is, Fig. 140 shows an example of the configuration of the LDPC decoding unit 56 of Fig. 134. In FIG. 140, the LDPC decoding unit 56 is configured similarly to the decoding device of FIG. 139 except that the received data rearrangement unit 310 of FIG. 139 is not provided, and the line replacement is performed without the equation (12), and FIG. Since the decoding apparatus performs the same processing, the description thereof will be omitted. As described above, since the LDPC decoding unit 56 is not provided with the received data rearrangement unit 310 ©, the decoding apparatus of FIG. 139 can be reduced in size. In addition, in FIGS. 136 to 140, in order to simplify the description, the code length N of the LDPC code is set to 90, the information length K is set to 60, and the number of rows of the loop structure (the number of columns and the number of rows of the matrix) P The number q (=M/P) of the same length is set to 6, but the code length Ν, the information length Κ, the number of rows of the loop structure unit P, and the number q (=M/P) are not limited. Above the above values. That is, in the transmitting apparatus 11 of Fig. 8, the LDPC encoding section 21 outputs, for example, a line in which the code length N is set to 64800 or 16200, and the information length K is set to N-¥Pq (=NM), and the loop structure is performed. The number P is set to 360, and the divisor q is set as the LDPC code of Μ/P. However, the LDPC decoding unit 56 of FIG. 140 takes the LDPC code as the object and performs P check node operations and variable node operations simultaneously. It can also be applied in the case of performing LDPC decoding. Then, the series of processes described above can be performed by hardware or by software. When a series of processing is performed by software, the program constituting the software is installed in a general-purpose computer or the like. 133671.doc -248 - 200947881 Therefore, Fig. 141 is a diagram showing an example of a configuration in which one of the computers having the program for executing the above-described series of processes is installed. The program can be recorded in advance on a hard disk 705 or ROM 703 built in the computer as a recording medium. Alternatively, the program can be temporarily or permanently stored (recorded) on a floppy disk or CD-ROM (Compact Disc Read Only Memory). A portable recording medium 711 such as a read-only memory, a MO (Magneto Optical) disc, a DVD (Digital Versatile Disc), a magnetic disc, or a semiconductor memory®. This type of portable recording medium 711 can be provided as a so-called package software. In addition, the program is installed in the portable recording medium 711 as described above to the computer, and can be wirelessly transmitted to the computer via the LAN (Local Area Network) via the artificial satellite for digital satellite broadcasting from the download page. The network of the Internet is transmitted to the computer by wire, and the program transmitted by the communication unit 708 is received by the computer 708 and installed on the built-in hard disk 705.

The CPU has a built-in CPU (Central Processing Unit) 702. In the CPU 702, an input/output interface 710 is connected via the bus bar 701, and an input unit 707 composed of a keyboard, a mouse, a microphone, or the like is operated by the user via the input/output interface 710, and an instruction is input. The 1J CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance therewith. Alternatively, the CPU 702 is a program stored on the hard disk 705, transmitted from the satellite or the network, and received by the communication unit 708 and installed on the hard disk 705, or loaded from the disk drive 709. 133671.doc -249 - 200947881 The recording medium 711 is read and installed on the hard disk 705, and is loaded into a RAM (Random Access Memory) 704 and executed. Thereby, the CPU 702 performs the processing according to the above-described flowchart or the processing performed by the above-described block diagram. Then, the CPU 702 outputs the processing result from the output unit 706 composed of an LCD (Liquid Crystal Display) or a speaker or the like via the input/output interface 710 as necessary, or transmits it from the communication unit 708, and further makes It is recorded on the hard disk 705 and the like. Herein, the processing steps of the program for causing the computer to perform various processes are described in the present specification, and it is not necessary to process them in time series in the order described in the flowchart, and also includes processing performed in parallel or individually (for example, Parallel processing or processing according to the object). Moreover, the program can be processed by one computer or distributed by a plurality of computers. Further, the program can also be transferred to a remote computer for execution. Next, the processing of LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11 will be further explained. w For example, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and 8/9. 133671.doc • 250- 200947881 The LDPC encoding unit 21 is an LDPC with a code length N of 64800 bits or 16200 bits, according to a check matrix 准备 prepared per code length N and per code rate. The code is encoded (missing correction code). In other words, the LDPC encoding unit 21 stores the check matrix initial value table to be described later, based on the code length and the coding rate. Here, in the specification of DVB-S.2, as described above, there are two kinds of code lengths of 64800 bits and 16200 bits, and 11 codes are respectively specified for the LDPC code with a code length of 64800 bits. The rate is about 10 encoding rates for an LDPC code having a code length N of 〇16,200 bits. Therefore, when the transmitting apparatus 11 is a device that performs processing according to the specifications of DVB-S.2, the LDPC encoding unit 21 stores an LDPC code having a code length N of 64,800 bits, which corresponds to the check of 11 encoding rates. The matrix initial value table and the LDPC code having a code length N of 16,200 bits respectively correspond to a check matrix initial value table of 10 coding rates. The LDPC encoding unit 21 sets the code length N and the encoding rate r of the LDPC code based on, for example, the operation of the operator. Here, the code length N and the code rate r' set by the LDPC encoding unit 21 are also referred to as a set code length N and a set code rate r, respectively. The LDPC encoding unit 2 1 corresponds to the information length K (=Nr=code length N - according to the set code length N and the set coding rate r according to the check matrix initial value table corresponding to the set code length N and the set coding rate r. The element of the information matrix HA of the same length M) is arranged in the row direction every cycle of 360 rows (the number of rows of the cycle structure), and a check matrix is generated. Then, the LDPC encoding unit 21 extracts the information bits of the information length κ from the image data 133671.doc - 251 - 200947881 supplied to the transmitting device 11 as the target data of the transmission target. Further, the LDPC encoding unit 21 calculates a code word (LDPC code) of one code long by calculating the parity bit of the information bit based on the check matrix Η. That is, the LDPC encoding unit 21 sequentially calculates the parity bits of the code word ^ which conforms to the following equation.

HcT = 于此 In the above equation, C denotes a column vector as a codeword (LDPC code), and CT denotes a transposition of the column vector C. As the column vector of the LDPC code (1 codeword) (in the case where the column vector 八 represents the portion of the information bit, and the column vector τ represents the portion of the parity bit, the column vector c can be used as the information bit The column vector A and the column vector T as the parity bits are represented by the formula C=[A|T]. Moreover, the check matrix Η can be represented by the portion of the code bit of the LDPC code corresponding to the information bit. The information matrix Ηα and the co-located matrix Ητ corresponding to the co-located bit are expressed as the formula Η=[Ηα|Ητ] (the elements of the information matrix Ηα are set to the left side element, and the elements of the parity matrix Ητ are set as the matrix of the right side element) Further, for example, in the specification of DVB_S 2, the parity matrix Ητ of the check matrix H=[HA|HT] becomes a ladder structure. The check matrix Η and the column vector c=[A|T] as the LDPC code must conform to the equation.

(In the case of the element, the first column of the row vector Hct of the formula HcT=〇 is sequentially obtained by making the elements of the respective columns 〇. 133671 .doc -252- 200947881 The LDPC encoding unit 21 The information bit A finds the parity bit, and the code word c=[A|T] represented by the information bit and the parity bit is output as the L_D PC coding result of the training bit A. As described above, the LDPC encoding unit 21 stores the code matrix initial value table corresponding to each code length N and each code rate r, and sets the L·DPC code of the code rate R of the code length N to be used from the history. The length N and the check matrix 生成 generated by the check matrix initial value table corresponding to the history of the stone are measured. The check matrix initial value table will check the matrix 对应 corresponding to the LDPC code® (by checking the matrix) The code length of the LDPC code defined by Η) and the information of the coding rate r. The position of the element of the information matrix Ha of 1 is expressed in units of 360 lines (the number of rows of the cyclic structure). The code length N and the check matrix of each coding rate r are prepared one by one. Figure 142 to Figure 187 show the inclusion of DVB-S.2. The check matrix initial value table specified by the grid is used to generate a check matrix initial value table of various check matrices. That is, the graph 142 indicates that the code length Ν is 16200 bits as defined by the specification of DVB-S.2. The check matrix initial value table of the check matrix 编码 with the coding rate r of 2/3. Fig. 143 to Fig. 145 show the coding rate r of the code length Ν 64800 bits specified by the specification of DVB-S.2 is 2/ In addition, Figure 144 is a diagram subsequent to Figure 143, and Figure 145 is a diagram subsequent to Figure 144. Figure 146 shows the code for DVB-S.2. Long Ν is 133671.doc -253 - 200947881 16200-bit code rate r is 3/4 check matrix 检查 check matrix initial value table. Figure 147 to Figure 150 shows the specifications of DVB-S.2 for The code length Ν is 64800 bits, and the code rate r is 3/4 of the check matrix 检查 check matrix initial value table. Further, 'Fig. 148 is continued from Fig. 147, and Fig. 149 is continued from Fig. 148. Figure 150 is taken as a diagram of Figure 149. Figure 151 is a diagram showing the specification of DVB-S.2 for a code length ν of 16,200 bits. Rate!^ is 4/5 check matrix 检查 check matrix initial value table 0 Figure 152 to Figure 155 shows that the code rate r is 64800 bits for the code rate r specified by the specification of DVB-S.2 is 4/ The check matrix initial value table of the check matrix of 5. The graph 153 is continued from the graph of FIG. 152, and the graph 154 is continued from the graph of FIG. Moreover, FIG. 155 is continued from the diagram of FIG. Figure 156 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 16200 bits with a code length of 5/6 as defined by the specification of DVB-S.2. Fig. 157 to Fig. 160 are diagrams showing the check matrix initial value table of the check matrix 编码 of the coding rate Γ of 64/800 with a code length 64 of 64/800 as defined by the specification of DVB_S.2. Further, Fig. 158 is continued from Fig. 157, and Fig. 159 is attached to the figure. Moreover, diagram 160 is continued from the diagram of FIG. Figure 161 is a table showing the initial value of the check matrix of the check matrix 码 for the code length 1336*71 .doc -254- 200947881 16200 bits with a coding rate r of 8/9 as defined by the specification of DVB-S.2. Fig. 162 to Fig. 165 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length r of 64,800 bits and the code rate r of 8/9 as defined by the specification of DVB-S.2. In addition, FIG. 163 is continued from FIG. 162, and FIG. 164 is continued from FIG. Moreover, Figure 165 is continued from the diagram of Figure 164. Fig. 166 to Fig. 169 show the check matrix initial value table of the check matrix 对于 for the code length 〇 Ν 64800 bits with a code length r of 9/10 as defined by the specification of DVB-S.2. In addition, FIG. 167 is continued from FIG. 166, and FIG. 168 is continued from FIG. Moreover, Figure 169 is continued from the diagram of Figure 168. Fig. 170 and Fig. 171 show the check matrix initial value table of the check matrix 编码 for the coding rate r of 64800 bits with a code length Ν defined by the specification of DVB-S.2. In addition, FIG. 171 is continued from the diagram of FIG. Fig. 172 and Fig. 173 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length 64 64800 bits as defined by the specification of DVB-S.2. In addition, FIG. 173 is continued from the diagram of FIG. Fig. 174 and Fig. 175 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length 64 of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 175 is continued from the diagram of FIG. 133671.doc -255 - 200947881 Figure 176 to Figure 178 show the check matrix initial value table of the check matrix η for the code rate N of 64800 bits with a code length N of 1/2 as defined by the specification of DVB-S.2. . Further, Fig. 177 is continued from Fig. 176. Fig. 178 is continued from Fig. 177. Fig. 179 to Fig. 181 show the check matrix initial value table of the check matrix 对于 for the code length Ν 64800 bits as defined by the specification of DVB-S.2. In addition, FIG. 180 is continued from FIG. 179, and FIG. 181 is continued from FIG. Figure 182 is a table showing the initial value of the check matrix of the check matrix η for the code rate ν of 16200 bits and the check matrix η of 丨/4 as defined by the specification of DVB-S.2. Fig. 183 is a table showing the initial value of the check matrix of the check matrix η for the coding rate 1_ of the code length ν of 16,200 bits as defined by the specification of DVB_S.2. Fig. 184 is a table showing the initial value of the check matrix of the check matrix η for the coding rate 1_ of the code length N of 16200 bits as defined by the specification of DvB-S_2. Fig. 185 is a table showing the initial value of the check matrix of the check matrix η for the coding rate 1_ of the code length ν of 16,200 bits as defined by the specification of Dvb_s.2. Figure 186 is a table showing the initial value of the check matrix η of the check matrix η for the code length ν of 16200 bits, which is specified by the specification of DvB_S 2 , 133671.doc - 256 - 200947881. Fig. 187 is a table showing the initial value of the check matrix of the check matrix H for the coding rate 3/5, which can be used in place of the check matrix initial value table of Fig. 186, with a code length N of 16,200 bits. The LDPC encoding unit 21 of the transmitting device 11 uses the inspection matrix initial value table to obtain the inspection matrix 以下 as follows. That is, Fig. 188 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. Further, the check matrix initial value table of FIG. 188 indicates a check matrix of the check matrix η having a code length ν of 16,200 bits and a code rate r of 2/3 as specified in the specification of DVB-S.2 shown in FIG. Initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix ΗΑ1 according to the code length Ν of the LDPC code and the coding rate r, every 360 lines (the number of rows of the loop construction unit) ρ) indicates the list of the number of the elements in the 1st column of the l+36〇x(il) of the check matrix 第 (the number of the column in the first column of the check matrix is set as the column) The number) is only the number of rows of weights that the row of the l + 36〇x(il) line has. In this case, the parity matrix 对应τ corresponding to the co-located long Μ is formed into a stepped structure, which is determined in advance. The information matrix 对应 corresponding to the information length K in the inspection matrix 可 can be obtained from the inspection matrix initial value table ’. Check the number of columns in the matrix initial value table k + Ι is different depending on the information length. The relationship between the information length K and the check matrix initial value table k + ,, the relationship of the following formula holds. 133671.doc -257· 200947881 K=(k+l)x360 Here, 360 of the above formula is the number of rows p of the unit of the loop structure. In the check matrix initial value table of Fig. 18, there are 13 values arranged from the 1st column to the 3rd column, and three values are arranged from the 4th column to the k+th column (the 30th column in Fig. 188). Therefore, the row weight of the check matrix η obtained from the check matrix initial value table of Fig. 188 is from the 1st line to the 1+36〇χ(3-1)·1 behavior 13 from the 1+36 (^ (3-1) Go to Behavior [3] The first column of the check matrix initial value table of Figure 188 is 〇, 2084, 1613, ❹ 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the inspection matrix ,, and the elements of the column numbers 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are 1 (and The other elements are 0). Moreover, the second column of the check matrix initial value table of FIG. 188 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 43 58 and 3108. Indicated in the 361th (= 1+ 〇 36 〇χ (2-1)) row of the inspection matrix η, the column numbers are 1, 122, 1516, 3448, 288 〇, 1407, 1847, 3799, 3529, 373, 971, The elements of 4358 and 3108 are 1. As above, the check matrix initial value table will check the position of the elements of the information matrix 11 of the matrix 以1 every 360 rows. Check the matrix l+36〇x (il The line other than the line, that is, from line 2 + 36〇x(i_l) to line 36〇xi, will be checked by the initial value of the matrix 133671.doc -258- 200947881 The element of 〇x(il) line 1 is cyclically shifted according to the direction of the same length M (downward direction of the line). That is, for example, the 2+36〇x(il) line will be Dijon + 邗 (10) 屮丨) The line is only cyclically shifted by M/360 (=q), and then the 3+36〇x(M) line is down from the l+36〇x(il) line. The direction is only cyclically shifted by 2xM/36〇 (=2xq) (the second 2+36〇x(il) line is only cyclically shifted by M/36〇(=q)). Now, if the value of the jth row (the jth from the left) of the third column (the first one from the top) of the check matrix initial value table is expressed as hi, j, and the matrix W is checked. The number of the first element of the line is indicated as the bar code, and the number of the element of the first comment line of the line other than the 1+360><〇1) line of the matrix 11 is checked. It can be obtained by the following formula.

Hw_j=mod {hi,j+mod((w - l),P)xq,M) Here, mod(x,y) means dividing y by the remainder of χ. Further, ρ is the number of rows of the above-described loop structure, for example, the specification of dvb·S.2 is 360. Further, the value M/36 获得 obtained by dividing the parity length μ by the number of rows P (= 360) of the loop configuration is used. The LDPC encoding unit 21 specifies the column number of the element of the first +360><(丨-1) line of the check matrix 11 by checking the matrix initial value table. Further, the LDPC encoding unit 21 obtains the column number Η of the element after the wth row of the row other than the 1+360x0-!) line of the inspection matrix 11, and generates the column number obtained by the above. The element is set as the inspection matrix 丨. Next, the description will be given of the replacement of the code bits of the LDpc code by the replacement unit 32 of the demultiplexer 25 of the transmitting device (4), that is, the code bit of the LDPC code and the symbol bit of the symbol. The change pattern of the yuan (also known as the bit allocation mode under 133671.doc -259- 200947881). In the demultiplexer 25, the code bits of the LDPC code are written in the wale direction of the memory 3 1 in the direction of the X direction of the X direction (N/(mb)) x (mb) bits, and thereafter Read in the horizontal direction in mb-bit units. Further, in the demultiplexer 25, the replacement bit 32 is replaced with the code bit of the mb bit read in the course direction of the memory 31, and the replaced code bit becomes (continuous) b symbols. The oct bit of the mb bit. That is, the replacing unit 32 counts the i+th bit from the most significant bit of the code bit of the mb bit read from the course direction of the memory 3 as the code bit ©, and will (Continuously) the most significant bit of the mb bit of the b-bit symbol, the i+th bit is calculated as the symbol bit yi, and the code of the mb bit is replaced according to the specific bit allocation pattern. Bits bG to bmn. Figure 1 89 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 5/6 or 9/10. The further modulation mode is 4096QAM, and the multiple b is 1 An example of a meta-allocation model. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The further modulation method is 4096QAM, and the multiple b is 1 in the case of V, in the multiplexer 25, The memory bit written by the memory 31 in the wale direction X direction (64800/(12x1)) χ (12x1) bits is in the horizontal direction, and is read in units of 12xl (= mb) bits, and It is supplied to the replacement unit 32. The replacing unit 32 is configured to b) the code bit b from the 12x1 (= mb) bit read from the memory 31 to b丨! Replace the 12x1 (= mb) bit code bits with the 12X 1 (= mb) bit symbol bits y 〇 〇 to yn as shown in Figure 189. bG to bn. 133671.doc -260- 200947881 That is, according to FIG. 189, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and a coding rate of 9/10. For the LDPC code, for any LDPC code, respectively, the code bit b〇 is assigned to the symbol bit y8, the code bit b! is assigned to the symbol bit y〇, and the code bit b2 is assigned to the symbol. Meta-bit y6, assigning code bit b3 to symbol y!, assigning code bit b4 to symbol y4, and assigning code bit b5 to symbol y5, the code bit B6 is assigned to symbol bit y2, code bit b7 is assigned to symbol bit y3, code bit b 8 is assigned to symbol bit y 7, and code bit b9 is assigned to symbol bit y 1 〇, assign the code bit b! 〇 to the symbol y! 1, and assign the code bit b! 1 to the symbol y 9, and replace it. Figure 190 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The bit modulation can be used in the case where the modulation mode is 4096QAM and the multiple b is 2. An example of a pattern. The LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the traversing. The code bit written in the memory 31 in the direction X direction of the (64800/(12χ2)) χ (12χ2) bit is in the course direction, is read in units of 12x2 (= mb) bits, and is supplied to Replacement section 32. 133671.doc -261 - 200947881 The replacement unit 32 is configured to allocate the code bits b to 12 from the 12x2 (= mb) bits of the memory 31, and assign them to consecutive 2 (= b) characters as shown in FIG. The 12-bit (= mb)-bit symbol bits y 〇 y y 23 are replaced by the 12-bit (= mb)-bit code bits bG to b23. That is, according to FIG. 190, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and an LDPC code having a coding rate of 9/10. An LDPC code is respectively assigned: a code bit b〇 is assigned to the symbol bit ys, a code bit b2 is assigned to the symbol bit y〇, and a code bit b4 is assigned to the symbol bit y6, and the code bit is The element b6 is assigned to the symbol bit y 1, the code bit b8 is assigned to the symbol bit y4, the code bit b! 〇 is assigned to the symbol bit y 5 , and the code bit b! 2 is assigned to the symbol Meta-bit y 2, assign code bit b! 4 to symbol bit y 3, assign code bit b! 6 to symbol bit y 7, assign code bit b! 8 to symbol bit The element y 1 〇, the code bit b2G is assigned to the symbol bit y 11, the code bit b22 is assigned to the symbol bit y9, and the code bit b is assigned to the symbol bit y2 〇, the code bit is Element b3 is assigned to symbol bit y 12, code bit b5 is assigned to symbol bit y 18, code bit b7 is assigned to symbol bit y 13, and code bit b9 is assigned to symbol bit Y 16, 133671.doc -262- 200947881 Assign the code bit b η to the symbol bit y! 7, put the code The element b 13 is assigned to the symbol bit y 14, the code bit b 15 is assigned to the symbol bit y 15 '. The code bit b! 7 is assigned to the symbol bit y] 9, and the code bit bi 9 Assigned to the symbol bit y22, the code bit b21 is assigned to the symbol bit y23, and the code bit b 2 3 is assigned to the symbol bit y 2 1 ' for replacement. Here, the bit allocation pattern of Fig. 190 is a bit allocation pattern of Fig. 189 in the case where the multiple b is directly used. That is, in FIG. 190, the code bit elements b 〇, b2, · · ·, b22 are assigned to the symbol bit yi and the code bit element ·, and b23 is assigned to the symbol bit yi. The code bits bG to b! i of Fig. 189 are assigned in the same manner for the symbol bits yi. Figure 191 shows the modulation mode is 1024QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits, a coding rate of 3/4, 5/6 or 8/9, a multiple b of 2, and an LDPC code. It is an example of a bit allocation pattern that can be used in the case where the code length N is 64,800 bits, the coding rate is 3/4, 5/6, or 9/10, and the multiple b is 2. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, 5/6 or 8/9. In the case where the modulation mode is 1024QAM and the multiple b is 2, the multiplexer 25 is used. The memory bit written in the memory 31 of the (16200/(1 〇χ2)) χ (10x2) bit in the X direction of the wander direction is in the course direction, with l〇x2 (= mb) bits. The unit is read out and supplied to the replacement unit 32 〇 133671.doc -263- 200947881 Moreover, the LDPC code is an LDPC code having a code length N of 64800 bits 编码 and a coding rate of 3/4, 5/6 or 9/10. When the modulation method is 1024QAM and the multiple b is 2, the memory multiplexer 25 is in the memory direction 31 in the direction of the X direction (64800/(1〇χ2)) 10 (10×2) bits. The written code bits are read in the course direction, read in units of l〇x2 (= mb) bits, and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits b to b19 read from the l〇x2 (= mb) bits of the memory 31, as shown in FIG. 191, to l连续x2 of consecutive 2 (=b) symbols. (= mb) The way of the bit yQ to y19 of the bit is to replace the code bit 1?() to 1^9 of the ® 1 〇 x2 (= mb) bit. That is, according to FIG. 191, the replacing unit 32 is an LDPC code having an encoding rate of 3/4 in an LDPC code having a code length N of 16,200 bits, an LDPC code having a coding rate of 5/6, and a coding rate of 8/. An LDPC code of 9 and an LDPC code having a coding rate of 3/4 in an LDPC code having a code length N of 64,800 bits, an LDPC code having a coding rate of 5/6, and an LDPC code having a coding rate of 9/10, Regarding any LDPC code, respectively: 分配 assigning the code bit bQ to the symbol bit y8, assigning the code bit b! to the symbol bit y3, and assigning the code bit b2 to the symbol bit y7, The code bit b3 is assigned to the symbol bit y!〇, the code bit b4 is assigned to the symbol bit y 19, the code bit b 5 is assigned to the symbol bit y4, and the code bit b6 is assigned to the symbol Meta-bit y9, assigning code bit b7 to symbol bit y5, 133671.doc -264- 200947881 assigning code bit b8 to symbol bit y 17, assigning code bit b9 to symbol bit Y6, assigning the code bit b 1 〇 to the symbol bit y 14, assigning the code bit b 11 to the symbol bit y 11 ' assigning the code bit b! 2 to the symbol bit y2, the code Bit b is assigned to symbol element y丨8, and code bit b! 4 is assigned to symbol Bit y 1 6, assign code bit b! 5 to symbol y! 5, ® assign code bit b! 6 to symbol y 〇, assign code bit b 丨 7 to symbol The meta-bit y 1, the code bit b] is assigned to the p-bit yi 3, and the code bit b 19 is assigned to the p- y 12' for replacement. Figure 192 shows that the modulation mode is 4096QAM, and the LDPC code is an LDPC code with a code length N of 16,200 bits, a coding rate of 5/6 or 8/9, a case where the multiple b is 2, and the LDPC code is a length N. An example of a bit allocation pattern that can be used in the case of a 64800-bit LDPC code having a coding rate of 5/6 or ^9/10 and a multiple b of 2. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6 or 8/9. In the case where the modulation method is 4096Q AM and the multiple b is 2, the multiplexer 25 is used in the multiplexer 25 The code bits written in the memory 31 in the row direction X direction of the (16200/(12χ2))χ(12χ2) bit are in the course direction, read out in 12x2 (=mb) bit units, and supplied To the replacement unit 32. Moreover, the LDPC code is a Ma Chang N of 64,800 bits, a coding rate of 5/6 or 133671.doc -265 - 200947881 9/10 of 1^卩 (: code, further modulation is 4096 () eight] ^, In the case where the multiple 1» is 2, in the demultiplexer 25, the code bit written in the memory 31 in the direction of the x direction of the x direction (64800/(12χ2)) χ (12x2) bit is attached to The course direction is read out in units of 12x2 (= mb) bits and supplied to the replacement unit 32. The replacement unit 32 is to read the code bits bQ to b23 of 12x2 (= mb) bits from the memory 31, Replace the 12><2(=mb) bits by assigning the symbol bits y〇 to y23 of 12x2 (= mb) bits of consecutive 2 (=b) symbols as shown in FIG. The code bits bG to b23. That is, according to FIG. 192, the replacement unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC having a coding rate of 8/9 in an LDPC code having a code length N of 16,200 bits. The code, and the LDPC code with a coding rate of 5/6 and the LDPC code with a coding rate of 9/10 in the LDPC code with a code length N of 64,800 bits are respectively related to any LDPC code: 〇 is assigned to the symbol y 1 〇, the code bit b! is assigned to the symbol y 15, and the code bit b2 Assigning the symbol bit y4, assigning the code bit b3 to the symbol bit y! 9, assigning the code bit b4 to the symbol bit y21, and assigning the code bit b5 to the symbol bit y 16, 16 The code bit b6 is assigned to the symbol bit y23, the code bit b7 is assigned to the symbol bit y 18, the code bit b8 is assigned to the symbol bit y 11, and the code bit b9 is assigned to the symbol bit Yuan y 14, 133671.doc -266- 200947881 assigns the code bit b! 〇 to the symbol bit y22, assigns the code bit b π to the symbol bit y 5 ' assigns the code bit b! 2 to The symbol bit y6 assigns the code bit b 13 to the symbol bit y 17 ', assigns the code bit bi 4 to the symbol bit y 1 3 , and assigns the code bit b 15 to the symbol bit y 2 〇, assigning the code bit b ! 6 to the symbol bit y 1, assigning the code bit bi 7 to the symbol bit y3,

The code bit b! 8 is assigned to the symbol bit y9, the code bit bi 9 is assigned to the symbol bit y2, the code bit b2G is assigned to the symbol bit y7, and the code bit b21 is assigned to the symbol The bit ys, the code bit b22 is assigned to the symbol bit y 1 2 , and the code bit b23 is assigned to the symbol bit y 〇 for replacement. According to the bit allocation pattern shown in FIG. 189 to FIG. 192, the same bit allocation mode can be adopted for the LDPC code of the plural type, and any one of the LDPC codes of the plural type can make the fault tolerance for the error become Required performance. That is, Figs. 193 to 196 show simulation results of BER (Bit Error Rate) in the case where the replacement processing is performed in accordance with the bit allocation pattern of Figs. 189 to 192. Further, in Figs. 193 to 196, the horizontal axis represents Es/N 〇 (signal power to noise power ratio per symbol), and the vertical axis represents BER. -267- 133671.doc 200947881 Moreover, the solid line indicates the BER in the case where the replacement processing has been performed, and the one-dot chain indicates the BER in the case where the replacement processing is not performed. Figure 193 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. 4096QAM is used as the modulation method, and the multiple b is set to 1, and is replaced according to the bit allocation pattern of FIG. BER in the case of processing. Figure 194 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. 4096QAM is used as the modulation method, and the multiple b is set to 2, and the replacement processing is performed according to the bit allocation pattern of FIG. In the case of ® BER. Further, in FIGS. 193 and 194, a graph with a triangular mark indicates a BER with respect to an LDPC code having a coding rate of 5/6, and a graph with a star mark (star mark) indicates that the coding rate is 9/10. The BER of the LDPC code. Figure 195 shows an LDPC code and a code length N of 64800 for a code length N of 16200 and a coding rate of 3/4, 5/6, and 8/9, respectively, and encoding rates of 3/4, 5/6, and 9/, respectively. The LDPC code of 10 uses 1024QAM as the modulation method, and the multiple b is set to 2, and the BER under the case of replacement processing according to the bit allocation pattern of FIG. Further, in FIG. 195, a graph attached with a star indicates a BER with respect to an LDPC code having a code length N of 64800 and a coding rate of 9/10, and a graph with an upward triangular mark indicating that the code length N is 64,800. The BER of the LDPC code with a coding rate of 5/6. Further, a graph with a square mark indicates a BER with respect to an LDPC code having a code length N of 64,800 and a coding rate of 3/4. Further, in FIG. 195, a graph with a circle mark indicates a BER of an LDPC code having a code length N of 16200 and a coding rate of 8/9, and a triangle mark with a downward direction attached thereto, 133671.doc-268-200947881 The graph shows the BER of the LDPC code with a code length N of 16200 and a coding rate of 5/6. Moreover, the graph with the positive sign is not related to the BER of the LDPC code having a code length N of 16200 and a coding rate of 3/4. Figure 196 shows an LDPC code with a code length N of 16200, a coding rate of 5/6 and 8/9, and an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. The mode adopts 4096QAM, and the multiple b is set to 2, and the BER in the case of performing the replacement processing according to the bit allocation pattern of FIG. In addition, in Fig. 196, a graph with a star indicates the BER of the LDPC code with a code length N of 64800 and a coding rate of 9/10, and a graph with an upward triangular mark indicates that the code length N is 64800, BER of the LDPC code with a coding rate of 5/6. Moreover, in FIG. 196, a graph with a circle mark indicates a BER with respect to an LDPC code having a code length N of 16200 and an encoding rate of 8/9, and a graph with a downward triangular mark indicating that the code length N is 16,200. The BER of the LDPC code with a coding rate of 5/6. ❹ According to FIG. 193 to FIG. 196, the same bit allocation mode can be adopted for the LDPC code of the plural type, and the fault tolerance for the error can be made with respect to any of the LDPC codes of the plural types using the same bit allocation mode. Required performance. In other words, when a plurality of types of LDPC codes having different code lengths or coding rates are used, and the bit allocation mode dedicated to the LDPC code is used, the error tolerance is extremely high, but different types must be used. The LDPC code changes the bit allocation pattern one by one. 133671.doc -269· 200947881 On the other hand, according to the bit allocation pattern of FIG. 189 to FIG. 192, the same bit allocation mode can be adopted for each of the plural types of LDPC codes having different code lengths or encoding rates, and regarding the plural type For each of the LDPC codes, it is not necessary to change the bit allocation pattern one by one for different types of LDPC codes as in the case of using the bit allocation pattern dedicated to the LDPC code. Further, according to the bit allocation pattern of FIG. 189 to FIG. 192, for each of the plural types of LDPC codes, even if the bit allocation mode dedicated to the LDPC code is slightly used, even if this is still possible, the error can be made. Fault tolerance is high performance. ®, that is, for example, in the case of a modulation mode of 4096QAM, for an LDPC code having a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively, any LDPC code can be used as shown in FIG. The same bit allocation mode of 190. Then, even with the same bit allocation mode, fault tolerance for errors can be made high performance. Further, for example, when the modulation mode is 1024Q AM, the code length N is 16200, the coding rate is 3/4, 5/6, and 8/9 LDPC codes, and the code length N is 64800, and the code is The rates are 3/4, 5/6, and 9/10 LDPC codes, respectively. V, the same bit allocation pattern of Figure 191 can be used for any LDPC code. Then, even with the same bit allocation mode, fault tolerance for errors can be made high performance. Moreover, for example, in the case where the modulation mode is 4096QAM, the LDPC code having a code length N of 16200 and a coding rate of 5/6 and 8/9, respectively, and a code length N of 64800 and a coding rate of 5/6 and 9 respectively. For the LDPC code of /10, the same bit allocation pattern of Figure 192 can be used for any LDPC code. Then, as in 133671.doc • 270- 200947881, even with the same bit allocation mode, fault tolerance for errors can be made south. Further explanation of the change in the bit allocation pattern. Figure 197 is a diagram showing the coding rate of the LDPC code defined by the check matrix 生成 generated by the check matrix initial value table shown in Figs. 142 to 187, where the LDPC code is a code length N of 16,200 or 64,800 bits. An example of a bit allocation pattern that can be used in the case where the LDPC code other than 3/5 is further modulated by QPSK and the multiple b is 1. ® LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate other than 3/5. In the case where the modulation method is QPSK and the multiple b is 1, the multiplexer 25 is used in the traversing. The code direction written by the memory 31 in the direction X direction of the (Ν/(2χ1)) χ (2x1) bit is in the course direction, is read in 2xl (= mb) bit units, and is supplied to Replacement section 32. The replacing unit 32 is configured to assign the code bits 1) and b! read from the 2x1 (= mb) bits of the memory 31 to 2x1 (= mb) of 1 (= b) symbols as shown in FIG. The bitwise symbol y〇 and yi of the bit are substituted for the code bits 〇 b〇 and hh of the 2>l(=mb) bits. That is, according to Fig. 197, the replacing unit 32 assigns the code bit bG to the symbol bit y 〇 and assigns the code bit b 1 to the symbol bit y!, respectively. In addition, in this case, it is also possible to consider not to replace, and the code bits ~ and !^ are directly used as the symbol bits yQ and y!, respectively. Figure 198 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5 of 133671.doc -271 - 200947881, and the modulation mode is 16QAM and the multiple b is 2. An example of a bit allocation pattern that can be employed. The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The memory element in which the X-direction is (Ν/(4χ2)) χ (4x2) bits is written in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to Replacement section 32. The replacing unit 32 assigns the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to the 4x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The meta-bits y〇 to y7 of the meta-elements replace the code bits b〇 to b7 of the 4<2(=mb) bits. That is, according to FIG. 1 98, the replacing unit 32 respectively assigns the code bit b〇 to the symbol bit y7, assigns the code bit b! to the symbol bit y!, and assigns the code bit b2. For the symbol bit y4, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y5, and the code bit b5 is assigned to the symbol bit y3, and the code bit is assigned B6 is assigned to the symbol bit y6, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Figure 199 shows that the modulation mode is 64QAM, and the LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5, and the bit allocation mode can be used when the multiple b is 2. example. 133671.doc -272 - 200947881 LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate other than 3/5. In the case where the modulation mode is 64QAM and the multiple b is 2, the multiplex is used. The memory element written in the memory 31 of the (Ν/(6χ2)) χ (6x2) bit in the wale direction X direction is in the horizontal direction, in units of 6x2 (= mb) bits. It is read out and supplied to the replacement unit 32. The replacing unit 32 is configured to assign the code bits bG to bu read from the 6 x 2 (= mb) bits of the memory 31 to 6x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bitwise bit yG to yn of the bit is substituted for the code bit b〇 to b!! of the 6<2(=mb) bit. That is, according to FIG. 199, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y 11, assigns the code bit bi to the symbol bit y7, and assigns the code bit b2 to the symbol. Bit y3, the code bit b3 is assigned to the symbol bit y], the code bit b4 is assigned to the symbol bit y6, the code bit b5 is assigned to the symbol bit y2, and the code bit b is 6 is assigned to the symbol bit y 9, the code bit b 7 is assigned to the symbol bit y 5 , the code bit b 8 is assigned to the symbol bit y ! , and the code bit b 9 is assigned to the symbol The bit y 8, the code bit b 1 〇 is assigned to the symbol bit y4, and the code bit b! 1 is assigned to the symbol bit y 〇 for replacement.

Figure 200 shows that the modulation mode is 256QAM, and the LDPC code is an LDPC code with a code length N 133671.doc -273 - 200947881 of 64800 bits and a coding rate of 3/5, and the multiple b can be used. An example of a bit allocation pattern. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is in the longitudinal direction and the horizontal direction is X. The code bits written in the memory 31 in the column direction of (64800 / (8 χ 2)) χ (8 χ 2) bits are in the course direction, read out in 8x2 (= mb) bit units, and supplied to the replacement portion 32. . The replacing unit 32 is configured to assign the code bits bQ to b15 read from the 8x2 (= mb) bits of the memory 31 to the 8x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The meta-bits 丫() to 3^5 of the meta-elements replace the code bits bG to b of the 8<2(=mb) bits. That is, according to the diagram 200, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y 15, assigns the code bit b! to the symbol bit y 1, and assigns the code bit b2 to The symbol bit y! 3, the code bit b3 is assigned to the symbol bit y3, the code bit b4 is assigned to the symbol bit y8, and the code bit b5 is assigned to the symbol bit yi! Bit b6 is assigned to symbol bit ys>, code bit b7 is assigned to symbol bit y5, code bit b8 is assigned to symbol bit y 1 〇, and code bit b9 is assigned to symbol bit Element y6, assign code bit b! 〇 to symbol bit y4, assign code bit b! 丨 to symbol bit y7, 133671.doc -274- 200947881 assign code bit b! 2 to character Meta-bit y 12, assigning code bit b 13 to symbol bit y 2 ' assigning code bit b! 4 to symbol bit y 14, assigning code bit b! 5 to symbol bit Y〇, and replace it. Fig. 201 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 3/5, and the bit b is 1 in the case where the multiple b is 1. The 〇LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation mode is 256QAM and the multiple b is 1, the multiplexer 25 is in the traverse direction X. The memory bit of the memory of the (16200/(8 X 1 )) χ (8 X 1) bit is written in the horizontal direction, in units of 8 X 1 (= mb) bits. It is read out and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits b to 8 from the 8 x 1 (= mb) bits of the memory 31 to 8 x 1 of the l (= b) symbols as shown in FIG. The mb) bit symbol yG to y7 is used to replace the 8 X1 (= mb) bit of the code bits 〇 b b to b7 〇, that is, according to FIG. 201, the replacement unit 32 respectively: The code bit bG is assigned to the symbol bit y7, the code bit b! is assigned to the symbol bit y3, the code bit b2 is assigned to the symbol bit y 1, and the code bit b3 is assigned to the symbol bit Element y5, assigning code bit b4 to symbol bit y2, assigning code bit b5 to symbol bit y6, 133671.doc -275 - 200947881 assigning code bit b6 to symbol bit y4, The code bit b7 is assigned to the symbol bit y〇 and replaced. Figure 202 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and an encoding rate of 3/5. Further modulation mode is QPSK, and the multiple b is 1. example. The LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5. When the modulation mode is QPSK and the multiple b is 1, the multiplexer 25 is in the traverse direction X. The direction of the course is (Ν/(2χ1))χ(2χ1). The code bits written by the memory 31 of the bit are in the horizontal direction, read in 2xl (= mb) bit units, and supplied to the replacement. Part 32. The replacement unit 32 is a code bit that will be read from the 2xl (= mb) bits of the memory 31. ^, as shown in FIG. 202, the code bits of the 2x1 (= mb) bits are replaced by the way of the symbol bits y 〇 and yi of the 2xl (= mb) bits of the l (= b) symbols. B〇 and h. That is, according to Fig. 202, the replacing unit 32 assigns the meta-bit bG to the symbol bit y, and assigns the code bit b! to the symbol y1, and replaces it. In addition, in this case, it is also possible to consider not to replace, and the code bits ~ and !^ are directly used as the symbol bits yG and yi, respectively. Figure 203 is a diagram showing an example in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a bit allocation pattern which can be employed in the case where the modulation method is 16QAM and the multiple b is 2. 133671.doc •276- 200947881 The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 3/5. In the case where the modulation mode is 16QAM and the multiple b is 2, the multiplexer 25 is used. The memory bit written in the memory direction 3 of the (64800/(4χ2)) χ(4χ2) bit in the wale direction X direction is in the course direction, and is read out in 4x2 (= mb) bit units. And supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bQ to b7 read from the 4x2 (= mb) bits of the memory 31 to 4 (= b) symbols of the following 2] < 2 ( =mb) The bit y of the bit. In the manner of y7, replace the code bits bQ to b7 of 4<2(=mb) ® bits. That is, according to FIG. 203, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, assigns the code bit b 1 to the symbol bit y5, and assigns the code bit to the symbol. Bit y 1, assign code bit b3 to symbol bit y2, assign code bit b4 to symbol bit y4, assign code bit b 5 to symbol bit y 7, and use code bit b 6 is assigned to the symbol bit y 3 , and the code bit b7 is assigned to the symbol bit y6 for replacement. Figure 204 shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and 7 〇 and a coding rate of 3/5. The bit modulation mode can be adopted in the case where the modulation mode is 16QAM and the multiple b is 2. example. The LDPC code is an LDPC code with a code length N of 1 6200 bits and a coding rate of 3/5. In the case where the modulation mode is 16QAM and the multiple b is 2, the solution is 133671.doc -277- 200947881 multiplexer 25 In the vertical direction, the memory of the (16200/(4χ2))χ(4χ2) bit is written in the horizontal direction, in the direction of 4 X2 (= mb) bits. It is read out and supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to 4 (= b) symbols of the following 2 as shown in Fig. 204 < 2 ( =mb) The way of the bit yG to y7 of the bit is substituted for the code bits bQ to b7 of the 4><2(=mb) bits. That is, according to FIG. 204, the replacing unit 32 respectively assigns the megabyte bG to the symbol y7, assigns the plaque b! to the symbol y1, and assigns the coder b2 to the symbol The meta-bit y4 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit y5, the code bit b5 to the symbol bit y3, and the code bit b6. To the symbol bit y6, the megabyte b7 is assigned to the symbol y 〇 and replaced. Figure 205 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a multiple of the bit allocation mode. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The direction is (64800/(6x2)) x (6x2: Hi memory 3 1 written code bits are in the horizontal direction, read in units of 6 χ 2 (= mb) bits 200947881 yuan, and supplied to replace Section 32. The replacing unit 32 is configured to allocate the code bits bQ to bn of the 6x2 (= mb) bits read from the memory 31 to 6x2 of the consecutive 2 (=b) symbols as shown in FIG. The mb) bit symbol y〇 to yn is replaced by the 6x2 (= mb) bit code bits bQ to b] 亦. That is, according to FIG. 205, the replacement unit 32 is respectively: The code bit b〇 is assigned to the symbol bit y2, the code bit b! is assigned to the symbol bit y 7, and the code bit 1?2 is assigned to the symbol bit y6, and the code bit b3 is allocated. For the symbol bit y9, the code bit b4 is assigned to the symbol bit y, the code bit b 5 is assigned to the symbol bit y3, and the code bit b6 is assigned to the symbol bit y丨, The code bit b7 is assigned to the symbol bit y8, and the code bit b 8 is assigned to the symbol bit y 4 The bit b9 is assigned to the symbol bit y 11, the code bit b! 〇 is assigned to the symbol bit y 5 , and the code bit b η is assigned to the symbol bit y! 〇, and is replaced. The modulation mode is 64QAM, and the LDPC code is an example of a bit allocation mode in which the code length N is 16200 bits and the coding rate is 3/5 LDPC code, and the multiple b is 2. The code length N is 16200 bits, and the coding rate is 3/5 LDPC code. If the modulation mode is 64QAM and the multiple b is 2, the solution is 133671.doc -279-200947881 multiplexer 25, in the vertical line. The code bit written in the memory 31 in the direction of the horizontal direction of the (16200/(6χ2))χ(6χ2) bit is in the horizontal direction, is read in units of 6x2 (=mb) bits, and is supplied to Replacement unit 32. The replacement unit 32 is configured to allocate the code bits b from the 6x2 (= mb) bits of the memory 31 to bn, and assign them to 6 (=b) symbols of the continuous symbol as shown in FIG. ; <2 (= mb) bit symbol y 〇 〇 to yn, to replace the 6 > 2 (= mb) bit of the code bit bQ to b!!. That is, according to In Fig. 206, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y 11, The code bit b 1 is assigned to the symbol bit y 7, the code bit b2 is assigned to the symbol bit y3, the code bit b3 is assigned to the symbol bit y 1 〇, and the code bit b4 is assigned to the symbol The bit y6 assigns the code bit b5 to the symbol y2, assigns the code bit b6 to the symbol ys>, assigns the code bit b7 to the symbol y5, and sets the code bit b8 Assigned to symbol bit y 1, assign code bit b9 to symbol bit y8, assign code bit b! 〇 to symbol bit y4, assign code bit b! 1 to symbol bit y 〇, and replace it. Figure 207 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a multiple of b can be used. 133671.doc -280- 200947881 LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 3/5. In the case where the modulation mode is 256QAM and the multiple b is 2, the multiplexer 25 is used. The code bits written in the memory 31 of the (64800/(8χ2)) χ (8χ2) bit in the wale direction X direction are in the horizontal direction and are read in 8x2 (= mb) bit units. And supplied to the replacement unit 32.

The replacing unit 32 is configured to allocate the code bits b to 8 from the 8x2 (= mb) bits of the memory 3 1 to 8 of consecutive 2 (= b) symbols as shown in FIG. 207; < 2 (= mb) bit symbol yQ to y15, to replace the 8x2 (= mb) bit mbit bG to b! That is, according to FIG. 207, the replacing unit 32 assigns the code bit bQ to the symbol bit y2, the code bit b! to the symbol bit y!!, and assigns the mbit b2 to The symbol bit y3 assigns the code bit b3 to the symbol bit y4, the code bit b4 to the symbol bit y〇, and the mbit b b to the symbol bit y 9, the code Bit b6 is assigned to symbol bit y!, code bit b7 is assigned to symbol bit y8, megabyte b8 is assigned to symbol bit y! 〇, and code bit b9 is assigned to symbol bit Element y! 3, assigning code bit b! 〇 to symbol bit y 7, assigning code bit b η to symbol bit y! 4, assigning code bit b! 2 to symbol bit Y6, assign the code bit b! 3 to the symbol y! 5, 133671.doc • 281 - 200947881 assign the code bit b ! 4 to the symbol y5, and assign the code bit bi 5 to the symbol The meta-bit y 12 is replaced. Figure 208 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and the bit b is 1 when the multiple b is 1. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 1, the multiplexer 25 is in the X direction in the wales. The memory bit written in the memory of the (16200/(8χ1))χ(8χ1) bit 3 1 is in the horizontal direction, read out in 8 X 1 (= mb) bit units, and supplied to the replacement. Part 32. The replacing unit 32 is configured to allocate the code bits b to 8 from the 8x1 (= mb) bits of the memory 31, and assign them to the 8x1 (= mb) bits of the l (= b) symbols as shown in FIG. The yuan symbol is y. In the manner of y7, the code bits b0 to b7 ° of 8 X 1 (= mb) bits are replaced, that is, according to FIG. 208, the replacing unit 32 respectively: assigns the code bit bG to the symbol bit y7 , the code bit b! is assigned to the symbol bit y 3 , the code bit b2 is assigned to the symbol bit y 1, the code bit b3 is assigned to the symbol bit y5, and the code bit b4 is assigned to The symbol bit y2 assigns the code bit b5 to the symbol bit y6, the code bit b6 to the symbol bit y4, and the code bit b7 to the symbol bit y〇, 13367J.doc - 282 - 200947881 and replaced. Next, the deinterleaver 53 constituting the receiving device 12 will be described. Figure 209 is a diagram for explaining the processing of the multiplexer 54 constituting the deinterleaver 53. That is, Fig. 209A shows an example of the functional configuration of the multiplexer 54. The multiplexer 54 is composed of a reverse replacement unit 1〇〇1 and a memory 1〇〇2. The multiplexer 54 performs the inverse replacement processing (replacement) of the replacement processing performed by the demultiplexer 25 corresponding to the transmitting device 作为, with the symbol bit supplied from the symbol of the demapping unit 52 of the previous stage as a target. Reverse processing of processing), that is, performing an inverse replacement process of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement process to the original position, and supplying the LDPC code obtained as a result to The slanting reverse deinterlacer 55 of the rear stage. That is, in the multiplexer 54, the inverse replacement unit 1〇〇1 supplies the symbol bits y, yi, · of the mb bits of the b symbols in units of (continuous) b symbols. · ·, ymb_]. The anti-replacement unit 1001 performs an arrangement in which the symbol bits y<) to ymb i of the mb bit are returned to the original mb bits of q, bi, · · · (on the side of the transmitting device 11) The replacement portion 32 of the multiplexer 25 is replaced by the inverse of the preceding code bits ～ 吣 ! ^, and the resulting code bits bo to bmbd of 2 mb bits are output. The memory 1002 is the same as the memory 31 constituting the demultiplexer 25 on the side of the transmitting device 11, and stores memory mb bits in the row (horizontal) direction and memorizes in the column (longitudinal) direction. Memory capacity of N/(mb) bits. That is, the 'memory 1002' is composed of mb vertical lines of memory N/(mb) bits; In the memory 1002, the anti-replacement unit 1〇〇1 is performed in the direction in which the code bits are read from the 133671.doc-283-200947881 S-resonant 31 of the demultiplexer 25 of the transmitting device 11. The writing of the code bit of the output LDPC code is performed in the direction in which the memory bit 3 is written in the memory 3, and the code bit written in the memory 1〇〇2 is read. That is, the multiplexer 54 of the receiving device 12, as shown in FIG. 2A and 9A, writes the code bits of the LDPC code outputted by the inverse replacement τ»卩1001 in the mb bit unit in the horizontal direction. It is carried out sequentially from the i-th column of the memory 1〇〇2 to the following. Then, if the writing of the code bit of 1 code long is finished, the code bit is read from the memory 1002 from the memory 1002 in the multiplexer G2, and supplied to the backward slant reverse deinterlacing. 55. Here, Fig. 209B shows a reading from the code bit of the memory 1〇〇2. The reading of the code bits of the multiplexer 54' LDPC code from the top to the bottom (the wale direction) of the memory 1() 〇2 is performed from the left to the right. Next, the processing of the whirling reverse deinterleaver 55 constituting the deinterleaver 53 of the receiving device 12 will be described with reference to FIG.曰 FIG. 21 shows an example of the structure of the memory 1 〇〇 2 of the multiplexer 54. The D-hidden body 1002 has a memory capacity of mb bits in the wale (longitudinal) direction and a memory capacity of N/(mb) bits in the horizontal (horizontal) direction, and is composed of a wales. The whirling torsion deinterlacer 55 is for the memory bank 1〇〇2, and controls the writing of the code bits of the LDpC code in the course direction and the reading in the wale direction to read 133671.doc -284·200947881 out position In this way, the longitudinal twist reverse deinterlacing is performed. Also, the vertical twist reverse deinterleaver 55 is adapted to appropriately change the start read position of the start code bit for the plurality of vertical lines, thereby performing the arrangement of the code bits rearranged by the vertical twist twist interleaving. To the original rearrangement of the arrangement. Here, Fig. 210 shows an example of the configuration of the memory 1002 in the case where the modulation method is 16QAM and the multiple b is 1. Therefore, the number of bits of the i-symbol is 4 〇 4 bits, and the memory of the memory 1 〇〇 2 is composed of 4 (= mb) wales. The longitudinal twist reverse deinterleaver 55 (instead of the multiplexer 54) sequentially shifts the code bits of the LDPC code outputted from the replacement unit 丨00丨 from the first column of the memory 1〇〇2 toward the following direction. Write. Then, if the writing of the code bit of 1 code long is finished, the whirling reverse deinterleaver 55 is a wales from the left to the right direction, and the code bit is moved from the memory 1002 from the top to the bottom (the wales) Read out of direction). The vertical twist reverse deinterleaver 55 writes the vertical twisting Q-turning error device 24 on the transmitting device u side to the start writing position of the code bit, as the starting reading position of the code bit, from the memory 1 〇 2 performs the reading of the code bits. That is, if the address of the position of the beginning (topmost) of each wales is set to 0', the address of each position in the walody direction is represented by an integer in ascending order, then the modulation mode is 16QAM and the multiple b is 1. In the case of the whirling reverse deinterleaver 55' with respect to the leftmost wales, the start reading position is set to the position where the address is ', and the second ide is started (from the left), and the read position is set as The position where the address is 2 'About the 3rd wales' will start the read position as the address where the address is 4'. Regarding the 4th ordinate, the start read position is set to the position where the address is 7. 133671.doc -285- 200947881 In addition, the beginning of the reading position is the position other than the position where the address is 0. After the reading of the code bit is performed to the lowest position, the image is returned to the beginning (the address is 〇 Position) 'Before the position before the start of the reading position. Sell. Then, the reading from the next (right) wales is performed thereafter. By performing the whirling de-interlacing as above, the arrangement of the code bits rearranged by the wobble interleaving will return to the original arrangement. Next, Fig. 211 is a block diagram showing another configuration example of the receiving device 12. In Fig. 2U, the receiving device 12 receives the data processing device from the modulation signal of the transmitting device 11, and is composed of a quadrature demodulating unit 51, a demapping unit 52, a reverse interleave 53 and an LDPC decoding unit 1021. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device n, performs quadrature demodulation, and supplies the obtained symbols (the values of the respective directions in the x-axis direction) to the demapping unit 52. The demapping unit 52 performs demapping of the symbols from the orthogonal demodulation unit 51 into code bits of the LDPC code, and supplies them to the deinterleaver 53. The deinterleaver 53 is composed of a multiplexer (MUX) 54, a vertical twist deinterleaver 55 © and a parity anti-parent 1011, and deinterleaves the code bits from the LDPC code of the demapping section 52. In other words, the 'multiple benefit 54 system performs the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing performed by the demultiplexer 25 of the transmitting device 11 as the object 'the LDPC code from the demapping unit 52'. That is, the inverse replacement processing of returning the position of the code bit replaced by the replacement processing to the original position is performed, and the LDPC code obtained as a result is supplied to the whirling reverse deinterlace 133671.doc - 286 - 200947881. The whirling torsional deinterlacer 55 takes the LDPC code from the multiplexer 54 as a target, and performs a whirling torsion which is performed by the whirling twist interleaver 24 of the transmitting device 11 as a rearrangement process. staggered. The LDPC code obtained as a result of the whirth reverse deinterlacing is supplied from the whirling reverse deinterleaver 55 to the parrot deinterleaver 1011. The paraxial deinterleaver 1011 performs the co-deverse interleaving of the co-interleaving performed by the co-located interleaver 23 of the transmitting device 11 with the code bit elements of the whirling and de-interlacing of the wander reverse deinterleaver 55 as objects. (Reverse processing of co-located interleaving), that is, performing parity de-interlacing of the code bits of the LDPC code arranged by the co-located interleave change back to the original arrangement. The LDPC code obtained as a result of the in-phase deinterlacing is supplied from the parrot deinterleaver 1011 to the LDPC decoding unit 1021. Therefore, in the receiving apparatus 12 of FIG. 211, the LDPC decoding unit 1021 is supplied with an LDPC code which has been subjected to the reverse replacement processing, the vertical twist deinterlacing, and the co-located inverse interleaving, that is, supplied with the LDPC code by the inspection matrix. Obtained LDPC code. The LDPC decoding unit 1021 uses the LDPC encoding unit 21 of the transmitting device 11 for the LDPC-encoded check matrix Η itself or the conversion check matrix obtained by performing at least the interlaced row replacement for the check matrix ,. The LDPC code of the LDPC code of the deinterleaver 53 is decoded, and the data obtained as a result is output as the decoding result of the object data. Here, in the receiving apparatus 12 of FIG. 211, since the deinterleaver 53 (the parity deinterleaver 1011) supplies the LDPC decoding unit 1021 to the LDPC decoding unit 1021, the LDPC encoding unit is used to check the matrix according to the inspection 133671.doc -287-200947881. The LDPC code is obtained. Therefore, when the LDPC encoding unit 21 of the transmitting apparatus 11 performs the LDPC decoding of the LDPC code by using the check matrix Η itself used for LDPC encoding, the LDPC decoding unit 1021 can be used, for example, by each node. Decoding device for performing LDPC decoding in a full serial decoding manner in which signals (check node information, variable node information) are sequentially processed, or by simultaneously (parallel) performing information operations for all nodes A decoding apparatus that performs LDPC decoding by a full parallel decoding method is constructed. Further, the LDPC decoding unit 1021 performs LDPC decoding of the LDPC code by performing at least the conversion check matrix obtained by the row replacement of the co-interleave by the LDPC encoding unit 21 for the LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11. In the case of a decoding device capable of performing an architecture of a check node operation and a variable node operation at the same time, and including the conversion of the LDPC code to obtain a conversion The row of the check matrix is replaced by the same row permutation, and is configured by rearranging the decoding means of the received data rearrangement unit 3 10 of the code bit of the LDPC code. In addition, in FIG. 211, for convenience of explanation, a multiplexer 54 for performing reverse replacement processing, a vertical twist reverse deinterleaver 55 for performing tangent reverse deinterlacing, and a co-located inverse interleaver 1011 for performing in-phase deinterlacing are separately configured. However, two or more of the multiplexer 54, the vertical twist deinterlacer 55, and the in-situ deinterleaver 1011 can be integrally formed in the same manner as the parity interleaver 23, the vertical twist interleaver 24, and the demultiplexer 25 of the transmitting device 11. . Next, Fig. 212 is a block diagram showing a first configuration example of 200947881 which is applicable to the receiving system of the receiving device 12. In Fig. 212, the receiving system is composed of an obtaining unit ι 101, a channel exhaustion processing unit 1102, and an information source decoding processing unit 11 〇3. The acquisition unit 1101 obtains, by means of, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, Internet, and other networks, a transmission channel including at least LDPC encoding of image data such as image data or audio data of the program. The signal of the obtained LDPC code is supplied to the transmission channel decoding processing unit 1102. Here, when the signal acquired by the acquisition unit 1101 is played, for example, from a broadcast station via a ground wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 11〇1 is a level adjuster or STB(Set τ〇ρ

Box. On-board box) and so on. Further, when the signal acquired by the acquisition unit 11〇1 is transmitted by multicast from a web server such as IPTV (Internet Pr() tc) eQl TelevisiQn: Internet Protocol TV, the acquisition unit 1101 is used. It is composed of, for example, a network I/F (Interface: Interface) such as an NIC (Network Interface Card). The channel decoding processing unit 11 〇2 is a channel decoding process for receiving a signal at least acquired by the acquisition unit i via the transmission channel, and obtaining the result of the error generated by the subscription channel. The signal is supplied to the information source decoding processing unit 11 〇3. That is, the signal obtained by the acquisition unit 1101 via the transmission path is a signal obtained by at least performing error correction coding for the error generated in the transmission path, and the transmission channel decommissioning processing unit should be responsible for such a signal. A channel decoding process such as a error correction process is applied. 133671.doc 200947881 Here, as the error correction coding, for example, LDPC coding or Lederman's code equal to this is performed as error correction coding, at least LDPC code 0 is performed, and 'transmission channel decoding process may include demodulation signal demodulation or the like. The information source decoding processing unit sub-system performs an information source decoding process including at least a process of extending the compressed information into the original information for the signal subjected to the channel decoding processing. * In other words, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding of the compressed information 为了 in order to reduce the amount of information such as images or sounds of the information. In this case, the information source decoding processing unit 1103 For the signal subjected to the channel decoding processing, information source decoding processing such as processing (stretching processing) of compressing the information into the original information is applied. Further, when the signal acquired by the acquisition unit 1101 via the transmission path is not subjected to compression coding, the information source decoding processing unit n〇3 does not perform the process of expanding the compressed information into the original information. Here, as the stretching processing, for example, MPEG decoding or the like is used. Moreover, the channel decoding processing may include a descrambling code or the like in addition to the stretching processing. In the receiving system configured as described above, the acquiring unit nGi applies, for example, a data such as an image or a sound to a compressed (four) code or the like, and further acquires a signal subjected to an error correction code such as an LDPC code via a transmission path. And supplied to the transmission channel decoding processing unit 丨丨〇2. . In the transmission channel decoding processing unit 11(2), for the transmission from the acquisition unit (10), for example, the orthogonal demodulation unit demapping unit 52, the deinterleaver 53, and the LDpc decoding unit % are applied as the transmission channel decoding processing ( The same processing as the LDpc decoding unit J33671.doc-290·200947881 1021) is supplied to the information source decoding processing unit 1103. The information source decoding processing unit 1103 performs information source decoding processing such as MPEG decoding on the signal from the channel decoding processing unit 1102, and outputs the image or sound obtained as a result. The receiving system as shown in Fig. 212 above can be applied to, for example, a television level adjuster that receives television broadcast as digital playback. Further, the acquisition unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 can each be used as ! A separate device (hardware (IC (Integrated Circuit), etc.) or software module). Further, the acquisition unit 010, the channel decoding processing unit 丨丨〇2, and the information source decoding processing unit 1103 can set the acquisition unit 11〇1 and the channel decoding processing unit 1102 or the channel decoding processing unit 11〇. The set of the information source decoding processing unit 1103, the acquisition unit 1101, the transmission channel decoding processing unit 11〇2, and the δ generation source decoding processing unit 1103 are configured as separate devices. Fig. 213 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 212, and the description thereof will be omitted as appropriate. The receiving system of FIG. 213 is a point including the acquisition unit u1, the transmission channel decoding processing unit 1102, and the information source decoding processing unit 11〇3, and is common to the case of FIG. 212, and the point where the output unit 1111 is newly provided is shown. The situation in 212 is different. The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs sound, and outputs an image or sound output as a signal 133671.doc - 291 - 200947881 output from the information source decoding processing unit 1103. That is, the output unit 显示i i i displays an image or outputs a sound. The receiving system as shown in Fig. 213 above can be applied to, for example, a TV (television receiver) that receives television broadcast as digital broadcast, or a broadcast receiver that receives broadcast broadcast, and the like. Further, when the signal acquired by the acquisition unit 11〇1 is not subjected to compression coding, the signal output from the transmission channel decoding processing unit 11〇2 is supplied to the output unit 1111. Figure 214 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 212, and the description thereof will be omitted as appropriate. The receiving system of Fig. 214 is the same as the case of Fig. 212 in that it includes the acquisition unit 11〇1 and the transmission channel decoding processing unit 1102. The receiving system of Fig. 214 is a point where the recording unit 1121 is newly provided without the information source decoding processing unit 1103, which is different from the case of Fig. 212. The s recording unit 1121 records the signal ❿ (for example, the TS packet of the MPEG TS) outputted by the channel decoding processing unit 11 〇 2 (recorded in the memory disc) or the hard disk (magnetic disk), fast. Record (memory) media such as flash memory. The receiving system as shown in Fig. 214 above can be applied to a video recorder or the like which records a television broadcast. In addition, in FIG. 214, the receiving system setting information source decoding processing unit is configured as the source decoding processing unit 11 , 3, and the recording unit 1121 can record the signal after the information source decoding process, that is, by Decode the image or sound obtained by 133671.doc -292- 200947881. Further, the actual drag-and-drop type of the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing a check matrix of an LDPC code. Figure 2 is a flow chart showing the decoding procedure of the LDPC code. Fig. 3 is a view showing an example of a check matrix of an LDPC code. Figure 4 is a diagram showing the Tanner graph of the inspection matrix. ® Figure 5 shows a diagram of a variable node. Figure 6 is a diagram showing a check node. Fig. 7 is a view showing an example of a configuration of an embodiment of a transport system to which the present invention is applied. FIG. 8 is a block diagram showing a configuration example of the transmitting device 11. Figure 9 is a diagram showing an inspection matrix. Fig. 10 is a view showing a parity matrix. 11A and 11B are diagrams showing the check matrix and row weight of the LDPC code defined by the specifications of DVB-S.2. 12A and B are diagrams showing the signal point arrangement of 16QAM. Figure 13 is a diagram showing the signal point configuration of 64QAM. Figure 14 is a diagram showing the signal point configuration of 64QAM. Figure 15 is a diagram showing the signal point configuration of 64QAM. 16A to 16D are diagrams for explaining the processing of the multiplexer 25. 17A and B are diagrams for explaining the processing of the multiplexer 25. Figure 18 is a diagram showing a Tanner graph for decoding of an LDPC code. 133671.doc - 293 - 200947881 FIGS. 19A and 19B are diagrams showing a parity matrix Ητ which is a step structure and a Tanner graph corresponding to the parity matrix Ητ. Figure 20 is a diagram showing the parity matrix Ητ of the check matrix 对应 corresponding to the LDPC code after the co-located interleaving. Fig. 21A and Fig. 21 are views showing a conversion check matrix. Fig. 22 is a view showing the processing of the whirling twist interleaver 24. Fig. 23 is a view showing the number of wales of the memory 3 1 and the address at which the write position is started, which are necessary for the whirling of the wagger. Fig. 24 is a view showing the number of wales of the memory 3 1 and the address of the start writing position necessary for the whirling of the wales. Fig. 25 is a flow chart showing the transmission processing. 26A and 26B are diagrams showing a model of a communication channel used in the simulation. Fig. 27 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency fd of the flutter. Fig. 28 is a graph showing the relationship between the error rate obtained by the simulation and the Buhler frequency fd of the flutter. FIG. 29 is a block diagram showing a configuration example of the LDPC encoding unit 21. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21. Fig. 31 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 16200. Figure 32 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Figure 33 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. 133671.doc -294- 200947881 FIG. 34 is a diagram showing a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 35 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200. Fig. 36 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 37 is a view showing a table of initial values of inspection matrices of a coding rate of 3/4 and a code length of 64,800. 〇 Fig. 38 is a diagram showing an initial value table of a check matrix of a coding rate of 3/4 and a code length of 64,800. Fig. 39 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 40 is a view showing a check matrix initial value table of a coding rate of 4/5 and a code length of 16200. Figure 41 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. ◎ Fig. 42 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Figure 43 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 44 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 45 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 16200. 133671.doc -295 - 200947881 Figure 46 is a diagram showing an initial value of the check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 47 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 48 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 49 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Fig. 50 is a diagram showing a check matrix initial value table ® of a coding rate of 8/9 and a code length of 16200. Figure 51 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 52 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 53 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 54 is a view showing a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 55 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 56 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 57 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. 133671.doc •296· 200947881 Fig. 58 is a diagram showing a table of initial values of inspection matrices with a coding rate of 9/10 and a code length of 64,800. Fig. 59 is a view for explaining a method of obtaining a check matrix 从 from a check matrix initial value table. Figures 60A through C are diagrams illustrating the replacement process of the current mode. Fig. 61Α~C are diagrams showing the replacement processing of the current mode. Fig. 62 is a diagram showing a code bit group and a symbol 〇 bit group in the case where the LDPC code of the code length 16200 and the coding rate 2/3 is modulated by 1024QAM and the multiple b is 2. Fig. 63 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Fig. 64A and Fig. 64 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 2/3 is modulated by 1024QAM and the multiple b is 2. 65A and FIG. 65B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Fig. 66 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Fig. 67A and Fig. 67 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. 68A and FIG. 68B are diagrams showing a code bit group and a symbol 133671.doc -297·200947881 bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Group map. Fig. 69 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Fig. 70A and Fig. 70 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 3/4 is modulated by 1024QAM and the multiple b is 2. 71A and 7B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. © Fig. 72 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Fig. 73A and Fig. 73 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Fig. 74A and Fig. 74 are diagrams showing a code bit group and a symbol 〇 bit group in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 1024QAM and the multiple b is 2. Fig. 75 is a diagram showing an allocation rule in the case where the LDPC is modulated by a 1024QAM code length of 16200 and a coding rate of 4/5, and the multiple 1) is 2. 76A and FIG. 76B are diagrams showing the replacement of the code bits of J according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. 77A and FIG. 77B show a code bit group and a symbol 133671.doc -298 - 200947881 bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. Group map. Fig. 78 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. 79A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. 80A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Fig. 81 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Fig. 82A and Fig. 82 are diagrams showing the replacement of the LDPC code having a code length of 16200 and a coding rate of 5/6 with a 1024QAM and a multiple b of 2 in accordance with the allocation code block. 83A and FIG. 83 are diagrams showing a code bit group and a symbol ❹ bit group in the case where the LDPC code of the code length of 64800 and the coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Fig. 84 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. 85A and FIG. 85B are diagrams showing the replacement of the code bits in accordance with the allocation rule J in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. 86A and FIG. 28B are diagrams showing a code bit group and a symbol 133671.doc • 299·200947881 bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. Group map. Fig. 87 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. 88A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 1024QAM and the multiple b is 2. 89A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. ❿ Fig. 90 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. 91A and FIG. 26B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. 92A and FIG. 28B show the code bit group and the symbol in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 1024QAM and the multiple b is 2.

A diagram of the Q meta-bit group. Fig. 93 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM and the multiple b is 2. Fig. 94A and Fig. 94 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 1024QAM and the multiple b is 2. 95A and FIG. 25B show a code bit group and a symbol 133671.doc -300-200947881 bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Group map. Fig. 96 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. 97A and FIG. 97B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. 98A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Fig. 99 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Figs. 100A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. 101A and FIG. 3B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. FIG. 102 is a diagram showing an allocation rule ij in the case where the LDPC code of the code length of 16200 and the coding rate of 3/4 is modulated by 4096QAM, and the multiple of the b is 2, FIG. 103A and B show that the code length is 1200QAM, and the code length is 16,200. The LDPC code with a coding rate of 3/4, and the multiple b is 2, in accordance with the replacement of the code bits of the distribution rule. 104A and B are diagrams showing a code bit group and a symbol 133671.doc -301 - 200947881 bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Group map. Fig. 105 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Fig. 106A and Fig. 106 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. 107A and FIG. 107B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Fig. 108 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Figs. 109A and B are views showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 4096QAM and the multiple b is 2. 110A and FIG. 110B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Fig. 111 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Fig. 112A and Fig. 4B are diagrams showing the replacement of the LDPC code having a code length of 64800 and a coding rate of 4/5 with 4096QAM and the multiple b being 2 in accordance with the allocation code block. 113A and FIG. 31B show a code bit group and a symbol 13367I.doc -302-200947881 bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Group map. Fig. 114 is a diagram showing an allocation rule J in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Figs. 115A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Fig. 116A and Fig. 116 are diagrams showing a code bit group and a symbol group in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Figure 117 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Fig. 118A and Fig. 118 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. 119A and FIG. BB are diagrams showing a code bit group and a symbol 〇 bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Fig. 120 is a diagram showing an allocation rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figs. 121A and 2B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 4096QAM and the multiple b is 2. 122A and B are diagrams showing a code bit group and a symbol 133671.doc -303 - 200947881 bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Group map. Fig. 123 is a diagram showing an allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Fig. 124A and Fig. 124 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figs. 125A and B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 4096QAM and the multiple b is 2. Figure 126 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 4096QAM and the multiple b is 2. 127A and BB are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 4096QAM and the multiple b is 2. Figure 128 is a diagram showing the signal point configuration of 1024QAM. Figure 129 is a diagram showing the signal point arrangement of 4096QAM. Fig. 130 is a view showing the case where the replacement process has been performed and the BER of the case where the process has not been performed. Fig. 13 is a diagram showing the case where the replacement process has been performed and the BER in the case where the process has not been performed. Fig. 132 is a view showing the case where the replacement process has been performed and the BER of the case where the process has not been performed. Figure 133 is a diagram showing the case where the replacement process has been performed and the BER in the case where the process has not been performed. 133671.doc -304- 200947881 FIG. 134 is a block diagram showing a configuration example of the receiving device 12. Figure 13 is a flow chart illustrating the receiving process. Figure 136 is a diagram showing an example of a check matrix of an LDPC code. Figure 137 is a diagram showing a matrix (conversion check matrix) after the column replacement and row replacement are performed on the inspection matrix. Figure 138 is a diagram showing a conversion check matrix divided into 5 x 5 units. Figure 139 is a block diagram showing an example of a configuration of a plurality of decoding devices for performing node operations. ® Fig. 140 is a block diagram showing a configuration example of the LDPC decoding unit 56. Figure 141 is a block diagram showing a configuration example of an embodiment of a computer to which the present invention is applied. Figure 142 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 1,600. Figure 143 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 144 is a diagram showing an example of an initial value of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 145 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 146 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 16200. Figure 147 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 148 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800 133671.doc - 305 - 200947881. Figure 149 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Fig. 150 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 151 is a diagram showing an example of an initial value of a check matrix of a coding rate of 4/5 and a code length of 16200. Figure 152 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 153 is a diagram showing an example of a check matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Figure 154 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 155 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 156 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 16,200. Figure 157 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 158 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Fig. 159 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 8004800. Fig. 160 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800 133671.doc - 306 - 200947881. Figure 161 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 16200. Figure 162 is a diagram showing an example of an initial value of the check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 163 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 164 is a diagram showing an example of a check matrix initial value ® table of a coding rate of 8/9 and a code length of 64,800. Figure 165 is a diagram showing an example of an initial value of a check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 166 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 167 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 168 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 169 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Fig. 170 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. Figure 171 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. Figure 172 is a diagram showing an example of the table of the initial value of the check matrix of the coding rate 1/3 and the code length of 64800. 133671.doc -307- 200947881. The figure shows a diagram of an example of the initial value of the check matrix of 1/3 of the bat drinking rate and a code length of 6. The figure shows a diagram of an example of the initial value of the check matrix of the bar code rate of 2/5 and the code length of 64 classes. The figure shows a diagram of an example of a table of initial values of a check matrix of a coding rate of 2/5 and a code length of 64,800. Fig. 176 is a diagram showing an example of the initial value of the inspection matrix of the codec Min, Xuanzang/Exhaustion rate 1 / 2, and code length 64800. Fig. 77 is a view showing an example of a check matrix initial value table of a bat code rate of 1/2 and a code length of 64,800. Figure 178 is a diagram showing an example of a table of initial values of a check matrix of code rate 1/2 and code length 64800. Fig. 17 is a diagram showing an example of a table of initial values of a check matrix of a code view, a frame rate, a code rate of 3/5, and a code length of 64,800. Fig. 18 is a diagram showing an example of the initial value of the check matrix of the code stone ballad 2 ς 石 stone horse rate 3/5 and code length 64800. Fig. 181 is a diagram showing an example of a table of initial values of a check matrix of a coder rate of 3/5 and a code length of 64,800. Fig. 182 is a diagram showing an example of a table of initial values of a check matrix of 1/4 of a numerator rate and a code length of 16200. Fig. 183 is a diagram showing an example of a table of initial values of a check matrix having a coding rate of 1/3 and a code length. Figure 184 shows the initial value of the inspection matrix of the overall arduous rate of 2/5 and the code length of 16200. 13367].doc 200947881 Diagram of the example. Figure 185 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 16200. Figure 186 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 16200. Figure 187 is a diagram showing another example of the check matrix initial value table of the coding rate 3/5 and the code length 16200. Figure 188 is a diagram for explaining the method of obtaining the inspection matrix from the inspection matrix initial value table. Figure 189 is a diagram showing an alternative of a code bit. Figure 190 is a diagram showing an alternative of a code bit. Figure 191 is a diagram showing an alternative of a code bit. Figure 192 is a diagram showing an alternative of a code bit. Figure 193 is a diagram showing the simulation result of BER. Figure 194 is a diagram showing the simulation result of BER. Figure 195 is a diagram showing the simulation result of BER. Figure 196 is a diagram showing the simulation result of BER. Figure 197 is a diagram showing an alternative of a code bit. Figure 198 is a diagram showing an alternative of a code bit. Figure 199 is a diagram showing an alternative of a code bit. Figure 200 is a diagram showing an alternative to a code bit. Figure 201 is a diagram showing an alternative of a code bit. Figure 202 is a diagram showing an alternative of a code bit. Figure 203 is a diagram showing an alternative of a code bit. 133671.doc -309- 200947881 Figure 204 is a diagram showing an alternative to a code bit. Figure 205 is a diagram showing an alternative of a code bit. Figure 206 is a diagram showing an alternative of a code bit. Figure 207 is a diagram showing an alternative of a code bit. Figure 208 is a diagram showing an alternative of a code bit. Fig. 209 is a view for explaining the processing of the multiplexer 54 constituting the deinterleaver 53. Fig. 210 is a view for explaining the processing of the reticular reverse deinterleaver 55. Figure 211 is a block diagram showing another configuration example of the receiving device 12. Figure 212 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. Figure 213 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 丨2. Figure 214 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12. [Major component symbol description] 11 12 21 22 23 24 25 26 27 Transmitting device receiving device LDPC coded part-element interleaver co-interleaver slant-twist interleaver multiplexer mapping unit quadrature modulation unit 133671.doc -310- 200947881

❹ 31 memory 32 replacement unit 51 orthogonal demodulation unit 52 demapping unit 53 deinterleaver 54 multiplexer 55 vertical twist deinterleaver 56 LDPC decoding unit 300 branch data storage memory 301 selector 302 check Node calculation unit 303 cyclic shift circuit 304 branch data storage memory 305 selector 306 reception data memory 307 variable node calculation unit 308 cyclic shift circuit 309 decoded word calculation unit 310 received data rearrangement unit 311 decoded data Rearrangement unit 601 Encoding processing unit 602 Memory unit 611 Encoding rate setting unit 612 Initial value table reading unit 133671.doc -311 - 200947881 613 Inspection matrix generation unit 614 Information bit reading unit 615 Coding parity calculation unit 616 Control unit 701 Bus 702 CPU 703 ROM 704 RAM 705 Hard disk 706 Output unit 707 Input unit 708 Communication unit 709 Disk drive 710 Input/output interface 711 Portable recording medium 1001 Reverse replacement unit 1002 Memory 1011 Parrot deinterlacer 1021 LDPC decoding p 1101 acquisition unit 1102 transmission channel decoding processing unit 1103 information source decoding processing unit 1111 1121 recording unit portion 133671.doc -312-

Claims (1)

200947881 X. Patent application scope: 1. A data processing device, comprising a replacement mechanism, which is an LDPC (Low Density Parity Check) code whose memory length is N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the preceding direction by the memory device of the code bit is written as one symbol, and the specific positive integer is set to b. The memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the wale direction of the memory mechanism. Then, in the foregoing direction, the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, and the LDPC code is used. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; ® LDPC code system DVB- S.2 or DVB-T.2 specifications The length N is an LDPC code of 1 6 2 0 0 ;; the foregoing allocation rule is to group the group of the foregoing code bits according to an error probability as a group of code bits, and the group will be distinguished according to the error probability. The group of symbol bits is used as a group of symbol bits, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the aforementioned symbol element of the foregoing code bit element to which the code bit group is allocated a combination of the preceding symbol bit groups of the bit 133671.doc 200947881, that is, a group set, and the foregoing code bit group of the foregoing code bit group and the foregoing symbol bit group, and the foregoing The number of bits of the symbol bit; wherein the m bit is 10 bits, and the integer bg2, the bit of the code bit ^ is mapped to 2lG, ie, ι 24 signal points as the preceding symbols In the case of any one of the above, the group of the above-mentioned code bits of the ι〇χ2 bit read in the above-mentioned course direction of the sufficiency mechanism is divided into five groups of the aforementioned code bits; The preceding symbolic element group area of the 1st and 2nd bits of the two preceding symbols is divided into 5 symbol positions. a meta-group; in the foregoing allocation rule, the following is: assigning a code-bit U-bit of the code-bit group of the first-good error probability to the symbol-bit of the fifth-perfect symbol group of the error probability ^元元; The error probability of the second good code bit group of the code bit 1 bit is the error probability of the 4th good symbol bit group of the i-bit of the symbol bit; 〇 will be wrong The 4th bit of the code bit of the probability 3rd good code bit group is assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the error probability 3rd good code 4 bits of the mother bit of the bit group, assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the error probability 3rd good code bit group 2 bits of the megabyte, 133671.doc 200947881 2 bits assigned to the symbol bit of the 3rd good symbol group of the error probability; the code of the 3rd good code bit group of the error probability 1 bit of the bit is assigned to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 4th good The 1 bit of the code bit of the code bit group is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; ® the 5th good code bit group of the error probability The 2 bits of the code bit are allocated to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; the code bit of the 5th good code bit group of the error probability is 1 The bit is allocated to the 1-bit of the symbol bit of the 4th good symbol bit group of the error probability; and the 3 bits of the code bit of the 5th good code bit group of the error probability are assigned to the error The probability of the 5th good symbolic group of the symbolic element is 3 digits ❹ 兀. A data processing device comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes the mb bit, and in the preceding paragraph 133671.doc 200947881 describes the longitudinal direction memory N/(mb) bit, the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then in the foregoing Reading in the course direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for the LDPC code Allocating an allocation rule to the symbol bit indicating the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code specified by the specification of -T.2 © length N is 16,200 bits An LDPC code having a coding rate of 2/3; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024 bits determined by 1024QAM as one of the preceding symbols. Any one of the signal points; the memory means includes 20 longitudinal lines of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; the replacement mechanism is in the course of the foregoing memory mechanism The code bit of the 10x2 bit read from the direction is set from the most significant bit, the i+1th bit is set to the ® bit bi, and the symbol bits of 2 consecutive 2 bits of the preceding symbol are consecutively The element is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to y8, the bit b! is assigned to y 6, and the bit is allocated. B2 is assigned to y〇, bit b3 is assigned to y!, 133671.doc 200947881 assigns bit b4 to y2, bit bs to y3, bit b6 to y4, and bit t&gt;7 For y5, assign bit b8 to y7, bit b9 to yi Q , bit b 1 Q to y丨丨, and bit b 11 to y i 2, 3. Assign bit bi2 to y13, bit b13 to y16, bit b14 to y14, bit b15 to y15, bit b! 6 to y 9, bit b! 7 is assigned to y 1 8, the bit bi 8 is assigned to yj 9, and the bit b 1 9 is assigned to y 丨 7. A data processing device includes a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is taken as a symbol, and the specific positive integer is b, and the memory mechanism is in the direction of the row. Memory mb bit, and travel N/(mb) bit in the preceding longitudinal direction, 133671.doc 200947881 The code bit of the aforementioned LDPC code is written in the foregoing longitudinal direction of the memory mechanism, and then in the foregoing row Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is LD of 64,800 bits. PC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol bit a tuple group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit group of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; wherein the m bit is 10 a bit, wherein the integer b is 2, and the 10-bit of the code bit is mapped to one of 21 (), that is, 1024 signal points as one of the symbols, in the foregoing memory mechanism The group of the preceding code bits of the 10x2 bit read in the course direction is divided into five groups of the aforementioned code bits; the preceding symbol bit group area of 10 X 2 bits of two consecutive symbols is 200947881 Divided into 5 symbol group; in the foregoing distribution rules, there are: The 1st bit of the code bit of the probability good first bit group is assigned to the 1st bit of the symbol bit of the 5th good symbol group of the error probability; the error probability 2nd good code 1 bit of the code bit of the bit group is assigned to 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; 〇 the error probability is 3rd good code bit group The 4 bits of the code bit are assigned to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; the 3 bits of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 3 bit of the symbol bit of the second good symbol bit group of the error probability; the 4 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 3, 4 bits of the symbol element of the good symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the 4th good symbol of the error probability 1 bit of the symbol bit of the bit group; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the error probability 2nd good 1 bit of the symbol bit of the meta-bit group; 3 bits of the code bit of the 5th good code bit group of the error probability 133671.doc 200947881 assigned the error probability 4th good symbol The 3 bits of the symbol bit of the metagroup; and the 2 bits of the code bit of the 5th good code bit group of the error probability are assigned to the symbol of the 5th good symbol bit group of the error probability 2 bits of the yuan. A data processing apparatus comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, w is used to assign the code bits of the LDPC code to the representation The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T. The code length N specified by the specification of 2 is 64,800 bits, and the coding rate is 2/3. LDPC code; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by 133671.doc 200947881 1024QAM The memory mechanism includes 20 wales that store 10x2 bits in the row direction and 64800/(10x2) bits in the wales direction; the replacement mechanism is read in the course direction of the memory mechanism. The 10x2 bit code bit is set from the most significant bit, and the i + + bit is set to the bit ratio, and the symbol bits of the 10x2 bits of the consecutive 2 symbols are counted from the most significant bit. The i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: ® assigns the bit bG to the bit y8, assigns the bit b 1 to the bit y 9, and assigns the bit b2 Giving bit y, assigning bit b3 to bit y 1, assigning bit b4 to bit y2, assigning bit b 5 to bit y 3, and assigning bit b6 to bit y4, Bit b7 is assigned to bit y5, bit b8 is assigned to bit y, bit b9 is assigned to bit y! 1, bit b1G is placed The allocation bit y12 assigns the bit b! 1 to the bit y 14, assigns the bit b! 2 to the bit y I 5 , assigns the bit b 13 to the bit y6, and assigns the bit b 14 to Bit y 7, assigns bit b 15 to bit y 13, 133671.doc 200947881 assigns bit b! 6 to bit y! 8, assigns bit b! 7 to bit y! 9, will Bit b! 8 is assigned to bit yi 6, and bit bi 9 is assigned to bit y! A data processing device comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a memory code length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbolic element of the W element replaces the code bit of the mb bit, and replaces the replaced code bit as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S.2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; The allocation rule is to group the group of the foregoing code bit groups as a group of code bits according to the error probability, and group the group of the preceding symbol bits according to the error probability as a group of symbol bits. And the rule described in 133671.doc -10- 200947881: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the element is 10 bits, and the integer b is 2, and 1 bit of the code bit is mapped as one of the symbols, that is, any one of 1 to 24 signal points, The group of the preceding code bits of the 丨〇χ2 bit read by the preceding direction of the memory mechanism is divided into four groups of the aforementioned code bits; the preceding symbols of the 1 〇χ 2 bits of the consecutive two preceding symbols The bit group is divided into 5 symbol bit groups; as specified in the foregoing allocation rules: The unit of the code bit of the code bit group with the wrong probability probability is assigned to the W element of the symbol bit of the fifth good symbol bit group of the error probability; the error probability is 2nd good The 2 bits of the code bit of the code bit group are assigned to the error probability! The symbolic element of a good symbolic group is erected; the 4th bit of the coded element of the error probability 2nd good code &amp; meta group is assigned to the second probability symbol of error probability The 4th bit of the symbol group of the metagroup; the 2nd bit of the code bit of the 2nd good code bit group of the error probability is 133671.doc •11 - 200947881 The error probability is the 3rd good symbol 2 bits of the symbol bit of the bit group; 2 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the symbol of the 4th good symbol group of the error probability 2 bits of the meta-bit; 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the 3rd bit of the symbol bit of the 5th good symbol bit group of the error probability The first bit of the code bit of the third good symbol bit group of the error probability is assigned to the one bit of the symbol bit of the first good symbol bit group of the error probability; 4 1 bit of the code bit of the good code bit group is assigned to the 1 bit of the symbol bit of the first good symbol bit group of the error probability; The 2 bits of the code bit of the probability 4th good code bit group are allocated to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; and the error probability is 4th good. The 2 bits of the code bit of the code bit group are assigned to the 2 bits of the symbol bit of the 4th good symbol bit group of the error probability. A data processing device comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the horizontal direction read in the direction of the row is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, and are used to assign the code bits of the LDPC code to the representation. The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T. The code length N specified by the specification of 2 is 16,200 bits, code The LDPC code is 3/4; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by 1024QAM. ◎ The memory mechanism includes 20 wales that store 10x2 bits in the row direction and 16200/(10x2) bits in the wales direction; the replacement mechanism is in the direction of the memory mechanism The read 10x2 bit code bit is set from the most significant bit, the i+th bit is set to bit bi, and the symbol bits of 10x2 bits of two consecutive symbols are from the most significant bit. From the first calculation, the i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, 133671.doc -13- 200947881, the bit b! is assigned to the bit Y〇' assigns bit b2 to bit y 1 ' assigns bit b3 to bit y2 ' assigns bit b4 to bit y3 ' assigns bit b5 to bit y4 ' assigns bit b6 to Bit y5' assigns bit b7 to bit y6, bit b8 to bit y 7 ' assigns bit b9 to bit y9, The bit b1G is assigned to the bit y12', the bit bi] is assigned to the bit y!3, the bit b12 is assigned to the bit y18', and the bit b!3 is assigned to the bit y! Element b 14 is assigned to bit y 1 〇 ' assigns bit b 15 to bit y 16, assigns bit b16 to bit y14, assigns bit b ] 7 to bit y丨7, places the bit b 1 8 is assigned to bit yi 5, and bit b19 is assigned to bit yil. 7. A data processing apparatus comprising: a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the aforementioned LDPC code which is written in the preceding row direction is used as the first symbol 喟 133671.doc 200947881, and the specific positive integer is b, the foregoing memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the aforementioned LDPC code For the allocation rule indicating the symbol element of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 64800 bits. The LDPC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol a group of bits, and stipulates the following rules: ◎ the foregoing group of code bits of the aforementioned code bit group and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of the groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; In the case of a 10-bit, and the aforementioned integer b is 2, and 10 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 21 () or 1024 signal points, 133671.doc - 15-200947881 The group of code bits of 10x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; the aforementioned symbols of 10x2 bits of two consecutive symbols The meta-bit group is divided into 5 symbol-bit groups; The provision is: assigning 1 bit of the code bit of the first good code bit group of the error probability to the 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; 1 bit of the code bit of the 2nd good code bit group © the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 3rd good The 4 bits of the code bit group of the code bit group are allocated to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability third good code bit group is The 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; ❹ 4 of the code bits of the 3rd good code bit group of the error probability The bit is allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability The 4th bit of the 4th good symbol group; the 2nd bit of the code bit of the 4th good code bit group of the error probability is 133671.doc • 16·200947881 allocates the 2-bit element of the symbol bit of the 4th good symbol group of the error probability; and assigns the 3 bits of the code bit of the 4th good code bit group of the error probability to The error probability is the 5th bit of the symbol bit of the 5th good symbol group. 8. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 LDPC with a code length N of 64,800 bits and a coding rate of 3/4 The m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by 133671.doc -17-200947881 1024QAM The memory mechanism includes 20 wales that store 1 〇χ 2 bits in the row direction and 64800/(10×2) bits in the wales direction; the replacement mechanism is in the direction of the memory mechanism The read 10x2 bit code bit is set from the most significant bit, the i+th bit is set to bit bi, and the symbol bits of 10x2 bits of two consecutive symbols are valid from the most significant. The i+th bit is set to the bit yi from the bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, the bit b! is assigned to the bit y6, and the bit b2 is Assigned to bit y, assign bit b3 to bit y 1, assign bit b4 to bit y2, assign bit b5 to bit y3, assign bit b6 to bit y4, place bit The element b7 is assigned to the bit y5, the bit b8 is assigned to the bit y7, the bit b9 is assigned to the bit y 1 〇, and the bit b! 〇 is allocated Bit y η, assign bit b!! to bit y 1 2, assign bit b! 2 to bit y 1 3, assign bit b ! 3 to bit y 1 4, place bit B14 is assigned to bit yi5, bit b! 5 is assigned to bit y9, 133671.doc -18- 200947881 assign bit b! 6 to bit y! 6, assign bit b ! 7 to bit y! 7, assign bit b 18 to bit y 18, and bit b! 9 to bit yi 9. A data processing device comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to represent the aforementioned symbols. The allocation rule of the symbol of the meta-sub-bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is 16200 bits 兀 LDPC code; the foregoing allocation The rule is that the group of the foregoing code bit groups is grouped as a code bit group according to the error probability, and the group of the aforementioned symbol bit groups is grouped according to the error probability as the symbol bit group, and Rule 133671.doc -19- 200947881: the foregoing code bit group of the foregoing code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of the groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; In the case of a 10-bit, and the integer b is 2, and 10 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 21Q or 1024 signal points, ® is in the memory mechanism described above. The group of the code bits of the 10x2 bit read in the horizontal direction is divided into three groups of the aforementioned meta-bits; the group of the above-mentioned symbol bits of the 10x2 bits of the two consecutive symbols is divided into five a group of symbolic bits; as specified in the foregoing distribution rules: The 4 bits of the code bit of the first good code bit group are assigned to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; the error probability is 1st good. The 3 bits of the code bit group of the code bit group are allocated to the 3 bit of the symbol bit of the second good symbol bit group of the error probability; the error probability first good code bit group is 1 bit of the code bit is assigned to 1 bit of the symbol bit of the 3rd good symbol bit group of the error probability; 3 bits of the code bit of the first good code bit group of the error probability Yuan 133671.doc •20- 200947881 The 3rd bit of the symbol bit of the 4th good symbol group of the error probability; 4 of the code bit of the 1st good code group of the error probability The bit is allocated to the 4th bit of the symbol bit of the 5th good symbol bit group of the error probability; the 1st bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability 1st bit of the symbol bit of the 3rd good symbol bit group; ® assign 1 bit of the code bit of the 3rd good code bit group of the error probability to The probability of the 2nd good symbol bit group of the symbol bit is 1 bit; the 2 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 3rd good 2 bits of the symbol bit of the symbol group; and assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the 4th good symbol group of the error probability One unit of the symbolic unit of the group. 10. A data processing apparatus comprising a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memory mb bit, and the preceding directional direction memory N/(mb) bit is written in the first 133671.doc -21 - 200947881, and the code bit of the LDPC code is written in the foregoing longitudinal direction of the memory mechanism, Then, in the foregoing direction of the course, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, the LDPC is used. The code bit of the code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB- The code specified in the specifications of S.2 or DVB-T.2® is N for 16 200 bits, LDPC code with a coding rate of 4/5, the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are mapped to 1024Q AM as one of the aforementioned symbols. Determining any one of 1024 signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; the foregoing replacement mechanism is to be in the foregoing memory The code bit of 10x2 bits read by the direction of the mechanism is set to the bit bi from the most significant bit, and the symbol of 10x2 bits of the preceding two symbols is consecutively The i-th bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y〇, and the bit b 1 is assigned to the bit. Yuan y!, assigning bit b2 to bit y2, assigning bit b3 to bit, 133671.doc -22- 200947881 assigning bit b4 to bit y4 and bit b5 to bit y6, Bit b6 is assigned to bit y7, bit b7 is assigned to bit y8, bit b8 is assigned to bit y9, bit b9 is assigned to bit Element y10, assigning bit b丨〇 to bit y!!, assigning bit bi! to bit y!2, assigning bit b12 to bit y16, and assigning bit b13 to bit y18, Bit b14 is assigned to bit y19, bit b! 5 is assigned to bit y5, bit bI6 is assigned to bit y14, bit b17 is assigned to bit y17, bit .b 1 8 is assigned Give bit y] 5, The bit b 1 9 is assigned to the bit y 丨 3. A data processing device comprising a replacement mechanism for a memory mechanism of a code bit of an LDPC (L0W Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction and written in the horizontal direction is taken as a symbol, and the specific positive integer is b, and the memory mechanism is just described above. The column direction memorizes the mb bit and memorizes the N/(mb) bit in the preceding wander direction, 133671.doc -23- 200947881 The code bit of the aforementioned LDPC code is written in the aforementioned wale direction of the aforementioned memory mechanism, and thereafter Read in the foregoing direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the code for the LDPC code The bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 64800 bits. LDPC code; the foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and group the group of the aforementioned symbol bits according to the error probability as a group a group of meta-bits, and defining the following rules: the foregoing group of code bits of the foregoing code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the element is 10 bits, and the integer b is 2, and 10 bits of the code bit are mapped as one of the aforementioned symbols to 21G or 1024 signal points, in the memory mechanism The group of the preceding code bits of the 10x2 bit read in the horizontal direction is divided into three groups of the aforementioned bit bits; the preceding symbol bit group region of the first two consecutive symbols of the first two bits 133671.doc -24- 200947881 is divided into 5 symbolic group; The rule provides: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; The error probability of the first good code bit group of the code bit is allocated to the error probability of the fifth good symbol bit group of the 1-bit symbol; ® will be the second best error probability The 4 bits of the code bit of the code bit group are assigned to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the second probability good bit group of the error probability 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; 3 of the code bits of the 2nd good code bit group of the error probability The bit is allocated to the 3-bit unit of the symbol bit of the 3rd good symbol bit group of the error probability; the 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error The 3rd bit of the symbol bit of the 4th good symbol group of the probability; the 1st bit of the code bit of the 3rd good code bit group of the error probability Give the 1st bit of the symbol bit of the 3rd good symbol bit group of the error probability; and the 3 bit of the code bit of the 3rd good code bit group of the error probability 133671.doc -25 - 200947881 The 3rd bit of the symbol bit of the 5th good symbol group of the error probability. 12. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction stores mb bits, and the N/(mb) bit is memorized in the preceding direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to Representing the allocation rule of the symbol element of the preceding symbol, replacing the code bit of the mb bit, ◎ replacing the replaced code bit as the aforementioned symbol bit; the foregoing LDPC code is DVB-S.2 or DVB- The code length N specified by the specification of T.2 is 64800 bits, and the coding rate is 4/. The LDPC code of 5; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to any one of 1024 signal points determined by 1024QAM. The memory mechanism includes 20 vertical rows of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction; 133671.doc -26-200947881 The foregoing replacement mechanism is in the horizontal direction of the aforementioned memory mechanism The code bit of the 10x2 bit read out in the column direction is set to the bit bi from the most significant bit, and will be 1 〇&gt;&lt;2 bits of 2 consecutive symbols The symbol element is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bQ is allocated to the bit y8, and the bit bi is allocated to the bit. Element y6, assigning bit b2 to bit y〇, assigning bit b3 to bit y!, assigning bit b4 to bit y2, assigning bit b5 to bit y3, bit b6 Assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y7, bit b9 is assigned to bit y! 〇, The bit b丨〇 is assigned to the bit yn, 位 the bit b! i is assigned to the bit y 12 'the bit b! 2 is assigned to the bit y 13 'the bit bi 3 is assigned to the bit y μ ' Assigning bit b]4 to bit y 16, assigning bit b! 5 to bit y 17 ' assigning bit b! 6 to bit y 9, assigning bit b! 7 to bit y 15. Assign bit b18 to bit y18, 133671.doc • 27- 200947881 Assign bit b19 to bit y19. 13. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the wale direction, 码 the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; 〇 the foregoing LDPC code system is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is an LDPC code of 16,200 bits; The allocation rule is to group the group of the foregoing code bit groups as a group of code bits according to the error probability, and group the group of the preceding symbol bits according to the error probability as a group of symbol bits. And specifying the following rules: a combination of the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit group of the foregoing symbol bit element of the code bit group to which the code bit group is allocated 133671. Doc -28· 200947881 is a group set, and the foregoing code bit group of the foregoing group set and the bit number of the foregoing symbol bit group and the number of bits of the foregoing symbol bit; When the bit is 10 bits and the integer b is 2, and 10 bits of the code bit are mapped as one of the aforementioned symbols to 21 () or 1024 signal points, The group of code bits of the 10x2 bit read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; ® the preceding symbol bit group of 10x2 bits of two consecutive symbols The group is divided into five groups of symbol bits; as specified in the foregoing allocation rules: Assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; The 4 bits of the code bit group of the code bit group are assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability 兀 兀, the error probability second good code bit group The 3 bits of the group of code bits are assigned to the 3 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 2nd good code bit group of the error probability is The 2-bit element is assigned to the 2-bit element of the symbol bit of the 3rd good symbol bit group of the error probability; the 4th bit of the code bit of the 2nd good code bit group of the error probability is 133671. Doc -29· 200947881 allocates 4 bits of the symbol bit of the 4th good symbol group of the error probability; assigns 2 bits of the code bit of the 2nd good code bit group of the error probability to The error probability is the 5th good symbol of the symbol group of the 5th good bit group; the error probability 3rd good symbol bit group of the 1st bit of the code bit Assign 1 bit of the symbol bit of the 5th good symbol group of the error probability; assign the 1 bit of the code bit of the 4th good code bit group of the error probability to the error probability 2 1 bit of the symbol element of the good symbol group; and 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the 3rd good symbol of the error probability The 2-bit of the symbol group of the meta-group. 14. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Q Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And 133671.doc -30- 200947881 in the case where the mb bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 16200 The LDPC code having a bit rate and a coding rate of 5/6; the m-bit is 10 bits, and the integer b is 2; © 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols Any one of 1024 signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; the foregoing replacement mechanism is the aforementioned memory mechanism The code bits of the 10x2 bits read in the row direction are set to the bit bi from the most significant bit, and the symbol bits of the 10x2 bits of the preceding two symbols are consecutively The element is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b 1 is assigned to the bit y〇. Assigning bit b2 to bit y 1, assigning bit b3 to bit y2, assigning bit b4 to bit y3, assigning bit b 5 to bit y 4, assigning bit b6 to Bit y5, 133671.doc -31 - 200947881 assigns bit b7 to bit y6 ' assigns bit b8 to bit y7 ' assigns bit b9 to bit Element y9, assigning bit b1G to bit yi 〇 ' assigning bit b!! to bit yi 1 ' assigning bit b12 to bit yi2 ' assigning bit b! 3 to bit y 16 ' Assign bit b14 to bit yn, bit b! 5 to bit y! 8, assign bit b16 to bit y19, assign bit b! 7 to bit y丨4, place bit Element b! 8 is assigned to bit y丨5, and bit b19 is assigned to bit y13. 15. A data processing device comprising a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written in the direction of the row is used as the symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and the code of 133671.doc 200947881 bits of the (10) bit read in the foregoing direction of the memory mechanism is used as the continuous b symbols, according to the code position of the LDPC code. The element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or The code length N specified by the specification of DVB-T.2 is 64800 bits. The LDPC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol a group of bits, and the following rules are defined: the foregoing group of code bits of the aforementioned code bit group and the aforementioned symbol bit group of the aforementioned symbol bit of the code bit group to which the code bit group is allocated The combination is the group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; a 10-bit, and the integer b is 2, and when the 10-bit of the code bit is mapped to one of 21G, that is, 1024 signal points as one of the symbols, the horizontal direction of the memory mechanism The group of the preceding code bits of the 10x2 bit read in the column direction is divided into 5 groups of the aforementioned code bits; the group of the preceding symbol bits of the 2 consecutive 2 bits of the preceding symbols is divided into 5 a group of symbolic bits; as specified in the foregoing distribution rules: Rate 1 bit of the code bit of the 1st good code bit group 133671.doc -33- 200947881 The 1st bit of the symbol bit of the 5th good symbol group of the error probability; Error probability 2nd good code bit group 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 3rd good The 4 bits of the code bit group of the code bit group are allocated to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability third good code bit group is The 4-bit code of the code bit is assigned to the 4-bit of the symbol bit of the second good symbol group of the error probability; the error bit probability of the 3rd good code bit group of the code bit 4 The bit is allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 2 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability The 2nd bit of the symbol bit of the 4th good symbol bit group ❹ 7L· 5 Assigns the 1st bit of the code bit of the 4th good code bit group of the error probability to the wrong The 1st bit of the symbol bit of the 4th good symbol bit group of the probability; and the 3 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 5th good The 3-bit symbol of the symbol element group. 16. A data processing apparatus comprising a replacement mechanism, which is a LDPC (Low Density Parity Check) having a memory code length of N bits in a row direction and a longitudinal direction of 133671.doc -34-200947881 The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means of the code bit in the preceding direction is set as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 64800 bits. The LDPC code having a marsh rate of 5/6; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 determined by 1024QAM as one of the preceding symbols. Any one of the signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction; the replacement mechanism is transverse to the aforementioned memory mechanism The code bit of the 10x2 bit read out in the column direction is set from the most significant bit, the i+th bit is set to the bit bi, and the symbol bits of 2 consecutive 2 bits of the preceding symbol are consecutively 133671.doc -35- 200947881 The element is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, and the bit b is丨 is allocated to bit y6, bit b2 is assigned to bit y〇, bit b3 is assigned to bit yt, bit b4 is assigned to bit y2, bit b5 is assigned to bit y3, bit is set The element b6 is assigned to the bit y4, the bit b7 is assigned to the bit y5, the bit b8 is assigned to the bit y7, and the bit b9 is assigned to the bit y! 0 , the bit b1G is allocated to the bit yn, the bit bn is assigned to the bit y12, the bit b12 is assigned to the bit y13, the bit b13 is assigned to the bit y14, and the bit b14 is assigned to the bit y15 , bit b15 is assigned to bit y16, bit b16 is assigned to bit y17, bit b 17 is assigned to bit y 9 ', bit b 8 is assigned to bit y 18 , bit b 19 is assigned to bit y] 9. 17 • A data processing device, which includes a replacement mechanism, and the code of the LDPC (Low 133671.doc 200947881 Density Parity Check) code of the N: yuan in the horizontal direction and the longitudinal direction of the child. The m-bit of the code bit of the LDPC code read in the row direction and written in the wale direction by the memory device of the bit is regarded as one symbol, and the specific positive integer is b, The memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then Reading in the course direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for the LDPC code Allocating an allocation rule to the symbol bit indicating the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 16200 bits. LDPC code; the foregoing allocation rule is to group a group of the foregoing code bit groups according to an error probability as a code bit group, and group the group of the preceding symbol bits according to an error probability as a symbol bit a tuple group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit group of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; 133671.doc -37· 200947881 In the case where the m-bit is 10 bits and the integer b is 2, and 10 bits of the code bit are mapped as one of the symbols to 21G, that is, 1024 signal points, The group of code bits of the 1 〇χ 2 bit read by the aforementioned direction of the memory mechanism is divided into 5 groups of the aforementioned code bits; the preceding symbol bits of 10x2 bits of two consecutive symbols The meta group is divided into 5 symbol bit groups; in the foregoing allocation rule The following is: assigning the 2-bit product of the code bit of the 1st good code bit group of the error probability to the 2 bit of the symbol bit of the 5th good symbol group of the error probability; The 1st bit of the code bit of the 2nd good code bit group is assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group of the error probability; the error probability 3rd good code The 4 bits of the code bit of the bit group are allocated to the 4 bit unit of the symbol bit of the first good symbol bit group of the error probability; the error probability 3rd good code bit group is The 4 bits of the code bit are assigned to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; 3 bits of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 3-bit symbol of the symbol element of the 3rd good symbol group of the error probability; the 3rd bit of the code bit of the 3rd good code bit group of the error probability is 133671.doc - 38- 200947881 The 3rd bit of the symbol bit of the 4th good symbol group of the error probability; the code bit of the 4th good code bit group of the error probability 1 bit is allocated to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; and 2 bits of the code bit of the 5th good code bit group of the error probability are assigned to The error probability is the 5th good symbol of the 5th good symbol group. </ RTI> 18. A data processing device comprising a replacement mechanism for gamma (Low Density Parity Check) code numerators with a length of N bits in the horizontal direction and the longitudinal direction The m-bit of the LDPC code bit read by the memory mechanism in the wale direction and read in the horizontal direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T. The code specified by the specification of 2 133671.doc -39- 200947881 The length N is 16200 The LDPC code with a bit rate and a coding rate of 8/9; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols. Any one of 1024 signal points; the memory mechanism includes 20 wales of 1 〇χ 2 bits in the horizontal direction, and 16200/(10×2) bits in the waling direction; the foregoing replacement mechanism is to be in the foregoing memory The 10x2 bit code bit read from the column direction of the mechanism is set to the bit bi from the most significant bit, and the symbol of 10x2 bits of the preceding two symbols is consecutively The bit is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b 1 is assigned to the bit y9. , bit b2 is assigned to bit y4, bit b3 is assigned to bit y, bit b4 is assigned to bit y 1, bit b5 is assigned to bit y2, bit b6 is assigned to bit Element y3, assigning bit b7 to bit ys, assigning bit b8 to bit y6, assigning bit b9 to bit y7, and dividing bit b! Give bit y! 〇, assign bit b!! to bit y 1], assign bit b 丨 2 to bit y ] 2, 133671.doc -40- 200947881 19. ❹ 〇 bit b 3 is assigned to bit y 1 3, bit b 14 is assigned to bit y 14, bit b! 5 is assigned to bit y! 5, bit bi6 is assigned to bit y16, bit bi is 7 is assigned to the bit y! 7, the bit bi 8 is assigned to the bit y! 8, and the bit b 19 is assigned to the bit y 19. A data processing device comprising a replacement mechanism for a memory device of a code bit of an LD PC (Low Density Parity Check) code having a memory code length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is the specification of DVB-S.2 or DVB-T.2 The specified code length N is 64800 bits of LDPC code; 133671.doc -41 - 20 0947881 month, the rule of the knife will be based on the error probability group to distinguish the group of the aforementioned code bits 作为 as the code group π group, and will group the group of the preceding symbols as symbols according to the error probability. a group of bits, and stipulates the following rules: the foregoing group of code bits of the code bit element and the aforementioned group of symbol bits of the aforementioned symbol bit of the code bit it to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the set of groups and the foregoing code bit of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the element is 10 bits, and the integer is 2, and the 10 bits of the code position port are used as i symbols, and are mapped to 2) 0, that is, any one of the signal points is deleted, The code bit TL group of the purchase position read by the memory unit in the foregoing direction is divided into five groups of the aforementioned code bits; the preceding ones of the two consecutive symbols of 1 〇 x 2 bits The meta-group is divided into five sub-bit groups; in the foregoing distribution rules, there are: The 2 bits of the code bit of the first good code bit group are assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability is 2nd good code bit The bit of the code bit of the metagroup is assigned to the g element of the symbol bit of the fourth good symbol bit group of the error probability; the code bit of the third good symbol bit group of the error probability 4 bits 133671.doc • 42- 200947881 The 4th bit of the symbol bit assigned to the 1st good symbol group of the error probability; the code bit of the 3rd good code bit group of the error probability The 4th bit of the element is allocated to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 4 bit of the code bit of the 3rd good code bit group of the error probability is allocated Give the 4th bit of the symbol bit of the 3rd good symbol group of the error probability; ® Assign the 1st bit of the code bit of the 3rd good code bit group of the error probability to the error probability 4th 1 bit of the symbol bit of a good symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the error probability 5 1 bit of the symbol bit of the good symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the 4th good symbol of the error probability 1 bit of the symbol group of the meta-group; 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the symbol of the 4th good symbol group of the error probability 1 bit of the meta-bit; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the symbol bit of the 5th good symbol bit group of the error probability Bit. 20. A data processing apparatus comprising a replacement mechanism, which is 133671.doc • 43· 200947881 LDPC (Low Density Parity Check) having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means of the code bit in the preceding direction is set as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing course direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used to The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by the .2 or DVB-T.2 specification is 64. 800 bits, LDPC code with a coding rate of 8/9; the m bits are 10 bits, and the aforementioned integer b is 2; w 10 bits of the above code bits are mapped to 1024QAM as one of the aforementioned symbols Determining any one of 1024 signal points; the memory mechanism includes 20 vertical rows of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction; the foregoing replacement mechanism is to be in the foregoing memory The 10x2 bit code bit read by the direction of the mechanism is set to the bit bi from the most significant bit, and the symbol of 10x2 bits of the preceding two symbols is consecutively Bit 133671.doc •44- 200947881 The first element is calculated from the most significant bit. The i+1th bit is set to the bit w. The allocation rule is replaced by the following: The bit b〇 is assigned to the bit ye ' The element th is assigned to the bit y9 'the bit b2 is assigned to the bit y6'. The bit b3 is assigned to the bit y〇' and the bit b4 is assigned to the bit y 1 ' Assigning bit b5 to bit y2' assigns bit b6 to bit y3, bit b7 to bit y4, bit b8 to bit y5, and bit b9 to bit y7, The bit b! 〇 is assigned to the bit y! 〇, the bit b 11 is assigned to the bit y丨i, the bit b! 2 is assigned to the bit y! 2, and the bit b13 is assigned to the bit y13 Bits b14 are assigned to bit y14, bit b15 is assigned to bit y15, bit b16 is assigned to bit y18, bit b17 is assigned to bit y16, bit b18 is assigned to bit yn , the bit b19 is assigned to the bit y19. 21. - (4) Processing device 'which includes a replacement mechanism for LDpc whose memory length is N bits in the horizontal direction and the longitudinal direction (L〇w 133671.doc -45-200947881 Density Parity Check: low density parity Checking that the m-bit of the code bit of the LDPC code read in the preceding direction by the memory means of the code bit of the code bit is written as one symbol, a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the foregoing course direction, and in the case where the code © bit of the mb bit read in the direction of the preceding direction of the memory mechanism is used as the continuous b symbols, The code bit of the LDPC code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, and replaces the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB The code length N specified in the specification of -S.2 or DVB-T.2 is 64800 The LDPC code of the element; the foregoing allocation rule is to group the group of the foregoing code bit Q elements as a group of code bits according to the error probability, and the group w is distinguished from the group of the aforementioned symbol bits according to the error probability. As a group of symbol bits, a rule is defined as follows: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of the meta-groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the foregoing code bit of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; 133671.doc -46- 200947881, wherein the m-bit is 10 bits, and the integer b is 2, and 10 bits of the code bit are mapped as 21 (or 1024 signal points) as one of the aforementioned symbols. In one case, the group of code bits of 10x2 bits read in the foregoing direction of the memory mechanism is divided into three groups of the preceding code bits; 10x2 bits of two consecutive symbols are consecutively The preceding symbol bit group is divided into 5 symbol bit groups; The rules stipulate that: 分配 assigning the two bits of the code bit of the first good symbol bit group of the error probability to the two bits of the symbol bit of the fifth good symbol bit group of the error probability; Assigning 4 bits of the code bit of the second good code bit group of the error probability to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; The 3 bits of the code bit of the code bit group are allocated to the 3 bit unit of the symbol bit of the 2nd good symbol bit group of the error probability; the 2nd good code bit group of the error probability The 4 bits of the group of code bits are assigned to the 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; the code bit of the 2nd good code bit group of the error probability is The 4-bit element is assigned to the 4-bit element of the symbol bit of the 4th good symbol bit group of the error probability; the 1st bit of the code bit of the 2nd good code bit group of the error probability is 133671. Doc -47- 200947881 The 1st bit of the symbol bit of the 5th good symbol group of the error probability; the 3rd good code bit group of the error probability One bit of the code bit is assigned to one bit of the symbol bit of the second good symbol bit group of the error probability; and the code bit of the third good symbol bit group of the error probability One bit is assigned to one bit of the symbol bit of the fifth good symbol bit group of the error probability. 22. A data processing apparatus comprising a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The code specified by the specification is 133671.doc -48· 200947881 Long N is 64800 The LDPC code with a coding rate of 9/10; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 determined by 1024QAM as one of the aforementioned symbols. Any one of the signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the waling direction; the replacement mechanism is transverse to the memory mechanism The code bit of the 10x2 bit read out in the column direction is the bit i from the most significant bit, and the symbol bit of 10x2 bits of the preceding two symbols is consecutive. The i+th bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, and the bit b 1 is assigned to the bit y9, Bit b2 is assigned to bit y, bit b3 is assigned to bit y!, bit b4 is assigned to bit y2, 位 bit b 5 is assigned to bit y 3, bit b6 is assigned to Bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y6, bit b9 is assigned to bit y7, bit b! The allocation bit y丨〇 assigns the bit bn to the bit y! i, and assigns the bit b 丨 2 to the bit y 12, 133671.doc -49- 200947881 assigns the bit b! 3 to the bit y 14. Assigning bit b 14 to bit y 15, assigning bit bi 5 to bit yi 6, assigning bit b ! 6 to bit y 1 7 , assigning bit b 17 to bit y18, The bit b!8 is assigned to the bit y 19 and the bit b! 9 is assigned to the bit y 1 3 . 23. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b). The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is an LDPC code of 16,200 bits; 133671.doc -50- 200947881 month's allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and group the group of the aforementioned symbol bits according to the error probability. As a group of symbol bits, a rule is defined as follows: the foregoing group of code bits of the foregoing code bit element and the aforementioned symbol bit element of the month of the code bit group to which the code bit group is allocated The combination of the symbol bit group, that is, the group set, and the foregoing code bit group of the group set and the bit code group of the foregoing symbol bit group and the number of bits of the foregoing symbol bit In the case where the m-bit is 12 bits, and the integer b&amp;2, the 12-bit of the above-mentioned code bit 映射 is mapped as one of the aforementioned symbols to any of f2, that is, one of the signal points. The group of the preceding code bits of the ΐ 2 χ 2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; the preceding symbols of the 12 χ 2 bits of the two consecutive symbols The bit group is divided into 6 symbol group; as specified in the foregoing allocation rules Assigning the code bit U bit of the error probability first good code bit group to the symbol bit of the 6th good symbol bit group of the error probability "Liyuan; the error is (4) 2 good code The code bit element of the bit group is assigned to the element of the symbol bit of the fifth good symbol bit group of the error probability; the third bit of the error probability is the code bit of the group 4 bits 13367] .doc •51 · 200947881 The 4th bit of the symbol bit assigned to the first good symbol group of the error probability; the code bit of the 3rd good code bit group of the error probability The 2 bits of the element are allocated to the 2 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the 4 bits of the code bit of the 3rd good code bit group of the error probability are allocated Give the 4th bit of the symbol bit of the third good symbol group of the error probability; assign the 3 bit of the code bit of the 3rd good code bit group of the error probability to the error probability 4th 3 bits of the symbol element of a good symbol group; 1 bit of the code bit of the 3rd good code bit group of the error probability The 1st bit of the symbol bit of the symbol group of the 5th good symbol group of the error probability is assigned; the 2nd bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 2nd good 2 bits of the symbol bit of the symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the 4th good symbol bit of the error probability 1 bit of the symbol bit of the group; 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the symbol bit of the 5th good symbol bit group of the error probability 2 bits of the element; and the 3 bits of the code bit of the 4th good code bit group of the error probability 133671.doc -52· 200947881 assigned to the error probability 6th good symbol group The three bits of the yuan. 24. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding direction and read in the direction of the row is regarded as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to Representing the allocation rule of the symbol element of the preceding symbol, replacing the code bit of the aforementioned mb bit, d replacing the replaced code bit as the aforementioned symbol bit; the foregoing LDPC code is DVB-S.2 or DVB- The code length N specified by the specification of T.2 is 16,200 bits, and the coding rate 2/3 LDPC code; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 signal points determined by 4096QAM The memory mechanism includes 24 vertical rows of 12x2 bits in the horizontal direction and 16200/(12x2) bits in the longitudinal direction; 133671.doc -53-200947881 The foregoing replacement mechanism is in the foregoing memory mechanism The 12x2 bit code bit read from the horizontal direction is set to the bit bi ' from the most significant bit and the 12 bits of the preceding two symbols are 12 χ 2 bits. The i+1th bit from the most significant bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y!〇, and the bit b! is assigned to the bit y 8, assigning bit b2 to bit y, assigning bit b3 to bit y!, assigning bit b4 to bit y2, assigning bit b5 to bit y3, allocating bit b6 To the bit y4, the bit b7 is assigned to the bit y5, the bit b8 is assigned to the bit y6, and the bit b9 is assigned to the bit y7, the bit bi is Assigned to bit y9, assigns bit h to bit yi2 ' assigns bit b丨2 to bit y 13, assigns bit b!3 to bit yi6, assigns bit b! 4 to Bit y 1 7, assign bit b! 5 to bit y 1 8, assign bit b! 6 to bit y2 〇 ' assign bit b! 7 to bit y 1 4, place bit B18 is assigned to the bit yu, -54- 133671.doc 200947881 The bit b! 9 is assigned to the bit y22, the bit b2 is assigned to the bit y23, and the bit b21 is assigned to the bit y2! The element b22 is assigned to the bit yi5, and the bit b23 is assigned to the bit yi9. 25. A data processing apparatus comprising a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit ' of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; The matching rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and the group of 133671.doc -55-200947881 is distinguished according to the error probability as the group of the preceding symbol bits. a symbol bit group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; The memory is 12 bits, and the integer b is 2, and the 12 bits of the code bit are mapped as one of the 212 symbols, that is, any of the 4096 letter ® points, as described above. The group of code bits of the 12x2 bit read by the foregoing direction of the mechanism is divided into four groups of the aforementioned code bits; the preceding symbol group of 12x2 bits of the preceding two symbols is distinguished. It is a group of 6 symbol bits; as stated in the foregoing distribution rules: The 1st bit of the code bit of the probability good 1st bit group is assigned to the error probability 6th good symbol bit group 1 bit ^ yuan; the error probability is 2nd good 1 bit of the code bit of the code bit group is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; the error probability 3rd good code bit group The 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; 133671.doc -56- 200947881 The error probability 3rd good code bit group The 4 bits of the group of code bits are assigned to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is 2 bits are allocated to the 2 bits of the symbol bit of the 3rd good symbol bit group of the error probability; the 3 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the error The 3rd unit of the symbol bit of the 4th good symbol group of the probability; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned The error probability is the 5th good symbol of the symbol element of the 5th good bit group; the 2nd bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 3rd good 2 bits of the symbol bit of the symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the error probability 4th good symbol group 1 bit of the symbol bit; assign the 3 bits of the code bit of the 4th good code bit group of the error probability to the symbol bit of the 5th good symbol bit group of the error probability 3 bits; and 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the 2nd bit of the symbol bit of the 6th good symbol bit group of the error probability 0 133671 Doc-57-200947881 26. A data processing apparatus comprising a replacement mechanism for LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction a code bit of the aforementioned LDPC code read by the memory unit of the code bit in the preceding direction and read in the direction of the preceding row The m bit is taken as one symbol, and the specific positive integer is set to b. The memory mechanism memorizes the mb bit in the direction of the preceding row, and memorizes the N/(mb) bit in the longitudinal direction, the code of the LDPC code. The bit is written in the longitudinal direction of the memory means, and then read in the direction of the row, and the code bits of the mb bits read in the direction of the memory of the memory mechanism are regarded as continuous b In the case of the foregoing symbol, the code bit used to allocate the code bit of the LDPC code to the symbol bit representing the symbol is replaced by the code bit of the mb bit, and the replaced code bit is replaced. The LDPC code is a symbol bit element of the foregoing DVBC code; the code Q length N specified by the specification of DVB-S.2 or DVB-T.2 is 64800 bits, and the coding rate is 2/3 LDPC code; The element is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; the memory mechanism is included in the course Direction memory 24 vertical lines of 12x2 bits, memory 64800/(12x2) bits in the longitudinal direction; The replacement mechanism is a 12x2 bit code bit read from the row direction of the memory mechanism from the most significant bit. The i+th bit is set to 133671.doc • 58-200947881 is the bit bi, And the symbol of the 12th and 2nd bits of the two consecutive symbols is calculated from the most significant bit, and the i+1th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: Assigned to bit y!, assign bit bi to bit yi 1, assign bit b2 to bit y, assign bit b3 to bit y 1, assign bit b4 to bit y2 , bit b5 is assigned to bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y6, bit b9 is assigned to bit y7 , assigning bit b! 〇 to bit y 8, assigning bit b!! to bit y 1 2, assigning bit b 2 to bit y 13, assigning bit b! 3 to bit Element y 1 4, assigning bit b! 4 to bit y 15, assigning bit h 5 to bit y 1 8, assigning bit b 丨 6 to bit y 9, bit b! 7 Assigned to bit y2〇' will be bit B 丨 8 is assigned to bit y 16, bit 】 9 is assigned to bit y22, bit b2 〇 is assigned to bit y23, -59- 133671.doc 200947881 bit b21 is assigned to bit y 17 The bit b22 is assigned to the bit y21, and the bit b23 is assigned to the bit y 1 9 . 27. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is used as one symbol, and the specific positive integer is b, © the memory mechanism The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the foregoing symbol replaces the code bit of the mb bit, and replaces the code bit as the symbol bit; the LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is an LDPC code of 16,200 bits; The foregoing allocation rule is to group a group of the foregoing code bit groups as a code bit group according to an error probability, and group the group of the aforementioned symbol bit groups according to an error probability as a symbol bit group. And stipulates the following rules: 133671.doc -60- 200947881 The foregoing code bit group of the foregoing code bit element and the aforementioned symbol bit of the aforementioned symbol bit element of the aforementioned code bit element to which the code bit group is allocated The combination of the meta-groups, that is, the group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the bit is 12 bits and the integer b is 2, and 12 bits of the code bit are mapped as one of the aforementioned symbols to 212, that is, 4096 signal points, ® is in the foregoing memory The group of code bits of the 12x2 bit read by the foregoing direction of the mechanism is divided into four groups of the aforementioned code bits; the preceding symbol group of 12x2 bits of the preceding two symbols is distinguished. It is a group of 6 symbol bits; as specified in the foregoing distribution rules: Assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability; The 3 bits of the code bit of the code bit group are assigned to the 3 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability second good code bit group 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; 3 of the code bits of the 2nd good code bit group of the error probability The bit is allocated to the 3rd bit of the symbol bit of the 3rd good symbol bit group of the error probability 133671.doc -61 - 200947881 yuan; the code bit of the 2nd good code bit group of the error probability is 2 bits are allocated to the 2 bits of the symbol bit of the 4th good symbol bit group of the error probability; the 2 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error The 2nd bit of the symbol bit of the 5th good symbol bit group of the probability; the 2 bit allocation of the code bit of the 2nd good code bit group of the error probability The error probability is the 6th good symbol of the symbolic bit group of the 6th bit; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 4th good 1 bit of the symbol bit of the symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the first probability symbol group of the error probability 1 bit of the symbol bit of the group; 分配 assign 1 bit of the code bit of the 4th good code bit group of the error probability to the symbol of the 3rd good symbol bit group of the error probability 1 bit of the element; 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; The 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the 2nd bit of the symbol bit of the 5th good symbol bit group of the error probability 133671.doc -62- 200947881 yuan And assigning 1 bit of the code bit of the 4th good code bit group of the error probability to 1 bit of the symbol bit of the 6th good symbol bit group of the error probability Yuan. 28. A data processing apparatus comprising: a replacement mechanism for remembering code bits of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding row direction is read as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row If the code bits of the mb bits read in the foregoing direction of the memory mechanism are read as consecutive b symbols, the code bits for the LDPC code are allocated to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is 16,200 bits and the coding rate is 3/4. LDPC code; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; 133671.doc -63- 200947881 The memory mechanism contains 24 wales of memory 丨 2x2 _ in the horizontal direction and 16200/(12x2) bits in the longitudinal direction; the aforementioned replacement mechanism will be in the aforementioned memory mechanism The code bit of the 12x2 bit read out in the course direction is set to the bit bi from the most significant bit, and the symbol bit of 12x2 bits of the preceding two symbols is consecutively The i+1th bit is set to the bit yi from the most south effective bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y10, and the bit b! is assigned to the bit y〇. The bit b2 is assigned to the bit y!, the bit b3 is assigned to the bit y2, the bit b4 is assigned to the bit y3, the bit b5 is assigned to the bit y4, and the bit b6 is assigned to the bit y5 , the bit b7 is assigned to the bit y6, the bit b8 is assigned to the bit y7, the bit b9 is assigned to the bit y8, and the bit b! The allocation bit y 9 ' assigns the bit b!! to the bit y η, assigns the bit b12 to the bit yi2, assigns the bit b!3 to the bit y 14 ' assigns the bit b14 to the bit y 〗 5, assign bit b15 to bit y〗 6, and assign bit b16 to bit y22, 133671.doc • 64- 200947881 29. 分配 Assign bit bi 7 to bit y丨8,1 Assigning bit b 18 to bit y23, assigning bit b! 9 to bit y丨7, assigning bit b2〇 to bit y! 9, assigning bit b21 to bit y2〇, Bits t &gt; 22 are assigned to bit y2 1, and bit b23 is assigned to bit y 1 3. A data processing device includes a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the direction of the row. Memorizing mb bits, and storing N/(mb) bits in the longitudinal direction, 码 the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the horizontal direction. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is the specification of DVB-S.2 or DVB-T.2 The specified code length N is 64800 bits of LDPC code; 133671.doc -65- 200947881 The foregoing allocation rule is to group the group of the foregoing code bit groups as a code bit group according to the error probability, and group the group of the aforementioned symbol bit groups according to the error probability as the symbol bit group. Group, and the following rules are defined: - a combination of the aforementioned code bit group of the aforementioned code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit group to which the code bit group is allocated That is, the group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; © the m bit is 12 a bit in the case where the integer b is 2, and 12 bits of the code bit are mapped to one of 212, ie, 4096 signal points, as one of the symbols, in the foregoing row of the memory mechanism The group of the preceding code bits of the 12x2 bit read by the direction is divided into three groups of the aforementioned code bit groups; the preceding symbol bit group of the 12x2 bits of the consecutive two preceding symbols is divided into six symbols. Bit group; 〇 In the foregoing distribution rules, there are: The 1st bit of the code bit of the probability good first bit group is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability first good code The 1 bit of the code bit of the bit group is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; the code of the 2nd good code bit group of the error probability 4 bits of the bit 133671.doc -66- 200947881 The 4th bit of the symbol bit assigned to the first good symbol group of the error probability; the second probability of the error probability group The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the 2nd good symbol bit group of the error probability; 4 bits of the code bit of the 2nd good code bit group of the error probability The element is assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; ® the 3 bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability The 3th bit of the symbol bit of the 4th good symbol bit group; the 2 bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error The probability of the 5th good symbol group of the symbol bit is 2 bits; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 2nd good character 1 bit of the symbol bit of the meta-bit group; 1 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 4th good symbol bit group 1 bit of the symbol bit; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the symbol bit of the 5th good symbol bit group of the error probability 1 bit; and the 3 bits of the code bit of the 3rd good code bit group of the error probability 133671.doc -67- 200947881 assigned to the error probability 6th good symbol bit group 3 yuan of yuan. 30. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction stores mb bits, and the N/(mb) bit is memorized in the preceding direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row. Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to Representing the allocation rule of the symbol element of the preceding symbol, replacing the code bit of the aforementioned mb bit, and replacing the replaced code bit as the aforementioned symbol bit; ® the aforementioned LDPC code system DVB-S.2 or DVB- The code length N specified by the specification of T.2 is 64,800 bits, and the coding rate is 3/4. LDPC code; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; The memory mechanism contains 24 vertical lines of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction; 133671.doc •68- 200947881 The former replacement mechanism is in the rank of the aforementioned memory mechanism The 12x2 bit code bit read by the direction is set to the bit ratio from the most significant bit, and the 12th bit of the preceding two symbols is the highest. The effective bit is calculated as the i+1th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit y10, and the bit b! is assigned to the bit y8 Bit b2 is assigned to bit y〇, Assigning bit b3 to bit y], assigning bit b4 to bit y2, assigning bit b5 to bit y3, assigning bit b6 to bit y4, and assigning bit b7 to bit y5 , the bit b8 is assigned to the bit y6, the bit b9 is assigned to the bit y7, the bit b1Q is assigned to the bit y9, and the bit b is! Assigned to bit y12, bit b12 is assigned to bit y13, bit b13 is assigned to bit y14, bit b14 is assigned to bit y16, bit b15 is assigned to bit y17, bit b16 is assigned Assigned to bit y18, bit b17 is assigned to bit y20, bit b! 8 is assigned to bit yi 5, 133671.doc -69- 200947881, bit b! 9 is assigned to bit y! i, The bit b2G is assigned to the bit y22, the bit b2! is assigned to the bit yi 9, the bit b22 is assigned to the bit y21, and the bit b23 is assigned to the bit y23. 3 1. A data processing device comprising a replacement mechanism for a coded bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read by the memory mechanism in the preceding direction is read as one symbol, and the specific positive integer is b, the memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, w is used to code the bits of the aforementioned LDPC code. The element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or LDPC code with a code length N specified by the specification of DVB-T.2 of 16,200 bits The foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and the group 133671.doc -70-200947881 according to the error probability is distinguished from the group of the aforementioned symbol bits. As a group of symbol bits, a rule is defined as follows: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit of the foregoing symbol bit element of the code bit element to which the code bit group is allocated The combination of the meta-groups, that is, the group set, and the foregoing code bit group of the foregoing group set and the bit number of the foregoing symbol bit group and the bit number of the foregoing symbol bit; Where the m bit is 12 bits, and the integer b is 2, and 12 bits of the code bit unit are mapped as one of the aforementioned symbols to 212, that is, 4096 signal points, in the foregoing The group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into three groups of the aforementioned code bits; the preceding symbol group of 12x2 bits of two consecutive symbols Divided into 6 symbol group; specified in the foregoing distribution rules : assigning the 2-bit of the code bit of the first good symbol bit group of the error probability to the 2-bit of the symbol bit of the first good symbol bit group of the error probability; 1 The 3 bits of the code bit of the good code bit group are assigned to the 3 bit of the symbol bit of the 2nd good symbol bit group of the error probability; the error probability first good code bit element The 4 bits of the code bit of the group are assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; 133671.doc -71- 200947881 The error probability is 1st good code position The 4 bits of the code bit of the metagroup are assigned to the 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; the code bit of the code group of the first good error bit of the error probability The 1st bit of the element is allocated to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the 4 bit of the code bit of the 1st good code bit group of the error probability is assigned Give the 4th bit of the symbol bit of the 6th good symbol bit group of the error probability; 1 bit of the code bit of the 2nd good code bit group of the error probability Assigning 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; assigning the 2 bits of the code bit of the 3rd good code bit group of the error probability to the error probability first good 2 bits of the symbol bit of the symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the second probability symbol group of the error probability 1 bit of the symbol bit of the group; and 2 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the symbol bit of the 5th good symbol bit group of the error probability 2 yuan of yuan. 3 2. A data processing apparatus, comprising: a replacement mechanism, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction 133671.doc -72- 200947881 The m-bit of the code bit of the LDPC code read in the preceding row direction and written in the preceding row direction is regarded as one symbol, a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the foregoing course direction, and in the case where the code bits of the mb bits read in the direction of the preceding direction of the memory mechanism are regarded as consecutive b symbols, The code bit of the LDPC code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, and replaces the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB The code length N specified by the specification of -S.2 or DVB-T.2 is 162. 00 bit, LDPC code with a coding rate of 4/5; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols Any one of 4096 signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; the foregoing replacement mechanism is in the foregoing memory mechanism The 12x2 bit code bit read from the horizontal direction is set to the bit bi from the most significant bit, and the 12x2 bits of the preceding two symbols are consecutively. The element is calculated from the most significant bit, and the i+1th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: 133671.doc -73- 200947881 The bit b〇 is assigned to the bit y〇, and the bit is The element b! is assigned to the bit y 1, the bit b2 is assigned to the bit y2, the bit b3 is assigned to the bit y3, the bit b4 is assigned to the bit y4, and the bit b5 is assigned to the bit y5, Bit b6 is assigned to bit y6, bit b7 is assigned to bit y7, bit b8 is assigned to bit y8, and bit b9 is assigned to bit y 1 〇, The bit b! 〇 is assigned to the bit y 11, the bit th! is assigned to the bit yi4, the bit b! 2 is assigned to the bit y 1 6, and the bit b! 3 is assigned to the bit y 17, The bit b ! 4 is assigned to the bit y 1 8, the bit b 5 is assigned to the bit y 19 , the bit b ! 6 is assigned to the bit y22 , and the bit b 1 7 is assigned to the bit y23 , assigning bit b! 8 to bit y 9, assigning bit bi9 to bit y2 〇, assigning bit b2G to bit y 1 2, and assigning bit b21 to bit y 13, bit Element b22 is assigned to bit y 1 5 and bit b23 is assigned to bit y2 1. 200947881 33. A data processing apparatus, comprising: a replacement mechanism, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The code length specified in the specification of .2 is 64,800 bits. a DPC code; the foregoing allocation rule is to group a group of the foregoing code bit groups according to an error probability as a code bit group, and group the group of the aforementioned symbol bits according to an error probability as a symbol bit a tuple group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit group of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination, that is, a group set, and 133671.doc • 75- 200947881, the aforementioned code bit group of the foregoing group set and the foregoing code bit of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; Where the m-bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of the 212 symbols, ie, 4096 signal points, as one of the symbols, The group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into five groups of the preceding code bits; the preceding group of symbol bits of 12x2 bits of two consecutive symbols The group is divided into 6 symbol group; © in the foregoing distribution rules There is: assigning 1 bit of the code bit of the first good code bit group of the error probability to the 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; The 1st bit of the code bit of the 1st good code bit group is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; 〇 the error probability 2nd good code The 1 bit of the code bit of the bit group is allocated to the 1st bit of the symbol bit of the first good symbol bit group of the error probability; the error probability is the 3rd good code bit group The 3 bits of the code bit are assigned to the 3 bits of the symbol bit of the first good symbol bit group of the error probability; 4 bits of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability 133671.doc • 76· 200947881 yuan; the code bit of the 3rd good code bit group of the error probability 3 The bit is allocated to the 3-bit symbol of the symbol element of the 3rd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is obtained The 4 bits are allocated to the 4th bit of the symbol bit of the 4th good symbol group of the error probability; the 2nd bit of the code bit of the 3rd good code bit group of the error probability is © The allocation of the symbolic probability of the 5th good symbol bit group of the error element is 2 yuan; the error probability of the 4th good code bit group of the code bit is assigned to the error probability 3rd good 1 bit of the symbol bit of the symbol group; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the 5th good symbol group of the error probability 1 bit of the symbol bit of the group; and 3 assign the 3 bits of the code bit of the 5th good code bit group of the error probability to the symbol of the 6th good symbol group of the error probability 3 bits of the bit. 34. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding direction is read as one symbol, and the specific positive integer is set to 133671.doc -77-200947881. b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, © the replaced code bit as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 64800 The LDPC code having a coding rate of 4/5; the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to 4096 determined by 4096QAM. Any one of the signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the row direction and 64800/(12x2) bits in the wales direction; ® the replacement mechanism is in the foregoing memory mechanism The 12x2 bit code bit read in the course direction is set to the bit bi from the most significant bit, and the symbol bits of the 12x2 bits of the preceding two symbols are consecutively The i+th bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y10, and the bit b! is assigned to the bit y 8. 133671.doc -78- 200947881 assigning bit b2 to bit y, assigning bit b3 to bit y 1, assigning bit b4 to bit y2, and assigning bit b 5 to bit y 3 , assigning bit b6 to bit y4, assigning bit b7 to bit y5, assigning bit b 8 to bit y 6, assigning bit b9 to Yuan y7, The bit b丨〇 is assigned to the bit y9, the bit b!! is assigned to the bit y! 2, the bit b! 2 is assigned to the bit y 13, and the bit b! 3 is assigned to the bit y 4, assign bit b! 4 to bit y 15, assign bit bi 5 to bit y! 6, assign bit b! 6 to bit yi 8, assign bit b! 7 to Bit y 19, assigning bit b! 8 to bit y2 〇, assigning bit b! 9 to bit y! 7, assigning bit b2 〇 to bit y2 1, assigning bit b21 to Bit y 11, bit b22 is assigned to bit y22, and bit b23 is assigned to bit y23. 35. A data processing apparatus comprising a replacement mechanism for LDPC having a memory code length of N bits in a row direction and a longitudinal direction (Low 133671.doc -79-200947881 Density Parity Check) The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means of the code bit in the preceding direction is set as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, And after reading in the foregoing course direction, and the code © bit of the mb bit read in the foregoing direction of the memory mechanism is regarded as consecutive b symbols, according to the LDPC code used for The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 1620 a 0-bit LDPC code; the foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and the group w will be distinguished according to the error probability. The group is a group of symbol bits, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the aforementioned symbol bit of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of the meta-bit group, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of the foregoing symbol bit group and the bit number of the foregoing symbol bit; 133671 .doc -80- 200947881 wherein the m-bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as 212 symbols or 4096 signal points as one of the preceding symbols. In one case, the group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; 12x2 bits of two consecutive symbols are consecutively The preceding symbol bit group is divided into 6 symbol bit groups; The matching rules stipulate that: ® assigns 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability. Assigning 4 bits of the code bit of the second good code bit group of the error probability to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; The 3 bits of the code bit of the good code bit group are assigned to the 3rd bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 2nd good code bit of the error probability The 3 bits of the code bit of the group are allocated to the 3 bits of the symbol bit of the 3rd good symbol bit group of the error probability; the code bit of the 2nd good code bit group of the error probability The 3 bits are allocated to the 3 bits of the symbol bit of the 4th good symbol bit group of the error probability; the 3 bit of the code bit of the 2nd good code bit group of the error probability is 133671 .doc -81 · 200947881 The 3rd bit of the symbol bit of the 5th good symbol group of the error probability; the 2nd good code bit of the error probability The 2 bits of the group of code bits are assigned to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability; the code bit of the error probability 3rd good code bit group is 1 bit is assigned to 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to The error probability is the 1st bit of the symbol bit of the 2nd good symbol group; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 3rd good 1 bit of the symbol bit of the symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the error probability 4th good symbol group 1 bit unit of the symbol bit; and 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to the symbol bit of the 6th good symbol group of the error probability One yuan of yuan. 36. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding direction is read as 133671.doc -82- 200947881, and the specific positive integer is set as one symbol. b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing course direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, ® is used to use the aforementioned LDPC code. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 1620 0 bit, LDPC code with a coding rate of 5/6; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols Any one of 4096 signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; the foregoing replacement mechanism is in the foregoing memory mechanism The 12x2 bit code bit read from the horizontal direction is set to the bit bi from the most significant bit, and the 12x2 bits of the preceding two symbols are consecutively. The element is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y! 〇, 133671.doc •83- 200947881 The element b! is assigned to the bit y 〇, the bit b2 is assigned to the bit y 1, the bit b3 is assigned to the bit y2, the bit b4 is assigned to the bit y3, and the bit b5 is assigned to the bit y4 , bit b6 is assigned to bit y5, bit b7 is assigned to bit y6, bit b8 is assigned to bit y7, bit b9 is assigned to bit Y8, assigning bit b 1 〇 to bit y9, assigning bit b 1! to bit y 11, assigning bit b! 2 to bit y 1 2, and assigning bit bi 3 to bit y 13, assign bit b ! 4 to bit y 1 4, assign bit b! 5 to bit y 1 6, assign bit b! 6 to bit y 18, place bit b!7 Assigned to bit y2〇, bit bi 8 is assigned to bit y22, bit b! 9 is assigned to bit y 2 1, bit b2G is assigned to bit y23, bit 1 is assigned to bit y 1 9, the bit b22 is assigned to the bit y 17, and the bit b23 is assigned to the bit y 1 5. 37. A data processing device comprising a replacement mechanism, which is -84- 133671.doc 200947881 The memory mechanism of the LDPC (Low Density Parity Check) code memory element having a length of N bits in the horizontal direction and the longitudinal direction is written in the preceding direction. The m-bit of the code bit of the LDPC code read in the horizontal direction is regarded as one symbol, and the specific positive integer is set to b*. The memory mechanism memorizes mb bits in the foregoing direction, and The wandering direction memory N/(mb) bit, the code bit of the LDPC code is written in the wale direction of the memory mechanism, and then read in the row direction, and in the foregoing row of the memory mechanism In the case where the code bits of the mb bits read by the direction are regarded as consecutive b symbols, according to the allocation rule for assigning the code bits of the LDPC code to the symbol bits representing the symbols, Replace the code bit of the mb bit, and replace the code bit as the symbol bit; the code length N specified by the LDPC code system DVB-S.2 or DVB-T.2 is 64800 bits. LDPC code of the element; the foregoing allocation rules will be grouped according to the error probability The group of the foregoing code bit groups is used as a group of code bit groups, and a group of the foregoing symbol bit groups is grouped according to an error probability as a group of symbol bit groups, and the following rules are defined: a combination of the foregoing code bit group and the foregoing symbol bit group of the aforementioned symbol bit of the code bit group of the code bit group, that is, a group set, and the foregoing code of the foregoing group set a bit group and the foregoing symbol bit group 133671.doc -85- 200947881 respective bit numbers of the foregoing code bits and the foregoing symbol bits; wherein the m bits are 12 bits, and the aforementioned integer b In the case where 2, 12 bits of the code bit are mapped to one of 212, ie, 4096 signal points, as one of the symbols, 12x2 bits read in the direction of the memory mechanism The foregoing code bit group of the element is divided into three groups of the foregoing code bit groups; the foregoing symbol bit group of 12 X 2 bits of two consecutive symbols is divided into six symbol bit groups; In the foregoing allocation rule, the code position of the code group of the first good error probability is specified. One bit is allocated to one bit of the symbol bit of the fourth good symbol bit group of the error probability; the one bit of the code bit of the first good code bit group of the error probability is assigned to The error probability is 6th good symbol bit of the symbol group of the sixth bit; the 4th bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability 1st good 4 bits of the symbol bit of the symbol bit group; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error probability 2nd good symbol bit group 4 bits of the symbol bit; assign 4 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the 3rd good symbol bit group of the error probability 4 bits; 133671.doc -86- 200947881 assigns the 2 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the 4th good symbol bit group of the error probability 2 bits; assign 4 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the 5th good symbol bit group of the error probability 4 bits; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; And assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the 3 bit of the symbol bit of the 6th good symbol bit group of the error probability. 3 8. A data processing device comprising a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding direction by the memory means is read as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row The direction is read, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, 133671.doc -87·200947881 is used to use the aforementioned LDPC The code bit of the code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB- The code length N specified by the specifications of S.2 or DVB-T.2 is 64800 bits, LDPC code with a coding rate of 5/6; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols. Any one of 4096 signal points; the memory mechanism includes 24 vertical lines of 12x2 bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction; the aforementioned replacement mechanism is in the foregoing memory The 12x2 bit code bit read by the direction of the mechanism is set to the bit bi from the most significant bit, and the symbol of 12x2 bits of the preceding two symbols is consecutively The bit is calculated from the most significant bit, and the i+1th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y! 〇, 分配 the bit b! is assigned to Bit y 6, assigning bit b2 to bit y, assigning bit b3 to bit y!, assigning bit b4 to bit y2, assigning bit b5 to bit y3, and placing bit B6 is assigned to bit y4, bit b7 is assigned to bit y5, and bit b 8 is assigned to bit y 7, 133671.doc -88- 200947881 bit b9 The bit ys is allocated, the bit bt 〇 is assigned to the bit y9, the bit b η is assigned to the bit y! 2, the bit b! 2 is assigned to the bit y 13, and the bit b 13 is assigned to the bit Yuan yi 4, assigning bit bi 4 to bit y 15, assigning bit b! 5 to bit yi 6, assigning bit b! 6 to bit y丨7, The bit b} 7 is assigned to the bit y! 8, the bit b! 8 is assigned to the bit y20, the bit b! 9 is assigned to the bit y21, and the bit b2 is assigned to the bit y11. The bit b21 is assigned to the bit y22, the bit b22 is assigned to the bit y 1 9, and the bit b23 is assigned to the bit y23. 39. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction stores mb bits, and the N/(mb) bit is memorized in the longitudinal direction, and the code bits of the LDPC code are written in the foregoing vertical direction of the memory mechanism 133671.doc -89·200947881, After reading in the foregoing direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 16200 The LDPC code of the element; the foregoing allocation rule is to group the group of the aforementioned code bits ® as a group of code bits according to the error probability, and group the group of the preceding symbol bits according to the error probability as a group a symbol bit group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the group set and the symbol bit group of the foregoing symbol bit group and the number of bits of the foregoing symbol bit; y is in the foregoing The m-bit is 12-bit, and the integer b is 2, and the 12-bit of the above-mentioned code bit is mapped as one of 212 symbols, that is, 4096 signal points, as one of the aforementioned symbols, in the foregoing memory. The group of code bits of the 12x2 bit read out in the foregoing direction of the mechanism is divided into five groups of the aforementioned code bits; the preceding symbol group group of 12x2 bits of two consecutive symbols Is a group of 6 symbol bits; 133671.doc -90- 200947881 The matching rule stipulates: assigning 2 bits of the code bit of the first good symbol bit group of the error probability to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; Assigning 1 bit of the code bit of the second good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability; 4 bits of the code bit of the code bit group® assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the third probability good bit group of the error probability The 4 bits of the group of code bits are assigned to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is 4 bits are allocated to 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the error The 4th bit of the symbol bit of the 4th good symbol bit group of the probabilities; the 2 bits of the code bit of the 3rd good code bit group of the error probability are assigned to The error probability is the 5th good symbol of the symbolic bit group of the 5th bit; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 5th good 1 bit 133671.doc -91 - 200947881 yuan of the symbol bit group of the symbol element group; assign 1 bit of the code bit element of the 5th good code bit group of the error probability to the error probability 5th good 1 bit of the symbol bit of the symbol group; and assign 1 bit of the code bit of the 5th good code bit group of the error probability to the 6th good symbol bit of the error probability One bit of the symbol bit of the group. 40. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 LDPC with a code length N of 16200 bits and a coding rate of 8/9 , 133671.doc -92- 200947881 The m-bit is 12 bits, and the aforementioned integer b is 2; the 12-bit of the aforementioned code bit is mapped as one of the aforementioned symbols to 4096 signal points determined by 4096QAM. The memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the wales direction; the replacement mechanism is read in the direction of the memory mechanism The 12x2 bit code bit is set to the bit ratio from the most significant bit, and the 12x2 bit of the preceding two symbols is from the most significant bit. From the first calculation, the i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit yi〇, the bit b! is assigned to the bit yi 1, and the bit is The element b2 is assigned to the bit y22, the bit b3 is assigned to the bit y, the bit b4 is assigned to the bit y 1, the bit b5 is assigned to the bit y2, and the bit b6 is assigned to the bit y3, Bit b7 is assigned to bit y4, bit b 8 is assigned to bit y 5 , bit b9 is assigned to bit y6, bit b 1 is assigned Assigned to bit y7, bit p!! is assigned to bit y8, bit b! 2 is assigned to bit y9, bit b! 3 is assigned to bit y! 2, 133671.doc -93- 200947881 assigns bit b 14 to bit y 13, assigns bit b! 5 to bit y! 4, assigns bit b! 6 to bit yi 5, assigns bit b! 7 to bit Yi 6, assigning bit b18 to bit y17, assigning bit b! 9 to bit y 18, assigning bit b2 〇 to bit y 19, and assigning bit b21 to bit y2 〇, Bit b22 is assigned to bit y21, and bit b23 is assigned to bit y23. 41. A data processing apparatus comprising: a replacement mechanism for a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to represent the aforementioned symbols. The allocation rule of the meta-bits of the meta-substitutes replaces the code bits of the aforementioned mb bits, 133671.doc -94- 200947881 replaces the replaced code bits as the aforementioned symbol bits; the aforementioned LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 64800 bits. The LDPC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol a group of bits, and the following rules are defined: the foregoing group of code bits of the aforementioned code bit group and the aforementioned symbol bit group of the aforementioned symbol bit of the code bit group to which the code bit group is allocated The combination is the group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; 12-bit, and the integer b is 2, and 12 bits of the code bit are mapped to one of 212, ie, 4096 signal points, as one of the aforementioned symbols, in the case of the aforementioned memory mechanism The group of the preceding code bits of the 12x2 bit read in the column direction is divided into five groups of the aforementioned code bits; the group of the preceding symbol bits of the 12x2 bits of the consecutive two preceding symbols is divided into six characters. Meta-bit group; specified in the foregoing allocation rules: 1 2 bits of the code bit of the good code bit group are assigned to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; the 2nd good code bit of the error probability 1 bit of the code bit of the group 133671.doc -95- 200947881 The 1st bit of the symbol bit of the 6th good symbol group of the error probability; the 3rd good code position of the error probability The 4 bits of the code bit of the metagroup are assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is The 4th bit of the element is allocated to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 4 bit of the code bit of the 3rd good code bit group of the error probability is allocated The 4th bit of the symbol bit of the symbol group of the 3rd good symbol of the error probability is assigned; the 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 4th good 4 bits of the symbol bit of the symbol group; assign the 2 bits of the code bit of the 3rd good code bit group of the error probability to the error probability 5th 2 bits of the symbol bit of the good symbol group; assign 1 bit of the code bit of the 4th good code bit group of the error probability to the 5th good symbol bit of the error probability 1 bit of the symbol bit of the group; 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the symbol bit of the 5th good symbol bit group of the error probability 1 bit of the element; and 1 bit of the code bit of the 5th good code bit group of the error probability 200947881 is assigned to the 1st bit of the symbol bit of the 6th good symbol group of the error probability yuan. 42. A data processing apparatus, comprising: a replacement mechanism for storing memory bits of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, ◎ the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is 64,800 bits and the coding rate is 8. LDPC code of /9; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 signal points determined by 4096QAM The memory mechanism includes 24 vertical rows of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction; 133671.doc 97·200947881 The foregoing replacement mechanism is transverse to the aforementioned memory mechanism The code bit of the 12x2 bit 读出 read in the column direction is set to the bit bi ' from the most significant bit, and the symbol of 2 x 2 bits of the preceding two symbols is consecutively 2 The bit is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit b 〇 is assigned to the bit y 1 〇, and the bit b 丨 is assigned to Bit y, assign bit b2 to bit y22, bit b3 to bit y, assign bit b4 to bit yj, assign bit b5 to bit y2, place bit B6 is assigned to bit y3, bit b7 is assigned to bit y4, bit b8 is assigned to bit y5, bit bs&gt; is assigned to bit y6 Assigning bit b 1 〇 to bit y 7, assigning bit b! 1 to bit y 8, assigning bit b! 2 to bit y9, and assigning bit b! 3 to bit yi 2 , bit b14 is assigned to bit y13, bit b! 5 is assigned to bit yi 4, bit b16 is assigned to bit y15, bit b! 7 is assigned to bit y! 6, bit is placed Element b! 8 is assigned to bit y! 7, 133671.doc -98- 200947881 assigns bit b! 9 to bit y 18, bit b2 〇 to bit y 19, assigns bit b21 to Bit y2 〇, bit b22 is assigned to bit y21, and bit b23 is assigned to bit y23. 43. A data processing apparatus comprising: a replacement mechanism for recording a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding row direction written in the preceding direction is used as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Directionally reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is 64800 bits 兀 LDPC code; The matching rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and the group of 133671.doc -99-200947881 is distinguished according to the error probability as the group of the preceding symbol bits. a symbol bit group, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the element is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of the aforementioned symbols to 212, that is, any one of 4096 signal points, the foregoing memory The group of code bits of 12 X 2 bits read in the foregoing direction of the mechanism is divided into 5 groups of the aforementioned code bits; the aforementioned symbol group of 12 x 2 bits of the preceding two symbols The group is divided into 6 symbol group; as stated in the foregoing allocation rules: The 2 bits of the code bit of the first good code bit group of the error probability are assigned to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; the error probability is 2nd good. 1 bit of the code bit of the code bit group is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability 3rd good code bit group The 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; 133671.doc -100- 200947881 The error probability 3rd good code bit group The 4 bits of the group of code bits are assigned to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is 4 bits are allocated to 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to the error The 4th bit of the symbol bit of the 4th good symbol bit group of the probabilities is allocated to the 2 bits of the code bit of the 3rd good code bit group of the error probability The probability of the 5th good symbol bit group of the symbol bit is 2 bits; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 6th good 1 bit of the symbol bit of the symbol group; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the error probability 5th good symbol bit group 1 bit of the symbol bit of the group; and assign 1 bit of the code bit of the 5th good code bit group of the error probability to the symbol bit of the 6th good symbol bit group of the error probability One yuan of yuan. 44. A data processing apparatus comprising: a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction; .doc -101 - 200947881 The m-bit of the code bit of the LDPC code read in the preceding row direction written in the preceding direction is regarded as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing course direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, ® is used to use the aforementioned LDPC code. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by the .2 or DVB-T.2 specification is 64. 800 bit, LDPC code with a coding rate of 9/10; the m bit is 12 bits, and the aforementioned integer b is 2; 12 bits of the above code bit are mapped as 前述4096QAM as one of the aforementioned symbols Determining any one of 4096 signal points; V The memory mechanism contains 24 wales of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the waling direction; The 12x2 bit code bit read by the direction of the memory mechanism is set to the bit bi from the most significant bit, and the 12x2 bit of the preceding symbol is consecutively The i-th bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: 133671.doc -102- 200947881 Assigning bit b〇 to bit y 1 〇, assigning bit b! to bit y! i, assigning bit b2 to bit ys, and assigning bit b3 to bit y, bit B4 is assigned to bit y 1, bit b5 is assigned to bit y2, bit b6 is assigned to bit y3, bit b7 is assigned to bit y4, bit b 8 is assigned to bit y 5, Bit b9 is assigned to bit y6, bit b 1 〇 is assigned to bit y7, bit bii is assigned to bit y9, bit bi 2 is assigned to bit y! 2, bit b 13 Assigned to bit y 13, assign bit b ! 4 to bit y 1 4, assign bit b! 5 to bit y 1 5, assign bit b! 6 to bit y 〖6, will Bit b 17 is assigned to bit y 17, bit b! 8 is assigned to bit y! 8, bit bi9 is assigned to bit y 19, bit b2 is assigned to bit y2, bit is set The element b21 is assigned to the bit y22, the bit b22 is assigned to the bit y23, and the bit b23 is assigned to the bit y2 1. The data processing apparatus according to any one of claims 1 to 44, wherein the LDPC code is an LDPC code obtained by performing LDPC encoding, and the LDPC encoding is in accordance with an LDPC code. The portion corresponding to the bit element, that is, the parity matrix is a check matrix of the ladder structure; further comprising a co-located interleaving mechanism for performing the co-interleaving of the same bit of the LDPC code to the position of the other co-located bit. 46. The data processing device of claim 45, wherein the number of bits of the parity bit of the LDPC code is a value other than a prime number, and the number of bits of the same bit is 1 and 2 of the number other than the number of the same bit The two divisors of the number of bits and the number of bits of the aforesaid bit are Ρ and q, and the number of bits of the information bit of the LDPC code is K, 0 or more is less than the integer of P is X, and 0 or less is less than When the integer of q is y, the co-located interleaving mechanism interleaves the K+1th to K+M code bits of the LDPC code, that is, the Κ+qx+y+1 code bits in the same bit to the first K+Py+x+1 code bit positions. The data processing apparatus of any one of claims 1 to 44, further comprising a rearrangement mechanism for rearranging the rearrangement of the code bits of the aforementioned LDPC code to avoid the check of the LDPC code The complex digital bit corresponding to 1 of any one of the columns of the matrix is included in the same symbol. The data processing device according to any one of claims 1 to 44, wherein the LDPC code is a part of the check matrix of the LDPC code corresponding to the information bit of the LDPC code, that is, the information matrix is a loop structure 133671.doc An LDPC code of -104-200947881; further comprising a rearrangement mechanism for performing a vertical twist interleave as a rearrangement process for rearranging code bits of the LDPC code, wherein the vertical twist interlace is coupled to the longitudinal direction of the memory mechanism In the row direction, the start writing position at the time of writing the code bit of the LDPC code is performed for each wales of the memory means. 49. The data processing apparatus of claim 48, wherein a part of the check matrix of the LDPC code corresponding to the parity bit of the LDPC code, that is, a parity matrix is a part of the parity matrix that is replaced by a row, A pseudo-loop structure of a cyclic structure. 50. The data processing device of claim 49, wherein the co-located matrix is a stepped structure and is replaced by a row to form the pseudo-loop structure. 51. The data processing apparatus of claim 50, further comprising a co-located interleaving mechanism that performs a co-interleaving of interleaving the co-located bits of the LDPC code to locations of other co-located bits; the rearrangement mechanism interleaving the co-located bits The aforementioned LDPC code is used as the object to perform the above-described directional twist interleaving. 52. The data processing device of claim 5, wherein the number of bits of the parity bit of the LDPC code is a value other than a prime number, and the number of bits of the aforesaid bit is set to be one of the number of bits of the same bit The two divisors of the two divisors and the number of bits of the aforesaid parity are Ρ and q, and the number of bits of the information bits of the LDPC code is K, 133671.doc -105 - 200947881 0 or more is less than P When the integer is X, and the integer above 0 is less than q, the co-located interleaving mechanism is the +1+qx+y+ of the K+1th to K+M code bits of the LDPC code, that is, the same bit. l code bits are interleaved to the position of the K+Py+x+1 megabits. 53. The data processing apparatus of claim 48, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is an LDPC code of 64,800 bits, and the m bit is 10 a bit, and the integer b is 2, and the 10-bit code bit of the LDPC code is mapped to any one of 1024 signal points determined by a specific modulation mode, and the memory mechanism is stored in the horizontal direction memory. 20 vertexes of 10x2 bits, in the case of memory 64800/(10x2) bits in the wale direction, the rearrangement mechanism is located at the address of the opening position in the longitudinal direction of the memory mechanism, and is 0. When the integer of the ascending order indicates the address of each position of the longitudinal direction of the memory mechanism, the start position of the first wales of the 20 wales of the memory means is set to the position where the address is 0, and the memory mechanism is used. The start position of the second wales of the 20 wales is the position where the address is 1, and the start position of the third wales of the 20 wales of the memory mechanism is the position where the address is 3, Write the beginning of the 4th wales of the 20 wales of the aforementioned memory mechanism to 133671.do c • 106· 200947881 Ο 作为 作为 作为 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位 位The sixth wales are set to the position where the address is 6, and the seventh wales of the 20 wales of the memory mechanism are set to the address of the address 6, and the wales of the memory mechanism are 20 wales. The eighth longitudinal direction is set to the position where the address is 9, and the ninth vertical line of the 20 wales of the memory mechanism is set to the position where the address is 13, and the monthly il The 10th vertical line of the squadron is set to the position of 14 and the start of the 11th wales of the 20 cups and girders of the memory mechanism is set as the address of 14 The 12th vertical line of the above-mentioned memory mechanism is placed in the position of address 16 as the start of the write start of the start of the write start of the write start of the write start of the write to write the above memory The twentieth of the organization's 20 彡 _ 仃 第 置 置 作为 作为 第 第 第 第 第 第 第 第 第 第 第 第 第 第Recall that the 20 locations of the mechanism are located at address 21, and the 20 vertical 彳 f + of the memory mechanism is set to the address of 23, and the 15th wales of the 14th trajectory of the trajectory are written. At the beginning, write the 16th latitude of the 20 towns in the memory mechanism. Start to write the bit bit. The bit is 133671.doc • 107- 200947881 is set as the address 25 a position where the start position of the 17th wales of the 20 wales of the memory mechanism is the address of the address 25, and the start position of the 18th wales of the 20 wales of the memory mechanism is used as the start position. The address of the address is 26, and the start writing position of the 19th wales of the 20 wales of the memory mechanism is the position of the address of 28, and the 20th wales of the 20 wales of the memory mechanism are Start writing the location as the location with the address 30. 54. The data processing apparatus of claim 48, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is 6 4 800 bit LDPC Ma' aforementioned m The bit element is 12 bits, and the integer b is 2, and the 12-bit code bit of the LDPC code is mapped to any one of 4096 signal points determined by a specific modulation mode, and the memory mechanism is included in 24 rows of 12x2 bits are stored in the horizontal direction, and 64800/(12x2) bits are stored in the wale direction. The rearrangement mechanism is located at the beginning of the longitudinal direction of the memory mechanism. 0, when the address of each position in the wale direction of the memory means is represented by an integer in ascending order, the start position of the first wales of the 24 wales of the memory means is set to the position where the address is 0, The start of the second wales in the 24 wales of the memory mechanism is 133671.doc -108- 200947881. The address is 5, and the third of the 24 vertical V- 记忆 of the memory mechanism will be described. The vertical position is set to the position of 8 and the middle of the 24 wales of the aforementioned memory mechanism (longitudinal When the address is 8, the start write bit of the start write bit writes the 24 bits of the memory mechanism to the beginning of the 5th ordinate of the position where the address is 8 ❹ ❹ The opening of the 6th vertical line of the 24 vertical lines of the organization should be set as the position with the address of 8,] the position will be set as the position of the 24 vertical lines of the aforementioned memory organization. At the position of 10, the 第 position sets the 8th vertical row of the 24 乡 丄 1 solid 仃 前述 of the memory mechanism as the address of the address 10, and the 24 memory γ 丄 前述 前述 前述The ninth longitudinal row is set to the position where the address is 10, and the tenth longitudinal row of the 24 vertical longitudinals of the memory mechanism is set to the position of the address of 12, and the memory of the 24 towns # ^ The 11th vertical line in the defeat is set to the position where the address is 13, and the beginning of the write bit begins with the start of the write bit. The write bit sets the 24 memory devices, and the value is set to the address. For the position of 16, the 24 wales f of the aforementioned memory mechanism are set to the position where the address is 17, and the foregoing Recall that the 12th vertical of the mechanism is the beginning of the 12th ordinate of the 12th ordinate. The beginning of the 13th ordinate is written at the beginning of the 14th traverse. 133671.doc •109·200947881 is set as the address of 19 The start position of the 15th wales of the 24 wales of the memory mechanism is taken as the address of the address 21, and the 24 call lines of the memory mechanism are set to the position of the address of 22, and the memory mechanism is used. The 24 longitudinal positions are set to the position where the address is 23, and the starting position of the 18th latitude in the 24 memory mechanisms, _ • moxibustion is used as the address of the address 26, and the memory mechanism is The starting position of the 19th latitude in the 24 townships is the position of the address 37, and the writing position of the 20th wales of the 24 嘥v-丄U gorges of the aforementioned memory mechanism is written. As a position where the address is 39, the start write position of the 17th ordinate in the start write bit of the 16th wales of the 24 wales of the memory mechanism is set as the address of the address 40, At the beginning of the 21st wales, write the position 55. The 22nd wales of the 24 wales of the aforementioned memory mechanism The position is 41, and the 23rd wales of the 24 wales of the memory mechanism are set to the position of the address 41, and the 24th wales of the 24 wales of the memory mechanism are set as The address is at the location of 41. The data processing device of claim 48, wherein the code length N defined by the specification of the UDPC code system, DVB-S.2 or DVB_T 2 is 16200 bits, and the start of the write bit begins. Write bit 〇 133671.doc -110- 200947881 The m-bit is 10 bits ' and the aforementioned integer b is 2, and the code bits of the 10 bits of tlC code are mapped to be determined by a specific modulation method. Any one of 1024 signal points, and the memory mechanism contains 2 纵 wales of 1 〇χ 2 bits in the horizontal direction, and 162 〇 0 / (1 〇 &gt;&lt; 2) in the longitudinal direction In the case of a bit, the rearrangement mechanism is located at the beginning of the longitudinal direction of the memory mechanism. 0, when the address of each position in the wale direction of the memory mechanism is represented by an integer in ascending order, the start of the third ordinate in the start of the second ordinate in the first write of the first walt The start of the eighth vertical line in the beginning of the fifth vertical line in the beginning of the write position of the fifth vertical line in the write position of the sixth vertical line in the beginning of the write line of the seventh vertical line The writing bit sets 20 longitudinal lines of the memory mechanism as the position where the address is 0, 20 wales of the memory mechanism are set to the position where the address is 0, and 20 vertical lines of the memory mechanism are set as bits. Where the address is 0, the 20 vertical lines of the memory mechanism are set to the position where the address is 2, and the 20 vertical lines of the memory mechanism are set to the position where the address is 2, and the longitudinal direction of the memory mechanism is 20 The row is set to the position where the address is 2, and the 20 vertical lines of the memory mechanism are set to the position where the address is 2, and the 2 vertical lines 133671.doc -111 - 200947881 of the memory mechanism are set as the address. In the position of 2, the ninth longitudinal row of the 20 坳1 仃 仃 of the aforementioned memory mechanism is opened. The write position is the position where the address is 5, and the 20 verticals of the mechanism set the memory as the position where the address is 5, and the start of the 10th vertical line in the middle writes the 20 pieces of the memory mechanism of the memory mechanism. The starting write position of the eleventh wales in the girders is the position where the address is 5, and the 20 wales of the memory mechanism are set to the position where the address is 5, and the start of the 12th waling is the aforementioned The starting position of the 13th latitude of the 20 townships of the memory mechanism is the position where the address is 5, and the 20 wales of the memory mechanism are set as the address of the address 7, the 14th. At the beginning of the wales, the starting position of the twentieth traverse of the 20 丄 丄 前述 前述 前述 前述 作为 作为 , , , , , , , , , , , 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述The beginning of the 16th wales is set to the position where the address is 7, and the 将 position opens the 17th wales of the 20 objects of the memory mechanism as the address of the address 7, and writes the bit. The two wales of the aforementioned memory mechanism are set as the address with the address of 8, and the 18th wales are The initial write bit sets the two wales of the memory mechanism as the address of the address 8, and starts the twentieth trajectory of the start of the ninth wales of the two wales of the memory mechanism. Write bit 133671.doc &quot;112. 200947881 is set as the location of the address ίο. 56. The data processing apparatus of claim 48, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is an LDPC code of 16,200 bits, and the m-bit is 12 a bit, and the integer b is 2, and the 12-bit code bit of the LDPC code is mapped to any one of 4096 signal points determined by a specific modulation mode, and the memory mechanism is stored in the horizontal direction memory. In the case of 24 wales of 2×2 bits, in the case of memory 16200/(12x2) bits in the wale direction, the rearrangement mechanism is located at the beginning of the longitudinal direction of the memory mechanism, When the integer of the ascending order indicates the address of each position in the wale direction of the memory mechanism, the fourth vertical line of the beginning of the first vertical line is written to the fourth vertical line of the beginning of the third vertical line. At the beginning of the fifth vertical line of the beginning of the write bit, the beginning of the sixth vertical line of the write bit sets the 24 wales of the memory mechanism as the address of the address. The 24 wales of the memory mechanism are set as the address of the address, and the 24 wales of the memory mechanism are set as the address of the address, and the 24 wales of the memory mechanism are set as The position of the address is 〇 / The 24 wales of the memory mechanism are set as the address of the address, and the 133671.doc -113·200947881 of the 24 wales of the memory device is set as the address 〇 Positioning 24 bits of the memory mechanism as the address of the address 0, 24 of the memory means are set to the address of 1 and 24 of the memory means are set to the address of 1 24 of the memory means are set to the address of the address 1, 24 of the memory means are set to the address of 2, and the 7th of the walt is written to the first of the wales The beginning of the ninth wales in the beginning of the wales, the beginning of the ninth latitude in the wales, the beginning of the ninth latitude in the vertical alignment, the beginning of the eleventh wales in the wales, the beginning of the write bit, the write bit, the memory The 12th vertical and the 12th vertical position of the organization The address is 2, the beginning of the write bit sets the 13th wales of the 24 wales of the memory mechanism as the address of the address 2, and the 14th wales of the 24 wales of the memory mechanism Starting to write the position as the address of the address 3. The starting position of the 15th wales of the 24 wales of the memory mechanism is the position of the address of 7, and the first of the 24 wales of the memory mechanism is The start position of the 16 wales is the position where the address is 9, and the start write position of the 17th wales of the 24 wales of the memory mechanism is the position of the address address 9, and the 24 vertical positions of the memory mechanism are used. At the beginning of the ninth latitude of the line, write 133671.doc • 114- 200947881. Set the position of the address as 9 and set the start position of the 19th wales of the 24 objects in the memory. The address of the address is 10, and the beginning of the 2nd wales of the 24 坳 纤 纤 前述 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 24 § § § § § § § § § § §第•The starting position of the 21st wales in the 仃 作为 is the position where the address is 10 The starting write bit V of the second twentieth line of the 24 縦 丄 丄 前述 置 作为 作为 作为 , , , , , , , , , , , , , , , , , 24 24 24 24 24 24 24 24 24 24 24 24 The start write position is a position where the address is 10, and the start write position of the 24th wales of the 24 wales of the memory means is set to the position of the address 11. 57. A data processing method comprising a replacement step of storing a code position of an LDPC (l〇w 〇Density Parity Check) code of N bits in a row direction and a longitudinal direction The memory element of the element is in the longitudinal direction. The code bit of the LDPC code read in the direction of the row is used as the symbol (10), and the specific positive integer is set to b, and the memory mechanism is The row direction stores 11^bits, and the N/(mb) bits are memorized in the longitudinal direction, and the code bits of the LDPC code are written in the preceding direction of the quotation c u' mechanism. In the case of the above-mentioned course direction, and the code 133671.doc -115-200947881 bits of the luminary bit read in the foregoing direction of the memory mechanism is used as the continuous b symbols, Substituting the code bit of the foregoing LDPC code into an allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC The code specified by the specification of DVB-S.2 or DVB-T.2 N is a 16200-bit LDPC code; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to an error probability, and group the above-mentioned symbol bits according to the error probability. The group is a group of symbol bits, and the rule is as follows: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing code bit element to which the code bit group is allocated a combination of a symbol bit group, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit group and the bit number of the foregoing symbol bit; In the case where the m-th bit is 10 bits, and the integer b is 2, and 10 bits of the code bit unit are mapped as one of the aforementioned symbols to 21G, that is, any one of 1024 signal points. The group of code bits of the 10x2 bit read in the foregoing direction of the memory mechanism is divided into five groups of the foregoing code bits; the preceding symbols of 10x2 bits of two consecutive symbols The bit group is divided into 5 symbol bit groups; Yes: 1 bit of the code bit of the 1st good code bit group of the error probability 133671.doc -116- 200947881 assigned to the error probability 5th good symbol bit group 1 Bit; assigning 1 bit of the code bit of the second good symbol bit group of the error probability to the 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; The 4th bit of the code bit of the 3rd good code bit group is allocated to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the error probability is 3rd good code bit The 4 bits of the code bit of the metagroup are assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is The 2 bits of the element are allocated to the 2 bits of the symbol bit of the 3rd good symbol bit group of the error probability; the 1 bit of the code bit of the 3rd good code bit group of the error probability is assigned Give the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 1 bit of the code bit of the 4th good code bit group of the error probability The 1st bit of the symbol bit of the symbol group of the 4th good symbol group of the error probability is assigned; the 2 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 3rd good 2 bits of the symbol bit of the symbol group; 1 bit of the code bit of the 5th good code bit group of the error probability 133671.doc -117- 200947881 ration error probability 4th 1 bit of the symbol element of the good symbol group; and assigning the 3 bits of the code bit of the 5th good code group of the error probability to the 5th good symbol of the error probability The 3-bit symbol of the meta-group. 5 8. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a memory code length of N bits in a horizontal direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the memory mechanism in the preceding direction and read in the direction of the row is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row When the direction is read, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, V is used to code bits of the LDPC code. Allocating an allocation rule to the symbol bit indicating the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 16,200 bits, and the coding rate The LDPC code is 2/3; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the foregoing code bit are mapped as one of the aforementioned symbols to 133671.doc -118-200947881 1024QAM Determining any one of 1024 signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the waling direction; The code bit of the 10x2 bit read from the row direction of the memory mechanism is set to the bit bi from the most significant bit, and the symbol of 10x2 bits of the preceding two symbols is consecutively The i-th bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: The bit bG is assigned to the bit y8, the bit bi is assigned to the bit y6, the bit b2 is assigned to the bit y, the bit b3 is assigned to the bit yi, and the bit b4 is assigned to the bit y2 , bit b 5 is assigned to bit y 3 , bit b6 is assigned to bit y4 , bit b7 is assigned to bit y5 , bit b8 is assigned to bit y7 , bit b9 is assigned to bit Yuan y 1 〇, assign bit b! 〇 to bit y!!, bit b丨! Assigned to bit y! 2, assign bit b! 2 to bit y 13, assign bit b! 3 to bit y! 6, assign bit b丨4 to bit y 1 4, will Bit b!5 is assigned to bit y!5, 133671.doc -119- 200947881 assigns bit b! 6 to bit y9, bit b17 to bit y18, bit bi 8 to bit Element y 19, assigns bit b! 9 to bit y 17. 59. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the preceding v element replaces the code bit of the mb bit, and replaces the code bit as the symbol bit; the LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is an LDPC code of 64,800 bits; The allocation rule is to group the group of the foregoing code bit groups as a group of code bits according to the error probability, and group the group of the preceding symbol bits according to the error probability as a group of symbol bits. And the rule recited in 133671.doc-120-200947881: the foregoing code bit group of the foregoing code bit element and the foregoing symbol bit element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the element is 10 bits, and the integer b is 2, and the 10 bits of the code bit are mapped as one of the aforementioned symbols to 21Q or 1024 letter® points, the memory is The group of code bits of the 10x2 bit read by the direction of the foregoing direction of the mechanism is divided into 5 groups of the aforementioned code bits; the preceding symbol group of 10x2 bits of the preceding two symbols is distinguished. Is a group of 5 symbol bits; as specified in the foregoing allocation rules: The 1 bit of the code bit of the first good code bit group of the error probability is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability is 2nd good. 1 bit of the code bit of the code bit group is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability 3rd good code bit group The 4 bits of the code bit are assigned to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; 3 of the code bits of the 3rd good code bit group of the error probability Bits 133671.doc • 121 - 200947881 The third bit of the symbol bit of the second good symbol group of the error probability; the code bit of the third good symbol group of the error probability 4 bits are allocated to 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to the error 1 bit of the symbol bit of the 4th good symbol group of the probability; 1 bit of the code bit of the 5th good code bit group of the error probability The first bit of the symbol bit of the second good symbol group is assigned to the error probability; the third bit of the code bit of the fifth good symbol group of the error probability is assigned to the error probability fourth. The 3 bits of the symbol bit of the symbol group; and the 2 bits of the code bit of the 5th good code bit group of the error probability are assigned to the 5th good symbol bit of the error probability The 2 digits of the group's symbolic bits. 60. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memory mb bit, and the first 133671.doc • 122·200947881 describes the vertical direction memory N/(mb) bit, and the code bit of the LDPC code is written in the foregoing longitudinal direction of the memory mechanism, Then, in the foregoing direction, the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, and the LDPC code is used. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; ® LDPC code system DVB- Code specified by the specifications of S.2 or DVB-T.2 N is a 64800-bit LDPC code with a coding rate of 2/3; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1 as one of the preceding symbols. Any one of the 1,024 signal points determined by 024QAM; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction; The i-th bit of the 10x2 bit that is read from the direction of the memory mechanism is set to be the bit element from the most significant bit, and the number of the preceding symbols is 10x2. The bit element of the bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b 1 is Assigned to bit y9, bit b2 is assigned to bit y〇, bit b3 is assigned to bit y 1, 133671.doc -123- 200947881 bit b4 is assigned to bit y2 ' bit b5 is allocated Assign bit y3 ' to bit b6 to bit y4 ' Assign bit b7 to bit ys ' Assign bit b8 to bit yio ' The element b9 is assigned to the bit y 11 ', and the bit b1G is assigned to the bit yi2 ′. The bit b!! is assigned to the bit y 14, Assigning bit b! 2 to bit y 15, assigning bit b! 3 to bit y 6 ' assigning bit b! 4 to bit y 7, assigning bit b! 5 to bit y 3, assign bit b16 to bit y18, bit h7 to bit y! 9, assign bit b丨8 to bit y! 6, ◎ assign bit b19 to bit yn . 61.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The !!! bit of the code bit of the LDPC code written in the preceding row direction in the row direction is regarded as a symbol, and the specific positive integer is b, and the memory mechanism is as described above. The direction of the row memorizes mb bits, and the N/(mb) bits are memorized in the direction of the wales; 133671. Doc • 124· 200947881 The code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row, and the mb bit read in the direction of the row of the memory mechanism In the case where the code bit of the element is used as the consecutive b symbols, the code of the mb bit is replaced according to the allocation rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol. a bit, the replaced code bit is used as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and will be based on the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit and the foregoing code bit element for allocating the code bit group The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits in the meta-bit; wherein the m-bit is 10 bits, and the integer b is 2, and the 10-bit of the code bit is mapped to 21 () or 1024 signals as one of the aforementioned symbols. In the case of any one of the points, the group of code bits of the 10x2 bit read in the direction of the preceding direction of the memory means is divided into four groups of the preceding code bits; 10x2 bits of the aforementioned symbol bit group area 133671. Doc -125- 200947881 is divided into 5 symbol group; in the foregoing allocation rule, it is specified that: 1 bit of the code bit of the first good symbol group of the error probability is assigned to the error probability 5th 1 bit of the symbol element of the good symbol group; assign the 2 bits of the code bit of the second good symbol group of the error probability to the first probability symbol of the error probability 2 bits of the symbol bit of the group; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the symbol bit of the 2nd good symbol bit group of the error probability 4 bits of the element; 2 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; The 2 bits of the code bit of the second good symbol bit group of the error probability are assigned to the 2 bits of the symbol bit of the 4th good symbol bit group of the error probability; the error probability is 2nd good. The 3 bits of the code bit of the code bit group are assigned to the 3 bit of the symbol bit of the 5th good symbol bit group of the error probability; The 1st bit of the code bit of the 3rd good code bit group is assigned to the 1st bit of the symbol bit of the first good symbol bit group of the error probability; the error probability is 4th good code bit 1 bit of the code bit of the metagroup 200947881 is assigned to the 1st bit of the symbol bit of the 1st good symbol group of the error probability; the code of the 4th good code bit group of the error probability The 2-bit of the bit is allocated to the 2-bit of the symbol bit of the 3rd good symbol bit group of the error probability; and the 2 bits of the code bit of the 4th good code bit group of the error probability The element is assigned to the 2 bit of the symbol bit of the 4th good symbol bit group of the error probability. ® 62.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code specified by the specification of 2 133671. Doc 127· 200947881 LDPC code with a length N of 16200 bits and a coding rate of 3/4; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the above-mentioned code bit are used as one of the aforementioned symbols Meta-mapped to any one of 1024 signal points determined by 1024QAM; the memory mechanism includes 20 wales that store 1 〇χ 2 bits in the horizontal direction and 16200/(10×2) bits in the wales direction; In the foregoing replacement step, the code bit of 10x2 bits read out in the row direction of the memory mechanism is set from the most significant bit, and the i+th bit is set to the bit bi, and two consecutive The symbol of the 10x2 bit of the symbol is calculated from the most significant bit. The i+th bit is set to the bit %. The following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit y8, The bit b! is assigned to the bit y 〇, the bit b2 is assigned to the bit y 1, the bit b3 is assigned to the bit y2, the bit b4 is assigned to the bit y3, and the bit b5 is assigned to the bit Element y4, assigning bit b6 to bit y5, bit b7 to bit y6, bit b8 to bit y7, bit b9 Y9 to the bit, the bit b! Y〗 billion bits allocated to 2, b !! bits assigned to the bit y 1 3, the bit b! 2 bits are assigned to y 1 8, 133671. Doc -128- 200947881 Assigning bit b ! 3 to bit y! 9, assigning bit b14 to bit yi〇, assigning bit b! 5 to bit yi 6, assigning bit b丨6 The bit yi 4 is assigned, the bit b! 7 is assigned to the bit y! 7, the bit b 丨 8 is assigned to the bit y! 5, and the bit b! 9 is assigned to the bit y! j. 63.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to represent the aforementioned symbols. The allocation rule of the symbol of the meta-sub-band replaces the code bit of the mb bit, and replaces the replaced bit element as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code specified by the specification of 2 is an LDPC code of 64,800 bits; 133671. Doc -129- 200947881 The foregoing allocation rule is to group the group of the aforementioned code bits 作为 as a group of code bits according to the error probability, and group the group of the aforementioned symbol bits according to the error probability as a group The symbol bit group, and the following rules are defined: the foregoing code bit group of the code bit element and the aforementioned symbol bit of the aforementioned symbol bit of the code bit element to which the code bit group is allocated a combination of the meta-groups, that is, a group set, and the foregoing code bit group of the group of the group and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; © Yu When the m-bit is 10 bits, and the integer bg2 is 10 bits of the code bit as one of the symbols and is mapped to 210, that is, 1024 signal points, the foregoing S The group of the preceding code bits of the ι〇χ2 bit read by the preceding direction of the mechanism is divided into four groups of the aforementioned code bits; the preceding symbols of the first two symbols of the first two symbols The bit group is divided into 5 symbol bit groups; as specified in the foregoing distribution rules : assigning 1 bit of the code bit of the first good code bit unit to the symbol of the 5th good symbol group of the error probability; 1 bit of the bit error probability 2Good Shimin/* Dry music and good people's code position 兀 group of code bits 丨 元 分 分 位 位 配 配 第 第 第 第 第 第 4 4 4 4 4 4 4 4 4 4 4 4 The bit score will be the error probability of the third good code bit group of the code bit 133671. Doc -130- 200947881 allocates the 4th bit of the symbol bit of the first good symbol group of the error probability; assigns the 4 bits of the code bit of the 3rd good code bit group of the error probability to The 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability; the 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 3rd good 4 bits of the symbol bit of the symbol group; ® assigns 1 bit of the code bit of the 3rd good code bit group of the error probability to the 4th good symbol group of the error probability 1 bit of the symbol bit of the group; 2 bits of the code bit of the 4th good code bit group of the error probability are assigned to the symbol bit of the 4th good symbol bit group of the error probability 2 bits; and assigning the 3 bits of the code bit of the 4th good code bit group of the error probability to the 3 bit of the symbol bit of the 5th good symbol bit group of the error probability . 64.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. Direction memory mb bit, and in the first 133671. Doc-131 - 200947881 describes a longitudinal direction memory N/(mb) bit, the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the horizontal direction, and In the case where the code bits of the mb bits read by the preceding direction of the memory mechanism are regarded as consecutive b symbols, the symbol bits for assigning the LDPC code are assigned to the symbols representing the symbols. The bit allocation rule replaces the code bit of the mb bit, and replaces the code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code specified by the specification of 2 is LDPC code with a length N of 64,800 bits and a coding rate of 3/4; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are used as One of the aforementioned symbols is mapped to any one of 1024 signal points determined by 1024QAM; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction. In the foregoing replacement step, the code bit of the 10x2 bit read from the Q direction of the memory mechanism is set from the most significant bit, and the i+th bit is set to the bit bi, and will be continuous. The symbol bits of the 10x2 bits of the two preceding symbols are set from the most significant bit, and the i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit Y8, assign the bit b! to the bit y6, assign the bit to the bit y, and assign the bit b3 to the bit y!, 133671. Doc •132- 200947881 assigns bit b4 to bit y2, bit b5 to bit y3, bit b6 to bit y4, bit b7 to bit y5, bit b 8 Assigned to bit y 7, assign bit bs&gt; to bit y 1 〇, assign bit b! 〇 to bit y丨j, assign bit b π to bit y! 2, ® will bit The element b! 2 is assigned to the bit y 13, the bit b! 3 is assigned to the bit y! 4, the bit b! 4 is assigned to the bit y! 5, and the bit b! 5 is assigned to the bit y9 , assign bit b! 6 to bit y! 6, assign bit b! 7 to bit y! 7, assign bit bi 8 to bit y! 8, assign bit b! 9 to Bit y 19. Q 65.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit and memorizes the N/(mb) bit in the preceding waling direction, 133671. Doc-133 - 200947881 The code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row, and the mb bit read in the direction of the row of the memory mechanism In the case where the code bit of the element is used as the consecutive b symbols, the code of the mb bit is replaced according to the allocation rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol. a bit, the replaced code bit is used as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; 前述 The foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and will be based on the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit and the foregoing code bit element for allocating the code bit group a combination of the foregoing symbol bit groups of the symbol bit group, that is, a group set, and the foregoing code bit group of the foregoing group of code bits and the foregoing symbol bit group, and the foregoing The number of bits of the symbol bit; wherein the m-bit is 10 bits and the integer b is 2 » the 10-bit of the aforementioned code bit is mapped to 21 () or 1024 as one of the aforementioned symbols In the case of any one of the signal points, the group of code bits of the 10x2 bit read in the direction of the preceding direction of the memory means is divided into three groups of the preceding code bits; two consecutive symbols The 10x2 bit of the preceding symbol bit group area 133671. Doc -134- 200947881 is divided into 5 symbol group; in the foregoing allocation rule, it is specified that: 4 bits of the code bit of the first good symbol group of the error probability are assigned to the error probability 1st 4 bits of the symbol element of the good symbol group; assign the 3 bits of the code bit of the first good symbol group of the error probability to the second probability symbol of the error probability 3 bits of the symbol bit of the group; 分配 assign 1 bit of the code bit of the first good code bit group of the error probability to the symbol of the 3rd good symbol group of the error probability 1 bit of the bit; assigns the 3 bits of the code bit of the 1st good code bit group of the error probability to the 3 bit of the symbol bit of the 4th good symbol bit group of the error probability Assigning 4 bits of the code bit of the first good code bit group of the error probability to the 4 bits of the symbol bit of the 5th good symbol bit group of the error probability; 2 1 bit of the code bit of the good code bit group is assigned to 1 bit of the symbol bit of the 3rd good symbol bit group of the error probability; The 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group; the error probability is 3rd good The code bit of the code bit group is 2 bits 133671. Doc 135- 200947881 allocates 2 bits of the symbol bit of the 3rd good symbol group of the error probability; and assigns 1 bit of the code bit of the 3rd good code bit group of the error probability to The error probability is the first bit of the symbol element of the fourth good symbol group. 66.  a data processing method, comprising: a replacement step, which is a memory mechanism of an LDPC (Low Density Parity Check) code bit of an LDPC (Low Density Parity Check) having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 16200 bits, and the coding rate is 4/5 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are taken as 1 The above symbols are mapped to 133671. Doc -136- 200947881 Any one of 1024 signal points determined by 1024QAM; the memory mechanism contains 20 vertical lines of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; The foregoing replacement step is that the code bit of the 10x2 bit read out in the row direction of the memory mechanism is set from the most significant bit, the i+th bit is set to the bit bi, and two consecutive symbols are consecutive. The 10x2 bit symbol of the element is calculated from the most significant bit, and the i+th bit is set to bit yi. The following replacement is performed according to the foregoing allocation rule: ® assign bit b〇 to bit y0, The bit b 1 is assigned to the bit y!, the bit b2 is assigned to the bit y2, the bit b3 is assigned to the bit y3, the bit b4 is assigned to the bit y4, and the bit b5 is assigned to the bit Y6, the bit b6 is assigned to the bit y7, the bit b7 is assigned to the bit y8, 位 the bit b8 is assigned to the bit y9, and the bit b9 is assigned to the bit y 1 〇, the bit b! 〇 Assigned to bit y!!, assigns bit b!! to bit y! 2, assigns bit bi 2 to bit y 16, assigns bit b 1 3 to bit Element y! 8, assigns bit b i 4 to bit y 19, and assigns bit b! 5 to bit y 5, 133671. Doc -137- 200947881 Assign bit bi 6 to bit y! 4, assign bit b! 7 to bit y! 7, assign bit b! 8 to bit y! 5, place bit b ! 9 is assigned to bit y 13. 67.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the above-mentioned horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as a group of symbol bits, and the provision is 133671. Doc -138· 200947881 The rule is as follows: the combination of the aforementioned code bit group of the aforementioned code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit group to which the code bit group is allocated is a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the bit number of the foregoing symbol bit; wherein the m bit is 10 bits And when the integer b is 2, and the 10-bit of the code bit is mapped to one of 21G, that is, 1024 letter-point points as one of the symbols, the foregoing row of the memory mechanism The foregoing group of code bits of the 10x2 bit read by the direction is divided into three groups of the aforementioned code bits; the preceding group of symbol bits of 10x2 bits of two consecutive symbols is divided into five symbols. a bit group; in the foregoing allocation rule, it is provided that: one bit of the code bit of the first good code bit group of the error probability is assigned to the symbol of the fourth probability symbol group of the error probability 1 bit of the bit; 1 bit of the code bit of the code group of the first good error probability Assigning 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; assigning the 4 bits of the code bit of the 2nd good code bit group of the error probability to the error probability first good The 4th bit of the symbol bit of the symbol group; the 4th bit of the code bit of the 2nd good code bit group of the error probability is 133671. Doc -139- 200947881 allocates the 4th bit of the symbol bit of the 2nd good symbol group of the error probability; assigns the 3 bits of the code bit of the 2nd good code bit group of the error probability to The error probability is the third good symbol of the symbol bit of the third bit group; the third bit of the code bit of the second good symbol bit group of the error probability is assigned to the error probability of the fourth good 3 bits of the symbol bit of the symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the error probability 3rd good symbol bit group 1 bit of the symbol bit; and assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the symbol bit of the 5th good symbol bit group of the error probability 3 bits. 68.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And 133671. Doc-140-200947881, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the aforementioned LDPC code Representing the allocation rule of the symbol element of the preceding symbol, replacing the mbit bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 64800 bits, and the coding rate is 4/5 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; ® 10 bits of the aforementioned code bit are used as One of the aforementioned symbols is mapped to any one of 1024 signal points determined by 1024QAM; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction. In the foregoing replacement step, the code bit of the 10x2 bit read from the row direction of the memory mechanism is calculated from the most significant bit, and the i+th bit is set to the bit bi, and will be consecutive 2 The symbolic element of the 10x2 bit of the preceding symbol is set from the most significant bit, and the i + Ι bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit be is allocated to the bit Element y8, assigning bit b 1 to bit y6, bit b2 to bit y, assigning bit b3 to bit y 1, assigning bit b4 to bit y2, bit b5 Assigned to bit y3, bit b6 is assigned to bit y4, 133671. Doc -141 - 200947881 Assign bit b7 to bit y5 ' Assign bit b8 to bit y7 ' Assign bit b9 to bit y 1 〇 ' Assign bit b1Q to bit yn ' Place bit b〗! Assigned to bit yi2 ' Assign bit b! 2 to bit y 13 ' Assign bit b13 to bit yi4 ' Assign bit b14 to bit yi6 and bit b] 5 to bit y 17, assigning bit b 16 to bit y 9 ' assigns bit b! 7 to bit y] 5, assigns bit 8 to bit y8, and assigns bit 9 to Bit y丨9. 69.   A data processing method includes a replacement step of a coded bit of a Density Parity Check code having a memory code length of N bits in a row direction and a longitudinal direction: The code bit of the aforementioned LDPC code read in the direction of the row described above is taken as the (10) symbol, and the specific positive integer is set to b, δ recalls the mb bit, and the foregoing The memory means stores the N/(mb) bit in the wale direction in the row direction, and reads the code bit of the LDPC code in the forward direction in the row direction of the memory means, and writes it in the forward direction. After reading in the above-mentioned course direction, the mb bit code is 133671. Doc - 142 - 200947881 The bit is replaced by the above mb bit according to the allocation rule for assigning the code bit of the aforementioned LDPC code to the symbol bit representing the preceding symbol in the case of consecutive b symbols. The code bit element, the replaced code bit element is used as the foregoing symbol bit element; the foregoing LDPC code system is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing group of code bits of the foregoing code bit element and the aforementioned code bit element to which the code bit group is allocated a combination of the foregoing symbol bit groups of the symbol bit group, that is, a group set, and the foregoing code bit group of the foregoing group of code bits and the foregoing symbol bit group and the foregoing symbol element The number of bits in the bit; wherein the m bit is 10 bits, and the integer b is 2, and the 10 bits of the code bit are mapped to 21G or 1024 signal points as one of the symbols. In either case, the group of code bits of the 10x2 bit read in the foregoing direction of the memory mechanism is divided into four groups of the preceding code bits; 10x2 bits of two consecutive symbols The preceding symbol bit group is divided into 5 symbol bit groups; With the rules stipulated are: good probability of error of 1 bit code group of code bits of one yuan points 133 671. Doc • 143 - 200947881 allocates 1 bit of the symbol bit of the 5th good symbol group of the error probability; assigns 4 bits of the code bit of the 2nd good code bit group of the error probability to The error probability is the first good 4th bit of the symbol bit of the symbol group; the 3rd bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability 2nd good 3 bits of the symbol element of the symbol element group; 2 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error probability 3rd good symbol bit group 2 bits of the symbol bit of the group; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the symbol bit of the 4th good symbol bit group of the error probability 4 bits; assigning 2 bits of the code bit of the second good symbol bit group of the error probability to the 2 bit unit of the symbol bit of the 5th good symbol bit group of the error probability; w assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the symbol bit of the 5th good symbol bit group of the error probability Assigning 1 bit of the code bit of the 4th good code bit group of the error probability to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; and the error probability The 2nd bit of the code bit of the 4th good code bit group is 133671. Doc 200947881 The second bit of the symbol bit of the third good symbol group of the error probability is assigned. 70_ - a data processing method, comprising a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, Q replaces the code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 16200 bits, and the coding rate is 5/6 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are taken as 1 The preceding symbols are mapped to any one of 1024 signal points determined by 1024QAM; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction. ; 133671. Doc-145-200947881 In the foregoing replacement step, the code bit of 10x2 bits read out in the row direction of the foregoing memory mechanism is set to the bit bi' from the most significant bit, and the i+1th bit is set as the bit bi' The i-th +1 bit of the two consecutive symbols of the octet 2 bits is set as the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: 〇 is assigned to bit y8, bit b! is assigned to bit y, bit b2 is assigned to bit y 1, bit b3 is assigned to bit y2, bit b4 is assigned to bit y3, Bit b5 is assigned to bit y4, bit b6 is assigned to bit y5, bit b7 is assigned to bit y6, bit b8 is assigned to bit y7, bit b9 is assigned to bit y9, The bit bi 〇 is assigned to the bit y! 〇, the bit b!! is assigned to the bit y 1!, the bit b 12 is assigned to the bit y 12 , and the bit b ! 3 is assigned to the bit y 1 6. Assign bit b14 to bit y17, bit b!5 to bit y!8, bit b! 6 to bit y 1 9, assign bit b17 to bit yi4 'Distribute bit b〗 8 Bit y 15 '133671. Doc . 146 - 200947881 Assign bit b! 9 to bit y 13. 71.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the LDPC code bit read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the preceding direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the foregoing direction. And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing group of code bits of the foregoing code bit element and the aforementioned code bit element to which the code bit group is allocated The combination of the preceding symbol bit groups of the aforementioned symbol bits 133671. Doc -147· 200947881 is a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; When the bit is 10 bits and the integer b is 2, and 10 bits of the code bit are mapped as one of the aforementioned symbols to 21G or 1024 signal points, the memory mechanism is used. The group of code bits of the 1 〇χ 2 bit read in the horizontal direction is divided into 5 groups of the aforementioned code bits; the preceding symbol group of 10×2 bits of two consecutive symbols The area® is divided into five symbol bit groups; in the foregoing allocation rule, it is specified that: 1 bit of the code bit of the first good code bit group of the error probability is assigned to the error probability 5th good character 1 bit of the symbol bit of the meta-bit group; 1 bit of the code bit of the second good code bit group of the error probability is assigned to the error probability 4th good symbol bit group 1 bit of the symbol bit 〇 7C 9 assigns 4 bits of the code bit of the 3rd good code bit group of the error probability to The 4th bit of the symbol bit of the first good symbol bit group of the first probability; the 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 2nd good 4 bits of the symbol bit of the symbol group; the 4th bit of the code bit of the 3rd good code bit group of the error probability is 133671. Doc -148- 200947881 allocates the 4th bit of the symbol bit of the 3rd good symbol group of the error probability; assigns the 2 bits of the code bit of the 3rd good code bit group of the error probability to The error probability is the 4th bit of the symbol element of the 4th good symbol group; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 4th good 1 bit of the symbol bit of the symbol group; and assigning the 3 bits of the code bit of the 5th good code bit group of the error probability to the 5th good symbol group of the error probability The 3 digits of the group of symbols. 72.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, the code bits for using the LDPC code are allocated to represent the aforementioned symbol 133671. . Doc -149- 200947881 The allocation rule of the symbolic element of the element replaces the code bit of the aforementioned mb bit, and replaces the replaced code bit as the above-mentioned symbol bit; The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 64800 bits, and the coding rate is 5/6 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are taken as 1 The preceding symbols are mapped to any one of 1024 signal points determined by 1024QAM; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction. In the foregoing replacement step, the code bit of 10x2 bits read out in the row direction of the memory mechanism is set from the most significant bit, the i+th bit is set to the bit bi, and two consecutive bits will be used. The symbolic element of the 10x2 bit of the preceding symbol is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: assigning the bit b〇 to the bit ys , assigning bit b! to bit y6, assigning bit b2 to bit y, assigning bit b3 to bit y 1, assigning bit b4 to bit y2, assigning bit b5 to Bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y7, bit b9 is assigned To the bit y] billion, 133,671. Doc -150- 200947881 Assigning bit b! G to bit y! 1, assigning bit bn to bit y12, assigning bit b! 2 to bit y 13, assigning bit b: 3 to Bit y! 4, assign bit b! 4 to bit y 1 5, bit b15 to bit y16, bit b! 6 to bit y! 7, bit b! 7 Assigned to bit y 9, bit B! 8 is assigned to bit y 18, and bit b! 9 is assigned to bit y 19. 73.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit, replacing the code bit of the aforementioned mb bit, 133671. Doc -151 - 200947881 The replaced code bit is used as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing group of code bits of the foregoing code bit element and the aforementioned code bit element to which the code bit group is allocated a combination of the foregoing symbol bit groups of the symbol bits, that is, a group set, and the foregoing code bit group of the foregoing group of code groups and the foregoing symbol bit group and the foregoing symbol The number of bits in the meta-bit; wherein the m-bit is 10 bits, and the integer b is 2, and the 10-bit of the code bit is mapped to 21 () or 1024 signals as one of the aforementioned symbols. In the case of any one of the points, the group of code bits in the range of 10x2 bits read in the foregoing direction of the memory mechanism is divided into five groups of the preceding code bits; two consecutive symbols The preceding symbol bit group of 10x2 bits is divided into 5 symbol bit groups; The foregoing allocation rule defines: assigning 2 bits of the code bit of the first good symbol bit group of the error probability to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability ; 1 bit of the code bit of the 2nd good code bit group of the error probability is 133671. Doc • 152- 200947881 allocates 1 bit of the symbol bit of the 3rd good symbol group of the error probability; assigns 4 bits of the code bit of the 3rd good code bit group of the error probability to The error probability is the first good 4-bit symbol of the symbol bit group; the error probability is the 4th good code bit group of the 4-bit code bit is assigned to the error probability second good 4 bits of the symbol bit of the symbol group; Assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the 3 bits of the symbol bit of the 3rd good symbol bit group of the error probability; The 3 bits of the code bit of the code bit group are assigned to the 3 bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability 4th good code bit group 1 bit of the code bit is assigned to 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; and the code bit of the 5th good code bit group of the error probability 2-bit is assigned to the 2-bit 0 of the symbol bit of the 5th good symbol group of the error probability. 74. A data processing method, which includes a replacement step, which is in the course direction and the waling direction. The memory mechanism of the code bit of the LDPC (Low Density Parity Check) code having the length of the N-bit is written in the preceding direction and read in the foregoing direction. 133671.doc -153 - 200947881 The m-bit of the code bit of the aforementioned LDPC code is taken as 1 symbol, and the specific positive integer is set to b, the aforementioned memory Having a memory mb bit in the row direction and storing N/(mb) bits in the wale direction, the code bit of the LDPC code is written in the wale direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the aforementioned LDPC code For the allocation rule indicating the symbol element of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 16200 bits, and the LDPC code is 8/9; the m-bit is 10 bits, and the aforementioned integer b is 2; 10 bits of the aforementioned code bits The element is mapped to one of the 1024 signal points determined by 1024QAM as one of the preceding symbols; 〇 the memory mechanism includes 20 vertical w lines of 10x2 bits in the horizontal direction, and 16200/ in the longitudinal direction. (10x2) bit; in the foregoing replacement step, it will be read in the direction of the aforementioned memory mechanism The 10x2 bit code bit is set from the most significant bit, the i+th bit is set to bit bi, and the symbol bits of 10x2 bits of two consecutive symbols are counted from the most significant bit. The i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, 133671.doc -154-200947881, the bit h is assigned to the bit y9 ' Bit b2 is assigned to bit y4', bit b3 is assigned to bit y〇', bit b4 is assigned to bit y 1 ', bit b5 is assigned to bit y2', bit b6 is assigned to bit y3 'Assign bit b7 to bit y5 ' 分配 Assign bit b8 to bit y6, bit b9 to bit y7, bit b! 〇 to bit y! 〇, bit bi Assigned to bit y! i, assign bit b! 2 to bit y 12, assign bit b 1 3 to bit y! 3, assign bit bi 4 to bit y! 4, Bit b15 is assigned to bit y15, bit b16 is assigned to bit y16, bit b17 is assigned to bit y17, bit b! 8 is assigned to bit yi8, bit b 1 9 is assigned to Bit y丨9. 75. A data processing method, comprising a replacement step, wherein: a 码, a column direction, and a directional direction δ 碣 碣 碣 D D D parity parity parity parity parity parity parity parity parity parity parity parity parity The memory unit is written in the preceding direction and the m-bit of the code bit of the LDPC code in the preceding direction = is read as a symbol - J55- 13367J.doc 200947881 Specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the foregoing course direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the LDPC The code bit of the code is assigned to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol element; the LDPC code is DVB The code length N specified by the specification of -S.2 or DVB-T.2 is 64800 bits. The LDPC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol a group of bits, and stipulates the following rules: 前述 the foregoing group of code bits of the foregoing code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of the groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; In the case of a 10-bit, and the aforementioned integer b is 2, and 10 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 21 () or 1024 signal points, 133671.doc • 156- 200947881 The group of code bits of 10 χ 2 bits read in the foregoing direction of the memory mechanism is divided into 5 groups of the aforementioned code bits; the aforementioned symbols of 10x2 bits of two consecutive symbols The meta-bit group is divided into 5 symbol-bit groups; The rules stipulate that: the 2 bits of the code bit of the first good code bit group of the error probability are assigned to the 2 bits of the symbol bit of the 5th good symbol bit group of the error probability; Assigning 1 bit of the code bit of the second good symbol bit group of the error probability to the 1 bit of the symbol bit of the 4th good symbol bit group of the error probability; The 4 bits of the code bit of the code bit group are assigned to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability 3rd good code bit group The 4 bits of the code bit are allocated to the 4 bit unit of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is 4 bits are allocated to 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; 1 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error 1 bit of the symbol bit of the 4th good symbol bit group of the probability; 1 bit of the code bit of the 3rd good code bit group of the error probability 133 671.doc •157- 200947881 allocates 1 bit of the symbol bit of the 5th good symbol group of the error probability; 1 bit of the code bit of the 4th good code bit group of the error probability 1 bit allocated to the symbol bit of the 4th good symbol bit group of the error probability; 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 4th 1 bit of the symbol bit of a good symbol group; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 5th good symbol One bit of the symbol bit of the bit group. 76. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol 133671.doc -158·200947881 is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 6 4800 bits, LDPC code with a coding rate of 8/9; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols. Any one of 1024 signal points; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction; The code bit of the 10x2 bit read from the row direction of the memory mechanism is set to the bit bi from the most significant bit, and the symbol of 10x2 bits of the preceding two symbols is consecutively The i-bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b! is assigned to the bit Y9, assigning bit b2 to bit y6, assigning bit b3 to bit y, assigning bit b4 to bit y 1, assigning bit b5 to bit y2, and assigning bit b6 Bit y3, bit b7 is assigned to bit y4, bit b8 is assigned to bit y5, bit b9 is assigned to bit y7, 133671.doc -159 - 200947881 Assign the bit b! q to the bit y! 〇, assign the bit bi! to the bit yi!, assign the bit b12 to the bit yi2, and assign the bit b! 3 to the bit yi 3 , assigning bit b14 to bit yi4, assigning bit b! 5 to bit y 1 5, assigning bit b! 6 to bit yi 8, assigning bit b! 7 to bit y丨6. Assign bit bi 8 to bit yi 7, assign bit b! 9 to bit y! 9. 77. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the aforementioned mb bit, 133671.doc -160- 200947881 replaces the code bit as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 64800 The LDPC code of the element; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a group of code bit groups, and group the group of the aforementioned symbol bit groups according to the error probability as a group a group of meta-bits, and defining the following rules: the foregoing group of code bits of the foregoing code bit element and the aforementioned symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of the groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; In the case of a 10-bit, and the integer b is 2, and the 10-bit of the above-mentioned code bit is mapped as one of the aforementioned symbols to 21 () or 1024 signal points, the memory mechanism is The group of code bits of the 10x2 bit read in the direction of the row is divided into three groups of the preceding code bits; the group of the preceding symbol bits of the 10x2 bits of two consecutive symbols is divided into 5 symbol group; in the foregoing distribution rules, there are: The 2 bits of the code bit of the first good code bit group are assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability 2nd good code The 4-bit code of the bit group is 133671.doc -161 · 200947881 The 4th bit of the symbol bit of the first good symbol group is assigned to the error probability; the error probability is 2nd good. The 3 bits of the code bit group of the code bit group are allocated to the 3 bit of the symbol bit of the second good symbol bit group of the error probability; the error probability second good code bit group is 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; 4 bits of the code bit of the 2nd good code bit group of the error probability The element is assigned to the 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; the 1st bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability 5 1 bit of the symbol bit of the good symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the error 1 bit of the symbol bit of the 2nd good symbol bit group; and 1 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 5th good character One bit of the symbol bit of the meta-bit group. 78. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding row direction and read in the above-mentioned row direction is taken as one symbol, and the specific positive integer is set as b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing course direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, ® is used to use the aforementioned LDPC code. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S .2 or the code specified by the specification of DVB-T.2 is long N 64800 bits, LDPC code with a coding rate of 9/10; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols. Any one of 1024 signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the waling direction; The 10x2 bit code bit read by the direction of the mechanism is set to the bit bi from the most significant bit, and the 1st and 2nd bits of the 2 consecutive symbols are consecutively The symbol element is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, 133671.doc -163- 200947881 Bit b! is assigned to bit y9, bit b2 is assigned to bit yc, bit b3 is assigned to bit y!, bit b4 is assigned to bit y2, bit b5 is assigned to bit y3 , assigning bit b6 to bit y4, assigning bit b7 to bit y5, assigning bit b8 to bit y6, and assigning bit b9 to Element y7, assigning bit b! 〇 to bit y 1 〇, assigning bit b 1! to bit y 1!, assigning bit b! 2 to bit y 1 2, bit b! 3 is assigned to the bit y 14, the bit b ! 4 is assigned to the bit y 1 5 , the bit b ! 5 is assigned to the bit y ! 6, the bit b ! 6 is assigned to the bit y 丨 7, The bit b! 7 is assigned to the bit y! 8, the bit b! 8 is assigned to the bit y! 9, and the bit bi9 is assigned to the bit y13. 79. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding row direction is read as one symbol, and the specific positive integer is set to b, 133671.doc 200947881 The memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then Reading in the course direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for the LDPC code Assigned to the allocation rule indicating the symbol element of the preceding symbol, the code bit of the mb bit is replaced, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 16,200 bits. The LDPC code; the foregoing allocation rule is to group the group of the foregoing code bit groups according to the error probability as a code bit group, and group the group of the aforementioned symbol bits according to the error probability as a symbol a group of bits, and the following rules are defined: the foregoing group of code bits of the aforementioned code bit group and the aforementioned symbol bit group of the aforementioned symbol bit of the code bit group to which the code bit group is allocated The combination is the group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; 12-bit, and the aforementioned integer b is 2, and 12 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 212, that is, 4096 signal points, 133671.doc -165- 200947881 The group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; the aforementioned symbols of 12 X 2 bits of two consecutive symbols The bit group is divided into 6 symbol bit groups; in the foregoing allocation rule The provision is: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability; 1 bit of the code bit of the 2nd good code bit group® is assigned to the 1st bit of the symbol bit of the 5th good symbol bit group of the error probability; the error probability 3rd good code The 4 bits of the code bit of the bit group are assigned to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; the code of the error probability 3rd good code bit group The 2-bit of the bit is allocated to the 2-bit unit of the symbol bit of the second-best symbol group of the error probability; the 4th bit of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 3rd bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 4 3 bits of the symbol element of the good symbol group; 1 bit of the code bit of the 3rd good code bit group of the error probability 133671.doc - 166- 200947881 allocates 1 bit of the symbol bit of the 5th good symbol group of the error probability; assigns the 2 bits of the code bit of the 4th good code bit group of the error probability to the error probability 2 bits of the symbol bit of the 2nd good symbol bit group; 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to the 4th good symbol of the error probability 1 bit of the symbol bit of the bit group; 分配 assign the 2 bits of the code bit of the 4th good code bit group of the error probability to the error probability 5th good symbol bit group 2 bits of the symbol bit; and assigning the 3 bits of the code bit of the 4th good code bit group of the error probability to the symbol bit of the 6th good symbol bit group of the error probability 3 bits. 80. A data processing method, comprising: a replacement step of a code bit of an LDPC (Low Q Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means in the row direction is regarded as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, and 133671.doc -167- 200947881 The mb bit of the mb bit read in the foregoing direction of the memory mechanism is taken as the continuous b preceding symbols, according to the LDPC used to The code bit of the code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB- Code length N specified by the specifications of S.2 or DVB-T.2 16200 bits, LDPC code with a coding rate of 2/3; the m bits are 12 bits, and the aforementioned integer b is 2; 12 bits of the above code bits are mapped as one of the aforementioned symbols to © 4096QAM. Determining any one of 4096 signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; The 12x2 bit code bit read by the direction of the memory mechanism is set to the bit bi from the most significant bit, and the 12x2 bit of the preceding symbol is consecutively The i-th bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the previous allocation rule: the bit bG is assigned to the bit y! 〇, the bit b! Assigned to bit y 8, assign bit b2 to bit y, assign bit b3 to bit y 1, assign bit b4 to bit y2, assign bit b5 to bit y3, Bit b6 is assigned to bit y4, 133671.doc -168· 200947881 assigning bit b7 to bit ys assigning bit b8 to bit y6 dividing bit b9 Assigning bit y·/ assigning bit b! 〇 to bit y9 assigning bit bi! to bit y 12 ' assigning bit b 1 2 to bit y 1 3 ' 分配 allocating bit bi 3 The bit y 1 6 ' is assigned a bit b14 to the bit yi7'. The bit b15 is assigned to the bit yis, the bit b!6 is assigned to the bit y2, and the bit b 17 is assigned to the bit y. ! 4, assign bit b! 8 to bit y丨! , bit b! 9 is assigned to bit y22, bit b2 〇 is assigned to bit y23, bit b 21 is assigned to bit y 2 丨, and bit b 2 2 is assigned to bit y 15, Assigning bit b 2 3 to bit y丨9 β 81. A data processing method comprising a replacement step in which the memory code length in the horizontal direction and the longitudinal direction is the Ν bit 2LDpc (L〇w Density Parity Check: the m-bit of the code bit of the aforementioned LDPC code read by the memory unit of the code bit in the preceding direction and read in the preceding direction is taken as one Symbol, a specific positive integer is set to b, then the memory mechanism memorizes mb bits in the foregoing direction, and stores the N/(mb) bit in the longitudinal direction in the first 133671.doc -169-200947881, the foregoing LDPC code The code bit is written in the longitudinal direction of the memory mechanism, and then read in the horizontal direction, and the code bits of the mb bit read in the direction of the memory of the memory mechanism are regarded as continuous In the case of b preceding symbols, the code bits for using the aforementioned LDPC code are assigned to represent the aforementioned symbols The allocation rule of the symbol bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is the specification of DVB-S.2 or DVB-T.2 The specified code © LDPC code with a length N of 64800 bits; the foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and the group will be distinguished according to the error probability. The group of the preceding symbol bits is used as a group of symbol bits, and the following rules are defined: the foregoing symbol bit group of the aforementioned mbit bit and the aforementioned symbol of the aforementioned code bit element to which the code bit group is allocated a combination of the preceding bit group of the meta-bit, that is, a group set, and the aforementioned code bit group of the foregoing group set and the foregoing code bit of the foregoing symbol bit group and the foregoing symbol The number of bits in the bit; wherein the m bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as 212 symbols, ie, 4096 signal points, as one of the aforementioned symbols. In either case, before the 12x2 bit read in the aforementioned direction of the memory mechanism The code bit group is divided into four preceding code bit groups; 133671.doc -170- 200947881 The preceding symbol bit group of 12x2 bits of two consecutive symbols is divided into six symbol bits. The foregoing allocation rule defines: assigning 1 bit of the code bit of the first good code bit group of the error probability to the symbol bit of the 6th good symbol bit group of the error probability 1 bit; assign 1 bit of the code bit of the 2nd good code bit group of the error probability to 1 bit of the symbol bit of the 6th good symbol bit group of the error probability Assigning 4 bits of the code bit of the 3rd good code bit group of the error probability to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; The 4 bits of the code bit of the code bit group are assigned to the 4 bit of the symbol bit of the 2nd good symbol bit group of the error probability; the error probability 3rd good code bit group The 2-bit score of the code bit is allocated to the 2-bit of the symbol bit of the 3rd good symbol group of the error probability; the code bit of the 3rd good code bit group of the error probability is 3 bits are allocated to the 3 bits of the symbol bit of the 4th good symbol bit group of the error probability; the 1 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error 1 bit of the symbol bit of the 5th good symbol group of the probability; 133671. Doc -171 - 200947881 assigns the 2 bits of the code bit of the 4th good code bit group of the error probability to the 2 bit of the symbol bit of the 3rd good symbol bit group of the error probability; Error probability 4th good code bit group 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; 〇 the error probability is 4th good The 3 bits of the code bit of the code bit group are assigned to the 3 bit of the symbol bit of the 5th good symbol bit group of the error probability; and the 4th good code bit group with the error probability The 2 bits of the group of code bits are assigned to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability. 82.  a data processing method, comprising: a replacement step, which is a memory mechanism of an LDPC (Low Density Parity Check) code bit of an LDC (Low Density Parity Check) having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And the code bit of the mb bit read in the foregoing direction of the memory mechanism is regarded as the continuous b symbols, 133671. Doc -172- 200947881 replaces the code bit of the mb bit in accordance with the allocation rule for assigning the code bit of the foregoing LDPC code to the symbol bit representing the symbol, and replaces the code bit as the foregoing Symbolic element; The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 64800 bits, and the coding rate is 2/3 LDPC code; the m-bit is 12 bits, and the aforementioned integer b is 2; the 12-bit of the aforementioned code bit is 1 The preceding symbols are mapped to any of the 4096 signal points determined by 4096QAM; ® The memory mechanism contains 24 vertical lines that memorize 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction. In the foregoing replacement step, the 12x2 bit code bit read out in the row direction of the memory mechanism is calculated from the most significant bit, the i+th bit is set to the bit bi, and will be consecutive 2 The symbol of the 12x2 bit of the preceding symbol is calculated from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit yi 〇, 分配 Assign bit b! to bit y!!, assign bit b2 to bit y〇, assign bit b3 to bit, assign bit b4 to bit y2, bit b5 Assigned to bit y3, bit b6 is assigned to bit y4, bit b7 is assigned to bit y5, bit b8 is assigned to bit y 6, 133671 . Doc -173- 200947881 assigns bit b9 to bit y?, assigns bit b! ο to bit y 8, assigns bit b!! to bit y12, and assigns bit b12 to bit yi3 , assigning bit b! 3 to bit y! 4, assigning bit b! 4 to bit y 〗 5, assigning bit b! 5 to bit y 1 8, allocating bit b! To the bit y9, the bit b!7 is assigned to the bit y2, the bit b! 8 is assigned to the bit y 1 6, the bit b ! 9 is assigned to the bit y22, and the bit b2G is assigned The bit y23 assigns the bit b21 to the bit y] 7, assigns the bit b22 to the bit y2 1, and assigns the bit b23 to the bit y 1 9 . 83.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction memorizes the mb bit, and memorizes the N/(mb) bit in the longitudinal direction, and the code bit of the LDPC code is in the foregoing vertical direction of the memory mechanism 133671. Doc -174- 200947881 writes, and then reads in the above-mentioned course direction, and the code bits of the mb bits read in the aforementioned direction of the memory mechanism are regarded as consecutive b symbols. Next, in accordance with an allocation rule for assigning the code bit of the foregoing LDPC code to the symbol bit representing the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; 〇 the foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and will be based on the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit and the foregoing code bit element for allocating the code bit group The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits of the meta-bit; wherein the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212, ie, 4096 signal points, as one of the aforementioned symbols. In either case, the group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; 12x2 bits of two consecutive symbols The preceding symbol element group of the element is divided into 6 symbol bit groups; 133671 . Doc 175-200947881 In the foregoing allocation rule, it is provided that: one bit of the code bit of the first good code bit group of the error probability is assigned to the symbol of the sixth probability symbol group of the error probability 1 bit of the bit; 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the 3 bit of the symbol bit of the first good symbol bit group of the error probability Assigning 4 bits of the code bit of the 2nd good code bit group of the error probability to the 4 bits of the symbol bit of the second good symbol bit group of the error probability; 2 The 3 bits of the code bit of the good code bit group are assigned to the 3 bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 2nd good code bit of the error probability is The 2 bits of the code bit of the group are allocated to the 2 bits of the symbol bit of the 4th good symbol bit group of the error probability; 〇 the code bit of the 2nd good code bit group of the error probability The 2 bits of the element are assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the second probability of the error probability is 2 The 2 bits of the code bit of the group are allocated to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability The 1 bit is assigned to the 1st digit of the symbol bit of the 4th good symbol group of the error probability 133671. Doc -176- 200947881 ;元; 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to 1 bit of the symbol bit of the first good symbol bit group of the error probability The first bit of the code bit of the 4th good code bit group of the error probability is assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group of the error probability; 4: 1 bit of the code bit of the good code bit group is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group of the error probability; the error probability 4th good code bit element The 2 bits of the code bit of the group are allocated to the 2 bits of the symbol bit of the 5th good symbol bit group of the error probability; and the code bit of the 4th good code bit group of the error probability The 1st bit of the element is assigned to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability.  yuan. A data processing method includes a replacement step of a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the direction of the row. Memorize mb bits and memorize N/(mb) bits in the preceding wales, 133671. Doc-177·200947881 The code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row, and the mb bit read in the direction of the row of the memory mechanism In the case where the code bit of the element is used as the consecutive b symbols, the code of the mb bit is replaced according to the allocation rule for assigning the code bit of the LDPC code to the symbol bit representing the symbol. a bit, the replaced code bit is used as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 16200 bits, and the coding rate is 3/4 LDPC code; ® the above m bit is 12 bits, and the aforementioned integer b is 2; 12 bits of the aforementioned code bit are used as One of the aforementioned symbols is mapped to any one of 4096 signal points determined by 4096QAM; the memory mechanism includes 24 vertical lines that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the longitudinal direction. In the foregoing replacement step, the 12x2 bit code bit read out in the row direction of the memory mechanism is calculated from the most significant bit, the i+th bit ❹ is set to the bit bi, and will be continuous The symbol bits of the 12x2 bits of the two preceding symbols are set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit y!〇, assigning bit b! to bit y 0, assigning bit b2 to bit y 1, assigning bit b3 to bit y2, and assigning bit b4 to bit y3, 133671. Doc -178- 200947881 Assigning bit b5 to bit y4 'Assign bit b6 to bit ys ' Assign bit b7 to bit y6, bit b8 to bit y7, bit b9 The bit ys is assigned, the bit b! 〇 is assigned to the bit y9, 位 the bit b!! is assigned to the bit yi 1, the bit b! 2 is assigned to the bit y 1 2, the bit b is 3 is assigned to bit yi 4, bit b 丨 4 is assigned to bit y 15, bit b! 5 is assigned to bit y! 6, bit b! 6 is assigned to bit y22, bit is set The element b! 7 is assigned to the bit y 18, the bit b! 8 is assigned to the bit y23, the bit b19 is assigned to the bit y17, the bit b2G is assigned to the bit y丨9, and the bit b21 is assigned The bit y20 is given, the bit b22 is assigned to the bit y2 1, and the bit b23 is assigned to the bit y!3. 85.  a data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (L〇w Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding row direction and read in the preceding row direction is taken as one symbol, 133671. Doc • 179- 200947881 The specific positive integer is set to b, the memory mechanism memorizes mb bits in the foregoing row direction, and stores N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are in the foregoing memory Writing in the longitudinal direction of the mechanism, and then reading in the horizontal direction, and the code bits of the mb bits read in the direction of the memory of the memory mechanism are regarded as consecutive b symbols. Substituting the code bits for assigning the code bits of the foregoing LDPC code to the symbol bits representing the preceding symbols, replacing the code bits of the mb bits, and replacing the replaced code bits with the preceding symbols Bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as a group of symbol bits, and defines the following rules: 前述 the foregoing code bit group of the foregoing code bit element and the foregoing code bit element for allocating the code bit group The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits of the meta-bit; wherein the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212, ie, 4096 signal points, as one of the aforementioned symbols. In either case, 133671. Doc -180- 200947881 The group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into three groups of the aforementioned code bits; 12x2 bits of two consecutive symbols The foregoing symbol bit group is divided into 6 symbol bit groups; wherein the foregoing allocation rule specifies: assigning 1 bit of the code bit of the first good code bit group of the error probability to the error probability The 1st bit of the symbol bit of the 5th good symbol group; ® assigns the 1st bit of the code bit of the 1st good code bit group of the error probability to the error probability 6th good character 1 bit of the symbol bit of the meta-bit group; 4 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error probability 1st good symbol bit group 4 bits of the symbol bit; assign the 3 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the 2nd good symbol bit group of the error probability Bit ; element; assign 4 bits of the code bit of the 2nd good code bit group of the error probability to the 3rd good symbol of the error probability The 4th bit of the symbol group of the metagroup; the 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the symbol of the 4th good symbol group of the error probability 3 bits of the bit; 2 bits of the code bit of the 2nd good code bit group of the error probability are 133671. Doc -181 - 200947881 allocates the 2nd bit of the symbol bit of the 5th good symbol group of the error probability; assigns 1 bit of the code bit of the 3rd good code bit group of the error probability to The probability of the second probability is the 1st bit of the symbol bit of the second good symbol group; the 1st bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability 4th good 1 bit of the symbol bit of the symbol group; assign 1 bit of the code bit of the 3rd good code bit group of the error probability to the error probability 5th good symbol group 1 bit of the symbol bit of the group; and assigning the 3 bits of the code bit of the 3rd good code bit group of the error probability to the symbol bit of the 6th good symbol bit group of the error probability 3 yuan of yuan. 86.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low ❹ Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And 133671. Doc-182·200947881, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, according to the code bits for assigning the LDPC code to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 64800 bits, and the coding rate is 3/4 LDPC code; the m-bit is 12 bits, and the aforementioned integer b is 2; 12 12 bits of the aforementioned code bit are used as One of the preceding symbols is mapped to any one of 4096 signal points determined by 4096QAM; the memory mechanism includes 24 vertical lines that memorize 12 χ 2 bits in the horizontal direction and 64800/(12x2) in the vertical direction. Bits; in the foregoing replacement step, the 12-bit bits of the code bits read in the direction of the memory mechanism are set from the most significant bit, and the i-th bit is set to the bit bi, and will be continuous. The symbol bits of the 12x2 bits of the two preceding symbols are set from the most significant bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the previous allocation rule: assigning the bit bG to Bit y! 〇, assign bit bi to bit y8, bit b2 to bit y〇, bit b3 to bit y!, bit b4 to bit y2, bit The element b5 is assigned to the bit y3, and the bit b6 is assigned to the bit y4, 133671. Doc -183 - 200947881 assigns bit b7 to bit y5, bit b8 to bit y6, bit b9 to bit y7, bit b1G to bit yg, bit b! Assigned to bit y 12 ' Assign bit b12 to bit yi3 ' Assign bit b13 to bit y14, bit b]4 to bit y! 6, assign bit b! 5 to Bit y! 7, assigns bit bi 6 to bit y 18, bit b 17 to bit y20, bit b 8 to bit y丨5, and bit b 19 to bit The bit y 丨丨 assigns the bit b2G to the bit y22, the bit b 2 1 to the bit y 丨 9, the bit b22 to the bit y2i, and the bit b23 to the bit y23. 87.   A data processing method includes a replacement step of a memory mechanism of a code bit of an ldpc (low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code written in the wale direction in the row direction is taken as a symbol, and the specific positive integer is b, and the memory means is stored in the course direction. Mb bit and the first 133671. Doc 200947881 describes a longitudinal direction memory N/(mb) bit, the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row, and is in the memory mechanism In the case where the code bits of the mb bits read in the horizontal direction are consecutive b symbols, the code bits for the LDPC code are allocated to the symbol bits representing the symbols. The allocation rule replaces the code bit of the foregoing mb bit, and replaces the replaced code bit as the aforementioned symbol bit; 〇 the aforementioned LDPC code system is DVB-S. 2 or DVB-T. The code specified by the specification of 2; the length N is an LDPC code of 16200 bits; the foregoing allocation rule is to group the group of the aforementioned code bits as a group of code bits according to the error probability, and will be based on the error probability. The group distinguishes the group of the preceding symbol bits as the group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit and the foregoing code bit element for allocating the code bit group a combination of the preceding symbol bit groups of the symbol bit, that is, a group set, and the foregoing code bit group of the foregoing group of code bits and the foregoing symbol bit group and the foregoing The number of bits of the symbol bit; wherein the m bit is 12 bits, and the integer b is 2, and the 12 bits of the code bit are mapped to 212 or 4096 signal points as one of the preceding symbols. In the case of any one of the above, the group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into three groups of the aforementioned code bits; 133671. Doc -185- 200947881 The preceding symbol bit group of 12x2 bits of two consecutive symbols is divided into 6 symbol bit groups; in the foregoing allocation rule, it is specified that: the error probability first good code The 2 bits of the code bit of the bit group are assigned to the 2 bits of the symbol bit of the first good symbol bit group of the error probability; the code of the code group of the first good error bit of the error probability The 3-bit of the bit is allocated to the 3-bit of the symbol bit of the second-good symbol bit group of the error probability; ❿ 4 bits of the code bit of the error probability first good code bit group The element is assigned to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 4th bit of the code bit of the 1st good code bit group of the error probability is assigned to the error probability 4 4 bits of the symbol element of the good symbol group; the 1st bit of the code bit of the 1st good code bit group of the error probability is assigned to the error probability 5th good symbol 1 bit of the symbol bit of the bit group; the 4 bits of the code bit of the first good code bit group of the error probability are assigned to the error The 4th bit of the symbol bit of the 6th good symbol group; the 1st bit of the code bit of the 2nd good code bit group of the error probability is assigned to the 5th good character of the error probability 1 bit of the symbol bit of the meta-bit group; 133671. Doc -186- 200947881 assigns the 2 bits of the code bit of the 3rd good code bit group of the error probability to the 2 bit of the symbol bit of the first good symbol bit group of the error probability; The error probability 3rd good symbol bit group of the code bit is allocated to the 1st bit of the symbol probability of the 2nd good symbol bit group; and the error probability is 3rd. The 2 bits of the code bit of the code bit group are allocated to the 2 bit unit of the symbol bit of the 5th good symbol bit group of the error probability. 88.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction memory mb bit, and the N/(mb) bit is memorized in the preceding Q direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the foregoing direction. And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol element; 133671. Doc -187- 200947881 The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is 16200 bits, and the coding rate is 4/5 LDPC code; the m-bit is 12 bits, and the aforementioned integer b is 2; the 12-bit of the aforementioned code bit is 1 The preceding symbols are mapped to any one of 4096 signal points determined by 4096QAM; the memory mechanism includes 24 vertical lines that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the vertical direction. In the foregoing replacement step, the 12x2 bit code bit read out in the row direction of the memory mechanism is set from the most significant bit, the i+th bit is set to the bit bi, and 2 consecutive bits will be used. The 12x2 bit symbol bit of the preceding symbol is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y〇 Assigning bit b 1 to bit y 1, assigning bit b2 to bit y2, assigning bit b3 to bit y3, assigning bit b4 to bit y4, and allocating bit b5 to bit Element y5, assigning bit b6 to bit y6, assigning bit b7 to bit y7, assigning bit b8 to bit y8, and allocating bit b9 To the bit y1G, assign the bit b! 〇 to the bit y!!, and assign the bit b!! to the bit y! 4, 133671. Doc -188- 200947881 assigning bit b ! 2 to bit y 1 6 ' assigning bit b13 to bit yi7 ' assigning bit b14 to bit yi8 and bit b15 to bit yi9, will Bit b! 6 is assigned to bit y22', bit b17 is assigned to bit y23, bit b 丨 8 is assigned to bit y9, bit bi 9 is assigned to bit y20, bit b2G is assigned to Bit y12, bit b21 is assigned to bit y!3, bit b:22 is assigned to bit y1 5, and bit b23 is assigned to bit y21. 89.  - a data processing method 'which includes a replacement step 'which is a record of the LDPC (Low Density parity check) code of the LDPC (Low Density parity check) code whose length is N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is taken as a symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the foregoing wales of the memory mechanism and then in the direction of the row The code bit 7L read out and read in the aforementioned direction of the memory mechanism is regarded as a continuous |5 preceding symbols, 133671. Doc 200947881 replaces the code bit of the mb bit in accordance with the allocation rule for assigning the code bit of the foregoing LDPC code to the symbol bit representing the symbol, and replaces the replaced code bit as the symbol bit The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as a group of symbol bits, and defines the following rules: 前述 the foregoing code bit group of the foregoing code bit element and the foregoing code bit element for allocating the code bit group The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits of the meta-bit; wherein the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212, ie, 4096, Q-numbers as one of the aforementioned symbols. In the case of any one of the points, the group of code bits of the 12x2 bit read in the direction of the preceding direction of the memory means is divided into five groups of the preceding code bits; The preceding symbol bit group of 12x2 bits is divided into 6 symbol bit groups; The foregoing allocation rule defines: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1st bit of the symbol bit of the fifth good symbol bit group of the error probability 133671 . Doc -190- 200947881 yuan; assign 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability Assigning 1 bit of the code bit of the second good code bit group of the error probability to the 1 bit of the symbol bit of the first good symbol bit group of the error probability; 3 bits of the code bit of a good code bit group ® 3 bits of the symbol bit of the first good symbol bit group of the error probability; 3rd good code bit of the error probability The 4 bits of the code bit of the group are allocated to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability The 3 bits are allocated to the 3 bits of the symbol bit of the 3rd good symbol bit group of the error probability; 4 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned Give the 4th bit of the symbol bit of the 4th good symbol group of the error probability; 2 bits of the code bit of the 3rd good code bit group of the error probability The second bit of the symbol bit of the fifth-perceived bit group of the error probability is assigned; the one bit of the code bit of the fourth-perfect code bit group of the error probability is assigned to the error probability third. 1 bit 133671 of the symbol bit of the symbol group. Doc -191 - 200947881 yuan; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the 1 bit of the symbol bit of the 5th good symbol bit group of the error probability And assigning the 3 bits of the code bit of the 5th good code bit group of the error probability to the 3 bit of the symbol bit of the 6th good symbol bit group of the error probability. 90.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low © Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the preceding wale direction, the code bits of the LDPC code are written in the longitudinal direction Q direction of the memory mechanism, and then read in the foregoing direction. And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code specified by the specification of 2 has a length N of 64,800 bits and an LDPC code with a coding rate of 4/5; 133671. Doc -192- 200947881 The m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to any of the 4096 signal points determined by 4096QAM. The memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 64800/(12x2) bits in the waling direction; the replacement step is read in the course direction of the memory mechanism. The 12x2 bit code bit is set from the most significant bit, the i+th bit is set to the bit bi, and the symbol 2 bits of the 12x2 bits of the preceding two symbols are counted from the most significant bit. The i+1th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit y! 〇, assigning the bit b! to the bit y8, and allocating the bit b2 Giving bit y, assigning bit b3 to bit y!, assigning bit b4 to bit y2, assigning bit b5 to bit y3, and assigning bit b 6 to bit y 4, Bit b7 is assigned to bit y5, bit b8 is assigned to bit y6, bit b9 is assigned to bit y7, bit b! 〇 is assigned to bit y9 B η bits assigned to the bit y! 2, the bit b! 2-bit is assigned to y 1 3, the bit b! 3 bits assigned to y 14, 133671. Doc -193- 200947881 assigns bit b ! 4 to bit y 1 5, bit b15 to bit y16, bit b! 6 to bit y 18, bit b17 to bit Y19, assigning bit b! 8 to bit y20, assigning bit b! 9 to bit y 1 7, assigning bit b2G to bit y2!, and assigning bit b2! to bit yn, The bit b22 is assigned to the bit y22, and the bit b23 is assigned to the bit y23. 91.  A data processing method includes a replacement step of a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the direction of the row. Memorizing mb bits, and storing N/(mb) bits in the longitudinal direction. The code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the foregoing direction, and In the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are assigned to the symbol. The allocation rule of the symbol bit, replacing the code bit of the aforementioned mb bit, 133671. Doc • 194- 200947881 The replaced code bit is used as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 16,200 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as a group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit element and the aforementioned code bit element of the code bit group. The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits of the meta-bit; wherein the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212, ie, 4096 signal points, as one of the aforementioned symbols. In either case, the group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into four groups of the aforementioned code bits; 12x2 bits of two consecutive symbols The preceding symbol element group of the element is divided into 6 symbol element groups; The allocation rule defines: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 6th good symbol bit group of the error probability; The 4th bit of the code bit of the 2nd good code bit group of the error probability is 133671. Doc •195· 200947881 allocates the 4-bit element of the symbol bit of the first good symbol group of the error probability; assigns the 3 bits of the code bit of the second good symbol group of the error probability to The error probability is the 2nd good symbol of the symbol element of the 2nd good symbol group; the 3rd bit of the code bit of the 2nd good code bit group of the error probability is assigned to the error probability 3rd good 3 bits of the symbol bit of the symbol element group; 3 bits of the code bit of the 2nd good code bit group of the error probability are assigned to the error probability 4th good symbol bit group 3 bits of the group of symbol bits; assign the 3 bits of the code bit of the 2nd good code bit group of the error probability to the symbol bit of the 5th good symbol group of the error probability 3 bits; assigning 2 bits of the code bit of the second good symbol bit group of the error probability to the 2 bits of the symbol bit of the 6th good symbol bit group of the error probability; Assigning 1 bit of the code bit of the 3rd good code bit group of the error probability to 1 bit of the symbol bit of the 5th good symbol bit group of the error probability The first bit of the code bit of the 4th good code bit group of the error probability is assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group of the error probability; 4 good code bit group of the code bit 1 bit 133671. Doc -196- 200947881 allocates 1 bit of the symbol bit of the 3rd good symbol group of the error probability; assigns 1 bit of the code bit of the 4th good code bit group of the error probability to The error probability is the first bit of the symbol bit of the 4th good symbol group; and the 1 bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 6th good One bit of the symbol bit of the symbol group. ® 92.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row. And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for using the LDPC code are allocated to represent the symbols. The allocation rule of the symbol bit is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T. The code specified by the specification of 2 133671. Doc -197- 200947881 LDPC code with a length N of 16200 bits and a coding rate of 5/6; the m-bit is 12 bits, and the aforementioned integer b is 2; 12 bits of the aforementioned code bit are used as one The symbol is mapped to any one of 4096 signal points determined by 4096QAM; the memory mechanism includes 24 vertical lines that memorize 12x2 bits in the horizontal direction and 16200/(12x2) bits in the longitudinal direction; The foregoing replacement step is that the 12-bit bit of the code bit read out in the row direction of the memory mechanism is set from the most significant bit, the i-th bit is set to the bit bi, and two consecutive symbols are consecutive. The 12x2 bit symbol element of the element is set to the bit element yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: the bit element bQ is assigned to the bit element y 1 〇, The bit b! is assigned to the bit y 〇, the bit b2 is assigned to the bit y 1, the bit b3 is assigned to the bit y2, the bit b4 is assigned to the bit y3, and the bit b 5 is assigned Bit y 4, assign bit b6 to bit y5, bit b7 to bit y6, bit b8 to bit y7, bit b9 To the bit y8, the bit b! Billion bits assigned to y 9, the bit b !! assigned to the bit y 1 !, bit b! 2-bit is assigned to y 1 2, 133671. Doc -198- 200947881 Assign bit bi 3 to bit y! 3, assign bit b! 4 to bit y! 4, assign bit bi 5 to bit y! 6, place bit b! 6 assigned to bit y! 8. , assign bit b! 7 to bit y20, assign bit b丨8 to bit y22, assign bit b! 9 to bit y2丨, and assign bit b2G to bit y23, ® Bit b21 is assigned to bit y 19, bit b22 is assigned to bit y 1 7 , and bit b23 is assigned to bit y 1 5 . 93.  a data processing method, comprising: a replacement step, which is a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the above-mentioned horizontal direction. The column direction memorizes mb bits, and stores N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then read in the row direction And in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to represent the aforementioned symbols. 133671. Doc -199· 200947881 The allocation rule of the symbolic element of the element replaces the code bit of the aforementioned mb bit, and replaces the replaced code bit as the above-mentioned symbol bit; The aforementioned LDPC code is DVB-S. 2 or DVB-T. The code length N specified by the specification of 2 is an LDPC code of 64,800 bits; the foregoing allocation rule is to group the group of the foregoing code bits as a group of code bits according to the error probability, and the group will be grouped according to the error probability. The group distinguishes the group of the preceding symbol bits as a group of symbol bits, and defines the following rules: the foregoing code bit group of the foregoing code bit element and the aforementioned code bit element of the code bit group. The combination of the foregoing symbol bit group of the symbol bit, that is, the group set, and the foregoing code bit group of the foregoing group set and the symbol bit group of the foregoing symbol bit group and the foregoing symbol The number of bits of the meta-bit; wherein the m-bit is 12 bits, and the integer b is 2, and the 12-bit of the code bit is mapped to 212, ie, 4096 signal points, as one of the aforementioned symbols. In either case, the group of code bits of 12x2 bits read in the foregoing direction of the memory mechanism is divided into three groups of the aforementioned code bits; 12x2 of two consecutive symbols The preceding symbol bit group of the bit is divided into 6 symbol bit groups; The foregoing allocation rule defines: assigning 1 bit of the code bit of the first good symbol bit group of the error probability to the 1 bit of the symbol bit of the 4th good symbol bit group of the error probability ; 133671. Doc -200- 200947881 assigns 1 bit of the code bit of the error probability first good code bit group to 1 bit of the symbol bit of the 6th good symbol bit group of the error probability; The 4th bit of the code bit of the 2nd good code bit group is assigned to the 4th bit of the symbol bit of the first good symbol bit group of the error probability; the error probability is 2nd good The 4 bits of the code bit group of the code bit group are assigned to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability Assigning 4 bits of the code bit of the second good symbol bit group of the error probability to the 4 bits of the symbol bit of the 3rd good symbol bit group of the error probability; The 2 bits of the code bit of the code bit group are assigned to the 2 bit of the symbol bit of the 4th good symbol bit group of the error probability; the 2nd good code bit group of the error probability The 4 bits of the code bit are assigned to the 4th bit of the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability is 1 The bit is allocated to the 1-bit of the symbol bit of the 4th good symbol bit group of the error probability; _ and the 3 bits of the code bit of the 3rd good code bit group of the error probability are assigned to Error probability 6th good symbol group of the symbol group 3 bits 0 133671.doc -201 · 200947881 94. A data processing method comprising a replacement step, which is in the course direction and the wales The memory unit of the LDPC (Low Density Parity Check) code of the N-bit LMC is in the foregoing vertical direction. The m-bit of the code bit of the LDPC code read in the direction of the horizontal direction is defined as one symbol, and the specific positive integer is b, and the memory mechanism stores mb bits in the direction of the preceding row. And storing N/(mb) bits in the longitudinal direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the direction of the row, and In the case where the code bits of the mb bits read by the preceding direction of the memory mechanism are regarded as consecutive b symbols, the symbol bits for assigning the LDPC code are assigned to the symbols representing the symbols. a bit allocation rule, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is defined by the specifications of DVB-S.2 or DVB-T.2 The code ❹ length N is 64800 bits, and the coding rate is 5/6 LDPC code; the m bit is 12 bits, and the aforementioned integer b is 2; the 12 bits of the code bit are used as one of the aforementioned symbols. Mapping to any of the 4096 signal points determined by 4096QAM; the aforementioned memory mechanism is included in the horizontal Memory 24 bits of 12x2 bits, memory 64800/(12x2) bits in the wale direction; in the foregoing replacement step, the 12x2 bits of the code bits read from the direction of the memory mechanism are highest The valid bit counts the i+th bit 133671.doc -202- 200947881 and is set to the bit bi, and the symbol bits of the 12x2 bits of the consecutive two descriptive symbols are counted from the most significant bit. The i+1 bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit y 1 〇 ' assigning the bit b! to the bit y 6 ' assigning the bit b2 Bit y〇, assigning bit b3 to bit y 1, assigning bit b4 to bit y2 ' Ο Assigning a bit to bit y3, assigning bit b6 to bit y4, assigning bit b7 to bit y5, assigning bit b8 to bit y7, and assigning bit b9 to bit y8' The bit h 〇 is assigned to the bit y9 'the bit b! 1 is assigned to the bit yi2'. The bit b 丨 2 is assigned to the bit y 13, the bit b13 is assigned to the bit yi4 ' The bit b14 is allocated The bit yi5 is assigned, the bit b15 is assigned to the bit yi6, the bit b16 is assigned to the bit yn, the bit b! 7 is assigned to the bit y 18, and the bit b 18 is assigned to the bit y2〇' Assigning bit b19 to bit y2i' assigns bit b2〇 to bit y 11, 133671.doc -203· 200947881 assigns bit b2i to bit y22 and bit b22 to bit y 19, Bit b23 is assigned to bit y23. 95. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is an LDPC code of 16,200 bits; The rule is that the group of the foregoing code bit groups is grouped as a code bit group according to the error probability, and the group of the aforementioned symbol bit groups is grouped according to the error probability as the symbol bit group, and The following rules are defined: 133671.doc -204- 200947881 The foregoing code bit group of the foregoing code bit element and the foregoing symbol bit group of the aforementioned symbol bit element of the code bit element to which the code bit group is allocated a combination of the groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; a 12-bit, and the integer b is 2, and 12 bits of the code bit are mapped as one of 212 symbols, that is, 4096 signal points, as one of the aforementioned symbols, and the memory mechanism is The group of code bits of the 12x2 bit read in the horizontal direction is divided into five groups of the aforementioned code bits; the group of the preceding symbol bits of the 12x2 bits of the consecutive two preceding symbols is divided into 6 a group of symbolic bits; as stated in the foregoing allocation rules: The 2 bits of the code bit of the first good code bit group of the probability are assigned to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability; ◎ The error probability is 2nd good One bit of the code bit of the code bit group is assigned to the one bit of the symbol bit of the sixth good symbol bit group of the error probability; the error probability third good code bit group The 4 bits of the code bit are assigned to the 4 bits of the symbol bit of the first good symbol bit group of the error probability; 4 bits of the code bit of the 3rd good code bit group of the error probability The element is assigned to the 4th bit of the symbol bit of the 2nd good symbol bit group of the error probability 133671.doc -205- 200947881 yuan; the code bit of the 3rd good code bit group of the error probability is 4 The bit is allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 4th bit of the code bit of the 3rd good code bit group of the error probability is assigned to the error probability The 4th bit of the symbol bit of the 4th good symbol group; the 2 bit of the code bit of the 3rd good code bit group of the error probability is assigned to the wrong The 2nd factor of the symbol bit of the 5th good symbol bit group of the probability is 5; the 1st bit of the code bit of the 4th good code bit group of the error probability is assigned to the error probability 5th good 1 bit of the symbol bit of the symbol bit group; assign 1 bit of the code bit of the 5th good code bit group of the error probability to the error probability 5th good symbol bit group 1 bit of the symbol bit; and 1 assign 1 bit of the code bit of the 5th good code bit group of the error probability to the symbol of the 6th good symbol group of the error probability One yuan of yuan. 96. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read by the mechanism in the preceding direction is read as one symbol, and the specific positive integer is set to 133671.doc -206-200947881. b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used The code bit is allocated to the allocation rule indicating the symbol element of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 1620 0 bit, LDPC code with a coding rate of 8/9; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols Any one of 4096 signal points; the memory mechanism includes 24 wales of 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; The 12x2 bit code bit read by the direction of the mechanism is set to the bit bi from the most significant bit, and the symbol of 12x2 bits of the preceding two symbols is consecutively The bit is calculated from the most significant bit, and the i+1th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit y! 〇, assigning the bit b! to the bit Yuan y! i, 133671.doc -207- 200947881 assigns bit b2 to bit y22, bit b3 to bit y〇, bit b4 to bit y 1, assigns bit b5 to Bit y2, assigning bit b6 to bit y3, bit b7 to bit y4, bit b8 to bit y5, and bit b9 to bit Bit y6, assigns bit b! 〇 to bit y7, bit b 11 to bit y 8, assigns bit b! 2 to bit y 9 ' assigns bit bi 3 to bit y 12, assigning bit b! 4 to bit y 1 3, assigning bit b 15 to bit y 14, assigning bit th 6 to bit y 15, assigning bit th 7 to bit Y 16, assigning bit b! 8 to bit y 17, assigning bit b! 9 to bit y 1 8, assigning bit b2G to bit y 1 9, assigning bit b2! to bit The element y2 〇 assigns the bit b22 to the bit y2 1, and assigns the bit b23 to the bit y23. 97. A data processing method comprising a replacement step of LDPC having a memory code length of N bits in a row direction and a longitudinal direction (Low-208-133671.doc 200947881 Density Parity Check: Low Density Parity Check) The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means of the code bit in the preceding direction is set as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing course direction, and the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used to The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 648. 00-bit LDPC code; the foregoing allocation rule is to group the group of the aforementioned code bits into groups according to the error probability as a group of code bits, and group the group of the aforementioned symbols according to the error probability The group is a group of symbol bits, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the foregoing symbol element of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination of bit groups, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of each of the foregoing symbol bit groups and the number of bits of the foregoing symbol bit; 133671. Doc-209-200947881 wherein the m-bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of the aforementioned symbols to 212, ie, 4096 signal points. In the case of the 12x2 bits read in the direction of the memory mechanism, the group of code bits is divided into five groups of the code bits; the foregoing two consecutive symbols of 12x2 bits are as described above. The symbol element group is divided into 6 symbol element groups; The matching rule stipulates: assigning the 2-bit code of the code bit of the first good symbol bit group of the error probability to the 2-bit of the symbol bit of the 6th good symbol bit group of the error probability Assigning 1 bit of the code bit of the 2nd good code bit group of the error probability to the 1st bit of the symbol bit of the 6th good symbol bit group of the error probability; The 4 bits of the code bit of the good code bit group are assigned to the 4 bit unit of the symbol bit of the first good symbol bit group of the error probability; the error probability third good code bit element The 4 bits of the code bit of the group are allocated to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability The 4 bits are allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 4th bit of the code bit of the 3rd good code bit group of the error probability is 133671 .doc -210- 200947881 The 4th bit of the symbol bit of the 4th good symbol group of the error probability; the 3rd good code bit group with the error probability The 2 bits of the code bit are assigned to the 2 bit of the symbol bit of the 5th good symbol bit group of the error probability; the code bit of the 4th good code bit group of the error probability is 1 The bit is assigned to 1 bit of the symbol bit of the 5th good symbol bit group of the error probability; ® 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error 1 bit of the symbol bit of the 5th good symbol bit group of the probability; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 6th good One bit of the symbol bit of the symbol element group. 98. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low ❹ Density Parity Check) code having a memory code length of N bits in a horizontal direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the memory means in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Read, and 133671.doc -211 - 200947881, in the case where the mb bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as consecutive b symbols, according to the LDPC code used to The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by the .2 or DVB-T.2 specification is 64800 bits, LDPC code with a coding rate of 8/9; the aforementioned m bits are 12 bits, and the aforementioned integer b is 2; 12 bits of the above code bits are mapped to ® 4096QAM as one of the aforementioned symbols Determining any one of 4096 signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the row direction and 64800/(12x2) bits in the waling direction; The 12x2 bit code bit read by the direction of the memory mechanism is set to the bit bi from the most significant bit, and the 12x2 bit of the preceding symbol is consecutively The i-th bit from the most significant bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the previous allocation rule: the bit bG is assigned to the bit y 1 〇, and the bit b! Assigned to bit y!!, bit b2 is assigned to bit y22, bit b3 is assigned to bit yG, bit b4 is assigned to bit y 1, bit b 5 is assigned to bit y 2 , assigning bit b6 to bit y3, 133671.doc -212- 200947881 assigning bit b7 to bit y4 assigning bit b8 to bit y5 dividing bit b9 To the bit y6 'will be assigned to the bit b i billion bits y7'. 1 the bits b! Allocated bit y 8 '〗 the bit b 2 to the bit y9' 分配 Assign bit b! 3 to bit y 12 ' Assign bit b ! 4 to bit y 1 3 ' Assign bit b! 5 to bit y Μ ' Assign bit b 16 to bit y 15 'Assign bit b 17 to bit yi 6, assign bit b 8 to bit y! 7, assign bit b19 to bit y18, and assign bit b2G to bit y丨9 The bit b21 is assigned to the bit y20, the bit b22 is assigned to the bit y21, and the bit b23 is assigned to the bit y23. 99. A data processing method, comprising: a replacement step of a code bit of an LDpc (L〇w Density Parity Check) code having a memory code length of N bits in a row direction and a longitudinal direction The memory element is written in the longitudinal direction and the bit position of the LDPC code read in the horizontal direction is regarded as one symbol, and the specific positive integer is set to b. The mechanism memorizes mb bits in the foregoing direction, and stores the N/(mb) bits in the wale direction in the previous J33671.doc • 213·200947881, and the code bits of the LDPC code are in the foregoing longitudinal direction of the memory mechanism. Writing, and then reading in the above-mentioned course direction, and in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, The code bit of the foregoing LDPC code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code system Codes specified in the specifications of DVB-S.2 or DVB-T.2® N is a 64800-bit LDPC code; the foregoing allocation rule is to group the group of the foregoing code bits according to the error probability as a group of code bits, and group the above-mentioned symbol bits according to the error probability. The group is a group of symbol bits, and the following rules are defined: the foregoing code bit group of the foregoing code bit element and the aforementioned symbol bit of the foregoing symbol bit element of the code bit element to which the code bit group is allocated a combination Q of the meta-bit group, that is, a group set, and the foregoing code bit group of the foregoing group set and the bit number of the foregoing symbol bit group and the number of bits of the foregoing symbol bit; Where the m-bit is 12 bits, and the integer b is 2, and 12 bits of the code bit are mapped as one of the 212 symbols, ie, 4096 signal points, as one of the symbols, The group of code bits of the 12x2 bit read by the aforementioned direction of the memory mechanism is divided into five groups of the aforementioned mbits; 133671.doc • 214-200947881 2x2 bits of two consecutive symbols The preceding symbol bit group is divided into 6 symbol bit groups; The foregoing allocation rule defines: assigning 2 bits of the code bit of the first good symbol bit group of the error probability to the 2 bit of the symbol bit of the 6th good symbol bit group of the error probability Assigning 1 bit of the code bit of the 2nd good code bit group of the error probability to the 1st element of the symbol bit of the 5th good symbol bit group of the error probability; 3 4 bits of the code bit of the good code bit group are assigned to the 4 bit of the symbol bit of the first good symbol bit group of the error probability; the error probability third good code bit element The 4 bits of the code bit of the group are allocated to the 4 bits of the symbol bit of the 2nd good symbol bit group of the error probability; the code bit of the 3rd good code bit group of the error probability The 4 bits are allocated to the 4th bit of the symbol bit of the 3rd good symbol bit group of the error probability; the 4 bits of the code bit of the 3rd good code bit group of the error probability are assigned to The 4th bit of the symbol bit of the 4th good symbol bit group of the error probability; the 2 bit of the code bit of the 3rd good code bit group of the error probability 2 bits of the symbol bit assigned to the 5th good symbol bit group of the error probability; 133671.doc -215- 200947881 1 bit of the code bit of the 4th good code bit group of the error probability 1 bit assigned to the symbol bit of the 6th good symbol bit group of the error probability; 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the error probability 5th 1 bit of the symbol element of the good symbol group; and 1 bit of the code bit of the 5th good code bit group of the error probability is assigned to the 6th good symbol of the error probability One bit of the symbol element of the metagroup. 100. A data processing method, comprising: a replacement step, which is a memory of a code bit of an LDPC (Low Density Parity Check) code having a memory code length of N bits in a horizontal direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written by the mechanism in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and stores N/(mb) bits in the longitudinal direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then read in the preceding direction And, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are consecutive b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol element; 133671.doc •216- 200947881 The aforementioned LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 64800 The LDPC code with a bit rate and a coding rate of 9/10; the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped to 4096QAM as one of the aforementioned symbols. Any one of 4096 signal points; the memory mechanism includes 24 vertical lines that memorize 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction; In the foregoing replacement step, the 12x2 bit code bit read out in the row direction of the memory mechanism is calculated from the most significant bit, and the i+th bit is set to the bit bi, and two consecutive The symbol of the 12x2 bit of the symbol is calculated from the most significant bit. The i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y! , assigning the bit b! to the bit y!!, assigning the bit b2 to the bit ys, assigning the bit b3 to the bit y, and assigning the bit t&gt;4 to the bit y 1, placing the bit Element b 5 is assigned to bit y 2, bit b6 is assigned to bit y3, bit b7 is assigned to bit y4, bit b 8 is assigned to bit y 5 , bit b9 is assigned to bit Y6, assign the bit b! 〇 to the bit y 7, assign the bit b!! to the bit y9, 133671.doc -217- 200947881 assign the bit b12 to the bit yi2, and place the bit b! Assigned to bit y! 3, assign bit bi 4 to bit y 14, assign bit b! 5 to bit y 15, assign bit b! 6 to bit yi 6, place bit b ! 7 is assigned to bit y 17, bit b! 8 points The allocation bit y! 8, assigns the bit b ! 9 to the bit y 1 9, assigns the bit b2 () to the bit y20, assigns the bit b21 to the bit y22, and assigns the bit b22 to the bit Element y23, bit b23 is assigned to bit y2 1. 218- 133671.doc