TW200937872A - Data processing device and data processing method - Google Patents
Data processing device and data processing method Download PDFInfo
- Publication number
- TW200937872A TW200937872A TW97145355A TW97145355A TW200937872A TW 200937872 A TW200937872 A TW 200937872A TW 97145355 A TW97145355 A TW 97145355A TW 97145355 A TW97145355 A TW 97145355A TW 200937872 A TW200937872 A TW 200937872A
- Authority
- TW
- Taiwan
- Prior art keywords
- bit
- code
- bits
- assigned
- symbol
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
200937872 九、發明說明: 【發明所屬之技術領域】 本發明係關於資料處理裝置及資料處理方法,特別關於 可使對於例如資料之錯誤之耐受性提升之資料處理裝置及 資料處理方法。 【先前技術】 LDPC碼具有高度之失誤訂正能力,近年來開始廣泛採 用於例如包含歐洲所進行之DVB(Digital Video Broadcasting φ :數位視訊廣播)-S.2等衛星數位播放在内之傳送方式(參 考例如非專利文獻1)。而且,LDPC碼亦檢討採用於下一 代之地面數位播放。 根據近年來之研究逐漸得知,LDPC碼係與渦輪碼等相 同,隨著碼長增長會獲得接近向農極限(Shannon limit)之 性能。而且,由於LDPC碼具有最小距離與碼長成比例之 性質,因此作為其特徵係區塊失誤概率特性佳,進一步作 為優點亦可舉出幾乎不產生在渦輪碼等之解碼特性所觀測 ® 到之所謂錯誤地板(error floor)現象。 以下,具體說明關於該類LDPC碼。此外,LDPC碼為線 性碼,未必要為二元,但於此說明作為二元。 LDPC碼之最大特徵為定義該LDPC碼之檢查矩陣(parity check matrix :同位校驗矩陣)鬆散。於此,鬆散之矩陣係 指矩陣要素"1"之個數非常少之矩陣(大部分之要素為0之矩 陣)。 圖1係表示LDPC碼之檢查矩陣Η之例。 135786.doc 200937872 於圖1之檢查矩陣Η,各行之權重(行權重)("1"之數 目)(weight)為"3",且各列之權重(列權重)為"6"。 於藉由LDPC碼所進行之編碼(LDPC編碼),例如根據檢 查矩陣Η來將生成矩陣G生成,將該生成矩陣G對於二元之 資訊位元乘算,藉此生成碼字(LDPC碼)。 具體而言’進行LDPC編碼之編碼裝置係首先於與檢查 矩陣Η之轉置矩陣Ητ間,算出式GHT=0會成立之生成矩陣 G。於此’生成矩陣G為K>N矩陣之情況下,編碼裝置係 對於生成矩陣G乘算由K位元所組成之資訊位元之位元串 列(向量u),生成由N位元所組成之碼字c(=uG) »藉由該編 碼裝置所生成之碼字(LDPC碼)係經由特定之通訊道而於接 收側被接收》 LDPC碼之解碼係界洛格(Gallager)稱作概率解碼 (Probabilistic Decoding:機率解碼)所提案之運算法,可 藉由利用在由可變節點(variable node(亦稱為訊息節點 (message node)))及校驗節點(check node)所組成之所謂 Tanner 圖(Tanner graph)上之概率傳遞(belief pr〇pagati〇n) 之訊息傳播運算法來進行。於此,以下亦適宜地將可變節 點及校驗節點僅稱為節點》 圖2係表示LDPC碼之解碼程序。 此外,以下適宜地將以對數概度比(log likeUh〇〇d rati〇) 所表現之接收側所接收到之L D P C碼(1碼字)之第丨個碼位元 之值"0”概似度之實數值’稱為接收值…"而且,從校驗 節點所輸出之訊息設為Uj ’從可變節點所輸出之訊息設為 135786.doc 200937872 首先’於LDPC碼之解碼中,如圖2所示,於步驟SH , 接收LDPC碼,訊息(校驗節點訊息)Uj初始化為"〇",並且 取定作為重複處理之計數器之整數之變數k初始化為"〇", 並前進至步驟S12。於步驟S12,藉由根據接收LDpc碼而 獲得之接收值uGi ’進行式(1)所示之運算(可變節點運算), 以求出訊息(可變節點訊息)Vi,並進一步藉由根據該訊息 L ’進行式(2)所示之運算(校驗節點運算),以求出訊息 Φ Uj。 [數1] dv-1BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a data processing method, and more particularly to a data processing apparatus and a data processing method which can improve the tolerance to errors such as data. [Prior Art] The LDPC code has a high degree of error correction capability, and has been widely used in recent years for transmission methods including, for example, DVB (Digital Video Broadcasting φ)-S.2 satellite digital broadcasting in Europe ( For example, Non-Patent Document 1). Moreover, the LDPC code is also reviewed for use in the next generation of terrestrial digital broadcasting. According to recent research, the LDPC code system is the same as the turbo code, and as the code length increases, the performance close to the Shannon limit is obtained. Moreover, since the LDPC code has a property that the minimum distance is proportional to the code length, it has a good probability of error in the characteristics of the block, and further advantages are also obtained by observing the decoding characteristics of the turbo code or the like. The so-called error floor phenomenon. Hereinafter, the LDPC code of this type will be specifically described. Further, the LDPC code is a linear code and is not necessarily binary, but is described here as a binary. The biggest feature of the LDPC code is that the parity check matrix (parity check matrix) defining the LDPC code is loose. Here, the loose matrix refers to a matrix with a very small number of matrix elements "1" (most of the elements are matrixes of 0). Fig. 1 is a diagram showing an example of a check matrix LDP of an LDPC code. 135786.doc 200937872 In the check matrix of Figure 1, the weight of each row (the weight of the row) ("1" the weight) is "3", and the weight of each column (column weight) is "6" . The encoding is performed by the LDPC code (LDPC encoding), for example, according to the check matrix Η, and the generating matrix G is multiplied for the binary information bits, thereby generating a codeword (LDPC code). . Specifically, the coding apparatus that performs LDPC coding first calculates a generation matrix G in which the equation GHT = 0 is established between the transposed matrix Ητ of the check matrix 。. In the case where the 'generating matrix G is a K>N matrix, the encoding device multiplies the bit matrix (vector u) of the information bits composed of K bits by the generating matrix G, and generates N bits. The code word c(=uG) composed of the code word (LDPC code) generated by the encoding device is received on the receiving side via a specific communication channel. The decoding system of the LDPC code is called Gallager. Probabilistic Decoding (Probabilistic Decoding) algorithm can be used by a variable node (also known as a message node) and a check node. The message propagation algorithm of the probability transfer (belief pr〇pagati〇n) on the Tanner graph is performed. Here, the variable node and the check node are also simply referred to as nodes in the following. FIG. 2 is a decoding procedure of the LDPC code. In addition, the value of the third code bit of the LDPC code (1 code word) received by the receiving side represented by the log-like probability ratio (log like Uh〇〇d rati〇) is suitably hereinafter "0" The real value of the degree is called the received value..." Moreover, the message output from the check node is set to Uj 'The message output from the variable node is set to 135786.doc 200937872 First, in the decoding of the LDPC code, As shown in FIG. 2, in step SH, the LDPC code is received, the message (check node message) Uj is initialized to "〇", and the variable k which is determined as the integer of the counter of the repeated processing is initialized to "〇" And proceeding to step S12. In step S12, the operation (variable node operation) of equation (1) is performed by the received value uGi ' obtained by receiving the LDpc code to obtain a message (variable node information) Vi, and further obtains the message Φ Uj by performing the operation (check node operation) according to the equation (2) according to the message L '. [1] dv-1
Vi=U〇j+ Σ Uj j=1 • · · (1) [數2] tanhVi=U〇j+ Σ Uj j=1 • · · (1) [Number 2] tanh
Ui :VtanhUi : Vtanh
ViVi
• · · (2) 於此,式(1)及式(2)之dv及de係分別表示檢查矩陣h之縱 向(行)及橫向(列)之"1"之個數之可任意選擇之參數,例如 於碼(3,6)之情況時,dv=3、de=6。 此外,於式(1)之可變節點運算及(2)之校驗節點運算, 由於分別不將從欲輸出訊息之分枝(edge :邊線)(連結可變 節點與校驗節點之線)所輸入之訊息,作為運算之對象, 因此運算之範圍為1至dv-l、或1至dc-l。而且,式(2)之校 驗節點運算實際上係藉由事先製作以對於2輸入Vl,v2之1輸 135786.doc 200937872 出所疋義之式(3)所不之函數r(Vi,V2)之表,將其如式⑷所 示連續地(回歸地)利用而進行。 [數3] x=2tanh~i {tanh (ν,/2) tanh (v2/2) J =R (Vl, v2) • · · (3) [數4] uj =R (V!,R (v2, R (v3, _ · .R (vdc_2 Vdc i)))) ❹ .· · (4) 於步驟S12,進一步將變數k僅遞增"1",並前進至步驟 S13。於步驟Si3,判定變數]^是否大於特定重複解碼次數 C。於步驟S13,㈣變數k不大於〇之情況時,返回步驟 S12,以下重複同樣處理。 而且於步驟s13,判定變數k大於匚之情況時,前進至 步驟S14 ’藉由進行式(5)所示之運算,求出並輸出作為最 終輸出之解碼結果之訊息Vi,LDpc碼之解碼處理終了。 φ [數 5] dy• (2) Here, the dv and de of the equations (1) and (2) respectively indicate that the number of the longitudinal (row) and the horizontal (column) of the inspection matrix h can be arbitrarily selected. The parameters are, for example, in the case of the code (3, 6), dv = 3, and de = 6. In addition, the variable node operation of equation (1) and the check node operation of (2) are not branched from the desired output (edge: edge) (the line connecting the variable node and the check node) The input message is the object of the operation, so the calculation range is from 1 to dv-l, or from 1 to dc-l. Moreover, the check node operation of the equation (2) is actually performed by a function r(Vi, V2) which is not previously produced by the equation (3) which is 疋 786786.doc 200937872 for 2 inputs V1, v2. The table was carried out continuously (regressively) as shown in the formula (4). [Equation 3] x=2tanh~i {tanh (ν,/2) tanh (v2/2) J =R (Vl, v2) • · · (3) [Number 4] uj =R (V!,R ( V2, R (v3, _ . . . . ( ( ( ( ( ( ( ( ( ( In step Si3, it is determined whether the variable ^^ is greater than a specific number of repeated decodings C. In step S13, if the variable k is not greater than 〇, the process returns to step S12, and the same process is repeated below. Further, if it is determined in step s13 that the variable k is larger than 匚, the process proceeds to step S14', and the operation shown in the equation (5) is performed to obtain and output the message Vi as the final output decoding result, and the decoding process of the LDpc code is performed. end. Φ [number 5] dy
Vi=U〇i+ Σ Uj j=1 • · · (5) 於此,式(5)之運算係與式之可變節點運算不同,利 用來自連接於可變節點之所有分枝之訊息Uj來進行。 圖3係表示(3,6)LDPC碼(編碼率1/2、碼長12)之檢查矩陣 Η之例 於圖3之檢查矩陣η,與圖丨相同,分別而言,行之權重 135786.doc 200937872 為3,列之權重為6。 圖4係表示圖3之檢查矩陣Η之Tanner圖。 於此,圖4中,校驗節點係以” + "表示,可變節點係以 "="表示。校驗節點及可變節點分別對應於檢查矩陣11之列 及行。校驗節點與可變節點間之結線為分枝(edge :邊 線),相當於檢查矩陣之要素"1 ·,。 亦即,檢查矩陣之第j列第i行之要素為丨之情況時,於圖 4,藉由分枝連接從上第i個可變節點("="之節點)與從上第 ❿』個校驗節點(" + ”之節點)。分枝係表示對應於可變節點之 瑪位元具有對應於校驗節點之限制條件。 於LDPC碼之解碼方法之和積運算法(Sum pr〇d⑽ Algorithm) ’重複進行可變節點運算及校驗節點運算。 圖5係表示於可變節點進行之可變節點運算。 於可變節點,對應於所欲計算之分枝之訊息讀藉由來 自相連於可變節點之剩餘分枝之訊息…及“、及利用接收 參值u〇i之式(1)之可變節點運算來求出。對應於其他分枝之 訊息亦同樣地求出。 圖6係表示於校驗節點進行之校驗節點運算。 於此,式(2)之校驗節點運算係可利用式 axb=eXp{ln(丨a|)+ln(|bl)卜sign(a)xsign(b)之關係來改寫為^ (6)。其中,Sign(x)係於時為1,於χ<〇時為、i。 " 135786.doc -10- 200937872 [數6] d〇-1Vi=U〇i+ Σ Uj j=1 • · · (5) Here, the operation of equation (5) is different from the variable node operation of the equation, using the message Uj from all the branches connected to the variable node. get on. 3 is a diagram showing an inspection matrix ( of a (3, 6) LDPC code (coding rate 1/2, code length 12) in the inspection matrix η of FIG. 3, which is the same as the figure ,, respectively, the weight of the row is 135786. Doc 200937872 is 3, with a weight of 6. Figure 4 is a Tanner diagram showing the inspection matrix of Figure 3. Here, in Fig. 4, the check node is represented by "+ ", and the variable node is represented by "=". The check node and the variable node correspond to the column and row of the check matrix 11, respectively. The knot between the node and the variable node is branch (edge: edge), which is equivalent to the element of the check matrix "1 ·, that is, when the element of the i-th row of the j-th column of the check matrix is 丨, Figure 4, by branching from the upper i-th variable node ("=" node) and from the top ❿" check node (" + ” node). The branching system indicates that the meta-bit corresponding to the variable node has a constraint condition corresponding to the check node. The variable node operation and the check node operation are repeated for the sum product operation method (Sum pr〇d(10) Algorithm) of the decoding method of the LDPC code. Figure 5 shows the variable node operation performed at the variable node. In the variable node, the message corresponding to the branch to be calculated is read by the message from the remaining branches connected to the variable node... and ", and the variable of the formula (1) using the receiving parameter u〇i The node calculation is performed in the same manner. The message corresponding to the other branches is also obtained in the same manner. Fig. 6 shows the check node operation performed by the check node. Here, the check node operation of the equation (2) is available. The relationship between axb=eXp{ln(丨a|)+ln(|bl)bsign(a)xsign(b) is rewritten as ^(6), where Sign(x) is 1 and is at χ< 〇时为,i. " 135786.doc -10- 200937872 [Number 6] d〇-1
Uj=2tanh-1 JT tanhUj=2tanh-1 JT tanh
Vi .-1 :2tanh' :2tanh_1 exp exp Σ In f dR-1Vi .-1 : 2tanh' : 2tanh_1 exp exp Σ In f dR-1
tanh ITanh I
Vi Σ - In tanhl ^xVsign(tanh(-y lvj| dc -1x Π sign(Vj) i=1 • (6) Ο 進一步而言,於x2 0,若將函數Φ(χ)定義為式 (Kx)=ln(tanh(x/2)),則式φ-丨(x):=2tanh-丨(e-X)成立,因此式 (6)可變形為式(7)。 [數7]Vi Σ - In tanhl ^xVsign(tanh(-y lvj| dc -1x Π sign(Vj) i=1 • (6) Ο Further, at x2 0, if the function Φ(χ) is defined as the formula (Kx ) = ln(tanh(x/2)), then the formula φ-丨(x):=2tanh-丨(eX) holds, so the equation (6) can be transformed into the equation (7).
Ui = 0 \ dc-1 ;Σ 0(|Vi|)l X Π sign(Vj) (7) --· v7 / 於校驗節點,式(2)之校驗節點運算係按照式(7)來進 行 〇 亦即,於校驗節點,如囷6,對應於所欲計算之分枝之 訊息Uj係藉由利用纟自相連於校驗節點之剩餘分枝之訊息 VI’V2’V3’V4,V5之式⑺之校驗節點運算來求出。對應於其他 分枝之訊息亦同樣地求出。 此外,式(7)之函數φ(χ)亦可表示為 時於Γ1則為Κχ)=φ1(χ)。將函數φ(χ)μ1(χ)實裝於硬 利用LUT(L〇〇k Up Table :杳找表)實裝声 況,但兩者均成為同一 LUT。 -找表)實裝之情 135786.doc 200937872 [非專利文獻 1] DVB-S.2 ·· ETSI ΕΝ 302 307 Vl.1.2 (2006-06) 【發明内容】 [發明所欲解決之問題] LDPC碼係於衛星數位播放之規格之DVB-S.2或下一代之 地面數位播放之規格DVB-T.2中採用。而且,LDPC碼預定 於下一代之CATV(Cable Television :有線電視)數位播放 之規格之DVB-C.2中採用。 ® 於依據DVB-S.2等DVB之規格之數位播放,LDPC碼被作 為 QPSK(Quadrature Phase Shift Keying :正交相位鍵移)等 正交調變(數位調變)之符元(符元化),該符元映射成信號 點並發送。 於LDPC碼之符元化,LDPC碼之碼位元之替換係以2位 元以上之碼位元單位進行,該替換後之碼位元被作為符元 之位元。 作為LDPC碼之符元化用之碼位元之替換方式已以各種 方式提案,但要求提案對於錯誤之耐受性提升之新方式。 本發明係有鑑於該類狀況所實現,可使對於LDPC碼等 資料之錯誤之耐受性提升。 [解決問題之技術手段] 本發明之一態樣之資料處理裝置或資料處理方法係於橫 列方向及縱行方向記憶碼長N位元之LDPC(Low Density Parity Check :低密度同位校驗)碼之碼位元之記憶機構之 前述縱行方向所寫入、於前述橫列方向所讀出之前述 135786.doc -12- 200937872 LDPC碼之碼位元之m位元被作為丨個符元,且特定正整數 "又為b,刚述s己憶機構係於前述橫列方向記憶mb位元,並 且於刖述縱行方向記憶N/(mb)位元;前述LDpc碼之碼仇 元係於前述記憶機構之前述縱行方向寫入,其後於前述橫 列方向讀出;具備替換機構或替換步驟,其係於前述記憶 機構之前述橫列方向讀出之mb位元之碼位元被作為b個前 述符元之情況下,按照用以將前述LDPC碼之碼位元分配 給表不前述符元之符元位元之分配規則,替換前述mb位元 ® 之碼位元,將替換後之碼位元作為前述符元位元》 前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定之碼長 N為16200位元、編碼率為2/32LDpc碼;前述m位元為1〇 位元,且前述整數b為2;前述碼位元之1〇位元作為丨個前 述符元而映射成1024QAM所決定之1〇24個信號點中之任一 個;前述記憶機構含有於橫列方向記憶1〇x2位元之2〇個縱 行,於縱行方向記憶16200/( 1〇χ2)位元之情況下,將於前 • 述記憶機構之橫列方向所讀出之1〇x2位元之碼位元從最高 位位元算起第i + Ι位元設為位元bi,並且將連續2個前述符 元之10x2位元之符元位元從最高位位元算起第丨+1位元設 為位元yi,可按照前述分配規則分別進行下述替換:將位 元bo分配給位元ys,將位元t>2分配給位元yQ,將位元b4分 配給位元y 1 ’將位元W分配給位元y2,將位元b8分配給位 元,將位元b1G分配給位元y4,將位元bl2分配給位元y6 , 將位元bM分配給位元ys ’將位元bl6分配給位元y9,將位元 b 1 s分配給位元y7 ’將位元b!分配給位元y丨8,將位元b3分配 135786.doc -13- 200937872 給位元y 1G,將位元bs分配給位元y】丨,將位元b7分配給位元 yi2 ’將位元b9分配給位元yn,將位元bn分配給位元y14, 將位元bn分配給位元y10 ’將位元b15分配給位元y15,將位 元1^7分配給位元yls ’將位元b19分配給位元yi7。 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為2/3之LDPC碼;前述m位 元為10位元,且前述整數b為2;前述碼位元之10位元作為 1個前述符元而映射成1024QAM所決定之1024個信號點中 之任一個;前述記憶機構含有於橫列方向記憶丨〇X2位元之 20個縱行’於縱行方向記憶64800/(10x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之1 〇x2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bi,並且將連續2個 前述符元之10x2位元之符元位元從最高位位元算起第i+1 位元設為位元yi ’可按照前述分配規則分別進行下述替 換:將位元bG分配給位元y8,將位元b>2分配給位元yQ,將 位元W分配給位元yi ’將位元b6分配給位元y2,將位元b8 分配給位元,將位元b1G分配給位元y4,將位元b〗2分配給 位元y6,將位元b〗4分配給位元y5,將位元b! 6分配給位元 y9,將位元bis分配給位元y?,將位元b!分配給位元yi8,將 位元b>3分配給位元y1Q,將位元b5分配給位元yn,將位元… 分配給位元y’將位元b>9分配給位元yi3,將位元b〗!分配 給位元,將位元b!3分配給位元,將位元b15分配給位 元yi5 ’將位元b!7分配給位元y19,將位元be分配給位元 yn 〇 135786.doc -14· 200937872 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為16200位元、編碼率為3/4之LDPC碼;前 述m位元為1〇位元’且前述整數b為2;前述碼位元之1〇位 元作為1個前述符元而映射成1024Q AM所決定之1〇24個信 號點中之任一個;前述記憶機構含有於橫列方向記憶1〇x2 位元之20個縱行,於縱行方向記憶162〇〇/(1〇x2)位元之情 況下’將於前述記憶機構之橫列方向所讀出之1〇x2位元之 碼位元從最高位位元算起第i+Ι位元設為位元bi,並且將連 續2個前述符元之10><2位元之符元位元從最高位位元算起 第i+1位元設為位元yi,可按照前述分配規則分別進行下述 替換:將位元bQ分配給位元y6,將位元b2分配給位元y4, 將位元t>4分配給位元y8 ’將位元分配給位元y5,將位元 bS分配給位元yt),將位元b1Q分配給位元y2,將位元b12分配 給位元y!,將位元bi4分配給位元y3,將位元b16分配給位元 y9 ’將位元bis分配給位元y7,將位元bi分配給位元y16,將 位元h分配給位元y14,將位元b5分配給位元y18,將位元157 分配給位元’將位元b9分配給位元y1(),將位元bn分配 給位元y! 2,將位元b i 3分配給位元y丨丨,將位元b丨5分配給位 元丫13 ’將位元bi7分配給位元y19,將位元b〗9分配給位元 yi? ° 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為3/4之LDPC碼;前述m位 元為10位元,且前述整數b為2;前述碼位元之10位元作為 1個前述符元而映射成1024QAM所決定之1024個信號點中 135786.doc -15- 200937872 之任一個;前述記憶機構含有於橫列方向記憶1 〇 x 2位元之 20個縱行,於縱行方向記憶64800/(1 0x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之10x2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bj,並且將連續2個 前述符元之1〇χ2位元之符元位元從最高位位元算起第丨+1 位元設為位元yi ’可按照前述分配規則分別進行下述替 換:將位元bG分配給位元,將位元b2分配給位元y4,將 位元W分配給位元ys,將位元b0分配給位元y5,將位元b8 © 分配給位元y〇,將位元b1()分配給位元y2,將位元b12分配給 位元y!,將位元bM分配給位元ys ’將位元bl6分配給位元 Μ,將位元bls分配給位元y7,將位元b!分配給位元yi6,將 位元t>3分配給位元y〗4 ’將位元分配給位元y〗8,將位元b7 分配給位元yls ’將位元t>9分配給位元y 1(),將位元bn分配 給位儿y!2 ’將位元b丨3分配給位元y丨丨,將位元b]5分配給位 元yi3,將位元b!7分配給位元y19,將位元bi9分配給位元 yn 〇 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為16200位元、編碼率為4/5之LDPC碼;前 述m位元為10位元,且前述整數b為2 ;前述碼位元之丨❽位 兀作為1個前述符元而映射成1024QAM所決定之1〇24個信 號點中之任個,前述記憶機構含有於橫列方向記憶丨〇x2 位兀之20個縱行,於縱行方向記憶162〇〇/ρ〇χ2)位元之情 況下,將於前述記憶機構之橫列方向所讀出之ι〇χ2位元之 碼位元從最高位位元算起第i + 1位元設為位元^,並且將連 135786.doc -16 - 200937872 續2個前述符元之1〇χ2位元之符元位元從最高位位元算起 第i+1位元設為位元yi ’可按照前述分配規則分別進行下述 替換:將位元bG分配給位元y6,將位元b2分配給位元y4, 將位元t>4分配給位元ys,將位元t>6分配給位元ys,將位元 分配給位元y〇,將位元b1G分配給位元yz,將位元bl2分配 給位元y !,將位元b!4分配給位元y 3,將位元b〗6分配給位元 ,將位元bls分配給位元y7,將位元b〗分配給位元y16,將 位元t>3分配給位元y M ’將位元b5分配給位元y u,將位元 分配給位元,將位元b9分配給位元yi。,將位元bn分配 給位元yi2,將位元bn分配給位元yu,將位元、5分配給位 元y〗3 ’將位元bn分配給位元y〗9,將位元bb分配給位元 丫17 ° 而且’前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為4/5之ldPC碼;前述!!!位 元為10位元,且前述整數b為2 ;前述碼位元之1〇位元作為 1個前述符元而映射成1024QAM所決定之丨〇24個信號點中 之任一個;前述記憶機構含有於橫列方向記憶1〇χ2位元之 20個縱行,於縱行方向記憶648〇〇/(1〇χ2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之1〇χ2位元之碼位元 從最尚位位元算起第i+1位元設為位元…,並且將連續2個 刖述符兀之10x2位元之符元位元從最高位位元算起第i+1 位7C設為位元yi,可按照前述分配規則分別進行下述替 換:將位元bG分配給位元%,將位元匕分配給位元,將 位元W分配給位元h,將位元分配給位元y5,將位元匕 135786.doc •17· 200937872 分配給位元yG,將位元b〗q分配給位元y2,將位元b! 2分配給 位元y 1,將位元b!4分配給位元y3,將位元b16分配給位元 y9 ’將位元b〗8分配給位元y7,將位元b!分配給位元y16,將 位元b>3分配給位元y〗4,將位元b5分配給位元y18,將位元匕7 分配給位元y丨5 ’將位元b9分配給位元y〗G,將位元b 1 !分配 給位元yu ’將位元bn分配給位元yn,將位元b15分配給位 元yi3,將位元b1?分配給位元y19 ’將位元b19分配給位元 yi7 0 © 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為16200位元、編碼率為5/6之LDPC瑪;前 述m位元為10位元,且前述整數b為2 ;前述碼位元之1〇位 元作為1個前述符元而映射成1024QAM所決定之1〇24個信 號點中之任一個;前述記憶機構含有於橫列方向記憶丨〇x2 位元之20個縱行’於縱行方向記憶16200/(10x2)位元之情 況下’將於前述記憶機構之橫列方向所讀出之1〇X2位元之 碼位元從最高位位元算起第i+Ι位元設為位元bi,並且將連 續2個前述符元之1〇χ2位元之符元位元從最高位位元算起 第i+1位元設為位元yi ’可按照前述分配規則分別進行下述 替換:將位元bG分配給位元y0,將位元b2分配給位元y4, 將位元b»4分配給位元ys,將位元b6分配給位元y5,將位元 be分配給位元yG,將位元b1Q分配給位元y2,將位元bl2分配 給位元yi ’將位元1^4分配給位元y3,將位元b16分配給位元 y9,將位元b!8分配給位元y7 ’將位元b!分配給位元y16,將 位元h分配給位元,將位元bs分配給位元yi8,將位元匕 135786.doc -18- 200937872 分配給位元y〗5,將位元W分配給位元yiQ,將位元bn分配 給位元ylz,將位元bu分配給位元yn,將位元bl5分配給位 元丫〗3,將位元bw分配給位元yis,將位元bi9分配給位元 yi? ° 而且’前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為5/6之ldpC碼;前述瓜位 元為10位元’且前述整數b為2;前述碼位元之1〇位元作為 1個前述符元而映射成1024QAM所決定之1024個信號點中 © 之任一個;前述記憶機構含有於橫列方向記憶ι〇χ2位元之 20個縱行’於縱行方向記憶64800/(10x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之1 〇 X2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bi,並且將連續2個 前述符元之10x2位元之符元位元從最高位位元算起第i+1 位元設為位元y i ’可按照前述分配規則分別進行下述替 換:將位元b〇分配給位元’將位元t>2分配給位元y4,將 ® 位元1>4分配給位元’將位元b6分配給位元y5,將位元 分配給位元yG,將位元b1G分配給位元,將位元b12分配給 位元y!,將位元bw分配給位元,將位元b16分配給位元 y9 ’將位元b!8分配給位元y*7,將位元b!分配給位元y16,將 位元b>3分配給位元’將位元b>5分配給位元y18,將位元b7 分配給位元yi5 ’將位元b?分配給位元y1(),將位元分配 給位元y! 2,將位元b 13分配給位元y 11 ’將位元b〗5分配給位 元y 13 ’將位元b!7分配給位元y 19,將位元b〗9分配給位元 yi7 ° 135786.doc -19- 200937872 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為16200位元、編碼率為8/92LDpc碼;前 述m位το為10位元,且前述整數1)為2 ;前述碼位元之丨〇位 元作為1個前述符元而映射成1〇24QAM所決定之1〇24個信 號點中之任一個;前述記憶機構含有於橫列方向記憶1〇χ2 位元之20個縱行,於縱行方向記憶162〇〇/(1〇><2)位元之情 況下’將於前述記憶機構之橫列方向所讀出之丨〇χ2位元之 碼位元從最高位位元算起第i + Ι位元設為位元bi,並且將連 β 續2個前述符元之10x2位元之符元位元從最高位位元算起 第i+1位元設為位元yi ’可按照前述分配規則分別進行下述 替換:將位元bG分配給位元y8,將位元b2分配給位元y0, 將位元b4分配給位元y! ’將位元b6分配給位元y2,將位元 b8分配給位元y3,將位元b1G分配給位元y4,將位元b12分配 給位元y6,將位元b14分配給位元y5,將位元b16分配給位元 y9,將位元b18分配給位元y7,將位元b!分配給位元y18,將 位元b3分配給位元y 1(),將位元b5分配給位元y n,將位元b7 ❹ 分配給位元y 12,將位元分配給位元y 13,將位元bi!分配 給位元y14,將位元bi3分配給位元yi6,將位元bi5分配給位 元y 1 5 ’將位元b 1 7分配給位元y 1 9 ’將位元b 1 9分配給位元 yu 〇 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為8/9之LDPC碼;前述m位 元為10位元,且前述整數b為2 ;前述瑪位元之10位元作為 1個前述符元而映射成1024QAM所決定之1024個信號點中 135786.doc • 20· 200937872 之任一個;前述記憶機構含有於橫列方向記憶1〇χ2位元之 20個縱行,於縱行方向記憶64800/g 〇χ2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之1〇χ2位元之碼位元 從最高位位元算起第i+l位元設為位元bi,並且將連續2個 前述符元之10x2位元之符元位元從最高位位元算起第i+i 位元設為位元yi,可按照前述分配規則分別進行下述替 換:將位元bG分配給位元ys,將位元h分配給位元,將 位元b4分配給位元y i,將位元、分配給位元乃,將位元h 〇 分配給位元乃,將位元No分配給位元w,將位元bl2分配給 位兀ye,將位元b!4分配給位元ys,將位元b16分配給位元 y9,將位元b1S分配給位元y7,將位元bl分配給位元yi8,將 位元b3分配給位元yiG,將位元bs分配給位元乃1,將位元b7 分配給位元yi2 ’將位元b分配給位元yn,將位元b"分配 給位元yu ’將位元bu分配給位元yi6,將位元b15分配給位 元yis ’將位元b1?分配給位元,將位元b19分配給位元 yi7〇 Θ 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為64800位元、編碼率為9/10之LDPC碼; 前述m位元為1〇位元’且前述整數b為2;前述碼位元之1〇 位元作為1個前述符元而映射成1〇24QAM所決定之1024個 信號點中之任—個;前述記憶機構含有於橫列方向記憶 10x2位元之20個縱行,於縱行方向記憶64800/(10x2)位元 之情況下’將於前述記憶機構之橫列方向所讀出之10χ2位 元之碼位元從最高位位元算起第i+Ι位元設為位元bi,並且 135786.doc • 21· 200937872 將連續2個前述符元之10x2位元之符元位元從最高位位元 算起第i+Ι位元設為位元yi,可按照前述分配規則分別進行 下述替換:將位元bG分配給位元y8,將位元b2分配給位元 y〇,將位元b>4分配給位元y!,將位元b6分配給位元y2,將 位元b8分配給位元y3,將位元b!〇分配給位元y4,將位元b j 2 分配給位元y0,將位元b 14分配給位元y 5,將位元b! 6分配給 位元’將位元b18分配給位元y7,將位元b!分配給位元 y 18 ’將位元b3分配給位元y〗〇,將位元b5分配給位元y n, © 將位元t>7分配給位元y 12 ’將位元b9分配給位元y〗3,將位元 bii分配給位元,將位元b13分配給位元y16,將位元b15分 配給位元y! 5 ’將位元b丨7分配給位元y丨9,將位元b! 9分配給 位元y i 7。 而且’前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為16200位元、編碼率為2/3之LDPC碼;前述m位 元為12位元,且前述整數b為2;前述碼位元之12位元作為 ©1個前述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶12X2位元之 24個縱行’於縱行方向記憶162〇〇/(12χ2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之12><2位元之碼位元 從最尚位位元算起第i+Ι位元設為位元bi,並且將連續2個 前述符元之12><2位元之符元位元從最高位位元算起第i+1 位元設為位元yi,可按照前述分配規則分別進行下述替 換:將位元bQ分配給位元y1(),將位元|^分配給位元yQ,將 位元b4分配給位元yi,將位元、分配給位元乃,將位元58 135786.doc •22- 200937872 分配給位元y3 ’將位元b1()分配給位元y4,將位元b12分配給 位元y5 ’將位元b14分配給位元y6,將位元b16分配給位元 y8 ’將位元b 18分配給位元y7,將位元b2G分配給位元y丨j, 將位元b22分配給位元y9,將位元b!分配給位元y22,將位元 b3分配給位元y 12 ’將位元b5分配給位元y13,將位元b7分配 給位元yi4,將位元b9分配給位元y15,將位元bn分配給位 元y16,將位元b13分配給位元y17,將位元b15分配給位元 y18,將位元b17分配給位元y2G,將位元b19分配給位元y19, 〇 將位元b21分配給位元y23,將位元b23分配給位元y21。 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為64800位元、編碼率為2/3之LDPC碼;前 述m位元為12位元’且前述整數b為2;前述碼位元之12位 元作為1個前述符元而映射成4096QAM所決定之4096個信 號點中之任一個;前述記憶機構含有於橫列方向記憶丨2X2 位元之24個縱行,於縱行方向記憶64800/(12x2)位元之情 況下,將於前述記憶機構之橫列方向所讀出之12x2位元之 碼位元從最高位位元算起第i+1位元設為位元bj,並且將連 續2個前述符元之12x2位元之符元位元從最高位位元算起 第i+Ι位元設為位元yi,可按照前述分配規則分別進行下述 替換:將位元bQ分配給位元y1Q,將位元匕分配給位元y〇, 將位元%分配給位元yi,將位元b6分配給位元y2,將位元 分配給位元ys ’將位元b1Q分配給位元y4,將位元bl2分配 給位元ys,將位元bw分配給位元y6,將位元bl6分配給位元 ys,將位元bls分配給位元y?,將位元b2Q分配給位元yn, 135786.doc -23· 200937872 將位元bn分配給位元’將位元b〗分配給位元y22,將位元 h分配給位元yu,將位元bs分配給位元yu,將位元卜分配 給位元y! 4 ’將位元b9分配給位元y〗5 ’將位元b!〗分配給位 元y 1 6 ’將位元b ! 3分配給位元y丨7,將位元b ! 5分配給位元 y〗s ’將位元bn分配給位元y2G,將位元bl9分配給位元yi9 , 將位元b>2丨分配給位元y23,將位元b23分配給位元y2 1。 而且’前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為16200位元、編碼率為3/4之LDPC碼;前述m位 元為12位元’且前述整數b為2;前述碼位元之12位元作為 1個前述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶丨2><2位元之 24個縱行’於縱行方向記憶162〇〇/(i2x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之12x2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bi,並且將連續2個 前述符元之12x2位元之符元位元從最高位位元算起第i+1 位元設為位元yi,可按照前述分配規則分別進行下述替 換:將位元bo分配給位元y8,將位元b2分配給位元yG,將 位元t»4分配給位元y6 ’將位元b6分配給位元yi,將位元b8 分配給位元y4,將位元b1Q分配給位元y5,將位元b12分配給 位元,將位元b14分配給位元y3,將位元b16分配給位元 y7,將位元bu分配給位元y1(),將位元b2G分配給位元yu, 將位元1>22分配給位元y 9,將位元b !分配給位元y 2Q,將位元 b3分配給位元y12 ’將位元fc>5分配給位元y18,將位元b7分配 給位元y 13 ’將位元b9分配給位元y 16,將位元b!!分配給位 135786.doc •24- 200937872 元yn ’將位元bn分配給位元yu,將位元bi5分配給位元 yi5 ’將位元bp分配給位元y!9,將位元bi9分配給位元y22, 將位元分配給位元乃3,將位元b23分配給位元乃" 進一步而言’前述LDPC瑪係DVB-S.2或DVB-T.2之規格 所規定之碼長N為64800位元、編碼率為3/4iLDpc碼;前 述m位元為12位元’且前述整數b為2;前述碼位元之12位 元作為1個前述符元而映射成4〇96QAM所決定之4096個信 號點中之任一個;前述記憶機構含有於橫列方向記憶12χ2 β 位元之24個縱行’於縱行方向記憶64800/(12x2)位元之情 況下,將於前述記憶機構之橫列方向所讀出之丨2χ2位元之 碼位元從最高位位元算起第i + Ι位元設為位元bi,並且將連 續2個前述符元之12x2位元之符元位元從最高位位元算起 第i+1位元設為位元yi,可按照前述分配規則分別進行下述 替換:將位元b〇分配給位元y8,將位元b2分配給位元y〇, 將位元t>4分配給位元y6,將位元b6分配給位元y ,,將位元 ©bS分配給位元y4 ’將位元b1G分配給位元y5,將位元b12分配 給位元y2 ’將位元b14分配給位元y3,將位元b16分配給位元 丫7,將位元b18分配給位元y1(),將位元b2G分配給位元, 將位元b22分配給位元y9,將位元b!分配給位元y2G,將位元 分配給位元y12,將位元b5分配給位元y18,將位元b7分配 給位元y 1 3,將位元b9分配給位元y! 6,將位元b !!分配給位 元y17,將位元b13分配給位元y14,將位元b15分配給位元 yi5,將位元b17分配給位元yi9,將位元bi9分配給位元y22, 將位元b21分配給位元y23,將位元b23分配給位元y21 β 135786.doc -25- 200937872 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為16200位元、編碼率為4/52LDpc碼;前述瓜位 兀*為12位元,且前述整數bg2;前述碼位元之12位元作為 1個刖述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶12χ2位元之 24個縱行,於縱行方向記憶162〇〇/(12><2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之丨2χ2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bi,並且將連續2個 G 前述符元之12x2位元之符元位元從最高位位元算起第i+1 位元設為位元yi,可按照前述分配規則分別進行下述替 換.將位元,b〇分配給位元ys ’將位元b2分配給位元,將 位元b»4分配給位元y0,將位元b6分配給位元y〗,將位元b8 分配給位元y4 ’將位元b1G分配給位元y5,將位元b12分配給 位元y2 ’將位元b〗4分配給位元y3,將位元b16分配給位元 y7,將位元b18分配給位元y1(),將位元b2Q分配給位元yn, 將位元b>22分配給位元y9 ’將位元b!分配給位元y2Q,將位元 曹 b3分配給位元y 12,將位元b5分配給位元y〗8,將位元b7分配 給位元y 13 ’將位元b9分配給位元y 16,將位元b〗1分配給位 元y17,將位元bi3分配給位元y14,將位元bi5分配給位元 y! 5,將位元b i 7分配給位元y〗9,將位元b! 9分配給位元y22, 將位元b2丨分配給位元y23,將位元b23分配給位元y21。 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為64800位元、編碼率為4/5之LDPC碼;前 述m位元為12位元,且前述整數b為2;前述碼位元之12位 135786.doc • 26- 200937872 元作為1個前述符元而映射成409 6Q AM所決定之4096個信 號點中之任一個;前述記憶機構含有於橫列方向記憶12χ2 位元之24個縱行’於縱行方向記憶648〇〇/(12χ2)位元之情 況下’將於前述記憶機構之橫列方向所讀出之丨2χ2位元之 碼位元從最高位位元算起第i + Ι位元設為位元bi,並且將連 續2個前述符元之12x2位元之符元位元從最高位位元算起 第i+ 1位元設為位元yi ’可按照前述分配規則分別進行下述 替換:將位元bQ分配給位元y8,將位元b2分配給位元y〇, 將位元b4分配給位元y0,將位元b6分配給位元yi,將位元 1>8分配給位元y4 ’將位元b1G分配給位元y5,將位元b12分配 給位元y2,將位元b】4分配給位元y3,將位元b16分配給位元 y*7 ’將位元bu分配給位元y1(),將位元b2G分配給位元yu, 將位元bu分配給位元’將位元比分配給位元y2(),將位元 b3分配給位元y,2 ’將位元bs分配給位元y18,將位元1^7分配 給位元y!3,將位元b>9分配給位元y 16,將位元b!!分配給位 元y〗7 ’將位元bn分配給位元y14,將位元b15分配給位元 yis,將位元bn分配給位元y〗9,將位元b19分配給位元y22, 將位元b2 !分配給位元y23 ’將位元b23分配給位元y2 J。 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為16200位元、編碼率為5/6之LDPC碼;前述m位 元為12位元,且前述整數b為2;前述碼位元之12位元作為 1個前述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶12x2位元之 24個縱行,於縱行方向記憶16200/( 12x2)位元之情況下, I35786.doc -27· 200937872 將於前述記憶機構之橫列方向所讀出之12x2位元之碼位元 從最高位位元算起第i + Ι位元設為位元bj,並且將連續2個 前述符元之12><2位元之符元位元從最高位位元算起第i+1 位元設為位元yi,可按照前述分配規則分別進行下述替 換:將位元bG分配給位元y8,將位元52分配給位元)^,將 位元b4分配給位元y6,將位元b6分配給位元y 1,將位元b8 分配給位元y4,將位元b1G分配給位元y5,將位元b12分配給 位元y2,將位元b14分配給位元y3,將位元b16分配給位元 O y7,將位元b 18分配給位元y 1 〇,將位元b2〇分配給位元y n, 將位元b22分配給位元y9,將位元b 1分配給位元y2G,將位元 b>3分配給位元y12,將位元b5分配給位元y18,將位元b7分配 給位元yn,將位元b9分配給位元y16,將位元bn分配給位 元yi7 ’將位元b13分配給位元y14,將位元b15分配給位元 yi5 ’將位元b17分配給位元y19,將位元b19分配給位元y22, 將位元b21分配給位元y23,將位元b23分配給位元y2 j。 進一步而言’前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規疋之碼長N為64 800位元、編碼率為5/6之LDPC碼;前 述m位元為12位元,且前述整數b為2;前述碼位元之12位 元作為1個前述符元而映射成4096Q AM所決定之4096個信 號點中之任一個;前述記憶機構含有於橫列方向記憶丨2χ2 位元之24個縱行’於縱行方向記憶64800/(12x2)位元之情 況下,將於前述記憶機構之橫列方向所讀出之12χ2位元之 碼位元從最高位位元算起第i+Ι位元設為位元匕,並且將連 續2個前述符元之12χ2位元之符元位元從最高位位元算起 135786.doc -28- 200937872 第1+1位元設為位元yi,可按照前述分配規則分別進行下述 替換:將位元bG分配給位元y8,將位元b2分配給位元y0, 將位元t>4分配給位元y6,將位元b6分配給位元y丨,將位元 t>8分配給位元’將位元b〗〇分配給位元y5,將位元b12分配 給位元y2,將位元b14分配給位元y3,將位元b16分配給位元 y*7 ’將位元b18分配給位元y1G,將位元b2G分配給位元yn, 將位元b22分配給位元y9,將位元b丨分配給位元y2Q,將位元 1>3分配給位元ylz,將位元b5分配給位元y18,將位元!^分配 給位元y! 3 ’將位元b9分配給位元y i 6,將位元b丨!分配給位 元yi? ’將位元b13分配給位元y14,將位元b15分配給位元 y〗5,將位元b17分配給位元y19,將位元b19分配給位元y22, 將位元b21分配給位元y23,將位元b23分配給位元y21。 而且,前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為16200位元、編碼率為8/9之LDPC碼;前述m位 元為12位元,且前述整數b為2;前述碼位元之12位元作為 1個前述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶12X2位元之 24個縱行’於縱行方向記憶16200/(12x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之12χ2位元之碼位元 從最高位位元算起第i+Ι位元設為位元bi,並且將連續2個 前述符元之12x2位元之符元位元從最高位位元算起第i+1 位元設為位元yi ’可按照前述分配規則分別進行下述替 換:將位元bG分配給位元y丨Q,將位元b2分配給位元,將 位元t>4分配給位元y!,將位元b6分配給位元y2,將位元b8 135786.doc -29- 200937872 分配給位元y3 ’將位元bi〇分配給位元y4,將位元b12分配給 位元y5,將位元b14分配給位元y6,將位元b16分配給位元 y8,將位元b18分配給位元y7 ’將位元b2G分配給位元yi j, 將位元bn分配給位元y9,將位元b i分配給位元y22,將位元 b3分配給位元y〗2 ’將位元b5分配給位元y〗3,將位元b7分配 給位元yi4,將位元b9分配給位元y15,將位元bn分配給位 元丫16,將位元b13分配給位元y17,將位元b15分配給位元 yis,將位元b17分配給位元y2〇,將位元b19分配給位元y19, 〇 將位元b2〗分配給位元y23,將位元b23分配給位元y2 J » 進一步而言,前述LDPC碼係DVB-S.2或DVB-T.2之規格 所規定之碼長N為64800位元、編碼率為8/9之LDPC碼;前 述m位元為12位元,且前述整數b為2;前述碼位元之12位 元作為1個前述符元而映射成4096 Q AM所決定之409 6個信 號點中之任一個;前述記憶機構含有於橫列方向記憶丨2x2 位元之24個縱行,於縱行方向記憶64800/(12x2)位元之情 況下,將於前述記憶機構之橫列方向所讀出之12 X 2位元之 碼位元從最高位位元算起第i+Ι位元設為位元bi,並且將連 續2個前述符元之12x2位元之符元位元從最高位位元算起 第1+1位元設為位元yi ’可按照前述分配規則分別進行下述 替換.將位元bG分配給位元y丨Q,將位元b2分配給位元y 〇, 將位元1>4分配給位元y 1 ’將位元b6分配給位元y 2,將位元 I?8分配給位元’將位元blG分配給位元y4,將位元bl2分配 給位元ys,將位元b14分配給位元y6,將位元b16分配給位元 ys ’將位元b ! 8分配給位元y7 ’將位元b2Q分配給位元y n, 135786.doc -30- 200937872 將位元t»22分配給位元y9,將位元b !分配給位元y22,將位元 1>3分配給位元y 1 2 ’將位元b5分配給位元y n,將位元b7分配 給位元yi4,將位元b9分配給位元y15,將位元b!丨分配給位 元yi6,將位元b13分配給位元yn,將位元b15分配給位元 yis,將位元b17分配給位元y2〇,將位元b19分配給位元y19, 將位元b2 i分配給位元y23 ’將位元b23分配給位元y2,。 而且’前述LDPC碼係DVB-S.2或DVB-T.2之規格所規定 之碼長N為64800位元、編碼率為9/10之LDPC碼;前述m位 © 元為12位元’且前述整數b為2;前述碼位元之12位元作為 1個前述符元而映射成4096QAM所決定之4096個信號點中 之任一個;前述記憶機構含有於橫列方向記憶12χ2位元之 24個縱行’於縱行方向記憶64800/(12x2)位元之情況下, 將於前述記憶機構之橫列方向所讀出之12 X 2位元之碼位元 從最尚位位元算起第i+Ι位元設為位元bj,並且將連續2個 前述符元之12x2位元之符元位元從最高位位元算起第i+i 位元設為位元yi ’可按照前述分配規則分別進行下述替 換:將位元bG分配給位元y,❶,將位元b2分配給位元yG,將 位元t>4分配給位元y】,將位元b6分配給位元y2,將位元b8 分配給位元y3 ’將位元b! 〇分配給位元y4,將位元b 12分配給 位元ys ’將位元b14分配給位元y6,將位元b16分配給位元 ys,將位元b18分配給位元y7,將位元b2G分配給位元yu, 將位元bn分配給位元y9,將位元b〗分配給位元y22,將位元 1>3分配給位元y!2,將位元b5分配給位元y i3,將位元b7分配 給位元,將位元b9分配給位元y15,將位元b! 1分配給位 135786.doc 31 200937872 元y〗6,將位元bls分配給位元yn,將位元bi5分配給位元 yi8將位元b17分配給位元y2Q,將位元h分配給位元^, 將位元bZ1分配給位元力3,將位元分配給位元力1。 於本發明之一態樣,碼長為N位元之LDpc(L〇w Density Parity Check .低密度同位校驗)碼之碼位元寫入於前述記 憶機構之前述縱行方向,其後於前述橫列方向讀出,於前 述記憶機構之前述橫列方向所讀出之爪匕位元之碼位元被作 為b個則述符元。屆時,前述mb位元之碼位元係如上述替 β 換,替換後之碼位元被作為前述符元位元。 此外,資料處理裝置為獨立之裝置、或構成丨個裝置之 内部區塊均可。 【實施方式】 [發明之效果] 若根據本發明,可使對於錯誤之耐受性提升。 圖7係表示適用本發明之傳送系統(系統係指稱複數裝置 _ 邏輯地集合之物,不問各結構之裝置是否處於同一框體 中)之一實施型態之結構例。 於圖7,傳送系統係由發送裝置丨丨及接收裝置12所構 成。 發送裝置11係進行例如電視播放節目之發送(播放)(傳 送)°亦即’發送裝置1 1係例如將作為電視播放節目之圖 像資料或聲音資料等作為發送對象之對象資料,編碼為 LDPC碼,經由例如衛星線路或地波、CATV網等通訊道i 3 而發送。 135786.doc •32- 200937872 接收裝置12為例如接收電視播放節目之調階器或電視受 像機、STB(Set Top Box :機上盒),接收從發送裝置11經 由通訊道13發送而來之LDPC碼,解碼為對象資料並輸 出。 於此,圖7之傳送系統所使用之LDPC碼據知於AWGN (Additive White Gaussian Noise :加成性白色高斯雜訊)通 訊道發揮極高之能力。 然而,於地波等之通訊道13,可能發生叢發(burst)失誤 ❹ 或抹除(erasure)。例如於 OFDM(Orthogonal Frequency Division Multiplexing :正交分頻多工)系統中,在D/U (Desired to Undesired Ratio :需要 /不需要率)為 OdB(不需 要=回聲之功率與需要=主路徑之功率相等)之多路徑環境 下,有根據回聲(echo)(主路徑以外之路徑)之延遲 (delay),特定符元之功率成為0(抹除)之情況。 而且,即使為顫振(flutter)(延遲為0且加算有花費都卜 勒(dopper)頻率之回聲之通訊道),於D/U為OdB之情況下, W 依都卜勒頻率而產生特定時刻之OFDM之符元全體之功率 成為0(抹除)之情況。 進一步而言,由於接收裝置12側從接收來自發送裝置11 之信號之天線等接收部(未圖示)至接收裝置12之布線狀 況、或接收裝置12之電源之不安定性,亦可能發生叢發失 誤。 另一方面,於LDPC碼之解碼中,於檢查矩陣Η之行,甚 而於對應於LDPC碼之碼位元之可變節點,由於如前述圖5 135786.doc -33- 200937872 所示,進行伴隨有 …… ^LDPC碼之碼位元(之接收值u〇i)之加算 之式(1)之可變節點遂 井 p點運算,因此若於該可變節點運算所用之 瑪位儿產生錯誤’則所求出之訊息之精度降低。 :、、、後於LDPC碼之解碼中於校驗節點由於利用以 相連於該校驗節點之可變節點所求出之訊息,進行式 校驗節點運算,_ 因此右相連之複數可變節點(對應之LdPc 夸瑪位元)同時成為錯誤(包含抹除)之校驗節點數變多, 則解碼之性能會劣化。 亦即例如校驗節點若相連於該校驗節點之可變節點2 個以上同時變成抹除,則對所有可變節點送回值〇之概率 與1之概率為等概率之訊息。該情況下’送回等概率之訊 息之校驗節點係無助於丨次解碼處理(1集合之可變節點運 算及校驗節點運算)’其結果,需要甚多解碼處理之重複 次數,解碼性能劣化’進一步而言,進行1^)1}(:碼之解碼 之接收裝置12之消耗電力增大。 因此,於圖7之傳送系統,欲維持在AWGN通訊道之性 能’同時提升對叢發失誤或抹除之耐受性。 圖8係表示圖7之發送裝置11之結構例。 於圖8 ’發送裝置11係由LDPC編碼部21、位元交錯器 22、映射部26及正交調變部27所構成。 對LDPC編瑪部21供給有對象資料。 LDPC編碼部21係針對供給至該處之對象資料,按照對 應於LDPC碼之同位位元之部分、即同位矩陣成為階梯構 造之檢查矩陣進行LDPC編碼’輸出將對象資料作為資訊 135786.doc -34- 200937872 位元之LDPC碼。 亦即,LDPC編碼部21係進行將對象資料編碼為例如 DVB-S.2或DVB-T.2之規格所規定之LDPC碼之LDPC編 碼,輸出其結果所獲得之LDPC碼。 於此,DVB-T.2之規格係預定採用DVB-S.2之規格所規 定之LDPC碼。DVB-S.2之規格所規定之LDPC碼為 IRA(Irregular Repeat Accumulate :非正規重複累加)碼, 該LDPC碼之檢查矩陣之同位矩陣成為階梯構造。關於同 G 位矩陣及階梯構造會於後面敘述。而且,關於IRA碼係記 載於例如"Irregular Repeat_Accumulate Codes(非正規重複 累加碼),"H. Jin,A. Khandekar, and R. J. McEliece,inUi = 0 \ dc-1 ;Σ 0(|Vi|)l X Π sign(Vj) (7) --· v7 / In the check node, the check node operation of equation (2) is according to equation (7) To perform the check, that is, at the check node, such as 囷6, the message Uj corresponding to the branch to be calculated is by using the message VI'V2'V3'V4 from the remaining branch connected to the check node. The check node operation of the formula (7) of V5 is obtained. The message corresponding to the other branches is also obtained in the same manner. Further, the function φ(χ) of the equation (7) can also be expressed as Κχ1 = φ1 (χ). The function φ(χ)μ1(χ) is mounted on the hard LUT (L〇〇k Up Table), but both become the same LUT. - Lookup table) 装装情情135786.doc 200937872 [Non-Patent Document 1] DVB-S.2 ·· ETSI ΕΝ 302 307 Vl.1.2 (2006-06) [Summary of the Invention] [Problems to be Solved by the Invention] LDPC The code is used in the DVB-S.2 specification for satellite digital broadcasting or the DVB-T.2 specification for terrestrial digital broadcasting of the next generation. Further, the LDPC code is intended to be used in the next-generation CATV (Cable Television) digital broadcasting specification DVB-C.2. ® is played in digital format according to DVB specifications such as DVB-S.2, and the LDPC code is used as a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). ), the symbol is mapped to a signal point and sent. In the symbolization of the LDPC code, the replacement of the code bits of the LDPC code is performed in units of code bits of 2 bits or more, and the replaced code bit is used as the bit of the symbol. The replacement of the code bits for the symbolization of the LDPC code has been proposed in various ways, but requires a new way of improving the tolerance of the proposal for errors. The present invention has been made in view of such a situation, and it is possible to improve the tolerance to errors in data such as LDPC codes. [Technical means for solving the problem] The data processing device or the data processing method according to an aspect of the present invention is an LDPC (Low Density Parity Check) of the N-bit length of the memory code in the course direction and the wale direction. The m-bit of the 135786.doc -12-200937872 LDPC code of the aforementioned 135786.doc -12-200937872 LDPC code written in the preceding direction of the memory unit of the code bit is used as the symbol And a specific positive integer " is also b, just s reminiscent of the system is in the above-mentioned horizontal direction memory mb bit, and in the narration direction memory N / (mb) bit; the aforementioned LDpc code of the code The element is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row; and has a replacement mechanism or a replacement step, which is a code of mb bits read in the direction of the direction of the memory mechanism. In the case where the bit is used as the b preceding symbols, the code bits of the mb bit® are replaced according to the allocation rule for assigning the code bits of the LDPC code to the symbol bits of the preceding symbols. , after replacing the code bit as the preceding symbol bit The LDPC code is DVB-S.2 or DVB-T.2, and the code length N is 16200 bits, and the coding rate is 2/32 LDpc code; the m-bit is 1 〇 bit, and the aforementioned integer b is 2; one bit of the aforementioned code bit is mapped as one of the 24 signal points determined by 1024QAM as one of the preceding symbols; the memory mechanism contains 1 〇 x 2 bits in the horizontal direction. 2 纵 纵 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The bit i-th is calculated as the bit bi, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are set from the highest bit to the first +1 bit. The element yi may be replaced by the following allocation rules: assigning the bit bo to the bit ys, assigning the bit t > 2 to the bit yQ, and assigning the bit b4 to the bit y 1 'the bit W is allocated to bit y2, bit b8 is assigned to bit, bit b1G is assigned to bit y4, bit bl2 is assigned to bit y6, bit bM is assigned to bit ys 'bit bl6 Assigned to bit y9 Assigning bit b 1 s to bit y7 'Assign bit b! to bit y丨8, assigning bit b3 to 135786.doc -13- 200937872 to bit y 1G, assigning bit bs to Bit y] 丨, assign bit b7 to bit yi2 'Assign bit b9 to bit yn, bit bn to bit y14, bit bn to bit y10 'bit b15 Assigned to bit y15, bit 1^7 is assigned to bit yls' and bit b19 is assigned to bit yi7. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64,800 bits and a coding rate of 2/3; the m-bit is 10 bits, and The integer b is 2; the 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes the 丨〇X2 bit in the horizontal direction. In the case where the 20 wales 'memorize 64800/(10x2) bits in the wale direction, the code bits of 1 〇x2 bits read in the course direction of the memory mechanism are counted from the highest bit The i+th bit is set to the bit bi, and the symbol bit of the 10x2 bit of the consecutive two preceding symbols is set from the highest bit to the i+1th bit as the bit yi ' The following replacement is performed according to the foregoing allocation rule: assigning bit bG to bit y8, assigning bit b>2 to bit yQ, assigning bit W to bit yi 'allocating bit b6 to bit Y2, the bit b8 is assigned to the bit, the bit b1G is assigned to the bit y4, the bit b is assigned to the bit y6, and the bit b is assigned to the bit y5, the bit b! 6 assigned to the bit Y9, assigning the bit bis to the bit y?, assigning the bit b! to the bit yi8, assigning the bit b>3 to the bit y1Q, and assigning the bit b5 to the bit yn, the bit... Assigned to bit y' assigns bit b > 9 to bit yi3, bit b! Assigned to the bit, the bit b!3 is assigned to the bit, the bit b15 is assigned to the bit yi5 'the bit b!7 is assigned to the bit y19, and the bit be is assigned to the bit yn 〇135786. Doc -14· 200937872 Further, the foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; The element is 1 ' bit ' and the integer b is 2; 1 〇 bit of the aforementioned code bit is mapped as one of the aforementioned symbols to any one of 24 signal points determined by 1024Q AM; the foregoing memory The mechanism contains 20 wales of 1 〇 x 2 bits in the horizontal direction, and 162 〇〇 / (1 〇 x 2) bits in the longitudinal direction. 'Reading in the direction of the memory mechanism The code bit of the 1〇x2 bit is set from the highest bit to the i+th bit to be the bit bi, and the 2 consecutive symbols are 10><2-bit symbol bit is calculated from the highest bit and the i+1th bit is set to bit yi, and the following replacement can be performed according to the foregoing allocation rule: assigning bit bQ to bit y6, Bit b2 is assigned to bit y4, bit t>4 is assigned to bit y8 'bit is assigned to bit y5, bit bS is assigned to bit yt), bit b1Q is assigned to bit Y2, the bit b12 is assigned to the bit y!, the bit bi4 is assigned to the bit y3, the bit b16 is assigned to the bit y9 'the bit bis is assigned to the bit y7, and the bit bi is assigned to the bit Element y16, assigning bit h to bit y14, bit b5 to bit y18, bit 157 to bit ' assigning bit b9 to bit y1(), assigning bit bn to Bit y! 2, assigning bit bi 3 to bit y 丨丨, assigning bit b 丨 5 to bit 丫 13 ' assigning bit bi7 to bit y19, assigning bit b 9 Bit yi? ° Moreover, the aforementioned LDPC code is MPEG-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64800 bits, and the coding rate is 3/4 LDPC code; the m-bit is 10-bit, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are taken as 1 One of the 1024 signal points determined by 1024QAM is mapped to any one of 135786.doc -15-200937872; the memory mechanism contains 20 vertical lines of 1 〇 x 2 bits in the horizontal direction. In the case of the row direction memory 64800/(1 0x2) bit, the iQ position of the 10x2 bit code bit read from the course direction of the memory mechanism is set from the highest bit bit. Bit bj, and the symbol bits of 1 〇χ 2 bits of two consecutive symbols are counted from the highest bit and the +1 +1 bit is set to bit yi ' can be respectively performed according to the foregoing allocation rule Replacement: assign bit bG to bit, assign bit b2 to bit y4, assign bit W to bit ys, assign bit b0 to bit y5, and assign bit b8 © to bit Yuan y, assigning bit b1() to bit y2, bit b12 to bit y!, assigning bit bM to bit ys ' assign bit bl6 to bit Μ, bit Bls is assigned to bit y7, bit b! is assigned to bit yi6, bit t>3 is assigned to bit y 〖4', bit is assigned to bit y-8, bit b7 is assigned to bit Yuan yls 'Assign bit #>9 to bit y 1(), bit bn to bit y!2 'Assign bit b丨3 to bit y丨丨, assign bit b]5 to The bit yi3 assigns the bit b!7 to the bit y19 and the bit bi9 to the bit yn. Further, the LDPC code is defined by the specifications of DVB-S.2 or DVB-T.2. The code length N is 16200 bits, and the coding rate is 4/5 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; the position of the above-mentioned code bit is 1 as one of the aforementioned symbols Mapped to any of the 24 signal points determined by 1024QAM, the memory mechanism contains 20 vertical lines in the horizontal direction memory 丨〇x2 position, and 162〇〇/ρ〇χ2 in the longitudinal direction. In the case of a bit, the iQ2 bit of the code bit read in the direction of the memory mechanism is set to the bit ^ from the highest bit, and will be connected 135786.doc -16 - 200937872 Continued the symbol of the 1st and 2nd bits of the two preceding symbols, the i+1th bit from the highest bit is set to the bit yi ' can be carried out according to the above allocation rules Replacement as follows: assign bit bG Bit y6, bit b2 is assigned to bit y4, bit t>4 is assigned to bit ys, bit t>6 is assigned to bit ys, bit is assigned to bit y, bit is set The element b1G is assigned to the bit yz, the bit bl2 is assigned to the bit y ! , the bit b ! 4 is assigned to the bit y 3 , the bit b 6 is assigned to the bit , and the bit bls is assigned to the bit Element y7, bit b is assigned to bit y16, bit t>3 is assigned to bit y M ', bit b5 is assigned to bit yu, bit is assigned to bit, bit b9 is assigned Give the bit yi. , the bit bn is assigned to the bit yi2, the bit bn is assigned to the bit yu, the bit, 5 is assigned to the bit y 〗 3 'the bit bn is assigned to the bit y 〗 9, the bit bb The LDPC code assigned to the bit 丫17 ° and the aforementioned LDPC code system DVB-S.2 or DVB-T.2 has a code length N of 64,800 bits and a coding rate of 4/5; The bit element is 10 bits, and the integer b is 2; 1 〇 bit of the above code bit is mapped as one of the aforementioned symbols to any one of 24 signal points determined by 1024QAM; the foregoing memory The mechanism contains 20 wales that store 1 〇χ 2 bits in the horizontal direction, and 648 〇〇 / (1 〇χ 2) bits in the longitudinal direction, which will be read in the course direction of the memory mechanism. The code bit of the 1 〇χ 2 bit is set to the bit element... from the most significant bit, and the symbol bits of the 10x2 bits of the consecutive 2 narrations are from the highest bit. From the first calculation, the i+1th bit 7C is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: assigning the bit bG to the bit %, assigning the bit 匕 to the bit, and allocating the bit W Give bit h, place bit Assigned to bit y5, assigns bit 匕 135786.doc •17· 200937872 to bit yG, bit b q to bit y2, bit b! 2 to bit y 1, bit The element b!4 is assigned to the bit y3, the bit b16 is assigned to the bit y9', the bit b8 is assigned to the bit y7, the bit b! is assigned to the bit y16, and the bit b>3 is assigned The bit y is 4, the bit b5 is assigned to the bit y18, the bit 匕7 is assigned to the bit y丨5', the bit b9 is assigned to the bit y G, and the bit b 1 ! is assigned The bit yu 'is assigned the bit bn to the bit yn, the bit b15 to the bit yi3, the bit b1? to the bit y19', and the bit b19 to the bit yi7 0 © further, The foregoing LDPC code is a LDPC code with a code length N of 16200 bits and a coding rate of 5/6 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2; 1 前述 bit of the aforementioned code bit is mapped to one of 24 signal points determined by 1024QAM as one of the aforementioned symbols; the memory mechanism is stored in the horizontal direction memory 丨〇 x2 bit 20 vertical lines of the yuan' memory in the longitudinal direction 16200/(1 In the case of 0x2) bit, the i-th bit of the code bit of the 1〇X2 bit read out in the course direction of the memory mechanism is set to the bit bi from the highest bit, and The i-th bit of the first two symbols of the preceding symbol is calculated from the highest-order bit, and the i+1th bit is set to the bit yi ', and the following replacement may be performed according to the foregoing allocation rule: The element bG is assigned to the bit y0, the bit b2 is assigned to the bit y4, the bit b»4 is assigned to the bit ys, the bit b6 is assigned to the bit y5, and the bit be is assigned to the bit yG, Assigning bit b1Q to bit y2, assigning bit bl2 to bit yi 'place bit 1^4 to bit y3, bit b16 to bit y9, assign bit b!8 Bit y7 'is assigned bit b! to bit y16, bit h is assigned to bit, bit bs is assigned to bit yi8, bit 匕135786.doc -18- 200937872 is assigned to bit y 〖5, assign bit W to bit yiQ, bit bn to bit ylz, bit bu to bit yn, bit bl5 to bit 丫3, assign bit bw Give bit yis, assign bit bi9 to bit And the above-mentioned LDPC code is DVB-S.2 or DVB-T.2, the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64,800 bits, and the coding rate is 5/6 of the lDP code; the aforementioned bite is 10 bits. And the integer b is 2; the 1st bit of the code bit is mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism is stored in the horizontal direction memory In the case where the tw〇χ2 bit 20 traverses memory 64800/(10x2) bits in the wale direction, the code bits of 1 〇X2 bits read from the course of the memory mechanism are The i+th bit is set to the bit bi from the highest bit, and the i+1th bit of the 10x2 bit of the consecutive two symbols is set from the highest bit. The bit yi ' can be replaced by the following allocation rules: assigning the bit b 给 to the bit ' assigning the bit t > 2 to the bit y4 and assigning the bit 1 > 4 to the bit ' Bit b6 is assigned to bit y5, bit is assigned to bit yG, bit b1G is assigned to bit, bit b12 is assigned to bit y!, bit bw is assigned to bit, bit is allocated B16 points The allocation bit y9' assigns the bit b!8 to the bit y*7, the bit b! to the bit y16, and the bit b>3 to the bit 'assign the bit b>5 to the bit Element y18, assigning bit b7 to bit yi5 'is assigning bit b? to bit y1(), assigning bit to bit y! 2, and assigning bit b 13 to bit y 11 ' The bit b is assigned to the bit y 13 ', the bit b! 7 is assigned to the bit y 19, and the bit b is 9 is assigned to the bit yi7 ° 135786.doc -19- 200937872 Further, the aforementioned LDPC The code length of the code system DVB-S.2 or DVB-T.2 is 16200 bits, and the coding rate is 8/92 LDpc code; the aforementioned m bit το is 10 bits, and the aforementioned integer 1) is 2 The first bit of the code bit is mapped to one of the 24 signal points determined by 1〇24QAM as one of the symbols, and the memory mechanism includes 1〇χ2 bits in the horizontal direction. 20 vertical lines, remembering 162〇〇/(1〇> in the longitudinal direction <2) In the case of a bit, the code bit of the 丨〇χ2 bit read out in the course direction of the memory mechanism is set from the highest bit to the i-th bit as the bit bi And, for example, the symbol of the 10x2 bit of the symbol of the second symbol is incremented from the highest bit and the i+1th bit is set to the bit yi ', and the following replacement may be performed according to the foregoing allocation rule: The bit bG is assigned to the bit y8, the bit b2 is assigned to the bit y0, and the bit b4 is assigned to the bit y! 'The bit b6 is assigned to the bit y2, and the bit b8 is assigned to the bit y3 The bit b1G is allocated to the bit y4, the bit b12 is assigned to the bit y6, the bit b14 is assigned to the bit y5, the bit b16 is assigned to the bit y9, and the bit b18 is assigned to the bit y7 , assigning bit b! to bit y18, assigning bit b3 to bit y 1(), assigning bit b5 to bit yn, and assigning bit b7 ❹ to bit y 12 to place the bit Assigned to bit y 13, assign bit bi! to bit y14, bit bi3 to bit yi6, bit bi5 to bit y 1 5 ' assign bit b 1 7 to bit y 1 9 'Assign bit b 1 9 to bit yu Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64,800 bits and an encoding rate of 8/9; the m-bit is 10 bits, and The integer b is 2; the 10 bits of the m-bit are mapped as one of the aforementioned symbols to any of 1024786.doc • 20· 200937872 of 1024 signal points determined by 1024QAM; the memory mechanism is included in the course The direction memory is 20 twentieth of 1 〇χ 2 bits, and in the case of memory 64800/g 〇χ 2) bits in the longitudinal direction, the code of 1 〇χ 2 bits read in the direction of the memory mechanism is read. The i+1th bit from the highest bit is set to the bit bi, and the iq bit of the 10x2 bit of the preceding two symbols is counted from the highest bit. The element is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit ys, the bit h is allocated to the bit, and the bit b4 is assigned to the bit yi, and the bit is allocated Assigning to the bit element, assigning the bit h 〇 to the bit element, assigning the bit No to the bit w, assigning the bit bl2 to the bit 兀ye, and assigning the bit b!4 to the bit ys Assigning bit b16 to bit y9, bit b1S to bit y7, bit bl to bit yi8, bit b3 to bit yiG, bit bs to bit 1. Assign bit b7 to bit yi2 'Assign bit b to bit yn, assign bit b" to bit yu' to assign bit bu to bit yi6 and bit b15 to bit Yuan yis 'Assign bit b1? to bit, and bit b19 to bit yi7〇Θ Further, the aforementioned LDPC code is the code length specified by the specification of DVB-S.2 or DVB-T.2 N is 64800 bits, and the coding rate is 9/10 LDPC code; the m-bit is 1 〇 bit ' and the aforementioned integer b is 2; 1 前述 bit of the above-mentioned code bit is mapped as one of the aforementioned symbols Any one of the 1024 signal points determined by 1〇24QAM; the memory mechanism contains 20 vertical lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction. 'The code bits of the 10 χ 2 bits read out from the direction of the memory mechanism are set to the bit bi from the highest bit, and 135786.doc • 21· 200937872 will be connected The symbol of the 10x2 bit of the two symbols is set from the highest bit and the i+th bit is set to the bit yi. The following replacement can be performed according to the foregoing allocation rule: assigning the bit bG to Bit y8, assigning bit b2 to bit y, assigning bit b>4 to bit y!, assigning bit b6 to bit y2, and assigning bit b8 to bit y3, bit The element b! is assigned to the bit y4, the bit bj 2 is assigned to the bit y0, the bit b 14 is assigned to the bit y 5 , and the bit b ! 6 is assigned to the bit ' assigning the bit b18 to Bit y7, assigning bit b! to bit y 18 ' assigns bit b3 to bit y 〇, assigns bit b5 to bit yn, © assigns bit t > 7 to bit y 12 'Assign bit b9 to bit y〗 3, assign bit bii to bit, assign bit b13 to bit y16, and bit b15 to bit y! 5 'put bit b丨7 is assigned to bit y丨9, and bit b! 9 is assigned to bit yi7. Moreover, the aforementioned LDPC code is a LDPC code having a code length N of 16200 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the preceding symbols; the memory mechanism includes 12X2 bits in the horizontal direction. In the case where 24 wales 'memorize 162 〇〇/(12 χ 2) bits in the wale direction, 12 will be read in the course direction of the memory mechanism described above><2-bit code bit The i+th bit is set to bit bi from the most significant bit, and 12 of the preceding symbols will be consecutive><2 bit symbolic element The i+1th bit is set to bit yi from the highest bit, and the following replacement can be performed according to the foregoing allocation rule: assigning bit bQ to bit y1 ( ), assigning the bit || to the bit yQ, assigning the bit b4 to the bit yi, assigning the bit to the bit, and assigning the bit 58 135786.doc •22-200937872 to the bit y3 ' Bits b1() are assigned to bit y4, bit b12 is assigned to bit y5', bit b14 is assigned to bit y6, bit b16 is assigned to bit y8', bit b 18 is assigned to bit Element y7, assigning bit b2G to bit y丨j, assigning bit b22 to bit y9, assigning bit b! to bit y22, and assigning bit b3 to bit y 12 'put bit B5 is assigned to bit y13, bit b7 is assigned to bit yi4, bit b9 is assigned to bit y15, bit bn is assigned to bit y16, bit b13 is assigned to bit y17, bit is allocated B15 is assigned to bit y18, bit b17 is assigned to bit y2G, bit b19 is assigned to bit y19, bit b21 is assigned to bit y23, and bit b23 is assigned to bit y21. Further, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64800 bits and a coding rate of 2/3; the m-bit is 12 bits. And the integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism is stored in the horizontal direction memory 丨 2X2 bit In the case of 24 vertical lines of the element, in the case of memory 64800/(12x2) bits in the longitudinal direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the highest bit. The i+1th bit is set to the bit bj, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the highest bit to the i+1th bit as the bit yi, which can be The foregoing allocation rules respectively perform the following substitutions: assigning the bit bQ to the bit y1Q, assigning the bit 匕 to the bit y〇, assigning the bit % to the bit yi, and assigning the bit b6 to the bit y2, Assigning a bit to bit ys ' allocates bit b1Q to bit y4, bit bl2 to bit ys, bit bw to bit y6, and bit bl6 to bit Ys, assigning the bit bls to the bit y?, assigning the bit b2Q to the bit yn, 135786.doc -23· 200937872 assigning the bit bn to the bit 'allocating the bit b to the bit y22, The bit h is assigned to the bit yu, the bit bs is assigned to the bit yu, the bit b is assigned to the bit y! 4 'the bit b9 is assigned to the bit y〗 5 'Bit b! Assigned to bit y 1 6 'distribute bit b ! 3 to bit y 丨 7 , assign bit b ! 5 to bit y s ' to assign bit bn to bit y2G, bit bl9 Assigned to bit yi9, bit b>2丨 is assigned to bit y23, and bit b23 is assigned to bit y2 1. Moreover, 'the foregoing LDPC code is DVB-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 16200 bits, and the coding rate is 3/4 LDPC code; the m-bit is 12 bits' and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism is stored in the course direction 丨2><24 twentieth of 2 bits' memory 162 〇〇/(i2x2) bits in the wale direction, the 12x2 bit code bits read from the course direction of the memory mechanism are The i+th bit is set to the bit bi from the highest bit, and the i+1th bit of the 12x2 bit of the preceding two symbols is set from the highest bit. The bit yi may be replaced by the following allocation rules: assigning the bit bo to the bit y8, assigning the bit b2 to the bit yG, and assigning the bit t»4 to the bit y6 'the bit B6 is assigned to bit yi, bit b8 is assigned to bit y4, bit b1Q is assigned to bit y5, bit b12 is assigned to bit, bit b14 is assigned to bit y3, bit b16 is assigned Assigned to bit y7, bit unit bu is assigned to bit y1(), bit b2G is assigned to bit yu, bit 1>22 is assigned to bit y 9, bit b! is assigned to bit y 2Q, assigning bit b3 to bit y12 'Assign bit fc>5 to bit y18, bit b7 to bit y 13 'Assign bit b9 to bit y 16, bit bit b!! Assigned to 135786.doc •24- 20093787 2 element yn ' assigns bit bn to bit yu, bit bi5 to bit yi5 ' assigns bit bp to bit y!9, bit bi9 to bit y22, assigns bit The bit number is 3, and the bit b23 is assigned to the bit. "Furthermore, the code length N specified by the specifications of the aforementioned LDPC DVB-S.2 or DVB-T.2 is 64,800 bits, and the code is The rate is 3/4 iLDpc code; the m-bit is 12-bit ' and the aforementioned integer b is 2; 12 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 4096 signal points determined by 4〇96QAM Any one of the above; the memory mechanism contains 24 wales of memory 12 χ 2 β bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction, which will be in the direction of the memory mechanism The code bit of the read 2 χ 2 bit is set from the highest bit to the i + Ι bit as the bit bi, and the symbol bits of the 12x2 bits of the 2 consecutive symbols are from the highest bit. The i+1th bit from the bit count is set to the bit yi, and the following replacement may be performed according to the foregoing allocation rule: the bit b〇 is allocated to the bit y8, and the bit b2 is assigned to the bit y〇. The bit t>4 is assigned to the bit y6, the bit b6 is assigned to the bit y, the bit ©bS is assigned to the bit y4', the bit b1G is assigned to the bit y5, and the bit b12 is assigned Bit y2' assigns bit b14 to bit y3, bit b16 to bit 丫7, bit b18 to bit y1(), bit b2G to bit, bit b22 Assigned to bit y9, bit b! is assigned to bit y2G, bit is assigned to bit y12, bit b5 is assigned to bit y18, bit b7 is assigned to bit y 1 3, bit is set Element b9 is assigned to bit y! 6, assigning bit b!! to bit y17, bit b13 to bit y14, bit b15 to bit yi5, bit b17 to bit Yi9, the bit bi9 is assigned to the bit y22, the bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y21 β 135786.doc -25- 200937872 Moreover, the aforementioned LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 16200 bits, and the coding rate is 4/52 LDpc code; the aforementioned melon position 兀* is 12 bits, and the aforementioned integer bg2; 12 bits of the aforementioned code bit element Determined as a symmetry symbol and mapped to 4096QAM 4096 signal points according to any one of; the memory means comprising memory 12χ2 bits in the course direction of the wales 24, in the longitudinal direction of the memory 162〇〇 / (12 ><2) In the case of a bit element, the code bit of the 丨2χ2 bit read out in the course direction of the memory mechanism is set to the bit bi from the highest bit bit, And the second i-th symbol of the 12x2 bit of the preceding symbol is calculated from the highest-order bit, and the i+1th bit is set as the bit yi, and the following replacement may be performed according to the foregoing allocation rule. Yuan, b〇 is assigned to bit ys 'Band bit b2 is assigned to bit, bit b»4 is assigned to bit y0, bit b6 is assigned to bit y, bit b8 is assigned to bit Y4 'Assign bit b1G to bit y5, bit b12 to bit y2' assign bit b 4 to bit y3, bit b16 to bit y7, assign bit b18 to The bit y1() assigns the bit b2Q to the bit yn, assigns the bit b>22 to the bit y9', assigns the bit b! to the bit y2Q, and assigns the bit b3 to the bit y 12 , assigning bit b5 to bit y 〗 8, assigning bit b7 to bit y 13 ' assigning bit b9 to bit y 16, assigning bit b 1 to bit y17, bit Bi3 is assigned to bit y14, and bit bi5 is assigned to bit y! 5. The bit b i 7 is assigned to the bit y 〗 9, the bit b! 9 is assigned to the bit y22, the bit b2 丨 is assigned to the bit y23, and the bit b23 is assigned to the bit y21. Further, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64800 bits and a coding rate of 4/5; the m-bit is 12 bits. And the aforementioned integer b is 2; 12 bits of the aforementioned code bit 135786.doc • 26-200937872 are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 409 6Q AM; the foregoing memory mechanism 24 wales containing 12 χ 2 bits in the horizontal direction memory 648 〇〇 / (12 χ 2) bits in the wale direction 丨 2 χ 2 bits read in the course direction of the memory mechanism The code bit is set to the bit bi from the highest bit, and the symbol bits of the 12x2 bits of the two consecutive symbols are counted from the highest bit. The bit is set to the bit yi ', and the following replacement can be performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, the bit b2 is assigned to the bit y, and the bit b4 is assigned to the bit y0. The bit b6 is assigned to the bit yi, the bit 1 > 8 is assigned to the bit y4 'the bit b1G is assigned to the bit y5, and the bit b12 is assigned to the bit y2, the bit b] 4 is assigned to bit y3, bit b16 is assigned to bit y*7 'bit element bu is assigned to bit y1(), bit b2G is assigned to bit yu, bit b is assigned to bit ' Assigning the bit ratio to bit y2(), assigning bit b3 to bit y, 2' assigning bit bs to bit y18, and assigning bit 1^7 to bit y!3, bit b>9 is assigned to bit y 16, and bit b!! is assigned to bit y 〖7', bit bn is assigned to bit y14, bit b15 is assigned to bit yis, bit bn is assigned to The bit y is 9, the bit b19 is assigned to the bit y22, the bit b2 ! is assigned to the bit y23 'the bit b23 is assigned to the bit y2 J. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16200 bits and a coding rate of 5/6; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 bits of memory 12x2 bits in the horizontal direction. In the case of a vertical line, in the case of a memory of 16200/(12x2) bits in the wale direction, I35786.doc -27· 200937872 will read the 12x2 bit code bit from the highest position in the direction of the memory mechanism. The bit i + Ι bit is set to bit bj, and 12 consecutive symbols of the preceding symbol will be 12><2 bit symbolic element The i+1th bit is set as the bit yi from the highest bit, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, The bit 52 is assigned to the bit), the bit b4 is assigned to the bit y6, the bit b6 is assigned to the bit y 1, the bit b8 is assigned to the bit y4, and the bit b1G is assigned to the bit Y5, the bit b12 is allocated to the bit y2, the bit b14 is assigned to the bit y3, the bit b16 is assigned to the bit O y7, and the bit b 18 is assigned to the bit y 1 〇, the bit b2 〇 is allocated to bit yn, bit b22 is assigned to bit y9, bit b 1 is assigned to bit y2G, bit b>3 is assigned to bit y12, and bit b5 is assigned to bit y18, Bit b7 is assigned to bit yn, bit b9 is assigned to bit y16, bit bn is assigned to bit yi7', bit b13 is assigned to bit y14, bit b15 is assigned to bit yi5' The bit b17 is assigned to the bit y19, the bit b19 is assigned to the bit y22, the bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y2j. Further, 'the aforementioned LDPC code is DVB-S.2 or DVB-T.2, and the code length N is 64 800 bits, and the coding rate is 5/6 LDPC code; the aforementioned m bit is 12 a bit, and the integer b is 2; 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096Q AM as one of the symbols; the memory mechanism is stored in the horizontal direction memory In the case where the 24 wales of 丨2χ2 bits are memory 64800/(12x2) bits in the wale direction, the 12-bit 2-bit code bits read from the course of the memory mechanism are from the highest bit. From the first calculation, the i+Ι bit is set to the bit 匕, and the symbol bits of the 12 χ 2 bits of the preceding two symbols are counted from the highest bit. 135786.doc -28- 200937872 1+1 The bit is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, the bit b2 is assigned to the bit y0, and the bit t > 4 is assigned to the bit y6 Assigning bit b6 to bit y, assigning bit t > 8 to bit 'allocating bit b 〇 to bit y5, assigning bit b12 to bit y2, allocating bit b14 To the bit y3, the bit b16 is assigned to the bit y*7', the bit b18 is assigned to the bit y1G, the bit b2G is assigned to the bit yn, and the bit b22 is assigned to the bit y9, the bit is allocated b丨 is assigned to bit y2Q, bit 1>3 is assigned to bit ylz, bit b5 is assigned to bit y18, bit !^ is assigned to bit y! 3 'bit b9 is assigned to bit Yuan yi 6, will be bit b! Assigned to bit yi? 'Assign bit b13 to bit y14, bit b15 to bit y〗 5, bit b17 to bit y19, bit b19 to bit y22, Bit b21 is assigned to bit y23, and bit b23 is assigned to bit y21. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16200 bits and an encoding rate of 8/9; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 bits of memory 12X2 bits in the horizontal direction. In the case where the traverse 'memorizes 16200/(12x2) bits in the wale direction, the 12-bit 2-bit code bits read in the course direction of the memory mechanism are counted from the highest bit i+ The Ι bit is set to the bit bi, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the highest bit to the i+1th bit as the bit yi 'can be according to the foregoing allocation rule The following replacement is performed: assigning bit bG to bit y丨Q, assigning bit b2 to bit, assigning bit t>4 to bit y!, and assigning bit b6 to bit y2, Assigning bit b8 135786.doc -29- 200937872 to bit y3 'Assign bit bi〇 to bit y4, bit b12 to bit y5, bit b14 to bit y6, will The element b16 is assigned to the bit y8, the bit b18 is assigned to the bit y7 'the bit b2G is assigned to the bit yi j , the bit bn is assigned to the bit y9 , and the bit bi is assigned to the bit y22 , Bit b3 is assigned to bit y 〗 2 'Band bit b5 is assigned to bit y 〗 3, bit b7 is assigned to bit yi4, bit b9 is assigned to bit y15, bit bn is assigned to bit Yuan 丫 16, assigning bit b13 to bit y17, bit b15 to bit yis, bit b17 to bit y2 〇, bit b19 to bit y19, 位 bit b2 Assigned to bit y23, bit b23 is assigned to bit y2 J » Further, the code length N specified by the specification of LDPC code system DVB-S.2 or DVB-T.2 is 64800 bits, An LDPC code having a coding rate of 8/9; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096 Q AM as one of the aforementioned symbols. Any of the six signal points; the memory mechanism contains 24 wales of 2x2 bits in the horizontal direction memory, and 64800/(12x2) bits in the longitudinal direction, which will be in the memory mechanism Horizontal side The read 12 bits of 12 X 2 bits are set from the most significant bit to the i-th bit, and the symbol bits of the 12x2 bits of the preceding two consecutive symbols are The 1+1th bit from the highest bit is set to the bit yi ', and the following replacement can be performed according to the foregoing allocation rule. The bit bG is assigned to the bit y丨Q, and the bit b2 is assigned to the bit y. 〇, assigning bit 1 > 4 to bit y 1 'allocating bit b6 to bit y 2 , assigning bit I 8 to bit ' assigning bit blG to bit y4, bit Bl2 is assigned to bit ys, bit b14 is assigned to bit y6, bit b16 is assigned to bit ys 'bit bit b! 8 is assigned to bit y7' and bit b2Q is assigned to bit yn, 135786 .doc -30- 200937872 assigns bit t»22 to bit y9, bit b! to bit y22, bit 1>3 to bit y 1 2 ' assign bit b5 to bit Yuan yn, assigning bit b7 to bit yi4, bit b9 to bit y15, bit b!丨 to bit yi6, bit b13 to bit yn, bit b15 Give bit yis, assign bit b17 to bit y2〇, Assigned to the bits b19 membered y19, the bit b2 i assigned to the bit y23 'y2 bits allocated to bit b23 ,. Moreover, 'the aforementioned LDPC code is DVB-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64,800 bits, and the coding rate is 9/10. The m-bit element is 12 bits. And the integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 12χ2 bits in the horizontal direction. In the case of 24 wales 'memory 64800/(12x2) bits in the wale direction, the 12 X 2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bits. The i+th bit is set to the bit bj, and the symbol of the 12x2 bit of the consecutive two symbols is set from the highest bit to the i+i bit as the bit yi ' According to the foregoing allocation rule, the following replacement is respectively performed: assigning the bit bG to the bit y, ❶, assigning the bit b2 to the bit yG, assigning the bit t > 4 to the bit y], and allocating the bit b6 To the bit y2, the bit b8 is assigned to the bit y3 'the bit b! 〇 is assigned to the bit y4, the bit b 12 is assigned to the bit ys 'the bit b14 is assigned to the bit y6, the bit is bit Yuan b16 allocation To bit ys, bit b18 is assigned to bit y7, bit b2G is assigned to bit yu, bit bn is assigned to bit y9, bit b is assigned to bit y22, bit 1> 3 is assigned to bit y!2, bit b5 is assigned to bit y i3, bit b7 is assigned to bit, bit b9 is assigned to bit y15, bit b! 1 is assigned to bit 135786 .doc 31 200937872 yuan y〗 6, assigning the bit bls to the bit yn, assigning the bit bi5 to the bit yi8, assigning the bit b17 to the bit y2Q, and assigning the bit h to the bit ^, will be bit The element bZ1 is assigned to the bit force 3, and the bit is assigned to the bit force 1. In one aspect of the present invention, a code bit of an LDpc (L〇w Density Parity Check) code having a code length of N bits is written in the foregoing longitudinal direction of the memory mechanism, and thereafter Read in the horizontal direction, the code bits of the X-ray bits read in the direction of the memory of the memory mechanism are referred to as b symbols. At that time, the code bits of the aforementioned mb bits are replaced by the above-mentioned β, and the replaced code bits are used as the aforementioned symbol bits. Further, the data processing device may be an independent device or an internal block constituting one device. [Embodiment] [Effects of the Invention] According to the present invention, tolerance to errors can be improved. Fig. 7 is a view showing an example of a configuration of an embodiment in which the transmission system to which the present invention is applied (the system refers to a plurality of devices _ logically aggregated, regardless of whether or not the devices of the respective structures are in the same casing). In Fig. 7, the transmission system is constituted by a transmitting device 接收 and a receiving device 12. The transmitting device 11 performs, for example, transmission (playback) (transmission) of a television broadcast program. That is, the transmitting device 11 is, for example, an image data to be transmitted as an image data or a voice material of a television broadcast program, and is encoded as LDPC. The code is transmitted via a communication channel i 3 such as a satellite line or a ground wave, a CATV network, or the like. 135786.doc • 32- 200937872 The receiving device 12 is, for example, a pacer or a television receiver that receives a television broadcast program, an STB (Set Top Box), and receives an LDPC transmitted from the transmitting device 11 via the communication channel 13. The code is decoded into the object data and output. Here, the LDPC code used in the transmission system of Fig. 7 is known to have an extremely high capability in the AWGN (Additive White Gaussian Noise) communication channel. However, in the communication channel 13 of the ground wave or the like, a burst error ❹ or erasure may occur. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, D/U (Desired to Undesired Ratio) is OdB (not required = echo power and required = main path) In a multipath environment with equal power, there is a delay based on the echo (path outside the main path), and the power of the specific symbol becomes 0 (erase). Moreover, even if it is a flutter (a delay is 0 and a channel with an echo of the Dopper frequency is added), in the case where D/U is OdB, W is specific to the frequency of the Doppler. The power of the entire OFDM symbol at the time is 0 (erased). Further, since the receiving device 12 side receives the wiring condition of the receiving unit (not shown) such as an antenna from the transmitting device 11 to the receiving device 12 or the power supply of the receiving device 12, the cluster may also occur. Make a mistake. On the other hand, in the decoding of the LDPC code, the row of the check matrix ,, even the variable node corresponding to the code bit of the LDPC code, is performed as shown in the above-mentioned FIG. 5 135786.doc -33- 200937872 There is a variable node of the formula (1) of the LDPC code (the received value u〇i) is added to the p-point operation, so if the position of the variable node is used, the error occurs. 'The accuracy of the information obtained is reduced. After the decoding of the LDPC code, the check node performs the check node operation by using the message obtained by the variable node connected to the check node, so the right-connected complex variable node (The corresponding LdPc quark bit) The number of check nodes that become an error (including erasure) increases, and the performance of decoding deteriorates. That is, for example, if the check node is connected to the variable node of the check node and two or more of the variable nodes become erased, the probability that the probability of returning the value 所有 to all the variable nodes and the probability of 1 is equal probability. In this case, the check node of the message that sends back the equal probability does not contribute to the decoding process (the variable node operation and the check node operation of the 1 set). As a result, the number of repetitions of the decoding process is required, and the decoding is performed. Performance degradation 'further, 1^)1} (: the power consumption of the receiving device 12 of the decoding of the code is increased. Therefore, in the transmission system of FIG. 7, the performance of the AWGN communication channel is to be maintained] Fig. 8 is a diagram showing an example of the configuration of the transmitting apparatus 11 of Fig. 7. Fig. 8 'The transmitting apparatus 11 is composed of an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and orthogonal The LDPC encoding unit 21 supplies the target data to the LDPC coder 21. The LDPC encoding unit 21 forms a step structure for the target data supplied to the LDPC code, that is, the parity matrix corresponding to the LDPC code. The check matrix performs LDPC encoding 'outputs the object data as the LDPC code of the information 135786.doc -34- 200937872 bit. That is, the LDPC encoding section 21 performs encoding of the object data into, for example, DVB-S.2 or DVB-T. LDPC as specified in .2 specifications The LDPC code of the code outputs the LDPC code obtained by the result. Here, the specification of DVB-T.2 is intended to adopt the LDPC code specified by the specification of DVB-S.2. The specification of DVB-S.2 is specified. The LDPC code is an IRA (Irregular Repeat Accumulate) code, and the parity matrix of the check matrix of the LDPC code is a ladder structure. The same G-bit matrix and the ladder structure will be described later. For example, "Irregular Repeat_Accumulate Codes, "H. Jin, A. Khandekar, and RJ McEliece, in
Proceedings of 2nd International Symposium on Turbo codes and Related Topics,pp. 1-8,Sept. 2000 〇 LDPC編碼部21所輸出之LDPC碼係供給至位元交錯器 22 〇 位元交錯器22係將資料予以交錯之資料處理裝置,其由 〇 同位交錯器(parity interleaver)23、縱行扭轉交錯器 (column twist interleaver)24 及解多工器(DEMUX)25 所構 成。 同位交錯器23係進行同位交錯,將來自LDPC編碼部21 之LDPC碼之同位位元,交錯至其他同位位元之位置,並 將該同位交錯後之LDPC碼供給至縱行扭轉交錯器24。 縱行扭轉交錯器24係針對來自同位交錯器23之LDPC碼 進行縱行扭轉交錯,將該縱行扭轉交錯後之LDPC碼供給 135786.doc -35- 200937872 至解多工器25。 亦即,LDPC碼係於後述之映射部26,將該LDPC碼之2 位元以上之碼位元映射成表示正交調變之1個符元之信號 點並發送。 於縱行扭轉交錯器24 ’為了使對應於位在ldpC編碼部 21所用之檢查矩陣之任意1列之1之ldpc碼之複數碼位 元,不含於1個符元’作為重排來自同位交錯器23之LDPC 碼之碼位元之重排處理而進行例如後述之縱行扭轉交錯。 © 解多工器25係針對來自縱行扭轉交錯器24之LDPC碼, 進行替換成符元之LDPC碼之2以上之碼位元之位置之替換 處理,藉此獲得已強化對於AWGN之财受性之LDPC碼。 然後,解多工器25係將藉由替換處理所獲得之ldpc碼之2 以上之碼位元,作為符元供給至映射部26。 映射部26係將來自解多工器25之符元,映射成以正交調 變部27所進行之正交調變(多值調變)之調變方式所決定之 各信號點。 亦即,映射部26係將來自解多工器25之LDPC碼予以映 射成’由表示與載波同相之I成分之I轴及表示與載波呈正 交之Q成分之Q軸所規定之IQ平面(IQ星座)上以調變方式決 定之信號點。 於此,作為正交調變部27所進行之正交調變之調變方 式,有例如包含規定於DVB-T之規格之調變方式之調變方 式,亦即例如QPSK(Quadrature Phase Shift Keying:正交 相位鍵移)或 16QAM(Quadrature Amplitude Modulation :正 135786.doc • 36- 200937872 交振幅調變)、64QAM、256QAM、1024QAM、4096QAM 等。於正交調變部27,按照例如發送裝置1 1之操作者之操 作,預先設定藉由某一調變方式進行正交調變。此外,於 正交調變部27,可進行其他例如4PAM(Pulse Amplitude Modulation :脈衝振幅調變)和其他正交調變。 於映射部26映射成信號點之符元係供給至正交調變部 27 ° 正交調變部27係按照來自映射部26之信號點(映射成該 © 信號點之符元),進行載波之正交調變,將其結果所獲得 之調變信號經由通訊道13(圖7)發送。 接著,圖9係表示於圖8之LDPC編碼部21用於LDPC編碼 之檢查矩陣Η。 檢查矩陣 Η為 LDGM(Low-Density Generation Matrix : 低密度生成矩陣)構造,可藉由LDPC碼之碼位元中對應於 資訊位元之部分之資訊矩陣Ha、及對應於同位位元之同位 矩陣Ητ,來表示為式H=[HA|HT](資訊矩陣HA之要素設為左 ® 側要素,同位矩陣Ητ之要素設為右側要素之矩陣)。 於此,1個LDPC碼(1碼字)之碼位元中之資訊位元之位元 數及同位位元之位元數,分別稱為資訊長K及同位長Μ, 並且1個LDPC碼之碼位元之位元數稱為碼長Ν(=Κ+Μ)。 關於某碼長Ν之LDPC碼之資訊長Κ及同位長Μ係由編碼 率決定。而且,檢查矩陣Η係列X行為ΜχΝ之矩陣。然 後,資訊矩陣HA為ΜχΚ之矩陣,同位矩陣Ητ為ΜχΜ之矩 陣。 135786.doc •31· 200937872Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000 The LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver 22. The bit interleaver 22 interleaves the data. The data processing device is composed of a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25. The parity interleaver 23 performs co-located interleaving, interleaving the parity bits of the LDPC code from the LDPC encoding section 21 to the positions of other parity bits, and supplies the parity interleaved LDPC code to the vertical twist interleaver 24. The whirling twist interleaver 24 performs wobble interleaving for the LDPC code from the co-located interleaver 23, and supplies the LDPC code which is twisted and interleaved to the multiplexer 25 from 135786.doc -35 - 200937872. In other words, the LDPC code is mapped to the mapping unit 26, which will be described later, and the code bits of two or more bits of the LDPC code are mapped to signal points representing one symbol of the quadrature modulation and transmitted. The vertical twist interleaver 24' is not included in one symbol 'as a rearrangement from the same position in order to make the complex digital bit of the ldpc code corresponding to one of the ones of the check matrix used by the ldpC encoding unit 21 The rearrangement processing of the code bits of the LDPC code of the interleaver 23 is performed, for example, by the wobble interleave described later. © The multiplexer 25 is a replacement process for replacing the position of the code bit of 2 or more LDPC codes of the symbol with respect to the LDPC code from the vertical twist interleaver 24, thereby obtaining the enhanced financial benefit for AWGN. Sexual LDPC code. Then, the demultiplexer 25 supplies the code bits of 2 or more of the ldpc code obtained by the replacement processing to the mapping unit 26 as symbols. The mapping unit 26 maps the symbols from the demultiplexer 25 to the respective signal points determined by the modulation method of the quadrature modulation (multi-value modulation) by the orthogonal modulation unit 27. That is, the mapping unit 26 maps the LDPC code from the demultiplexer 25 into an IQ plane defined by the I axis representing the I component in phase with the carrier and the Q axis representing the Q component orthogonal to the carrier. The signal point determined by modulation in the (IQ constellation). Here, as a modulation method of the quadrature modulation performed by the quadrature modulation unit 27, for example, a modulation method including a modulation method defined by the specification of DVB-T, that is, QPSK (Quadrature Phase Shift Keying), for example, QPSK (Quadrature Phase Shift Keying) : Quadrature phase key shift) or 16QAM (Quadrature Amplitude Modulation: positive 135786.doc • 36-200937872 cross-amplitude modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc. The quadrature modulation unit 27 preliminarily sets the orthogonal modulation by a certain modulation method in accordance with, for example, the operation of the operator of the transmission device 11. Further, in the quadrature modulation unit 27, for example, 4PAM (Pulse Amplitude Modulation) and other orthogonal modulation can be performed. The symbol mapped to the signal point by the mapping unit 26 is supplied to the orthogonal modulation unit 27°. The orthogonal modulation unit 27 performs carrier wave in accordance with the signal point (the symbol mapped to the © signal point) from the mapping unit 26 The quadrature modulation is performed, and the modulated signal obtained as a result is transmitted via the communication channel 13 (FIG. 7). Next, Fig. 9 shows an inspection matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of Fig. 8. The check matrix Η is an LDGM (Low-Density Generation Matrix) structure, which can be obtained by the information matrix Ha corresponding to the information bit in the code bit of the LDPC code, and the parity matrix corresponding to the parity bit. Ητ is expressed as the formula H=[HA|HT] (the elements of the information matrix HA are set to the left side element, and the elements of the parity matrix Ητ are set to the matrix of the right element). Here, the number of bits of information bits and the number of bits of the parity bits in the code bits of one LDPC code (1 code word) are respectively referred to as information length K and parity length, and one LDPC code. The number of bits of the code bit is called the code length Ν (=Κ+Μ). The information length and the same length of the LDPC code of a certain code length are determined by the coding rate. Moreover, check the matrix of the matrix Η series X behavior. Then, the information matrix HA is a matrix of ΜχΚ, and the parity matrix Ητ is a matrix of ΜχΜ. 135786.doc •31· 200937872
圖10係表示DVB-S.2(及DVB-T.2)之規格所規定之LDPC 碼之檢查矩陣Η之同位矩陣Ητ。 DVB-S .2之規格所規定之LDPC碼之檢查矩陣Η之同位矩 陣Ητ係如圖10所示’成為1之要素排成所謂階梯狀之階梯 構造。同位矩陣Ητ之列權重就第1列而言為1,就剩餘全部 列而言為2。而且’行權重就最後一行而言為1,剩餘全部 行為2。 如以上’同位矩陣Ητ為階梯構造之檢查矩陣η之LDPC碼 © 可利用該檢查矩陣Η容易地生成。 亦即’以列向量c表示LDPC碼(1碼字),並且將轉置該列 向量所獲得之行向量表示作CT。而且,以列向量Α表示 LDPC碼之列向量c中之資訊位元之部分,並且以列向量τ 表示同位位元之部分。 於此’該情況下,列向量c可藉由作為資訊位元之列向Figure 10 is a diagram showing the parity matrix Ητ of the check matrix LDP of the LDPC code specified by the specifications of DVB-S.2 (and DVB-T.2). The parity matrix of the inspection matrix LDP of the LDPC code defined by the specification of DVB-S.2 is as shown in Fig. 10, and the elements which become 1 are arranged in a so-called stepped structure. The column weight of the co-located matrix Ητ is 1 for the first column and 2 for the remaining columns. Moreover, the weight of the row is 1 for the last row and 2 for all remaining behaviors. The LDPC code © which the above-mentioned parity matrix Ητ is a ladder structure check matrix η can be easily generated by using the check matrix Η. That is, the LDPC code (1 code word) is represented by the column vector c, and the row vector obtained by transposing the column vector is represented as CT. Moreover, the portion of the information bit in the column vector c of the LDPC code is represented by the column vector ,, and the portion of the parity bit is represented by the column vector τ. In this case, the column vector c can be used as a column of information bits.
量A、及作為同位位元之列向量Τ,以式c==[A|T](列向量A 之要素設為左側要素’列向量T之要素設為右側要素之列 向量)來表示。 檢查矩陣Η及作為LDPC碼之列向量C=[A|T]必須符合式 ΤΓThe quantity A and the column vector 同 as a parity bit are expressed by the equation c==[A|T] (the element of the column vector A is set to the left element ‘the column vector T is set to the right element column vector). Check matrix Η and column vector C=[A|T] as LDPC code must conform to ΤΓ
Hc—〇’作為構成符合該式HcT=0之列向量C=[A|T]之同位 位元之列向量τ可藉由於檢查矩陣H=[HA|HT]之同位矩陣ht 成為圖10所示之階梯構造之情況下,從式HcT=0之行向量 HC之第1列之要素’依序使各列之要素成為〇而可逐次地 求出。Hc_〇' as the column vector τ constituting the parity bit of the column vector C=[A|T] satisfying the formula HcT=0 can be obtained by the parity matrix ht of the check matrix H=[HA|HT] In the case of the step structure shown in the figure, the elements of the first column of the row vector HC of the equation HcT=0 are sequentially obtained by sequentially making the elements of the respective columns 〇.
圖11係表示DVB-S.2(及DVB-T.2)之規格所規定之LDPC 135786.doc -38- 200937872 碼之檢查矩陣Η及行權重。 亦即,圖11Α係表示DVB-S.2之規格所規定之LDPC碼之 檢查矩陣Η。 分別而言,關於檢查矩陣Η從第1行之ΚΧ行,行權重為 X,關於其後之Κ3行,行權重為3,關於其後之Μ-1行,行 權重為2,關於最後1行,行權重為1。 於此,ΚΧ+Κ3+Μ-1 + 1等於碼長Ν。 於DVB-S.2之規格,行數ΚΧ、Κ3及Μ(同位長)、以及行 Ο 權重X係規定如圖11Β所示。 亦即,圖11Β係表示DVB-S.2之規格所規定之LDPC碼之 各編碼率之行數ΚΧ、Κ3及Μ,以及行權重X。 於DVB-S.2之規格,規定有64800位元及16200位元之碼 長Ν之LDPC碼。 然後,如圖11Β所示,關於碼長Ν為64800位元之LDPC 碼,規定有11個編碼率(nominal rate :標稱速率)1/4、 1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6、8/9及 9/10,關 於碼長N為16200位元之LDPC碼,規定有10個編碼率1/4、 1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6及 8/9。 關於LDPC碼,據知對應於檢查矩陣Η之行權重越大之行 之碼位元,其錯誤率越低。 於圖1 1所示之DVB-S.2之規格所規定之檢查矩陣Η,越 是開頭側(左側)之行,其行權重傾向越大,因此關於對應 於該檢查矩陣Η之LDPC碼,越是開頭之碼位元,對錯誤越 強勢(對於錯誤有耐受性),越是末尾之碼位元,對錯誤傾 135786.doc -39- 200937872 向越弱勢。 接著,圖12係表示以圖8之正交調變部27進行16QAM2 情況下之16個符元(對應之信號點)之…平面上之配置。 亦即,圖12A係表示16QAM之符元。 於16QAM,1符元表示4位元,存在有16(=24)個符元。 然後,16個符元係以IQ平面之原點為中心,以j方向方 向成為4x4之正方形狀之方式配置。 現在,若將1符元所表示之位元串列從最高位位元算起 © 第1+1位元之位元表示作位元yi,則16QAM之1符元所表示 之4位兀從最高位位元依序可表示作位元八,力,乃,^。於調 變方式為16QAM之情況下,LDPC碼之碼位元之4位元被作 為(符元化為)4位元yQ至y3之符元(符元值)。 圖12B係表示分別關m16QAM之符元所表示之4位元(以 下亦稱為符元位元)yG至y3之位元界線。 於此’關於符元位元yi(於圖12為丨=〇,1,2,3)之位元界線 @ 係意味該符元位元yi成為〇之符元及成為1之符元之界線。 如圖12B所示,關於16QAM之符元所表示之4符元位元八 至ys中之最高位符元位元yQ,僅有平面之Q軸之i處成為 位元界線,關於第2個(從最高位位元算起第2個)之符元位 元yi,僅有IQ平面之丨轴之i處成為位元界線。 而且’關於第3個符元位元y2,4x4個符元中之左起第1 行與第2行間、及第3行與第4行間之2處成為位元界線。 進一步而s ’關於第4個符元位元y3,4x4個符元中之從 上算起第1列與第2列間、及第3列與第4列間之2處成為位 135786.doc 200937872 元界線。 符元所表不之符元位亓在^ 凡^係從位元界線遠離之符元越 多,越不易失誤(錯誤概率低),接近位元界線之符元越 多,越谷易失誤(錯誤概率高)。 一現在、,若將不易失誤(對錯誤強勢)之位元稱為「強勢位 兀」並且將谷易失誤(對錯誤弱勢)之位元稱為「弱勢位 元」:則關於16QAM之符元之4符元位^。至心,最高位 之疋位7〇 y 〇及第2個士从- ❹Figure 11 shows the check matrix and row weights of the LDPC 135786.doc -38- 200937872 code specified by the specifications of DVB-S.2 (and DVB-T.2). That is, Fig. 11 is a check matrix LDP of the LDPC code defined by the specifications of DVB-S.2. Separately, regarding the check matrix Η from the first row, the row weight is X, and for the next 行3 rows, the row weight is 3, and for the subsequent Μ-1 row, the row weight is 2, about the last 1 Line, the row weight is 1. Here, ΚΧ+Κ3+Μ-1 + 1 is equal to the code length Ν. For the specifications of DVB-S.2, the number of lines ΚΧ, Κ3 and Μ (colocated length), and the line weight X X are defined as shown in Figure 11Β. That is, Fig. 11 is a line number ΚΧ, Κ3 and Μ, and a row weight X of each coding rate of the LDPC code defined by the specification of DVB-S.2. In the specification of DVB-S.2, there are LDPC codes with a length of 64,800 bits and 16,200 bits. Then, as shown in FIG. 11A, regarding the LDPC code having a code length Ν of 64,800 bits, 11 coding rates (nominal rate) of 1/4, 1/3, 2/5, 1/2 are specified. 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, for an LDPC code with a code length N of 16,200 bits, 10 encoding rates of 1/4 are specified. 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9. Regarding the LDPC code, it is known that the code bit corresponding to the row having the larger row weight of the check matrix has a lower error rate. The inspection matrix 规定 specified in the specification of DVB-S.2 shown in FIG. 11 has a larger row weighting tendency as the row on the head side (left side), and therefore, regarding the LDPC code corresponding to the inspection matrix ,, The more the code bit at the beginning, the stronger the error (tolerance to the error), the more the last bit of the code bit, the more vulnerable the error is 135786.doc -39- 200937872. Next, Fig. 12 shows an arrangement on the plane of 16 symbols (corresponding signal points) in the case of 16QAM2 by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 12A shows the symbol of 16QAM. In 16QAM, 1 symbol represents 4 bits, and there are 16 (= 24) symbols. Then, the 16 symbols are arranged around the origin of the IQ plane and in a square shape of 4x4 in the direction of the j direction. Now, if the bit string represented by 1 symbol is counted from the highest bit bit © the bit of the 1+1th bit is represented as the bit yi, the 4 bit represented by the 1 symbol of 16QAM The highest bit can be expressed as bit eight, force, yes, ^. In the case where the modulation method is 16QAM, the 4-bit code bit of the LDPC code is used as the symbol (symbol value) of the 4-bit yQ to y3. Fig. 12B shows the bit boundary of the 4-bit (hereinafter also referred to as symbol bit) yG to y3 indicated by the symbol of m16QAM, respectively. Here, the bit boundary @ of the symbol element yi (in Figure 12 is 丨 = 〇, 1, 2, 3) means that the symbol yi becomes the symbol of 〇 and the boundary of the symbol of 1 . As shown in FIG. 12B, with respect to the highest-order symbol bit yQ of the four-character bit eight to ys represented by the symbol of 16QAM, only the i-axis of the Q-axis of the plane becomes the bit boundary, regarding the second The symbol element yi (the second from the highest bit) is only the bit boundary of the i-axis of the IQ plane. Further, regarding the third symbol bit y2, two of the 4x4 symbols from the left to the first row and the second row, and two of the third row and the fourth row become the bit boundary. Further, s 'About the fourth symbol element y3, 4x4 symbols, from the above, between the first column and the second column, and between the third column and the fourth column become the bit 135786.doc 200937872 Yuanjie line. The symbol of the symbol is not in the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ High probability). Now, if the bit that is not easy to make mistakes (for the wrong strength) is called "strong position" and the position of the valley error (for the wrong position) is called "weak position": then the symbol of 16QAM The 4 symbol bits ^. At the highest level, the highest position is 7〇 y 〇 and the 2nd slave is - ❹
符7L位TLyi成為強勢位元,第3個符 元位元h及第4個符元位元乃成為弱勢位元。 圖13至圖15係表示以圖8之正交調變部27進行64QAM之 情況下之64個符元(對應之信號點)之IQ平面上之配置。 於64QAM ’ 1符元表不6位元,存在有64(=26)個符元。 然後,64個符元係以IQ平面之原點為中心,以了方向^方 向成為8x8之正方形狀之方式配置。 64QAM之1符元之符元位元係從最高位位元,可依序表 不作位70 yG,yi,y2,y3,y4,y5。於調變方式為64QAM之情況 下’ LDPC碼之碼&元之6位元被作為6位%之符元位元^ 至ys之符元。 於此,圖13係表示分別關於64QAM之符元之符元位元^ 至中之最高位之符元位元y〇及第2個符元位元”之位元界 線;圖14係表示分別關於第3個符元位元及第4個符元位 兀^3之位元界線,圖15係表示分別關於第5個符元位元h及 第6個符元位元y5之位元界線。 如圖13所示,分別關於最高位之符元位元乃及第2個符 135786.doc • 41- 200937872 元位元yi之位元界線為1處。而且,如圖14所示,分別關 於第3個符元位元d及第4個符元位元之位元界線為2處; 如圖I5所示,分別關於第5個符元位元h及第6個符元位元 y5之位元界線為4處。 因此,關於64QAM之符元之符元位元”至”,最高位符 兀位7Gy〇及第2個符元位元yi成為強勢位元,第3個符元位 元h及第4個符元位元成為其次強勢之位元。然後第$ 個符元位元y4及第6個符元位元力成為弱勢位元。 從圖12,進一步從圖13至圖15可知’關於正交調變之符 元之符元位元,有高位位元成為強勢位元,低位位元成為 弱勢位元之傾向。 於此,如圖11所說明,關於LDPC編碼部21(圖8)所輸出 之LDPC碼’有對錯誤強勢之碼位元及對錯誤弱勢之碼位 元。 而且,如圖12至圖15所說明,關於正交調變部27所進行 之正交調變之符το之符元位元,有強勢位元及弱勢位元。 因此,若將LDPC碼之對錯誤弱勢之碼位元分配給正交 調變之符元之弱勢符元位元,則作為全體對於錯誤之耐受 性會降低。 因此,提案一種交錯器,其係以將LDpc碼之對錯誤弱 勢之碼位70分配給正交調變之符元之強勢位元(符元位元) 之傾向,來交錯LDPC碼之碼位元。 圖8之解多工器25係進行該交錯器之處理。 圖16係說明圖8之解多工器25之處理之圖。 135786.doc -42- 200937872 亦即’圖16A係表*解多卫㈣之功能性結構例。 解多工器25係由記憶體3丨及替換部32所構成。 斜"己憶體31 ’供給有來自LDpc編碼部2kLDpc碼。 記憶體31係含有於橫列(r〇w)(橫)方向記憶灿位元炎 且於縱行(column)(縱)方向記憶N/(mb)位元之記憶容量, 將供給至該處之LDPC碼之碼位元於縱行方向寫入,於橫 列方向讀出,並供給至替換部32。 於此,N(=資訊長K +同位長M)係如上述表*LDpc碼之 © 碼長。 而且,m係表示成為1符元之LDPC碼之碼位元之位元 數;b為特定之正整數,其係用於將爪予以整數倍之倍數。 解多工器25係如上述,將LDPC瑪之碼位元作為符元(符元 化)’倍數b係表示解多工器25藉由所謂丨次符元化所獲得 之符元個數。 圖16A係表示調變方式為64QAM之情況下之解多工器乃 之結構W ,此,成為i符元之LDpc碼之瑪位元之位元數 Θ 111為6位元。 而且,於圖16A,倍數^^為丨,因此記憶體31係具有縱行 方向X松列方向為Ν/(6χ l)x(6x 1)位元之記憶容量。 於此,將記憶體31之橫列方向為丨位元之延伸於縱行方 向之記憶區域,以下適宜地稱為縱行。於圖16八,記憶體 31係由6(=6xl)個縱行所構成。 於解多工器25, LDPC碼之碼位元在構成記憶體31之縱 行從上往下方向(縱行方向)之寫入係從左朝向右方向之縱 135786.doc *43- 200937872 行進行。 然後,右碼位7G之寫入至最右縱行之最下面終了,則從 構成記憶體31之所有縱行之第1列,往橫列方向以6位元 (mb位元)單位讀出碼仅元並供給至替換部32。 替換部32係進行替換來自記憶體3 1之6位元之碼位元之 位置之替換處理,將其結果所獲得之6位元作為表示 64QAM之1符元之6符元位元y〇,yi,y2,y3,y4,y5而輸出。 亦即,從記憶體31,於橫列方向讀出mb位元(於此為6位 0 元)之碼位^,若該從記憶體31所讀出之mb位元之碼位元 從最高位位元算起第1位元(i=〇,l,· · .,mb-l)表示作位元 h ’則從記憶體31,於橫列方向所讀出之6位元之碼位元係 從最高位位元,可依序表示作位元b〇,bi,b2,b3,b4,b5。 、圖11所說明之行權重之關係,位於位元bG之方向之碼 位凡係成為對錯誤強勢之碼位元,位於位元、之方向之碼 位元係成為對錯誤弱勢之碼位元。 ❹於替換部32 ’ 4 了使來自記憶體3 1之6位元之碼位元b。 至b5中對錯誤弱勢之碼位元,n給_舰之丄符元之符 元位元y〇至ys中之強勢位元,可進行替換來自記憶體之6 位元之碼位元bQ至之位置之替換處理。 於此,作為如何替換來自記憶體31之6位元之碼位元b〇 至b5,並分配給表示符元之6符元位元乃至”之 各個之替換方式,從各企業提案有各種方式。 刀别而s ,圖16B係表示第1替換方式,圖16C係表示第 2替換方式’圖16D係表示第3替換方式。 135786.doc 200937872 於圖16B至圖i6D(於後述之圖17亦相同),連結位元…與 y_i之線段係意咮將碼位元b;分配給符元之符元位元y〗(替換 至符元位元y」·之位置)。 作為圖16B之第1替換方式,提案採用3種類之替換方式 中之任1種,作為圖16C之第2替換方式,提案採用2種類之 替換方式中之任1種。 作為圖16D之第3替換方式’提案順序地選擇6種類之替 換方式來利用。 圖17係表示調變方式為64qAM(因此,映射成1符元之 LDPC碼之碼位元之位元數m與圖16同樣為6位元)且倍數匕 為2之情況下之解多工器25之結構例、及第4替換方式。 倍數b為2之情況下,記憶體31係具有縱行方向χ橫列方 向為Ν/(6χ2)χ(6χ2)位元之記憶容量,由12(=6χ2)個縱行所 構成。 圖17Α係表示對記憶體31之LDPC碼之寫入順序。 於解多工器25,如圖16所說明,LDPC碼之碼位元在構 成記憶體3 1之縱行從上往下方向(縱行方向)之寫入係從左 朝向右方向之縱行進行。 然後,若碼位元之寫入至最右縱行之最下面終了則從 構成記憶體31之所有縱行之第1列,往橫列方向以12位元 (mb位元)單位讀出碼位元,並供給至替換部32。 替換部32係進行將來自記憶體31之12位元之碼位元之位 置,以第4替換方式替換之替換處理,並將其結果所獲得 之12位兀,作為表示64QAM之2符元(b個符元;)之12位元, 135786.doc -45· 200937872 亦即作為表示64QAM之1符元之6符元位元yojbyhysjhys 及表示接著之1符元之6符元位元丫〇,力72,73^475而輸出。 於此’圖17B係表示藉由圖17A之替換部32所進行之替 換處理之第4替換方式。 此外’倍數b為2之情況下(3以上之情況亦同理),於替 換處理,mb位元之碼位元分配給連續b個符元之mb位元之 符元位元。包含圖17在内,以下為了便於說明,從連續b 個符元之mb位元之符元位元之最高位位元算起之第i+1位 元表示作位元(符元位元)yi。 而且’何種替換方式適當,亦即如何更提升在AWGN通 讯道之錯誤率’係依lDpc碼之編碼率或碼長、調變方式 等而不同。 接著’參考圖18至圖2〇來說明關於藉由圖8之同位交錯 器23所進行之同位交錯。 圖18係表示LDPC碼之檢查矩陣之Tanner圖(一部分)。 校驗節點係若如圖丨8所示,相連於該校驗節點之可變節 點(對應之碼位元)之2個等複數個同時成為抹除等錯誤,則 對相連於該校驗節點之所有可變節點,送回值〇之概率與i 之概率為等概率之訊息。因此,若相連於同一校驗節點之 複數可變節點同時成為抹除等,則解碼性能會劣化。 然而,圖8之LDPC編碼部21所輸出之DVB-S.2之規格所 規疋之LDPC碼為ira碼,檢查矩陣Η之同位矩陣ht係如圖 10所示成為階梯構造。 圖19係表示成為階梯構造之同位矩陣Ητ&對應於該同位 J35786.doc -46 · 200937872 矩陣Ητ之Tanner圖。 亦即’圖19A係表示成為階梯構造之同位矩陣Ητ ;圖 19Β係表示對應於圖19Α之同位矩陣HT^Tannei^。 同位矩陣Ητ成為階梯構造之情況下,於該同位矩陣仏之 Tanner圖中’利用LDPC碼之對應於同位矩陣Ητ之值為1之 要素之行之鄰接碼位元(同位位元)來求出訊息之可變節 點’係相連於同一校驗節點。 因此’若由於叢發失誤或抹除等,上述鄰接之同位位元 同時變成錯誤’則相連在分別對應於該變成錯誤之複數同 位位元之複數可變節點(利用同位位元求出訊息之可變節 點)之校驗節點會將值〇之概率與1之概率為等概率之訊 息,送回相連於該校驗節點之可變節點,因此解碼性能會 劣化。然後,於叢發長(由於叢發而變成錯誤之位元數)甚 大之情況時,解碼性能進一步劣化。 因此’同位交錯器23(圖8)係為了防止上述解碼性能之 劣化’進行將來自LDPC編碼部21之LDPC碼之同位位元, 予以交錯至其他同位位元之位置之同位交錯。 圖20係表示對應於圖8之同位交錯器23進行同位交錯後 之LDPC碼之檢查矩陣η之同位矩陣ht。 於此,LDPC編碼部21所輸出之對應於DVB_S 2之規格所 規定之LDPC碼之檢查矩陣η之資訊矩陣Ha係成為巡迴構 造。 巡迴構造係指稱某行與其他行之循環一致之構造,亦包 含例如於每P行,該P行之各列之丨之位置為將該p行之最初 135786.doc •47- 200937872 行,僅以與除算同位長Μ所得之值q成比例之值,往行方 向循環移位後之位置之構造。以下,適宜地將巡迴構造之 P行稱為巡迴構造之單位之行數。 作為LDPC編碼部21所輸出之DVB-S.2之規格所規定之 LDPC碼係如圖11所說明,有碼長N為64800位元及16200位 元之2種類之LDPC碼。 現在,若著眼於碼長N為64800位元及16200位元之2種類 之LDPC碼中之碼長N為64800位元之LDPC碼,則該碼長N © 為64800位元之LDPC碼之編碼率係如圖11所說明有11個。 關於該1 1個編碼率分別之碼長N為64800位元之LDPC 碼,就任一個而言,於DVB-S.2之規格均規定巡迴構造之 單位之行數P為同位長Μ之約數中之一及Μ除外之約數之一 之 3 60。 而且,關於11個編碼率分別之碼長Ν為64800位元之 LDPC碼,同位長Μ係利用依編碼率而不同之值q,成為以 式“^9><?=9<360所表示之質數以外之值。因此,值9亦與 ® 巡迴構造之單位之行數P同樣為同位長Μ之約數中之1及Μ 除外之約數之其他1個,藉由以巡迴構造之單位之行數Ρ除 算同位長Μ來獲得(同位長Μ之約數之Ρ及q之積為同位長 M)。 同位交錯器23係如上述,若將資訊長設為K,而且將0以 上、小於P之整數設為X,並且將0以上、小於q之整數設為 y,則作為同位交錯,將來自LDPC編碼部21之LDPC碼之 第K+1至K+M(=N)個碼位元之同位位元中之第Κ+qx+y+l個 135786.doc -48- 200937872 碼位元,交錯至第K+Py+x+1個碼位元之位置。 若根據該類同位交錯,則由於相連於同一校驗節點之可 變節點(對應之同位位元)僅相隔巡迴構造之單位之行數 P,亦即於此僅相隔360位元,因此於叢發長小於360位元 之情況時,可避免相連於同一校驗節點之可變節點之複數 個同時變成錯誤之事態,其結果可改善對於叢發失誤之耐 受性。 此外,將第Κ+qx+y+l個碼位元交錯至第Κ+Py+x+l個碼 Ο 位元之位置之同位交錯後之LDPC碼,係與原本之檢查矩 陣Η進行將第Κ+qx+y+l行置換為第Κ+Py+x+l行之行置換 所獲得之檢查矩陣(以下亦稱轉換檢查矩陣)之LDPC碼一 致。 而且,於轉換檢查矩陣之同位矩陣,如圖20所示出現以 P行(於圖20為360行)作為單位之擬似巡迴構造。 於此,擬似巡迴構造係意味一部分除外之部分成為巡迴 構造之構造。對於DVB-S.2之規格所規定之LDPC碼之檢查 w 矩陣,施以相當於同位交錯之行置換所獲得之轉換檢查矩 陣係於其右角落部分之360列X360行之部分(後述之移位矩 陣),僅缺少1個1之要素(成為0之要素),因此非(完全)巡 迴構造而成為擬似巡迴構造。 此外,圖20之轉換檢查矩陣係成為對於原本之檢查矩陣 Η,除相當於同位交錯之行置換以外,亦施以用以使轉換 檢查矩陣以後述之構成矩陣構成之列之置換(列置換)後之 矩陣。 135786.doc -49- 200937872 接著,參考圖21至圖24,來說明關於作為藉由圖8之縱 行扭轉交錯器24所進行之重排處理之縱行扭轉交錯。 於圖8之發送裝置11,為了提升頻率之利用效率,如上 述將LDPC碼之碼位元之2位元以上作為丨個符元發送。亦 即,例如將碼位元之2位元作為1個符元之情況時,作為調 變方式係利用例如QPSK,將碼位元之4位元作為i個符元 之情況時’作為調變方式係利用例如16qAM。 如此,將碼位元之2位元以上作為〗個符元發送之情況 ® 夺右於某符元發生抹除等,則該符元之碼位元全部變成 錯誤(抹除)。 因此,為了使解碼性能提升,降低相連於同一校驗節點 之可變節點(對應之碼位元)之複數個同時變成抹除之概 率,必須避免對應於1個符元之碼位元之可變節點相連於 同一校驗節點。 另一方面,如上述,LDPC編碼部21所輸出之Dvb_s.2之 ❹ 規格所規定之LDPC碼之檢查矩陣η,資訊矩陣心含有巡 迴構造,同位矩陣Ητ含有階梯構造。然後’如圖2〇所說 明,於同位交錯後之LDPC碼之檢查矩陣即轉換檢査矩 陣’於同位矩陣亦出現巡迴構造(正確而言,如上述為擬 似巡迴構造)。 圖21係表示轉換檢查矩陣。 亦即,圖21A係表示碼長n為64800位元、編碼率⑴為 3/4之LDPC碼之檢查矩陣H之轉換檢查矩陣。 於圖21A’於轉換檢查矩陣,值為1之要素之位置係以點 135786.doc -50· 200937872 (·)表示。 圖21B係以圖21A之轉換檢査矩陣之LDpc碼,亦即以同 位交錯後之LDPC碼作為對象,表示解多工器25(圖8)所進 行之處理。 於圖21B,將調變方式設為16QAM,於構成解多工器25 之s己憶體3 1之4縱行,同位交錯後之LDpc碼之碼位元係寫 入於縱行方向。 於構成記憶體31之4縱行,寫入於縱行方向之碼位元係 ® 於橫列方向,以4位元單位讀出而成為1符元。 該情況下’成為1符元之4位元之碼位元]8(),]81,;82,83可能 成為對應於位於圖21A之轉換後檢查矩陣之任意丨列之j之 碼位70,該情況下,分別對應於該碼位元以,813233之可 變即點係相連於同一校驗節點。 因此,於1符元之4位元之碼位元8〇山132,83成為對應於 位於轉換後檢查矩陣之任意〗列之丨之碼位元之情況下若 ^ 於該符元發生抹除,則於分別對應於碼位元之 可變節點所相連之同一校驗節點,無法求出適當之訊息, 其結果’解碼性能會劣化。 關於編碼率為3/4以外之編碼率亦相同,對應於相連於 同一校驗節點之複數可變節點之複數碼位元可能作為 16QAM之1個符元。 因此’縱行扭轉交錯器24係進行將來自同位交錯器23之 同位交錯後之LDPC碼之碼位元,予以交錯之縱行扭轉交 錯,以便對應於位於轉換檢查矩陣之任意1列之1之複數碼 135786.doc 51 200937872 位元不含於1個符元。 圖 亦 22係說明縱行扭轉交錯 即’圖22係表示解多 17)。 之圖。 工器25之記憶體31(圖16、圓 體31係如圖16所說明,具有於縱行(縱)方向記憶 位’並且於橫列(橫)方向記憶N/(mb)位元之記憶容量, 由W個縱行所構成。然後,縱行扭轉交錯器24係對於記憶The 7L bit TLyi becomes a strong bit, and the 3rd symbol bit h and the 4th symbol bit become weak bits. Figs. 13 to 15 show the arrangement on the IQ plane of 64 symbols (corresponding signal points) in the case where 64QAM is performed by the quadrature modulation unit 27 of Fig. 8. The 64QAM ’1 symbol table is not 6 bits, and there are 64 (=26) symbols. Then, 64 symbols are arranged centering on the origin of the IQ plane, and the direction of the direction is 8x8 square. The symbolic element of the symbol of 64QAM is from the highest bit, and can be used as the sequence 70 yG, yi, y2, y3, y4, y5. In the case where the modulation method is 64QAM, the LDPC code code & the 6-bit element is used as the 6-bit symbolic element ^ to the ys symbol. Here, FIG. 13 is a view showing a bit boundary of the highest bit symbol y 〇 and the second symbol bit of the symbol bit ^ to the symbol of 64QAM, respectively; FIG. 14 shows Regarding the bit boundary of the third symbol bit and the fourth symbol bit 兀^3, FIG. 15 shows the bit boundary for the fifth symbol bit h and the sixth symbol bit y5, respectively. As shown in Fig. 13, respectively, the bit boundary of the highest bit and the second bit 135786.doc • 41-200937872 bit yi are one. And, as shown in Fig. 14, respectively The bit boundary of the third symbol bit d and the fourth symbol bit is two; as shown in FIG. I5, respectively, regarding the fifth symbol bit h and the sixth symbol bit y5 The bit boundary is four. Therefore, regarding the symbolic bit "to" of the symbol of 64QAM, the highest bit position 7Gy〇 and the second symbol bit yi become strong bits, and the third symbol is the third symbol. The bit h and the fourth symbol bit become the next strong bit. Then the 0th symbol bit y4 and the 6th bit bit force become the weak bit. From Fig. 12, further from Fig. 13 Figure 15 shows that 'about orthogonal tuning The sign bit of the symbol has a tendency that the high bit becomes a strong bit and the low bit becomes a weak bit. Here, as illustrated in Fig. 11, the LDPC outputted by the LDPC encoding unit 21 (Fig. 8) The code 'has a code bit element that is strong against the error and a code bit element that is inferior to the error. Moreover, as illustrated in FIGS. 12 to 15 , the symbol of the sign το of the orthogonal modulation performed by the quadrature modulation unit 27 is described. Bits, there are strong bits and weak bits. Therefore, if the error bit of the LDPC code is assigned to the weak symbol of the quadrature modulated symbol, it is the tolerance for the error. Sexuality is reduced. Therefore, an interleaver is proposed which interleaves LDPC by assigning the LDpc code to the error-sense code bit 70 to the strong bit (symbol bit) of the quadrature-modulated symbol. The code multiplexer of the code is processed by the multiplexer 25 of Fig. 8. Fig. 16 is a diagram illustrating the processing of the multiplexer 25 of Fig. 8. 135786.doc -42- 200937872 16A is a functional structure example of the solution (4). The multiplexer 25 is constructed by the memory 3丨 and the replacement unit 32. The oblique "remembered body 31' is supplied with the 2kLDpc code from the LDpc coding unit. The memory 31 is contained in the horizontal (r〇w) (horizontal) direction memory and the longitudinal (column) (longitudinal) The memory capacity of the directional memory N/(mb) bit is written in the wale direction of the LDPC code supplied thereto, and is read in the course direction and supplied to the replacement unit 32. Here, N (=information length K + co-located length M) is the code length of the above table *LDpc code. Moreover, m is the number of bits of the code bit of the LDPC code which becomes 1 symbol; b is a specific positive integer, It is used to multiply the claws by multiples. The multiplexer 25 is as described above, and the LDPC code bit is used as a symbol (symbol) multiple b to indicate the number of symbols obtained by the demultiplexer 25 by the so-called 丨 符 。. Fig. 16A shows the structure W of the demultiplexer in the case where the modulation method is 64QAM, and the number of bits of the megablock of the LDpc code which becomes the i symbol is 6111 is 6 bits. Further, in Fig. 16A, the multiple ^^ is 丨, so the memory 31 has a memory capacity in the wale direction X of the Ν/(6χ l)x (6x 1) bit. Here, the course direction of the memory 31 is a memory area in which the 丨 bit extends in the waling direction, and is hereinafter referred to as a wales as appropriate. In Fig. 16, the memory 31 is composed of 6 (= 6 x 1) vertical lines. In the demultiplexer 25, the code bits of the LDPC code are written from the top to the bottom (the wale direction) in the wales constituting the memory 31. The 135786.doc *43-200937872 lines are from the left to the right. get on. Then, the right code bit 7G is written to the bottom of the rightmost vertical line, and is read out from the first column constituting all the wales of the memory 31 in the horizontal direction by 6 bits (mb bits). The code is only supplied to the replacement unit 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 6-bit memory of the memory 31, and the 6-bit obtained as a result is used as the 6-symbol y〇 representing the symbol of 64QAM. Yi, y2, y3, y4, y5 and output. That is, from the memory 31, the code bit ^ of the mb bit (here, 6 bits 0) is read in the course direction, and if the code bit of the mb bit read from the memory 31 is the highest The bit bit counts the first bit (i = 〇, l, · · ., mb - l), and represents the bit position of the 6-bit read from the memory 31 in the course direction. The meta-system is represented by the highest-order bit, which can be expressed as bits b, bi, b2, b3, b4, b5. The relationship between the weights of the rows illustrated in FIG. 11 is that the code bits in the direction of the bit bG are the code bits for the error strength, and the code bits in the direction of the bit elements become the code bits for the error weakness. . The replacement unit 32' 4 causes the code bit b of the 6-bit from the memory 31. To the strong bit of the error weakening in b5, n to the strong bit in the symbol y〇 to ys of the _ ship , , , , , , , , , ys ys ys ys ys ys ys ys ys Replacement of the location. Here, as an alternative to how to replace the 6-bit code bits b〇 to b5 from the memory 31 and assign them to the 6-symbol bits or even the symbols, there are various ways to propose from each company. Fig. 16B shows a first alternative, and Fig. 16C shows a second alternative. Fig. 16D shows a third alternative. 135786.doc 200937872 is shown in Fig. 16B to Fig. 6D (Fig. 17 which will be described later) The same), the line segment... and the line segment of y_i are intended to assign the code bit b; to the symbol y of the symbol (replaced to the position of the symbol y). As a first alternative to Fig. 16B, any one of the three types of alternatives is proposed, and as a second alternative of Fig. 16C, any one of the two types of alternatives is proposed. As a third alternative of Fig. 16D, it is proposed to sequentially select six types of replacement methods for use. Fig. 17 is a diagram showing the multiplexing in the case where the modulation method is 64qAM (hence, the number of bits m of the code bit mapped to the 1-element LDPC code is 6 bits as in Fig. 16) and the multiple 匕 is 2. The configuration example of the device 25 and the fourth alternative. When the multiple b is 2, the memory 31 has a memory capacity of Ν/(6χ2)χ(6χ2) bits in the wale direction, and is composed of 12 (=6χ2) wales. Fig. 17 shows the order in which the LDPC codes of the memory 31 are written. In the demultiplexer 25, as illustrated in FIG. 16, the code bits of the LDPC code are written from the top to the bottom (the wale direction) in the wales constituting the memory 3 1 from the left to the right. get on. Then, if the code bit is written to the bottom of the rightmost vertical line, the code is read from the first column of all the wales constituting the memory 31 to the horizontal direction in units of 12 bits (mb bits). The bit is supplied to the replacement unit 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 12-bit memory of the memory 31 with the fourth alternative, and obtains the 12-bit 兀 obtained as a result of the symbol of 64QAM ( b symbols;) 12 bits, 135786.doc -45· 200937872, which is the 6-symbol yojbyhysjhys representing the 1 symbol of 64QAM and the 6-symbol bit representing the next symbol. The force is 72, 73^475 and is output. Here, Fig. 17B shows a fourth alternative of the replacement process performed by the replacement unit 32 of Fig. 17A. Further, in the case where the multiple b is 2 (the same applies to the case of 3 or more), in the replacement processing, the code bits of the mb bits are allocated to the symbol bits of the mb bits of the consecutive b symbols. Including the figure 17, the i+1th bit from the highest bit of the mb bit of the consecutive b symbols is represented as a bit (symbol bit) for convenience of explanation. Yi. Moreover, what kind of replacement method is appropriate, that is, how to improve the error rate of the AWGN communication channel is different depending on the coding rate, code length, modulation mode, etc. of the lDpc code. Next, the co-interleaving by the parity interleaver 23 of Fig. 8 will be explained with reference to Figs. 18 to 2B. Fig. 18 is a Tanner diagram (part) showing a check matrix of an LDPC code. If the check node is as shown in FIG. 8, two or more of the variable nodes (corresponding code bits) connected to the check node are simultaneously erased and the like, and the pair is connected to the check node. For all variable nodes, the probability of returning the value 〇 and the probability of i are equal probability messages. Therefore, if the complex variable nodes connected to the same check node become erased at the same time, the decoding performance deteriorates. However, the LDPC code of the specification of DVB-S.2 outputted by the LDPC encoding section 21 of Fig. 8 is the ira code, and the parity matrix ht of the check matrix 成为 is a ladder structure as shown in Fig. 10 . Fig. 19 is a view showing a tandem map of a matrix Ητ & which corresponds to the same position J35786.doc -46 · 200937872 matrix Ητ. That is, Fig. 19A shows the parity matrix Ητ which is a step structure; Fig. 19 shows the parity matrix HT^Tannei^ corresponding to Fig. 19A. In the case where the co-located matrix Ητ is a ladder structure, in the Tanner graph of the co-located matrix ', the contiguous code bit (the parity bit) of the row corresponding to the element having the value of the parity matrix Ητ of the LDPC code is used. The variable node of the message is connected to the same check node. Therefore, if the above-mentioned adjacent parity bits become errors at the same time due to clumping errors or erasures, etc., they are connected to complex variable nodes corresponding to the complex multiplicative bits that become erroneous (using the same bit to obtain the information) The check node of the variable node sends the probability of the value 与 and the probability of 1 to the equal probability message back to the variable node connected to the check node, so the decoding performance is degraded. Then, when the length of the cluster (the number of bits that become the error due to the burst) is large, the decoding performance is further deteriorated. Therefore, the 'co-located interleaver 23 (Fig. 8) performs the co-interleaving in which the parity bits of the LDPC code from the LDPC encoding unit 21 are interleaved to the positions of the other parity bits in order to prevent the deterioration of the above-described decoding performance. Figure 20 is a diagram showing the parity matrix ht of the check matrix η of the LDPC code corresponding to the co-interleave 23 of the co-located interleaver 23 of Figure 8 . Here, the information matrix Ha of the inspection matrix η corresponding to the LDPC code defined by the specification of DVB_S 2 output by the LDPC encoding unit 21 is a tour configuration. The tour structure refers to a structure in which a row is consistent with the cycle of other rows, and includes, for example, in each P row, the position of each row of the P row is the first 135786.doc •47-200937872 row of the p row, only The structure of the position after the cyclic shift in the row direction is a value proportional to the value q obtained by subtracting the same length. Hereinafter, the P row of the tour structure is appropriately referred to as the number of rows of the tour structure. The LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 is as shown in Fig. 11, and has two types of LDPC codes of code length N of 64,800 bits and 16,200 bits. Now, if we look at the LDPC code in which the code length N of the two types of LDPC codes of 64800 bits and 16200 bits is 64800 bits, the code length N © is the encoding of the 64800-bit LDPC code. The rate is 11 as illustrated in Figure 11. Regarding the LDPC code in which the code length N of each of the 11 coding rates is 64,800 bits, in either case, the specification of the unit of DVB-S.2 stipulates that the number of rows P of the unit of the tour structure is the divisor of the same length. One of the covenants except one and the third is 60. Further, regarding the LDPC codes in which the code lengths of the 11 coding rates are 64,800 bits, the parity is expressed by the value "^9><?=9<360, which is different depending on the coding rate. The value other than the prime number. Therefore, the value 9 is also the same as the number of rows P of the unit of the patrol structure, and the other one of the divisors of the same length, and the other one of the divisors, by the unit of the tour structure. The number of 同 is calculated by the same-digit length ( (the product of the divisor and the q is the same-length length M). The co-interleaver 23 is as described above, if the information length is set to K, and the value is 0 or more and less than P When the integer is set to X, and an integer of 0 or more and less than q is set to y, the K+1 to K+M (=N) code bits of the LDPC code from the LDPC encoding unit 21 are used as the parity interleave. The Κ+qx+y+l 135786.doc -48- 200937872 code bits in the same bit are interleaved to the position of the K+Py+x+1 code bits. Since the variable nodes (corresponding co-located bits) connected to the same check node are only separated by the number of rows P of the unit of the tour structure, that is, only 360 bits apart, When the length of the burst is less than 360 bits, the multiple of the variable nodes connected to the same check node can be prevented from becoming a wrong state at the same time, and the result can improve the tolerance to the burst error. +qx+y+l code bits are interleaved to the Κ+Py+x+l code LDP bit position, and the LDPC code after the parity interleaving is performed with the original check matrix Κ+qx+y The LDPC code of the check matrix (hereinafter also referred to as the conversion check matrix) obtained by the row replacement of the +1 row and the Py+x+l row is identical. Moreover, the parity matrix of the conversion check matrix is as shown in FIG. A pseudo-tour structure in which the P line (360 lines in Fig. 20) is used as a unit appears. Here, the pseudo-tour structure means that a part of the circuit structure is a structure of the tour structure. The LDPC code specified for the specification of DVB-S.2 Checking the w matrix, the conversion check matrix obtained by the row replacement corresponding to the co-interlace is part of 360 rows X360 rows in the right corner portion (the shift matrix described later), and only one element of 1 is missing. 0 element), so non- (complete) tour structure In addition, the conversion check matrix of FIG. 20 is a replacement for the original check matrix Η, except for the row substitution corresponding to the co-interleaving, and the column for forming the matrix of the conversion check matrix described later. Matrix after (column replacement) 135786.doc -49- 200937872 Next, with reference to FIG. 21 to FIG. 24, the longitudinal twist interleaving as a rearrangement process by the whirling twist interleaver 24 of FIG. 8 will be described. In the transmitting apparatus 11 of FIG. 8, in order to increase the frequency utilization efficiency, two bits or more of the code bits of the LDPC code are transmitted as one symbol as described above. In other words, for example, when two bits of the code bit are used as one symbol, the modulation method is used as a modulation when, for example, QPSK is used, and four bits of the code bit are used as i symbols. The method utilizes, for example, 16qAM. In this case, when two or more bits of the code bit are transmitted as the first symbol, the code bit of the symbol is erased (erased). Therefore, in order to improve the decoding performance, the probability that the plurality of variable nodes (corresponding code bits) connected to the same check node are simultaneously erased must be avoided, and the code bit corresponding to one symbol must be avoided. The variable nodes are connected to the same check node. On the other hand, as described above, the inspection matrix η of the LDPC code defined by the D specification of Dvb_s.2 outputted by the LDPC encoding unit 21 has a tour matrix structure, and the parity matrix Ητ has a ladder structure. Then, as shown in Fig. 2, the check matrix of the LDPC code after the co-interleaving, that is, the conversion check matrix, also exhibits a tour structure in the parity matrix (correctly, as described above, a pseudo-tour structure). Figure 21 shows a conversion check matrix. That is, Fig. 21A shows a conversion check matrix of the check matrix H of the LDPC code having a code length n of 64,800 bits and a coding rate (1) of 3/4. In Fig. 21A', in the conversion check matrix, the position of the element having a value of 1 is represented by a point 135786.doc -50· 200937872 (·). Fig. 21B shows the processing performed by the demultiplexer 25 (Fig. 8) by using the LDpc code of the conversion check matrix of Fig. 21A, that is, the LDPC code which is interleaved. In Fig. 21B, the modulation mode is set to 16QAM, and the DMA block of the LDpc code which constitutes the multiplexer 25 is written in the wale direction. In the four vertical lines constituting the memory 31, the code bit system ® written in the wale direction is read in the horizontal direction and is read into one symbol in units of four bits. In this case, 'a 4-bit code bit that becomes a symbol> 8(),]81,; 82, 83 may become a code bit 70 corresponding to j of any of the columns of the post-conversion check matrix of FIG. 21A. In this case, respectively, corresponding to the code bit, the variable point of 813233 is connected to the same check node. Therefore, in the case where the code bit of the 4-bit symbol of the 1-bit element 8 〇山132,83 becomes the code bit corresponding to the 〗 column of any of the columns of the post-conversion check matrix, if the symbol is erased Then, the same check node connected to the variable node corresponding to the code bit can not find an appropriate message, and the result 'decoding performance deteriorates. The coding rate other than the coding rate of 3/4 is also the same, and the complex digital bit corresponding to the complex variable node connected to the same check node may be one symbol of 16QAM. Therefore, the 'twist twist interleaver 24 performs the bitwise twist interleaving of the code bits of the LDPC code interleaved from the co-located interleaver 23 so as to correspond to any one of the columns of the conversion check matrix. Complex digital 135786.doc 51 200937872 Bits are not included in 1 symbol. Fig. 22 also shows the longitudinal twisting and staggering, i.e., Fig. 22 shows the solution 17). Picture. The memory 31 of the tool 25 (Fig. 16, the circle 31 is as illustrated in Fig. 16, has memory in the longitudinal (longitudinal) direction] and memorizes the memory of the N/(mb) bit in the horizontal (horizontal) direction. Capacity, consisting of W wales. Then, the longitudinal twisting interleaver 24 is for memory
❹ 體3卜控制將LDPC碼之碼位元寫入於縱行方向於橫列 方向Μ時K寫位置’藉此進行縱行扭轉交錯。 亦即,於縱行扭轉交錯器24,分別針對複數縱行,適宜 地變更開始碼位元之寫入之開始寫位置,以使於橫列方向 讀出之作為1符元之複數瑪位元,不會成為對應於位於轉 換檢查矩陣之任意1列之1之碼位元(重排LDPC碼之碼位 元,以使對應於位於檢查矩陣之任意丨列以之複數瑪位元 不含於同一符元)。 於此圓22係表不調變方式為16QAM且圖16所說明之倍 數b為1之情況下之記憶體31之結構例。因此,被作為丨符 元之LDPC碼之碼位元之位元數瓜為斗位^,而1記憶體?! 係以4(=mb)個縱行所構成。 縱行扭轉交錯器24(取代圖16之解多工器25)係從左朝向 右方向之縱行,進行將1^1)1)(:碼之碼位元從構成記憶體31 之4個縱行從上往下方向(縱行方向)之寫入。 然後,若碼位元之寫入至最右縱行終了,則縱行扭轉交 錯器24係從構成記憶體3 1之所有縱行之第1列,於橫列方 135786.doc •52· 200937872 向以4位元⑽位元)單位讀出碼位元,並作為縱行扭轉交 錯後之LDPC碼輸出至解多工器25之替換部32(圓16 17)。 其中,於縱行扭轉交錯器24,《將各縱行之開頭(最上 面)之位置之絲設為〇,以升序之整數表示縱行方向之各 位置之位址,則關於最左縱行,將開始寫位置設作位址為 〇之位置,關於(左起)第2縱行,將開始寫位置設作位址為2 之位置,關於第3縱行,將開始寫位置設作位址為4之位 Ο 置,關於第4縱行,將開始寫位置設作位址為了之位置。 此外,關於開始寫位置是位址為〇之位置以外之位置之 縱行,將碼位元寫入至最下面之位置後,返回開頭(位址 為〇之位置),進行即將至開始寫位置前之位置為止之寫 入。然後,其後進行對下一(右)縱行之寫入。 藉由進行如以上之縱行扭轉交錯,關於DVB S2之規格 所規定之碼長N為64800之所有編碼率之1^)1>(:碼,可避免 於相連於同—校驗節點之複數可變節點之複數瑪位元 被作為16QAM之1個符元(含於同一符元)其結果,可使有 抹除之通訊道之解碼性能提升。 圓23係針對DVB_S2之規格所規定之碼長料6卿之η 個編碼率分別之LDPC碼,依各調變方式表示縱行扭轉交 錯所必要之記憶體31之縱行數及開始寫位置之位址。 由於倍數b為1,且作為調變方式採用例如因此i 符元之位元數―:位元之情況下,若根據圖23,記憶體^ 係含有於橫列方向記憶2xl(=mb)位元之2個縱行於縱行 135786.doc -53- 200937872 方向記憶64800/(2x1)位元β j後"己隐體31之2個縱行中,分別第1縱行之開始寫位 置設作位址為〇之位置’第2縱行之開始寫位置設作位址為 2之位置。 此外’於作為例如解多工器25(圖8)之替換處理之替換 方式採用圖16之第】至第3替換方式中之任—方式之情況等 時’倍數b成為1。The body 3 control converts the code bits of the LDPC code into the writ direction in the wale direction K when the K write position ', thereby performing the wobble interleave. That is, in the vertical twist interleaver 24, for each of the plurality of wales, the start write position of the start code bit is appropriately changed so that the complex position of the first symbol is read in the horizontal direction. , does not become corresponding to the code bit located in any one of the columns of the conversion check matrix (rearrangement of the code bits of the LDPC code, so that the complex bits corresponding to any of the columns in the check matrix are not included in The same symbol). The circle 22 is a configuration example of the memory 31 in the case where the modulation mode is 16QAM and the multiple b is as shown in Fig. 16. Therefore, the number of bits of the code bit of the LDPC code that is used as the symbol is the bucket position ^, and 1 memory? ! It consists of 4 (= mb) wales. The whirch twist interleaver 24 (instead of the demultiplexer 25 of FIG. 16) is a vertical line from the left to the right direction, and performs 1^1) 1) (: code bits are coded from 4 constituting the memory 31) The wales are written from the top to the bottom (the waling direction). Then, if the writing of the code bits to the rightmost wales is finished, the walt twist interleaver 24 is from all the wales constituting the memory 3 1 In the first column, the code bit is read out in units of 4 bits (10) bits in the horizontal row 135786.doc • 52· 200937872, and is output to the demultiplexer 25 as the LDPC code after the wobble interleaving. Replacement portion 32 (circle 16 17). Wherein, in the whirling twist interleaver 24, "the wire at the position of the beginning (topmost) of each wales is set to 〇, and the address of each position in the wale direction is expressed in ascending integer, and the leftmost wales are , the write start position is set as the address of the address, and the second write line (from the left) is set to the position where the address is set to 2, and for the 3rd line, the write position is set as the bit. The address is the position of 4, and for the 4th ordinate, the write position will be set as the address for the position. In addition, regarding the starting position where the writing position is a position other than the position of the address, the code bit is written to the lowermost position, and the beginning is returned (the address is the position of the 〇), and the writing position is started immediately. Write to the previous position. Then, the writing to the next (right) wales is performed thereafter. By performing the wobble interleaving as described above, the code length N defined by the specification of DVB S2 is 1^)1> of the coding rate of 64800 (: code can be avoided in the plural connected to the same-check node The complex-matrix of the variable node is used as the symbol of 16QAM (contained in the same symbol), and the decoding performance of the erased communication channel can be improved. The circle 23 is the code specified by the specification of DVB_S2. The LDPC code of the η encoding rate of the long material 6 qing, the number of wales of the memory 31 and the address of the starting writing position necessary for the vertical twisting interleaving according to each modulation mode. Since the multiple b is 1, and In the case of the modulation method, for example, in the case of the number of bits of the i-symbol -: bit, according to Fig. 23, the memory system contains two wales of 2xl (= mb) bits in the horizontal direction. Line 135786.doc -53- 200937872 Direction memory 64800 / (2x1) bit β j After " 2 hidden lines of the hidden body 31, respectively, the starting position of the first vertical line is set as the address of the position 'The start position of the second wales is set to the position where the address is 2. In addition, as for example, the multiplexer 25 (Fig. 8) Conversion processing using the alternative embodiment of FIG. 16] to the third alternative embodiment of any of - when the situation, etc. 'becomes a multiple of 1 b.
由於倍數b為2,且作為調變方式採用例如qPSK,因此^ 符το之位元數爪為2位元之情況下,若根據圖23,記憶體Μ 係含有於橫列方向記憶2x2位元之4個縱行,於縱行方向記 憶 64800/(2x2)位元。 然後,記憶體31之4個縱行中,分別第丨縱行之開始寫位 置設作位址為0之位置,第2縱行之開始寫位置設作位址為 2之位置,第3縱行之開始寫位置設作位址為*之位置,第* 縱行之開始寫位置設作位址為7之位置。 此外,於作為例如解多工器25(圖8)之替換處理之替換 方式採用圖17之第4替換方式之情況等時,倍數b成為2。 由於倍數b為1,且作為調變方式採用例如丨6qAM,因此 1符元之位元數m為4位元之情況下,若根據圖23,記憶體 31係含有於橫列方向記憶4xl位元之4個縱行,於縱行方向 記憶64800/(4χ 1)位元。 然後’記憶體31之4個縱行中,分別第丨縱行之開始寫位 置設作位址為〇之位置,第2縱行之開始寫位置設作位址為 2之位置,第3縱行之開始寫位置設作位址為4之位置,第4 135786.doc •54· 200937872 縱行之開始寫位置設作位址為7之位置。 由於倍數b為2,且作為調變方式採用例如16QAM,因此 1符兀之位元數m為4位元之情況下,若根據圖23,記憶體 31係含有於橫列方向記憶4χ2位元之8個縱行,於縱行方向 記憶6480〇/(4χ2)位元。 然後,記憶體31之8個縱行中,分別第丨縱行之開始寫位 置設作位址為0之位置,第2縱行之開始寫位置設作位址為 0之位置,第3縱行之開始寫位置設作位址為2之位置,第4 ©縱行之開始寫位置設作位址為4之位置H縱行之開始寫 位置設作位址為4之位置,第6縱行之開始寫位置設作位址 為5之位置,第7縱行之開始寫位置設作位址為了之位置, 第8縱行之開始寫位置設作位址為7之位置。 由於倍數1)為卜且作為調變方式採用例如64QAM,因此 1符兀之位元數6位元之情況下,若根據圖23,記憶體 31係含有於橫列方向記憶6 χ丨位元之6個縱行,於縱行方向 記憶64800/(6x1)位元。 然後,記憶體31之6個縱行中,分別第丨縱行之開始寫位 置設作位址為〇之位置,第2縱行之開始寫位置設作位址為 2之位置,第3縱行之開始寫位置設作位址為5之位置第4 縱行之開始寫位置設作位址為9之位置,第5縱行之開始寫 位置設作位址為1〇之位置,第6縱行之開始寫位置設作位 址為13之位置。 由於倍數b為2,且作為調變方式採用例如64QAM,因此 1符兀之位元數瓜為6位元之情況下,若根據圖23,記憶體 135786.doc -55· 200937872 31係含有於橫列方向記憶6x2位元之12個縱行,於縱行方 向記憶648〇〇/(6x2)位元。 然後,記憶體3 1之12個縱行中,分別第丨縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為0之位置’第3縱行之開始寫位置設作位址為2之位置, 第4縱行之開始寫位置設作位址為2之位置第5縱行之開 始寫位置設作位址為3之位置,第6縱行之開始寫位置設作 位址為4之位置,第7縱行之開始寫位置設作位址為4之位 © 置,第8縱行之開始寫位置設作位址為5之位置,第9縱行 之開始寫位置設作位址為5之位置,第1〇縱行之開始寫位 置設作位址為7之位置,第丨丨縱行之開始寫位置設作位址 為8之位置,第12縱行之開始寫位置設作位址為9之位置。 由於倍數b為1,且作為調變方式採用例如256qam,因 此1符元之位元數„!為8位元之情況下,若根據圖23,記憶 體31係含有於橫列方向記憶8xl位元之8個縱行,於縱行方 向記憶64800/(8x1)位元。 ❹ 然後,記憶體31之8個縱行中,分別第丨縱行之開始寫位 置設作位址為〇之位置,第2縱行之開始寫位置設作位址為 〇之位置’第3縱行之開始寫位置設作位址為2之位置,第4 縱行之開始寫位置設作位址為4之位置,第5縱行之開始寫 位置設作位址為4之位置,第6縱行之開始寫位置設作位址 為5之位置,第7縱行之開始寫位置設作位址為7之位置, 第8縱行之開始寫位置設作位址為7之位置。 由於倍數b為2’且作為調變方式採用例如256qAM,因 135786.doc -56- 200937872 此1符元之位元數m為8位元之情況下,若根據圖23,記憶 體31係含有於橫列方向記憶8χ2位元之16個縱行,於縱行 方向記憶64800/(8x2)位元。 然後,記憶體3 1之16個縱行中,分別第丨縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為2之位置,第3縱行之開始寫位置設作位址為2之位置, 第4縱行之開始寫位置設作位址為2之位置,第5縱行之開 始寫位置設作位址為2之位置,第6縱行之開始寫位置設作 © 位址為3之位置,第7縱行之開始寫位置設作位址為7之位 置,第8縱行之開始寫位置設作位址為15之位置,第9縱行 之開始寫位置設作位址為16之位置,第1〇縱行之開始寫位 置設作位址為20之位置,第u縱行之開始寫位置設作位址 為22之位置,第12縱行之開始寫位置設作位址為^之位 置,第13縱行之開始寫位置設作位址為27之位置,第^縱 行之開始寫位置設作位址為27之位置,第15縱行之開始寫 位置设作位址為28之位置,第16縱行之開始寫位置設作位 址為3 2之位置。 由於倍數b為1,且作為調變方式採用例如1〇24QAM,因 此1符元之位元數爪為⑺位元之情況下,若根據圖23,記憶 體3 1係含有於橫列方向記憶丨〇χ丨位元之丨〇個縱行於縱行 方向記憶64800/(1 〇xl)位元。 然後,記憶體31之10個縱行中,分別第丨縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為3之位置,第3縱行之開始寫位置設作位址為6之位置, 135786.doc -57· 200937872 第4縱行之開始寫位置設作位址為8之位置,第5縱行之開 始寫位置設作位址為11之位置,第6縱行之開始寫位置設 作位址為13之位置,第7縱行之開始寫位置設作位址為^ 之位置,第8縱行之開始寫位置設作位址為17之位置,第9 縱行之開始寫位置設作位址為18之位置,第1〇縱行之開始 寫位置設作位址為20之位置。 由於倍數b為2,且作為調變方式採用例如1〇24QAM,因 此1符元之位元數m為1〇位元之情況下,若根據圖23,記憶 © 體31係含有於橫列方向記憶10x2位元之20個縱行,於縱行 方向記憶64800/( 1〇χ2)位元。 然後,記憶體3 1之20個縱行中,分別第i縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為1之位置,第3縱行之開始寫位置設作位址為3之位置, 第4縱行之開始寫位置設作位址為4之位置第5縱行之開 始寫位置設作位址為5之位置,第6縱行之開始寫位置設作 ❿位址為6之位置,第7縱行之開始寫位置設作位址為6之位 置,第8縱行之開始寫位置設作位址為9之位置,第9縱行 之開始寫位置設作位址為13之位置,第1〇縱行之開始寫位 置設作位址為14之位置,第u縱行之開始寫位置設作位址 為14之位置,第〗2縱行之開始寫位置設作位址為丨6之位 置,第13縱行之開始寫位置設作位址為21之位置,第^縱 行之開始寫位置設作位址為21之位置,第15縱行之開始寫 位置成作位址為23之位置,第16縱行之開始寫位置設作位 址為25之位置,第丨7縱行之開始寫位置設作位址為之位 135786.doc -58 · 200937872 置’第18縱行之開始寫位置設作位址為26之位置,第19縱 行之開始寫位置設作位址為28之位置,第20縱行之開始寫 位置設作位址為30之位置。 由於倍數b為1,且作為調變方式採用例如4096QAM,因 此1符元之位元數爪為丨]位元之情況下,若根據圖23,記憶 體3 1係含有於橫列方向記憶〗2x丨位元之丨2個縱行,於縱行 方向記憶64800/(12x1)位元。 然後’記憶體3 1之12個縱行中,分別第1縱行之開始寫 ® 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為0之位置,第3縱行之開始寫位置設作位址為2之位置, 第4縱行之開始寫位置設作位址為2之位置,第5縱行之開 始寫位置設作位址為3之位置,第6縱行之開始寫位置設作 位址為4之位置,第7縱行之開始寫位置設作位址為4之位 置,第8縱行之開始寫位置設作位址為5之位置,第9縱行 之開始寫位置設作位址為5之位置,第1〇縱行之開始寫位 ❹置叹作位址為7之位置,第U縱行之開始寫位置設作位址 為8之位置,第12縱行之開始寫位置設作位址為9之位置。 由於倍數b為2,且作為調變方式採用例如4〇96QAm,因 此1符兀之位凡數111為12位元之情況下,若根據圖23,記憶 體31係3有於橫列方向記憶12χ2位元之24個縱行,於縱行 方向記憶64800/(12x2)位元。 然後,記憶體3丨之24個縱行中,分別第丨縱行之開始寫 又作位址為〇之位置,第2縱行之開始寫位置設作位址 、、5之位置’第3縱行之開始寫位置設作位址為8之位置, 135786.doc •59· 200937872 第4縱行之開始寫位置設作位址為8之位置,第5縱行之開 始寫位置設作位址為8之位置’第6縱行之開始寫位置設作 位址為8之位置,第7縱行之開始寫位置設作位址㈣之位 置,第8縱行之開始寫位置設作位址為1〇之位置,第9縱行 之開始寫位置設作位址為10之位置,第1〇縱行之開始寫位 置設作位址為12之位置,第U縱行之開始寫位置設作位址 為13之位置,第12縱行之開始寫位置設作位址為“之位 置,第13縱行之開始寫位置設作位址為17之位置,第丨斗縱 ❹行之開始寫位置設作位址為19之位置,第15縱行之開始寫 位置設作位址為21之位置,第16縱行之開始寫位置設作位 址為22之位置,第17縱行之開始寫位置設作位址為幻之位 置,第18縱行之開始寫位置設作位址為%之位置,第^縱 行之開始寫位置設作位址為37之位置,第2〇縱行之開始寫 位置設作位址為39之位置,第21縱行之開始寫位置設作位 址為40之位置,第22縱行之開始寫位置設作位址為〇之位 ◎ 置,第23縱行之開始寫位置設作位址為u之位置,第縱 行之開始寫位置設作位址為41之位置。 圖24係針對DVB_S.2之規格所規定之碼長N為l62oo之lo 個編碼率分別之LDPC碼,依各調變方式表示縱行扭轉交 錯所必要之記憶體31之縱行數及開始寫位置之位址。 由於倍數b為1 ’且作為調變方式採用例如QpSK ,因此i 符兀之位tl數m為2位元之情況下,若根據圖24,記憶體31 係含有於橫列方向記憶2x1位元之2個縱行,於縱行方向記 憶 16200/(2x1)位元。 135786.doc •60- 200937872 然後,記憶體3 1之2個縱行中,分別第】縱行之開始寫位 覃設作位址為〇之位置,第2縱行之開始寫位置設作位址為 0之位置。 由於倍數b為2,且作為調變方式採用例如QpSK,因此】 符兀之位元數m為2位元之情況下,若根據圖24,記憶體3 ^ 係含有於橫列方向記憶2 X2位元之4個縱行,於縱行方向記 憶 16200/(2x2)位元。 然後,記憶體3 1之4個縱行中,分別第丨縱行之開始寫位 © 置設作位址為〇之位置’第2縱行之開始寫位置設作位址為 2之位置,第3縱行之開始寫位置設作位址為3之位置,第4 縱行之開始寫位置設作位址為3之位置。 由於倍數b為1,且作為調變方式採用例如16QAM,因此 1符元之位元數4位元之情況下,若根據圖24,記憶體 31係含有於橫列方向記憶4xl位元之4個縱行,於縱行方向 記憶16200/(4 xl)位元。 〇 然後,記憶體31之4個縱行中,分別第!縱行之開始寫位 置設作位址為0之位置’第2縱行之開始寫位置設作位址為 2之位置,第3縱行之開始寫位置設作位址為3之位置,第* 縱行之開始寫位置設作位址為3之位置。 由於倍數b為2,且作為調變方式採用例如16QAM,因此 1符兀•之位元數!《為4位元之情況下,若根據圖%,記憶體 Η係含有於橫列方向記憶4x2位元之8個縱行,於縱行方向 記憶16200/(4x2)位元。 然後,6己憶體3 1之8個縱行中,分別第丨縱行之開始寫位 135786.doc -61 - 200937872 置設作位址為〇之位置,第2縱行之開始寫位置設作位址為 〇之位置’第3縱行之開始寫位置設作位址為〇之位置,第4 縱行之開始寫位置設作位址為1之位置,第5縱行之開始寫 位置設作位址為7之位置,第6縱行之開始寫位置設作位址 為20之位置,第7縱行之開始寫位置設作位址為2〇之位 置’第8縱行之開始寫位置設作位址為21之位置。 由於倍數b為1,且作為調變方式採用例如64qam,因此 1符元之位元數瓜為6位元之情況下’若根據圖24,記憶體 3 1係含有於橫列方向記憶6 X 1位元之6個縱行,於縱行方向 記憶16200/(6 XI)位元。 然後,記憶體3 1之6個縱行中,分別第1縱行之開始寫位 置設作位址為0之位置,第2縱行之開始寫位置設作位址為 〇之位置’第3縱行之開始寫位.置設作位址為2之位置,第4 縱行之開始寫位置設作位址為3之位置,第5縱行之開始寫 位置設作位址為7之位置,第6縱行之開始寫位置設作位址 為7之位置。 由於倍數b為2,且作為調變方式採用例如64QAM,因此 1符元之位元數„!為6位元之情況下,若根據圖24,記憶體 31係含有於橫列方向記憶6x2位元之12個縱行,於縱行方 向記憶16200/(6x2)位元。 然後,記憶體31之12個縱行中,分別第〗縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為〇之位置,第3縱行之開始寫位置設作位址為〇之位置, 第4縱行之開始寫位置設作位址為2之位置,第5縱行之開 135786.doc •62· 200937872 始寫位置設作位址為2之位置,第6縱行之開始寫位置設作 位址為2之位置,第7縱行之開始寫位置設作位址為3之位 置’第8縱行之開始寫位置設作位址為3之位置,第9縱行 之開始寫位置設作位址為3之位置,第1〇縱行之開始寫位 置設作位址為6之位置,第11縱行之開始寫位置設作位址 為7之位置,第12縱行之開始寫位置設作位址為7之位置。 由於倍數b為1 ’且作為調變方式採用例如256qam,因 此1符元之位元數瓜為8位元之情況下,若根據圖24,記憶 〇 體31係含有於橫列方向記憶8x1位元之8個縱行,於縱行方 向記憶16200/(8x1)位元。 然後,記憶體31之8個縱行中,分別第丨縱行之開始寫位 置設作位址為〇之位置,第2縱行之開始寫位置設作位址為 〇之位置’第3縱行之開始寫位置設作位址為〇之位置,第4 縱行之開始寫位置設作位址為1之位置,第5縱行之開始寫 位置設作位址為7之位置,第6縱行之開始寫位置設作位址 ❿ 為20之位置,第7縱行之開始寫位置設作位址為2〇之位 置,第8縱行之開始寫位置設作位址為2丨之位置。 由於倍數b為1,且作為調變方式採用例如1024qam,因 此1符兀之位元數丨〇位元之情況下,若根據圖24,記憶 體3 1係含有於橫列方向記憶1 〇x 1位元之10個縱行,於縱行 方向記憶16200/(10x1)位元。 然後’記憶體3 1之1 〇個縱行中,分別第1縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為1之位置’第3縱行之開始寫位置設作位址為2之位置, 135786.doc -63 - 200937872 第4縱行之開始寫位置設作位址為2之位置,第5縱行之開 始寫位置設作位址為3之位置,第6縱行之開始寫位置設作 位址為3之位置,第7縱行之開始寫位置設作位址為4之位 置第8縱行之開始寫位置設作位址為4之位置,第9縱行 之開始寫位置設作位址為5之位置,第1〇縱行之開始寫位 置設作位址為7之位置。 由於倍數b為2,且作為調變方式採用例如1〇24QAM,因 此1符70之位兀數爪為i 〇位元之情況下,若根據圖24 ’記憶 ®體31係含有於橫列方向記憶10X2位元之20個縱行,於縱行 方向記憶16200/(10x2)位元。 然後,記憶體3 1之20個縱行中,分別第i縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為〇之位置,第3縱行之開始寫位置設作位址為〇之位置, 第4縱行之開始寫位置設作位址為2之位置,第义縱行之開 始寫位置設作位址為2之位置’第6縱行之開始寫位置設作 ◎ 址為2之位置,第7縱行之開始寫位置設作位址為2之位 置,第8縱行之開始寫位置設作位址為2之位置,第9縱行 之開始寫位置設作位址為5之位置,第1〇縱行之開始寫位 置設作位址為5之位置,第u縱行之開始寫位置設作位址 為5之位置,第12縱行之開始寫位置設作位址為^之位置, 第13縱行之開始寫位置設作位址為5之位置,第14縱行之 開始寫位置設作位址為7之位置,第15縱行之開始寫位置 設作位址為7之位置,第16縱行之開始寫位置設作位址為7 之位置,第17縱行之開始寫位置設作位址為7之位置,第 135786.doc 200937872 18縱行之開始寫位置設作位址為8之位置,第19縱行之開 始寫位置設作位址為8之位置,第20縱行之開始寫位置設 作位址為1 〇之位置。 由於倍數b為1,且作為調變方式採用例如4〇96qaM,因 此1符元之位元數m為、丨2位元之情況下,若根據圖24 ’記憶 體31係含有於橫列方向記憶i2x i位元之丨2個縱行,於縱行 方向記憶16200/( 12x1)位元。 然後,記憶體3 1之丨2個縱行中,分別第丨縱行之開始寫 © 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為0之位置,第3縱行之開始寫位置設作位址為〇之位置, 第4縱行之開始寫位置設作位址為2之位置,第5縱行之開 始寫位置设作位址為2之位置,第6縱行之開始寫位置設作 位址為2之位置,第7縱行之開始寫位置設作位址為3之位 置,第8縱行之開始寫位置設作位址為3之位置第9縱行 之開始寫位置設作位址為3之位置,第1〇縱行之開始寫位 q 置設作位址為6之位置,第11縱行之開始寫位置設作位址 為7之位置,第丨2縱行之開始寫位置設作位址為7之位置。 由於倍數b為2,且作為調變方式採用例如4〇96QAM,因 此1符兀之位兀數mg12位元之情況下,若根據圖24,記憶 體31係含有於橫列方向記憶12)<2位元之24個縱行,於縱行 方向記憶16200/(12x2)位元。 然後,記憶體31之24個縱行中,分別第i縱行之開始寫 位置設作位址為〇之位置,第2縱行之開始寫位置設作位址 為〇之位置,第3縱行之開始寫位置設作位址為〇之位置, 135786.doc 200937872 第4縱行之開始寫位置設作位址為〇之位置,第5縱行之開 始寫位置設作位址為〇之位置,第6縱行之開始寫位置設作 位址為0之位置’第7縱行之開始寫位置設作位址為〇之位 置’第8縱行之開始寫位置設作位址為1之位置,第9縱行 之開始寫位置設作位址為1之位置,第丨〇縱行之開始寫位 置設作位址為1之位置,第u縱行之開始寫位置設作位址 為2之位置,第12縱行之開始寫位置設作位址為2之位置, 第13縱行之開始寫位置設作位址為2之位置,第u縱行之 © 開始寫位置設作位址為3之位置,第15縱行之開始寫位置 設作位址為7之位置,第16縱行之開始寫位置設作位址為9 之位置,第17縱行之開始寫位置設作位址為9之位置,第 18縱行之開始寫位置設作位址為9之位置,第19縱行之開 始寫位置設作位址為10之位置,第2〇縱行之開始寫位置設 作位址為10之位置,第21縱行之開始寫位置設作位址為1〇 之位置,第22縱行之開始寫位置設作位址為丨〇之位置,第 23縱行之開始寫位置設作位址為1〇之位置,第以縱行之開 始寫位置設作位址為1 1之位置。 接著,參考圖25之流程圖來說明關於圖8之發送裝置u 所進行之發送處理。 LDPC編碼部21係於該處等待對象資料供給於步驟 si〇i,將對象資料編碼為LDPC碼,將該LDpc碼供給至位 元交錯器22 ’處理係前進至步驟S102。 位元交錯器22係於步驟S102,將來自LDPC編碼部21之 LDPC碼作為對象,進行位元交錯,將該位元交錯後之 135786.doc -66 - 200937872 LDPC碼經符元化之符元供給至映射部%,處理係前進至 步驟S103。 亦即,於步驟S102,於位元交錯器22,同位交錯器 將來自LDPC編瑪部21之LDPC碼作為對象,進行同位交Since the multiple b is 2, and qPSK is used as the modulation method, if the number of bits of the ^τ is 2 bits, according to Fig. 23, the memory contains 2x2 bits in the horizontal direction. The four wales store 64800/(2x2) bits in the wale direction. Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is *, and the start write position of the *th vertical line is set to the position where the address is 7. Further, when the fourth alternative of Fig. 17 is used as an alternative to the replacement processing of the demultiplexer 25 (Fig. 8), the multiple b becomes 2. Since the multiple b is 1, and the modulation method is, for example, 丨6qAM, when the number of bits of the 1-symbol m is 4 bits, according to FIG. 23, the memory 31 contains 4x1 bits in the horizontal direction. 4 vertical lines of the Yuan, remembering 64800/(4χ 1) bits in the longitudinal direction. Then, in the four wales of the memory 31, the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start of the write position is set to the address of 4, the 4th 135786.doc •54·200937872 The start position of the wales is set to the address of 7. Since the multiple b is 2, and 16HAM is used as the modulation method, for example, when the number of bits of the one symbol is 4 bits, according to FIG. 23, the memory 31 contains 8 bits of 4 bits in the horizontal direction. Longitudinal, remembering 6480〇/(4χ2) bits in the longitudinal direction. Then, among the eight wales of the memory 31, the start write position of the ninth wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start position of the line is set to the position of the address 2, the start position of the 4th ordinate is set to the position where the address is 4, and the start position of the waling is set to the position where the address is 4, the 6th vertical The start write position of the line is set to the position where the address is 5, and the start write position of the seventh vertical line is set as the address for the position, and the start write position of the eighth vertical line is set to the position of the address 7. Since the multiple 1) is used as the modulation method and 64QAM is used as the modulation method, for example, when the number of bits of the 1 symbol is 6 bits, according to FIG. 23, the memory 31 contains 6 bits of the memory in the horizontal direction. Longitudinal, remembering 64800/(6x1) bits in the wale direction. Then, among the six wales of the memory 31, the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start position of the line is set to the position where the address is 5, the start position of the 4th vertical line is set to the position where the address is 9, and the write position of the 5th vertical line is set to the position of the address of 1〇, the sixth position. The start position of the wales is set to the position of the address 13. Since the multiple b is 2, and the modulation method is, for example, 64QAM, if the number of bits of the 1 symbol is 6 bits, according to FIG. 23, the memory 135786.doc -55· 200937872 31 is included in the course. The direction stores 12 vertical lines of 6x2 bits, and stores 648〇〇/(6x2) bits in the longitudinal direction. Then, in the 12 wales of the memory 3 1 , the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position where the address is 0. The write start position of the wales is set to the position where the address is 2, the start write position of the 4th ordinate is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth position The start position of the wales is set to the address of 4, the start position of the 7th ordinate is set to the address of 4, and the write position of the 8th traverse is set to the position of 5 The write position of the ninth vertical line is set to the position where the address is 5, the start write position of the first vertical line is set to the address of the address 7, and the start write position of the first vertical line is set as the address. At the position of 8, the start position of the 12th wales is set to the position of the address 9. Since the multiple b is 1, and the modulation method is, for example, 256qam, the number of bits of the first symbol „! is 8 bits, and according to FIG. 23, the memory 31 contains 8×1 bits in the horizontal direction. The 8 vertical lines of the element store 64800/(8x1) bits in the wale direction. ❹ Then, in the 8 wales of the memory 31, the start write position of the 丨 丨 设 is set as the address of the 〇 The write position of the 2nd wales is set to the address of 〇. The write position of the 3rd ordinate is set to the address of 2, and the write position of the 4th trajectory is set to the address of 4. Position, the start position of the 5th ordinate is set to the address of 4, the start position of the 6th ordinate is set to the address of 5, and the write position of the 7th traverse is set to the address of 7. Position, the start position of the 8th wales is set to the position of the address 7. Since the multiple b is 2' and the modulation method is used, for example, 256qAM, because 135786.doc -56- 200937872 is a 1-bit bit In the case where the number m is 8 bits, according to Fig. 23, the memory 31 contains 16 vertical lines in which 8 χ 2 bits are stored in the course direction, and is recorded in the waling direction. 64800/(8x2) bit. Then, in the 16 wales of the memory 3 1 , the start write position of the 丨 丨 设 is set as the address of the 〇, and the write position of the 2nd ordinate is set as the bit. The address is 2, the write position of the 3rd vertical line is set to the position where the address is 2, the write position of the 4th vertical line is set to the position where the address is 2, and the write position of the 5th vertical line is set as the write position. The address of the address is 2, the write position of the sixth vertical line is set to the position where the address is 3, and the write position of the 7th vertical line is set to the position where the address is 7, and the write position of the eighth vertical line is started. The address is set to the position of 15, the write position of the ninth wales is set to the address of 16, and the write position of the first wales is set to the address of 20, the beginning of the ut. The write position is set to the address of the address 22, the start write position of the 12th vertical line is set to the position of the address of ^, and the start write position of the 13th vertical line is set to the position of the address of 27, the second vertical line The start write position is set to the position where the address is 27, the start write position of the 15th vertical line is set to the position of the address 28, and the start write position of the 16th vertical line is set to the position of the address of 3 2 Since the multiple b is 1, and the modulation method is, for example, 1〇24QAM, when the number of bits of the 1 symbol is (7) bits, according to FIG. 23, the memory 3 1 is stored in the horizontal direction. The 纵 丨〇 记忆 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 The address of the address is 〇, the write position of the 2nd ordinate is set to the address of 3, and the write position of the 3rd trajectory is set to the address of 6, 135786.doc -57· 200937872 4 The write start position of the wales is set to the address of 8, the start write position of the 5th ordinate is set to the address of the address 11, and the start write position of the sixth traverse is set to the position of the address of 13, the first The start position of the 7 wales is set to the position where the address is ^, the start write position of the 8th wales is set to the position of the address 17, and the start write position of the ninth walt is set to the position of the address of 18, The first write position of the first wales is set to the position of the address 20. Since the multiple b is 2, and the modulation method is, for example, 1〇24QAM, when the number m of the 1-symbol is 1〇, the memory © 31 is included in the course direction according to FIG. It memorizes 20 vertical lines of 10x2 bits and memorizes 64800/(1〇χ2) bits in the longitudinal direction. Then, in the 20 wales of the memory 3 1 , the start write position of the ith wales is set as the address of the 〇, and the start write position of the second row is set as the address of the address 1, the third The start position of the wales is set to the position where the address is 3, the start position of the 4th rowth is set to the position where the address is 4, and the start position of the 5th traverse is set to the position where the address is 5, the sixth position The start position of the wales is set to the position where the address is 6, the start position of the seventh rowth is set to the address of the address 6, and the start write position of the eighth trajectory is set to the position of the address of 9, The write position of the ninth wales is set to the address of 13, the start write position of the first wales is set to the address of 14, and the start write position of the utitudinal line is set to address 14 Position, the start position of the ">2 wales is set to the address of 丨6, the start write position of the 13th traverse is set to the position of the address 21, and the start write position of the twentieth line is set as the address. For the position of 21, the start position of the 15th wales is the position where the address is 23, and the start of the 16th traverse is set to the position of 25, and the start of the 7th wales The location is set to the address 135786.doc -58 · 200937872. The beginning of the 18th traverse is set to the address of 26, and the write position of the 19th traverse is set to the location of 28. The start position of the 20th wales is set to the position where the address is 30. Since the multiple b is 1, and the modulation method is, for example, 4096QAM, if the number of bits of the 1 symbol is 丨] bit, if according to FIG. 23, the memory 3 1 is stored in the horizontal direction. 2 纵 丨 2 纵 , , 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 64 64 64 64 64 64 64 64 64 64 64 64 64 Then, in the 12 wales of the memory 3 1 , the writing position of the first waling is set to the position of 〇, and the writing position of the second traverse is set to the position of 0. 3 The starting position of the vertical line is set to the position where the address is 2, the writing position of the 4th vertical line is set to the position where the address is 2, and the writing position of the 5th vertical line is set to the position of the address of 3, The start position of the sixth vertical line is set to the position where the address is 4, the start write position of the seventh vertical line is set to the position where the address is 4, and the start write position of the eighth vertical line is set to the position of the address of 5. The write position of the ninth wales is set to the position where the address is 5, and the start of the first 〇 写 写 写 叹 叹 叹 叹 位 位 位 , , 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第For the position of 8, the start position of the 12th wales is set to the position where the address is 9. Since the multiple b is 2, and the modulation method is, for example, 4〇96QAm, the case where the number 111 of the 1 symbol is 12 bits, if the memory 31 is 3, the memory is stored in the horizontal direction according to FIG. 24 vertical lines of the Yuan, remembering 64800/(12x2) bits in the longitudinal direction. Then, among the 24 wales of the memory 3, the start of the 丨 丨 又 又 又 又 位置 , , , , , , , , , , , 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The start position of the wales is set to the address of 8, 135786.doc •59· 200937872 The start position of the 4th wales is set to the address of 8 and the write position of the 5th ordinate is set as the bit. The address of the address is 8 'the start position of the sixth vertical line is set to the address of 8, the start position of the 7th vertical line is set as the address (4), and the write position of the 8th vertical line is set as the position. The address is 1 ,, the start position of the ninth wales is set to the address of 10, and the start write position of the 1st wales is set to the address of 12, and the write position of the U walt is started. The address is set to the position of 13, and the write position of the 12th vertical line is set to the address of "the position, and the write position of the 13th vertical line is set to the position of the address of 17," The start write position is set to the address of 19, the start position of the 15th traverse is set to the address of 21, and the write position of the 16th trajectory is set to the address of 2 In the position of 2, the writing position of the 17th waling is set as the position of the phantom, the writing position of the 18th ordinate is set to the position where the address is %, and the writing position of the first traverse is set as the address. For the position of 37, the start write position of the 2nd wales is set to the position of 39, the start write position of the 21st walt is set to the address of 40, and the write position of the 22nd walt is set as the start position. The address is the position of 〇, and the write position of the 23rd rowth is set to the position where the address is u, and the write position of the first trajectory is set to the position of the address 41. Fig. 24 is for DVB_S.2 The code length N specified by the specification is the LDPC code of the encoding rate of l62oo, and the number of vertical lines of the memory 31 and the address of the start writing position necessary for the vertical twisting interleaving are expressed in each modulation mode. If 1' is used as the modulation method, for example, QpSK is used. Therefore, in the case where the bit number t of the i symbol is 2 bits, according to Fig. 24, the memory 31 contains 2 wales of 2x1 bits in the course direction. , memory 16200/(2x1) bits in the wale direction. 135786.doc •60- 200937872 Then, in the 2 wales of memory 3 1 The first write position is set to the position of the address, and the write position of the second vertical line is set to the position where the address is 0. Since the multiple b is 2, and as a modulation method, for example, QpSK is used. Therefore, in the case where the number m of the symbol is 2 bits, according to Fig. 24, the memory 3^ contains 4 vertical lines of 2 X2 bits in the horizontal direction and 16200/ in the vertical direction. 2x2) Bits. Then, in the 4 wales of the memory 3 1 , the write bit of the 丨 丨 © © © © © © © ' ' ' ' ' ' ' ' ' ' ' ' ' ' 第 第 第 第 第 第 第 第 第 第 第 第For the position of 2, the start position of the 3rd rowth is set to the position where the address is 3, and the start write position of the 4th traverse is set to the position where the address is 3. Since the multiple b is 1, and the modulation method is, for example, 16QAM, if the number of bits of the 1-symbol is 4 bits, according to FIG. 24, the memory 31 contains 4×1 bits in the horizontal direction. A vertical line that memorizes 16200/(4 xl) bits in the wale direction. 〇 Then, among the four wales of memory 31, respectively! The write start position of the wales is set to the position where the address is 0. The start write position of the 2nd wales is set to the address of 2, and the write position of the 3rd ordinate is set to the position of the address of 3, * The start position of the wales is set to the position where the address is 3. Since the multiple b is 2, and the modulation method is, for example, 16QAM, the number of bits of the symbol is 1! "In the case of 4 bits, if the memory is based on the graph %, the memory system contains 4x2 in the horizontal direction. The eight vertical lines of the bit store 16200/(4x2) bits in the wale direction. Then, in the 8 wales of the 6 mnemonic body 3, the writing position of the 丨 丨 135 135 786.doc -61 - 200937872 is set as the address of the 〇, and the writing position of the 2nd ordinate is set. The address is the location of the 〇 'the third write start position is set to the address of 〇, the start position of the fourth traverse is set to the address of 1, the start position of the fifth trajectory The address is set to the position of 7, the start position of the sixth vertical line is set to the address of 20, and the write position of the seventh vertical line is set to the position of the address of 2 ' 'the beginning of the eighth vertical line The write location is set to the location of the address 21. Since the multiple b is 1, and the modulation method is, for example, 64qam, if the number of bits of the 1 symbol is 6 bits, 'If the memory 3 1 is stored in the horizontal direction, 6 X according to FIG. 24 6 vertical lines of 1 bit, memory 16200/(6 XI) bits in the longitudinal direction. Then, in the six wales of the memory 3 1 , the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address ' 3 The write bit at the beginning of the wales is set to the position where the address is 2, the start write position of the 4th rowth is set to the position where the address is 3, and the start write position of the 5th traverse is set to the position where the address is 7. The start position of the sixth vertical line is set to the position where the address is 7. Since the multiple b is 2, and the modulation method is, for example, 64QAM, the number of bits of the 1 symbol is „! is 6 bits, and according to FIG. 24, the memory 31 is stored in the horizontal direction to store 6×2 bits. The 12 vertical lines of the element store 16200/(6x2) bits in the longitudinal direction. Then, in the 12 vertical lines of the memory 31, the start writing position of the first walt is set as the address of the 〇, The write position of the second wales is set to the position of 〇, the write position of the third traverse is set to the position of 〇, and the write position of the fourth traverse is set to the position of address 2. , 5th vertical opening 135786.doc •62· 200937872 The initial writing position is set to the address of 2, the beginning of the 6th vertical writing position is set to the address of 2, the beginning of the 7th vertical line The position is set to the position where the address is 3'. The write position of the 8th vertical line is set to the position where the address is 3, and the start write position of the 9th vertical line is set to the position where the address is 3, and the first vertical line is The start write position is set to the address of 6, the start write position of the 11th vertical line is set to the address of the address 7, and the start write position of the 12th vertical line is set as the address is 7. Since the multiple b is 1 ' and the modulation method is, for example, 256qam, if the number of bits of the 1 symbol is 8 bits, according to Fig. 24, the memory 31 is included in the course. The direction stores 8 octets of 8x1 bits, and memorizes 16200/(8x1) bits in the wales direction. Then, among the 8 wales of the memory 31, the start write position of the 丨 丨 is set as the address. In the position of the 纵, the write position of the 2nd ordinate is set to the address of 〇 'the start position of the 3rd row is set as the address of 〇, and the write position of the 4th traverse is set as the address For the position of 1, the write position of the fifth wales is set to the position of the address 7, and the start of the sixth traverse is set to the position where the address ❿ is 20, and the write position of the seventh traverse is set as the start position. The address is 2〇, and the write position of the 8th ordinate is set to the address of 2丨. Since the multiple b is 1, and the modulation method is, for example, 1024qam, the number of bits of the 1 symbol is clamped. In the case of the element, according to FIG. 24, the memory 3 1 contains 10 vertical lines of 1 〇 x 1 bit in the horizontal direction, in the longitudinal direction. The memory is 16200/(10x1) bits. Then, in the memory 3 1 of 1 纵 纵, the write position of the first wales is set as the address of 〇, and the write position of the 2nd ordinate is started. The position where the address is 1 is 'the start position of the 3rd vertical line is set to the position where the address is 2, 135786.doc -63 - 200937872 The write position of the 4th vertical line is set to the position where the address is 2, The start position of the fifth wales is set to the position where the address is 3, the start write position of the sixth traverse is set to the position where the address is 3, and the start write position of the seventh traverse is set to the position of the address of 4. The write position of the 8th wales is set to the position where the address is 4, the start write position of the ninth wales is set to the address of 5, and the start write position of the 1st wales is set to the address of 7 position. Since the multiple b is 2, and the modulation method is, for example, 1〇24QAM, if the number of fingers of the 1st 70 is the i 〇 bit, the memory type body 31 is included in the course direction according to Fig. 24 It memorizes 20 vertical lines of 10X2 bits and memorizes 16200/(10x2) bits in the longitudinal direction. Then, in the 20 wales of the memory 3 1 , the start write position of the ith walt is set as the address of the 〇, and the start write position of the second row is set as the address of the ,, the third The start position of the wales is set to the position of 〇, the start position of the 4th rowth is set to the position where the address is 2, and the start write position of the ideographic trajectory is set to the position where the address is 2' 6 The starting position of the vertical line is set to ◎ the position of the address is 2, the writing position of the 7th vertical line is set to the position where the address is 2, and the writing position of the 8th vertical line is set to the position of the address of 2, The start position of the ninth wales is set to the position where the address is 5, the start write position of the first wales is set to the position of the address 5, and the start write position of the utitudinal line is set to the address of 5 Position, the start position of the 12th wales is set to the position of the address, the start position of the 13th traverse is set to the address of 5, and the start position of the 14th traverse is set to the address of 7 At the position, the write position of the 15th wales is set to the position of the address 7, the start position of the 16th wales is set to the position of the address 7, and the write position of the 17th ordinate is started. The address is set to the position of 7, the first write position of the 135786.doc 200937872 18 wales is set to the address of 8, the beginning of the 19th traverse is set to the address of 8, the 20th vertical The start of the line write position is set to the address of 1 〇. Since the multiple b is 1, and the modulation method is, for example, 4〇96qaM, when the number m of the 1-symbol is 丨2 bits, the memory 31 is included in the course direction according to FIG. 24 Memorize 2 wales of i2x i bits and remember 16200/( 12x1) bits in the wales. Then, in the two wales of the memory 3 1 , the write position of the first wales is set to the position of the address, and the write position of the second traverse is set to the address of the address of 0. The write position of the third vertical line is set to the position of the address, the write position of the fourth vertical line is set to the position of the address 2, and the write position of the fifth vertical line is set to the position of the address of 2. The write position of the sixth vertical line is set to the position where the address is 2, the start write position of the seventh vertical line is set to the position where the address is 3, and the start write position of the eighth vertical line is set to the address of 3 The start write position of the position 9th wales is set to the position where the address is 3, the start write bit q of the 1st vertical line is set to the position where the address is 6, and the start write position of the 11th vertical line is set as the address. For the position of 7, the start position of the second wales is set to the position of the address 7. Since the multiple b is 2, and the modulation method is, for example, 4〇96QAM, if the number of bits of the 1 symbol is mg12 bits, the memory 31 is stored in the course of the direction according to Fig. 24)) <2 The 24 vertical lines of the bit store 16200/(12x2) bits in the wale direction. Then, among the 24 wales of the memory 31, the start write position of the ith wales is set as the address of the 〇, and the start write position of the second traverse is set as the address of the ,, the third vertical The start of the write position is set to the address of 〇, 135786.doc 200937872 The start position of the 4th traverse is set to the address of 〇, and the write position of the 5th trajectory is set as the address. Position, the start position of the sixth vertical line is set to the position where the address is 0. 'The start position of the 7th vertical line is set to the address where the address is ''. The start position of the 8th vertical line is set as the address is 1 At the position, the start position of the ninth wales is set to the position where the address is 1, the start position of the 丨〇 丨〇 is set to the position where the address is 1, and the start of the utitudinal write position is set as the address. For the position of 2, the start position of the 12th wales is set to the position where the address is 2, the start write position of the 13th wales is set to the position where the address is 2, and the start of the utitudinal line is set to be the write position. The address of the address is 3, the write position of the 15th vertical line is set to the address of the address 7, and the start write position of the 16th vertical line is set to the position of the address of 9, The write position of the 17th wales is set to the position where the address is 9, the start position of the 18th wales is set to the position of the address 9, and the start of the 19th traverse is set to the position of the address of 10. The write position of the 2nd vertical line is set to the address of 10, the start write position of the 21st vertical line is set to the address of 1〇, and the start write position of the 22nd vertical line is set as the address is In the position of the 丨〇, the write position of the 23rd wales is set to the position of 1 ,, and the write position of the wales is set to the position of 1 1 . Next, the transmission processing performed by the transmitting apparatus u of Fig. 8 will be described with reference to the flowchart of Fig. 25. The LDPC encoding unit 21 supplies the target data to the step si〇i, encodes the target data into an LDPC code, and supplies the LDpc code to the bit interleaver 22'. The processing proceeds to step S102. The bit interleaver 22 is in step S102, and the LDPC code from the LDPC encoding unit 21 is subjected to bit interleaving, and the 135786.doc -66 - 200937872 LDPC code symbolized symbol is interleaved. The processing is supplied to the mapping unit %, and the processing proceeds to step S103. That is, in step S102, in the bit interleaver 22, the parity interleaver takes the LDPC code from the LDPC composing unit 21 as an object, and performs the same position.
錯,將該同位交錯後之LDPC碼供給至縱行扭轉交鈣 24。 S 縱行扭轉交錯器24係將來自同位交錯器232LDpc碼作 為對象,進行縱行扭轉交錯,並供給至解多工器25。 解多工器25係替換藉由縱行扭轉交錯器24予以縱行扭轉 交錯後之LDPC碼之碼位元,進行使替換後之碼位元成為 符元之符元位元(表示符元之位元)之替換處理。 於此,藉由解多工器25所進行之替換處理除可按照圖“ 及圖17所示之第丨至第4替換方式來進行以外,亦可按照分 配規則來進行。分配規則係用以將1^1)1>(:碼之碼位元分配 給表示符元之符元位元之規則,關於其詳細會於後面敘 述。 藉由解多工器25之替換處理所獲得之符元係從解多工器 25供給至映射部26。 映射部26係於步驟8103,將來自解多工器乃之符元映射 成正交調變部27所進行之正交調變之調變方式所決定之信 號點,並供給至正交調變部27 ’處理係前進至步驟sl〇4。 正交調變部27係於步驟S104,按照來自映射部%之信號 點,進行載波之正交調變,處理係前進至步驟sl〇5,發送 正交調變之結果所獲得之調變信號,並終了處理。 135786.doc -67- 200937872 此外’圖25之發送處理係重複於管線進行。 如以上,藉由進行同位交錯或縱行扭轉交錯,可提升將 LDPC碼之複數瑪位元作為1個符元發送之情 除或叢發失誤之財受性。 況下之對於抹 於此’圖8中係為了便於說明’個別地構成進行同位交 錯之區塊即同位交錯器23、與進行縱行扭轉 縱行扭轉交錯器24 ,但同位交錯器23與縱行扭轉交^器μ 亦可一體地構成。 ❹Wrong, the co-interleaved LDPC code is supplied to the longitudinal twisted calcium 24. The S-wound twisting interleaver 24 performs the wobble interleaving from the co-located interleaver 232LDpc code and supplies it to the demultiplexer 25. The demultiplexer 25 replaces the code bits of the LDPC code which are longitudinally twisted and interleaved by the wobble interleaver 24, and performs the symbol bit of the replaced code bit as a symbol (representing the symbol Replacement processing of bits). Here, the replacement processing by the demultiplexer 25 can be performed in accordance with the "the fourth to fourth alternatives shown in FIG. 17, and can also be performed according to the allocation rule. The allocation rule is used. The rule of assigning a code bit of 1^1)1> (: code to a symbol bit representing a symbol, which will be described later in detail. The symbol obtained by the replacement processing of the multiplexer 25 is obtained. The signal is supplied from the demultiplexer 25 to the mapping unit 26. The mapping unit 26 is in step 8103, and maps the symbols from the demultiplexer to the modulation method of the quadrature modulation by the quadrature modulation unit 27. The determined signal point is supplied to the quadrature modulation unit 27' processing unit and proceeds to step sl4. The quadrature modulation unit 27 performs the orthogonality of the carrier in accordance with the signal point from the mapping unit % in step S104. Modulation, the processing proceeds to step sl5, the modulated signal obtained by the result of the quadrature modulation is transmitted, and the processing is terminated. 135786.doc -67- 200937872 In addition, the transmission processing of FIG. 25 is repeated in the pipeline. As above, the LDPC can be improved by performing the co-interleaving or the longitudinal twisting interleaving. The complex number of bits is transmitted as a symbol or the financial error of the clumping error. In the case of this figure, in Figure 8, for the sake of convenience, the blocks that are co-located in the same way are co-located. The interleaver 23 and the whirling torsional whirling interleaver 24 are formed, but the in-situ interleaver 23 and the whirling torsion device μ may be integrally formed.
亦即,同位交錯與縱行扭轉交錯之任—均可藉由碼位元 對於記憶體之寫人及讀出來進行,可藉由將進行碼位元之 寫入之位⑽入位址)轉換為進行碼位元之讀出之位址(讀 出位址)之矩陣來表示。 因此’若預先求出乘算表示同位交錯之矩陣與表示縱行 扭轉交錯之矩陣所獲得之矩陣,則藉由利用該㈣轉換碼 位疋’可獲得進行同位交錯,並進—步將該同位交錯後之 LDPC碼予以縱行扭轉交錯後之結果。 而且’除同位交錯H23及縱行扭轉交錯器⑽外解多 工器25亦可一體地構成。 亦即’以解多工器25所進行之#換處理亦可藉由將記憶 LDPC喝之記憶體31之寫入位址,轉換為讀出位址之矩陣 來表不。 因此’若預先求出乘算表示同位交錯之矩陣、表示縱行 扭轉交錯之矩陣及表示替換處理之矩陣所獲得之矩陣,則 可藉由該矩陣總括進行同位交錯、縱行扭轉交錯及替換處 135786.doc •68· 200937872 理。 此外,關於同位交錯及縱行扭轉交錯,僅進行其中任一 方或雙方均不進行亦可。 接著,參考圖26至圖28,說明關於針對圖8之發送裝置 11所進行之計測錯誤率(bit error rate :位元錯誤率)之模 擬。 模擬係採用D/U為OdB之有顫振(flutter)之通訊道來進 行。 Ο 圖26係表示模擬所採用之通訊道之模型。 亦即,圖26A係表示模擬所採用之顫振之模型。 而且,圖26B係表示有圖26A之模型所表示之顫振之通 訊道之模型。 此外,於圖26B,Η表示圖26A之顫振之模型。而且,於 圖 26Β,Ν 表示 ICI(Inter Carrier Interference :載波間干 擾),於模擬中,以AWGN逼近其功率之期待值E[N2]。 圖27及圖28係表示模擬所獲得之錯誤率與顫振之都卜勒 〇 ¥ 頻率&之關係。 此外,圖27係表示調變方式為16QAM、編碼率(r)為 (3/4),替換方式為第1替換方式之情況下之錯誤率與都卜 勒頻率fd之關係。而且,圖28係表示調變方式為64QAM、 編碼率(r)為(5/6),替換方式為第1替換方式之情況下之錯 誤率與都卜勒頻率fd之關係。 進一步而言,於圖27及圖28,粗線係表示進行同位交 錯、縱行扭轉交錯及替換處理全部之情況下之錯誤率與都 I35786.doc -69- 200937872 卜勒頻率fd之關係,細線係表示僅進行同位交錯、縱行扭 轉交錯及替換處理中之替換處理之情況下之錯誤率與都卜 勒頻率fd之關係。 於圖27及圖28之任一圖,可知進行同位交錯、縱行扭轉 交錯及替換處理全部之情況係較僅進行替換處理之情況, 其錯誤率提升(變小)。 接著,進一步說明關於圖8之LDPC編碼部21。 如圖11所說明,於DVB-S.2之規格,規定有64800位元及 〇 16200位元之2種碼長N之LDPC碼。 然後,關於碼長N為64800位元之LDPC碼,規定有11個 編碼率 1/4、1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6、8/9 及9/10,關於碼長N為16200位元之LDPC碼,規定有10個 編碼率 1/4、1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6及 8/9(圖 11B)。 LDPC編碼部21係按照依每碼長N及每編碼率所準備之檢 查矩陣Η,藉由該類碼長N為64800位元或16200位元之各 ® 編碼率之LDPC碼進行編碼(失誤訂正編碼)。 圖29係表示圖8之LDPC編碼部21之結構例。 LDPC編碼部21係由編碼處理部601及記憶部602所構 成。 編碼處理部601係由編碼率設定部611、初始值表讀出部 612、檢查矩陣生成部613、資訊位元讀出部614、編碼同 位運算部615、及控制部616所構成,其進行供給至LDPC 編碼部2 1之對象資料之LDPC編碼,將其結果所獲得之 135786.doc -70- 200937872 LDPC碼供給至位元交錯器22(圖8)。 亦即’編碼率設定部611係根據例如操作者之操作等, 來設定LDPC碼之碼長N及編碼率。 初始值表讀出部612係從記憶部602,讀出對應於編碼率 設定部611所設定之碼長N及編碼率之後述之檢查矩陣初始 值表。 〇 檢查矩陣生成部613係根據初始值表讀出部612所讀出之 楝查矩陣初始值表’於行方向以每36〇行(巡迴構造之單位 之行數P)之週期,配置對應於根據編碼率設定部6!丨所設 疋之碼長N及編碼率之資訊長κ(=碼長N-同位長Μ)之資訊 矩陣HAil之要素’產生檢查矩陣η並儲存於記憶部6〇2。 資訊位元讀出部614係從供給至LDPC編碼部21之對象資 料,讀出(擷取)資訊長K份之資訊位元。 編碼同位運算部61 5係從記憶部602讀出檢査矩陣生成部 613所生成之檢查矩陣H,根據特定式算出對於資訊位元讀 出部614所讀出之資訊位元之同位位元來生成碼字(ldpc 碼)。 控制部616係控制構成編碼處理部6〇丨之各區塊。 於記憶部602,儲存有分別關於64800位元及16200位元 之2種碼長N之分別對應於圖n所示之複數編碼率之複數檢 查矩陣初始值表等。而且,記憶部602係暫時記憶編碼處 理部601之處理上所必要之資料。 圖30係說明圖29之LDPC編碼部21之處理之流程圖。 於步驟S201,編碼率設定部611係決定(設定)進行LDpc 135786.doc 71 200937872 編碼之碼長N及編碼率r。 於步驟S202,初始值表讀出部612係從記憶部6〇2,讀出 對應於藉由編碼率設定部611所決定之碼長N及編碼率『之 預先決定之檢査矩陣初始值表。 於步驟S203,檢查矩陣生成部613係利用初始值表讀出 部612從記憶部602所讀出之檢查矩陣初始值表,求出(生 成)藉由編碼率設定部611所決定之碼長N及編碼率[之 LDPC碼之檢查矩陣H,供給至記憶部6〇2並儲存。 © 於步驟S204,資訊位元讀出部614係從供給至LDPC編碼 部21之對象資料,讀出對應於藉由編碼率設定部611所決 疋之碼長N及編碼率r之資訊長K(=Nxr)之資訊位元,並且 從記憶部602讀出檢查矩陣生成部613所求出之檢查矩陣 Η,並供給至編碼同位運算部615。 於步驟S205 ’編碼同位運算部615係依次運算符合式(8) 之碼字C之同位位元。That is, the co-located interleaving and the directional intertwial interleaving can be performed by the code bit to write and read the memory, and can be converted by inputting the bit (10) into the address of the code bit. It is represented by a matrix of addresses (read addresses) from which the code bits are read. Therefore, if the matrix obtained by multiplying the matrix representing the co-located interlace and the matrix representing the wobble interleaving of the wales are obtained in advance, the co-located interleaving can be obtained by using the (four)-converted code bit 疋', and the co-located interleaving is performed in advance. The latter LDPC code is the result of the twisted interleaving. Further, the demultiplexer H23 and the longitudinal twist interleaver (10) external demultiplexer 25 may be integrally formed. That is, the #change process performed by the demultiplexer 25 can also be expressed by converting the write address of the memory 31 of the memory LDPC into a matrix of read addresses. Therefore, if a matrix representing the co-located interlace, a matrix representing the wobble interleave, and a matrix obtained by the matrix representing the replacement process are obtained in advance, the parity interleaving, the wobble interleaving, and the replacement can be performed by the matrix. 135786.doc •68· 200937872. Further, regarding the co-interlacing and the whirling twisting, only one or both of them may not be performed. Next, with reference to Figs. 26 to 28, an simulation of the measurement error rate (bit error rate) performed with respect to the transmitting apparatus 11 of Fig. 8 will be described. The analog system uses a communication channel with D/U for OdB with flutter. Ο Figure 26 shows the model of the communication channel used for the simulation. That is, Fig. 26A shows a model of the flutter used in the simulation. Further, Fig. 26B shows a model of the chattering channel of the flutter represented by the model of Fig. 26A. Further, in Fig. 26B, Η represents the model of the flutter of Fig. 26A. Further, in Fig. 26, Ν denotes ICI (Inter Carrier Interference), and in the simulation, the expected value E[N2] of the power is approximated by AWGN. Fig. 27 and Fig. 28 show the relationship between the error rate obtained by the simulation and the frequency of the flutter 〇 ¥ frequency & Further, Fig. 27 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 16QAM and the coding rate (r) is (3/4), and the alternative is the first alternative. Further, Fig. 28 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 64QAM and the coding rate (r) is (5/6), and the alternative is the first alternative. Further, in FIGS. 27 and 28, the thick line indicates the relationship between the error rate in the case of performing the co-located interleaving, the longitudinal torsional interleaving, and the replacement processing, and the relationship between the I35786.doc -69-200937872 Buhler frequency fd, thin line The relationship between the error rate and the Doppler frequency fd in the case of performing the interleave interleaving, the wobble interleave, and the replacement processing in the replacement process. As shown in any of Figs. 27 and 28, it can be seen that the case where all of the co-located interleaving, the whirling twist interleaving, and the replacement processing are performed is a case where only the replacement processing is performed, and the error rate is increased (smaller). Next, the LDPC encoding unit 21 of Fig. 8 will be further explained. As illustrated in Fig. 11, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64,800 bits and 〇16,200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and 8/9 (Fig. 11B). The LDPC encoding unit 21 encodes the LDPC code of each of the code lengths of 64800 bits or 16200 bits according to the check matrix 准备 prepared for each code length N and per coding rate (error correction) coding). FIG. 29 shows an example of the configuration of the LDPC encoding unit 21 of FIG. The LDPC encoding unit 21 is composed of an encoding processing unit 601 and a storage unit 602. The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, a coded parity calculating unit 615, and a control unit 616, and supplies them. The LDPC code of the target data to the LDPC encoding unit 21 is supplied to the bit interleaver 22 (Fig. 8) by the 135786.doc -70-200937872 LDPC code obtained as a result. In other words, the coding rate setting unit 611 sets the code length N and the coding rate of the LDPC code based on, for example, the operation of the operator. The initial value table reading unit 612 reads out the check matrix initial value table described later in accordance with the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602. The check matrix generation unit 613 is arranged in accordance with the cycle of the check matrix initial value table ' read in the initial direction table reading unit 612 every 36 lines (the number of rows P of the circuit structure). The check matrix η is generated based on the code length N set by the coding rate setting unit 6 and the information length κ (= code length N - parity length 之) of the information matrix HAil and stored in the memory unit 6 2. The information bit reading unit 614 reads (takes) the information bits of the information length K from the object information supplied to the LDPC encoding unit 21. The coding co-located operation unit 615 reads the inspection matrix H generated by the inspection matrix generation unit 613 from the storage unit 602, and calculates the parity bit of the information bit read by the information bit reading unit 614 based on the specific expression to generate a parity bit. Code word (ldpc code). The control unit 616 controls each block constituting the encoding processing unit 6A. The memory unit 602 stores a complex check matrix initial value table corresponding to the complex code rates shown in Fig. n for the two code lengths N of 64800 bits and 16200 bits, respectively. Further, the storage unit 602 temporarily stores the data necessary for the processing of the encoding processing unit 601. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21 of Fig. 29. In step S201, the coding rate setting unit 611 determines (sets) the code length N and the coding rate r to be coded by LDpc 135786.doc 71 200937872. In step S202, the initial value table reading unit 612 reads out a predetermined check matrix initial value table corresponding to the code length N and the coding rate determined by the coding rate setting unit 611 from the storage unit 6〇2. In step S203, the check matrix generation unit 613 obtains (generates) the code length N determined by the coding rate setting unit 611 by using the check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612. And the inspection matrix H of the LDPC code of the encoding rate is supplied to the memory unit 6〇2 and stored. In step S204, the information bit reading unit 614 reads the information length K corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611 from the target data supplied to the LDPC encoding unit 21. The information bit of (=Nxr) is read from the storage unit 602 by the check matrix Η obtained by the check matrix generation unit 613, and supplied to the coded parity calculation unit 615. In step S205, the coded co-located operation unit 615 sequentially calculates the parity bits of the code word C conforming to the equation (8).
HcT=〇 ❹ · · . (8) 於式(8) ’ c表示作為瑪字(LDPC碼)之列向量,CT表示列 向量c之轉置。 於此,如上述,作為LDPC碼(1碼字)之列向量〇中,以列 向量A表示資訊位元之部分,並且以列向量τ表示同位位 元之部分之情況下,列向量c可藉由作為資訊位元之列向 量A及作為同位位元之列向量T,並以式c=[a|T]來表示。 檢查矩陣Η及作為LDPC碼之列向量c=[A|T]必須符合式 135786.doc -72- 200937872HcT = 〇 · · · (8) where (8) ’ c denotes a column vector as a martensial (LDPC code), and CT denotes a transpose of the column vector c. Here, as described above, in the column vector LDP of the LDPC code (1 code word), the column vector A represents a portion of the information bit, and in the case where the column vector τ represents a portion of the parity bit, the column vector c can be It is represented by the column vector A as the information bit and the column vector T as the parity bit, and is represented by the formula c=[a|T]. Check matrix Η and column vector c=[A|T] as LDPC code must conform to 135786.doc -72- 200937872
HcT=0,作為構成符合該式HcT=0之列向量c=[A|T]之同位 位元之列向量T可藉由於檢查矩陣H=[HA|HT]之同位矩陣Ητ 成為圖10所示之階梯構造之情況下,從式HcT=0之行向量 HcT之第1列之要素,依序使各列之要素成為0而可逐次地 求出。 編碼同位運算部61 5若對於資訊位元A求出同位位元T, 則將藉由該資訊位元A及同位位元T所表示之碼字c=[A|T] 作為資訊位元A之L D P C編碼結果而輸出。 〇 此外,碼字c為64800位元或16200位元。 其後,於步驟8206,控制部616係判定是否終了[〇?(:編 碼。於步驟S206,判定不終了 LDPC編碼之情況下,亦即 例如尚有應予以LDPC編碼之對象資料之情況下,處理係 返回步驟S201,以下重複步驟S201至S206之處理。 而且,於步驟S206,判定終了 LDPC編碼之情況下,亦 即例如無應予以LDPC編碼之對象資料之情況下,LDPC編 碼部21係終了處理。 ® 如以上,準備有對應於各碼長N及各編碼率r之檢查矩陣 初始值表,LDPC編碼部21係將特定碼長N之特定編碼率r 之LDPC編碼,利用從對應於該特定碼長N及特定編碼率r 之檢查矩陣初始值表所產生之檢查矩陣Η來進行。 檢查矩陣初始值表係將檢查矩陣Η之對應於根據LDPC碼 (藉由檢查矩陣Η所定義之LDPC碼)之碼長N及編碼率r之資 訊長K之資訊矩陣HA(圖9)之1之要素之位置,以每360行 (巡迴構造之單位之行數P)表示之表,依各碼長N及各編碼 135786.doc -73- 200937872 率r之檢查矩陣Η逐一事先編製。 圖31至圖58係表示DVB-S.2之規格所規定之數個檢查矩 陣初始值表。 亦即,圖31係表示DVB-S.2之規格所規定之尉於碼長Ν 為16200位元之編碼率|>為2/3之檢查矩陣η之檢查矩陣初# 值表® 圖32至圖34係表示DVB-S.2之規格所規定之對於碼長Ν 為64800位元之編碼率r為2/3之檢查矩陣Η之檢查矩陣初始 ❹ 值表。 11 此外’圖33係接續於圖32之圖,圖34係接續於圊33之 圖。 圖35係表示DVB-S.2之規格所規定之對於碼長^為162〇〇 位元之編碼率r為3/4之檢查矩陣Η之檢查矩陣初始值表。 圖36至圖39係表示DVB-S.2之規格所規定之對於碼長Ν 為64800位元之編碼率r為3/4之檢查矩陣Η之檢查矩陣初始 值表》 ❹ 此外’圖37係接續於圖36之圖,圖38係接續於圖37之 圖。而且,圖39係接續於圖38之圖。 圖40係表示DVB-S.2之規格所規定之對於碼長Ν為16200 位元之編瑪率r為4/5之檢查矩陣Η之檢查矩陣初始值表。 圖41至圖44係表示DVB-S.2之規格所規定之對於碼長Ν 為64800位元之編碼率r為4/5之檢查矩陣Η之檢查矩陣初始 值表。 此外,圖42係接續於圖41之圖,圖43係接續於圖42之 135786.doc -74- 200937872 圖。而且,圖44係接續於圖43之圖。 圖45係表示DVb_s.2之規格所規定之對於碼長n為ι62〇〇 位元之編碼率r為5/6之檢查矩陣Η之檢查矩陣初始值表。 圖46至圖49係表示DVB-S.2之規格所規定之對於瑪長Ν 為64800位元之編碼率1*為5/6之檢查矩陣Η之檢查矩陣初始 值表。 此外,圖47係接續於圖46之圖,圖48係接續於圖47之 圖。而且,圖49係接續於圖48之圖。 ❹ 圖50係表示DVB-S.2之規格所規定之對於碼長Ν為16200 位元之編碼率Γ為8/9之檢查矩陣Η之檢查矩陣初始值表。 圖51至圖54係表示DVB-S.2之規格所規定之對於碼長Ν 為64800位元之編碼率!》為8/9之檢查矩陣Η之檢查矩陣初始 值表。 此外’圖52係接續於圖51之圊,圖53係接續於圖52之 圖。而且,圖54係接續於圖53之圖。 圖55至圖58係表示DVB-S.2之規格所規定之對於碼長Ν ® 為64800位元之編碼率r為9/10之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖56係接續於圖55之圖,圖57係接續於圖56之 圖。而且,圖58係接續於圖57之圖。 檢查矩陣生成部613(圖29)係利用檢查矩陣初始值表, 如以下求出檢查矩陣Η。 亦即,圖59係表示從檢查矩陣初始值表求出檢查矩陣η 之方法。 135786.doc -75- 200937872 此外,圖59之檢查矩陣初始值表係表示對於圖31所示之 DVB-S.2之規格所規定之碼長1<[為162〇〇位元之編碼率^為 2/3之檢查矩陣Η之檢查矩陣初始值表。 檢查矩陣初始值表係如上述,將對應於根據LDpc碼之 碼長N及編碼率r之資訊長艮之資訊矩陣Ha(圖9)之丨之要素 之位置,以每360行(巡迴構造之單位之行數p)表示之表, 於其第i列,檢查矩陣Η之第行之i之要素之列 鍊碼(檢查矩陣Η之第1列之列號碼設作〇之列號碼)僅排列 © 有該第1+36〇x(i-l)行之行所具有之行權重之數目。 於此,由於檢查矩陣Η之對應於同位長M之同位矩陣 Ητ(圖9)係如圖19所示決定,因此若根據檢查矩陣初始值 表’可求出檢查矩陣Η之對應於資訊長κ之資訊矩陣Ηα(圖 9) 〇 檢查矩陣初始值表之列數k+Ι係依資訊長Κ而不同。 於資訊長K與檢查矩陣初始值表之列數k+1間,式(9)之 關係成立。 冒 K=(k+l)x360 • · · (9) 於此,式(9)之360係圖20所說明之巡迴構造之單位之行 數P。 於圖59之檢查矩陣初始值表’從第1列至第3列排列有i 3 個數值’從第4列至第k+Ι列(於圖59為第30列)排列有3個 數值。HcT=0, as the column vector T constituting the parity bit of the column vector c=[A|T] conforming to the equation HcT=0 can be obtained by the parity matrix Ητ of the check matrix H=[HA|HT] In the case of the step structure shown in the figure, the elements of the first column of the row vector HcT of the equation HcT=0 are sequentially obtained by sequentially making the elements of the respective columns zero. When the coded co-located operation unit 61 5 finds the co-located bit T for the information bit A, the code word c=[A|T] represented by the information bit A and the co-located bit T is used as the information bit A. The LDPC coded result is output. 〇 In addition, the codeword c is 64800 bits or 16200 bits. Thereafter, in step 8206, the control unit 616 determines whether or not [??: encoding. In the case where it is determined in step S206 that the LDPC encoding is not finished, that is, for example, if there is still object data to be LDPC-encoded, The processing returns to step S201, and the processing of steps S201 to S206 is repeated as follows. Further, in the case where it is determined in step S206 that the LDPC encoding is ended, that is, for example, in the case where there is no object data to be LDPC-encoded, the LDPC encoding unit 21 is terminated. As described above, the inspection matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoding unit 21 encodes the LDPC encoding the specific coding rate r of the specific code length N, which corresponds to the The check matrix generated by the check matrix initial value table of the specific code length N and the specific coding rate r is performed. The check matrix initial value table checks the matrix Η corresponding to the LDPC code according to the LDPC code (by checking the matrix Η) The code length of the code N and the information of the code rate r. The position of the element of the information matrix HA (Fig. 9) 1 is expressed in units of 360 lines (the number of rows of the circuit of the tour structure), according to each code. Long N and each code 135786.doc -73- 200937872 The check matrix of rate r is prepared one by one. Fig. 31 to Fig. 58 show the table of initial values of several check matrices specified by the specifications of DVB-S.2. That is, Fig. 31 shows DVB. -S.2 specification specifies the code length Ν is 16200 bits of code rate|> is 2/3 check matrix η check matrix initial # Value table ® Figure 32 to Figure 34 shows DVB-S The specification of .2 is for the check matrix of the code length Ν 64800 bits, which is 2/3, and the check matrix initial check value table. 11 In addition, 'Fig. 33 is connected to Fig. 32, Fig. 34 The diagram is continued from Fig. 33. Fig. 35 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 162 〇〇 for the code length r of 3/4 as defined by the specification of DVB-S.2. Fig. 36 to Fig. 39 show the check matrix initial value table of the check matrix 编码 for the code length 64 64800 bits with a code length 为 of 3/4 as defined by the specification of DVB-S.2 ❹ In addition, 'Fig. 37 Figure 38 is a view continuing from Figure 37. Figure 39 is a view subsequent to Figure 38. Figure 40 shows the specification of DVB-S.2 for a code length of 16200. The bit rate r of the bit is the check matrix initial value table of the check matrix of 4/5. Fig. 41 to Fig. 44 show the coding rate for the code length 64 64800 bits specified by the specification of DVB-S.2. r is a check matrix initial value table of 4/5 check matrix. In addition, Fig. 42 is continued from Fig. 41, and Fig. 43 is continued from Fig. 42 135786.doc-74-200937872. Moreover, Fig. 44 is a view subsequent to Fig. 43. Fig. 45 is a table showing the check matrix initial value of the check matrix 编码 for the code rate r of i/62. Fig. 46 to Fig. 49 are diagrams showing the check matrix initial value table of the inspection matrix 编码 for the coding rate 1* of 5/6 of Ma ChangΝ, which is defined by the specification of DVB-S.2. Further, Fig. 47 is a view continuing from Fig. 46, and Fig. 48 is a view continuing from Fig. 47. Moreover, Fig. 49 is continued from Fig. 48. Figure 50 is a table showing the initial value of the check matrix of the check matrix 编码 with a code length 16 of 16200 bits and a code rate of 8/9 as defined by the specification of DVB-S.2. Fig. 51 to Fig. 54 are diagrams showing the initial value of the check matrix of the check matrix of 8/9 as defined by the specification of DVB-S.2 for the code rate 64 64800 bits. Further, Fig. 52 is continued from Fig. 51, and Fig. 53 is continued from Fig. 52. Moreover, Fig. 54 is continued from Fig. 53. Fig. 55 to Fig. 58 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length Ν ® 64800 bits with a code rate r of 9/10 as defined by the specification of DVB-S.2. Further, Fig. 56 is continued from Fig. 55, and Fig. 57 is continued from Fig. 56. Moreover, Fig. 58 is continued from Fig. 57. The inspection matrix generation unit 613 (FIG. 29) obtains the inspection matrix 如 by using the inspection matrix initial value table as follows. That is, Fig. 59 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. 135786.doc -75- 200937872 In addition, the check matrix initial value table of Fig. 59 indicates the code length 1 <[ 162 〇〇 bit code rate] specified for the specification of DVB-S.2 shown in Fig. 31 Check the matrix initial value table for the 2/3 check matrix. The check matrix initial value table is as described above, and corresponds to the position of the element after the information matrix Ha (Fig. 9) according to the code length N of the LDpc code and the information rate r, for every 360 lines (tour structure) The table of the number of rows of the unit p), in its column i, check the chain of the elements of the i-th row of the matrix ( (the number of the column in the first column of the inspection matrix is set as the column number) © The number of lines of the line that has the 1+36〇x(il) line. Here, since the parity matrix Ητ ( FIG. 9 ) corresponding to the parity M of the check matrix 决定 is determined as shown in FIG. 19 , if the check matrix initial value table ' can be obtained, the check matrix Η corresponds to the information length κ . The information matrix Ηα (Fig. 9) 〇 Check the matrix initial value table number k + Ι is different depending on the information length. The relationship of the equation (9) holds between the information length K and the number k+1 of the check matrix initial value table. K = (k + l) x 360 • (9) Here, 360 of the equation (9) is the number of rows P of the unit of the tour structure illustrated in Fig. 20. In the inspection matrix initial value table of Fig. 59, i 3 numerical values are arranged from the first column to the third column, and three values are arranged from the fourth column to the k+1th column (the 30th column in Fig. 59).
因此,從圖59之檢查矩陣初始值表所求出之檢查矩陣H 135786.doc •76· 200937872 之行權重係從第1行至第1+36〇x(3-1)-1行為13,從第 l+36〇x(3-l)行至第K行為3。 圖59之檢查矩陣初始值表之第1列為0 ' 2084、1613、 1548、1286、1460、3196、4297、2481、3369、3451、 4620、2622,此係表示於檢查矩陣Η之第1行,列號碼為 0 、 2084 、 1613 、 1548 、 1286 、 1460 、 3196 、 4297 、 2481、3369、3451、4620、2622之列之要素為ι(且其他要 素為0)。 Ο 而且,圖59之檢查矩陣初始值表之第2列為1、122、 1516、3448、2880、1407、1847、3799、3529、373、 971、4358、3 108 ’此係表示於檢查矩陣Η之第361(=1 + 36〇x(2 — 1))行,列號碼為 1、122、1 5 16、3448、2880、 1407、1847、3799、3529、373、971、4358、3108之列之 要素為1。 如以上’檢查矩陣初始值表係將檢查矩陣Η之資訊矩陣 Ηα之1之要素之位置以每360行表示。 檢查矩陣Η之第1+360x(i-l)行以外之行,亦即從第 2+36〇x(i-l)行至第36〇xi行之各行係將藉由檢查矩陣初始 值表所決定之第l + 36〇x(i-l)行之1之要素,按照同位長μ 往下方向(行之下方向)週期性地予以循環移位而配置。 亦即’例如第2+36〇χ(Μ)行係將第卜“⑽⑴丨)行往下方 向僅循環移位M/360(=q) ’接著之第係將第 l+36〇x(i-l)行往下方向僅循環移位2xM/36〇(=2xq)(將第 2+3 60><〇1)行往下方向僅循環移位]^/36〇(=(1))。 135786.doc •77- 200937872 現在,若將檢查矩陣初始值表之第丨列(從上算起第丨個) 之第j行(左起第j個)之數值表示作hij,並且將檢查矩陣Η 之第w行之第j個之i之要素之列號碼表示作^^·〗,則檢查矩 陣Η之第l+3 6〇x(i-l)行以外之行之第w行之1之要素之列號 碼11叫可由式(1〇)求出。Therefore, the check weight of the check matrix H 135786.doc • 76· 200937872 obtained from the check matrix initial value table of Fig. 59 is from the 1st line to the 1+36〇x(3-1)-1 behavior 13, From the l+36〇x(3-l) line to the Kth act 3. The first column of the check matrix initial value table of Fig. 59 is 0 ' 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the check matrix Η The elements whose column numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are ι (and other elements are 0). Ο Moreover, the second column of the check matrix initial value table of Fig. 59 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3 108 'This is shown in the inspection matrixΗ The 361th (=1 + 36〇x(2 - 1)) row, column number is 1, 122, 1 5 16, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108 The factor is 1. As shown above, the inspection matrix initial value table will check the position of the element of the information matrix Ηα of the matrix 以 in every 360 rows. Check the line other than the 1+360x(il) line of the matrix ,, that is, the line from the 2+36〇x(il) line to the 36th 〇 line will be determined by checking the matrix initial value table. The element of 1 + 36 〇 x (il) line is cyclically shifted according to the same length μ in the downward direction (downward direction of the line). That is to say, 'for example, the 2+36〇χ(Μ) line will only shift the head of the ((10)(1)丨) row downwards by M/360(=q) 'then the first line will be the l+36〇x ( Il) The line is only cyclically shifted by 2xM/36〇(=2xq) in the downward direction (the second 2+3 60><〇1) line is rotated only downwards]^/36〇(=(1)) 135786.doc •77- 200937872 Now, if the value of the jth row (jth from the left) of the third column (the first one from the top) of the check matrix initial value table is expressed as hij, and will be checked The column number of the element of the jth i of the wth row of the matrix 表示 is expressed as ^^·, and then the 1st line of the line other than the l+3 6〇x(il) line of the matrix 检查 is checked. The number 11 of the element number can be obtained by the formula (1〇).
Hw.j=mod{hi)j+ mod((w-l),P)xq,M} ...(10) 於此’ mod(x,y)係意味以y除以x後之餘數。 而且,p為上述巡迴構造之單位之行數,例如於DVB_ © S.2之規格係如上述為360。進一步而言,q係藉由以巡迴 構造之單位之行數P(=360)除算同位長M所獲得之值 M/360。 檢查矩陣生成部613(圖29)係藉由檢查矩陣初始值表, 來特定出檢查矩陣Η之第l+36〇x(M)行之1之要素之列號 碼0 進一步而言,檢查矩陣生成部613(圊29)係按照式(1〇), 求出檢查矩陣H之第1+36〇x(i-l)行以外之行之第评行之1之 要素之列號碼Hw-j ’並生成將藉由以上所獲得之列號瑪之 要素作為1之檢查矩陣Η。 然而’於下一代之CATV數位播放之規格之dvB-C. 2, 預估採用例如2/3至9/10等之高編碼率及1〇24qAm或 4096QAM等信號點多之調變方式。 於高編碼率或信號點多之調變方式,一般由於通訊道 13(圖7)對於錯誤之耐受性會降低,因此宜施以用以提升對 於錯誤之耐受性之對策。 135786.doc •78· 200937872 作為用以提升對於錯誤之耐受性之對策,例如有解多工 器25(圖8)所進行之替換處理。 於替換處理,作為替換LDPC碼之碼位元之替換方式有 例如上述第1至第4替換方式,但要求提案對於錯誤之耐受 性較包含該等第1至第4替換方式之既已提案之方式更提升 之方式。 因此,於解多工器25(圖8),如圖25所說明,可按照分 配規則來進行替換處理。 〇 以下,說明關於按照分配規則之替換處理,在其之前先 說明關於藉由既已提案之替換方式(以下亦稱為現行方式) 所進行之替換處理。 參考圖60及圖61,說明關於在解多工器25假設以現行方 式進行替換處理之情況下之該替換處理。 圖60係表示LDPC碼是碼長N為64800位元、編碼率為3/5 之LDPC碼之情況下之現行方式之替換處理之一例。 亦即,圖60A係表示LDPC碼是碼長N為64800位元、編 ® 碼率為3/5之LDPC碼,進一步調變方式為16QAM,倍數b 為2之情況下之現行方式之替換處理之一例。 調變方式為16QAM之情況下,碼位元之4(=m)位元係作 為1個符元而映射成16QAM所決定之16個信號點中之任一 個。 進一步而言,碼長N為64800位元,倍數b為2之情況下, 解多工器25之記憶體3 1(圖16、圖17)係含有於橫列方向記 憶4x2(=mb)位元之8個縱行,於縱行方向記憶64800/(4x2) 135786.doc -79- 200937872 位元。 於解多工器25,LDPC碼之碼位元寫入於記憶體3 1之縱 行方向,若64800位元之碼位元(1碼字)之寫入終了,則寫 入於記憶體31之碼位元係於橫列方向,以4x2(=mb)位元單 位讀出,並供給至替換部32(圖16、圖17)。 替換部32係以將讀出自記憶體31之4x2(=mb)位元之碼位 元 ,例如圖 60A所示分配給連續 2( = b) 個符元之4x2(=mb)位元之符元位元yG,yi,y2,y3,y4,y5,y6,y7i Ο 方式,替換4x2(=mb)位元之碼位元b〇至b7。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y7, 將碼位元b 1分配給符元位元y 1, 將碼位元b2分配給符元位元y4, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元ys, 將碼位元b5分配給符元位元y3, 將碼位元b6分配給符元位元y6, 將碼位元b7分配給符元位元y〇, 而進行替換。 圖60B係表示LDPC碼是碼長N為64800位元、編碼率為 3/5之LDPC碼,進一步調變方式為64QAM,倍數b為2之情 況下之現行方式之替換處理之一例。 調變方式為64QAM之情況下,碼位元之6(=m)位元係作 為1個符元而映射成64QAM所決定之64個信號點中之任一 135786.doc -80. 200937872 個0 解多工^ 瑪長NA 648G(H^,倍數之情況下, 憶6斧,;之記憶體31(圖16、圖17)係含有於橫列方向記 位元 凡之12個縱行’於縱行方向記憶64800/㈣) ❹Hw.j=mod{hi)j+ mod((w-l), P)xq, M} (10) where 'mod(x, y) means the remainder after dividing y by x. Further, p is the number of rows of the above-described tour structure, and the specification of DVB_© S.2 is, for example, 360 as described above. Further, q is a value M/360 obtained by dividing the co-located length M by the number of rows P (= 360) of the unit of the tour structure. The check matrix generation unit 613 (FIG. 29) specifies the column number 0 of the element of the 1st + 36 〇 x (M) line of the check matrix 藉 by checking the matrix initial value table. Further, the check matrix generation The part 613 (圊29) obtains the column number Hw-j ' of the element 1 of the first row of the line other than the 1+36〇x(il) line of the inspection matrix H according to the equation (1〇) and generates The element of the column number obtained by the above is taken as the inspection matrix 1 of 1. However, dvB-C. 2, which is a specification for the next-generation CATV digital broadcast, is estimated to have a high coding rate of, for example, 2/3 to 9/10 and a modulation method such as 1〇24qAm or 4096QAM. In the case of a high coding rate or a multi-signal modulation method, generally, the communication path 13 (Fig. 7) is less tolerant to errors, and therefore countermeasures for improving the tolerance to errors should be applied. 135786.doc •78· 200937872 As a countermeasure to improve the tolerance to errors, for example, the replacement processing by the multiplexer 25 (Fig. 8). In the replacement process, as an alternative to replacing the code bit of the LDPC code, for example, the above-described first to fourth alternatives are provided, but the proposal is required to be more resistant to errors than the first to fourth alternatives. The way to improve it. Therefore, in the demultiplexer 25 (Fig. 8), as illustrated in Fig. 25, the replacement processing can be performed in accordance with the allocation rule. 〇 Hereinafter, the replacement processing according to the distribution rule will be described, and the replacement processing by the alternative method (hereinafter also referred to as the current method) which has been proposed will be described before. Referring to Fig. 60 and Fig. 61, the replacement processing in the case where the demultiplexer 25 assumes that the replacement processing is performed in the current manner will be described. Fig. 60 is a diagram showing an example of replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. That is, FIG. 60A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a code rate of 3/5, and a further modulation method is 16QAM, and the multiple b is 2, and the current mode is replaced. One example. In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the 16 signal points determined by 16QAM as one symbol. Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 3 1 of the multiplexer 25 (FIG. 16, FIG. 17) contains 4x2 (= mb) bits in the horizontal direction. 8 vertical lines of the Yuan, memory 64800/(4x2) 135786.doc -79- 200937872 bits in the longitudinal direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is configured to assign a code bit read from a 4x2 (= mb) bit of the memory 31, for example, as shown in Fig. 60A to a 4x2 (= mb) bit of 2 consecutive (= b) symbols. The meta-bit yG, yi, y2, y3, y4, y5, y6, y7i Ο mode replaces the code bits b〇 to b7 of 4x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol bit y4. The code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit ys, the code bit b5 is assigned to the symbol bit y3, and the code bit b6 is assigned to the symbol bit Y6, the code bit b7 is assigned to the symbol bit y〇, and is replaced. Fig. 60B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped as one symbol to any of the 64 signal points determined by 64QAM. 135786.doc -80. 200937872 0 Solution multiplex ^ Ma Chang NA 648G (H ^, in the case of multiples, recall 6 axe; memory 31 (Figure 16, 17) is contained in the horizontal direction of the record of the 12 vertical lines of the ' Longitudinal direction memory 64800/(4)) ❹
1多m5,LDPC碼之碼位元寫入於記憶體31之縱 叮方向’若64_位元之瑪位元(1碼字)之寫入終了,則寫 入於記憶體31之碼位元係於橫列方向,以6x2(=mb)位元單 位讀出,並供給至替換部32(圖16、圖17)。 替換部32係以將讀出自記憶體以的卜响位元之碼位 元 b〇,b 丨,匕2,1)3,1)4,1)5,1)6,137,1)8,1)9,1)丨0山11,例如圖6〇3所示分配 給連續2(=b)個符元之6x2(=mb)位元之符元位元 丫〇’71,丫2’又3’又4,丫5,丫6,丫7,丫8,丫9,71〇,丫"之方式,替換6><2(=1^) 位元之碼位元至b 1丨。 亦即,替換部32係分別 將碼位元bG分配給符元位元y,丨, 將瑪位元b 1分配給符元位元y7, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y丨0, 將碼位元b4分配給符元位元y6, 將碼位元b 5分配給符元位元y 2, 將碼位元b6分配給符元位元y9, 將碼位元b7分配給符元位元y5, 將碼位元b8分配給符元位元y〗, 135786.doc -81 · 200937872 將碼位元t>9分配給符元位元y8, 將瑪位元b〗〇分配給符元位元y *, 將碼位元bn分配給符元位元”, 而進行替換。 圖60C係表示LDPC碼是碼長n為64800位元、編碼率為 3/5之LDPC碼’進一步調變方式為256QAM,倍數b為2之 情況下之現行方式之替換處理之一例。 調變方式為256QAM之情況下,碼位元之8(=m)位元係作 © 為1個符7°而映射成256QAM所決定之256個信號點中之任 一個。 進步而言,碼長N為64800位元,倍數b為2之情況下, 解多工器25之記憶體31(圖16、圖17)係含有於橫列方向記 隐8x2(-mb)位元之16個縱行,於縱行方向記憶648〇〇/(8><2) 位元。 —於解多工器25,LDPC碼之碼位元寫入於記憶體31之縱 ◎ 行方向,若64800位元之碼位元(〗碼字)之寫入終了,則寫 入於記憶體31之碼位元係於橫列方向,以8x2(=mb)位元單 位讀出,並供給至替換部32(圖16、圖17)。 替換部32係以將讀出自記憶體3128><2(==mb)位元之碼位 _ o’bi’bs’bhbhbs’be’b^’bs’bs’bw’bH’b^babAb”,例如 圖6〇c所示分配給連續2(=b)個符元之8x2(:=mb)位元之符元 位疋 y〇’y】,y2,y3,y4,y5,y6,y7,y8,y9,y】0,y",yi2,yi3,yi4,yi5t* 式’替換8x2(=mb)位元之碼位元bG至b15。 亦即,替換部32係分別 135786.doc •82· 200937872 將碼位元b〇分配給符元位元y丨5, 將碼位元b !分配給符元位元y〗, 將瑪位元t>2分配給符元位元y〗3, 將碼位元t>3分配給符元位元y3, 將碼位元t>4分配給符元位元y8, 將碼位元b5分配給符元位元y n ’ 將碼位元分配給符元位元y9, 將碼位元b7分配給符元位元y5,More than 1 m5, the code bit of the LDPC code is written in the vertical direction of the memory 31. If the writing of the 64-bit mbit (1 code word) is finished, the code bit written in the memory 31 is written. The element system is read out in the horizontal direction, in units of 6x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is a code bit b〇, b 丨, 匕 2, 1) 3, 1) 4, 1) 5, 1) 6, 137, 1) 8 which will be read from the memory. , 1) 9, 1) 丨 0 mountain 11, for example, as shown in Fig. 6〇3, the symbol of the 6x2 (=mb) bits of consecutive 2 (=b) symbols 丫〇 '71, 丫 2 '3' and 4, 丫5, 丫6, 丫7, 丫8, 丫9,71〇, 丫" way, replace 6><2(=1^) bits of code bits to b 1丨. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y, respectively, and assigns the m-bit b 1 to the symbol bit y7 and the code bit b2 to the symbol bit y3. The code bit b3 is assigned to the symbol bit y丨0, the code bit b4 is assigned to the symbol bit y6, the code bit b 5 is assigned to the symbol bit y 2 , and the code bit b6 is assigned to The symbol bit y9 assigns the code bit b7 to the symbol bit y5, and the code bit b8 to the symbol bit y, 135786.doc -81 · 200937872 assigns the code bit t>9 to the symbol The bit y8 assigns the megabyte b to the symbol y*, and assigns the Byte bn to the symbol ”, and replaces it. Figure 60C shows that the LDPC code has a code length n of 64,800. An example of the replacement processing of the current mode in the case where the LDPC code of the bit rate and the coding rate is 3/5 is further modulated by 256QAM and the multiple b is 2. When the modulation mode is 256QAM, the code bit is 8 The (=m) bit system is mapped to one of the 256 signal points determined by 256QAM for one character 7°. In the case of progress, the code length N is 64800 bits, and the multiple b is 2. , solution multiplexer 25 The memory 31 (Fig. 16, Fig. 17) contains 16 vertical lines of 8x2 (-mb) bits in the horizontal direction, and stores 648 〇〇 / (8 >< 2) bits in the wale direction. - In the multiplexer 25, the code bit of the LDPC code is written in the vertical direction of the memory 31, and if the writing of the 64800 bit code bit (the code word) is finished, it is written in the memory. The code bits of 31 are read in the horizontal direction, read in 8x2 (= mb) bit units, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is to be read from the memory 3128><; 2 (== mb) bit code _ o'bi'bs'bhbhbs'be'b^'bs'bs'bw'bH'b^babAb", for example, as shown in Figure 6〇c for consecutive 2 (=b) The symbol of the 8x2 (:=mb) bit of the symbol 疋y〇'y], y2, y3, y4, y5, y6, y7, y8, y9, y] 0, y", The yi2, yi3, yi4, yi5t* type replaces the code bits bG to b15 of the 8x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y丨5, respectively, and assigns the code bit b! to the symbol bit y, respectively, to assign the m-bit to the symbol bit y丨5, respectively. t > 2 is assigned to the symbol bit y 〗 3, the code bit element t > 3 is assigned to the symbol bit y3, the code bit element t > 4 is assigned to the symbol bit y8, and the code bit b5 is assigned to The symbol bit yn ' is assigned to the symbol bit y9, and the code bit b7 is assigned to the symbol bit y5.
將碼位元b8分配給符元位元y1(), 將碼位元b9分配給符元位元y6, 將碼位元bi〇分配給符元位元y4, 將碼位元b丨〗分配給符元位元y 7, 將瑪位元b 12分配給符元位元y 12, 將碼位元b 13分配給符元位元y 2, 將碼位元b 14分配給符元位元y 14, 將碼位元b 15分配給符元位元y〇, 而進行替換。 圖61係表示LDPC碼是碼長N為16200位元、編碼率為3/5 之LDPC碼之情況下之現行方式之替換處理之一例。 亦即,圖61A係表示LDPC碼是碼長N為16200位元、編 碼率為3/5之LDPC碼’進一步調變方式為16qam,倍數b 為2之情況下之現行方式之替換處理之一例。 調變方式為16QAM之情況下,碼位元之4(=m)位元係作 為1個符元而映射成16QAM所決定之個信號點中之任一 135786.doc •83· 200937872 個。 進—步而言,碼長N為16200位元,倍數bg2之情況下, 解多工器25之記憶體31(圖16、圖17)係含有於橫列方向記 憶4x2(=mb)位元之8個縱行,於縱行方向記憶ΐ62〇〇/(4χ2) 位元。 "於解多工器25,LDPC碼之碼位元寫入於記憶體31之縱 行方向,若16200位元之碼位元(1碼字)之寫入終了,則寫 入於記憶體31之碼位元係於橫列方向,以4x2(=mb)位元單 ® 位讀出,並供給至替換部32(圖16、圖17)。 替換部32係以將讀出自記憶體31之4><2(=1111))位元之碼位 元b〇,b丨,1^2,1)3,1)4,135,1)6,1)7,例如圖61八所示分配給連續2(=1)) 個符元之4x2(=mb)位元之符元位元yG,yi,y2,y3,y4,y5,y6,y< 方式,替換4x2(=mb)位元之碼位元b〇至卜。 亦即,替換部32係與上述圖60A之情況相同,進行將碼 仅元bG至by分配給符元位元7。至77之替換。 φ 圖61B係表示LDPC碼是碼長162〇〇位元、編碼率為 3/5之LDPC碼,進一步調變方式為64QAM,倍數ba2之情 況下之現行方式之替換處理之一例。 調變方式為64QAM之情況下,碼位元之6(=m)位元係作 為1個符元而映射成64QAM所決定之64個信號點中之任一 個。 進一步而言,碼長N為16200位元,倍數b為2之情況下, 解多工器25之記憶體31(圖16、圖17)係含有於橫列方向記 憶6x2(=mb)位元之12個縱行,於縱行方向記憶162〇〇/(6χ2) 135786.doc • 84 - 200937872 位元》 "於解多卫器25,LDPC碼之碼位元寫人於記憶體31之縱 行方向,若162〇〇位元之碼位元〇瑪字)之寫人终了,則寫 ;"己隐體3 1之碼位元係於橫列方向以位元單 位讀出,並供給至替換部32(圖16、圖17卜 替換部32係以將冑出自記憶體31之6><2(=1^)位元之碼位 _ ,例如圖 61B所示分配 給連續2(’個符元之“2(=叫位元之符元位元 © y〇’yi’y2’y3’y4,y5,yG7,y8,y9,y1〇,yil 之方式,替換 6x2(=mb) 位凡之碼位元bG至bu。 亦即,替㈣32係與上^6GB之情況相同,進行將碼 位兀、至匕,分配給符元位元y。至之替換。 圖61C係表示LDPC碼是碼長_62〇〇位元編碼率為 3/5之LDPC碼,進—步調變方式為256_,倍數⑷之 情況下之現行方式之替換處理之一例。 G广方式為256QAM之情況下,碼位元之位元係作 ,,、、1個符元而映射成256QAM所決定之256個信號點中之任 芡而言,碼長N為 16200位元,倍數b*!之情況下, =多工器25之記憶體31(@16、圖17)係含有於橫列方向記 :::(=,位元之8個縱行,於縱行方向記憶⑽。·】) 多工器25,LDPC碼之碼位元寫人於記憶㈣之縱 仃向’若⑹00位元之碼位元〇碼字)之寫入終了,則寫 I35786.doc -85- 200937872 入於記憶體3 1之碼位元係於橫列方向,以8 x 1 (=mb)位元單 位讀出’並供給至替換部32(圖16、圖17)。 替換部32係以將讀出自記憶體31之8x1 (=mb)位元之碼位 元boAbbhbhbobhl^,!^,例如圖61C所示分配給l(=b)個符 元之8xl(=mb)位元之符元位元丫〇,71,丫2,丫3,丫4,)^5,丫6,77之方 式’替換8 X1 (=mb)位元之碼位元b〇至b7。 亦即,替換部32係分別 將崎位元b〇分配給符元位元y7, Ο 將碼位元b〗分配給符元位元y3, 將碼位元b2分配給符元位元yi, 將碼位元b3分配給符元位元y 5, 將碼位元t>4分配給符元位元y2, 將碼位元b5分配給符元位元y6, 將碼位元1)6分配給符元位元y4, 將碼位元b7分配給符元位元y〇, 而進行替換。 〇 接著’說明關於按照分配規則之替換處理(以下亦稱為 採新替換方式之替換處理)。 圖62至圖64係說明新替換方式之圖。 於新替換方式,解多工器25之替換部32係按照事先決定 之分配規則來進行mb位元之碼位元之替換。 分配規則係用以將LDPC碼之碼位元分配給符元位元之 規則。於分配規則規定有:碼位元之碼位元群組、與分配 該碼位元群組之碼位元之符元位元之符元位元群組之組合 135786.doc -86 - 200937872 即群組集合;及該群組集合之碼位元群組、及符元位元群 組刀別之碼位兀及符元位元之位元數(以下亦稱為群組位 元數)。 於此,碼位元係如上述,於錯誤概率有差別,符元位元 亦於錯誤概率有差別。碼位元群組係根據錯誤概率來群組 區分碼位元之群組,符元位元群組係根據錯誤概率來群組 區分符元位元之群組。 圖62係表示LDPC碼是碼長>!為162〇〇位元、編碼率為2/3 ® 之1〇1>(:碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之1〇xl(==mb)位元之碼位 兀•係根據錯誤概率之差別,如圖62A所示可群組區分為4個 碼位元群組〇131,0匕2,〇1)3,〇134。 於此,碼位元群組Gbi係其下標i越小,屬於該碼位元群 組Gbj之碼位元之錯誤概率越良好(越小)之群組。 於圖62A,分別而言,碼位元群組Gbi係碼位元%所屬, ® 碼位元群組Gbz係碼位元1?1,1?2,153,1)4,135所屬,碼位元群組 Gbs係碼位元W所屬’碼位元群組Gh係碼位 屬。 調變方式為1024QAM,倍數b為1之情況下,1〇xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖62B所示可 群組區分為5個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5。 於此’符元位元群組Gyi係與碼位元群組相同,其下標i 越小’属於該符元位元群組Gy i之符元位元之錯誤概率越 135786.doc •87. 200937872 良好之群組。 於圖62B,分別而言,符元位元群組^…係符元位元 所屬,符元位元群組Gyz係符元位元乃七所屬,符元位元 群組Gy;係符元位元所屬,符元位元群組Gy4係符元位 元y6,y?所屬,符元位元群組Gys係符元位元78,丫9所屬。 圖63係表示LDPC碼是碼長N*162〇〇位元、編碼率為2/3 之LDPC碼,進一步調變方式為1〇24QAM ,倍數^^為i之情 況下之分配規則。 於圖63之分配規則,規定碼位元群組Gbl與符元位元群 組Gys之組合作為1個群組集合。然後,該群組集合之群組 位元數規定為1位元。 於此’以下將群組集合及其群組位元數一併稱為群組集 合資訊。然後,例如將碼位元群組Gbl與符元位元群組Gy5 之群組集合、及該群組集合之群組位元數即1位元,記載 為群組集合資訊(Gb^Gy^l) » 於圖63之分配規則,除群組集合資訊以外, 亦規定有群組集合資訊(Gb2,Gy丨,2),(Gb2,Gy2,2),(Gb2,Gy3,l), (Gb3,Gy4,l),(Gb4,Gy3,l),(Gb4,Gy4,l),(Gb4,Gy5,l)。 例如群組集合資訊(〇1?1,〇75,1)係意味將屬於碼位元群組 Gb!之碼位元之1位元,分配給屬於符元位元群組Gy〗之符 元位元之1位元。 因此’於圖63之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l) ’將錯誤概率第1良好之 瑪位元群組Gb!之碼位元之1位元,分配給錯誤概率第5良 135786.doc • 88 - 200937872 好(最差)之符元位元群組Gys之符元位元之1位元; 根據群組集合資訊(Gb^GyiJ),將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元,分配給錯誤概率第1良 好之符元位元群組Gyi之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 拫據群組集合資訊(Gb2,Gy3,l),將錯誤概率第2良好之 © 碼位元群組Gt>2之碼位元之1位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之1位元; 根據群組集合資訊(Gb^Ghj),將錯誤概率第3良好之 碼位元群組Gt>3之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 根據群組集合資訊(Gb>4,Gy3,l),將錯誤概率第4良好之 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第3良 好之符元位元群組之符元位元之1位元; 〇 根據群組集合資訊(Gt>4,Gy4,1),將錯誤概率第4良好之 碼位元群組Gin之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之丨位元; 及根據群組集合資訊,將錯誤概率第4良好 之碼位元群組Gb>4之瑪位元之1位元,分配給錯誤概率第5 良好之符元位元群組Gy5之符元位元之1位元。 如上述,碼位元群組係根據錯誤概率來群組區分碼位元 之群組,符元位元群組係根據錯誤概率來群組區分符元位 135786.doc -89- 200937872 元之群組。因此,分配規則亦可謂規定碼位元之錯誤概 率、與分配該碼位元之符元位元之錯誤概率之組合。 如此,規定碼位元之錯誤概率、與分配該碼位元之符元 位元之錯誤概率之組合之分配規則係藉由例如計測BER之 模擬等,決定為改善對於錯誤之耐受性(對於雜訊之耐受 性)。 此外,即使於同一符元位元群組之位元中變更某碼位元 群組之碼位元之分配去處,(幾乎)不會影響對於錯誤之耐 ❹ 受性。 因此,為了提升對於錯誤之耐受性,規定最縮小 BER(Bit Error Rate :位元錯誤率)之群組集合資訊,亦即 規定碼位元之碼位元群組與分配該碼位元群組之碼位元之 符元位元之符元位元群組之組合(群組集合)、該群組集合 之碼位元群組及符元位元群組分別之碼位元、及符元位元 之位元數(群組位元數),作為分配規則,按照該分配規 則,將碼位元分配給符元位元以進行碼位元之替換即可。 ® 其中,按照分配規則,將何個碼位元分配給何個符元之 具體分配方式,必須於發送裝置11及接收裝置12(圖7)間事 先決定。 圖64係表示按照圖63之分配規則之碼位元之替換例。 亦即,圖64A係表示LDPC碼是碼長N為16200位元、編 碼率為2/3之LDPC碼,進一步調變方式為1024QAM,倍數 b為1之情況下之按照圖63之分配規則之碼位元之替換之第 1例。 135786.doc -90- 200937872 LDPC碼是碼長N為16200位元、編碼率為2/3iLDpc 碼,進一步調變方式為1024QAM、倍數之情況下,於 解多工器25,於縱行方向X橫列方向為(162〇〇/(ι〇χΐ))χ(ι〇χΐ) 位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係按照圖63之分配規則,將讀出自記憶體3丨之 l〇xl(=mb)位元之碼位元bQ至h,例如圖64A所示分配給 © l(=b)個符元之1〇xl(=mb)位元之符元位元…至乃,以替換 l〇xl(=mb)位元之碼位元bQ至b9。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y 8, 將瑪位元b 1分配給符元位元y〇, 將碼位元b2分配給符元位元y丨, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元bs分配給符元位元y4, 將碼位元be分配給符元位元y6, 將碼位元b7分配給符元位元y5, 將瑪位元bg分配給符元位元y9, 將碼位元b9分配給符元位元, 而進行替換。 圖64B係表示LDPC碼是碼長N為16200位元、編碼率為 2/3之LDPC碼,進一步調變方式為i〇24QAM,倍數1>為i之 135786.doc •91 - 200937872 情況下之按照圖63之分配規則之碼位元之替換之第2例。 若根據圖64B,替換部32係按照圖63之分配規則,針對 從記憶體3 1所讀出之10X 1 (=mb)位元之碼位元bG至b9,分 別進行下述替換: 將碼位元bG分配給符元位元y9, 將碼位元b!分配給符元位元y 2, 將碼位元b2分配給符元位元y3, * 將碼位元b3分配給符元位元y 1, © 將碼位元b4分配給符元位元ys, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y7, 將碼位元b7分配給符元位元y4, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y6。 於此,圖64A及圖64B所示之碼位元bj對符元位元yj之分 配方式均按照圖63之分配規則(遵守分配規則)。 ® 圖65係表示LDPC碼是碼長N為64800位元、編碼率為2/3 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體3 1所讀出之10X 1 (=mb)位元之碼位 元係根據錯誤概率之差別,如圖65 A所示可群組區分為4個 碼位元群組Gbl,Gb2,Gb3,Gb4。 於圖65 A,分別而言,碼位元群組Gbi係碼位元b〇所屬, 碼位元群組Gb2係碼位元b!至b5所屬,碼位元群組Gb3係碼 135786.doc -92- 200937872 位元be所屬,碼位元群組Gb4係碼位元卜至心所屬。 調變方式為1024QAM,倍數b為1之情況下,l〇xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖65B所示可 群組區分為5個符元位元群組(^1,(^2,(^3,(^4,(^5。 於圖65B ’與圖62B相同,分別而言,符元位元群組Gy, 係符元位元所屬,符元位元群組Gy2係符元位元y2,y3 所屬’符元位元群組Gy3係符元位元y4,y5所屬.,符元位元 群組Gy*係符元位元y0,y7所屬,符元位元群組Gy5係符元位 ❹ 元ys,y9所屬。 圖66係表示LDPC碼是碼長N為64800位元、編碼率為2/3 之LDPC碼,進一步調變方式為1〇24qAM,倍數^丨之情 況下之分配規則。 於圖66之分配規則,規定有群組集合資訊 (Gb2,Gy1,2),(Gb2,Gy252),(Gb2,Gy3,l)5(Gb3,Gy4,l),(Gb4,Gy3, l),(Gb4,Gy4,l),(Gb4,Gy5,l)。 亦即,於圖66之分配規則,規定如下: ® 根據群組集合資訊(GbbGy^l) ’將錯誤概率第1良好之 碼位元群組Gb丨之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gl>2,Gyi,2),將錯誤概率第2良好之 碼位元群組Gh之瑪位元之2位元,分配給錯誤概率第}良 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 瑪位7C群組G b2之碼位7〇之2位το,分配給錯誤概率第2良 135786.doc -93· 200937872 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之1位元; 根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb4,Gy3,l),將錯誤概率第4良好之 © 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之1位元; 根據群組集合資訊(Gb4,Gy4,l),將錯誤概率第4良好之 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 及根據群組集合資訊(Gb4,Gy5,l),將錯誤概率第4良好 之碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第5 良好之符元位元群組Gy5之符元位元之1位元。 ® 圖67係表示按照圖66之分配規則之碼位元之替換例。 亦即,圖67A係表示LDPC碼是碼長N為64800位元、編 碼率為2/3之LDPC碼,進一步調變方式為1024QAM,倍數 b為1之情況下之按照圖66之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長N為64800位元、編碼率為2/3之LDPC 碼,進一步調變方式為1024QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(64800/(10xl))x(10xl) 135786.doc -94- 200937872 位疋之記憶體3 1寫入之碼位元係於撗列方向,以 l〇xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係按照圖66之分配規則,將讀出自記憶體31之 l〇xl(=mb)位元之碼位元bQ至h,例如圖67八所示分配給 U=b)個符元i10x1(=rnb)位元之符元位元%至乃,以替換 l〇xl(=mb)位元之碼位元b()至b9。 亦即,替換部32係分別 將碼位元bQ分配給符元位元y 8, 將碼位元bi分配給符元位元y〇, 將碼位元b2分配給符元位元yi, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y 3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y6, 將碼位元b7分配給符元位元y5, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖67B係表示LDPC碼是碼長N為64800位元、編碼率為 2/3之LDPC碼’進一步調變方式為i〇24QAM,倍數b為1之 情況下之按照圖66之分配規則之碼位元之替換之第2例。 若根據圖67B ’替換部32係按照圖66之分配規則,針對 從記憶體3 1所讀出之1 〇X 1 (=mb)位元之碼位元bG至b9,分 135786.doc •95- 200937872 別進行下述替換: 將碼位元b〇分配給符元位元y9, 將碼位元1^分配給符元位元y2, 將碼位元b2分配給符元位元丫3, 將喝位元b3分配給符元位元y 1, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y7, 將碼位元b7分配給符元位元y4, 將碼位元b8分配給符元位元y8, 將碼位元bp分配給符元位元y6。 圖68係表示LDP C碼是碼長Ν為16200位元、編碼率為3/4 之LDPC碼’進一步調變方式為i〇24QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下’從記憶體3 1所讀出之1 〇 X 1 (=mb)位元之瑪位 元係根據錯誤概率之差別,如圖68A所示可群組區分為4個 碼位元群組0131,0132,0153,0154。 於圖68A,分別而言,碼位元群組〇1>1係碼位元bQ所屬, 碼位元群組Gt>2係碼位元b!至b6所屬,碼位元群組Gb3係碼 位元b7所屬,碼位元群組Gb4係碼位元b8及b9所屬。 調變方式為1024QAM,倍數b為1之情況下,l〇xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖68B所示可 群組區分為5個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5。 於圖68B,與圖62B相同,分別而言,符元位元群組Gy〗 135786.doc 96- 200937872 係符元位元yG,yi所屬,符元位元群組Gy2係符元位元 所屬,符元位元群組Gys係符元位元所屬,符元位元3 群組Gy*係符元位元y0,y7所屬,符元位元群組係符元位 元ys,y9所屬。 圖69係表示LDPC碼是碼長162〇〇位元、編碼率為3/4 之LDPC碼,進一步調變方式為1〇24QAM,倍數1?為1之情 況下之分配規則。 於圖69之分配規則,規定有群組集合資訊 ® (Gb25Gyi52),(Gb2,Gy2,l),(Gb2,Gy3,2),(Gb2,Gy5,l),(Gb3jGy2,l), (Gb4,Gy4,l),(Gb4,Gy5,l)。 亦即’於圖69之分配規則,規定如下: 根據群組集合資訊(Gbi,Gy4,l),將錯誤概率第i良好之 碼位元群組Gb丨之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之〖位元; 根據群組集合資訊(Gt>2,Gyi,2),將錯誤概率第2良好之 _ 碼位元群組Gb:j之碼位元之2位元,分配給錯誤概率第i良 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gl>2,Gy2,l),將錯誤概率第2良好之 碼位元群組Gb>2之碼位元之1位元’分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之1位元; 根據群組集合資訊(Gb>2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb2,Gy5,1 ),將錯誤概率第2良好之 135786.doc -97- 200937872 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第$良 好之符元位元群組Gy5之符元位元之1位元·, 根據群組集合資訊(Gb^Ghl),將錯誤概率第3良好之 碼位元群組Gh之碼位元之1位元’分配給錯誤概率第2良 好之符元位元群組Gyz之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l) ’將錯誤概率第4良好之 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 及根據群組集合資訊(〇1)4,〇75,1),將錯誤概率第4良好 之碼位元群組GW之碼位元之〖位元,分配給錯誤概率第5 良好之符元位元群組Gys之符元位元之丨位元。 圖70係表示按照圖69之分配規則之碼位元之替換例。 亦即,圖70 A係表示LDPC碼是碼長N為16200位元、編 碼率為3/4之LDPC碼,進一步調變方式為1〇24qAM,倍數 b為1之情況下之按照圖69之分配規則之碼位元之替換之第 1例0 LDPC碼是碼長N為1 6200位元、編碼率為3/4之LDPC 碼,進一步調變方式為1024QAM、倍數^為丄之情況下,於 解多工器25 ’於縱行方向X橫列方向為(162〇〇/(1〇χ (l〇xl)位元之s己憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出’並供給至替換部32(圖16、圖 17) 〇 替換部3 2係按照圖69之分配規則,將讀出自記憶體3 1之 l〇x l(=mb)位元之碼位元bQ至bp,例如圖7〇a所示分配給 135786.doc •98- 200937872 l(=b)個符元之i〇xl(=mb)位元之符元位元…至乃,以替換 l〇xl(=mb)位元之碼位元%至b9。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y6, 將碼位元b】分配給符元位元y4, 將碼位元b2分配給符元位元y8, 將瑪位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y0, Ο 將碼位元b5分配給符元位元y2, 將碼位元1)6分配給符元位元y丨, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖70B係表示LDPC碼是碼長N為16200位元、編碼率為 ❾ 3/4之LDpC碼’進一步調變方式為1024QAM,倍數b為1之 情況下之按照圖69之分配規則之碼位元之替換之第2例。 若根據圖70B ’替換部32係按照圖69之分配規則,針對 從記憶體31所讀出之l〇xi (=mb)位元之碼位元%至b9,分 別進行下述替換: 將碼位元bG分配給符元位元y7, 將碼位元bi分配給符元位元y9, 將瑪位元b2分配給符元位元y4, 將碼位元b3分配給符元位元y!, 1357E6.doc 200937872 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y6。 圖71係表示LDPC碼是碼長N為64800位元、編碼率為3/4 之LDPC碼,進一步調變方式為1024qAM,倍數bg!之情 © 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之l〇xl(=mb)位元之碼位 元係根據錯誤概率之差別’如圖71A所示可群組區分為4個 碼位元群組01?1,01)2,0133,01)4。 於圖7 1 A ’分別而言’碼位元群組〇1?1係碼位元b0所屬, 碼位元群組Gbz係碼位元比至!^所屬,碼位元群組Gb3係碼 位元by所屬,碼位元群組Gb4係碼位元158及1>9所屬。 ❹ 調變方式為1024QAM ’倍數b為1之情況下,i〇xi(=mb) 位元之符元位元係根據錯誤概率之差別,如圖71β所示可 群組區分為5個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5。 於圖71B,與圖62B相同,分別而言,符元位元群組 係符元位元所屬,符元位元群組Gy2係符元位元y2,y3 所屬,符元位元群組Gya係符元位元y4,y5所屬,符元位元 群組Gy*係符元位元ye,y7所屬,符元位元群組Gy5係符元位 元ys,y9所屬。 圖72係表示LDPC碼是碼長^為648〇〇位元、編碼率為3/4 135786.doc -100. 200937872 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之分配規則。 於圖72之分配規則,規定有群組集合資訊(GbbGy^l), (Gb25Gy1,2),(Gb2,Gy2,l),(Gb2,Gy3,2)5(Gb2,Gy5,l),(Gb3,Gy2,l), (Gb4,Gy4,l),(Gb4,Gy5,l)。 亦即,於圖72之分配規則,規定如下: 根據群組集合資訊(Gbi,Gy4,l) ’將錯誤概率第1良好之 碼位元群組Gb 1之碼位元之1位元’分配給錯誤概率第4良 Ο 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb^Gy,。),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元’分配給錯誤概率第【良 好之符元位元群組Gyi之符元位元之2位元; 根據群組集合資訊(Gbz,Gy2,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元’分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之1位元; ❹ 根據群組集合資訊(Gt>2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gh>2之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb2,Gy5,l) ’將錯誤概率第2良好之 瑪位元群組Gh之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb3,Gy2,l),將錯誤概率第3良好之 碼位元群組Gb>3之碼位元之1位元’分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之1位元; 135786.doc -101 - 200937872 根據群組集合資訊(Gtu’Gy^l),將錯誤概率第4良好之 碼位元群組Gb>4之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 及根據群組集合資訊(Gb>4,Gy5,l),將錯誤概率第4良好 之碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第5 良好之符元位元群組Gys之符元位元之丨位元。 圖73係表示按照圖72之分配規則之瑪位元之替換例。 亦即,圖73A係表示LDPC碼是碼長n為64800位元、編 © 碼率為3/4之LDPC碼,進一步調變方式為1〇24QAM,倍數 b為1之情況下之按照圖72之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長N為64800位元、編碼率為3/4之ldpc 碼,進一步調變方式為1024QAM、倍數bgi之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(1〇χΐ))χ (1 0 X 1)位元之記憶體3 1寫入之碼位元係於橫列方向,以 1〇Xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 V 17) 〇 替換部32係按照圖72之分配規則,將讀出自記憶體31之 l〇xl(=mb)位元之碼位元bG至h,例如圖73A所示分配給 U=b)個符元21〇xl(=mb)位元之符元位元至乃,以替換 l〇xl(=mb)位元之碼位元bG至b9。 亦即,替換部32係分別 將瑪位元b〇分配給符元位元y6, 將瑪位元b 1分配給符元位元y4, 135786.doc •102- 200937872 將碼位元b2分配給符元位元y8, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y〇, 將碼位元b5分配給符元位元y2, 將碼位元b6分配給符元位元y丨, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7,The code bit b8 is assigned to the symbol bit y1(), the code bit b9 is assigned to the symbol bit y6, the code bit bi〇 is assigned to the symbol bit y4, and the code bit b丨 is assigned. The symbol bit y 7, the numerator b 12 is assigned to the symbol y 12 , the code bit b 13 is assigned to the symbol y 2 , and the modulo b 14 is assigned to the symbol y 14, the code bit b 15 is assigned to the symbol bit y 〇 and replaced. Fig. 61 is a diagram showing an example of a replacement process of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. That is, FIG. 61A shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5 and a further modulation method is 16qam and a multiple b is 2. . In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the signal points determined by 16QAM as one symbol, 135786.doc • 83· 200937872. In the case of the step, the code length N is 16,200 bits, and in the case of the multiple bg2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains the memory 4x2 (= mb) bits in the horizontal direction. The 8 vertical lines store ΐ62〇〇/(4χ2) bits in the longitudinal direction. " In the multiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory The code bits of 31 are read in the horizontal direction, read in the 4x2 (= mb) bit \\ position, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is a code bit b〇, b丨, 1^2, 1) 3, 1) 4, 135, 1) which is read from the 4><2 (=1111) bits of the memory 31. 6,1)7, for example, the symbol bits yG, yi, y2, y3, y4, y5, y6 assigned to 4x2 (= mb) bits of consecutive 2 (=1) symbols as shown in Fig. 61. , y< mode, replacing the 4x2 (= mb) bit of the code bit b〇 to Bu. That is, the replacing unit 32 assigns the code elements bG to by to the symbol bit 7 as in the case of the above-described Fig. 60A. Replace to 77. φ Fig. 61B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3/5, and a further modulation method is 64QAM and a multiple of ba2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 16,200 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains 6x2 (= mb) bits in the horizontal direction. 12 vertical lines, memory 162〇〇/(6χ2) in the longitudinal direction 135786.doc • 84 - 200937872 bits " in the solution of the multi-guard 25, the code bits of the LDPC code are written in the memory 31 In the traverse direction, if the 162 〇〇 之 码 字 ) 终 则 则 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & It is supplied to the replacement unit 32 (Fig. 16 and Fig. 17 is a replacement unit 32 for assigning a code bit _ from the memory of the memory 31 to the < 2 (=1^) bit, for example, as shown in Fig. 61B to the continuous 2 ('Function of the symbol "2 (= called bit element symbol bit © y〇'yi'y2'y3'y4, y5, yG7, y8, y9, y1〇, yil way, replace 6x2 (= mb The code bits bG to bu are the same. In other words, for the case of the (4) 32 series, the code bits 兀 and 匕 are assigned to the symbol bits y, and are replaced. Fig. 61C shows The LDPC code is an LDPC code with a code length of _62 bits and a coding rate of 3/5. The modulation method is 256 _, an example of the replacement processing of the current mode in the case of multiple (4). In the case where the G-wide mode is 256QAM, the bits of the code bit are mapped to 256QAM by one, and one symbol. For any of the 256 signal points determined, the code length N is 16,200 bits, and the multiples b*!, the memory 31 of the multiplexer 25 (@16, Fig. 17) is included in the course. Direction note:::(=, 8 vertical lines of bit, memory in the direction of the vertical direction (10). ·]) multiplexer 25, the code bit of the LDPC code is written in the memory (4) to the vertical (or) (6) 00 bit The end of the writing of the meta-coded bit code of the element is written as I35786.doc -85- 200937872. The code bit in the memory 3 1 is in the horizontal direction, in units of 8 x 1 (= mb). The readout is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is a code bit boAbbhbhbobhl^, which is read from the 8x1 (= mb) bit of the memory 31, for example, as shown in Fig. 61C. The way to allocate the 8xl (= mb) bits of the symbol (1, 丫 2, 丫 3, 丫 4, ) ^ 5, 丫 6, 77 assigned to l (= b) symbols 8 X1 (= mb) bits of code bits b〇 to b7. That is, the replacement unit 32 Do not assign the parity bit b〇 to the symbol bit y7, 分配 assign the code bit b to the symbol bit y3, assign the code bit b2 to the symbol bit yi, and assign the code bit b3 to The symbol bit y 5 assigns the code bit t>4 to the symbol bit y2, the code bit b5 to the symbol bit y6, and the code bit 1)6 to the symbol bit y4. The code bit b7 is assigned to the symbol bit y〇 and replaced. 〇 Next, explain the replacement process according to the distribution rule (hereinafter also referred to as the replacement process of the new replacement method). 62 to 64 are diagrams illustrating a new alternative. In the new alternative, the replacement unit 32 of the demultiplexer 25 replaces the code bits of the mb bits in accordance with a predetermined allocation rule. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits. The allocation rule stipulates that the combination of the code bit group of the code bit element and the symbol bit group of the symbol bit element of the code bit element of the code bit group is 135786.doc -86 - 200937872 a set of groups; and a code bit group of the group set, and a code bit of the symbol bit group and a bit number of the symbol bit (hereinafter also referred to as a group bit number). Here, the code bit system is as described above, and there is a difference in the error probability, and the symbol bit is also different in the error probability. The code bit group is grouped according to the error probability to distinguish the groups of code bits, and the symbol bit group is grouped according to the error probability to distinguish the group of symbol bits. Fig. 62 is a diagram showing that the LDPC code is a code length >! is 162 bits, and the coding rate is 2/3 ® 1〇1> (: code, further modulation is 1024QAM, and the multiple b is 1. The code bit group and the symbol bit group. In this case, the code position of the 1〇xl (== mb) bit read from the memory 31 is based on the difference in error probability, as shown in Fig. 62A. The group shown can be divided into 4 code bit groups 〇131, 0匕2, 〇1)3, 〇134. Here, the code bit group Gbi is a group in which the subscript i is smaller, and the error probability of the code bit belonging to the code bit group Gbj is better (smaller). In FIG. 62A, respectively, the code bit group Gbi is the code bit %, and the ® code bit group Gbz is the code bit 1?1,1?2,153,1)4,135 belongs to, code The bit group Gbs is a code bit element belonging to the 'code bit group Gh code bit genus. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the 1〇xl (=mb) bit are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 62B. Metagroups Gyi, Gy2, Gy3, Gy4, Gy5. Here, the 'symbol bit group Gyi is the same as the code bit group, and the smaller the subscript i is, the more the error probability of the symbol bit belonging to the symbol bit group Gy i is 135786.doc •87 200937872 Good group. In FIG. 62B, respectively, the symbol bit group ^... is a symbol bit bit, and the symbol bit group Gyz is a symbol element belonging to the seventh bit, and the symbol bit group Gy; The bit element belongs to, the symbol element group Gy4 is a symbol element y6, y? belongs to, the symbol element group Gys is a symbol element 78, and 丫9 belongs. Fig. 63 is a diagram showing an allocation rule in the case where the LDPC code is an LDPC code having a code length of N*162 bits and a coding rate of 2/3, and the modulation method is 1〇24QAM, and the multiple ^^ is i. In the allocation rule of Fig. 63, the combination of the code bit group Gbl and the symbol bit group Gys is defined as one group set. Then, the number of group bits of the group set is defined as 1 bit. Here, the group set and its group bit number are collectively referred to as group group information. Then, for example, a group set of the code bit group Gbl and the symbol bit group Gy5, and a group bit number of the group set, that is, 1 bit, are described as group set information (Gb^Gy^ l) » In the distribution rule of Figure 63, in addition to the group collection information, group collection information (Gb2, Gy丨, 2), (Gb2, Gy2, 2), (Gb2, Gy3, l), ( Gb3, Gy4, l), (Gb4, Gy3, l), (Gb4, Gy4, l), (Gb4, Gy5, l). For example, the group collection information (〇1?1, 〇75, 1) means that 1 bit of the code bit belonging to the code bit group Gb! is assigned to the symbol belonging to the symbol bit group Gy. 1 bit of the bit. Therefore, the allocation rule in Fig. 63 is defined as follows: According to the group set information (Gb^Gy^l) '1 bit of the code bit of the error probability first good maze group Gb! The probability of error is 5th 135786.doc • 88 - 200937872 The 1st bit of the symbol of the good (worst) symbol group Gys; according to the group collection information (Gb^GyiJ), the probability of error 2 2 bits of the code bit of the good code bit group Gt>2, allocated to the 2 bit of the symbol bit of the first good symbol bit group Gyi of the error probability; (Gb2, Gy2, 2), assigning the 2 bits of the code bit of the second good symbol bit group Gbz of the error probability to the symbol bit of the second good symbol bit group Gy2 of the error probability 2 bits; according to the group set information (Gb2, Gy3, l), the 1st bit of the code bit of the 2nd good code bit group Gt>2 of the error probability is assigned to the error probability 3rd 1 bit of the symbol element of the good symbol element group Gy3; according to the group set information (Gb^Ghj), the code bit of the 3rd good code bit group Gt> 1 The element is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (Gb>4, Gy3, l), the error probability is 4th good. One bit of the code bit of the code bit group Gb4 is assigned to one bit of the symbol bit of the third good symbol bit group of the error probability; 〇 according to the group set information (Gt > 4, Gy4, 1), assigns 1 bit of the code bit of the 4th good code bit group Gin of the error probability to the symbol bit of the 4th good symbol bit group Gy* of the error probability. Bits; and according to the group set information, assign the 1st bit of the imaginary bit of the 4th good code bit group Gb>4 of the error probability to the 5th good symbol bit group Gy5 of the error probability One bit of the symbol bit. As described above, the code bit group is grouped according to the error probability to group the code bit groups, and the symbol bit group is grouped according to the error probability to group the symbol bits 135786.doc -89- 200937872 group. Therefore, the allocation rule can also be said to combine the error probability of the specified code bit with the error probability of the symbol bit to which the code bit is assigned. Thus, the allocation rule for specifying the combination of the error probability of the code bit element and the error probability of assigning the symbol bit of the code bit element is determined by improving the tolerance to the error by, for example, measuring the BER simulation or the like (for Tolerance of noise). In addition, even if the allocation of the code bits of a certain code bit group is changed in the bit of the same symbol bit group, (almost) does not affect the resistance to errors. Therefore, in order to improve the tolerance to errors, the group set information of the BER (Bit Error Rate) is specified, that is, the code bit group of the specified code bit group and the code bit group are allocated. The combination of the symbol group of the symbol bit of the group of code bits (group set), the code bit group of the group set, and the code bit and the character of the symbol bit group respectively The number of bits of the meta-bit (group bit number), as an allocation rule, assigns a code bit to the symbol bit according to the allocation rule to replace the code bit. ® Among them, according to the allocation rule, the specific allocation method of which code bits are assigned to which symbols must be determined before the transmitting device 11 and the receiving device 12 (Fig. 7). Figure 64 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 63. That is, FIG. 64A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the further modulation method is 1024QAM, and the multiple b is 1, and the allocation rule according to FIG. 63 is used. The first example of the replacement of the code bit. 135786.doc -90- 200937872 LDPC code is code length N is 16200 bits, coding rate is 2/3iLDpc code, further modulation mode is 1024QAM, multiple case, in solution multiplexer 25, in the longitudinal direction X The code direction written by the memory 31 of the (162〇〇/(ι〇χΐ))χ(ι〇χΐ) bit is in the horizontal direction, in the order of l〇xl (= mb) bits. It is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits bQ to h of the l〇x1 (= mb) bits read from the memory 3 according to the allocation rule of FIG. 63, for example, as shown in FIG. 64A to © l (=b) The symbol bits of the symbol 〇xl (= mb) bits are ... to replace the code bits bQ to b9 of the l 〇 xl (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 8, respectively, assigns the m-bit b 1 to the symbol bit y, and assigns the code bit b2 to the symbol y.丨, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit bs is assigned to the symbol bit y4, and the code bit be is assigned to the symbol The bit y6 assigns the code bit b7 to the symbol bit y5, assigns the m-bit bg to the symbol bit y9, and assigns the code bit b9 to the symbol bit to be replaced. 64B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the modulation method is i〇24QAM, and the multiple 1 is 135786.doc •91 - 200937872 in the case of i. The second example of replacement of the code bits according to the distribution rule of FIG. 63. According to Fig. 64B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 63: Bit bG is assigned to symbol bit y9, code bit b! is assigned to symbol bit y 2, code bit b2 is assigned to symbol bit y3, * code bit b3 is assigned to symbol bit Element y 1, © assigns code bit b4 to symbol bit ys, assigns code bit b5 to symbol bit y, assigns bit b6 to symbol y7, and w1 Assigned to the symbol bit y4, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. Here, the code bit bj shown in Figs. 64A and 64B is assigned to the symbol bit yj in accordance with the allocation rule of Fig. 63 (according to the allocation rule). ® Figure 65 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3. The further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the 10X 1 (= mb) bits read from the memory 3 1 are group-divided into 4 code bit groups according to the difference in error probability as shown in FIG. 65A. Gbl, Gb2, Gb3, Gb4. In FIG. 65A, respectively, the code bit group Gbi is the code bit b〇, the code bit group Gb2 is the code bit b! to b5, and the code bit group Gb3 is the code 135786.doc -92- 200937872 The bit ben belongs to, and the code bit group Gb4 is the code bit element to the heart. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 65B. The meta group (^1, (^2, (^3, (^4, (^5. in Fig. 65B' is the same as Fig. 62B, respectively, the symbol bit group Gy, the symbol bit bit belongs to , symbol element group Gy2 symbol element y2, y3 belongs to the 'character bit group Gy3 system symbol element y4, y5 belongs., symbol element group Gy* system symbol element y0 , y7 belongs to, the symbol element group Gy5 is a symbol element ❹, y9 belongs to Fig. 66 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3, further modulating The method is 1〇24qAM, the allocation rule in the case of multiples. In the allocation rule of Figure 66, group group information (Gb2, Gy1, 2), (Gb2, Gy252), (Gb2, Gy3, l) is specified. 5 (Gb3, Gy4, l), (Gb4, Gy3, l), (Gb4, Gy4, l), (Gb4, Gy5, l). That is, the allocation rules in Fig. 66 are as follows: ® according to the group Set information (GbbGy^l) 'Assign the error probability to the 1st good code bit group Gb丨 of the code bit The probability 5th good symbol group Gy5 symbolic bit 1 bit; according to the group set information (Gl> 2, Gyi, 2), the error probability 2nd good code bit group Gh The 2 bits of the megabyte are assigned to the 2nd bit of the symbolic component of the error probability yth; the group of information (Gb2, Gy2, 2) will be wrong. Probability 2nd good maze 7C group G b2 code position 7〇 2 digits το, assigned to the error probability 2nd good 135786.doc -93· 200937872 Good symbol meta-group Gy2 symbolic bit 2 bits; according to the group set information (Gb2, Gy3, l), assign 1 bit of the code bit of the second good code bit group Gb2 of the error probability to the symbol 3 of the error probability One bit of the symbol bit of the bit group Gy3; according to the group set information (Gb3, Gy4, l), the one bit of the code bit of the third bit of the error bit group Gb3 of the error probability, Assigned to the 1-bit of the symbol bit of the fourth-perfect symbol group Gy4 of the error probability; according to the group set information (Gb4, Gy3, l), the error probability is the fourth best © code bit group Group Gb4 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability; according to the group set information (Gb4, Gy4, l), the error probability is 4: 1 bit of the code bit of the good code bit group Gb4, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and according to the group set information ( Gb4, Gy5, l), assigning 1 bit of the code bit of the 4th good code bit group Gb4 of the error probability to the symbol bit of the 5th good symbol bit group Gy5 of the error probability 1 bit. ® Figure 67 is an alternative representation of the code bits in accordance with the allocation rules of Figure 66. That is, FIG. 67A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 1024QAM, and the multiple b is 1 according to the allocation rule of FIG. 66. The first example of the replacement of the code bit. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25 is disposed in the X direction of the traversing direction. The direction is (64800/(10xl))x(10xl) 135786.doc -94- 200937872 The memory of the bit 3 1 is written in the direction of the queue, in l〇xl (= mb) bit unit It is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits bQ to h read from the l〇x1 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. 66, for example, as shown in FIG. 67 and assigns U=b) symbols. The i10x1 (= rnb) bit symbol bit % to is replaced by the code bit b() to b9 of the l〇xl (= mb) bit. That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y 8, respectively, assigns the code bit bi to the symbol bit y, and assigns the code bit b2 to the symbol yi, The code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y 3 , the code bit b5 is assigned to the symbol bit y4 , and the code bit b6 is assigned to the symbol bit Y6, the code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. 67B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. The further modulation method is i〇24QAM, and the multiple b is 1, and the code according to the allocation rule of FIG. 66 is used. The second example of the replacement of the bit. According to FIG. 67B, the replacement unit 32 is based on the allocation rule of FIG. 66, and the code bits bG to b9 of 1 〇X 1 (= mb) bits read from the memory 3 1 are divided into 135786.doc • 95. - 200937872 Do not replace the following: assign code bit b〇 to symbol bit y9, assign code bit 1^ to symbol bit y2, and assign code bit b2 to symbol bit 丫3, Assigning the drink bit b3 to the symbol bit y 1, assigning the code bit b4 to the symbol bit y5, assigning the code bit b5 to the symbol bit y, and assigning the code bit b6 to the symbol The bit y7 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit y8, and the code bit bp to the symbol bit y6. Figure 68 is a diagram showing that the LDP C code is a code bit group of 16200 bits and an encoding rate of 3/4. The further modulation method is i〇24QAM, and the multiples b is 1 Meta-bit group. In this case, the position of the 1 〇X 1 (= mb) bit read from the memory 3 1 is grouped into 4 code bit groups according to the difference in error probability as shown in FIG. 68A. Groups 0131, 0132, 0153, 0154. In FIG. 68A, respectively, the code bit group 〇1>1 is the code bit bQ, the code bit group Gt>2 is the code bit b! to b6, and the code bit group Gb3 is coded. The bit b7 belongs to, and the code bit group Gb4 belongs to the code bits b8 and b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 68B. Metagroups Gyi, Gy2, Gy3, Gy4, Gy5. 68B, as in FIG. 62B, respectively, the symbol bit group Gy 135786.doc 96- 200937872 is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit group. , the symbol element group Gys is a symbol element bit, the symbol element 3 group Gy* is a symbol element y0, y7 belongs to, the symbol element group is a symbol element ys, y9 belongs. Fig. 69 is a diagram showing an allocation rule in the case where the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3/4, and a further modulation method is 1〇24QAM, and the multiple 1 is 1. In the distribution rule of Figure 69, there is a group set information® (Gb25Gyi52), (Gb2, Gy2, l), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3jGy2, l), (Gb4 , Gy4, l), (Gb4, Gy5, l). That is, the allocation rule in Fig. 69 is defined as follows: According to the group set information (Gbi, Gy4, l), the 1st bit of the code bit of the error probability i-th good code bit group Gb is allocated. Give the bit error of the 4th good symbol group Gy* of the error probability bit bit; according to the group set information (Gt>2, Gyi, 2), the error probability is 2nd good _ code bit The 2-bit of the code bit of the meta-group Gb:j is allocated to the 2-bit of the symbol bit of the symbol i-good symbol group Gy!; according to the group set information (Gl>2 , Gy2, l), assigning the 1-bit ' of the code bit of the second good code bit group Gb>2 of the error probability to the symbol bit of the second good symbol bit group Gy2 of the error probability 1 bit; according to the group set information (Gb>2, Gy3, 2) 'Assign the 2 bits of the code bit of the second good code bit group Gb2 of the error probability to the third probability of error probability 2 bits of the symbol bit of the symbol group Gy3; according to the group set information (Gb2, Gy5, 1), the error probability is the second best 135786.doc -97- 200937872 code bit group Gh Code 1 bit of the bit, assigned to the 1st bit of the symbol bit of the error probability $th good symbol bit group Gy5, according to the group set information (Gb^Ghl), the error probability is 3rd good 1 bit of the code bit of the code bit group Gh is assigned to the 1st bit of the symbol bit of the second good symbol group Gyz of the error probability; according to the group set information (Gb^Gy ^l) '1 bit of the code bit of the 4th good code bit group Gh of the error probability is assigned to 1 bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability And according to the group set information (〇1) 4, 〇 75, 1), assign the bit position of the code bit of the error probability 4th good code bit group GW to the error probability 5th good The unit of the symbol bit of the symbolic group Gys. Figure 70 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 69. That is, FIG. 70A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 1〇24qAM, and the multiple b is 1 according to FIG. 69. The first example of the replacement of the code bits of the allocation rule 0 LDPC code is an LDPC code with a code length N of 1 6200 bits and a coding rate of 3/4, and further modulation mode is 1024QAM, and the multiple ^ is 丄The code locator written by the multiplexer 25' in the direction of the X direction of the multiplexer (162 〇〇 / (1 〇χ (l 〇 xl) bits) is in the course direction. Read out in l〇xl (= mb) bit units and supply it to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 3 2 reads out from the memory 3 according to the allocation rule of Fig. 69. The code bits bQ to bp of the xl (= mb) bits are allocated to 135786.doc • 98 - 200937872 l (= b) symbols i 〇 xl (= mb) bits as shown in Fig. 7 〇 a The symbol bit is ... to replace the code bit % to b9 of the l〇xl (= mb) bit. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, respectively, The code bit b] is assigned to the symbol bit y4, and the code bit b2 is assigned to the symbol bit y8. The m-bit b3 is assigned to the p-bit y5, the code-bit b4 is assigned to the p-bit y0, 码 the code-bit b5 is assigned to the p-bit y2, and the code-bit 1) is assigned to the symbol The bit y is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. The LDPC code is an LDpC code with a code length N of 16,200 bits and a coding rate of ❾ 3/4. The further modulation mode is 1024QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. 69 The second example is replaced. According to FIG. 70B, the replacement unit 32 performs the allocation rules of FIG. 69 for the code bits % to b9 of the l〇xi (= mb) bits read from the memory 31, respectively. The following replacement: assigning the code bit bG to the symbol bit y7, assigning the code bit bi to the symbol bit y9, assigning the mbit b2 to the symbol bit y4, and assigning the code bit b3 to The symbol bit y!, 1357E6.doc 200937872 assigns the code bit b4 to the symbol bit y5, the code bit b5 to the symbol bit y〇, and the code bit b6 to the symbol bit y2 , will be the code position B7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. Fig. 71 shows that the LDPC code has a code length N of 64800 bits, The LDPC code with a coding rate of 3/4 is further modulated by 1024qAM, and the code bit group and the symbol bit group in the case of multiple bg! In this case, the code bits of the l〇x1 (= mb) bits read from the memory 31 are grouped into 4 code bit groups as shown in FIG. 71A according to the difference in error probability. ?1,01)2,0133,01)4. In Figure 7 1 A 'respectively' the code bit group 〇1?1 code bit b0 belongs, the code bit group Gbz is the code bit ratio to ^^ belongs, the code bit group Gb3 code The bit by belongs to, and the code bit group Gb4 is associated with the code bits 158 and 1>9.调 When the modulation mode is 1024QAM 'When the multiple b is 1, the symbol of the i〇xi(=mb) bit is based on the difference in error probability, and can be grouped into 5 symbols as shown in Fig. 71β. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 71B, as in FIG. 62B, respectively, the symbol bit group belongs to the symbol bit, the symbol bit group Gy2 is the symbol bit y2, y3 belongs to, and the symbol bit group Gya belongs to The symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element ye, y7 belongs to, the symbol element group Gy5 is the symbol element ys, y9 belongs. Figure 72 is a diagram showing that the LDPC code is an LDPC code having a code length of 648 bits and a coding rate of 3/4 135786.doc -100. 200937872, and the modulation is further modulated by 1024QAM, and the multiple b is 1. rule. The allocation rule in Fig. 72 specifies group information (GbbGy^l), (Gb25Gy1, 2), (Gb2, Gy2, l), (Gb2, Gy3, 2) 5 (Gb2, Gy5, l), ( Gb3, Gy2, l), (Gb4, Gy4, l), (Gb4, Gy5, l). That is, the allocation rule in FIG. 72 is defined as follows: According to the group set information (Gbi, Gy4, l) 'Assign 1 bit of the code bit of the first good code bit group Gb 1 of the error probability' Give the error probability the fourth good Ο Ο Ο Ο Ο G G G G G G ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The 2 bits of the code bit of the group Gb2 are assigned to the error probability [2 bits of the symbol element of the good symbol bit group Gyi; according to the group set information (Gbz, Gy2, l), Error probability 2nd good code bit group Gb2 code bit 1 bit 'as assigned to error probability 2nd good symbol bit group Gy2 symbol bit 1 bit; ❹ According to group Aggregate information (Gt > 2, Gy3, 2) 'Assign the 2 bits of the code bit of the 2nd good code bit group Gh>2 of the error probability to the 3rd good symbol bit group of the error probability 2 bits of the symbol element of Gy3; according to the group set information (Gb2, Gy5, l) 'Assign the error probability to the 1st bit of the code bit of the 2nd good horse bit group Gh, to the wrong The probability 5th good symbol bit group Gy5 is 1 bit of the symbol bit; according to the group set information (Gb3, Gy2, l), the error probability 3rd good code bit group Gb>3 The 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group Gy2 of the error probability; 135786.doc -101 - 200937872 According to the group collection information (Gtu'Gy ^l), assigning 1 bit of the code bit of the 4th good code bit group Gb>4 of the error probability to the symbol bit of the 4th good symbol bit group Gy* of the error probability 1 bit; and according to the group set information (Gb>4, Gy5, l), the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is assigned to the error probability 5th good The unit of the symbol bit of the symbolic group Gys. Figure 73 is a diagram showing an alternative of the megabits according to the allocation rule of Figure 72. That is, Fig. 73A shows that the LDPC code is an LDPC code having a code length n of 64,800 bits and a code rate of 3/4, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to Fig. 72. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an ldpc code having a code length N of 64,800 bits and a coding rate of 3/4. In the case where the modulation method is 1024QAM and the multiple bgi, the multiplexer 25 is in the direction of the X direction in the wale direction. (648〇〇/(1〇χΐ))χ (1 0 X 1) bit memory 3 1 written code bits are in the horizontal direction, read in 1〇Xl (= mb) bit units And supplied to the replacement unit 32 (FIG. 16, FIG. V17). The replacement unit 32 reads the code bits bG to h from the l〇x1 (=mb) bits of the memory 31 in accordance with the allocation rule of FIG. For example, as shown in FIG. 73A, the symbol bits assigned to U=b) symbols 21〇xl (=mb) bits are replaced by the code bits bG to b9 of the l〇xl (=mb) bits. . That is, the replacing unit 32 assigns the megabyte b 给 to the symbol y6, and assigns the megabyte b 1 to the symbol y4, 135786.doc • 102- 200937872 assigns the code bit b2 to The symbol bit y8 assigns the code bit b3 to the symbol bit y5, the code bit b4 to the symbol bit y, and the code bit b5 to the symbol y2, and the code bit B6 is assigned to the symbol bit y丨, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7.
而進行替換。 圖73B係表示LDPC碼是碼長N為64800位元、編碼率為 3/4之LDPC碼,進一步調變方式為1024QAM,倍數b為1之 情況下之按照圖72之分配規則之碼位元之替換之第2例。 若根據圖73B,替換部32係按照圖72之分配規則,針對 從記憶體31所讀出之l〇xl(=mb)位元之碼位元bG至b9,分 別進行下述替換: 將碼位元bG分配給符元位元y7, 將碼位元b i分配給符元位元y 9, 將碼位元b2分配給符元位元y4, 將碼位元b3分配給符元位元y!, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y8, 135786.doc -103· 200937872 將碼位元b9分配給符元位元“。 圖74係表示LDPC碼是碼長>1為162〇〇位元、編碼率為4/5 之LDPC碼,進一步調變方式為1〇24QAM ,倍數丄之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出21〇xl(=mb)位元之碼位 兀*係根據錯誤概率之差別,如圖74A所示可群組區分為3個 碼位元群組Gb,,Gb2,Gb3。 於圖74A,分別而言,碼位元群組叫係碼位元至^所 © 屬’碼位元群組仍2係碼位^所屬,碼位元群組叫係碼 位元b8及b9所屬。 調變方式為1〇24QAM,倍數1)為1之情況下,1〇xi(=mb) 位元之符元位元係根據錯誤概率之差別,如圖74B所示可 群組區分為5個符元位元群組Gy丨如你办办。 於圖74B,與圖62B相1¾,分別而言,符元位元群組μ 係符兀位TGyo’y!所屬,符元位元群組如係符元位元^3 ❹所屬’符元位元群組Gy3係符元位元㈣所屬,符元位元 群組Gy4_元位元y6,y7所屬,#元位元群组巧5係符元位 元ys,y9所屬。 圓75係表7FLDPC碼是碼仙為16位元、編碼率為仍 之LDPC碼,進一步調變方式為1〇24QAM,倍數^丨之情 況下之分配規則。 於圖75之分配規則,規定有群組集合資訊(Gbl,Gyi,2), (Gb1,Gy2,l),(Gb1,Gy3,2)J(Gb1,Gy4,1)5(GbijGy5)1)}(Gb2j^ (Gb3,Gy4,l),(Gb3,Gy5,l) 〇 135786.doc -104. 200937872 亦即,於圖75之分配規則,規定如下: 根據群組集合資訊(Gb〗,Gyi,2) ’將錯誤概率第好< 碼位元群組Gb!之碼位元之2位元’分配給錯誤概率第1 ^ 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第丄良#< 碼位元群組Gb!之碼位元之1位元,分配給錯誤概率第2 ^ 好之符元位元群組Gy2之符元位元之1位元;And replace it. 73B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and further modulation is 1024QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 73B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the l〇x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 72: The bit bG is assigned to the symbol bit y7, the code bit bi is assigned to the symbol bit y 9, the code bit b2 is assigned to the symbol bit y4, and the code bit b3 is assigned to the symbol bit y !, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y〇, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol The bit y3 assigns the code bit b8 to the symbol y8, 135786.doc -103· 200937872 assigns the code bit b9 to the symbol bit ". Figure 74 shows that the LDPC code is the code length > For a 162-bit LDPC code with a coding rate of 4/5, the further modulation method is 1〇24QAM, and the code bit group and the symbol bit group in the case of multiples. In this case, The code bits 〇* of the 21〇xl (=mb) bits read by the memory 31 are grouped into three code bit groups Gb, Gb2, Gb3 according to the difference in error probability as shown in FIG. 74A. In Figure 74A, respectively, the code bit The group is called the code bit to ^ is the genus 'code bit group is still 2 code bit ^ belongs, the code bit group is called the code bit b8 and b9 belongs. The modulation mode is 1〇24QAM, multiple 1 In the case of 1, the 〇 xi (= mb) bit symbol bit is based on the difference in error probability, as shown in FIG. 74B, the group can be divided into 5 symbol bit groups Gy, such as you. In Fig. 74B, in contrast to Fig. 62B, respectively, the symbol bit group μ 兀 TG TG ' ' TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG The symbol element group Gy3 is represented by the symbol element (4), the symbol element group Gy4_ meta-bit y6, y7 belongs to, the #元位元巧5-character element ys, y9 belongs. The round 75 series table 7FLDPC code is a 16-bit code, the coding rate is still LDPC code, and the further modulation method is 1〇24QAM, and the allocation rule in the case of multiples is as shown in Fig. 75. Group collection information (Gbl, Gyi, 2), (Gb1, Gy2, l), (Gb1, Gy3, 2) J (Gb1, Gy4, 1) 5 (GbijGy5) 1)} (Gb2j^ (Gb3, Gy4, l), (Gb3, Gy5, l) 〇 135786.doc -104. 200937872 That is, the distribution rules in Figure 75, The following is as follows: According to the group collection information (Gb, Gyi, 2) 'Assign the error probability to the best < 2 bit of the code bit group Gb!' to the error probability 1st ^ The bit position of the meta-bit group Gy! is 2 bits; according to the group set information (Gb^Gy^l), the code probability of the error probability 丄良良#< code bit group Gb! 1 bit, assigned to 1 bit of the symbol bit of the error probability 2nd good symbol bit group Gy2;
❹ 根據群組集合資訊(Gb^Gy^) ’將錯誤概率第i良好之 碼位元群組Gb,之碼位元之2位元’分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gbi,Gy4,l) ’將錯誤概率第1 $好之 碼位元群組Gb,之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb】,Gy5,l),將錯誤概率第i良好之 碼位元群組Gl^之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy 5之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之〗位元,分配給錯誤概率第2良 好之符元位元群組Gyz之符元位元之1位元; 根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之丨位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 及根據群組集合資訊(Gb^Gy5,〗),將錯誤概率第3良好 之碼位元群組Gh之碼位元之丨位元,分配給錯誤概率第5 135786.doc -105· 200937872 良好之符元位元群組Gys之符元位元之1位元。 圖76係表示按照圖75之分配規則之碼位元之替換例。 亦即’圖76A係表示LDPC碼是碼長N為16200位元、編 碼率為4/5之LDPC碼,進一步調變方式為1〇24QAM,倍數 b為1之情況下之按照圖7 5之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長N為16200位元、編碼率為4/5之LDPC 碼’進一步調變方式為1024QAM、倍數b為1之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(1〇χ1))χ (l〇xl)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係按照圖75之分配規則’將讀出自記憶體31之 1 〇x 1 (=mb)位元之碼位元至bp ’例如圖76A所示分配給 U=b)個符元之i〇xi(=mb)位元之符元位元…至乃,以替換 l〇xl(=mb)位元之碼位元b〇至b9。 亦即,替換部32係分別 將碼位元bG分配給符元位元y6, 將瑪位元b !分配給符元位元y 4, 將碼位元b2分配給符元位元y 8, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y〇, 將瑪位元b5分配給符元位元y2, 將碼位元1>6分配給符元位元y!, 135786.doc -106- 200937872 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖76B係表示LDPC碼是碼長N為16200位元、編碼率為 4/5之LDPC碼,進一步調變方式為1024QAM,倍數b為1之 情況下之按照圖75之分配規則之碼位元之替換之第2例。 若根據圖76B,替換部32係按照圖75之分配規則,針對 〇 從記憶體3 1所讀出之10 X 1 (=mb)位元之碼位元bG至b9,分 別進行下述替換: 將碼位元bG分配給符元位元y9, 將碼位元b i分配給符元位元y 7, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y 1, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, w 將碼位元b6分配給符元位元y4, 將碼位元b7分配給符元位元y2, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y6。 圖77係表示LDPC碼是碼長N為64800位元、編碼率為4/5 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之l〇xl(=mb)位元之碼位 135786.doc •107· 200937872 元係根據錯誤概率之差別,如圖77A所示可群組區分為3個 碼位元群組GbhGbhGbs。 於圖77A ’分別而言,碼位元群組〇1>1係碼位元bG所屬, 碼位元群組Gb>2係碼位元b!至b7所屬,碼位元群組Gb3係碼 位元b8及b9所屬。 調變方式為1024QAM,倍數b為1之情況下,i〇xi(=mb) 位元之符元位元係根據錯誤概率之差別,如圖77B所示可 群組區分為5個符元位元群組Gy丨,Gy2,Gy3,Gy4,Gy5。 ® 於圖77B,與圖62B相同,分別而言,符元位元群組Gy! 係符元位元所屬’符元位元群組Gy2係符元位元y2,y3 所屬’符元位元群組Gy3係符元位元y4,y5所屬,符元位元 群組Gy4係符元位元y6,y7所屬,符元位元群組Gy5係符元位 元y%y9所屬。 圖78係表示LDPC碼是碼長N為64800位元、編碼率為4/5 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之分配規則。 ◎ 於圖78之分配規則’規定有群組集合資訊 (Gb2,Gylj2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy5,l),(Gb3,Gy4,l), (Gb3,Gy5,l) ° 亦即’於圖78之分配規則,規定如下: 根據群組集合資訊(Gb〗,Gy4,l),將錯誤概率第1良好之 碼位元群組Gb!之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb2,Gy!,2),將錯誤概率第2良好之 135786.doc •108· 200937872 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第1良 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; © 根據群組集合資訊(Gb2,Gy5,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 及根據群組集合資訊(Gb3,Gy5,l),將錯誤概率第3良好 之碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第5 ® 良好之符元位元群組Gy5之符元位元之1位元。 圖79係表示按照圖78之分配規則之碼位元之替換例。 亦即,圖79A係表示LDPC碼是碼長N為64800位元、編 碼率為4/5之LDPC碼,進一步調變方式為1024QAM,倍數 b為1之情況下之按照圖78之分配規則之碼位元之替換之第 1例0 LDPC碼是碼長N為64800位元、編碼率為4/5之LDPC 碼,進一步調變方式為1024QAM、倍數b為1之情況下,於 135786.doc -109- 200937872 解多工器25’於縱行方向χ橫列方向為(64800/^ 〇χ (l〇xl)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) ° 替換部32係按照圖78之分配規則,將讀出自記憶體31之 10><1( = !1113)位元之碼位元1)()至159,例如圖79八所示分配給 l(=b)個符元之l〇xl(=mb)位元之符元位元至,以替換 l〇xl(=mb)位元之碼位元bG至b9。 © 亦即,替換部32係分別 將碼位元b〇分配給符元位元y 6, 將碼位元b 1分配給符元位元y 4, 將碼位元b2分配給符元位元y 8, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y 〇, 將碼位元b5分配給符元位元y2, 將碼位元1)6分配給符元位元yi, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖79B係表示LDPC碼是碼長N為64800位元、編碼率為 4/5之LDPC碼’進一步調變方式為1〇24qam,倍數b為1之 情泥下之按照圖78之分配規則之碼位元之替換之第2例。 若根據圖79B,替換部32係按照圖78之分配規則,針尉 135786.doc •110· 200937872 從記憶體31所讀出之1〇xl(=mb)位元之碼位元b❶至b,八 別進行下述替換: 刀 將碼位元bG分配給符元位元y7, 將碼位元b!分配給符元位元yi, 將碼位元t>2分配給符元位元y3, 將碼位元I)3分配給符元位元y4, 將碼位元I)4分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, ® 將碼位元b6分配給符元位元y 2, 將碼位元b7分配給符元位元y 9, 將碼位元b8分配給符元位元y 8, 將碼位元b9分配給符元位元y6。 圖80係表示LDPC碼是碼長N為16200位元、編碼率為5/6 之LDPC碼,進一步調變方式為1〇24QAM,倍數1)為1之情 況下之碼位元群組及符元位元群組。 ❹該情況下,從記憶體31所讀出之1〇xl(=mb)位元之碼位 元係根據錯誤概率之差別,如圖80A所示可群組區分為4個 碼位元群組GbhGbzAbsAN。 於圖80A,分別而言,碼位元群組Gbi係碼位元%所屬, 碼位元群組Gb2係碼位元b!至by所屬,碼位元群組Gb3係碼 位元bs所屬,碼位元群組Gb4係碼位元^所屬。 調變方式為1024QAM ’倍數b為1之情況下,10xl(:=mb) 位元之符元位元係根據錯誤概率之差別,如圖8 〇B所示可 群組區分為5個符元位元群組Gy丨,Gy2,Gy3,Gy4,Gy5。 -Ill . 135786.doc 200937872 於圖80B,與圖62B相同,分別而言’符元位元群組Gyi 係符元位元yQ,yi所屬’符元位元群組Gy2係符元位元乃心 所屬,符元位元群組Gys係符元位元y4,y5所屬,符元位元 群組Gy*係符元位元“山所屬,符元位元群組Gy5係符元位 元ys,y9所屬。 圖81係表示LDPC碼是碼長N*162〇〇位元、編碼率為5/6 之LDPC碼,進一步調變方式為1〇24QAM,倍數1?為1之情 況下之分配規則》 於圖81之分配規則,規定有群組集合資訊 (Gb2,Gyi,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy5,l),(Gb3,Gy5,l), (Gb4,Gy4,l)。 亦即’於圖81之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l),將錯誤概率第1良好之 碼位元群組Gbi之碼位元之1位元’分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb2,Gyi,2) ’將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第1良 好之符元位元群組Gy丨之符元位元之2位元; 根據群組集合資訊(Gb>2,Gy2,2) ’將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 135786.doc • 112· 200937872 根據群組集合資訊(Gb^Gy^l),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之丨位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之丨位元; 根據群組集合資訊(Gb3,Gys,l),將錯誤概率第3良好之 碼位元群組Gbs之碼位元之丨位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gb4,Gy4,l),將錯誤概率第4良好 之碼位元群組GW之碼位元之1位元’分配給錯誤概率第4 © 良好之符元位元群組Gy*之符元位元之1位元。 圖82係表示按照圖81之分配規則之碼位元之替換例。 亦即,圖82A係表示LDPC碼是碼長N為16200位元、編 碼率為5/6之LDPC碼,進一步調變方式為1〇24QAM,倍數 b為1之情況下之按照圖81之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長N為16200位元、編碼率為5/6之LDpc ❹ 碼’進一步調變方式為1024QAM、倍數b為1之情況下,於 解多工器25 ’於縱行方向X橫列方向為(162〇〇/(1〇x i))x (10 χ 1)位元之§己憶體3 1寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出’並供給至替換部32(圖16、圖 17)。 替換部32係按照圖81之分配規則’將讀出自記憶體3丨之 l〇x l(=mb)位元之瑪位元b〇至1>9 ’例如圖82A所示分配給 l(=b)個符元之i〇xi(=mb)位元之符元位元”至”,以替換 l〇xl(=mb)位元之碼位元b〇至b9。 135786.doc -113 - 200937872 Ο 亦即’替換部32係分別 將碼位元b〇分配給符元位元y6 將碼位元b!分配給符元位元y4 將碼位元b2分配給符元位元y8 將碼位元b3分配給符元位元y5 將碼位元b4分配給符元位元y〇 將碼位元b5分配給符元位元y2 將碼位元b6分配給符元位元yi 將碼位元b7分配給符元位元y3 將碼位元b8分配給符元位元y9 將碼位元b9分配給符元位元y7 而進行替換。 圖82B係表示LDPC碼是碼長N為16200位元、蝙碼率 5/6之LDPC碼,進一步調變方式為1024QA]VI,倍數 情況下之按照圖81之分配規則之碼位元之替換之第2例。 為 之 Ο 若根據圖82B,替換部32係按照圖81之分配規則,針斜 從記憶體31所讀出之i〇xl(=mb)位元之碼位元〜至%,分 別進行下述替換: 將碼位元b〇分配給符元位元y7, 將碼位元b!分配給符元位元y8, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, 135786.doc •114· 200937872 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y 1, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y6。 圖83係表示LDPC碼是碼長N為64800位元、編碼率為5/6 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之l〇xl (=mb)位元之碼位 © 元係根據錯誤概率之差別,如圖83A所示可群組區分為4個 碼位元群組 Gb 1,Gb2,Gb3,Gb4。 於圖83 A,分別而言,碼位元群組Gb 1係碼位元b〇所屬, 碼位元群組Gb2係碼位元b!至b7所屬,碼位元群組Gb3係碼 位元bs所屬,碼位元群組Gb4係碼位元b9所屬。 調變方式為1024QAM,倍數b為1之情況下,l〇xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖83B所示可 群組區分為5個符元位元群組Gy^Gy^Gy^Gy^Gys。 ® 於圖83B,與圖62B相同,分別而言,符元位元群組Gy! 係符元位元yG,yi所屬,符元位元群組Gy2係符元位元y2,y3 所屬,符元位元群組Gy3係符元位元y4,y5所屬,符元位元 群組Gy4係符元位元y6,y7所屬,符元位元群組Gy5係符元位 元ys,y9所屬。 圖84係表示LDPC碼是碼長N為64800位元、編碼率為5/6 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之分配規則。 135786.doc -115- 200937872 於圖84之分配規則’規定有群組集合資訊(GbiGy4i), (〇^5〇Υι,2),(0525072,2),(0^,〇Υ3,2),(〇^,〇Υ5,ι)?(<31)3 j} ? (Gb4,Gy4,1)。 亦即,於圖84之分配規則,規定如下: 根據群組集合資訊(Gb!,Gy4,1),將錯誤概率第1良好之 碼位元群組Gh之碼位元之1位元’分配給錯誤概率第斗良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb2,Gy!,2) ’將錯誤概率第2良好之 © 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第i良 好之符元位元群組Gy〗之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第3 ^ 好之符元位元群組Gy3之符元位元之2位元; ❹ 根據群組集合資訊(Gb2,Gys,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第$良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gh>3,Gy5,1),將錯誤概率第3良好之 碼位元群組Gbs之碼位元之1位元,分配給錯誤概率第^良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gb^Gy4,1),將錯誤概率第4良好 之碼位元群組Gb>4之瑪位元之1位元’分配給錯誤概率第* I35786.doc •116· 200937872 良好之符元位元群組之符元位元之1位元。 圖85係表示按照圖84之分配規則之碼位元之替換例。 亦即,圖85A係表示LDPC碼是碼長\為648〇〇位元、編 碼率為5/6之LDPC碼,進一步調變方式為1〇24QAM,倍數 b為1之情況下之按照圖84之分配規則之碼位元之替換之第 1例0❹ According to the group set information (Gb^Gy^) 'Assign the error probability i-th good code bit group Gb, the 2-bit code bit is assigned to the error probability third good symbol bit group 2 bits of the symbol element of Gy3; according to the group set information (Gbi, Gy4, l) 'Assign the error probability 1st good code bit group Gb, 1 bit of the code bit to Error probability 4th good symbol group Gy4 symbol bit 1 bit; according to group set information (Gb), Gy5, l), the error probability i is good code group Gl ^1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy 5 of the error probability; according to the group set information (Gb^Gy^l), The bit of the code bit of the second good code bit group Gbz of the error probability is assigned to the 1-bit of the symbol bit of the second good symbol bit group Gyz of the error probability; The information (Gb3, Gy4, l) assigns the unit of the code bit of the 3rd good code bit group Gh of the error probability to the symbol of the 4th good symbol group Gy* of the error probability. 1 bit of bit And according to the group set information (Gb^Gy5, 〗), assign the error bit of the code bit of the third good symbol bit group Gh to the error probability. 5 135786.doc -105· 200937872 Good One bit of the symbol bit of Gys. Figure 76 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 75. That is, FIG. 76A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the allocation rule. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 1024QAM and the multiple b is 1, the multiplexer 25 is in the traverse direction x. The code bit written in the memory 31 of the direction (162〇〇/(1〇χ1))χ(l〇xl) bit is in the course direction, and is read out in l〇xl (=mb) bit units. And supplied to the replacement unit 32 (FIG. 16, FIG. 17). The replacing unit 32 assigns the code bits read from the 1 〇 x 1 (= mb) bits of the memory 31 to bp ' according to the allocation rule of FIG. 75, for example, as shown in FIG. 76A to U=b) symbols. I〇xi (= mb) bit symbol bit... to replace the code bits b〇 to b9 of l〇xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y6, assigns the m-bit b! to the symbol bit y 4, and assigns the code bit b2 to the symbol bit y 8, respectively. The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y 〇, the megabyte b5 is assigned to the symbol y2, and the code bit 1 > 6 is assigned to the symbol The meta-bit y!, 135786.doc -106- 200937872 assigns the code bit b7 to the symbol bit y3, the code bit b8 to the symbol bit y9, and the code bit b9 to the symbol bit Y7, and replace it. 76B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and further modulation is 1024QAM, and when the multiple b is 1, the code bit according to the allocation rule of FIG. 75 is used. The second example of replacement. According to FIG. 76B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10 X 1 (= mb) bits read from the memory 3 1 in accordance with the allocation rule of FIG. 75: The code bit bG is assigned to the symbol bit y9, the code bit bi is assigned to the symbol bit y 7, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Element y 1, assigning code bit b4 to symbol bit y5, assigning code bit b5 to symbol bit y〇, w assigning code bit b6 to symbol bit y4, and using code bit b7 The symbol bit y2 is assigned, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. 77 is a diagram showing that an LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code position 135786.doc • 107· 200937872 of the l〇xl (= mb) bit read from the memory 31 is grouped into 3 according to the difference in error probability as shown in FIG. 77A. One code bit group GbhGbhGbs. In Fig. 77A', respectively, the code bit group 〇1>1 is the code bit bG, the code bit group Gb>2 is the code bit b! to b7, and the code bit group Gb3 is coded. Bits b8 and b9 belong. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the i〇xi(=mb) bit are different according to the error probability. As shown in FIG. 77B, the group can be divided into 5 symbol bits. Metagroups Gy丨, Gy2, Gy3, Gy4, Gy5. In Fig. 77B, which is the same as Fig. 62B, respectively, the symbol element group Gy! is represented by the 'character bit group Gy2, the symbol bit y2, and the y3 belongs to the 'symbol bit The group Gy3 is a symbol element y4, y5 belongs to, the symbol element group Gy4 is a symbol element y6, y7 belongs to, and the symbol element group Gy5 is a symbol element y%y9 belongs to. Fig. 78 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method of 1024QAM and a multiple b of 1. ◎ The distribution rule in Figure 78 specifies group information (Gb2, Gylj2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3, Gy4, l) ), (Gb3, Gy5, l) °, that is, the allocation rule in Figure 78, as follows: According to the group set information (Gb, Gy4, l), the error probability first good code bit group Gb The 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb2, Gy!, 2), The probability of error is the second best 135786.doc •108·200937872 The 2-bit element of the code bit group Gb2 is assigned to the symbol bit of the first good symbol group Gy! 2 bits; according to the group set information (Gb2, Gy2, 2), the 2 bits of the code bit of the second good code bit group Gb2 of the error probability are assigned to the second good symbol bit of the error probability. 2 bits of the symbol element of the meta group Gy2; according to the group set information (Gb2, Gy3, 2), the 2 bits of the code bit of the second good code bit group Gb2 of the error probability are allocated Give the symbol probability of the third good symbol group Gy3 of the error probability 2 bits of the element; © according to the group set information (Gb2, Gy5, l), the 1st bit of the code bit of the 2nd good code bit group Gb2 of the error probability is assigned to the error probability 5th good 1 bit of the symbol bit of the symbol group Gy5; 1 bit of the code bit of the 3rd good code bit group Gb3 of the error probability according to the group set information (Gb3, Gy4, l) Yuan, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and the 3rd good code bit of the error probability according to the group set information (Gb3, Gy5, l) The 1-bit of the code bit of the meta-group Gb3 is assigned to the 1-bit of the symbol bit of the error probability 5 ® good symbol bit group Gy5. Figure 79 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 78. That is, FIG. 79A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and the further modulation method is 1024QAM, and the multiple b is 1 in accordance with the allocation rule of FIG. The first example of the replacement of the code bit 0 LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 4/5, and further modulation mode is 1024QAM, and the multiple b is 1, 135786.doc -109- 200937872 The multiplexer 25' is written in the direction of the wales in the direction of the horizontal direction (64800/^ 〇χ (l〇xl) bits of the memory 31 written in the horizontal direction, to The 〇xl (= mb) bit unit is read and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads the 10><1 from the memory 31 in accordance with the allocation rule of Fig. 78. = !1113) The bit position of the bit 1)() to 159, for example, the symbol bit assigned to the l〇xl(=mb) bit of l(=b) symbols as shown in Fig. 79. To replace the code bits bG to b9 of l〇xl (= mb) bits. © that is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 6, respectively, and assigns the code bit b 1 to the symbol bit y 4 and the code bit b2 to the symbol bit. y 8, assign code bit b3 to symbol bit y5, assign code bit b4 to symbol bit y 〇, assign code bit b5 to symbol bit y2, and code bit 1) Assigned to the symbol bit yi, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. . 79B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5. The further modulation method is 1〇24qam, and the multiple b is 1 according to the distribution rule of FIG. The second example of replacement of code bits. According to FIG. 79B, the replacing unit 32 is in accordance with the allocation rule of FIG. 78, and the code bits ❶ 135786.doc • 110· 200937872 are read from the memory 31 by the code bits b❶ to b of 1〇xl (= mb) bits. The following substitutions are made: the knife assigns the code bit bG to the symbol bit y7, the code bit b! to the symbol bit yi, and the code bit t>2 to the symbol bit y3. The code bit I)3 is assigned to the symbol bit y4, the code bit I)4 is assigned to the symbol bit y 5 , and the code bit b5 is assigned to the symbol bit y 〇, ® the code bit B6 is assigned to the symbol bit y 2, the code bit b7 is assigned to the symbol bit y 9, the code bit b8 is assigned to the symbol bit y 8, and the code bit b9 is assigned to the symbol bit y6 . 80 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and a further modulation method is 1〇24QAM, and a multiple of 1) is a code bit group and a symbol. Meta-bit group. In this case, the code bits of the 1〇x1 (=mb) bit read from the memory 31 are group-divided into 4 code bit groups according to the difference in error probability as shown in FIG. 80A. GbhGbzAbsAN. 80A, respectively, the code bit group Gbi belongs to the code bit %, the code bit group Gb2 is the code bit b! to by, and the code bit group Gb3 belongs to the code bit bs. The code bit group Gb4 is a code bit element ^ belongs. When the modulation mode is 1024QAM 'when the multiple b is 1, the 10xl (:=mb) bit symbol is based on the difference in error probability, as shown in Figure 8 〇B, the group can be divided into 5 symbols. The bit group Gy丨, Gy2, Gy3, Gy4, Gy5. -Ill. 135786.doc 200937872 In Fig. 80B, as in Fig. 62B, respectively, the 'character bit group Gyi is the meta-bit yQ, yi belongs to the 'character bit group Gy2-character bit The heart belongs to, the symbol element group Gys is the symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element bit "Mountain belongs, the symbol element group Gy5 system symbol element ys Y9 belongs to Fig. 81. The LDPC code is an LDPC code whose code length is N*162〇〇 and the coding rate is 5/6. The further modulation is 1〇24QAM, and the multiple 1 is 1 Rules The distribution rules in Figure 81 specify group information (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3, Gy5, l), (Gb4, Gy4, l). That is, the allocation rule in Figure 81 is defined as follows: According to the group set information (Gb^Gy^l), the error probability first good code group The 1 bit of the code bit of the group Gbi is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb2, Gyi, 2) ' Error probability 2nd good code bit group Gb2 code position 2 bits of the element, assigned to the 2nd bit of the symbol element Gy丨 of the first good symbol group of the error probability; according to the group set information (Gb>2, Gy2, 2) 'The error probability 2 bits of the code bit of the second good code bit group Gb2, allocated to the 2 bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information ( Gb2, Gy3, 2) 'The 2 bits of the code bit of the second good symbol bit group Gb2 of the error probability are assigned to the symbol bit of the symbol group Gy3 of the third good error probability group. 2 bits; 135786.doc • 112· 200937872 According to the group set information (Gb^Gy^l), the unit of the code bit of the second good symbol group Gbz of the error probability is assigned to the error probability. The 5th good symbol group Gy5 symbol bit unit; according to the group set information (Gb3, Gys, l), the code probability of the 3rd good code bit group Gbs The 丨 丨 丨 , , , , , 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元The 1st bit of the code bit of the 4th good code bit group GW is assigned to the error probability. 4 © 1 bit of the symbol bit of the good symbol bit group Gy*. An alternative example of the code bit according to the allocation rule of Fig. 81. That is, Fig. 82A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and further modulation is 1〇24QAM. In the case where the multiple b is 1, the first example of the replacement of the code bits according to the allocation rule of FIG. 81 is used. The LDPC code is an LDpc code with a code length N of 16200 bits and a coding rate of 5/6. In the case where the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25' is in the longitudinal direction X horizontally. The code direction of the column direction is (162〇〇/(1〇xi))x (10 χ 1) bits. The code bits written in the row are in the horizontal direction, with l〇xl (= mb) bits. The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the m-bit b〇 to 1> 9' read from the memory 3's l〇xl (= mb) bit in accordance with the allocation rule of Fig. 81, for example, as shown in Fig. 82A to l (=b). The symbolic bits "to" of the i〇xi (= mb) bits of the symbol are replaced by the code bits b〇 to b9 of the l〇xl (= mb) bits. 135786.doc -113 - 200937872 Ο That is, the 'replacement unit 32 assigns the code bit b〇 to the symbol bit y6, respectively, and assigns the code bit b! to the symbol bit y4 to assign the code bit b2 to the symbol The meta-bit y8 assigns the code bit b3 to the symbol bit y5, the code bit b4 to the symbol bit y, the code bit b5 to the symbol bit y2, and the code bit b6 to the symbol The bit yi assigns the code bit b7 to the symbol bit y3. The code bit b8 is assigned to the symbol bit y9. The code bit b9 is assigned to the symbol bit y7 for replacement. 82B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a bat rate of 5/6, and the further modulation method is 1024QA]VI. In the case of multiples, the replacement of the code bits according to the allocation rule of FIG. 81 is performed. The second example. According to FIG. 82B, the replacing unit 32 performs the following steps according to the allocation rule of FIG. 81, and the stitches of the i〇xl (= mb) bits read from the memory 31 are respectively ~~%. Replace: assign the code bit b〇 to the symbol bit y7, assign the code bit b! to the symbol bit y8, assign the code bit b2 to the symbol bit y3, and assign the code bit b3 to The symbol bit y4 assigns the code bit b4 to the symbol bit y 5 and the code bit b5 to the symbol bit y 〇, 135786.doc • 114· 200937872 assigns the code bit b6 to the symbol The bit y2 assigns the code bit b7 to the symbol bit y 1, assigns the code bit b8 to the symbol bit y9, and assigns the code bit b9 to the symbol bit y6. 83 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and the modulation bit is 1024QAM, and the multiple of b is 1 and the code bit group and the symbol bit are Group. In this case, the code bit source of the l〇xl (= mb) bit read from the memory 31 can be grouped into 4 code bit groups as shown in FIG. 83A according to the difference in error probability. Gb 1, Gb2, Gb3, Gb4. In FIG. 83A, respectively, the code bit group Gb 1 belongs to the code bit b〇, the code bit group Gb2 belongs to the code bits b! to b7, and the code bit group Gb3 is the code bit. Bs belongs to, and the code bit group Gb4 belongs to the code bit b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol positions as shown in FIG. 83B. The meta group Gy^Gy^Gy^Gy^Gys. In Fig. 83B, the same as Fig. 62B, respectively, the symbol bit group Gy! is represented by the symbol bit yG, yi, and the symbol bit group Gy2 is the symbol bit y2, y3 belongs to The meta-bit group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy4 is the symbol element y6, y7 belongs to, and the symbol element group Gy5 is the symbol element ys, y9 belongs. Fig. 84 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and a further modulation method of 1024QAM and a multiple b of 1. 135786.doc -115- 200937872 The distribution rule in Figure 84 specifies the group collection information (GbiGy4i), (〇^5〇Υι, 2), (0525072, 2), (0^, 〇Υ 3, 2), (〇^,〇Υ5,ι)?(<31)3 j} ? (Gb4, Gy4, 1). That is, the allocation rule in FIG. 84 is defined as follows: According to the group set information (Gb!, Gy4, 1), the 1 bit of the code bit of the coded bit group Gh of the first error probability group is allocated. Give 1 bit of the symbol bit of the symbol group Gy4 with a good probability of error; according to the group set information (Gb2, Gy!, 2) 'The error probability is 2nd good © code bit group The 2 bits of the code bit of the group Gh are allocated to the 2 bits of the symbol bit of the symbol i-good symbol group Gy of the error probability; according to the group set information (Gb2, Gy2, 2), Assigning 2 bits of the code bit of the second good symbol bit group Gh of the error probability to the 2 bits of the symbol bit of the second good symbol bit group Gy2 of the error probability; The set information (Gb2, Gy3, 2) assigns the 2 bits of the code bit of the second good code bit group Gb2 of the error probability to the symbol of the error probability 3^good symbol bit group Gy3 2 bits of the meta-bit; 分配 According to the group set information (Gb2, Gys, l), assign 1 bit of the code bit of the 2nd good code bit group Gb2 of the error probability to the error probability of $ 1 bit of the symbol element of the good symbol group Gy5; according to the group set information (Gh>3, Gy5, 1), the code position of the 3rd good code bit group Gbs of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the error probability ^^good symbol bit group Gy5; and according to the group set information (Gb^Gy4,1), the error probability is 4th A good bit of the bit group Gb>4 is allocated to the error probability. * I35786.doc • 116· 200937872 A good bit of the symbol bit of the symbol group. Figure 85 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 84. That is, FIG. 85A shows that the LDPC code is an LDPC code having a code length of 648 bits and a coding rate of 5/6, and further modulation is 1〇24QAM, and the multiple b is 1 according to FIG. 84. The first example of the replacement of the code bits of the distribution rule
LDPC碼疋碼長n為64800位元、編碼率為5/6之LDPC 碼,進一步調變方式為1〇24QAM、倍數1)為1之情況下,於 © 解多工器25,於縱行方向X橫列方向為(6480 0/( l〇xl))x (10 X 1)位元之記憶體3丨寫入之碼位元係於橫列方向以 l〇xl(*~mb)位元單位讀出,並供給至替換部32(圖16、圊 17)。 替換部32係按照圖84之分配規則,將讀出自記憶體3 1之 l〇xl(=mb)位元之碼位元b()至&,例如圖85A所示分配給 U=b)個符元之i〇xl(=rnb)位元之符元位元乂❶至“,以替換 l〇xl(=mb)位元之碼位元b()至b9。 亦即,替換部32係分別 將石馬位元bG分配給符元位元y6, 將碼位元b〗分配給符元位元y 4, 將碼位元b2分配給符元位元y8, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y〇, 將碼位元b5分配給符元位元y2, 將碼位元b6分配給符元位元y i ’ 135786.doc •117· 200937872 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖85B係表示LDPC碼是碼長N為64800位元、編碼率為 5/6之LDPC碼,進一步調變方式為1024QAM,倍數b為1之 情況下之按照圖84之分配規則之碼位元之替換之第2例。LDPC code 疋 code length n is 64800 bits, encoding rate is 5/6 LDPC code, further modulation mode is 1〇24QAM, multiple 1) is 1 in the case of © multiplexer 25, in the vertical line The direction of the X direction is (6480 0 / ( l 〇 xl)) x (10 X 1) bits of the memory 3 丨 written code bits are in the horizontal direction with l 〇 xl (* ~ mb) bits The unit is read out and supplied to the replacement unit 32 (Fig. 16, 圊 17). The replacing unit 32 assigns the code bit b() read from the l〇xl (= mb) bit of the memory 3 1 to & according to the allocation rule of FIG. 84, for example, as shown in FIG. 85A to U=b). The symbol of the i〇xl (=rnb) bit of the symbol is "to replace the code bit b() of the l〇xl (= mb) bit to b9. That is, the replacement section 32 The stone horse bit bG is assigned to the symbol bit y6, the code bit b is assigned to the symbol y 4 , the code bit b2 is assigned to the symbol y8 , and the code bit b3 is allocated For the symbol bit y5, the code bit b4 is assigned to the symbol bit y, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to the symbol bit yi ' 135786.doc • 117· 200937872 assigns the code bit b7 to the symbol bit y3, assigns the code bit b8 to the symbol bit y9, and assigns the code bit b9 to the symbol bit y7 for replacement. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6. The further modulation method is 1024QAM, and the multiple of the code bits of the allocation rule of FIG. The second case.
若根據圖85B,替換部32係按照圖84之分配規則,針對 從記憶體3 1所讀出之10X 1 (=mb)位元之碼位元bG至b9,分 別進行下述替換: 將碼位元bG分配給符元位元y7, 將碼位元b!分配給符元位元y 8, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y 1, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y6。 圖86係表示LDPC碼是碼長N為16200位元、編碼率為8/9 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之l〇xl(=mb)位元之碼位 135786.doc -118- 200937872 元係根據錯誤概率之差別,如圖86A所示可群組區分為5個 碼位元群組 Gbi,Gb2,Gb3,Gb4,Gl>5。 於圖86A ’分別而言’碼位元群組〇1)1係碼位元b〇所屬, 碼位元群組Gt>2係碼位元b!所屬,碼位元群組〇b3係碼位元 b2至b>7所屬’碼位元群組Gb>4係碼位元1)8所屬,碼位元群組 Gb〗係碼位元bg所屬。 調變方式為1024QAM,倍數b為1之情況下,i〇xi(=mb) 位元之符元位元係根據錯誤概率之差別,如圖86B所示可 © 群組區分為5個符元位元群組0丫1,0丫2,0丫3,0丫4,0丫5。 於圖86B ’與圖62B相同’分別而言,符元位元群組Gy丨 係符元位元yG,y〗所屬,符元位元群組Gy2係符元位元y2,y3 所屬’符元位元群組Gy3係符元位元y4,y5所屬,符元位元 群組Gy*係符元位元y6,y·;所屬,符元位元群組〇75係符元位 元ys,y9所屬。 圖8 7係表示LDPC瑪是碼長N為16200位元、編碼率為8/9 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 〇 w 況下之分配規則。 於圖87之分配規則,規定有群組集合資訊…、々”」), (Gb2,Gy!, l),(Gb3,Gyi5l),(Gb3,Gy2,2),(Gb3,Gy3,2),(Gb3,Gy4,l), (Gb4,Gy5,l),(Gb5,Gy4,l)。 亦即,於圖87之分配規則,規定如下: 根據群組集合資訊(Gbl5Gy5,l),將錯誤概率第1良好之 碼位元群組Gb!之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy 5之符元位元之1位元; 135786.doc .119· 200937872 根據群組集合資訊(Gt^Gyhl),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之!位元,分配給錯誤概率第^良 好之符元位元群組Gy,之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之丨位元,分配給錯誤概率第工良 好之符元位元群組Gy〗之符元位元之丨位元; 根據群組集合資訊(Gb3,Gy2,2),將錯誤概率第3良好之 碼位兀群組Gh之碼位元之2位元,分配給錯誤概率第2良 ® 好之符元位元群組Gy〗之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊,將錯誤概率第3良好之 碼位元群組Gb3之碼位元之丨位元,分配給錯誤概率良 好之符元位元群組Gy4之符元位元之1位元; 〇 根據群組集合資訊(Gb^GhD,將錯誤概率第4良好之 碼位το群組Gh之碼位元之丨位元,分配給錯誤概率第$良 好之符元位元群組(Jy5之符元位元之i位元; 4 及根據群組集合資訊⑽…^丨),將錯誤概率第$良好 之碼位元群組Gb5之碼位元之i位元,分配給錯誤概率P 良好之符元位元群組Gy《之符元位元之丨位元。 圖88係表示按照圖87之分配規則之碼位元之替換例。 亦即,圖88A係表示LDPC碼是碼長Ng162〇〇位元、編 碼率為8/9之LDPC碼’進_步調變方式為1〇24qam,倍數 135786.doc 200937872 b為1之情況下之按照圖87之分配規則之碼位元之替換之第 1例0 LDPC瑪是瑪長N為16200位元、編碼率為8/9之ldpc 碼’進一步調變方式為l〇24QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(ΐ62〇〇/(1〇χ1))χ (1〇χ1)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出’並供給至替換部32(圖16、圖 17) 〇 替換部32係按照圖87之分配規則,將讀出自記憶體3丨之 l〇xl(=mb)位元之碼位元〜至!^,例如圖88A所示分配給 1(-b)個符元之i〇x 位元之符元位元“至乃,以替換 l〇xl(=mb)位元之碼位元b()至b9。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元bi分配給符元位元y〇, 將碼位元b 2分配給符元位元y!, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y6 ’ 將碼位元b7分配給符元位元y5, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 135786.doc -121 - 200937872 圖88B係表示LDPC碼是碼長N為16200位元、編碼率為 8/9之LDPC碼,進一步調變方式為1024QAM,倍數b為1之 情況下之按照圖87之分配規則之碼位元之替換之第2例。 若根據圖88B,替換部32係按照圖87之分配規則,針對 從記憶體3 1所讀出之10X 1 (=mb)位元之碼位元bG至b9,分 別進行下述替換: 將碼位元bG分配給符元位元ys», 將碼位元b 1分配給符元位元y 1, © 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 將碼位元b 8分配給符元位元y 8, 將碼位元b9分配給符元位元y6。 ❹ 圖89係表示LDPC碼是碼長N為64800位元、編碼率為8/9 之LDPC碼,進一步調變方式為1024QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之l〇xl(=mb)位元之碼位 元係根據錯誤概率之差別,如圖89A所示可群組區分為5個 碼位元群組 Gbi,Gb2,Gb3,Gb4,Gb5。 於圖89A,分別而言,碼位元群組01^係碼位元bG所屬, 碼位元群組Gb2係瑪位元bi所屬,碼位元群組Gb3係碼位元 135786.doc -122- 200937872 h至b所屬,碼位元群組〇134係碼位元b8所屬,碼位元群組 Gb5係瑪位元b9所屬。 調變方式為1024QAM,倍數b為1之情況下,l〇xi(=mb) 位元之符元位元係根據錯誤概率之差別,如圖8 9B所示可 群組區分為5個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5。 於圖89B,與圖62B相同,分別而言,符元位元群組Gyi 係符元位元yG,yi所屬,符元位元群組Gy2係符元位元y2,y3 所屬’符元位元群組Gy3係符元位元y4,y5所屬,符元位元 © 群組Gy4係符元位元y0,y7所屬,符元位元群組Gy5係符元位 元ys,y9所屬。 圖90係表示LDPC碼是碼長N為64800位元、編碼率為8/9 之LDPC碼,進一步調變方式為1 〇24QAM,倍數b為1之情 況下之分配規則。 於圖90之分配規則,規定有群組集合資訊(Gbi,Gy5 l), (Gb2,Gy1,l),(Gb3,Gyi,l),(Gb3,Gy252),(Gb3,Gy3,2),(Gb3,Gy4,l)i (Gb4,Gy5,l),(Gb5,Gy4,l)。 ’ 亦即,於圖90之分配規則,規定如下: 根據群組集合資訊(Gbi,Gy,,1) ’將錯誤概率第1良好之 碼位元群組Gb!之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb2,Gyi,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第1良 好之符元位元群組之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好之 135786.doc 200937872 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第1良 好之符元位元群組〇丫丨之符元位元之1位元; 根據群組集合資訊(Gb3,Gy2,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 〇 根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb4,Gy5,l),將錯誤概率第4良好之 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gb5,Gy4,l),將錯誤概率第5良好 之碼位元群組Gb5之碼位元之1位元,分配給錯誤概率第4 ® 良好之符元位元群組Gy4之符元位元之1位元。 圖91係表示按照圖90之分配規則之碼位元之替換例。 亦即,圖91A係表示LDPC碼是碼長N為64800位元、編 碼率為8/9之LDPC碼,進一步調變方式為1024QAM,倍數 b為1之情況下之按照圖90之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長N為64800位元、編碼率為8/9之LDPC 碼,進一步調變方式為1024QAM、倍數b為1之情況下,於 135786.doc -124- 200937872 解多工器25,於縱行方向χ橫列方向為(64800/^ 〇χ1))χ (l〇xl)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(-mb)位元單位讀出,並供給至替換部32(圖16、圖 17) ° 替換部32係按照圖90之分配規則,將讀出自記憶體3丨之 l〇xl(=mb)位元之碼位元bQ至h,例如圖91A所示分配給 l(=b)個符元之l〇xl(=mb)位元之符元位元”至乃,以替換 l〇xl(=mb)位元之碼位元1^至b9。 Ο 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b〗分配給符元位元y〇, 將碼位元b〗分配給符元位元y j, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y6,According to Fig. 85B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 84: The bit bG is assigned to the symbol bit y7, the code bit b! is assigned to the symbol bit y 8, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Y4, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol The meta-bit y 1, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y6. 86 is a diagram showing that an LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code bits 135786.doc -118- 200937872 of the l〇xl (= mb) bit read from the memory 31 are grouped into 5 according to the difference in error probability as shown in FIG. 86A. One code bit group Gbi, Gb2, Gb3, Gb4, Gl>5. In Fig. 86A, respectively, 'the code bit group 〇1) 1 is the code bit b〇, the code bit group Gt>2 is the code bit b! belongs to, the code bit group 〇b3 code Bits b2 to b>7 belong to the 'code bit group Gb>4 code bit 1)8, and the code bit group Gb is associated with the code bit bg. When the modulation mode is 1024QAM and the multiple b is 1, the symbol of the i〇xi(=mb) bit is different according to the error probability. As shown in Fig. 86B, the group can be divided into 5 symbols. The bit group 0丫1, 0丫2, 0丫3, 0丫4, 0丫5. 86B 'same as FIG. 62B', respectively, the symbol bit group Gy丨 symbol bit yG, y〗 belongs to, the symbol bit group Gy2 is the symbol bit y2, y3 belongs to the 'character The meta-bit group Gy3 is a symbol element y4, y5 belongs to, the symbol element group Gy* is a symbol element y6, y·; belongs to, the symbol-bit group 〇75-character bit ys , y9 belongs. 8 is a diagram showing an LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and the modulation mode is 1024QAM, and the multiple b is 1. In the allocation rule of Figure 87, there is a group collection information..., 々""), (Gb2, Gy!, l), (Gb3, Gyi5l), (Gb3, Gy2, 2), (Gb3, Gy3, 2) , (Gb3, Gy4, l), (Gb4, Gy5, l), (Gb5, Gy4, l). That is, the allocation rule in FIG. 87 is defined as follows: According to the group set information (Gbl5Gy5, l), the 1st bit of the code bit of the coded bit group Gb! of the error probability is assigned to the error. Probability 5th good symbol group Gy 5 symbol 1 bit; 135786.doc .119· 200937872 According to the group collection information (Gt^Gyhl), the error probability is 2nd good code position The code bit of the meta group Gb2! The bit is assigned to the error probability ^^good symbol bit group Gy, the 1-bit element of the symbol bit; according to the group set information (Gb^Gy^l), the error probability is the third good code The unit of the code bit of the bit group Gh is allocated to the bit element of the symbol bit of the symbol bit group Gy with good error probability; according to the group set information (Gb3, Gy2, 2), assigning the error probability 3rd good code bit to the 2 bit of the code bit of the group Gh, and assigning it to the error probability 2nd good ® good symbol bit group Gy Bits; according to the group set information (Gb3, Gy3, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are assigned to the 3rd good symbol bit of the error probability. 2 bits of the symbol bit of the group Gy3; according to the group set information, assign the bit position of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol bit with good error probability 1 bit of the symbol group of the meta group Gy4; 分配 according to the group set information (Gb^GhD, the error probability is the 4th good code bit το group Gh the code bit element, the allocation Give the probability probability of the $th good symbol group (the i bit of the symbol of Jy5; 4 and according to the group collection information (10)...^丨), the error probability of the $good symbol group The i-bit of the code bit of Gb5 is assigned to the bit element of the symbol bit group Gy, which has a good probability probability P. Figure 88 shows the code bit element according to the allocation rule of Fig. 87. In other words, FIG. 88A shows that the LDPC code is a code length Ng 162 bit, and the LDPC code with an encoding rate of 8/9 is 1 〇 24 qam, and the multiple 135786.doc 200937872 b is 1. In the case of the first example of the replacement of the code bits according to the allocation rule of FIG. 87, the LDPC code is an ldpc code with a length of 16200 bits and a coding rate of 8/9. Further modulation is l〇24QAM. When the multiple b is 1, the memory 31 of the (ΐ62〇〇/(1〇χ1))χ(1〇χ1) bit is written in the demultiplexer 25 in the wale direction X. The code bits are in the course direction, read out in units of l〇xl (= mb) bits and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads according to the allocation rule of Fig. 87. From memory The code bit of the l〇xl (=mb) bit is ~ to !^, for example, the symbol bit assigned to the i〇x bit of 1 (-b) symbol as shown in Fig. 88A To replace the code bits b() to b9 of the l〇xl (= mb) bits. That is, the replacement unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit bi For the symbol bit y, assign the code bit b 2 to the symbol bit y!, assign the code bit b3 to the symbol bit y2, and assign the code bit b4 to the symbol bit y3, The code bit b5 is assigned to the symbol bit y4, the code bit b6 is assigned to the symbol bit y6', the code bit b7 is assigned to the symbol bit y5, and the code bit b8 is assigned to the symbol bit y9 , the code bit b9 is assigned to the symbol bit y7, and is replaced. 135786.doc -121 - 200937872 Figure 88B shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 8/9. The further modulation method is 1024QAM, and the multiple b is 1. The second example of the replacement of the code bits of the distribution rule. According to Fig. 88B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 87: The bit bG is assigned to the symbol bit ys», the code bit b 1 is assigned to the symbol bit y 1, © the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol Bit y4, assign code bit b4 to symbol bit y5, assign code bit b5 to symbol bit y 〇, assign code bit b6 to symbol y2, assign code bit b7 To the symbol bit y7, the code bit b 8 is assigned to the symbol bit y 8, and the code bit b9 is assigned to the symbol bit y6. ❹ FIG. 89 shows that the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 8/9, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the l〇x1 (= mb) bits read from the memory 31 are group-divided into 5 code bit groups Gbi according to the difference in error probability as shown in FIG. 89A. , Gb2, Gb3, Gb4, Gb5. 89A, respectively, the code bit group 01^ is the code bit bG, the code bit group Gb2 belongs to the mbit bi, and the code bit group Gb3 is the code bit 135786.doc -122 - 200937872 h to b belongs, the code bit group 〇 134 is the code bit b8, and the code bit group Gb5 belongs to the mbit b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of l〇xi(=mb) bits are different according to the error probability. As shown in Figure 8 9B, the group can be divided into 5 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 89B, as in FIG. 62B, respectively, the symbol bit group Gyi is associated with the symbol bit yG, yi, and the symbol bit group Gy2 is the symbol bit y2, and the y3 belongs to the 'character bit. The meta-group Gy3 is a symbol element y4, y5 belongs to, the symbol element bit © group Gy4 is a symbol element y0, y7 belongs to, the symbol element group Gy5 is a symbol element ys, y9 belongs. Fig. 90 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and an encoding rate of 8/9, and a further modulation method of 1 〇 24QAM and a multiple b of 1. In the distribution rule of FIG. 90, group collection information (Gbi, Gy5 l), (Gb2, Gy1, l), (Gb3, Gyi, l), (Gb3, Gy252), (Gb3, Gy3, 2), (Gb3, Gy4, l)i (Gb4, Gy5, l), (Gb5, Gy4, l). That is, the allocation rule in Fig. 90 is defined as follows: According to the group set information (Gbi, Gy, 1, 1) '1 bit of the code bit of the error probability first good code bit group Gb! , assigned to the 1st bit of the symbol bit of the fifth-perfect symbol group Gy5 of the error probability; according to the group set information (Gb2, Gyi, l), the error probability second good symbol group One bit of the code bit of the group Gb2 is assigned to the 1-bit of the symbol bit of the first good symbol bit group of the error probability; according to the group set information (Gb^Gy^l), the error is Probability 3rd good 135786.doc 200937872 Code bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the first good symbol bit group According to the group set information (Gb3, Gy2, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are assigned to the 2nd good symbol bit group with the error probability 2 bits of the symbol bit of Gy2; according to the group set information (Gb3, Gy3, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are allocated The error probability is the third good symbol bit group Gy3 symbol bit 2 bit; 〇 according to the group set information (Gb3, Gy4, l), the error probability third good code bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb4, Gy5, l), the error probability 1 bit of the code bit of the 4th good code bit group Gb4, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; (Gb5, Gy4, l), assigning the 1st bit of the code bit of the 5th good code bit group Gb5 of the error probability to the symbol of the error probability 4 ® good symbol bit group Gy4 One yuan of yuan. Figure 91 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 90. That is, FIG. 91A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and the further modulation method is 1024QAM, and the multiple b is 1 in accordance with the distribution rule of FIG. The first example of the replacement of the code bit. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 8/9. When the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25 is solved at 135786.doc -124-200937872. In the wale direction, the direction of the column is (64800/^ 〇χ1)) χ (l〇xl) bits of the memory 31 are written in the horizontal direction, in the order of l〇xl (-mb) The unit is read out and supplied to the replacing unit 32 (Fig. 16, Fig. 17). The replacing unit 32 reads the code position of the l〇xl (= mb) bit from the memory 3 in accordance with the allocation rule of Fig. 90. The elements bQ to h, for example, are assigned to l(xb) bits of l(=b) symbols as shown in Fig. 91A, to replace l〇xl(=mb) bits. The code bits 1^ to b9. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit b to the symbol bit y, and sets the code bit. The element b is assigned to the symbol bit yj, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, and the code bit b5 is assigned to the symbol bit y4. The code bit b6 is assigned to the symbol bit y6,
A 將碼位元b 7分配給符元位元y 5, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y 7, 而進行替換。 圖91B係表示LDPC碼是碼長N為64800位元、編碼率為 8/9之LDPC碼’進一步調變方式為1〇24QAM,倍數b為1之 情況下之按照圖90之分配規則之碼位元之替換之第2例。 若根據圖91B’替換部32係按照圖90之分配規則,針對 135786.doc -125- 200937872 從記憶體31所讀出之l〇xl(=mb)位元之碼位元^至、,分 別進行下述替換: 將碼位元b〇分配給符元位元y9, 將碼位元b 1分配給符元位元y!, 將碼位元ba分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, © 將碼位元b 6分配給符元位元y 2, 將碼位元b?分配給符元位元, 將碼位元bs分配給符元位元y8, 將碼位元bg分配給符元位元y6。 圖92係表不LDPC碼是碼長N為64800位元、編碼率為 9/10之LDPC碼,進一步調變方式為1024QAM,倍數b為1 之情況下之碼位元群組及符元位元群組。 該情況下’從記憶體31所讀出之l〇xi (=mb)位元之碼位 元係根據錯誤概率之差別,如圖92A所示可群組區分為3個 碼位元群組Gb!,Gb2,Gb3。 於圖92A ’分別而言,碼位元群組Gb〗係碼位元b〇所屬, 碼位元群組Gt>2係碼位元b!至bs所屬,碼位元群組Gb3係碼 位元b9所屬。 調變方式為1024QAM,倍數b為1之情泥下,i〇x i(=mb) 位元之符元位元係根據錯誤概率之差別,如圖92B所示可 群組區分為5個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5。 135786.doc •126· 200937872 於圖92B,與圖62B相同,分別而言,符元位元群組Gyi 係符元位元yG,yi所屬,符元位元群組Gy2係符元位元y2,y3 所屬’符元位元群組Gy3係符元位元y4,y5所屬,符元位元 群組Gy*係符元位元y6,y?所屬,符元位元群組Gy5係符元位 元ys,y9所屬。 圖93係表示LDPC瑪是碼長N為64800位元、編碼率為 9/10之LDPC碼,進一步調變方式為i〇24QAM,倍數b為1 之情況下之分配規則。 於圖93之分配規則’規定有群組集合資訊(Gbi,Gy5 l), (Gb2}Gy1,2),(Gb2,Gy2,2),(Gb2,Gy3i)2),(Gb2,Gy4,l),(Gb2,Gy5,l), (Gb3,Gy4,l) ° 亦即,於圖93之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l) ’將錯誤概率第1良好之 瑪位元群組Gbi之碼位元之1位元’分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb2,Gy〗,2),將錯誤概率第2良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2),將錯誤概率第2良好之 碼位元群組Oh之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 135786.doc •127- 200937872 根據群組集合資訊(Gbz,Gy4,l),將錯誤概率第2良好之 碼位元群組Gb2之瑪位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之丨位元; 根據群組集合資訊(Gt>2,Gy5,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之丨位元,分配給錯誤概率第5良 好之符元位元群組Gys之符元位元之丨位元; 及根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好 之碼位το群組Gb3之碼位元之丨位元,分配給錯誤概率第4 ® 良好之符元位元群組Gy4之符元位元之1位元。 圖94係表示按照圖93之分配規則之碼位元之替換例。 亦即,圖94A係表示LDPC碼是碼長1^為648〇〇位元編 碼率為9/10之LDPC碼,進一步調變方式為1〇24QAM,倍 數b為1之情況下之按照圖93之分配規則之碼位元之替換之 第1例。 LDPC碼是碼長N為64800位元、編碼率為9/1〇之LDpc 碼,進一步調變方式為l〇24QAM、倍數匕為】之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(1〇><1)> (10x1)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部3 2係按照圖9 3之分配規則’將讀出自記憶體3 1之 l〇xl(=mb)位元之碼位元bG至b?,例如圖94A所示分配給 U=b)個符元之l〇x1(=mb)位元之符元位。至y9,以替換 l〇xl(=mb)位元之碼位元bG至b9。 135786.doc -128- 200937872 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元b〗分配給符元位元y〇, 將碼位元b2分配給符元位元y!, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元1)彡分配給符元位元八, © 將碼位元b7分配給符元位元y5, 將碼位元be分配給符元位元y9, 將碼位元b9分配給符元位元y7, 而進行替換。 圖94B係表示LDPC碼是碼長N為64800位元、編碼率為 9/10之LDPC碼’進一步調變方式為i〇24QAM,倍數b為1 之情況下之按照圖93之分配規則之碼位元之替換之第2 例。 若根據圖94B,替換部32係按照圖93之分配規則,針對 從記憶體31所讀出之l〇xl(=mb)位元之碼位元bQ至h,分 別進行下述替換: 將碼位元b〇分配給符元位元y8, 將碼位元1^分配給符元位元y6, 將碼位元b2分配給符元位元y 9, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 135786.doc •129· 200937872 將碼位元分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y 1, 將碼位元b8分配給符元位元y3, 將碼位元b9分配給符元位元y7。 圖95係表示LDPC碼是碼長N為16200位元、編碼率為2/3 之LDPC碼,進一步調變方式為4096QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 〇 該情況下,從記憶體31所讀出之12xl(=mb)位元之碼位 元係根據錯誤概率之差別,如圖95 A所示可群組區分為3個 碼位元群組01>1,012,0匕3。 於圖95A,分別而言,碼位元群組Gb!係碼位元b〇所屬, 碼位元群組Gb2係碼位元bi至b7所屬,碼位元群組Gb3係碼 位元b8至th !所屬。 調變方式為4096QAM,倍數b為1之情況下,12xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖95B所示可 ® 群組區分為6個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖95B,分別而言,符元位元群組Gy〗係符元位元y〇,yi 所屬,符元位元群組Gy2係符元位元y2,y3所屬,符元位元 群組Gy3係符元位元y4,y5所屬,符元位元群組Gy4係符元位 元y6,y7所屬,符元位元群組Gy5係符元位元y8,y9所屬’符 元位元群組Gy6係符元位元yi〇,yii所屬。 圖96係表示LDPC碼是碼長N為16200位元、編碼率為2/3 之LDPC碼,進一步調變方式為4096QAM,倍數b為1之情 135786.doc •130- 200937872 況下之分配規則。 於圖96之分配規則,規定有群組集合資訊(Gbi Gy6 l), (Gb25Gyl52),(Gb2,Gy252),(Gb2jGy352),(Gb2>Gy45i)5(Gb3Gy4jl)5 (Gb3,Gy5,2),(Gb3,Gy6,l)。 亦即,於圖96之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l),將錯誤概率第i良好之 碼位元群組Gb!之碼位元之1位元’分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; © 根據群組集合資訊(Gb2,Gyi,2) ’將錯誤概率第2良好之 瑪位元群組Gbz之碼位元之2位元’分配給錯誤概率第1良 好之符元位元群組Gy 1之符元位元之2位元; 根據群組集合資訊(Gt>2,Gy2,2) ’將錯誤概率第2良好之 碼位元群組Gh之碼位元之2位元’分配給錯誤概率第2良 好之符元位元群組Gyz之符元位元之2位元; 根據群組集合資訊(GbhGyy),將錯誤概率第2良好之 ❹碼位元群組之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb^Gkl),將錯誤概率第2良好之 碼位7L群組Gbz之碼位元之丨位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 根據群組集合資訊(GbhGki),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之丨位元; 根據群組集合資訊(Gb3,Gy5,2),將錯誤概率第3良好之 135786.doc -131 · 200937872 碼位元群組Gb3之碼位元之2位元,分配给㈣㈣ 好之符元位元群組Gys之符元位元之2位元; 义 及根據群組集合資訊(Gl^Gy^),將錯誤概率第3良好 之碼位元群組Gb3之碼位元之i位元,分配給錯誤概率第6 良好之符元位元群組Gye之符元位元之1位元。 圖97係表示按照圖96之分配規則之碼位元之替換例。 亦即,圖97A係表示LDPC碼是碼長\為162〇〇位元編 碼率為2/3之LDPC碼,進-步調變方式為4〇96qam,倍數 © b為1之情況下之按照圖96之分配規則之碼位元之替換之第 1例。 LDPC碼是碼長>^為162〇〇位元、編碼率為2/3之[ο% 碼,進一步調變方式為4〇96QAM、倍數之情況下於 解多工器25,於縱行方向X橫列方向為(162〇〇/(12χΐ))χ (12 X 1)位元之s己憶體3 1寫入之碼位元係於橫列方向,以 12xl(=mb)位元單位讀出’並供給至替換部32(圖16、圖 17) 〇 替換部32係按照圖96之分配規則,將讀出自記憶體3 1之 12><1(=11113)位元之碼位元1)()至1)11,例如圖97八所示分配給 l(-b)個符元之i2xl(=mb)位元之符元位元y〇至yu,以替換 12xl(=mb)位元之碼位元至bn。 亦即’替換部32係分別 將碼位元bQ分配給符元位元乃〇, 將碼位元b〗分配給符元位元y〇, 將碼位元b2分配給符元位元yi, 135786.doc -132- 200937872 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b 5分配給符元位元y 4, 將碼位元b6分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y7, 將碼位元b 1 〇分配給符元位元y 11, 〇 將碼位元bn分配給符元位元y9, 而進行替換。 圖97B係表示LDPC碼是碼長N為16200位元、編碼率為 2/3之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖96之分配規則之碼位元之替換之第2例。 若根據圖97B,替換部32係按照圖96之分配規則,針對 從記憶體31所讀出之12x1 (=mb)位元之碼位元bG至bn ’分 別進行下述進替換: ® 將碼位元bG分配給符元位元y 11, 將碼位元b!分配給符元位元y 1, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b 5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 135786.doc •133· 200937872 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y6, 將碼位元b i 〇分配給符元位元y 1 〇, 將碼位元b! 1分配給符元位元y 8。 圖98係表示LDPC碼是碼長N為64800位元、編碼率為2/3 之LDPC碼,進一步調變方式為4096QAM,倍數b為1之情 況下之碼位元群組及符元位元群組。 該情況下,從記憶體3 1所讀出之12 X 1 (=mb)位元之碼位 〇 元係根據錯誤概率之差別,如圖98A所示可群組區分為3個 碼位元群組Gbi,Gb2,Gb3。 於圖98A,分別而言,碼位元群組Gth係碼位元b〇所屬, 碼位元群組Gb2係碼位元b i至b7所屬,碼位元群組Gb3係碼 位元b8至bu所屬。 調變方式為4096QAM,倍數b為1之情況下,12xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖98B所示可 群組區分為6個符元位元群組Gy^Gj^Gy^Gy^Gy^Gys。 ® 於圖98B,與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元y^y!所屬,符元位元群組Gy2係符元位 元y2,y3所屬,符元位元群組Gy3係符元位元y4,y5所屬’符 元位元群組Gy4係符元位元y6,y7所屬,符元位元群組Gy5係 符元位元y8,y9所屬,符元位元群組Gy6係符元位元yi〇,yii 所屬。 圖99係表示LDPC碼是碼長N為64800位元、編碼率為2/3 之LDPC碼,進一步調變方式為4096QAM,倍數b為1之情 135786.doc -134- 200937872 況下之分配規則。 於圖99之分配規則,規定有群組集合資訊 (Gb2,Gy1,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy4,l),(Gb3,Gy4,l)> (Gb3,Gy5,2),(Gb3,Gy6,l)。 亦即,於圊99之分配規則,規定如下: 根據群組集合資訊(Gbi,Gy6,1)’將錯誤概率第1良好之 碼位元群組Gb!之瑪位元之1位元’分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; ❹ 根據群組集合資訊(Gb2,Gy ι,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元’分配給錯誤概率第1良 好之符元位元群組Gy〗之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之2位元’分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gys之符元位元之2位元; 根據群組集合資訊(GbhGykl),將錯誤概率第2良好之 碼位元群組Gh之碼位元之i位元,分配給錯誤概率 <第4良 好之符元位元群組Gy4之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第*良 好之符元位元群組Gy*之符元位元之1位元; 根據群組集合資訊(Gb3,Gy5,2),將錯誤概率第3良好之 135786.doc -135- 200937872 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第5良 好之符元位元群組Gys之符元位元之2位元; 及根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好 之碼位元群組Gh之碼位元之1位元,分配給錯誤概率第6 良好之符元位元群組Gy0之符元位元之丨位元。 圖100係表示按照圖99之分配規則之碼位元之替換例。 亦即,圖100A係表示LDPC碼是碼長]^為648〇〇位元、編 碼率為2/3之LDPC碼,進一步調變方式為4〇96qAM,倍數 〇 b為1之情況下之按照圖99之分配規則之碼位元之替換之第 1例0A assigns the code bit b 7 to the symbol bit y 5 , assigns the code bit b8 to the symbol bit y9 , and assigns the code bit b9 to the symbol bit y 7 for replacement. 91B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9. The further modulation method is 1〇24QAM, and the multiple b is 1 in the case of the allocation rule according to FIG. The second example of the replacement of the bit. According to FIG. 91B, the replacement unit 32 is in accordance with the allocation rule of FIG. 90, and the code bits ^ to , respectively, read from the memory 31 of 135786.doc -125-200937872 The following replacement is performed: the code bit b〇 is assigned to the symbol bit y9, the code bit b1 is assigned to the symbol bit y!, the code bit ba is assigned to the symbol bit y3, and the code bit is The element b3 is assigned to the symbol bit y4, the code bit is assigned to the symbol bit y 5 , the code bit b5 is assigned to the symbol bit y , and the code bit b 6 is assigned to the symbol bit . y 2, the code bit b? is assigned to the symbol bit, the code bit bs is assigned to the symbol bit y8, and the code bit bg is assigned to the symbol bit y6. FIG. 92 shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the l〇xi (=mb) bit read from the memory 31 are group-divided into three code bit groups Gb according to the difference in error probability as shown in FIG. 92A. !, Gb2, Gb3. In Fig. 92A', respectively, the code bit group Gb is associated with the code bit b〇, the code bit group Gt> 2 is the code bit b! to bs, and the code bit group Gb3 is the code bit. Yuan b9 belongs. The modulation mode is 1024QAM, and the multiple b is 1. The i〇xi(=mb) bit symbol is based on the difference in error probability. As shown in Fig. 92B, the group can be divided into 5 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 135786.doc • 126· 200937872 In Fig. 92B, as in Fig. 62B, respectively, the symbol bit group Gyi is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2. , y3 belongs to the 'character bit group Gy3 system symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element y6, y? belongs to, the symbol element group Gy5 symbol Bits ys, y9 belong. Fig. 93 shows an LDPC code in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and the modulation method is i〇24QAM, and the multiple b is 1. The distribution rule in Figure 93 specifies group information (Gbi, Gy5 l), (Gb2}Gy1, 2), (Gb2, Gy2, 2), (Gb2, Gy3i) 2), (Gb2, Gy4, l) ), (Gb2, Gy5, l), (Gb3, Gy4, l) ° That is, the distribution rule in Figure 93 is as follows: According to the group collection information (Gb^Gy^l) 'The error probability is 1st good 1 bit of the code bit of the Gigabit group Gbi is assigned to the 1st bit of the symbol bit of the symbol 5th good symbol bit group Gy5; according to the group set information (Gb2, Gy 〖, 2), the 2 bits of the code bit of the second good symbol bit group Gh of the error probability are assigned to the 2 bits of the symbol bit of the symbol group Gy! According to the group set information (Gb2, Gy2, 2), the 2 bits of the code bit of the second good code bit group Gbz of the error probability are assigned to the second good symbol bit group with the wrong probability. 2 bits of the symbol bit of the group Gy2; according to the group set information (Gb2, Gy3, 2), the 2 bits of the code bit of the second good code bit group Oh of the error probability are assigned to the error Probability 3rd good symbolic group of bits of Gy3, 2 digits of symbolic bits; 135786.do c • 127- 200937872 According to the group set information (Gbz, Gy4, l), the 1st bit of the megabit of the 2nd good code bit group Gb2 of the error probability is assigned to the 4th good symbol of the error probability. The bit element of the symbol group of the bit group Gy*; according to the group set information (Gt > 2, Gy5, l), the code bit of the second good code bit group Gb2 of the error probability The bit element is assigned to the bit element of the symbol bit of the fifth good symbol bit group Gys of the error probability; and the third probability code of the error probability according to the group set information (Gb3, Gy4, l) The τ bit of the code bit of the bit το group Gb3 is assigned to the 1-bit of the symbol bit of the error probability 4 ® good symbol bit group Gy4. Figure 94 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 93. That is, FIG. 94A shows that the LDPC code is an LDPC code having a code length of 1^ of 648 bits and a coding rate of 9/10, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an LDpc code with a code length N of 64,800 bits and a coding rate of 9/1 ,. In the case where the modulation method is l〇24QAM and the multiple is 】, the multiplexer 25 is in the traverse direction. The code bit written in the memory 31 of the X-direction direction is (648〇〇/(1〇><1)> (10x1) bits in the course direction, l〇xl(=mb) The bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 3 2 reads the l〇xl (= mb) bit from the memory 3 1 according to the allocation rule of Fig. 93. The code bits bG to b?, for example, are assigned to the symbol bits of l=x1 (= mb) bits of U=b) symbols as shown in Fig. 94A. To y9, to replace the code bits bG to b9 of the l〇xl (= mb) bits. 135786.doc -128- 200937872 That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit b to the symbol bit y, and assigns the code bit b2 to The symbol bit y!, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b5 is assigned to the symbol bit y4, and the code bit is assigned 1) 彡 is assigned to symbol octet 8, © assigns code bit b7 to symbol y5, assigns code bit be to symbol y9, and assigns bit b9 to y7 , and replace it. 94B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10. The further modulation method is i〇24QAM, and the multiple b is 1, the code according to the allocation rule of FIG. The second example of the replacement of the bit. According to FIG. 94B, the replacing unit 32 performs the following replacement for the code bits bQ to h of the l〇x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 93: Bit b〇 is assigned to symbol bit y8, code bit 1^ is assigned to symbol bit y6, code bit b2 is assigned to symbol bit y 9, and code bit b3 is assigned to symbol bit Element y4, assigning code bit b4 to symbol bit y 5, 135786.doc • 129· 200937872 assigning code bit to symbol bit y〇, and assigning code bit b6 to symbol bit y2, The code bit b7 is assigned to the symbol bit y 1, the code bit b8 is assigned to the symbol bit y3, and the code bit b9 is assigned to the symbol bit y7. 95 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the 12xl (= mb) bits read from the memory 31 are group-divided into 3 code bit groups 01> according to the difference in error probabilities as shown in FIG. 95A. ; 1,012,0匕3. In FIG. 95A, respectively, the code bit group Gb! belongs to the code bit b〇, the code bit group Gb2 belongs to the code bits bi to b7, and the code bit group Gb3 is the code bit b8 to Th ! belongs. When the modulation mode is 4096QAM and the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability. As shown in Fig. 95B, the group can be divided into 6 symbol bits. Groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 95B, respectively, the symbol bit group Gy is a symbol element y 〇, yi belongs to, the symbol bit group Gy2 is a symbol element y2, y3 belongs to, and the symbol element group belongs to Gy3 is a symbol element y4, y5 belongs to, a symbol element group Gy4 is a symbol element y6, y7 belongs to, a symbol element group Gy5 is a symbol element y8, y9 belongs to a 'character bit group Group Gy6 is a symbol element yi〇, yii belongs to. Figure 96 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 2/3, and the modulation method is 4096QAM, and the multiple b is 1 135786.doc • 130-200937872 . In the distribution rule of Fig. 96, group gather information (Gbi Gy6 l), (Gb25Gyl52), (Gb2, Gy252), (Gb2jGy352), (Gb2> Gy45i) 5 (Gb3Gy4jl) 5 (Gb3, Gy5, 2) are specified. , (Gb3, Gy6, l). That is, the allocation rule in FIG. 96 is defined as follows: According to the group set information (Gb^Gy^l), the 1-bit '1' of the code bit of the error probability i-th good code bit group Gb! Give the error probability the sixth good symbol group Gy6 of the symbol bit 1 bit; © according to the group set information (Gb2, Gyi, 2) 'the wrong probability second good matriary group The 2 bits of the code bit of Gbz are assigned to the 2 bit of the symbol bit of the first good symbol bit group Gy 1 of the error probability; according to the group set information (Gt > 2, Gy2, 2) 'Assign the 2 bits of the code bit of the second good code bit group Gh of the error probability to the 2 bit of the symbol bit of the second good symbol bit group Gyz of the error probability; The group set information (GbhGyy) assigns the 2 bits of the code bit of the 2nd good weight bit group of the error probability to the symbol bit of the symbol group Gy3 of the 3rd good error probability group. 2-bit; according to the group set information (Gb^Gkl), the symbol bit of the code bit of the second good code bit 7L group Gbz of the error probability is assigned to the fourth symbol of the error probability 1 bit of the symbol bit of the bit group Gy*; according to the group set information (GbhGki), the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the error probability 4th The good bit element group Gy* is the bit element of the symbol bit; according to the group set information (Gb3, Gy5, 2), the error probability is the third best 135786.doc -131 · 200937872 code bit 2 bits of the code bit of the group Gb3, assigned to (4) (4) 2 bits of the symbol bit of the good symbol bit group Gys; meaning and according to the group set information (Gl^Gy^), will be wrong The i-bit of the code bit of the probability good third bit group Gb3 is assigned to the 1-bit of the symbol bit of the sixth symbol of the error probability bit Gye. Figure 97 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 96. That is, FIG. 97A shows an LDPC code in which the LDPC code is code length \ 162 〇〇 bit coding rate is 2/3, and the step-by-step modulation method is 4 〇 96 qam, and the multiple of the factor b is 1 according to the figure. The first example of the replacement of the code bits of the distribution rule of 96. The LDPC code is 162 bits in code length >^, and the encoding rate is 2/3 [ο% code, further modulation is 4〇96QAM, in the case of multiples in the multiplexer 25, in the vertical line The direction X direction of the direction is (162 〇〇 / (12 χΐ)) χ (12 X 1) bits of the suffix 3 1 written code bits are in the horizontal direction, with 12xl (= mb) bits The unit reads 'and supplies to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads the code of the 12><1 (=11113) bits from the memory 3 in accordance with the allocation rule of Fig. 96. Bits 1)() to 1)11, for example, the symbol bits y〇 to yu assigned to the i2xl (=mb) bits of l(-b) symbols as shown in Fig. 97 and 8, in place of 12xl (= Mb) The bitwise bit of the bit to bn. That is, the 'replacement unit 32 assigns the code bit bQ to the symbol bit, respectively, the code bit b to the symbol bit y, and the code bit b2 to the symbol yi, 135786.doc -132- 200937872 assigning code bit b3 to symbol bit y2, assigning code bit b4 to symbol bit y3, and assigning code bit b 5 to symbol bit y 4, the code Bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, code bit b8 is assigned to symbol bit y8, and code bit b9 is assigned to symbol bit y7. The code bit b 1 〇 is assigned to the symbol bit y 11, and the code bit bn is assigned to the symbol bit y9 for replacement. 97B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and further modulation is 4096QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to Fig. 97B, the replacing unit 32 performs the following replacement for the 12x1 (= mb) bit code bits bG to bn ' read from the memory 31 in accordance with the allocation rule of Fig. 96: The bit bG is assigned to the symbol bit y 11, the code bit b! is assigned to the symbol bit y 1, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Element y4, assigning code bit b4 to symbol bit y5, assigning code bit b 5 to symbol bit y 〇, assigning code bit b6 to symbol y2, and assigning bit b7 The symbol bit y7, 135786.doc • 133· 200937872 assigns the code bit b8 to the symbol bit y9, the code bit b9 to the symbol bit y6, and the code bit bi 〇 to the symbol The bit y 1 〇 assigns the code bit b! 1 to the symbol y 8 . Figure 98 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the 12 X 1 (= mb) bits read from the memory 3 1 are group-divided into 3 code bit groups according to the difference in error probability as shown in FIG. 98A. Group Gbi, Gb2, Gb3. In FIG. 98A, respectively, the code bit group Gth is a code bit b〇, the code bit group Gb2 is a code bit bi to b7, and the code bit group Gb3 is a code bit b8 to bu. Own. When the modulation mode is 4096QAM and the multiple b is 1, the symbol bits of the 12xl (= mb) bits are different according to the error probability. As shown in FIG. 98B, the group can be divided into 6 symbol bit groups. Group Gy^Gj^Gy^Gy^Gy^Gys. In Fig. 98B, as in the case of Fig. 95B, respectively, the symbol bit group Gy! is represented by the symbol bit y^y!, and the symbol bit group Gy2 is the symbol bit y2, y3. Affiliation, the symbol element group Gy3 is a symbol element y4, y5 belongs to the 'character bit group Gy4 is a symbol element y6, y7 belongs to, the symbol element group Gy5 is a symbol element y8, Y9 belongs to, the symbol element group Gy6 is the symbol element yi〇, yii belongs. Figure 99 shows an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method of 4096QAM, a multiple b of 1 135786.doc -134-200937872 . In the distribution rule of FIG. 99, group group information (Gb2, Gy1, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, l), (Gb3, Gy4, l) > (Gb3, Gy5, 2), (Gb3, Gy6, l). That is, the distribution rule of Yu圊99 is as follows: According to the group set information (Gbi, Gy6, 1) 'Assign the 1st bit of the malt unit of the error probability first good code bit group Gb! Give the 1st bit of the symbol bit of the 6th good symbol group Gy6 of the error probability; ❹ According to the group set information (Gb2, Gy ι, 2) 'The second probability of the error probability group The 2 bits of the code bit of the group Gt>2 are assigned to the 2 bit of the symbol bit of the first good symbol group Gy of the error probability; according to the group set information (Gb2, Gy2, 2 And assigning the 2-bit ' of the code bit of the second good symbol bit group Gbz of the error probability to the 2-bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; Group set information (Gb2, Gy3, 2) 'Assort the 2 bits of the code bit of the second good code bit group Gh of the error probability to the 3rd good symbol bit group Gys of the error probability 2 bits of the symbol bit; according to the group set information (GbhGykl), assign the i bit of the code bit of the second good code bit group Gh of the error probability to the error probability < 4: 1 bit of the symbol element of the good symbol element group Gy4; according to the group set information (Gb^Gy^l), the code bit of the error probability third good code bit group Gh 1 bit, assigned to the 1st bit of the symbol bit of the error probability **good symbol bit group Gy*; according to the group set information (Gb3, Gy5, 2), the error probability is 3rd good 135786.doc -135- 200937872 The bit position of the code bit group Gh is allocated to the 2nd bit of the symbol bit of the 5th good symbol bit group Gys; The group set information (Gb^Gy^l) assigns the 1st bit of the code bit of the 3rd good code bit group Gh of the error probability to the 6th good symbol bit group Gy0 of the error probability. The bit of the symbol element. Figure 100 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 99. That is, FIG. 100A shows that the LDPC code is an LDPC code whose code length is 648 bits and the coding rate is 2/3, and the further modulation method is 4〇96qAM, and the multiple 〇b is 1. The first example of the replacement of the code bits according to the distribution rule of FIG.
LDPC碼是碼長N為64800位元、編碼率為2/3之LDPC 碼,進一步調變方式為4096QAM、倍數之情況下,於 解多工器25 ’於縱行方向X橫列方向為(648〇〇/(12χ1))χ (12 X 1)位元之記憶體3 [寫入之碼位元係於橫列方向以 12><1(=011))位元單位讀出,並供給至替換部32(圖16、圖 17) 〇 ❿ 替換部32係按照圖99之分配規則,將讀出自記憶體3 1之 12><1(=1111))位元之碼位元|3()至1)】1,例如圖1〇〇人所示分配給 U=b)個符元之12><1(=〇11))位元之符元位元”至m,以替換 12xl(=mb)位元之碼位元b(>ibii。 亦即’替換部32係分別 將碼位元b〇分配給符元位元。〇, 將碼位元b,分配給符元位元y〇 , 將碼位元分配給符元位元yi, 135786.doc •136· 200937872 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y7, 將碼位元b 1 〇分配給符元位元y 11,The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 4096QAM and a multiple, the direction of the X direction of the demultiplexer 25' in the wale direction is ( 648〇〇/(12χ1))χ (12 X 1) bit memory 3 [Writing code bits are read in the horizontal direction in units of 12><1 (=011)), and Supply to the replacement unit 32 (Figs. 16 and 17) 〇❿ The replacement unit 32 reads the code bits from the 12><1 (=1111) bits of the memory 3 in accordance with the allocation rule of Fig. 99 | 3() to 1)]1, for example, as shown in Fig. 1 to assign U=b) symbols to 12><1 (=〇11) bits of the symbol bits" to m, Replace the code bit b of the 12xl (= mb) bit (>ibii. That is, the 'replacement unit 32 assigns the code bit b〇 to the symbol bit respectively. 〇, assign the code bit b to the symbol The bit y, assigning the code bit to the symbol yi, 135786.doc • 136· 200937872 assigning the code bit b3 to the symbol y2 and the code bit b4 to the y3 , the code bit b5 is assigned to the symbol bit y4, the code bit b6 is assigned to the symbol bit y5, and the code bit b7 is allocated. To the symbol bit y6, the code bit b8 is assigned to the symbol bit y8, the code bit b9 is assigned to the symbol bit y7, and the code bit b 1 〇 is assigned to the symbol bit y 11.
將碼位元b 1!分配給符元位元y 9, 而進行替換。 圖100B係表示LDPC碼是碼長N為64800位元、編碼率為 2/3之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖99之分配規則之碼位元之替換之第2例。 若根據圖100B,替換部32係按照圖99之分配規則,針對 從記憶體31所讀出之12xl(=mb)位元之碼位元bG至bn,分 別進行下述替換: 將碼位元bG分配給符元位元y i 1, 將碼位元b丨分配給符元位元y 1, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 135786.doc -137- 200937872 將碼位元b 8分配給符元位元y 9, 將碼位元b9分配給符元位元y6, 將碼位元bio分配給符元位元710, 將碼位元b π分配給符元位元y 8。 圖101係表示LDPC碼是碼長N為16200位元、編碼率為 3/4之LDPC碼’進一步調變方式為4096QAM,倍數匕為j之 情況下之碼位元群組及符元位元群組。 該情況下’從記憶體31所讀出之I2xl(=mb)位元之碼位 © 元係根據錯誤概率之差別,如圖101A所示可群組區分為4 個碼位元群組GbhGbhGbhGbc 於圖101A ’分別而言,碼位元群組碼位元%所 屬’碼位元群組Gbz係碼位元…至卜所屬,碼位元群組Gb3 係碼位元bs所屬’碼位元群組GW係碼位元b9至b! 1所屬。 調變方式為4096QAM ’倍數b為1之情況下,I2xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖1〇1B所示可 群組區分為6個符元位元群組Gy丨,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖101B ’與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元yQ,yi所屬,符元位元群組Gy2係符元位 元yz,y3所屬’符元位元群組Gy3係符元位元y4,y5所屬,符 元位元群組Gy*係符元位元y6,y7所屬,符元位元群組〇)^5係 符元位元ys,y9所屬,符元位元群組Gy6係符元位元y1G,yu 所屬。 圖102係表示LDPC碼是碼長N為16200位元、編碼率為 3M之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 135786.doc •138· 200937872 情況下之分配規則。 於圖102之分配規則’規定有群組集合資訊(Gb^Gy^l), (Gb2,Gyi,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy4,l),(Gb3,Gy4,l)’ (Gb4,Gy5,l),(Gb4,Gy6,2)。 亦即,於圖102之分配規則,規定如下: 根據群組集合資訊(Gb〗,Gy5,1)’將錯誤概率第1良好之 碼位元群組Gb 1之碼位元之1位元’分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; © 根據群組集合資訊(Gb2,Gyi,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元’分配給錯誤概率第1良 好之符元位元群組Gy!之符元位元之2位元; 根據群組集合資訊(Gl>2,Gy2,2),將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元’分配給錯誤概率第2良 好之符元位元群組Gy,之符元位元之2位元; 根據群組集合資訊(Gb>2,Gy3,2) ’將錯誤概率第2良好之 ❾碼位元群組Gh之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb2,Gy4,l),將錯誤概率第2良好之 碼位兀群組Gb2之碼位元之1位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 根據群組集合資訊(Gb3,Gy4,l),將錯誤概率第3良好之 碼位το群組Gh之碼位元之丨位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之1位元; 根據群組集合資訊(GbhGys’l),將錯誤概率第4良好之 135786.doc -139- 200937872 碼位元群組Gin之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gb4,Gy6,2),將錯誤概率第4良好 之碼位元群組Gh之碼位元之2位元,分配給錯誤概率第6 良好之符元位元群組Gy6之符元位元之2位元。 圖103係表示按照圖1〇2之分配規則之碼位元之替換例。 亦即,圖103A係表示LDPC碼是碼長N為16200位元、編 碼率為3/4之LDPC碼,進一步調變方式為4〇96QAM,倍數 €) b為1之情況下之按照圖} 〇 2之分配規則之碼位元之替換之 第1例。 LDPC碼是碼長N為16200位元、編碼率為3/4之LDpc 碼,進一步調變方式為4096QAM、倍數1)為1之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(12χΐ))χ (12 X 1)位元之記憶艎3 1寫入之碼位元係於橫列方向,以 12xl(-mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係按照圖102之分配規則,將讀出自記憶體31 之12x1(=mb)位元之碼位元1)。至1311,例如圖1〇3八所示分配 給l(=b)個符元之i2xl(=mb)位元之符元位元…至丫^,以替 換12xl(=mb)位元之碼位元至bu。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b !分配給符元位元y〇, 將碼位元分配給符元位元y 6, 135786.doc -140- 200937872 將碼位元b3分配給符元位元y!, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y 1 〇, 將碼位元b! 〇分配給符元位元y! 1,The code bit b 1 ! is assigned to the symbol bit y 9 and replaced. 100B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method is 4096QAM, and a multiple of b is 1 in the case of a code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 100B, the replacing unit 32 performs the following replacement for the code bits bG to bn of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 99: bG is assigned to the symbol bit yi 1, the code bit b丨 is assigned to the symbol bit y 1, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit y4 , the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y〇, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol Bit y7, 135786.doc -137- 200937872 assigns code bit b 8 to symbol bit y 9, assigns code bit b9 to symbol bit y6, and assigns bit bit bio to symbol bit 710. Assign the code bit b π to the symbol bit y 8. Figure 101 is a diagram showing that the LDPC code is an LDPC code whose code length N is 16,200 bits and the coding rate is 3/4. The further modulation method is 4096QAM, and the multiple is j is the code bit group and the symbol bit. Group. In this case, the code bit source of the I2x1 (= mb) bit read from the memory 31 is grouped into four code bit groups GbhGbhGbhGbc according to the difference in error probability as shown in FIG. 101A. 101A 'respectively, the code bit group code bit % belongs to the 'code bit group Gbz code bit element... to the subordinate, the code bit group Gb3 is the code bit bs belongs to the 'code bit group The group GW system code bits b9 to b! 1 belong. When the modulation mode is 4096QAM 'when the multiple b is 1, the symbol bits of the I2xl (= mb) bits are different according to the error probability, as shown in Figure 〇1B, the group can be divided into 6 symbol bits. Metagroups Gy丨, Gy2, Gy3, Gy4, Gy5, Gy6. 101B is the same as the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit yz, y3 belongs to ' The symbol element group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy* is the symbol element y6, y7 belongs to, the symbol element group 〇) ^5 system symbol element Ys, y9 belongs to, the symbol element group Gy6 is the symbol element y1G, yu belongs. Figure 102 is a diagram showing an LDPC code which is an LDPC code having a code length N of 16,200 bits and a coding rate of 3M, a further modulation method of 4096QAM, and a multiple b of 135786.doc • 138·200937872. The allocation rule in Fig. 102 specifies group information (Gb^Gy^l), (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, l), (Gb3, Gy4, l)' (Gb4, Gy5, l), (Gb4, Gy6, 2). That is, the allocation rule in FIG. 102 is defined as follows: According to the group set information (Gb, Gy5, 1) '1 bit of the code bit of the first good code bit group Gb 1 of the error probability' Assigned to the 1-bit of the symbol bit of the fifth-perfect symbol group Gy5 of the error probability; © according to the group set information (Gb2, Gyi, 2) 'The second probability of the error probability group The 2 bits of the code bit of the group Gt>2 are assigned to the 2 bit of the symbol bit of the first good symbol bit group Gy! of the error probability; according to the group set information (Gl>2, Gy2 2), assigning the 2-bit ' of the code bit of the second good code bit group Gt>2 of the error probability to the second bit symbol group Gy of the error probability, the symbol bit 2 bit; according to the group set information (Gb>2, Gy3, 2) 'Assign the 2nd bit of the code bit of the 2nd good weight bit group Gh of the error probability to the 3rd good error probability 2 bits of the symbol bit of the symbol element group Gy3; according to the group set information (Gb2, Gy4, l), the second good code bit of the error probability is 1 bit of the code bit of the group Gb2 Yuan, minute Give the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (Gb3, Gy4, l), the error probability 3rd good code bit το group The unit of the code bit of Gh is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (GbhGys'l), the error probability 4th good 135786.doc -139- 200937872 1 bit of the code bit of the code bit group Gin, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability And according to the group set information (Gb4, Gy6, 2), assign the 2 bits of the code bit of the 4th good code bit group Gh of the error probability to the 6th good symbol bit group of the error probability Group 2 of the symbol of Gy6. Figure 103 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1-2. That is, FIG. 103A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 4〇96QAM, and the multiple is €) b is 1 according to the figure} The first example of the replacement of the code bits of the allocation rule of 〇2. The LDPC code is an LDpc code with a code length N of 16,200 bits and a coding rate of 3/4. In the case where the modulation method is 4096QAM and the multiple 1) is 1, the multiplexer 25 is in the traverse direction and is horizontally traversed. The column direction is (162 〇〇 / (12 χΐ)) χ (12 X 1) bits of memory 艎 3 1 written code bits are in the horizontal direction, read in 12xl (-mb) bit units, and It is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the code bits 1x from the 12x1 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. Up to 1311, for example, the symbol bits of i2xl (= mb) bits assigned to l (=b) symbols as shown in Fig. 1〇3-8 are replaced by 丫^ to replace the code of 12xl (=mb) bits. Bit to bu. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b! to the symbol bit y, and assigns the code bit to the symbol y6. 135786.doc -140- 200937872 assign code bit b3 to symbol bit y!, assign code bit b4 to symbol bit y4, assign code bit b5 to symbol bit y5, place code bit The element b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y 1 〇 , assign the code bit b! 〇 to the symbol y! 1,
將碼位元b i!分配給符元位元y 9, 而進行替換。 圖103B係表示LDPC碼是碼長N為16200位元、編碼率為 3/4之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖102之分配規則之碼位元之替換之第2例。 若根據圖103B,替換部32係按照圖102之分配規則,針 對從記憶體3 1所讀出之12 X 1 (=mb)位元之碼位元bG至b!丨’ 分別進行下述替換: 將碼位元bG分配給符元位元y9, 將碼位元b!分配給符元位元y 1, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 135786.doc -141 - 200937872 將碼位元bg分配給符元位元y6, 將碼位元b 9分配給符元位元y丨J, 將碼位元b 1 〇分配給符元位元y丨〇, 將碼位元bl!分配給符元位元y8。 圖104係表示LDPC碼是碼長N為64800位元、編碼率為 3/4之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之碼位元群組及符元位元群組。 該情況下,從記憶體31所讀出之丨2χ丨(=mb)位元之碼位 元係根據錯誤概率之差別,如圖104A所示可群組區分為3 個碼位元群組Gb^Gb^Gh。 於圖104A,分別而言,碼位元群組Gbi係碼位元%所 屬’碼位元群組Gh係碼位元卜至!^所屬,碼位元群組Gb3 係碼位元b9至bn所屬。 調變方式為4096QAM ’倍數b為1之情況下,12xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖i 〇4B所示可 群組區分為6個符元位元群組GybGyhGyhGy^GyhGye。 於圖104B,與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元y Q,y 1所屬,符元位元群組Gy 2係符元位 元y2,y3所屬’符元位元群組Gys係符元位元y4,y5所屬,符 元位元群組Gy4係符元位元y6,y7所屬,符元位元群組Gy5係 符元位元ys,y9所屬,符元位元群組GW係符元值元 所屬。 圖105係表示LDPC碼是碼長N為64800位元、編碼率為 3/4之LDPC碼,進一步調變方式為1〇24qAM,倍數# i之 135786.doc •142- 200937872 情況下之分配規則。 於圖105之分配規則,規定有群組集合資訊(Gh Gwj), (Gb2,Gyi,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy4,2),(Gb3,Gy5,l), (Gb3,Gy6,2)。 亦即,於圖105之分配規則,規定如下: 根據群組集合資訊(Gb!,Gy5,l) ’將錯誤概率第1良好之 碼位元群組Gb!之碼位元之1位元,分配給錯誤概率第5良 妤之符元位元群組Gy 5之符元位元之1位元; Ο 根據群組集合資訊(Gb2,Gyi,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元’分配給錯誤概率第i良 好之符元位元群組Gy】之符元位元之2位元; 根據群組集合資訊(Gb2,Gy2,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gh»2之碼位元之2位元’分配給錯誤概率第3良 ® 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb>2,Gy4,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊(Gb3,Gys,l),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gb3,Gy6,2),將錯誤概率第3良好 135786.doc •143- 200937872 之碼位元群組Gh之碼位元之2位元,分配給錯誤概率第6 良好之符元位元群組Gy6之符元位元之2位元。 圖106係表示按照圖1 〇5之分配規則之碼位元之替換例。 亦即,圖106A係表示LDPC碼是碼長N為64800位元、編 碼率為3/4之LDPC碼,進一步調變方式為4096QAM,倍數 b為1之情況下之按照圖1〇5之分配規則之碼位元之替換之 第1例。 LDPC碼是碼長N為64800位元、編碼率為3/4之LDPC ❹ 碼’進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(12x1))x (12 X 1)位元之記憶體3 1寫入之瑪位元係於橫列方向,以 12xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) 〇 替換部32係按照圖1〇5之分配規則,將讀出自記憶體3 j 之12xl(=mb)位元之碼位元b(^bn,例如圖1〇6A所示分配 給1(=b)個符元之12xl(=mb)位元之符元位元7〇至711,以替 換12xl(=mb)位元之碼位元b()至bn。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b〗分配給符元位元y〇, 將碼位元b2分配給符元位元y6, 將碼位元b3分配給符元位元y i, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 135786.doc •144. 200937872 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y 7, 將碼位元b9分配給符元位元丫1〇, 將碼位元b 1 〇分配給符元位元y丨丨, 將碼位元bi丨分配給符元位元y9, 而進行替換。 圖106B係表示LDPC瑪是碼長N為 64800位元、雄瑪率為 © 3/4之LDpC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖105之分配規則之碼位元之替換之第2例。 若根據圖106B,替換部32係按照圖105之分配規則,針 對從記憶體31所讀出之12x1 (=mb)位元之碼位元bG至bn, 分別進行下述替換: 將瑪位元b〇分配給符元位元y9, 將碼位元b 1分配給符元位元y 1, 將碼位元b 2分配給符元位元y 3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, 將碼位元分配給符元位元y2, 將碼位元1)7分配給符元位元y7, 將碼位元1)8分配給符元位元y6, 將碼位元b9分配給符元位元y丨1, 將碼位元1)1()分配給符元位元71〇, 135786.doc • 145- 200937872 將碼位元b!!分配給符元位元y 8。 圖107係表示LDPC碼是碼長N為16200位元、編碼率為 4/5之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之碼位元群組及符元位元群組。 該情況下’從記憶體31所讀出之I2xl(=mb)位元之碼位 元係根據錯誤概率之差別’如圖107A所示可群組區分為3 個碼位元群組Gb^GbhGbs » 於圖107A,分別而言’碼位元群組碼位元%至、 © 所屬’碼位元群組Gh係碼位元%所屬,碼位元群組Gb3係 碼位元b 1 〇及b 11所屬。 調變方式為4096QAM,倍數b為1之情況下,12x1 (=mb) 位元之符元位元係根據錯誤概率之差別,如圖1 所示可 群組區分為6個符元位元群組Gy丨,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖107B,與圖95B之情況相同,分別而言,符元位元 群組Gy〗係符元位元yQ,yi所屬,符元位元群組Gy2係符元位 元y2,y3所屬’符元位元群組Gy3係符元位元y4,y5所屬,符 元位元群組Gy4係符元位元ye,y7所屬,符元位元群組日”係 符元位元ys,y9所屬,符元位元群組Gy6係符元位元yiQ,y" 所屬。 圖108係表示LDPC碼是碼長N為16200位元、編碼率為 4/5之LDPC碼,進一步調變方式為4096QAM ,倍數b為1之 情況下之分配規則。 於圖108之分配規則,規定有群組集合資訊(Gbi,Gyi 2), (Gbi,Gy2,2),(Gb1,Gy352),(Gb1,Gy4,2)}(Gb1,Gy5,l),(Gb2,Gy6,l), 135786.doc •146· 200937872 (Gb3,Gy5,l),(Gb3,Gy6,l)。 亦即’於圖108之分配規則,規定如下: 根據群組集合資訊(〇1?1,〇71,2),將錯誤概率第1_好 碼位元群組Gbi之碼位元之2位元,分配蛉扭崎, 刀此狯錯誤概率第i良 好之符元位元群組Gy,之符元位元之2位元; 根據群組集合資訊(Gb^Gy2』),將錯誤概率第^戸好 碼位元群組Gb!之碼位元之2位元,分配給錯誤概率第2声 好之符元位元群組Gyz之符元位元之2位元; © 根據群組集合資訊(GbuGysJ) ’將錯誤概率第j良好之 碼位元群組Gh之碼位元之2位元’分配給錯誤概率第3声 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb^Gy4。)’將錯誤概率第i良好之 碼位元群組Gb,之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊(Gbi,Gy〗,1) ’將錯誤概率第1良好之 ❹ 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb>2,Gy6,l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; 根據群組集合資訊(Gb3,Gys,l),將錯誤概率第3良好之 媽位元群組Gt>3之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy 5之符元位元之1位元; 及根據群組集合資訊(01?3,〇76,1),將錯誤概率第3良好 135786.doc • 147- 200937872 之碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第6 良好之符元位元群組Gy6之符元位元之1位元。 圖109係表示按照圖1 〇8之分配規則之碼位元之替換例。 亦即’圖109A係表示LDPC碼是碼長N為16200位元、編 碼率為4/5之LDPC碼,進一步調變方式為4096QAM,倍數 b為1之情況下之按照圖1 之分配規則之碼位元之替換之 第1例。 LDPC瑪是碼長N為16200位元、編碼率為4/5之LDPC 〇 碼,進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(丨62〇〇/( 12x1))X (12x1)位元之記憶體31寫入之碼位元係於橫列方向,以 12xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) 〇 替換部3 2係按照圖1 〇 8之分配規則’將讀出自記憶體3 1 之12xl(=mb)位元之碼位元bG至bn,例如圖i〇9A所示分配 給l(=b)個符元之12xl(=mb)位元之符元位元7()至丫11,以替 ® 換Kxibmb)位元之碼位元至bn。 亦即,替換部32係分別 將碼位元bo分配給符元位元y8, 將碼位元bi分配給符元位元y〇, 將碼位元b2分配給符元位元y 6, 將碼位元b3分配給符元位元y !, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 135786.doc -148 - 200937872 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將瑪位元bs分配給符元位元y7, 將碼位元b9分配給符元位元y 1〇, 將碼位Sb1G分配給符元位元yn, 將碼位元b! i分配給符元位元y9, 而進行替換》 圖1098係表示1^?(1;碍是碼長]^為16200位元、編碼率為 © 4/5iLDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖108之分配規則之碼位元之替換之第2例。 若根據圖109B,替換部32係按照圖108之分配規則,針 對從記憶體3 1所讀出之Ι2χ 1 (=mb)位元之碼位元b〇至b!!, 分別進行下述替換: 將碼位元b〇分配給符元位元y6, 將碼位元b 1分配給符元位元y!, 將碼位元b2分配給符元位元y3,The code bit b i! is assigned to the symbol bit y 9, and replaced. FIG. 103B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and further modulation is 4096QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 103B, the replacing unit 32 performs the following replacement for the code bits bG to b!丨' of the 12 X 1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. : assigning the code bit bG to the symbol bit y9, assigning the code bit b! to the symbol bit y 1, assigning the code bit b2 to the symbol bit y3, and assigning the code bit b3 to the symbol The bit position y4 assigns the code bit b4 to the symbol bit y5, the code bit b5 to the symbol bit y, and the code bit b6 to the symbol y2, and the code bit b7 Assigned to the symbol bit y7, 135786.doc -141 - 200937872 assigns the code bit bg to the symbol bit y6, and assigns the code bit b 9 to the symbol bit y丨J, the code bit b 1 〇 is assigned to the symbol element y丨〇, and the code bit bl! is assigned to the symbol element y8. Figure 104 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the χ丨2 χ丨 (= mb) bits read from the memory 31 are group-divided into 3 code bit groups Gb according to the difference in error probability as shown in FIG. 104A. ^Gb^Gh. In FIG. 104A, respectively, the code bit group Gbi code bit % belongs to the 'code bit group Gh code bit to the ^, the code bit group Gb3 is the code bit b9 to bn Own. When the modulation mode is 4096QAM 'when the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability, as shown in Figure 〇4B, the group can be divided into 6 symbols. The meta group GybGyhGyhGy^GyhGye. In FIG. 104B, as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit y Q, y 1 belongs to, and the symbol bit group Gy 2 is a symbol bit y2. Y3 belongs to the 'character bit group Gys system symbol element y4, y5 belongs to, the symbol element group Gy4 is the symbol element y6, y7 belongs to, the symbol element group Gy5 is the symbol element ys , y9 belongs to, the symbol element group GW system symbol element value belongs to. 105 is a diagram showing an LDPC code in which an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method of 1〇24qAM, multiples #i of 135786.doc • 142-200937872 . The distribution rule in FIG. 105 specifies group information (Gh Gwj), (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, 2), (Gb3, Gy5, l), (Gb3, Gy6, 2). That is, the allocation rule in FIG. 105 is defined as follows: According to the group set information (Gb!, Gy5, l) '1 bit of the code bit of the error probability first good code bit group Gb! The 1st bit of the symbol element assigned to the symbol element group Gy 5 of the error probability 5th; Ο According to the group set information (Gb2, Gyi, 2) 'The error probability is 2nd good code point The 2-bit ' of the code bit of the meta-group Gt>2 is assigned to the 2-bit of the symbol bit of the error probability i-th good symbol bit group Gy; according to the group set information (Gb2, Gy2) 2) 'The 2 bits of the code bit of the second good code bit group Gt>2 of the error probability are assigned to the symbol bit of the second good symbol bit group Gy2 of the error probability 2 Bit; according to the group set information (Gb2, Gy3, 2) 'Assign the 2nd bit of the code bit of the 2nd good code bit group Gh»2 of the error probability to the error probability 3rd good® 2 bits of the symbol bit of the symbol element group Gy3; according to the group set information (Gb>2, Gy4, 2) 'the code point of the second good code bit group Gt> 2 yuan of yuan, The second bit of the symbol bit of the 4th good symbol group Gy4 of the error probability is assigned; according to the group set information (Gb3, Gys, l), the error probability third good symbol bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; and according to the group set information (Gb3, Gy6, 2), the error Probability 3rd good 135786.doc • 143- 200937872 The code bit group Gh 2 bits of the code bit are assigned to the 2nd bit of the symbolic bit of the 6th good symbol bit group Gy6 of the error probability yuan. Figure 106 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1 〇 5. That is, FIG. 106A shows that the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 3/4, and the modulation mode is 4096QAM, and the multiple b is 1 according to the allocation according to FIG. The first example of the replacement of the ruled code bits. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 3/4. In the case where the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is in the traversing direction and the horizontal direction is X. The memory of the (648〇〇/(12x1))x (12 X 1) bit is stored in the horizontal direction, read in 12xl (= mb) bits, and Supply to the replacement unit 32 (FIG. 16, FIG. 17) The replacement unit 32 reads the code bits b (^bn, 12x1 (=mb) bits from the memory 3j according to the allocation rule of FIG. For example, as shown in Fig. 1〇6A, the symbol bits 7〇 to 711 of 12xl (= mb) bits allocated to 1 (=b) symbols are replaced with the code bits b of 12xl (= mb) bits ( That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b to the symbol bit y, and assigns the code bit b2 to the symbol. Bit y6, assigning code bit b3 to symbol bit yi, assigning code bit b4 to symbol bit y4, and assigning code bit b5 to symbol bit y5, 135786.doc • 144. 200937872 The code bit b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, and the code bit is B8 is assigned to the symbol bit y 7, the code bit b9 is assigned to the symbol bit 丫1〇, the code bit b 1 〇 is assigned to the symbol bit y丨丨, and the code bit bi丨 is assigned to Figure 106B shows that the LDPC is an LDpC code with a code length N of 64,800 bits and a male rate of 3/4. The further modulation is 4096QAM, and the multiple b is 1. The second example of replacing the code bit according to the allocation rule of Fig. 105. According to Fig. 106B, the replacing unit 32 is for the 12x1 (= mb) bit read from the memory 31 in accordance with the allocation rule of Fig. 105. The code bits bG to bn of the element are respectively replaced by: assigning the m-bit b〇 to the symbol bit y9, and assigning the code bit b 1 to the symbol bit y 1, and the code bit b 2 Assigned to the symbol bit y 3 , the code bit b3 is assigned to the symbol bit y4 , the code bit b4 is assigned to the symbol bit y 5 , and the code bit b5 is assigned to the symbol bit y 〇 . The code bit is assigned to the symbol bit y2, the code bit 1)7 is assigned to the symbol bit y7, the code bit 1)8 is assigned to the symbol bit y6, and the code bit b9 is assigned to the symbol The meta-bit y丨1, the code bit 1)1() Assigned to the symbol bit 71〇, 135786.doc • 145- 200937872 Assign the code bit b!! to the symbol bit y 8. Figure 107 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the difference between the error bit probability of the I2x1 (= mb) bit read from the memory 31 can be grouped into three code bit groups Gb^GbhGbs as shown in FIG. 107A. » In Fig. 107A, respectively, the 'code bit group code bit % to, © the 'code bit group Gh code bit % % belongs to, the code bit group Gb3 is the code bit b 1 〇 and b 11 belongs. When the modulation mode is 4096QAM and the multiple b is 1, the 12x1 (=mb) bit symbol is based on the difference in error probability. As shown in Figure 1, the group can be divided into 6 symbol groups. Groups Gy丨, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 107B, as in the case of FIG. 95B, respectively, the symbol bit group Gy is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2, and y3 belongs to ' The symbol element group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy4 is the symbol element ye, y7 belongs to, the symbol element group day "signature element bit ys, y9 Affiliation, symbol group Gy6 is a symbol element yiQ, y" belongs. Figure 108 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 4/5. 4096QAM, the allocation rule in the case where the multiple b is 1. The allocation rule in Fig. 108 specifies group information (Gbi, Gyi 2), (Gbi, Gy2, 2), (Gb1, Gy352), (Gb1, Gy4,2)}(Gb1,Gy5,l),(Gb2,Gy6,l), 135786.doc •146· 200937872 (Gb3,Gy5,l),(Gb3,Gy6,l). That is, 'Figure 108 The allocation rule is as follows: According to the group set information (〇1?1, 〇71, 2), the 2 bits of the code bit of the error probability 1st good code bit group Gbi are allocated to the 蛉 崎, the knife is wrong, the probability of the i-th good symbol group Gy, the symbol element 2 bits; according to the group set information (Gb^Gy2), the 2nd bit of the code bit of the error probability bit group Gb! is assigned to the second symbol of the error probability 2 bits of the symbol bit of the bit group Gyz; © According to the group set information (GbuGysJ) 'Assign the error probability jth good code bit group Gh 2 bits of the code bit' to the error The probability 3rd sound is good, the bit group Gy3 is 2 bits of the symbol bit; according to the group set information (Gb^Gy4.) 'the error probability is the i-th good code bit group Gb, 2 bits of the code bit, assigned to the 2nd bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gbi, Gy, 1) 'The error probability 1st good 1 1 bit of the code bit of the code bit group Gh, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; (Gb>2, Gy6, l), assigning the 1-bit of the code bit of the second-perfect code bit group Gb2 of the error probability to the symbol of the sixth-perfect symbol bit group Gy6 of the error probability Bit 1 bit; according to the group set information (Gb3, Gys, l), assign 1 bit of the code bit of the error probability 3rd good mother bit group Gt>3 to the error probability 5th good 1 bit of the symbol bit of Gy 5; and according to the group set information (01?3, 〇76,1), the error probability is 3rd good 135786.doc • 147- 200937872 One bit of the code bit of the bit group Gb3 is assigned to one bit of the symbol bit of the sixth bit symbol group Gy6 of the error probability. Figure 109 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1-8. That is, FIG. 109A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 4096QAM, and the multiple b is 1 according to the allocation rule of FIG. The first example of the replacement of the code bit. LDPC is an LDPC code with a code length N of 16200 bits and a coding rate of 4/5. In the case where the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is in the traversing direction, and the horizontal direction is X. The code bits written in the memory 31 of the column direction (丨62〇〇/(12x1))X (12x1) bits are in the course direction, read out in 12xl (=mb) bit units, and supplied to The replacing unit 32 (FIG. 16, FIG. 17) 〇 replacing unit 3 2 reads the code bits bG to bn of 12x1 (= mb) bits from the memory 3 1 according to the allocation rule of FIG. 1 , 8 , for example, i〇9A is assigned to symbolic bits 7() to 丫11 of 12xl (= mb) bits of l (=b) symbols, to replace the code bits of Kxibmb) bits to bn. That is, the replacing unit 32 assigns the code bit bo to the symbol bit y8, the code bit bi to the symbol bit y, and the code bit b2 to the symbol y 6, respectively. The code bit b3 is assigned to the symbol bit y !, the code bit b4 is assigned to the symbol bit y4, and the code bit b5 is assigned to the symbol bit y5, 135786.doc -148 - 200937872 B6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the mate bs is assigned to the peg y7, and the code bit b9 is assigned to the peg y 1〇, The code bit Sb1G is assigned to the symbol bit yn, and the code bit b! i is assigned to the symbol bit y9, and is replaced. FIG. 1098 indicates that 1^?(1; the block is the code length)^ is 16200 bits. The second example in which the coding rate is a 4/5 iLDPC code, and the modulation method is 4096QAM, and the multiple b is 1, the replacement of the code bits according to the allocation rule of FIG. 108. If the replacement unit is according to FIG. 109B, According to the distribution rule of FIG. 108, for the code bits b〇 to b!! of the Ι2χ 1 (= mb) bits read from the memory 3 1 , the following replacement is performed respectively: The code bit b 〇 Assigned to the symbol y6, The code bit b 1 to the symbol bit y !, allocating the code bit b2 to the symbol bit y3,
A 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y0, 將碼位元b6分配給符元位元y2, 將碼位元by分配給符元位元y7, 將瑪位元bs分配給符元位元y9, 將碼位元b9分配給符元位元y 11 ’ 將碼位元b!〇分配給符元位元yi〇 ’ 135786.doc -149- 200937872 將碼位元bn分配給符元位元y8。 圖110係表不LDPC碼疋碼長N為64800位元、編碼率為 4/5之LDPC碼,進一步調變方式為4096QAM,倍數13為1之 情況下之碼位元群組及符元位元群組。 該情況下’從記憶體31所讀出之i2xl (==inb)位元之碼位 元係根據錯誤概率之差別,如圖11 〇A所示可群組區分為5 個碼位元群組GbhGbhGbhGbhGbs。 於圖110A,分別而言,碼位元群組Gbi係碼位元%所 〇 屬,碼位元群組Gb2係碼位元\所屬,碼位元群組Gb3係碼 位元bz至bs所屬,碼位元群組oh係碼位元%所屬,碼位元 群組Gb5係碼位元bi〇及bi!所屬。 調變方式為4096QAM,倍數b為1之情況下,12xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖Η 所示可 群組區分為6個符元位元群組(^1,(^2,(^3,(^4,(^5,(^6。 於圖110B,與圖95B之情況相同,分別而言,符元位元 群組Gyi係符元位元yQ,yi所屬,符元位元群組Gy2係符元位 ® 元Μ,”所屬,符元位元群組Gys係符元位元y4,y5所屬,符 元位元群組Gy*係符元位元ye,y7所屬,符元位元群組(^5係 符元位元所屬,符元位元群組Gy6係符元位元yiQ,yn 所屬。 圖111係表示LDPC碼是碼長Na 648〇〇位元編碼率為 4/5之LDPC碼,進一步調變方式為4〇96QAM,倍數1之 情況下之分配規則。 於圖111之分配規則,規定有群組集合資訊(Gbi,Gy5 l), 135786.doc •150- 200937872 (Gb2,Gy1,l),(Gb3,Gy1,l),(Gb3,Gy2,2),(Gb3,Gy352),(Gb3>Gy4 2) (Gb4,Gy6,l),(Gb5,Gy5,l),(Gb5,Gy6,l)。 ’ 亦即,於圖111之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l),將錯誤概率第i良好之 碼位元群組Gb,之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之1位元,分配給錯誤概率第ι良 © 好之符元位元群組Gy!之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好之 碼位元群組Gb>3之碼位元之ι位元’分配給錯誤概率第J良 好之符元位元群組之符元位元之1位元; 根據群組集合資訊(Gt>3,Gy2,2),將錯誤概率第3良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy;j之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2),將錯誤概率第3良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy;之符元位元之2位元; 根據群組集合資訊(Gb3,Gy4,2),將錯誤概率第3良好之 碼位兀群組Gbs之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy*之符元位元之2位元; 根據群組集合資訊,將錯誤概率第4良好之 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gw之符元位元之ι位元; 135786.doc -151 · 200937872 根據群組集合資訊(Gb5,Gys,l),將錯誤概率第5良好之 碼位元群組Gb>5之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 及根據群組集合資訊(Gt>5,Gy6,l),將錯誤概率第5良好 之碼位元群組Gb>5之碼位元之1位元,分配給錯誤概率第6 良好之符元位元群組Gy6之符元位元之1位元。 圖112係表示按照圖ill之分配規則之碼位元之替換例。 亦即’圖112A係表不LDPC碼是碼長N為64800位元、編 © 碼率為4/5之LDPC碼,進一步調變方式為4〇96QAM,倍數 1之情況下之按照圖111之分配規則之碼位元之替換之 第1例。A assigns the code bit b3 to the symbol bit y4, assigns the code bit b4 to the symbol bit y5, assigns the code bit b5 to the symbol bit y0, and assigns the code bit b6 to the symbol bit The element y2 assigns the code bit unit to the symbol bit y7, assigns the m-bit bs to the symbol bit y9, and assigns the code bit b9 to the symbol bit y 11 '. The code bit b! Assigned to the symbol bit yi〇' 135786.doc -149- 200937872 The code bit bn is assigned to the symbol bit y8. Figure 110 shows an LDPC code with an LDPC code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method of 4096QAM, a multiple of 13 is a code bit group and a symbol bit. Meta group. In this case, the code bits of the i2xl (==inb) bits read from the memory 31 are grouped into 5 code bit groups according to the difference in error probability as shown in FIG. 11A. GbhGbhGbhGbhGbs. In FIG. 110A, respectively, the code bit group Gbi is the code bit %, the code bit group Gb2 is the code bit\ belongs, and the code bit group Gb3 is the code bit bz to bs. The code bit group oh belongs to the code bit %, and the code bit group Gb5 is the code bit bi〇 and bi! When the modulation method is 4096QAM and the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability. As shown in Figure 可, the group can be divided into 6 symbol groups. Group (^1, (^2, (^3, (^4, (^5, (^6. in Fig. 110B, which is the same as the case of Fig. 95B, respectively, the symbol element group Gyi symbol) The bit yQ, yi belongs to, the symbol element group Gy2 is a symbol element Μ yuan Μ," belongs, the symbol element group Gys is a symbol element y4, y5 belongs to, the symbol element group Gy* The symbol element ye, y7 belongs to, the symbol element group (^5 is the symbol element belongs to, the symbol element group Gy6 is the symbol element yiQ, yn belongs to. Figure 111 shows that the LDPC code is The code length Na 648 〇〇 bit encoding rate is 4/5 LDPC code, and the further modulation mode is 4 〇 96QAM, the allocation rule in the case of multiple 1. The allocation rule in FIG. 111 specifies group group information ( Gbi, Gy5 l), 135786.doc • 150- 200937872 (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy2, 2), (Gb3, Gy352), (Gb3 > Gy4 2) ( Gb4, Gy6, l), (Gb5, Gy5, l), (Gb5, Gy6, l). ' That is, the distribution rules in Figure 111, As follows: According to the group set information (Gb^Gy^l), the code bit of the i-th good code bit group Gb of the error probability is assigned to the fifth bit of the error probability. 1 bit of the symbol bit of the group Gy5; according to the group set information (Gb^Gy^l) '1 bit of the code bit of the second good code bit group Gt> Assigned to the error probability ι 良 © The good symbol meta-group Gy! The 1-bit symbol; according to the group collection information (Gb^Gy^l), the error probability is the third good code position The ι bit of the code bit of the meta-group Gb>3 is assigned to the 1-bit of the symbol bit of the error probability J-good symbol group; according to the group set information (Gt>3, Gy2 2), assigning the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability to the second bit symbol group Gy of the error probability; Bits; according to the group set information (Gb3, Gy3, 2), assign the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability to the 3rd good symbol bit of the error probability Group Gy; 2 bits; according to the group set information (Gb3, Gy4, 2), assign the error probability 3rd good code bit to the 2 bits of the code bit of the group Gbs to the 4th good symbol of the error probability 2 bits of the symbol group of the meta group Gy*; according to the group set information, the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is assigned to the sixth error probability. The ι bit of the symbol bit of the symbol group Gw; 135786.doc -151 · 200937872 According to the group set information (Gb5, Gys, l), the error probability fifth good symbol group 1 bit of the code bit of Gb>5, assigned to the 1st bit of the symbol bit of the symbol 5th good symbol group Gy5 of the error probability; and according to the group set information (Gt>5, Gy6, l), assigning 1 bit of the code bit of the 5th good code bit group Gb>5 of the error probability to 1 bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability yuan. Figure 112 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure ill. That is, 'FIG. 112A shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and a code rate of 4/5. The further modulation method is 4〇96QAM, and the multiple 1 is in accordance with FIG. 111. The first example of the replacement of the code bits of the allocation rule.
LDPC瑪是碼長N為64800位元、編碼率為4/5之LDPC 碼’進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(ΐ2χΐ))χ (12 1)位元之s己憶體3 1寫入之碼位元係於橫列方向,以 12xl(=mb)位元單位讀出’並供給至替換部32(圖16、圖 ❹ 17) 〇 替換部3 2係按照圖1 11之分配規則,將讀出自記憶體3 J 之12xl(=mb)位元之碼位元%至bn ’例如圖112A所示分配 給l(=b)個符元之i2xl(=mb)位元之符元位元yG至yu,以替 換12xl(=mb)位元之碼位元%至bn。 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碣位元b!分配給符元位元y〇, 135786.doc •152- 200937872 將瑪位元b〗分配給符元位元y6, 將碼位元b3分配給符元位元y j, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y丨〇, © 將碼位元b , 〇分配給符元位元y , i, 將碼位元b〗丨分配給符元位元y9, 而進行替換。 圖112B係表示LDPC碼是碼長N為64800位元、編碼率為 4/5之LDPC碼,進一步調變方式為4096qAM,倍數b為1之 情況下之按照圖111之分配規則之碼位元之替換之第2例。 若根據圖1 UB,替換部32係按照圖111之分配規則,針 對從記憶體31所讀出之12x1 (=mb)位元之碼位元^❶至, d U 1 W 分別進行下述替換: 將碼位元b〇分配給符元位元y9, 將碼位元b!分配給符元位元yi, 將碼位元b2分配給符元位元y 3, 將瑪位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 將碼位元bs分配給符元位元y〇, 將瑪位元b6分配給符元位元y 2, 135786.doc -153 - 200937872 將碼位元b7分配給符元位元y7 ’ 將碼位元1)8分配給符元位元y6, 將碼位元b9分配給符元位元yn ’ 將碼位元131()分配給符元位元710 ’ 將碼位元b 1】分配給符元位元y8。 圖113係表示LDPC碼是碼長N為16200位元、編碼率為 5/6之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之碼位元群組及符元位元群組。 © 該情況下’從記憶體31所讀出之12x1 (=mb)位元之碼位 元係根據錯誤概率之差別,如圖113A所示可群組區分為4 個碼位元群組Gb1,Gb2,Gb3,Gb4。 於圖113A,分別而言,碼位元群組Gbl係碼位元^所 屬,碼位元群組Gh係碼位元卜至!)8所屬,碼位元群組Gb3 係碼位元bp所屬,碼位元群組Gh係碼位元及bn所屬。 調變方式為4096QAM,倍數b為1之情況下,i2xl(=mb) ❹ 位元之符元位元係根據錯誤概率之差別,如圖113B所示可 群組區分為6個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖113B,與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元yG,yi所屬,符元位元群組係符元位 元yz,y3所屬,符元位元群組係符元位元y4,y5所屬,符 兀位元群組Gh係符元位元Υ6,&所屬,符元位元群組Gy5係 符元位元化乃所屬,符元位元群組Gy6係符元位元yiG,yu 所屬。 圖114係表示LDPC碼是碼長^為162〇〇位元編碼率為 135786.doc -154- 200937872 5/6之LDPC碼,進一步調變方式為4096QAM,倍數匕為i之 情況下之分配規則。 於圖114之分配規則,規定有群組集合資訊(Gbi Gy5 ^ (Gb2,Gyi,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb25Gy4,2),(Gb3,Gy6 1) (Gb4,Gy5,l),(Gb4,Gy6,l)。 亦即,於圖114之分配規則,規定如下: 根據群組集合資訊(Gb〗,Gy5,l),將錯誤概率第i良好之 碼位元群組Gth之碼位元之1位元’分配給錯誤概率第5良 © 好之符元位元群組Gy 5之符元位元之1位元; 根據群組集合資訊(Gl>2, Gy!,2) ’將錯誤概率第2良好之 瑪位元群組Gt>2之碼位元之2位元’分配給錯誤概率第 好之符元位元群組Gy i之符元位元之2位元; 根據群組集合資訊(Gb2, Gy〗,2),將錯誤概率第2良好之 碼位元群組Gbz之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; ❹ 根據群組集合資訊(Gb2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb2,Gy4,2),將錯誤概率第2良好之 碼位tl群組Gh之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊,將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; 135786.doc -155- 200937872 根據群組集合資訊(Gb4,Gys,l) ’將錯誤概率第4良好之 碼位元群組GW之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gys之符元位元之1位元; 及根據群組集合資訊(Gb>4,Gy6,l),將錯誤概率第4良好 之碼位元群組Gh之碼位元之1位元,分配給錯誤概率第6 良好之符元位元群組Gy0之符元位元之丨位元。 圖115係表示按照圖114之分配規則之碼位元之替換例。 亦即’圖115A係表示LDPC碼是瑪長N為16200位元、編 © 碼率為5/6之LDPC碼,進一步調變方式為4〇96QAM,倍數 b為1之情況下之按照圖114之分配規則之碼位元之替換之 第1例。 LDPC瑪是碼長N為16200位元、編碼率為5/6之LDpc 碼’進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25 ’於縱行方向X橫列方向為(162〇〇/(12χ1))χ (12x1)位元之記憶體31寫入之碼位元係於橫列方向以 12x l(-mb)位元單位讀出’並供給至替換部32(圖μ、圖 V 17)。 替換部3 2係按照圖114之分配規則,將讀出自記憶體3 1 之12xl(=mb)位元之碼位元b()至bll,例如圖U5A所示分配 給l(=b)個符元之I2xl(=mb)位元之符元位元y。至yn,以替 換12xl(=mb)位元之碼位元bQ至bn。 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元bi分配給符元位元y〇, 135786.doc -156- 200937872 將碼位元b2分配給符元位元y6, 將碼位元b3分配給符元位元y!, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元1)6分配給符元位元y2, 將碼位元b7分配給符元位元y 3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y 1〇, Ο 將碼位元1?1()分配給符元位元yn, 將碼位元bi!分配給符元位元y9, 而進行替換。 圖115B係表示LDPC碼是碼長N為16200位元、編碼率為 5/6之LDPC碼,進一步調變方式為4096QAM ’倍數b為1之 情況下之按照圖114之分配規則之碼位元之替換之第2例。 若根據圖115B,替換部32係按照圖114之分配規則,針 對從記憶體31所讀出之12xl(=mb)位元之碼位元bQ至bu, 分別進行下述替換: 將碼位元bG分配給符元位元y9, 將碼位元b】分配給符元位元y丨, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 135786.doc -157- 200937872 將瑪位元b7分配給符元位元y7, 將碼位元be分配給符元位元y6, 將碼位元b9分配給符元位元yi!, 將碼位元bi〇分配給符元位元丫10, 將碼位元b 1〗分配給符元位元y 8。 圖11 6係表示LDPC碼是碼長N為64 8 00位元、編碼率為 5/6之LDPC碼,進一步調變方式為4096QAM,倍數i之 情況下之碼位元群組及符元位元群組。 ® 該情況下’從記憶艎31所讀出之I2xl(=mb)位元之碼位 元係根據錯誤概率之差別’如圖116A所示可群組區分為3 個碼位元群組Gbi,Gb2,Gb3 » 於圖116A,分別而言,碼位元群組Gbl係碼位元b〇所 屬,碼位元群組Gbz係碼位元卜至!)9所屬,碼位元群組Gb3 係碼位元1>1()及bn所屬。 調變方式為4096QAM,倍數b為1之情況下,12xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖116B所示可 群組區分為6個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖116B,與圖95B之情況相同,分別而言,符元位元 群組Gy〗係符元位元yQ,yi所屬,符元位元群組Gy2係符元位 元yZ,y3所屬,符元位元群組Gy3係符元位元y4,ys所屬,符 元位元群組Gy*係符元位元y0,y7所屬,符元位元群組係 符兀位元ys,y9所屬,符元位元群組Gy6係符元位元 所屬。 圖Π7係表不LDPC碼是碼長^^為648〇〇位元、編碼率為 135786.doc -158· 200937872 5/6之LDPC碼,進一步調變方式為4〇96QAM,倍數1?為1之 情況下之分配規則。 於圖117之分配規則,規定有群組集合資訊(Gbi,Gy5,1}, (Gb2,Gyi,2),(Gb2,Gy2,2),(Gb2,Gy3,2),(Gb2,Gy4,2),(Gb2,Gy6,l), (Gb3,Gy5,l),(Gb3,Gy6,l) 〇 亦即,於圖117之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l),將錯誤概率第1良好之 碼位元群組Gb 1之碼位元之1位元’分配給錯誤概率第5良 © 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb2,Gy!,2) ’將錯誤概率第2良好之 碼位元群組Gb>2之碼位元之2位元,分配給錯誤概率第1良 好之符元位元群組Gy,之符元位元之2位元; 根據群組集合資訊(Gbz,Gy2,2),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; ©根據群組集合資訊(Gb2,Gy3,2) ’將錯誤概率第2良好之 碼位元群組Gb2之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy〗之符元位元之2位元; 根據群組集合資訊(Gb2,Gy4,2) ’將錯誤概率第2良好之 碼位元群組Gt>2之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊(Gl>2,Gy6,1),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; 135786.doc -159- 200937872 根據群組集合資訊(Gb3,Gys,l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之丨位元,分配給錯誤概率第5良 好之符元位元群組Gys之符元位元之1位元; 又 及根據群組集合資訊(Gb^G^D,將錯誤概率第3良好 之碼位元群組Gbs之碼位元之丨位元,分配給錯誤概率第6 良好之符元位元群組Gye之符元位元之1位元。 圖118係表示按照圖117之分配規則之碼位元之替換例。 亦即,圖118A係表示LDPC碼是碼長N為64800位元、塢 © 碼率為5/6之LDPC碼,進一步調變方式為4〇96qAM,倍數 b為1之情況下之按照圖丨17之分配規則之碼位元之替換之 第1例 LDPC碼是碼長N為64800位元、編碼率為5/6之LDpc 碼,進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(12χ1))χ (12 X 1)位元之s己憶體3 1寫入之瑪位元係於橫列方向,以 12xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 ® 17)。 替換部32係按照圖117之分配規則,將讀出自記憶體3 i 之12xl(=mb)位元之碼位元b()至bu,例如圖118A所示分配 給l(=b)個符元之l2xl(=mb)位元之符元位元y〇至yn,以替 換12xl(=mb)位元之碼位元b〇至bn。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b!分配給符元位元yG, 135786.doc -160· 200937872 將碼位元b2分配給符元位元y 6, 將碼位元b3分配給符元位元y〗, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y! 〇, © 將碼位元b 1 〇分配給符元位元y 1 J, 將碼位元b 1 1分配給符元位元y9, 而進行替換。 圖118B係表示LDPC碼是碼長N為64800位元、編碼率為 5/6之LDPC碼’進一步調變方式為4096QAM,倍數1>為i之 情況下之按照圖117之分配規則之碼位元之替換之第2例。 若根據圖118B,替換部32係按照圖117之分配規則,針 對從記憶體31所讀出之12x1 (=mb)位元之碼位元bG至bn, W 分別進行下述替換: 將碼位元b〇分配給符元位元y9, 將碼位元b 1分配給符元位元y J, 將碼位元b〗分配給符元位元y 3, 將碼位元b3分配給符元位元y4, 將瑪位元b4分配給符元位元y 5, 將碼位元bs分配給符元位元y〇, 將碼位元分配給符元位元y2, 135786.doc -161 - 200937872 將碼位元b7分配給符元位元y7, 將碼位元b8分配給符元位元yn, 將碼位元b 9分配給符元位元y 6, 將碼位元b 1〇分配給符元位元y i 〇, 將碼位元bu分配給符元位元y8。 圖119係表示LDPC碼是碼長N為16200位元、編碼率為 8/9之LDPC瑪’進一步調變方式為4096QAM,倍數b為1之 情況下之碼位元群組及符元位元群組。 〇 該情況下’從記憶體31所讀出之I2xl(=mb)位元之碼位 元係根據錯誤概率之差別,如圖119A所示可群組區分為5 個碼位 7C 群組 Gb 1,Gb2,Gb3,Gb4,Gb5。 於圖119A,分別而言,碼位元群組Gb〗係碼位元b〇所 屬’碼位元群組Gb2係碼位元b!所屬,碼位元群組Gb3係碼 位元h至所屬’碼位元群組Gb4係碼位元1)1()所屬,碼位 元群組Gb〗係碼位元bn所屬。 調變方式為4096 Q AM ’倍數b為1之情況下,12x1 (=mb) 位元之符元位元係根據錯誤概率之差別,如圖Π 9B所示可 群組區分為6個符元位元群組〇丫1,0丫2,〇73,0丫4,〇75,〇76。 於圖119B,與圖95B之情況相同,分別而言,符元位元 群組Gyi係符元位元所屬,符元位元群組Gy2係符元位 元y2,y3所屬,符元位元群組Gy3係符元位元y4,y5所屬,符 元位元群組Gy4係符元位元y6,y7所屬,符元位元群組Gy5係 符元位元ys,y9所屬’符元位元群組Gy6係符元位元yi〇,yii 所屬。 135786.doc -162- 200937872 圊120係表示LDPC碼是碼長N為16200位元、編竭率為 8/9之LDPC碼,進一步調變方式為4096QAM,倍數^^為!: 情況下之分配規則。 於圖120之分配規則,規定有群組集合資訊 (Gb2,Gyi,l),(Gb3,Gyi,l),(Gb3,Gy2,2),(Gb3,Gy3,2),(Gb3,Gy4,2), (Gb3,Gy5,l),(Gb4,Gy6,l),(Gb5,Gy5,l)。 亦即,於圖120之分配規則,規定如下: 根據群組集合資訊(Gb〗,Gy6,l),將錯誤概率第!良好之 © 碼位元群組Gbi之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組G y6之符元位元之1位元; 根據群組集合資訊(Gbz,Gyi,l),將錯誤概率第2良好之 碼位元群組Gh之碼位元之丨位元,分配給錯誤概率^ 好之符元位元群組Gy〗之符元位元之丨位元; 根據群組集合資訊(Gb3,Gyi,l),將錯誤概率第3良好之 碼位元群組Gbs之碼位元之】位元,分配給錯誤概率'"第】良 好之符元位元群組Gyi之符元位元之!位元; 义 ® 根據群組集合資訊(Gb3,Gy2,2),將錯誤概率第3良好之 碼位元群組Gh之碼位元之2位元,分配給錯誤概率 <第2良 好之符元位元群組Gy〗之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2),將錯誤概率第好之 碼位元群組Gbs之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb3,Gy4,2) ’將錯誤概率第3 ^ 碼位元群組Gh之碼位元之2位元,分配給錯誤概率'"第斗良 135786.doc -163· 200937872 好之符元位元群組Gy*之符元位元之2位元; 根據群組集合資訊(队办山,將錯誤概率第3良好之 瑪位元群組Gb3之碼位元之1位元,分配給錯誤概:第5良 好之符元位元群組Gb之符元位元之丨位元; 根據群組集合資訊(GhGy6,〗),將錯誤概率第4良好之 碼位元群組Gb4之碼位元之i位元,分配給錯誤概率I良 好之符元位元群組Gy0之符元位元之1位元; 及根據群組集合資訊((^,(^⑴’將錯誤概率第^义好 €>之碼位元群組Gb5之碼位元之1位元,分配給錯誤概率第5 良好之符元位元群組Gys之符元位元之丨位元。 圖121係表示按照圖120之分配規則之碼位元之替換例。 亦即,圖121A係表示LDPC碼是碼長N*162〇〇位元、編 碼率為8/9之LDPC碼,進一步調變方式為4〇96QAM,倍數 b為1之情況下之按照圖120之分配規則之碼位元之替換之 第1例。 ❹ LDPC碼是碼長N為16200位元、編碼率為8/9之LDpc 碼,進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(12><ι))χ (12x1)位元之記憶體31寫入之碼位元係於橫列方向以 12xl(=mb)位元單位讀出,並供給至替換部32(圖16、 17) 〇 替換部32係按照圖120之分配規則,將讀出自記憶體3 j 之12xl(=mb)位元之碼位元至bn,例如圖121A所示分配 給l(=b)個符元之i2xi(=mb)位元之符元位元yQ至yn,以替 135786.doc -164- 200937872 換12xl(=mb)位元之瑪位元b〇至bii。 亦即,替換部32係分別 將碼位元b〇分配給符元位元yio ’ 將碼位元b 1分配給符元位元y〇, 將碼位元b2分配給符元位元y, ’ 將碼位元b〗分配給符元位元y2’ 將碼位元b4分配給符元位元y3, 將崎位元bs分配給符元位元y4, ❾ 將碼位元b6分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元bs分配給符元位元y8, 將碼位元b9分配給符元位元y7, 將碼位元b 1 〇分配給符元位元y〗丨, 將碼位元th ]分配給符元位元y9, 而進行替換。 ❹ 圖121B係表示LDPC碼是碼長N為16200位元、編碼率為 8/9之LDPC碼,進一步調變方式為4〇96qam,倍數b為1之 情況下之按照圖120之分配規則之碼位元之替換之第2例。 若根據圖121B,替換部32係按照圖12〇之分配規則,針 對從§己憶體31所讀出之i2xi(=mb)位元之碼位元b()至bn, 分別進行下述替換: 將碼位元bG分配給符元位元yu, 將碼位元比分配給符元位元yi, 將碼位元bz分配給符元位元y3, 135786.doc •165· 200937872 將碼位元b3分配給符元位元y4, 將碼位元t»4分配給符元位元y 5, 將碼位元b5分配給符元位元y〇, 將碼位元1?6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y6, 將碑位元b 1 〇分配給符元位元y! 〇, © 將瑪位元b 1 1分配給符元位元y8。 圖122係表不LDPC碼是碼長N為64800位元、編碼率為 8/9之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之碼位元群組及符元位元群組。 該情況下’從記憶體3 1所讀出之12X 1 (=mb)位元之碼位 元係根據錯誤概率之差別,如圖122A所示可群組區分為5 個碼位元群組 Gbi,Gb2,Gb3,Gb4,Gb5。 於圖122A ’分別而言’碼位元群組Gbi係碼位元b〇所 屬’碼位元群組Gb>2係碼位元bi所屬’碼位元群組(}b3係碼 位元h至b?所屬,碼位元群組GW係碼位元151()所屬,碼位 元群組Gb5係碼位元bn所屬。 調變方式為4096QAM,倍數b為1之情況下,i2xl(=mb) 位元之符元位元係根據錯誤概率之差別,如圖122B所示可 群組區分為6個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖122B,與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元yQ,y!所屬,符元位元群組Gy2係符元位 135786.doc -166- 200937872 元yz,y3所屬’符元位元群組Gw係符元位元所屬,符 元位元群組Gy*係符元位元ye,y7所屬,符元位元群組係 符元位元ys,y9所屬,符元位元群組Gy6係符元位元yiQ,y" 所屬》 圖123係表示LDPC碼是碼長n為64800位元、編碼率為 8/9之LDPC碼,進一步調變方式為4〇96QAM,倍數之 情況下之分配規則。 於圖123之分配規則,規定有群組集合資訊 © (Gb2,Gy1,l),(Gb3,Gy1,l),(Gb3,Gy252),(Gb3,Gy3,2),(Gb3,Gy4,2), (Gb3,Gy5,l),(Gb4,Gy6,l),(Gb5,Gy5,1)。 亦即,於圖123之分配規則,規定如下: 根據群組集合資訊(Gb^Gy^l),將錯誤概率第i良好之 碼位元群組Gb〗之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gye之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第2良好之 碼位元群組Gb2之碼位元之1位元’分配給錯誤概率第i良 好之符元位元群組Gy!之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第^良 好之符元位元群組Gy!之符元位元之丨位元; 根據群組集合資訊(Gb3,Gy2,2) ’將錯誤概率第3良好之 碼位元群組Gb>3之碼位元之2位元,分配給錯誤概率第 好之符元位元群組Gyz之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2) ’將錯誤概率第3良好之 135786.doc •167· 200937872 碼位元群組Gfc»3之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb3,Gy4,2),將錯誤概率第3良好之 碼位元群組Gt>3之碼位元之2位元,分配給錯誤概率第4良 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊(Gl>3,Gy5,l),將錯誤概率第3良好之 碼位元群組Gbs之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gt>4,Gy6,1),將錯誤概率第4良好之 碼位元群組GW之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; 及根據群組集合資訊(Gb^Gy^l),將錯誤概率第5良好 之碼位元群組Gbs之碼位元之1位元’分配給錯誤概率第5 良好之符元位元群組Gys之符元位元之1位元。 圖124係表示按照圖123之分配規則之碼位元之替換例。 亦即,圖124A係表示LDPC碼是碼長Ng 648〇〇位元、編 碼率為8/9之LDPC碼,進一步調變方式為4〇96QAM,倍數 b為1之情況下之按照圖12 3之分配規則之碼位元之替換之 第1例。 LDPC碼是碼長N為64800位元、編碼率為8/9之LDpc 碼,進一步調變方式為4096QAM、倍數bgi之情況下,於 解多工器25 ’於縱行方向X橫列方向為(648〇〇/(ΐ2χΐ))χ (12 X 1)位元之s己憶體3 1寫入之碼位元係於橫列方向,以 12xl(=mb)位元單位讀出,並供給至替換部32(圖16、圖 135786.doc -168- 200937872 17卜 替換部32係按照圖123之分配規則,將讀出自記憶體3ι 之12xU=mb)位元之碼位元b〇至bn,例如圖124A所示分配 給l(=b)個符元之i2xi(=mb)位元之符元位元y〇至yn,以替 換12xl(=mb)位元之碼位元b〇至bn。 亦即,替換部32係分別 將碼位元bG分配給符元位元y10, 將碼位元b〗分配給符元位元y 0, © 將碼位元b2分配給符元位元y 1, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y7, ® 將碼位元b1Q分配給符元位元yn, 將碼位元b i.i分配給符元位元y9 ’ 而進行替換。 圖124B係表不LDPC碼是碼長N為64800位7C*、編碼率為 8/9之LDPC碼,進一步調變方式為4096QAM,倍數b為1之 情況下之按照圖123之分配規則之碼位元之替換之第2例。 若根據圖124B,替換部32係按照圖123之分配規則,針 對從記憶體31所讀出之12xl(=mb)位元之碼位元bG至bn, 135786.doc -169- 200937872 分別進行下述替換: 將碼位元bG分配給符元位元yi t, 將碼位元b!分配給符元位元y!, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y 5, 將瑪位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 〇 將碼位元b7分配給符元位元y7, 將竭位元be分配給符元位元y9, 將碼位元t>9分配給符元位元y6, 將瑪位元b 1 〇分配給符元位元y丨〇, 將碼位元bn分配給符元位元y8。 圖125係表示LDPC碼是碼長N為64800位元、蝙竭率為 9/10之LDPC碼,進一步調變方式為4〇96QAM,倍數bAi 之情況下之瑪位元群組及符元位元群组。 該情況下,從記憶體31所讀出之I2xl(=mb)位元之碼位 元係根據錯誤概率之差別,如圖125 A所示可群組區分為5 個碼位元群組GbhGbhGbhGb^Gbs。 於圖125A,分別而言,碼位元群組Gbi係碼位元、所 屬,碼位元群組Gh係碼位元比所屬,碼位元群組Gb3係碼 位元bz至b所屬’碼位元群組Gb4係碼位元!^。所屬,碼位 元群組Gb5係碼位元b!丨所屬。 調變方式為4096QAM,倍數之情況下,12xl卜邮) 135786.doc -170. 200937872 位元之符元位元係根據錯誤概率之差別,如圖125B所示可 群組區分為6個符元位元群組Gyi,Gy2,Gy3,Gy4,Gy5,Gy6。 於圖125B ’與圖95B之情況相同,分別而言,符元位元 群組Gy!係符元位元yG,yi所屬,符元位元群組Gy2係符元位 元y2,ys所屬,符元位元群組GY3係符元位元y4,y5所屬,符 元位元群組Gy〗係符元位元y0,y7所屬,符元位元群組Gy5係 符元位元丫8,乃所屬’符元位元群組Gy6係符元位元yiQ,yu 所屬。 圖126係表示LDPC碼是碼長N為64800位元、編碼率為 9/10之LDPC碼,進一步調變方式為4〇96qA]vi,倍數 之情況下之分配規則。 於圖126之分配規則,規定有群組集合資訊 (Gb2,Gy1,l),(Gb3,Gy1,l),(Gb3,Gy2,2),(Gb3,Gy3j2),(Gb3,Gy4,2), (Gb3,Gy5,l),(Gb4,Gy6,l),(Gb5,Gy5,l)。 亦即’於圖126之分配規則,規定如下: 根據群組集合資訊(Gth’Gye’l),將錯誤概率第j良好之 碼位兀群組Gb丨之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy0之符元位元之1位元; 根據群組集合資訊(Gb^Gy^l),將錯誤概率第2良好之 碼位兀群組Gbz之碼位元之1位元,分配給錯誤概率第^戸 好之符元位元群組Gy〗之符元位元之丨位元; 又 根據群組集合資訊(Gb3,Gyi,l),將錯誤概率第3良好之 碼位元群組Gh之碼位元之1位元,分配給錯誤概率第1声 好之符元位元群組Gy!之符元位元之1位元; 135786.doc -17! · 200937872 根據群組集合資訊(Gb3,Gy2,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第2良 好之符元位元群組Gy2之符元位元之2位元; 根據群組集合資訊(Gb3,Gy3,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第3良 好之符元位元群組Gy3之符元位元之2位元; 根據群組集合資訊(Gb3,Gy4,2),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之2位元,分配給錯誤概率第4良 〇 好之符元位元群組Gy4之符元位元之2位元; 根據群組集合資訊(Gb3,Gy5,l),將錯誤概率第3良好之 碼位元群組Gb3之碼位元之1位元,分配給錯誤概率第5良 好之符元位元群組Gy5之符元位元之1位元; 根據群組集合資訊(Gb4,Gy6,l),將錯誤概率第4良好之 碼位元群組Gb4之碼位元之1位元,分配給錯誤概率第6良 好之符元位元群組Gy6之符元位元之1位元; 及根據群組集合資訊(Gb5,Gy5,l),將錯誤概率第5良好 ^ 之碼位元群組Gb5之碼位元之1位元,分配給錯誤概率第5 良好之符元位元群組Gy 5之符元位元之1位元。 圖127係表示按照圖126之分配規則之碼位元之替換例。 亦即,圖127A係表不LDP C碼是碼長N為64800位7〇、編 碼率為9/10之LDPC碼,進一步調變方式為4096QAM,倍 數b為1之情況下之按照圖126之分配規則之碼位元之替換 之第1例。LDPC is an LDPC code with a code length N of 64,800 bits and a coding rate of 4/5. In the case where the modulation is 4096QAM and the multiple b is 1, the multiplexer 25 is in the X direction in the wales. The direction is (648〇〇/(ΐ2χΐ))χ (12 1) bits of the suffix 3 1 written code bits are in the horizontal direction, read in 12xl (= mb) bit units 'and Supply to the replacement unit 32 (Fig. 16, Fig. 17) The replacement unit 3 2 reads the code bit % from the 12xl (= mb) bits of the memory 3 J to bn ' according to the allocation rule of Fig. 11 For example, as shown in Fig. 112A, the symbol bits yG to yu of the i2x1 (= mb) bits assigned to the l (= b) symbols are replaced with the code bits % to bn of the 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, and assigns the bit b! to the symbol bit y, respectively, 135786.doc • 152-200937872 assigns the megabyte b For the symbol bit y6, the code bit b3 is assigned to the symbol bit yj, the code bit b4 is assigned to the symbol bit y4, and the code bit b5 is assigned to the symbol bit y5, and the code bit is assigned B6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y丨〇. © Assign the code bits b, 〇 to the symbol bits y, i, and assign the code bits b to the symbol y9 for replacement. Figure 112B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and further modulation is 4096qAM, and the multiple b is 1, the code bit according to the allocation rule of Fig. 111 The second example of replacement. According to FIG. 1 UB, the replacement unit 32 performs the following replacement for the code bits from the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 111, d U 1 W : assigning the code bit b〇 to the symbol bit y9, assigning the code bit b! to the symbol bit yi, assigning the code bit b2 to the symbol bit y 3, and assigning the mbit b3 to The symbol bit y4 assigns the code bit b4 to the symbol bit y 5 , assigns the code bit bs to the symbol bit y , and assigns the m place b6 to the symbol bit y 2, 135786. Doc -153 - 200937872 assigning code bit b7 to symbol bit y7 ' assigning code bit 1) 8 to symbol bit y6, and assigning code bit b9 to symbol bit yn ' will be code bit 131() is assigned to symbol bit 710' to assign code bit b1] to symbol bit y8. Figure 113 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and a further modulation method is 4096QAM, and a multiple of b is a code bit group and a symbol bit. Group. © In this case, the code bits of the 12x1 (= mb) bits read from the memory 31 are grouped into 4 code bit groups Gb1 according to the difference in error probability, as shown in FIG. 113A. Gb2, Gb3, Gb4. In FIG. 113A, respectively, the code bit group Gbl is associated with the code bit ^, the code bit group Gh is the code bit to be !)8 belongs to, the code bit group Gb3 is the code bit bp belongs to The code bit group Gh is a code bit and belongs to bn. When the modulation mode is 4096QAM and the multiple b is 1, the i2xl (= mb) ❹ bit symbol is based on the difference in error probability. As shown in FIG. 113B, the group can be divided into 6 symbol bits. Groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 113B, as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yG, yi belongs to, and the symbol bit group is a symbol bit yz, y3 belongs to, and The meta-bit group is a symbol element y4, y5 belongs to, the symbol bit group Gh is a symbol element Υ6, & belongs to, the symbol element group Gy5 is a symbol element bit belongs to The meta-bit group Gy6 is a symbol element yiG, yu belongs to it. Figure 114 is a diagram showing an LDPC code whose code length is 162 〇〇 bit code rate 135786.doc -154 - 200937872 5/6, and the modulation method is 4096QAM, and the multiple is i is i. . In the allocation rule of Fig. 114, group group information (Gbi Gy5 ^ (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb25Gy4, 2), (Gb3, Gy6 1) (Gb4, Gy5, l), (Gb4, Gy6, l). That is, the allocation rule in Figure 114 is as follows: According to the group collection information (Gb, Gy5, l), the error probability is i good code bit group Gth code bit 1 bit 'assigned to error probability 5th good © good symbol bit group Gy 5 symbol bit 1 bit; according to group set Information (Gl>2, Gy!, 2) 'Assign the 2nd bit of the code bit of the 2nd good maze group Gt>2 of the error probability to the symbol group Gy with the wrong probability probability 2 bits of the symbol bit of i; according to the group set information (Gb2, Gy, 2), the 2 bits of the code bit of the 2nd good code bit group Gbz of the error probability are assigned to the error 2nd bit of the symbolic second bit symbol group Gy2; ❹ According to the group set information (Gb2, Gy3, 2) 'The error probability second good code bit group Gh 2 bits of the code bit, assigned to the 3rd good symbol group Gy with the wrong probability 2 bits of the symbol element of 3; according to the group set information (Gb2, Gy4, 2), the 2nd bit of the code bit of the second good code bit tl group Gh of the error probability is assigned to the error probability The 4th good symbol element group Gy4 is a 2-bit symbol; according to the group set information, the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability is allocated. Give the error probability the sixth good symbol group Gy6 symbolic bit 1 bit; 135786.doc -155- 200937872 According to the group collection information (Gb4, Gys, l) 'The error probability is 4th good 1 bit of the code bit of the code bit group GW, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gys of the error probability; and according to the group set information (Gb> 4, Gy6, l), assigning the 1st bit of the code bit of the 4th good code bit group Gh of the error probability to the symbol bit of the 6th good symbol bit group Gy0 of the error probability Figure 115 is an alternative to the code bit according to the allocation rule of Figure 114. That is, Figure 115A shows that the LDPC code is a length of 16200 bits and a code rate of 5/6. The first example of the replacement of the code bits according to the allocation rule of Fig. 114 in the case where the DPC code is further modulated by 4〇96QAM and the multiple b is 1. The LDPC is a code length N of 16,200 bits and a coding rate. In the case where the 5/6 LDpc code 'further modulation mode is 4096QAM and the multiple b is 1, the demultiplexer 25' is in the direction of the X direction (162〇〇/(12χ1))χ ( The code bits written by the 12x1) bit memory 31 are read in the order of 12x l (-mb) bits in the course direction and supplied to the replacement unit 32 (Fig. μ, Fig. V 17). The replacing unit 3 2 allocates the code bits b() to b11 from the 12x1 (= mb) bits of the memory 3 1 according to the allocation rule of FIG. 114, for example, as shown in FIG. U5A, to l(=b) The symbol y of the I2xl (= mb) bit of the symbol. To yn, replace the code bits bQ to bn of 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, respectively, and assigns the code bit bi to the symbol bit y, 135786.doc -156- 200937872 assigns the code bit b2 to the symbol The bit y6 assigns the code bit b3 to the symbol y!, assigns the code bit b4 to the symbol y4, and assigns the code bit b5 to the symbol y5, and the code bit 1 6 is assigned to symbol bit y2, code bit b7 is assigned to symbol bit y 3, code bit b8 is assigned to symbol bit y7, and code bit b9 is assigned to symbol bit y 1 〇, 分配 The code bit 1?1() is assigned to the symbol bit yn, and the code bit bi! is assigned to the symbol bit y9 for replacement. Figure 115B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and further modulation is 4096QAM. When the multiple b is 1, the code bit according to the allocation rule of Fig. 114 is used. The second example of replacement. According to FIG. 115B, the replacing unit 32 performs the following replacement for the code bits bQ to bu of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 114: bG is assigned to the symbol bit y9, the code bit b] is assigned to the symbol bit y, the code bit b2 is assigned to the symbol y3, and the code bit b3 is assigned to the symbol y4. The code bit b4 is assigned to the symbol bit y 5 , the code bit b5 is assigned to the symbol bit y 〇 , and the code bit b6 is assigned to the symbol bit y2 , 135786.doc -157- 200937872 Bit b7 is assigned to symbol bit y7, code bit be be assigned to symbol bit y6, code bit b9 is assigned to symbol bit yi!, and code bit bi is assigned to symbol bit丫10, the code bit b 1 is assigned to the symbol bit y 8 . Figure 11 shows that the LDPC code is an LDPC code with a code length N of 64 8 00 bits and a coding rate of 5/6, and the modulation mode is 4096QAM, and the code bit group and the symbol bit in the case of the multiple i Meta group. ® In this case, the difference between the error vectors of the I2xl (= mb) bits read from the memory 31 can be grouped into 3 code bit groups Gbi as shown in Fig. 116A. Gb2, Gb3 » In Fig. 116A, respectively, the code bit group Gb is the code bit b〇, the code bit group Gbz is the code bit to the !)9, the code bit group Gb3 is The code bit 1 > 1 () and bn belong. When the modulation mode is 4096QAM and the multiple b is 1, the symbol bits of the 12xl (= mb) bits are grouped into six symbol bit groups according to the difference in error probability as shown in FIG. 116B. Group Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 116B, as in the case of FIG. 95B, respectively, the symbol bit group Gy is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit yZ, y3 belongs to, The symbol element group Gy3 is represented by the symbol element y4, ys belongs to, the symbol element group Gy* is the symbol element y0, y7 belongs to, and the symbol element group symbol 兀, y9 belongs to , the symbol element group Gy6 is a symbol element belongs to. Figure 7 shows that the LDPC code is LDPC code with a code length of ^^ of 648, and the coding rate is 135786.doc -158· 200937872 5/6. The further modulation method is 4〇96QAM, and the multiple is 1? The distribution rules in the case. In the allocation rule of FIG. 117, group group information (Gbi, Gy5, 1}, (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, 2), (Gb2, Gy6, l), (Gb3, Gy5, l), (Gb3, Gy6, l) 〇 That is, the allocation rule in Figure 117 is specified as follows: According to the group collection information (Gb^Gy^ l), assigning the 1-bit ' of the code bit of the first good code bit group Gb 1 to the error probability 5th good © the good symbol bit group Gy5 Bit; according to the group set information (Gb2, Gy!, 2) 'The second bit of the code bit of the error probability second good code bit group Gb>2 is assigned to the first probability of the error probability The bit group Gy, the 2 bit of the symbol bit; according to the group set information (Gbz, Gy2, 2), the 2nd bit of the code bit of the second good code bit group Gb2 of the error probability Yuan, assigned to the 2nd bit of the symbol bit of the second good symbol group Gy2 of the error probability; © according to the group set information (Gb2, Gy3, 2) 'The second probability of the error probability 2 bits of the code bit of the meta-group Gb2, assigned to the third probability of error probability The good symbol meta-group Gy is the 2-bit symbol; according to the group collection information (Gb2, Gy4, 2) 'The error probability second good code group Gt> 2 code The 2-bit of the bit is assigned to the 2-bit of the symbol bit of the fourth-perfect symbol group Gy4 of the error probability; according to the group set information (Gl>2, Gy6, 1), the error probability 1 bit of the code bit of the second good code bit group Gb2, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability; 135786.doc -159- 200937872 According to the group set information (Gb3, Gys, l), the unit of the code bit of the 3rd good code bit group Gh of the error probability is assigned to the 5th good symbol bit group of the error probability. 1 bit of the symbol bit of Gys; and according to the group set information (Gb^G^D, assign the error bit of the code bit of the 3rd good code bit group Gbs of the error probability to the error Fig. 118 is an alternative example of the code bit according to the allocation rule of Fig. 117. That is, Fig. 118A shows an LDPC code. The code length N is 64800 bits, the docking code rate is 5/6 LDPC code, and the further modulation mode is 4〇96qAM, and the multiple b is 1 in the case of replacing the code bit according to the allocation rule of FIG. The first example of the LDPC code is an LDpc code having a code length N of 64,800 bits and a coding rate of 5/6. In the case where the modulation method is 4096QAM and the multiple b is 1, the multiplexer 25 is on the traverse. The direction X direction of the direction is (648〇〇/(12χ1))χ (12 X 1) bits of the suffix 3 1 written horses are in the horizontal direction, with 12xl (= mb) bits The unit is read out and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b() from the 12x1 (= mb) bits of the memory 3 i to the bu according to the allocation rule of FIG. 117, for example, as shown in FIG. 118A, assigns 1 (=b) characters. The symbol bits y〇 to yn of the l2xl (= mb) bits of the element are substituted for the code bits b〇 to bn of the 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit b! to the symbol bit yG, 135786.doc -160· 200937872 assigns the code bit b2 to Symbol bit y 6, assign code bit b3 to symbol bit y, assign code bit b4 to symbol y4, assign code bit b5 to symbol y5, place code bit The element b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y! , © assigns the code bit b 1 〇 to the symbol bit y 1 J, and assigns the code bit b 1 1 to the symbol bit y9 for replacement. Figure 118B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6. The further modulation method is 4096QAM, and the multiple 1 is a code position according to the allocation rule of Fig. 117 in the case of i. The second example of the replacement of Yuan. According to FIG. 118B, the replacing unit 32 performs the following replacement for the code bits bG to bn, W of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 117: The element b〇 is assigned to the symbol bit y9, the code bit b 1 is assigned to the symbol bit y J , the code bit b is assigned to the symbol bit y 3 , and the code bit b3 is assigned to the symbol Bit y4, the numerator b4 is assigned to the symbol y5, the symbol bs is assigned to the symbol y, and the symbol is assigned to the symbol y2, 135786.doc -161 - 200937872 assigns the code bit b7 to the symbol bit y7, assigns the code bit b8 to the symbol bit yn, assigns the code bit b 9 to the symbol bit y 6, and assigns the code bit b 1〇 The symbol bit yi 给 is assigned to the symbol bit y8. Figure 119 is a diagram showing that the LDPC code is a code bit group and a symbol bit in the case where the code length N is 16,200 bits and the coding rate is 8/9, and the further modulation method is 4096QAM, and the multiple b is 1. Group. In this case, the code bits of the I2x1 (= mb) bits read from the memory 31 are group-divided into 5 code bits 7C group Gb 1 according to the difference in error probability as shown in FIG. 119A. , Gb2, Gb3, Gb4, Gb5. 119A, respectively, the code bit group Gb is the code bit group b belongs to the 'code bit group Gb2 code bit b! belongs to, the code bit group Gb3 is the code bit h to belong to The 'code bit group Gb4 is the code bit 1) 1() belongs to, and the code bit group Gb is the code bit bn. When the modulation method is 4096 Q AM 'when the multiple b is 1, the 12x1 (= mb) bit symbol is based on the difference in error probability, as shown in Figure 9B, the group can be divided into 6 symbols. The bit group is 1,0丫2, 〇73,0丫4, 〇75, 〇76. In FIG. 119B, as in the case of FIG. 95B, respectively, the symbol bit group Gyi is associated with the symbol bit, and the symbol bit group Gy2 is the symbol bit y2, y3 belongs to the symbol bit. Group Gy3 is a symbol element y4, y5 belongs to, symbol element group Gy4 is a symbol element y6, y7 belongs to, symbol element group Gy5 is a symbol element ys, y9 belongs to 'female position The meta-group Gy6 is a symbol element yi〇, yii belongs to. 135786.doc -162- 200937872 圊120 indicates that the LDPC code is an LDPC code with a code length N of 16200 bits and a compilation rate of 8/9. The further modulation method is 4096QAM, and the multiple ^^ is! : Distribution rules in the case. The distribution rule in Fig. 120 specifies group information (Gb2, Gyi, l), (Gb3, Gyi, l), (Gb3, Gy2, 2), (Gb3, Gy3, 2), (Gb3, Gy4, 2), (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, l). That is, the distribution rule in Figure 120 is as follows: According to the group collection information (Gb, Gy6, l), the error probability is the first! 1 bit of the code bit of the good © code bit group Gbi, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group G y6 of the error probability; according to the group set information ( Gbz, Gyi, l), assigning the bit position of the code bit of the second good code bit group Gh of the error probability to the symbol bit of the error probability ^ good symbol bit group Gy丨 bit; according to the group set information (Gb3, Gyi, l), the bit of the code bit of the third good code bit group Gbs of the error probability is assigned to the error probability '" The symbolic bit group Gyi is the symbol bit! Bits; Sense® assigns the error probability to the error probability <2nd good according to the group set information (Gb3, Gy2, 2), the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability 2 bits of the symbol element of the symbol element group Gy; 2 bits of the code bit of the code bit group Gbs with the wrong probability probability according to the group set information (Gb3, Gy3, 2) Yuan, assigned to the 2nd bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability; according to the group set information (Gb3, Gy4, 2) 'The error probability 3rd code bit group The 2 bits of the code bit of the group Gh are assigned to the error probability '" Didouliang 135786.doc -163· 200937872 The 2nd bit of the symbolic element of the good symbolic group Gy*; Group assembly information (team-mountain, assigning the error probability to the 1st bit of the code bit of the 3rd good-horse group Gb3 to the error: the 5th good symbol-bit group Gb The meta-bit of the element; according to the group set information (GhGy6, 〗), assigns the i-bit of the code bit of the fourth-order error bit group Gb4 of the error probability to the symbolic bit with good error probability I 1 bit of the symbol group of the meta group Gy0; and the code bit of the code bit group Gb5 according to the group set information ((^,(^(1)' will be the wrong probability) 1 bit, assigned to the bit element of the symbol bit of the symbolic group of the fifth good symbol bit Gys of Fig. 120. Fig. 121 is an alternative example of the code bit element according to the allocation rule of Fig. 120. FIG. 121A shows an LDPC code in which the LDPC code is a code length N*162 〇〇 bit and a coding rate of 8/9. The further modulation method is 4〇96QAM, and the multiple b is 1 in accordance with the allocation rule according to FIG. The first example is the replacement of the code bit. ❹ The LDPC code is an LDpc code with a code length N of 16200 bits and a coding rate of 8/9. When the modulation mode is 4096QAM and the multiple b is 1, the solution is solved. The multiplexer 25 writes the code bits written in the memory 31 of the (162 〇〇 / (12 >< ι)) χ (12 x 1) bits in the wale direction x column direction in the course direction by 12 x 1 The (= mb) bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the 12x1 (= mb) bits from the memory 3 j in accordance with the allocation rule of Fig. 120. Code bit to bn, for example Figure 1 The symbol bits yQ to yn assigned to the i2xi (= mb) bits of l (= b) symbols as shown in Fig. 21A are replaced by 135786.doc -164 - 200937872 for the position of 12xl (= mb) bits. The unit b〇 to bii. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit yio ', respectively, assigns the code bit b 1 to the symbol bit y 〇, and assigns the code bit b2 to The symbol bit y, ' assigns the code bit b to the symbol bit y2', assigns the code bit b4 to the symbol bit y3, and assigns the parity bit bs to the symbol bit y4, ❾ the code Bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, code bit bs is assigned to symbol bit y8, and code bit b9 is assigned to symbol bit y7. The code bit b 1 〇 is assigned to the symbol bit y 丨, and the code bit th ] is assigned to the symbol y9 for replacement. 121 FIG. 121B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and the further modulation method is 4〇96qam, and the multiple b is 1 according to the distribution rule of FIG. The second example of replacement of code bits. According to FIG. 121B, the replacing unit 32 performs the following replacement for the code bits b() to bn of the i2xi (= mb) bit read from the § memory 31 according to the allocation rule of FIG. 12B. : assigning the code bit bG to the symbol bit yu, assigning the code bit ratio to the symbol bit yi, and assigning the code bit bz to the symbol bit y3, 135786.doc • 165· 200937872 B3 is assigned to the symbol bit y4, the code bit t»4 is assigned to the symbol bit y 5, the code bit b5 is assigned to the symbol bit y 〇, and the code bit 1?6 is assigned to the symbol Bit y2, code bit b7 is assigned to symbol bit y7, code bit b8 is assigned to symbol bit y9, code bit b9 is assigned to symbol bit y6, and beacon bit b 1 〇 Assigned to the symbol y! 〇, © assigns the tilde b 1 1 to the symbol y8. Figure 122 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 8/9, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the 12X 1 (= mb) bits read from the memory 3 1 are group-divided into 5 code bit groups Gbi according to the difference in error probability as shown in FIG. 122A. , Gb2, Gb3, Gb4, Gb5. 122A 'respectively' the code bit group Gbi code bit b〇 belongs to the 'code bit group Gb> 2 code bit unit bi belongs to the 'code bit group' (}b3 code bit h The code bit group GW is associated with the code bit 151(), and the code bit group Gb5 is the code bit bn. The modulation mode is 4096QAM, and the multiple b is 1, i2xl (= The mb) bit symbol is based on the difference in error probability, and can be grouped into six symbol bit groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6 as shown in Fig. 122B. As in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yQ, y! belongs to, and the symbol bit group Gy2 is a symbol bit 135786.doc -166- 200937872 yuan yz , y3 belongs to the 'character bit group Gw system symbol element belongs to, the symbol element group Gy* is the symbol element ye, y7 belongs, the symbol element group symbol s, y9 Affiliation, symbol group Gy6 is a symbol element yiQ, y" belongs to Fig. 123 shows that the LDPC code is an LDPC code with a code length n of 64800 bits and a coding rate of 8/9, and the modulation mode is further 4〇96QAM, allocation in the case of multiples Then, in the distribution rule of Figure 123, the group collection information © (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy252), (Gb3, Gy3, 2), (Gb3, Gy4) is specified. , 2), (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, 1). That is, the distribution rule in Figure 123 is defined as follows: According to the group collection information (Gb^Gy ^l), assigning 1 bit of the code bit of the error probability bit i-th good code bit group Gb to 1 bit of the symbol bit of the 6th good symbol bit group Gye of the error probability According to the group set information (Gb^Gy^l), the 1st bit of the code bit of the 2nd good code bit group Gb2 of the error probability is assigned to the error probability i-th good symbol bit group One bit of the symbol bit of the group Gy!; according to the group set information (Gb^Gy^l), the one bit of the code bit of the third good code bit group Gh of the error probability is assigned to Error probability ^^good symbol group Gy! symbol element bit; according to group set information (Gb3, Gy2, 2) 'The error probability third good code bit group Gb> 2 bits of the code bit of 3; assigned to the symbol of the wrong symbol group Gyz 2 bits of the bit; according to the group set information (Gb3, Gy3, 2) 'The error probability is 3rd good 135786.doc •167·200937872 code bit group Gfc»3 of the code bit 2 bits , assigned to the 2-bit of the symbol element of the third-perfect symbol group Gy3 of the error probability; according to the group set information (Gb3, Gy4, 2), the error probability third good symbol group The 2 bits of the code bit of the group Gt>3 are allocated to the 2 bit of the symbol bit of the symbol 4th group of the error probability group Gy4; according to the group set information (Gl>3, Gy5, l), assigning 1 bit of the code bit of the 3rd good code bit group Gbs of the error probability to 1 bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; According to the group set information (Gt > 4, Gy6, 1), the 1st bit of the code bit of the 4th good code bit group GW of the error probability is assigned to the 6th good symbol bit group of the error probability. One bit of the symbol bit of the group Gy6; and according to the group set information (Gb^Gy^l), assign the 1 bit of the code bit of the 5th good code bit group Gbs of the error probability to Error probability 5 Good symbol bits of the symbol bit group of Gys 1 yuan. Figure 124 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 123. That is, FIG. 124A shows that the LDPC code is an LDPC code having a code length of Ng 648 〇〇 bits and a coding rate of 8/9, and the further modulation method is 4 〇 96QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an LDpc code with a code length N of 64,800 bits and a coding rate of 8/9. In the case where the modulation method is 4096QAM and the multiple bgi, the direction of the multiplexer 25' in the wale direction X is (648〇〇/(ΐ2χΐ))χ (12 X 1) bits of the suffix 3 1 written code bits are in the horizontal direction, read in 12xl (= mb) bit units, and supplied To the replacement unit 32 (FIG. 16, FIG. 135786.doc-168-200937872), the replacement unit 32 b) the code bit b read from the memory of the memory 3i to the bn according to the allocation rule of FIG. 123 For example, as shown in FIG. 124A, the symbol bits y〇 to yn of the i2xi (= mb) bits allocated to 1 (=b) symbols are replaced by the code bits b to 12xl (= mb) bits. Bn. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y10, the code bit b to the symbol bit y 0, and the code bit b2 to the symbol bit y 1 . , the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b5 is assigned to the symbol bit y4, and the code bit b6 is assigned to the symbol bit Element y5, assigning code bit b7 to symbol bit y6, assigning code bit b8 to symbol bit y8, assigning code bit b9 to symbol bit y7, and assigning code bit b1Q to The symbol bit yn is assigned by assigning the code bit b ii to the symbol bit y9 '. Figure 124B shows that the LDPC code is an LDPC code with a code length N of 64800 bits and 7C* and a coding rate of 8/9. The further modulation method is 4096QAM, and the multiple b is 1 according to the code of the distribution rule of Fig. 123. The second example of the replacement of the bit. According to FIG. 124B, the replacing unit 32 performs the lowering of the code bits bG to bn, 135786.doc - 169 - 200937872 of the 12xl (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 123, respectively. Replacement: assign code bit bG to symbol bit yi t, assign code bit b! to symbol bit y!, assign code bit b2 to symbol y3, and code bit b3 Assigned to the symbol bit y4, the code bit b4 is assigned to the symbol bit y 5 , the megabyte b5 is assigned to the symbol y 〇 , and the code bit b6 is assigned to the symbol y y 2 , 〇 The code bit b7 is assigned to the symbol bit y7, the exhaust bit be is assigned to the symbol bit y9, the code bit t>9 is assigned to the symbol bit y6, and the m-bit b 1 〇 is assigned to The symbol bit y is assigned to the symbol bit y8. Figure 125 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a depletion rate of 9/10, and the further modulation method is 4 〇 96QAM, and the megabit group and the symbol bit in the case of the multiple bAi Meta group. In this case, the code bits of the I2x1 (= mb) bits read from the memory 31 are grouped into 5 code bit groups GbhGbhGbhGb^ according to the difference in error probability as shown in FIG. 125A. Gbs. In FIG. 125A, respectively, the code bit group Gbi is a code bit, belongs to, the code bit group Gh is a code bit ratio, and the code bit group Gb3 is a code bit bz to b belongs to the 'code. The bit group Gb4 is a code bit!^. Affiliation, the code bit group Gb5 is a code bit b! The modulation mode is 4096QAM, in the case of multiples, 12xl (post) 135786.doc -170. The symbol of the 200937872 bit is based on the difference in error probability, as shown in Fig. 125B, the group can be divided into 6 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In the case of FIG. 125B', as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2, ys belongs to The symbol element group GY3 is a symbol element y4, y5 belongs to, the symbol element group Gy is a symbol element y0, y7 belongs to, the symbol element group Gy5 is a symbol element 丫8, It belongs to the 'female element group Gy6 system symbol element yiQ, yu belongs. Figure 126 shows an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and a further modulation method of 4 〇 96qA]vi, in the case of a multiple. In the allocation rule of Figure 126, group aggregation information (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy2, 2), (Gb3, Gy3j2), (Gb3, Gy4, 2) are specified. , (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, l). That is, the allocation rule in Figure 126 is defined as follows: According to the group set information (Gth'Gye'l), the error probability jth good code bit is allocated to the 1 bit of the code bit of the group Gb丨. Give the 1st bit of the symbol bit of the 6th good symbol bit group Gy0 of the error probability; according to the group set information (Gb^Gy^l), the second good code bit of the error probability is the group Gbz The 1 bit of the code bit is assigned to the bit error element of the error probability bit group; Gy, according to the group set information (Gb3, Gyi, l), Assigning 1 bit of the code bit of the 3rd good code bit group Gh of the error probability to the 1st bit of the symbol bit of the first bit of the error probability group Gy!; 135786 .doc -17! · 200937872 According to the group set information (Gb3, Gy2, 2), the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the 2nd good error probability. 2 bits of the symbol bit of the symbol element group Gy2; according to the group set information (Gb3, Gy3, 2), the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability yuan, The second bit of the symbol bit assigned to the third bit symbol group Gy3 of the error probability; the third bit of the error probability group according to the group set information (Gb3, Gy4, 2) The 2 bits of the code bit of Gb3 are allocated to the 2nd bit of the symbol bit of the 4th good symbolic group Gy4 of the error probability; according to the group set information (Gb3, Gy5, l), Assigning 1 bit of the code bit of the 3rd good code bit group Gb3 of the error probability to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; The set information (Gb4, Gy6, l) assigns the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability to the symbol of the 6th good symbol bit group Gy6 of the error probability. 1 bit of the bit; and according to the group set information (Gb5, Gy5, l), the 1st bit of the code bit of the code bit group Gb5 of the 5th good error probability is assigned to the error probability 5th A good one of the symbol bits of Gy 5 of the symbol group. Figure 127 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 126. That is, FIG. 127A shows that the LDP C code is an LDPC code having a code length N of 64800 bits and 7 〇 and a coding rate of 9/10, and the further modulation method is 4096QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the allocation rule.
LDPC碼是碼長N為64800位元、編碼率為9/10之LDPC 135786.doc -172- 200937872 碼’進一步調變方式為4096QAM、倍數b為1之情況下,於 解多工器25,於縱行方向X橫列方向為(64800/(12xl))x (12x 1)位元之記憶體31寫入之碼位元係於橫列方向,以 12xl (=mb)位元單位讀出,並供給至替換部32(圖16、kj 圈 17) 〇 替換部3 2係按照圖12 6之分配規則,將讀出自記憶體3 1 之12xl(=mb)位元之碼位元bQ至bn,例如圖127A所示分配 给l(=b)個符元之12xl(=mb)位元之符元位元y❹至yn,以替 換11 (=mb)位元之碼位元b〇至bn。 亦即,替換部32係分別 將碼位元b〇分配給符元位元丫10, 將碼位元b 1分配給符元位元y〇, 將碼位元b2分配給符元位元y j, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b 5分配給符元位元y 4, ❹ 將碼位元分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元bg分配給符元位元y8, 將碼位元b9分配給符元位元y7, 將碼位元b 1 〇分配給符元位元y丨丨, 將碼位元b 1 1分配給符元位元y9, 而進行替換。 囷127B係表示LDPC碼是碼長N為64800位元、編碼率為 135786.doc •173- 200937872 9/10之1^卩(:碼,進一步調變方式為4096(^入]^,倍數1)為1 之情況下之按照圖126之分配規則之碼位元之替換之第2 例0 若根據圖127B,替換部32係按照圖126之分配規則,針 對從記憶體31所讀出之12xl(=mb)位元之碼位元bG至bn, 分別進行下述替換: 將碼位元bG分配給符元位元y! i, 將碼位元b丨分配給符元位元y!, © 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y〇, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y7, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y6, ® 將碼位元1)1()分配給符元位元丫10, 將碼位元b i!分配給符元位元y 8。 以上,作為新替換方式之替換處理,說明分別將碼長N 為 64800位元、編碼率為 2/3、3/4、4/5、5/6、8/9、9/10之 6種類之LDPC碼,以1024QAM及4096QAM之2種類之調變 方式分別調變之情況下之12種類之替換處理,及分別將碼 長N為16200位元、編碼率為2/3、3/4、4/5、5/6、8/9之5 種類之LDPC碼,以1024QAM及4096QAM之2種類之調變 135786.doc -174· 200937872 方式分別調變之情況下之1 〇種類之替換處理,合計說明22 種類之替換處理,該22種類之處換處理係作為替換碼位元 之替換方式,可藉由例如採用4種類之替換方式,利用該4 種類之替換方式中之任一種來進行。 亦即,於以1024QAM調變碼長Ν為64800或16200位元、 編碼率為3/4、4/5或5/6之LDPC碼之情況下,替換處理能 以例如圖70Α等所表示之替換方式分別進行如下: 將碼位元b〇分配給符元位元y6, 〇 將碼位元b!分配給符元位元y 4, 將碼位元b2分配給符元位元y8, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y〇, 將碼位元b5分配給符元位元y2, 將碼位元b6分配給符元位元y!, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y9, ❹ 將碼位元b9分配給符元位元y7。 而且,於以4096QAM調變碼長N為64800或16200位元、 編碼率為3/4、4/5或5/6之LDPC碼之情況下,替換處理能 以例如圖103 A等所表示之替換方式分別進行如下: 將碼位元b〇分配給符元位元y8, 將碼位元b!分配給符元位元y 〇, 將碼位元b2分配給符元位元y6, 將碼位元b3分配給符元位元y!, 135786.doc -175- 200937872 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y! 〇, 將碼位元b! 〇分配給符元位元y 1!, 將碼位元b!!分配給符元位元y 9。The LDPC code is an LDPC with a code length N of 64,800 bits and a coding rate of 9/10. 135786.doc -172- 200937872 code 'When the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is used. The code bits written in the memory 31 of the (64800/(12x1)) x (12x 1) bits in the wale direction X direction are in the course direction, and are read out in 12xl (= mb) bit units. And supplied to the replacement unit 32 (FIG. 16, kj circle 17). The replacement unit 3 2 reads the code bit bQ from the 12x1 (= mb) bit of the memory 3 1 according to the allocation rule of FIG. Bn, for example, the symbol bits y❹ to yn of 12xl (= mb) bits allocated to l (=b) symbols as shown in FIG. 127A, in place of the code bits b of 11 (= mb) bits Bn. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 分别10, the code bit b1 to the symbol bit y, and the code bit b2 to the symbol yj. , the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b 5 is assigned to the symbol bit y 4, ❹ the code bit is assigned to the symbol The bit position y5 assigns the code bit b7 to the symbol bit y6, the code bit bg to the symbol bit y8, and the code bit b9 to the symbol bit y7, and the code bit b 1 〇 is assigned to the symbol bit y丨丨, and the code bit b 1 1 is assigned to the symbol bit y9 for replacement.囷 127B indicates that the LDPC code has a code length N of 64,800 bits and a coding rate of 135,786.doc • 173 - 200937872 9/10 of 1^卩 (: code, further modulation is 4096 (^) ^, multiple 1 In the case of 1 , the second example 0 of the replacement of the code bit according to the allocation rule of FIG. 126 is as follows. According to FIG. 127B, the replacing unit 32 is for the 12x1 read from the memory 31 according to the allocation rule of FIG. The code bits pG to bn of the (= mb) bit are respectively replaced by the following: the code bit bG is assigned to the symbol bit y! i, and the code bit b is assigned to the symbol bit y! © assign code bit b2 to symbol bit y3, code bit b3 to symbol bit y4, code bit b4 to symbol bit y5, and code bit b5 to symbol bit Element y, assigning code bit b6 to symbol bit y2, assigning code bit b7 to symbol bit y7, assigning code bit b8 to symbol bit y9, and assigning code bit b9 to The symbol bit y6, ® assigns the code bit 1)1() to the symbol bit 丫10, and the code bit bi! to the symbol bit y8. As described above, as a replacement process of the new alternative, six types of code length N of 64,800 bits and encoding ratios of 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are respectively described. The LDPC code is replaced by 12 types in the case of modulation of two types of 1024QAM and 4096QAM, and the code length N is 16,200 bits, and the coding rate is 2/3, 3/4, respectively. The LDPC code of the 5/5, 5/6, and 8/9 types is replaced by the 〇 〇 〇 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 In the total description of the type 22 replacement processing, the 22-type replacement processing is an alternative to the replacement code bit, and can be performed by using any of the four types of replacement methods, for example, by using four types of replacement methods. That is, in the case of an LDPC code having a modulation code length of 64800 or 16200 bits and a coding rate of 3/4, 4/5 or 5/6 in 1024QAM, the replacement processing can be expressed, for example, as shown in FIG. The alternatives are as follows: assign the code bit b〇 to the symbol bit y6, assign the code bit b! to the symbol bit y 4, and assign the code bit b2 to the symbol bit y8, The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to the symbol bit y!, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7. Moreover, in the case of an LDPC code having a code length N of 64800 or 16200 bits and a coding rate of 3/4, 4/5 or 5/6 in 4096QAM, the replacement processing can be expressed, for example, as shown in FIG. 103A or the like. The alternatives are as follows: assign the code bit b〇 to the symbol bit y8, the code bit b! to the symbol bit y 〇, and the code bit b2 to the symbol y6, the code Bit b3 is assigned to symbol bit y!, 135786.doc -175- 200937872 assigns code bit b4 to symbol bit y4, code bit b5 to symbol bit y5, and code bit b6 Assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y! 〇, The code bit b! 〇 is assigned to the symbol bit y 1!, and the code bit b!! is assigned to the symbol bit y 9.
進一步而言,於以1024QAM調變碼長N為64800或16200 位元、編碼率為2/3或8/9之LDPC碼,或碼長N為64800位 元、編碼率為9/10之LDPC碼之情況下,替換處理能以例 如圖64A等所表示之替換方式分別進行如下: 將碼位元bG分配給符元位元y8, 將碼位元b,分配給符元位元y 〇, 將碼位元b2分配給符元位元y】, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b5分配給符元位元y4, 將碼位元b6分配給符元位元y6, 將碼位元b7分配給符元位元y5, 將碼位元b8分配給符元位元y9, 將碼位元b9分配給符元位元y7。 而且,於以4096QAM調變碼長N為64800或16200位元、 編碼率為2/3或8/9之LDPC碼,或碼長N為64800位元、編 135786.doc -176· 200937872 碼率為9/10之LDPC碼之情況下,替換處理能以例如圖97A 等所表示之替換方式分別進行如下: 將碼位元bG分配給符元位元y 1 〇, 將碼位元b!分配給符元位元y 〇, 將碼位元b2分配給符元位元y!, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y3, 將碼位元b 5分配給符元位元y 4, 〇 將碼位元b6分配給符元位元y5, 將碼位元b7分配給符元位元y6, 將碼位元b8分配給符元位元y8, 將碼位元b9分配給符元位元y7, 將碼位元b! 〇分配給符元位元y!!, 將碼位元b η分配給符元位元y 9。 以上,針對調變方式為1024QAM之情況及4096QAM之 情況來說明關於新替換方式,以下說明關於各個調變方式 ® 之符元(對應之信號點)之配置。 圖128係表示以圖8之正交調變部27進行1024QAM之情況 下之1024個符元(對應之信號點)之IQ平面上之配置。 亦即,圖128係表示從DVB-T.2之256QAM之符元之配 置,歸納地求出1024QAM之符元之配置之方法。 此外,於圖128,(i,q)係表示符元之IQ平面上之座標(I座 標及Q座標)。 而且,C256(i,q)係表示序列式地附於256QAM之256個符 135786.doc -177- 200937872 元之特定出符元之號碼(以下亦稱為符元號碼)中之位於座 標(i,q)之位置之符元之(附於符元之)符元號碼。以下,位 於座標(i,q)之位置之256QAM之符元亦稱為第Cwdq)個符 元。 進一步而言,C1024(i,q)係表示1024QAM之1024個符元中 之位於座標(i,q)之位置之符元之符元號碼。以下,位於座 標(i,q)之位置之1024QAM之符元亦稱為第C1〇24(i,q)個符 7t 0 ❹ 現在,若使256QAM之256個符元全部平行移動於iq平面 上之第1象限内,則該平行移動後之256QAM之第C256(i,q) 個符元成為1024QAM之第Ci〇24(i,q)=C256(i,q)個符元。 進一步若使已平行移動於第1象限内之25 6QAM之256個 符元,對於I軸對稱移動,則該對稱移動後之256QAM之第 C256(i,q)個符元成為 1024QAM之第 C丨024(i,-q)=C256(i,q)+256 個符元。 而且,若使已平行移動於第1象限内之256QAM之256個 ® 符元,對於Q軸對稱移動,則該對稱移動後之256QAM之 第 C256(i,q)個符元成為 1024QAM之第 C丨〇24(-i,q)=C256(i,q)+ 256x2個符元。 進一步若使已平行移動於第1象限内之25 6QAM之256個 符元,對於原點對稱移動,則該對稱移動後之256QAM之 第 C256(i,q)個符元成為 1024QAM之第 C1024(-i,-q)=C256(i,q)+ 256x3個符元。 此外,關於上述第X個符元,以2進位表現X之值係表示 135786.doc •178- 200937872 該符元之值(符元被映射之信號點)。 例如C256(i,q)=25之情況下,第Cwdq)個符元之符元值 為0001 1001 B(B表示其前面之值為2進仅),而且例如 Ci〇24(i,q)=823之情況下’第Ci〇24(i,q)個符元之符元值為 1100110111B 。 而且,例如第2象限(I<0,Q>0)之第 256x2個符元(i,q>0)係位於使已平行移動於第1象限内之 256QAM之256個符το中之第C256(i,q)個符元,對於q柄呈 Ο 線對稱地移動後之位置’該第Ci〇24(-i,q)=c;25eii,q>+256x2 個符元之符元值啤於以2進位表現Czwdq)之值之高位2位 元,附加以2進位表現256x2中之2之值即10B後之值。 於1024QAM,1符元之位元數m為10,1符元之符元位元 從最高位位元表示作(yojb· · y6,y7,y8,y9) 〇 例如Ci〇24(i,q)=823之情況下’第Ci〇24(i,q)個符元之符元 值、亦即10位元之符元位元(y〇,yi,y2,y3,y4,y5,y6,y7,y8,y9^ ^ (1,1,M,1,1,G,1,1,1)。 然後,如圖62至圖94所說明,分別而言,符元位元y〇 ^ 係屬於符元位元群組Gy!,符元位元y^y3係屬於符元位元 群組Gyz,符元位元y^y5係屬於符元位元群組,符元位 元ye,y7係屬於符元位元群組Gy4,符元位元y8,y9係屬於符 元位元群組Gy5。 進一步而言,下標j屬於越小符元位元群組之符元位 元’錯誤概率越良好(對於錯誤之耐受性強)。 135786.doc -179· 200937872 圖129係表示以圖8之正交調變部27進行4096QAM之情沉 下之4096個符元(對應之信號點)之IQ平面上之配置。 此外,於圖129,C4〇96(i,q)係表示4096QAM之4〇96個符 元中之位於座標(i,q)之位置之符元之符元號碼。以下,位 於座標(i,q)之位置之4096QAM之符元亦稱為第C4〇96(i,q)個 符元。 現在,若使圖128所說明之1024QAM之1024個符元全部 平行移動於IQ平面上之第1象限内,則該平行移動後之 〇 1024QAM之第C1024(i,q)個符元成為4096QAM之第 C4096(i,q) = Cl〇24(i,q)個符元。 進一步若使已平行移動於第1象限内之1024QAM之1024 個符元,對於I軸對稱移動,則該對稱移動後之1024QAM 之第C丨024(i,q)個符元成為4096QAM之第C4096(i,-q)= C1C)24(i,q)+1024個符元。 而且,若使已平行移動於第1象限内之1 024QAM之1024 個符元,對於Q軸對稱移動,則該對稱移動後之1024QAM ® 之第 C1024(i,q)個符元成為 4096QAM 之第 C4096(-i,q)= C1024(i,q)+l〇24x2個符元。 進一步若使已平行移動於第1象限内之1024QAM之1024 個符元,對於原點對稱移動,則該對稱移動後之1024QAM 之第 C!〇24(i,q)個符元成為 4096QAM 之第 C4〇96(_i,-q)= C 1 024(i,q)+l〇24x3個符元。 關於1024QAM(圖128)及4096QAM(圖129)之符元之符元 位元,亦與圖12等所說明之情況相同,存在強勢位元及弱 135786.doc -180- 200937872 勢位元。 圖130至圖133係表示已進行新替換方式之替換處理之情 況及未進行替換處理之情況之BER(Bit Error Rate :位元錯 誤率)之模擬之結果。 亦即,圖130係表示將碼長N為16200、編碼率為2/3、 3/4、3/5、5/6、8/9分別之LDPC碼作為對象,作為調變方 式採用1024QAM之情況下之BER。 圖131係表示將碼長N為64800、編碼率為2/3、3/4、 〇 3/5、5/6、8/9、9/10分別之LDPC碼作為對象,作為調變方 式採用1024QAM之情況下之BER。 圖132係表示將碼長N為16200、編碼率為2/3、3/4、 3/5、5/6、8/9分別之LDPC碼作為對象,作為調變方式採 用4096QAM之情況下之BER。 圖133係表示將碼長N為64800、編碼率為2/3、3/4、 3/5、5/6、8/9、9/10分別之LDPC碼作為對象,作為調變方 式採用4096QAM之情況下之BER。 ❹ 此外,於圖130至圖133,倍數b為1。 而且,於圖130至圖133,橫軸表示Es/N〇(每1符元之信號 電力對雜訊電力比),縱軸表示BER。而且,實線表示已進 行新替換方式之替換處理之情況下之BER,點線表示未進 行替換處理之情況下之BER。 從圖130至圖133,新替換方式之替換處理係比較起未進 行替換處理之情況,其BER提升,因此可知對於錯誤之耐 受性提升。 135786.doc -181 - 200937872 此外,於本實施型態,為了便於說明,於解多 =部32係㈣出自記憶㈣之碼位元作為對象而進行替 臭處理’但替換處理可藉由控制對於記憶體以之 寫入或讀出來進行。 亦即’替換處理可藉由例如控制讀出碼位元之位址(讀 出位址)’以替換後之碼位元之順序進行從記憶體Η 位元之讀出來進行。 ❹ 然而,於圖62至圖127雖說明倍數13為1之情況下之作為 碼位元之替換方式之新替換方式,但倍數1>為丨之情況下之 作為碼位元之替換方式可直接利用於倍數b*2以上之值 (其中,必須為碼長N之約數)之情況下之碼位元之替換。 參考圖134及圖135,來說明關於倍數1)為1之情況下之碼 元之替換直接利用於倍數b為2以上之值之情況下之碼位 元之替換。 圖134係說明倍數b為1之情況下之碼位元之替換之圖。 此外’於圖134(後述之圖135亦相同)為了簡化說明, LDPC碼之碼長N設為例如24位元。而且,調變方式係例如 碼位元之4(=m)位元作為1個符元而映射成4個信號點中之 任一個之QPSK。 碼長N為24位元,倍數b為1,碼位元之4(=m)位元成為1 個符元之情況下,解多工器25之記憶體31(圖16、圖17)係 含有於橫列方向記憶4x l(=mb)位元之4個縱行,於縱行方 向記憶24/(4xl)位元。 現在,若將24位元之LDPC碼之碼位元從開頭表示作 135786.doc -182- 200937872 〜u,C,a,· · .,v,w,x,則該24位元之LDpc碼之碼位元&至χ 係對於記憶體3丨之4個縱行,如圖134A所示於縱行方向依 次寫入。 亦即,圖134A係表示對於記憶體31之4個縱行之“位元 之LDPC碼之寫入之狀態。 分別於記憶體31之4個縱行中之第丨個縱行寫入有碼位元 a,b,C,d’e,f ’於第2個縱行寫入有碼位元g,hijk,卜於第3個 縱行寫入有碼位元m,n,〇,p,q,r ’於第4個縱行寫入有碼位元 S,t,U,V,W,X。 此外,於圖134(於圖135亦同),為了易於理解碼位元從 縱行之讀出順序,於縱行下方圖示有先進行寫入之碼位 元。 若對於記憶體31之24位元之碼位元&至乂之寫入終了,寫 入於該記憶體31之碼位元aix係於橫列方向,以4xl(=mb) 位元單位讀出’並供給至替換部32(圖16、圓17)。 替換部32係進行將從記憶體3丨於橫列方向所讀出之 4><l(=mb)位元之碼位元bi,例如圖134B所示分配給1(=1>)個 符元之符元位元yi之碼位元bi之替換。 亦即’圖134B係表示將4位元之碼位元b〗分配給1個符元 之符元位元yi之替換例。 於圖134B’分別進行下述替換:將讀出自第1個縱行之 碼位元b〇分配給符元位元,將讀出自第2個縱行之碼位元 bi分配給符元位元丫, ’將讀出自第3個縱行之碼位元匕分配 給符元位元ys ’將讀出自第4個縱行之碼位元b3分配給符元 135786.doc -183- 200937872 位元y〇 〇 …碼…符元… 從記憶㈣於橫列方向所讀出之4xl(=mb)位元之碼位元 心九九按照圖测之替換模式替換之結果獲得以圖 134C所示之符元位元y〇,y丨,y2,y3所構成之丨個符元。 亦即,圖134C係表示藉由按照圖U4B之替換模式替 換如圖134A所示而寫入之碼位元所獲得之符元。Further, an LDPC code having a modulation code length N of 64800 or 16200 bits, a coding rate of 2/3 or 8/9, or an LDPC having a code length N of 64,800 bits and an encoding rate of 9/10 is used. In the case of a code, the replacement processing can be performed as follows, for example, in the alternative manner shown in FIG. 64A or the like: assigning the code bit bG to the symbol bit y8 and the code bit b to the symbol bit y 〇, The code bit b2 is assigned to the symbol bit y], the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, and the code bit b5 is assigned to the symbol bit The element y4 assigns the code bit b6 to the symbol bit y6, the code bit b7 to the symbol bit y5, the code bit b8 to the symbol bit y9, and the code bit b9 to the symbol The meta-bit y7. Moreover, the LDPC code with a code length N of 64800 or 16200 bits, a coding rate of 2/3 or 8/9, or a code length N of 64800 bits, 409678.doc -176·200937872 code rate is modified by 4096QAM. In the case of an LDPC code of 9/10, the replacement processing can be performed as follows, for example, in the alternative manner shown in Fig. 97A, etc.: The code bit bG is assigned to the symbol bit y 1 〇, and the code bit b! For the symbol bit y 〇, the code bit b2 is assigned to the symbol bit y!, the code bit b3 is assigned to the symbol bit y2, and the code bit b4 is assigned to the symbol bit y3, and the code is assigned Bit b 5 is assigned to symbol bit y 4, 码 code bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, and code bit b8 is assigned to symbol bit The element y8 assigns the code bit b9 to the symbol bit y7, the code bit b! 〇 to the symbol bit y!!, and the code bit b η to the symbol bit y 9. In the above, the new replacement method will be described with respect to the case where the modulation method is 1024QAM and the case of 4096QAM, and the configuration of the symbol (corresponding signal point) of each modulation method ® will be described below. Fig. 128 is a diagram showing the arrangement on the IQ plane of 1024 symbols (corresponding signal points) in the case where 1024QAM is performed by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 128 shows a method of arranging the arrangement of symbols of 1024QAM inductively from the configuration of the symbol of 256QAM of DVB-T.2. Further, in Fig. 128, (i, q) indicates the coordinates (I coordinate and Q coordinate) on the IQ plane of the symbol. Moreover, C256(i,q) denotes a coordinate (i is also referred to as a symbol number) of a 256-symbol 135786.doc-177-200937872 element of 256QAM which is serially attached to the coordinate (i). , q) The position of the symbol (attached to the symbol) symbol number. Hereinafter, the symbol of 256QAM located at the position of the coordinate (i, q) is also referred to as the Cwdq) symbol. Further, C1024(i, q) is a symbol number indicating a symbol located at a position of a coordinate (i, q) among 1024 symbols of 1024QAM. Hereinafter, the symbol of 1024QAM located at the position of the coordinate (i, q) is also referred to as the C1〇24(i,q) character 7t 0 ❹ Now, if all 256 symbols of 256QAM are moved in parallel on the iq plane In the first quadrant, the C256(i,q) symbols of the 256QAM after the parallel movement become the CiV24(i,q)=C256(i,q) symbols of 1024QAM. Further, if 256 symbols of 25 6QAM in the first quadrant are moved in parallel, for the I-axis symmetric movement, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C of the 1024QAM. 024(i,-q)=C256(i,q)+256 symbols. Moreover, if 256 ® symbols of 256QAM that have been moved in parallel in the first quadrant are moved symmetrically about the Q axis, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C of 1024QAM.丨〇24(-i,q)=C256(i,q)+ 256x2 symbols. Further, if 256 symbols of 25 6QAM have been moved in parallel in the first quadrant, and the symmetric movement of the origin, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C1024 of 1024QAM ( -i, -q) = C256(i, q) + 256x3 symbols. In addition, with respect to the above Xth symbol, the value of X in the binary representation is 135786.doc •178- 200937872 The value of the symbol (signal point to which the symbol is mapped). For example, in the case of C256(i,q)=25, the symbol value of the Cwdq) symbol is 0001 1001 B (B indicates that the previous value is 2 in only), and for example, Ci〇24(i,q) In the case of =823, the symbol value of the 'Ci〇24(i,q) symbols is 1100110111B. Further, for example, the 256th 2th symbol (i, q > 0) of the second quadrant (I < 0, Q > 0) is located at the C256 of 256 symbols τ ο of 256 QAM that has been moved in parallel in the first quadrant. (i, q) symbols, for the position of the q-handle after Ο line-symmetric movement 'The Ci_24(-i,q)=c;25eii,q>+256x2 symbolic value beer The upper 2 bits of the value of Czwdq) are represented by the 2-bit, and the value of 2 of 256x2, that is, the value of 10B is added by the 2-bit. In 1024QAM, the number m of 1 symbol is 10, and the symbol of 1 symbol is represented from the highest bit (yojb· · y6, y7, y8, y9) 〇 for example Ci〇24(i,q In the case of =823, the symbolic value of the 'Ci〇24(i,q) symbols, that is, the 10-bit symbolic element (y〇, yi, y2, y3, y4, y5, y6, Y7, y8, y9^ ^ (1,1,M,1,1,G,1,1,1). Then, as illustrated in Fig. 62 to Fig. 94, respectively, the symbol bit y〇^ It belongs to the symbol element group Gy!, the symbol element y^y3 belongs to the symbol element group Gyz, and the symbol element y^y5 belongs to the symbol element group, and the symbol element ye, y7 It belongs to the symbol bit group Gy4, and the symbol bit y8, y9 belongs to the symbol bit group Gy5. Further, the subscript j belongs to the smaller symbol group of the symbol group. The better the probability (the resistance to the error is). 135786.doc -179· 200937872 Figure 129 shows the 4096 symbols (corresponding signal points) of the 4096QAM with the quadrature modulation unit 27 of Fig. 8 In the IQ plane, the configuration on the IQ plane. In addition, in Figure 129, C4〇96(i,q) represents 4〇96 characters of 4096QAM. The symbol number of the symbol located at the position of the coordinate (i, q). Below, the symbol of 4096QAM located at the position of the coordinate (i, q) is also called the C4〇96(i,q) symbol. Now, if all 1024 symbols of 1024QAM described in FIG. 128 are moved in parallel in the first quadrant on the IQ plane, the C1024(i, q) symbols of the 1024QAM after the parallel movement become 4096QAM. The first C4096(i,q) = Cl〇24(i,q) symbols. Further, if the 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically for the I-axis, the symmetric movement The C 024 (i, q) symbols of the subsequent 1024QAM become the C4096 (i, -q) = C1C) 24 (i, q) + 1024 symbols of 4096QAM. Moreover, if 1024 symbols of 1,024QAM that have been moved in parallel in the first quadrant are moved symmetrically about the Q axis, the C1024(i,q) symbols of the 1024QAM® after the symmetric movement become the first of 4096QAM. C4096(-i,q)= C1024(i,q)+l〇24x2 symbols. Further, if 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically to the origin, the C!〇24(i,q) symbols of the 1024QAM after the symmetric movement become the first of 4096QAM. C4〇96(_i,-q)= C 1 024(i,q)+l〇24x3 symbols. The symbol bits of the symbols of 1024QAM (Fig. 128) and 4096QAM (Fig. 129) are also the same as those described in Fig. 12, and there are strong bits and weak 135786.doc -180-200937872 potential bits. Figs. 130 to 133 show the results of the simulation of the BER (Bit Error Rate) in the case where the replacement processing of the new replacement method has been performed and the case where the replacement processing has not been performed. That is, FIG. 130 shows that an LDPC code having a code length N of 16,200, a coding rate of 2/3, 3/4, 3/5, 5/6, and 8/9 is used as a target, and 1024QAM is used as a modulation method. BER in case. FIG. 131 is a view showing an LDPC code having a code length N of 64,800, a coding rate of 2/3, 3/4, 〇3/5, 5/6, 8/9, and 9/10 as a modulation method. BER in the case of 1024QAM. FIG. 132 is a diagram showing an LDPC code having a code length N of 16,200, a coding rate of 2/3, 3/4, 3/5, 5/6, and 8/9 as a target, and 4096QAM is used as a modulation method. BER. Figure 133 shows an LDPC code with a code length N of 64800 and a coding rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10 as the object, and 4096QAM is used as the modulation method. The BER in the case. ❹ In addition, in FIGS. 130 to 133, the multiple b is 1. Further, in Figs. 130 to 133, the horizontal axis represents Es/N 〇 (signal power to noise power ratio per symbol), and the vertical axis represents BER. Further, the solid line indicates the BER in the case where the replacement processing of the new replacement method has been performed, and the dotted line indicates the BER in the case where the replacement processing is not performed. From Fig. 130 to Fig. 133, the replacement processing of the new alternative is compared with the case where the replacement processing is not performed, and the BER is increased, so that the resistance to errors is improved. 135786.doc -181 - 200937872 In addition, in the present embodiment, for convenience of explanation, the code bit from the memory (4) is used as the object for the odor treatment, but the replacement processing can be controlled by The memory is written or read by it. That is, the 'replacement processing can be performed by, for example, controlling the address of the read code bit (read address)' from the memory bit in the order of the replaced code bit. ❹ However, although FIG. 62 to FIG. 127 illustrate a new alternative as a replacement method of the code bit in the case where the multiple 13 is 1, the multiple of 1 is a direct replacement of the code bit in the case of 丨The replacement of the code bits in the case where the value of the multiple b*2 or more (which must be the approximate number of the code length N) is utilized. Referring to Fig. 134 and Fig. 135, the replacement of the symbols in the case where the multiple 1) is 1 is directly used for the replacement of the code bits in the case where the multiple b is a value of 2 or more. Figure 134 is a diagram for explaining the replacement of the code bits in the case where the multiple b is 1. Further, in Fig. 134 (the same applies to Fig. 135 to be described later), the code length N of the LDPC code is set to, for example, 24 bits for simplification of explanation. Further, the modulation method is, for example, 4 (=m) bits of a code bit as one symbol and mapped to QPSK of any of the four signal points. When the code length N is 24 bits, the multiple b is 1, and the 4 (=m) bits of the code bit become 1 symbol, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) is Four wales containing 4x l (= mb) bits in the horizontal direction are stored, and 24/(4xl) bits are stored in the wales. Now, if the code bit of the 24-bit LDPC code is represented from the beginning as 135786.doc -182- 200937872 ~u, C, a, · · . . , v, w, x, then the 24-bit LDpc code The code bits & to the four wales of the memory 3 , are sequentially written in the wale direction as shown in FIG. 134A. That is, FIG. 134A shows the state of writing the "bit LDPC code" of the four wales of the memory 31. The code is written in the third wales of the four wales of the memory 31, respectively. The bits a, b, C, d'e, f' are written with the code bits g, hijk in the second vertical line, and the code bits m, n, 〇, p are written in the third vertical line. , q, r ' is written in the fourth vertical line with code bits S, t, U, V, W, X. In addition, in Figure 134 (also in Figure 135), in order to easily understand the code bits from the vertical The reading order of the lines is shown below the wales with the code bits first written. If the writing of the 24-bit code bits & to the end of the memory 31 is completed, the memory is written in the memory. The code bit aix of 31 is in the course direction, and is read out in 4x1 (= mb) bit units and supplied to the replacement unit 32 (Fig. 16, circle 17). The replacement unit 32 is performed from the memory 3 The code bit bi of the 4>l (= mb) bit read in the course direction, for example, the code bit element assigned to the symbol bit yi of 1 (=1> symbol) as shown in FIG. 134B Replacement of bi. That is, 'Fig. 134B shows that the 4-bit code bit b is assigned to one symbol. An alternative to the bit yi. The following replacement is performed in FIG. 134B': the code bit b〇 read from the first vertical line is assigned to the symbol bit, and the code bit from the second vertical line is read. Bi is assigned to the symbol bit 丫, 'The code bit 匕 read from the 3rd ordinate is assigned to the symbol ys ′', and the code bit b3 read from the 4th row is assigned to the symbol 135786. Doc -183- 200937872 Bit y〇〇...code...symbol... The result of replacing the 4xl (= mb) bit of the coded bit heart read from the memory (4) in the horizontal direction according to the replacement mode of the graph test One symbol is formed by the symbol bits y 〇, y 丨, y2, y3 shown in Fig. 134C. That is, Fig. 134C shows the replacement of Fig. 134A by replacing the replacement pattern according to Fig. U4B. The symbol obtained by the written code bit.
例如於圖134A,於第!至4縱行之第】下面之列(_:橫 列)所寫入之碼位元a,g,m,s(之排列)係藉由按照圖i 34B之替 換模式替換,以便如圖134C之最下面所示,成為符元位元 s,g,a,m之排列之符元。 而且,例如於圖134A,於第1至第4縱行從下算起第2列 所寫入之碼位元b,h,n,t係藉由按照圖134B之替換模式替 換,以便如圖134C之下算起第2個所示,成為符元位元 t,h,b,n之排列之符元。 圖135係說明直接利用圖134之倍數匕為!之情況下之碼位 元之替換模式之倍數b為2之情況下之碼位元之替換之圖。 此外,於圖135,僅有倍數b非為i而為2之點與圖134之 情況不同。因此,LDPC碼之碼長N為24位元,調變方式係 碼位元之4(=m)位元作為1個符元而映射成4個信號點中之 任一個之pPSK。 碼長N為24位元,倍數b為2,碼位元之4(=m)位元成為j 個符元之情況下,解多工器25之記憶體31(圖16、圖17)係 135786.doc •184· 200937872 含有於橫列方向記憶4x2 (=mb)位元之8個縱行,於縱行方 向記憶24/(4χ2)位元。 24位元之LDPC碼之碼位元&至χ係對於記憶體3丨之8個縱 行’如圖13 5 Α所示於縱行方向依次寫入。 亦即’圖135A係表示對於記憶體31之8個縱行之24位元 之LDPC碼之寫入之狀態。 此外’於圖135A ’為了便於說明,將8個縱行以第1縱 行 '第3縱行、第5縱行、第7縱行、第2縱行、第4縱行、 © 第6縱行、第8縱行之順序圖示。 於圖Π5Α,分別而言,於記憶體31之8個縱行中之第1縱 行寫入碼位元a,b,c,於第2縱行寫入碼位元d,e,f,於第3縱 行寫入碼位元g,h,i,於第4縱行寫入碼位元j k,卜於第5縱 仃寫入碼位元m,n,〇,於第6縱行寫入碼位元p,q,r,於第7 縱行寫入碼位元s,t,u ,於第8縱行寫入碼位元 若對於圯憶體31之24位元之碼位元3至乂之寫入終了,寫 φ 於,°己憶體31之碼位元&至乂係於橫列方向,以4x2(=mb) 也元單位讀出,並供給至替換部32(圖16、圖17) 〇 替換部32係進行將從記憶體31於橫列方向所讀出之 4 2(-mbhi兀之碼位元卜,例如圖ΐ35β所示分配給連續 2( b)個符元之符元位元yi之碼位元bi之替換。 ★亦即,圖135B係表示將8位元之碼位元bi分配給連續2個 符疋之符元位元yi之替換例。 於此\於圖Π5Β,符元位元八至乃係連績之2個符元中 個符元之符元位元,符元位元〜至乃係連績2個符元 135786.doc -185· 200937872 中之第2個符元之符元位元。 於圖135B,直接利用圖134B所示之倍數b為1之情況下 之碼位元之替換模式。 亦即’於圖135B,分別進行下述替換模式之替換:將讀 出自第1縱行之碼位元b〇分配給符元位元yz,將讀出自第3 縱行之碼位元bz分配給符元位元yi,將讀出自第5縱行之碼 位元feu分配給符元位元ys,將讀出自第7縱行之碼位元、分 配給符元位元yG ;該替換模式(圖135B之箭頭之配置模式) © 係與圖134B所示之倍數b為1之情況下之碼位元之替換模式 一致。 而且’於圖135B ’分別進行下述替換模式之替換:將讀 出自第2縱行之碼位元bi分配給符元位元y0,將讀出自第4 縱行之碼位元t>3分配給符元位元ys,將讀出自第6縱行之碼 位元bS分配給符元位元y? ’將讀出自第8縱行之碼位元卜分 配給符元位元y4 ;該替換模式亦與圖134B所示之倍數6為i 之情況下之碼位元之替換模式一致。 ❹ 從記憶體31於橫列方向所讀出之4x2(=mb)位元之碼位元 ^>〇,1>1,52,133,匕4山5,匕6,137按照圖1358之替換模式替換,結果獲 得以圖135C所示之符元位元y(),y1,y2,y3,y4,y5,y6,y7所構成之 連續2個符元。 亦即’圖135C係表示藉由按照圖135B之替換模式,替 換如圖135A所示而寫入之碼位元所獲得之符元。 例如於圖135A,於第1至8縱行之最下面之列所寫入之瑪 位元a,g,m,s,d,j,p,v(之排列)係藉由按照圖135B之替換模式 135786.doc -186- 200937872 替換’以便如圖135C之最下面所示,成為符元位元^爪 之排列之符元及符元位元v,j,d,p之排列之符元。 而且,例如於圖135A ’於第1至8縱行之下算起第2列所 寫入之碼位元b,h,n,t,e,k,q,w係藉由按照圖135B之替換模式 替換’以便如圖135C之下算起第2個所示,成為符元位元 t,h,b,n之排列之符元及符元位元w,k,e,q之排列之符元。 於此’如比較圖134C及圖135C可知,若直接利用倍數b 為1之情況下之替換模式來進行倍數bg2之情況下之碼位 © 元之替換,則可獲得由與倍數b為1之情況同一符元位元 (碼位元)之排列所組成之符元。 因此,直接利用倍數b為1之情況下之替換模式來進行倍 數b為2之情況下之碼位元之替換之情況時,藉由該替換所 造成之對於錯誤之耐受性係與倍數b*〗之情況成為同樣耐 受性。 此外,由同一符元位元之排列所組成之符元可獲得之順 序係於倍數b為1之情況與2之情況可能不同。 接著,如上述,說明直接利用倍數1?為1之情況下之替換 模式之倍數b為2之情況下之碼位元之替換之具體例。 圖136係表示LDPC碼是瑪長叫162〇〇位元編碼率為 2/3之LDPC碼’進—步調變方式為1〇24QAM,倍數之 情況下之碼位元之替換例。 圖136之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數…之點不同之圖64A之碼位元之替換。因此, 圖136之碼位元之替換係按照圖63之分配規則。 135786.doc -187- 200937872 LDPC碼是碼長N為16200位元、編碼率為2/3之LDPC 碼,進一步調變方式為1024QAM、倍數b&2之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(1〇χ2))χ (10x2)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、 17)。 替換部32係以將讀出自記憶體31之1〇χ2卜位元之碼 位元13〇至be,如圖136所示分配給連續之2(=b)個 一 ❹i〇x2(=mb)位元之符元位元〜至y〗9之方式,來:二 l〇x2(=mb)位元之碼位元“至!^。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b2分配給符元位元y 〇, 將碼位元b4分配給符元位元y丨, 將瑪位元t>6分配給符元位元y2, 將碼位元分配給符元位元y3, 〇 將碼位元b 1 〇分配給符元位元y 4, 將碼位元b! 2分配給符元位元y 6, 將碼位元b 14分配給符元位元y 5, 將碼位元b 16分配給符元位元y 9, 將碼位元b〗8分配給符元位元y 7, 將碼位元bi分配給符元位元;^8, 將碼位元b3分配給符元位元y丨〇 ’ 將碼位元bs分配給符元位元y 11, 135786.doc -188- 200937872 將碼位元b7分配給符元位元丫12, 將碼位元b9分配給符元位元713, 將碼位元bu分配給符元位元y14, 將碼位元b丨3分配給符元位元y_i6, 將碼位元b 1 5分配給符元位元y丨5, 將碼位元b〗7分配給符元位元y丨9, 將碼位元b〗9分配給符元位元y丨7, 两進行替換。For example, in Figure 134A, in the first! The code bits a, g, m, s (arranged) written in the following column (_: course) are replaced by the replacement mode according to Fig. 34B, as shown in Fig. 134C. At the bottom, the symbol of the arrangement of the symbol bits s, g, a, m is obtained. Further, for example, in FIG. 134A, the code bits b, h, n, t written in the second column from the bottom of the first to fourth wales are replaced by the replacement mode according to FIG. 134B. Under the 134C, the second symbol is shown, which becomes the symbol of the arrangement of the symbol bits t, h, b, and n. Figure 135 is a diagram illustrating the direct use of the multiple of Figure 134! In the case where the multiple of the replacement mode of the code bit b is 2, the replacement of the code bit is shown. Further, in Fig. 135, the point where only the multiple b is not i and is 2 is different from the case of Fig. 134. Therefore, the code length N of the LDPC code is 24 bits, and the 4 (=m) bits of the modulation mode code bit are mapped as one symbol to the pPSK of any of the four signal points. When the code length N is 24 bits, the multiple b is 2, and the 4 (=m) bits of the code bit become j symbols, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) is 135786.doc •184· 200937872 Contains 8 vertical lines that store 4x2 (=mb) bits in the horizontal direction and 24/(4χ2) bits in the longitudinal direction. The 24-bit LDPC code code bit & χ is the 8 vertical lines of the memory 3 ’ as shown in Fig. 13 5 依次 in the wale direction. That is, Fig. 135A shows the state of writing to the 24-bit LDPC code of the eight wales of the memory 31. In addition, in FIG. 135A', for the sake of convenience, eight vertical lines are referred to as a first vertical line, a third vertical line, a fifth vertical line, a seventh vertical line, a second vertical line, a fourth vertical line, and a sixth vertical line. The order of the line and the eighth line is shown. In FIG. 5, respectively, the first vertical line of the eight vertical lines of the memory 31 is written with the code bits a, b, c, and the second vertical line is written with the code bits d, e, f, Write the code bit g, h, i in the third vertical line, write the code bit jk in the fourth vertical line, and write the code bit m, n, 〇 in the fifth vertical 于 in the sixth vertical line Write code bits p, q, r, write code bits s, t, u in the 7th ordinate, and write the code bits in the 8th ordinate if the code bits for the 24-bit of the memory 31 The writing of the element 3 to 乂 is finished, and the code bit & 乂 is written in the course direction, read in 4x2 (= mb) and is supplied to the replacing unit 32. (Fig. 16 and Fig. 17) The 〇 replacing unit 32 performs 4 2 (-mbhi 码 code bit 卜, which is read from the memory 31 in the course direction, for example, as shown in Fig. 35β, and is assigned to continuous 2 (b). Replacement of the code bit bi of the symbol element yi of the symbol. That is, Fig. 135B shows an alternative example of assigning the code bit bi of the 8-bit to the symbol bit yi of two consecutive symbols. Here, in Figure 5, the symbolic element is the symbolic element in the 2 symbols of the successor, and the symbolic element is ~ The symbolic symbol of the second symbol in the second symbol 135786.doc -185· 200937872. In Fig. 135B, the code bit in the case where the multiple b shown in Fig. 134B is 1 is directly used. Replacement mode. That is, in Fig. 135B, the replacement of the following replacement mode is respectively performed: the code bit b〇 read from the first vertical line is assigned to the symbol bit yz, and the code position from the third vertical line is read. The element bz is assigned to the symbol bit yi, and the code bit feu read from the fifth vertical line is assigned to the symbol bit ys, and the code bit from the seventh vertical line is read and assigned to the symbol bit yG; The replacement mode (the arrangement mode of the arrow in Fig. 135B) is the same as the replacement mode of the code bit in the case where the multiple b is 1 shown in Fig. 134B, and the replacement mode is replaced by the following replacement mode in Fig. 135B. : assigning the code bit bi read from the second vertical line to the symbol bit y0, and assigning the code bit t > 3 read from the fourth vertical line to the symbol bit ys, which will be read from the sixth vertical line The code bit bS is assigned to the symbol bit y? 'The code bit element read from the 8th vertical line is assigned to the symbol bit y4; the replacement mode is also shown in FIG. 134B. The replacement mode of the code bits in the case where the multiple 6 is i is the same. 码 The code bits of the 4x2 (= mb) bits read from the memory 31 in the course direction ^ 〇, 1 > 1, 52 , 133, 匕4山5, 匕6, 137 are replaced by the replacement mode of Fig. 1358, and the result is obtained by the symbol y(), y1, y2, y3, y4, y5, y6, y7 shown in Fig. 135C. Two consecutive symbols are constructed. That is, 'FIG. 135C shows a symbol obtained by replacing the code bit written as shown in FIG. 135A by the replacement mode of FIG. 135B. For example, in FIG. 135A, the positions a, g, m, s, d, j, p, v written in the lowermost column of the first to eighth wales are by the arrangement according to FIG. 135B. Replacement mode 135786.doc -186- 200937872 Replace 'to the symbol shown in the bottom of Figure 135C, the symbol of the arrangement of the symbol bit ^ claw and the symbol of the symbol element v, j, d, p . Moreover, for example, in Fig. 135A, the code bits b, h, n, t, e, k, q, w written in the second column are counted under the first to eighth vertical lines, according to Fig. 135B. The replacement mode is replaced by 'in order to be the second one as shown in Fig. 135C, and the arrangement of the symbols of the symbol bits t, h, b, n and the arrangement of the symbol bits w, k, e, q Fu Yuan. As can be seen from the comparison of FIG. 134C and FIG. 135C, if the replacement of the code bit © when the multiple bg2 is used in the replacement mode in the case where the multiple b is 1, the multiple of b is obtained. A symbol consisting of an arrangement of the same symbol bits (code bits). Therefore, when the replacement of the code bit in the case where the multiple b is 2 is directly used in the case of the substitution mode in the case where the multiple b is 1, the tolerance to the error and the multiple b are caused by the replacement. *〗 The situation is equally tolerant. Further, the order in which the symbols consisting of the same symbol bit arrangement can be obtained is that the case where the multiple b is 1 may be different from the case of 2. Next, as described above, a specific example of replacement of the code bit in the case where the multiple b of the replacement mode in the case where the multiple 1 is 1 is used is directly used will be described. Figure 136 is a diagram showing an alternative example of the LDPC code in which the LDPC code is 162 〇〇 bit code rate 2/3 LDPC code 'in the step modulation mode is 1 〇 24QAM, in the case of a multiple. The replacement of the code bits in the case where the multiple b of Fig. 136 is 2 is directly replaced by the code bit of Fig. 64A in which only the multiples are different. Therefore, the replacement of the code bits of FIG. 136 is in accordance with the allocation rule of FIG. 135786.doc -187- 200937872 LDPC code is an LDPC code with a code length N of 16200 bits and a coding rate of 2/3. In the case of further modulation mode 1024QAM and multiple b&2, in the multiplexer 25, The code bit written in the memory 31 in the wx direction x direction (1.6 〇〇 / (1 〇χ 2)) χ (10 x 2) bits is in the course direction, l〇x2 (= mb) The bit unit is read out and supplied to the replacement unit 32 (Figs. 16, 17). The replacing unit 32 is configured to assign the code bits 13 from the 1⁄2 bit position of the memory 31 to be, as shown in FIG. 136, to 2 consecutive (=b) one ❹i〇x2 (= mb). The bitwise symbol of the bit is ~ to y9, and the code bit of the two l〇x2 (= mb) bits is "to !^. That is, the replacement section 32 respectively sets the code bit b" Assigned to the symbol bit y8, the code bit b2 is assigned to the symbol bit y 〇, the code bit b4 is assigned to the symbol bit y 丨, and the megabyte t>6 is assigned to the symbol y2 , the code bit is assigned to the symbol bit y3, the code bit b 1 〇 is assigned to the symbol bit y 4 , the code bit b b 2 is assigned to the symbol bit y 6 , and the code bit is assigned b 14 is assigned to the symbol bit y 5 , the code bit b 16 is assigned to the symbol bit y 9, the code bit b 8 is assigned to the symbol bit y 7, and the code bit bi is assigned to the symbol Meta-bit; ^8, assigning code bit b3 to symbol bit y丨〇' assigning code bit bs to symbol bit y 11, 135786.doc -188- 200937872 assigning code bit b7 to The symbol bit 丫12 assigns the code bit b9 to the symbol bit 713, and assigns the code bit bu to the symbol y14. The code bit b丨3 is assigned to the symbol bit y_i6, the code bit b 1 5 is assigned to the symbol bit y丨5, and the code bit b 7 is assigned to the symbol bit y丨9, The code bit b 9 is assigned to the symbol bit y 丨 7 and the two are replaced.
❹ 此外,於圖 136,碼位元b〇,b2,b4,b6,b8,bl〇,bi2,bi4,bi6,bi8 之替換模式及碼位元b丨,1)3,1>5,137,1)9,1)丨丨,1313,1)15,1)丨7,15丨9之替換 模式兩者均與圖64A之碼位元bo至bp之替換模式—致。 圖137係表示LDPC碼是碼長1^為648〇〇位元、編碼率為 2/3之LDPC碼’進一步調變方式為1〇24(^八河,倍數^^為]之 情況下之碼位元之替換例。 圖137之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖67A之碼位元之替換。因此, 圖137之碼位元之替換係按照圖“之分配規則。 LDPC瑪是碼長叫6侧位元、編碼率為2/3之[則 瑪,進-步調變方式為1024QAM、倍數⑷之情況下於 解多H25於縱行方向χ橫列方向為(6彻小 (1〇Χ2)位元之記憶體31寫入之碼位元係於橫列方向,以 1〇X2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出 自記憶體31之10><2(=11113)位元之碼 135786.doc 200937872 位元13〇至b19,如圖137所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元y〇至yi9之方式,來替換 1 〇x2(=mb)位元之碼位元bG至b19。 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y 1, 將碼位元b6分配給符元位元y2, ❹❹ In addition, in FIG. 136, the replacement pattern of the code bits b〇, b2, b4, b6, b8, bl〇, bi2, bi4, bi6, bi8 and the code bit b丨, 1) 3, 1 > 5, 137 The replacement modes of 1) 9, 1) 丨丨, 1313, 1) 15, 1) 丨 7, 15 丨 9 are both identical to the replacement mode of the code bits bo to bp of Fig. 64A. Figure 137 is a diagram showing that the LDPC code is an LDPC code having a code length of 1^ of 648 bits and a coding rate of 2/3. Further modulation is 1〇24 (^八河, multiple ^^ is] An alternative to the code bit. The replacement of the code bit in the case where the multiple b of Fig. 137 is 2 is directly replaced by the code bit of Fig. 67A in which only the multiple b is 1; therefore, Fig. 137 The replacement of the code bit is in accordance with the distribution rule of the figure. LDPC is the code length of 6 side bits, the coding rate is 2/3 [Zema, the step-step modulation mode is 1024QAM, multiple (4)) Multi-H25 in the wale direction, the direction of the horizontal direction is (6-small (1〇Χ2)-bit memory 31 written by the code bit in the course direction, read in 1〇X2(=mb) bit units The replacement unit 32 is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to read the code 135786.doc 200937872 from the 10><2 (=11113) bits of the memory 31 to B19, as shown in FIG. 137, is assigned to the manner of the symbol bits y〇 to yi9 of the consecutive 2 (=b) symbols of l〇x2 (= mb) bits, replacing 1 〇 x2 (= mb) The code bits bG to b19 of the bit. That is, the replacement unit 32 is respectively The code bit bG is assigned to the symbol bit y8, the code bit b2 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, and the code bit b6 is assigned to the symbol Bit y2, ❹
將碼位元b8分配給符元位元y3, 將碼位元b! 〇分配給符元位元y 4, 將碼位元b 12分配給符元位元y 6, 將碼位元b 14分配給符元位元y 5, 將碼位元b! 6分配給符元位元y 9, 將碼位元b! 8分配給符元位元y 7, 將碼位元b!分配給符元位元y 18, 將碼位元b3分配給符元位元y 1 〇, 將碼位元b5分配給符元位元y 11, 將碼位元b7分配給符元位元y 12, 將碼位元b9分配給符元位元y 13, 將碼位元bu分配給符元位元y 14, 將碼位元b13分配給符元位元y!6, 將碼位元b! 5分配給符元位元y 15, 將碼位元b】7分配給符元位元y 19, 將碼位元b 19分配給符元位元y 17, 135786.doc -190- 200937872 而進行替換。 #t!Iir'^bl,b3,b5^ 模式兩者均與圖67A之碼位认至%之替換模式一致。 圖m係表示LDPC碼是碼長料162〇〇位元編碼率為 3M之LDPC碼,進一步調變方式為1〇24qam,倍數_之 情況下之碼位元之替換例。 ❹The code bit b8 is assigned to the symbol bit y3, the code bit b! 〇 is assigned to the symbol bit y 4 , and the code bit b 12 is assigned to the symbol bit y 6, and the code bit b 14 Assigned to the symbol bit y 5, the code bit b! 6 is assigned to the symbol y 9, the code bit b! 8 is assigned to the symbol y 7, and the code bit b! is assigned to the symbol Meta-bit y 18, assigning code bit b3 to symbol bit y 1 〇, assigning code bit b5 to symbol bit y 11, assigning code bit b7 to symbol bit y 12, The code bit b9 is assigned to the symbol bit y 13, the code bit bu is assigned to the symbol bit y 14, the code bit b13 is assigned to the symbol bit y!6, and the code bit b! 5 is assigned. The symbol bit y 15, the code bit b] is assigned to the symbol y 19, and the code bit b 19 is assigned to the symbol y 17, 135786.doc -190 - 200937872 for replacement. Both the #t!Iir'^bl, b3, b5^ modes are consistent with the replacement pattern of the code bits recognized to % in Fig. 67A. Figure m shows an LDPC code which is an LDPC code with a code length of 162 bits and a bit rate of 3M, and a further modulation method of 1 〇 24qam, a multiple of _. ❹
圖138之倍數4 2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖70A之碼位元之替換。因此, 圖138之碼位元之替換係按照圖69之分配規則。 LDPC碼疋碼長N為16200位元、編碼率為3/4之ldpC 碼進步調變方式為1024QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(162〇〇/(1〇χ2))χ (10 X 2)位元之記憶體31寫入之碼位元係於橫列方向,以 10x2 (=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31之i〇X2(=mb)位元之碼 位元b〇至be ’如圖138所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元y。至y19之方式,來替換 10x2(=mb)位元之碼位元bG至b19。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y 6, 將碼位元b〗分配給符元位元y4, 將碼位元分配給符元位元ys, 135786.doc -191 - 200937872 將碼位元b6分配給符元位元y5 ’ ❹ 將碼位元b 8分配給符元位元y 〇 ’ 將碼位元131()分配給符元位元y2 ’ 將碼位元b12分配給符元位元yi ’ 將碼位元b14分配給符元位元y3 ’ 將碼位元b 16分配給符元位元y 9, 將碼位元b18分配給符元位元y7 ’ 將碼位元b!分配給符元位元yl6, 將碼位元b3分配給符元位元y14, 將碼位元b5分配給符元位元又18 ’ 將碼位元b7分配給符元位元y15, 將碼位元b9分配給符元位元y1〇, 將碼位元b ! 1分配給符元位元y 5 2, 將瑪位元b!3分配給符元位元y 1 ,, 將碼位元1^5分配給符元位元丫13, 將碼位元b!7分配給符元位元719, 將碼位元1^9分配給符元位元717, 而進行替換。 此外,於圖138 ^^^D〇,b2,b4,b6,b8,bl〇b , 之替換模式及瑪位元 bl,b3,b5,b7,b9,bii,bi3,bi5’b2,Abl6,bl8 模式兩者均與圖70A之碼位元%至%之替換:’式7二之替換 圖139係表示LDPC碼是碼長N為“_位I—:瑪率為 3/4之LDPC* ’進一步調變方式為i〇24qam,倍數匕為之之 情況下之碼位元之替換例。 135786.doc -192- 200937872 圖139之倍數b為2之情況下之瑪位元之替換係直接利用 僅有倍數b為1之點不同之圖73A之碼位元之替換。因此, 圖139之碼位元之替換係按照圖72之分配規則。 LDPC碼疋碼長n為64800位元、編碼率為3/4之LDpc 碼進步調變方式為1024QAM、倍數b為2之情況下,於 解多工器25,於縱行方向x橫列方向為(64800/(10χ2))χ (10x2)位元之記憶體31寫入之碼位元係於橫列方向以 l〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 ❹ 17)。 替換部32係以將讀出自記憶體3121〇x2(=mb)位元之碼 位元1)()至1)19,如圖139所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元yQ至^之方式,來替換 l〇x2(=mb)位元之碼位元〜至!^。 亦即’替換部32係分別 將碼位元bG分配給符元位元y6, 將碼位元b2分配給符元位元y4, 將碼位元b4分配給符元位元y8, 將碼位元136分配給符元位元y5, 將碼位元b8分配給符元位元y〇, 將碼位元b1()分配給符元位元y2, 將碼位元13〗2分配給符元位元y!, 將碼位元b14分配給符元位元y3, 將碼位元b16分配給符元位元y9 ’ 將碼位元b18分配給符元位元y7, 135786.doc •193- 200937872 將碼位元b 1分配給符元位元y】6, 將碼位元b〗分配給符元位元y丨4, 將碼位元b5分配給符元位元y丨8, 將碼位元b7分配給符元位元y丨5, 將碼位元b9分配給符元位元y1〇, 將碼位元b 1丨分配給符元位元y丨2, 將碼位元b 1 3分配給符元位元y丨1, 將碼位元b 1 5分配給符元位元y丨3, © 將碼位元bp分配給符元位元丫19, 將碼位元b 1 9分配給符元位元y! 7, 而進行替換。 此外’於圖 139,碼位元 b〇,b2,b4,b6,b8,b1(),b12,b14,b16,b18 之替換模式及碼位元 1)1,1)3,1>5,137,59,1)11,1)13,1315,1)〗7,1)19之替換 模式兩者均與圖73 A之碼位元bG至bp之替換模式一致。 圖140係表示LDPC碼是碼長N為16200位元、編蜗率為 4/5之LDPC碼,進一步調變方式為1〇24QAM,倍數b為2之 ® 情況下之碼位元之替換例。 圖140之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖76A之碼位元之替換。因此, 圖140之碼位元之替換係按照圖75之分配規則。 LDPC碼是碼長N為16200位元、編碼率為4/5之LDpc 碼,進一步調變方式為1024QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(162〇〇/(1〇χ2))χ (10x2)位元之記憶體31寫入之碼位元係於橫列方向以 135786.doc -194- 200937872 l〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31之i〇x2(=mb)位元之碼 位元bG至b!9,如圖140所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元至^之方式,來替換 l〇x2(=mb)位元之碼位元心至^^。 亦即,替換部32係分別 將媽位元bQ分配給符元位元y6,The replacement of the code bits in the case of the multiple of 4 in Fig. 138 is directly used. The replacement of the code bits of Fig. 70A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 138 is in accordance with the allocation rule of FIG. The LDPC code code length N is 16200 bits, and the coding rate is 3/4. The ldpC code is adjusted to 1024QAM and the multiple b is 2. In the case of the multiplexer 25, the direction of the X direction is in the direction of the X direction. The code bits written for the memory 31 of (162 〇〇 / (1 〇χ 2)) χ (10 X 2) bits are in the course direction, read out in units of 10x2 (= mb) bits, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to be ' read from the i〇X2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The symbol y of the x2 (= mb) bit. In the manner of y19, the code bits bG to b19 of 10x2 (= mb) bits are replaced. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 6, respectively, assigns the code bit b to the symbol bit y4, and assigns the code bit to the symbol bit ys, 135786. .doc -191 - 200937872 Assigning code bit b6 to symbol bit y5 ' 分配 Assigning code bit b 8 to symbol bit y 〇 ' Assigning code bit 131 () to symbol bit y2 ' Assigning code bit b12 to symbol bit yi ' assigning code bit b14 to symbol bit y3 ' assigning code bit b 16 to symbol bit y 9, assigning code bit b18 to symbol Bit y7' assigns code bit b! to symbol bit yl6, code bit b3 to symbol bit y14, code bit b5 to symbol bit 18' and code bit b7 Assigned to the symbol bit y15, the code bit b9 is assigned to the symbol bit y1 〇, the code bit b ! 1 is assigned to the symbol bit y 5 2 , and the megabyte b! 3 is assigned to the symbol Bit y 1 ,, assign code bit 1^5 to symbol bit 丫13, assign code bit b!7 to symbol bit 719, and assign code bit 1^9 to symbol bit 717, and replace it. In addition, in Figure 138 ^^^D〇, b2, b4, b6, b8, bl〇b, the replacement mode and the mbit bl, b3, b5, b7, b9, bii, bi3, bi5'b2, Abl6, The bl8 mode is replaced with the code bit % to % of FIG. 70A: 'The replacement of Equation 7 II 139 indicates that the LDPC code is LDPC* whose code length N is "_bit I-: Markov rate is 3/4" 'The further modulation is i〇24qam, and the substitution of the code bit in the case of multiple 。. 135786.doc -192- 200937872 The substitution of the mega-bit in the case of the multiple b of Figure 139 is directly The replacement of the code bits of Fig. 73A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 139 is in accordance with the allocation rule of Fig. 72. The LDPC code length n is 64800 bits, coding When the LDpc code rate of 3/4 is 1024QAM and the multiple b is 2, in the multiplexer 25, the direction of the x direction in the wale direction is (64800/(10χ2)) χ (10x2). The code bits written by the memory 31 of the bit are read in units of l〇x2 (= mb) bits in the course direction and supplied to the replacement unit 32 (Fig. 16, Fig. 17). To read the code from the memory 3121 〇 x 2 (= mb) bits Bits 1)() to 1)19, as shown in FIG. 139, are assigned to the symbolic bits yQ to ^ of the consecutive 2 (=b) symbols of l〇x2 (= mb) bits. Replace the code bits of l〇x2 (= mb) bits ~ to !^. That is, the 'replacement unit 32 assigns the code bit bG to the symbol bit y6, respectively, and assigns the code bit b2 to the symbol bit. Element y4, code bit b4 is assigned to symbol bit y8, code bit 136 is assigned to symbol bit y5, and code bit b8 is assigned to symbol bit y 〇, code bit b1() Assigned to the symbol bit y2, the code bit 13>2 is assigned to the symbol bit y!, the code bit b14 is assigned to the symbol bit y3, and the code bit b16 is assigned to the symbol bit y9 ' The code bit b18 is assigned to the symbol bit y7, 135786.doc • 193- 200937872 The code bit b 1 is assigned to the symbol bit y] 6, and the code bit b is assigned to the symbol y 丨4. Assign code bit b5 to symbol bit y丨8, assign code bit b7 to symbol bit y丨5, assign code bit b9 to symbol bit y1〇, and code bit b 1丨 is assigned to the symbol bit y丨2, the code bit b 1 3 is assigned to the symbol bit y丨1, and the code bit b 1 5 is assigned to The meta-bit y丨3, © assigns the code bit bp to the symbol bit 丫19, and assigns the code bit b 1 9 to the symbol bit y! 7, and replaces it. Further, in Figure 139, the code Replacement patterns and code bits of bits b〇, b2, b4, b6, b8, b1(), b12, b14, b16, b18 1)1,1)3,1>5,137,59,1)11 The replacement mode of 1) 13, 1315, 1), 7, 1) 19 is identical to the replacement mode of the code bits bG to bp of FIG. 73A. Figure 140 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a codec ratio of 4/5, and a further modulation method is 1〇24QAM, and the multiple b is 2; . The replacement of the code bit in the case where the multiple b of Fig. 140 is 2 is directly replaced by the code bit of Fig. 76A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 140 is in accordance with the distribution rule of FIG. The LDPC code is an LDpc code with a code length N of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the walody direction. The memory bit written by the memory 31 in the direction of (162 〇〇 / (1 〇χ 2)) χ (10x2) bits is in the horizontal direction with 135786.doc -194 - 200937872 l〇x2 (= mb) bits The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is configured to allocate the code bits bG to b! 9 read from the i〇x2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 〇x2 (= mb) bit symbol bit to ^ way, to replace the l〇x2 (= mb) bit of the code bit heart to ^ ^. That is, the replacing unit 32 assigns the mom bit bQ to the symbol bit y6, respectively.
將碼位元b2分配給符元位元y 4, 將瑪位元b4分配給符元位元y8, 將碼位元b6分配給符元位元y5, 將碼位元b8分配給符元位元y〇, 將碼位元bio分配給符元位元y2, 將碼位元bi2分配給符元位元y!, 將碼位元b14分配給符元位元y3, 將碼位元bi6分配給符元位元y9, 將碼位元b18分配給符元位元y7, 將碼位元b 1分配給符元位元y , 6, 將碼位元b〕分配給符元位元y丨4, 將碼位元b〗分配給符元位元y18, 將碼位元b7分配給符元位元y! 5, 將瑪位元b9分配給符元位元yi〇, 將瑪位元bii分配給符元位元丫12, 將碼位元b!3分配給符元位元yn, 135786.doc -195- 200937872 將碼位元b15分配給符元位元丫13, 將碼位元b 1 7分配給符元位元y丨9, 將碼位元b19分配給符元位元y17, 而進行替換。 此外,於圖 140,瑪位元 b〇,b2,b4,b6,b8,bi〇,bi2bi4,bl6bi8 之替換模式及碼位元 bl,b3,b5,b7,b9,bn,bi3,bi5,bi7X_ 模式兩者均與圖76A之碼位元b0至%之替換模式一致。 圖141係表示LDPC碼是碼長N為64800位元、維踩老么 ❹-之咖碼,進-步調變方式為贿QAM,倍數= 情況下之碼位元之替換例。 圖141之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖79A之碼位元之替換。因此, 圖141之碼位元之替換係按照圖78之分配規則。 LDPC碼是碼長N為 64800位元、編碼率為4/52LDpc 碼,進一步調變方式為1024QAM、倍數bg2之情況下於 解多工器25,於縱行方向x橫列方向為(64800/(10x2))x (10X2)位元之記憶體31寫入之碼位元係於橫列方向,以 i〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) 〇 替換部32係以將讀出自記憶體31之l〇x2(=mb)位元之碼 位元^至、9,如圖141所示分配給連續之2(=1?)個符元之 l〇x2(=mb)位元之符元位元yQ至μ之方式,來替換 10x2(=mb)位元之碼位元%至\9。 亦即,替換部3 2係分別 135786.doc •196· 200937872 將碼位元bG分配給符元位元y6, 將碼位元b2分配給符元位元y4, 將碼位元b4分配給符元位元y8, 將碼位元b6分配給符元位元y5, 將碼位元b8分配給符元位元y〇, 將碼位元b! 〇分配給符元位元y 2, 將碼位元b! 2分配給符元位元y!, 將碼位元b】4分配給符元位元y 3, © 將碼位元b16分配給符元位元y9, 將碼位元b i 8分配給符元位元y 7, 將碼位元b!分配給符元位元y 16, 將碼位元b3分配給符元位元y 14, 將碼位元b5分配給符元位元y 18, 將碼位元b7分配給符元位元y 15, 將碼位元b9分配給符元位元y 1〇, 將碼位元b丨〗分配給符元位元y 12, ❹ 將碼位元b13分配給符元位元yn, 將碼位元b ! 5分配給符元位元y 1 3, 將碼位元b丨7分配給符元位元y 19, 將碼位元b! 9分配給符元位元y 17, 而進行替換。 此外,於圖 141,碼位元 之替換模式及碼位元之替換 模式兩者均與圖79 A之碼位元b〇至b9之替換模式一致。 135786.doc -197- 200937872 圖142係表示LDPC碼是碼長以162〇〇位元編碼率為 5/6之LDPC碼’進-步調變方式為職qam,倍數^ 2之 情況下之碼位元之替換例。 142之倍數…之情況下之碼位元之替換係直接㈣ 僅有倍數b為1之點不同之圖82A之碼位元之替換。因此, 圖142之碼位元之替換係按照圖8丨之分配規則。The code bit b2 is assigned to the symbol bit y 4 , the megabyte b4 is assigned to the symbol y8 , the code bit b6 is assigned to the symbol y5 , and the code bit b8 is assigned to the symbol bit . Element y〇, assigning the code bit bio to the symbol bit y2, assigning the code bit bi2 to the symbol bit y!, assigning the code bit b14 to the symbol bit y3, and allocating the code bit bi6 For the symbol bit y9, the code bit b18 is assigned to the symbol bit y7, the code bit b1 is assigned to the symbol bit y, and the code bit b] is assigned to the symbol bit y. 4, the code bit b is assigned to the symbol bit y18, the code bit b7 is assigned to the symbol bit y! 5, the mate b9 is assigned to the symbol bit yi 〇, the m-bit bii Assigned to the symbol bit 丫12, the code bit b!3 is assigned to the symbol yn, 135786.doc -195- 200937872 assigns the code bit b15 to the symbol 丫13, the code bit b 1 7 is assigned to the symbol bit y丨9, and the code bit b19 is assigned to the symbol bit y17 for replacement. In addition, in FIG. 140, the replacement pattern of the megabytes b〇, b2, b4, b6, b8, bi〇, bi2bi4, bl6bi8 and the code bits bl, b3, b5, b7, b9, bn, bi3, bi5, bi7X_ Both modes are identical to the replacement pattern of the code bits b0 to % of Fig. 76A. Figure 141 is a diagram showing an alternative example of the LDPC code in which the code length N is 64,800 bits, the code is stepped on the old 幺-之, the step-by-step modulation method is bribe QAM, and the multiple is =. The replacement of the code bit in the case where the multiple b of Fig. 141 is 2 is directly replaced by the code bit of Fig. 79A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 141 is in accordance with the allocation rule of FIG. The LDPC code has a code length N of 64,800 bits and a coding rate of 4/52 LDpc code. The further modulation mode is 1024QAM and the multiple bg2 is used in the demultiplexer 25, and the direction of the x direction in the wale direction is (64800/). The (10x2))x (10X2) bit memory 31 is written in the horizontal direction, read out in units of i〇x2 (= mb) bits, and supplied to the replacement unit 32 (FIG. 16, Fig. 17) The 〇 replacing unit 32 is configured to allocate the code bits ^ to 9, read from the l 〇 x 2 (= mb) bits of the memory 31, as shown in Fig. 141 to consecutive 2 (=1?) Replace the symbol bits % to \9 of 10x2 (= mb) bits by the symbol yQ to μ of the l〇x2 (= mb) bit of the symbol. That is, the replacing unit 3 2 assigns the code bit bG to the symbol bit y6, assigns the code bit b2 to the symbol bit y4, and assigns the code bit b4 to the symbol, respectively, 135786.doc •196·200937872 The meta-bit y8 assigns the code bit b6 to the symbol bit y5, the code bit b8 to the symbol bit y, and the code bit b! 〇 to the symbol y 2, the code The bit b! 2 is assigned to the symbol bit y!, the code bit b] is assigned to the symbol bit y 3, © the code bit b16 is assigned to the symbol bit y9, and the code bit bi 8 Assigned to symbol bit y 7, assign code bit b! to symbol bit y 16, assign code bit b3 to symbol y 14, and assign code bit b5 to symbol y 18, assigning the code bit b7 to the symbol bit y 15, assigning the code bit b9 to the symbol bit y 1 〇, and assigning the code bit b 丨 to the symbol bit y 12, ❹ Bit b13 is assigned to symbol bit yn, code bit b! 5 is assigned to symbol bit y 1 3, and code bit b 丨 7 is assigned to symbol bit y 19, and code bit b! 9 is assigned to the symbol bit y 17, and is replaced. Further, in Fig. 141, both the replacement mode of the code bit and the replacement mode of the code bit are identical to the replacement mode of the code bits b 到 b9 of Fig. 79A. 135786.doc -197- 200937872 Figure 142 shows that the LDPC code is an LDPC code with a code length of 162 bits and a coding rate of 5/6. The code position in the case of the step-by-step modulation mode is qam, and the multiple is ^2. A replacement for the yuan. In the case of a multiple of 142, the replacement of the code bits is directly (4). The replacement of the code bits of Fig. 82A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 142 is in accordance with the allocation rule of FIG.
G LDPC碼是碼長N為16200位元、編碼率為5/6之LDpc 崎進一步調變方式為1024QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(162〇〇/(1〇χ2))χ (10 X 2)位元之§己憶體3 1寫入之碼位元係於橫列方向,以 l〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) 〇 替換部32係以將讀出自記憶體31之ioupmb)位元之碼 位元13〇至be,如圖142所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元yG至y”之方式,來替換 10x2(=mb)位元之碼位元^至b19。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y6, 將碼位元b〗分配給符元位元y4, 將碼位元b4分配給符元位元y8, 將碼位元b6分配給符元位元y5, 將碼位元bg分配給符元位元y〇, 將碼位元b1G分配給符元位元y2, 將碼位元b〗2分配給符元位元y!, 135786.doc -198- 200937872 將碼位元b14分配給符元位元y3, 將碼位元b16分配給符元位元y9, 將碼位元b18分配給符元位元y7, 將碼位元b〗分配給符元位元y16, 將碼位元b3分配給符元位元y14, 將碼位元b5分配給符元位元y丨8, 將碼位元b7分配給符元位元715, 將碼位元b9分配給符元位元710, 〇 將碼位元b"分配給符元位元712, 將碼位元b 1 3分配給符元位元y丨J, 將碼位元b15分配給符元位元yn, 將碼位元b17分配給符元位元3^19, 將碼位元b!9分配給符元位元y17 , 而進行替換。 此外,於圖 142,碼位元 b〇,b2,b4,b6,b8,bi〇,bu 之替換模式及碼位元 b 丨,b3,b5,b7,b9,bn,b13>babh14’16’" ❹模式兩者均與圖82A之碼位元bjb9之替換模式二:,替換 圖143係表示LDPC碼是碼長6侧位元、編碼㈣ 5/6之LDPC瑪,進一步調變方式為1〇24qam,倍數b為2之 情況下之碼位元之替換例。 圖143之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數13為1之點不同之圖85A之碼位元之替換。因此’ 圖143之碼位元之替換係按照圖料之分配規則。 LDPC碼是碼長648〇〇位元編碼率為5/6之LDpc 135786.doc •199· 200937872 碼’進一步調變方式為1024QAM、倍數b為2之情況下, 解多工器25,於縱行方向X橫列方向為(648〇〇/(1〇>^^ (1 〇 2)位元之s己憶體31寫入之碼位元係於橫列方向,以 10x2(-mb)位元單位讀出,並供給至替換部32(圖、圖 17) 〇 ❹The G LDPC code is an LDpc with a code length N of 16200 bits and a coding rate of 5/6. The further modulation mode is 1024QAM and the multiple b is 2. In the case of the multiplexer 25, the X direction in the wale direction The direction is (162 〇〇 / (1 〇χ 2)) χ (10 X 2) bits § 体 体 3 1 written code bits are in the horizontal direction, with l 〇 x 2 (= mb) bits The unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to assign the code bits 13 to be from the ioupmb) bits of the memory 31 to be, as shown in Fig. 142. Replace the code bits ^ to b19 of the 10x2 (= mb) bits by the continuous 2 (= b) symbols of the l〇x2 (= mb) bits of the symbol yG to y". That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, assigns the code bit b to the symbol bit y4, and assigns the code bit b4 to the symbol bit y8, and sets the code. Bit b6 is assigned to symbol bit y5, code bit bg is assigned to symbol bit y〇, code bit b1G is assigned to symbol bit y2, and code bit b is assigned to symbol bit Yuan y!, 135786.doc -198- 200937872 assigns the code bit b14 to the symbol bit y3, and divides the code bit b16 For the symbol bit y9, the code bit b18 is assigned to the symbol bit y7, the code bit b is assigned to the symbol bit y16, and the code bit b3 is assigned to the symbol bit y14, and the code bit is The element b5 is assigned to the symbol bit y丨8, the code bit b7 is assigned to the symbol bit 715, the code bit b9 is assigned to the symbol bit 710, and the code bit b" is assigned to the symbol bit. Element 712, assigning code bit b 1 3 to symbol bit y丨J, assigning code bit b15 to symbol bit yn, and assigning bit bit b17 to symbol bit 3^19, The bit b!9 is assigned to the symbol bit y17 and is replaced. In addition, in FIG. 142, the replacement pattern of the code bits b〇, b2, b4, b6, b8, bi〇, bu and the code bit b 丨, b3, b5, b7, b9, bn, b13>babh14'16'" ❹ mode are both replaced with the replacement mode 2 of the code bit bjb9 of Fig. 82A: the replacement figure 143 indicates that the LDPC code is the code length 6 side Bit, code (4) 5/6 LDPC Ma, further modulation method is 1〇24qam, and the multiple of b is 2. The code bit in the case where the multiple b is 2 The replacement is directly utilized with only a multiple of 13 The point is different from the replacement of the code bits in Fig. 85A. Therefore, the replacement of the code bits in Fig. 143 is in accordance with the distribution rule of the picture. The LDPC code is LDpc 135786 with a code length of 648 bits and a coding rate of 5/6. Doc •199· 200937872 Code 'When the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is solved, and the direction of the X direction in the wale direction is (648〇〇/(1〇>^^ ( 1 〇 2) The bit code written by the suffix 31 of the bit is in the course direction, read out in units of 10x2 (-mb) bits, and supplied to the replacement unit 32 (Fig. 17, Fig. 17)
替換部32係以將讀出自記憶體3121〇x2(=mb)位元之碼 位元1^至be,如圖143所示分配給連續之2(=b)個符元之 l〇x2(=mb)位元之符元位元y{)至y]9之方式,來替換 10x2(=mb)位元之碼位元bG至b丨9。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y6, 將碼位元b〗分配給符元位元y4, 將碼位元b4分配給符元位元y8, 將碼位元b6分配給符元位元y5, 將碼位元b8分配給符元位元y〇, 將碼位元bi〇分配給符元位元y2, 將瑪位元b 12分配給符元位元y 1, 將碼位元b14分配給符元位元y3, 將碼位元bi6分配給符元位元y9, 將碼位元b 18分配給符元位元y 7, 將碼位元b 1分配給符元位元y 16 ’ 將碼位元分配給符元位元yi4, 將碼位元b5分配給符元位元yi8 ’ 將碼位元b7分配給符元位元yi5 ’ 135786.doc -200- 200937872 將碼位元b9分配給符元位元y ι〇, 將碼位元bh!分配給符元位元y〗2, 將碼位元b! 3分配給符元位元y! ι, 將碼位元b15分配給符元位元丫13, 將碼位元bi7分配給符元位元yi9, 將碼位元b 19分配給符元位元y 17, 而進行替換。 此外,於圖 i43,碼位元 b0,b2,b4,b6,b8,bl〇,bi2,bi4,b〗6,bi8 © 之替換模式及碼位元 bl,b3,b55,b17,b19之替換 模式兩者均與圖85A之碼位元bo至b9之替換模式一致。 圖144係表示LDPC碼是碼長N為16200位元、編碼率為 8/9之LDPC碼,進一步調變方式為1〇24qAm ,倍數b為2之 情況下之碼位元之替換例。 圖144之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為ι之點不同之圖88A之碼位元之替換。因此, ❿ 圖M4之碼位元之替換係按照圖87之分配規則。 LDPC碼是碼長>^為162〇〇位元、編碼率為8/9之[则 碼,進一步調變方式為1024QAM、倍數5為2之情況下於 解多工器25,於縱行方向x橫列方向為(16200/(10χ2))χ (i〇x2)位元之記憶體31寫入之碼位元係於橫列方向以 (mb)位元單位讀出,並供給至替換部32(圖16、圓 17)。 替換部32係以將讀出自記憶體31之lGx2(=mb)位元之碼 元%至bl9 ’如圖〗44所示分配給連續之2(=b)個符元之 135786.doc 200937872 l〇x2(=mb)位元之符元位元y〇至yi9之方式,來替換 1 〇x2(=mb)位元之碼位元b〇至b!9。 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y 1, 將碼位元b6分配給符元位元y2, 將碼位元b8分配給符元位元y3,The replacing unit 32 is configured to allocate the code bits 1 to be from the memory 3121 〇 x 2 (= mb) bits to be as shown in FIG. 143 to the consecutive 2 (= b) symbols l 〇 x 2 ( =mb) The way of the bit y{) to y]9 of the bit replaces the code bits bG to b丨9 of the 10x2 (= mb) bit. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, assigns the code bit b to the symbol bit y4, and assigns the code bit b4 to the symbol bit y8, The code bit b6 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y, the code bit bi〇 is assigned to the symbol bit y2, and the mbit b 12 is assigned to the symbol Bit y 1, assign code bit b14 to symbol bit y3, assign code bit bi6 to symbol bit y9, assign code bit b 18 to symbol bit y 7, and use code bit b 1 is assigned to the symbol bit y 16 ' to assign the code bit to the symbol bit yi4, the code bit b5 is assigned to the symbol bit yi8 ' to assign the code bit b7 to the symbol bit yi5 ' 135786 .doc -200- 200937872 assign code bit b9 to symbol bit y ι〇, assign code bit bh! to symbol bit y 〗 2, assign code bit b! 3 to symbol bit y! ι, assign code bit b15 to symbol bit 丫13, assign code bit bi7 to symbol bit yi9, and assign code bit b19 to symbol y17 for replacement. In addition, in Figure i43, the replacement of the code bits b0, b2, b4, b6, b8, bl〇, bi2, bi4, b, 6, bi8 © and the replacement of the code bits bl, b3, b55, b17, b19 Both modes are identical to the replacement mode of the code bits bo to b9 of Fig. 85A. Figure 144 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and a further modulation method is 1 〇 24 q Am and a multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 144 is 2 is directly replaced by the code bit of Fig. 88A in which only the multiple b is ι. Therefore, the replacement of the code bits of Fig. M4 is in accordance with the allocation rule of Fig. 87. The LDPC code is a code length >^ is 162 bits, and the coding rate is 8/9 [then code, further modulation is 1024QAM, and the multiple 5 is 2 in the case of the multiplexer 25, in the vertical line The code bits written by the memory 31 whose direction x direction is (16200/(10χ2)) χ (i〇x2) bits are read in the order of (mb) bits in the course direction and supplied to the replacement. Part 32 (Fig. 16, circle 17). The replacing unit 32 assigns the symbol % to bl9 ' read from the lGx2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 44. 135786.doc 200937872 l The 〇x2(=mb) bit symbol y〇 to yi9 is replaced by the code 位b〇 to b!9 of the 1 〇x2 (= mb) bit. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y 1, respectively. The code bit b6 is assigned to the symbol bit y2, and the code bit b8 is assigned to the symbol bit y3.
將碼位元b! 〇分配給符元位元y 4, 將碼位元b! 2分配給符元位元y 6, 將碼位元b i 4分配給符元位元y 5, 將碼位元b i 6分配給符元位元y 9, 將碼位元b 18分配給符元位元y 7, 將碼位元b 1分配給符元位元y! 8, 將碼位元b3分配給符元位元y 1 〇, 將碼位元b5分配給符元位元y 11, 將碼位元b7分配給符元位元y 12, 將碼位元b9分配給符元位元y 13, 將碼位元th!分配給符元位元y 14, 將碼位元b! 3分配給符元位元y 16, 將碼位元b i 5分配給符元位元y 15, 將碼位元b i 7分配給符元位元y 19, 將碼位元b丨9分配給符元位元y 17, 而進行替換。 135786.doc -202- 200937872 此外 >Vn ISJ it η· -^^b0sb2,b4,b6,b8,b10jbl2}bl4jbl6)bl8 之替換模式及碼位几b丨,hkhbd丨丨,b丨Jab丨do之替換 模式兩者均與圖88A之碼位元%至、之替換模式一致。 圖145係表示LDPC碼是碼長N為648〇〇位元、編碼率為 8/9之LDPC碼,進一步調變方式為1〇24QAM,倍數b為2之 情況下之碼位元之替換例。The code bit b! 〇 is assigned to the symbol bit y 4 , the code bit b ! 2 is assigned to the symbol bit y 6, the code bit bi 4 is assigned to the symbol bit y 5 , and the code bit is The element bi 6 is assigned to the symbol bit y 9, the code bit b 18 is assigned to the symbol bit y 7, the code bit b 1 is assigned to the symbol bit y! 8, and the code bit b3 is assigned to The symbol bit y 1 〇, the code bit b5 is assigned to the symbol bit y 11, the code bit b7 is assigned to the symbol bit y 12, and the code bit b9 is assigned to the symbol bit y 13, The code bit element th! is assigned to the symbol bit y 14, the code bit b! 3 is assigned to the symbol bit y 16, the code bit bi 5 is assigned to the symbol bit y 15, and the code bit is Bi 7 is assigned to the symbol bit y 19, and the code bit b丨9 is assigned to the symbol bit y 17, and replaced. 135786.doc -202- 200937872 In addition, >Vn ISJ it η· -^^b0sb2,b4,b6,b8,b10jbl2}bl4jbl6) bl8 replacement mode and code bit b丨, hkhbd丨丨, b丨Jab丨do The replacement mode is consistent with the replacement mode of the code bit % to FIG. 88A. Figure 145 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 648 〇〇 bits and a coding rate of 8/9, and the modulation mode is 1 〇 24QAM, and the multiple b is 2. .
圖145之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖91A之碼位元之替換。因此, 圖145之碼位元之替換係按照圖9〇之分配規則。 LDPC碼是碼長N為64800位元、編碼率為8/92LDpc 碼,進一步調變方式為1024qAM、倍數b*2之情況下,於 解多工器25,於縱行方向x橫列方向為(648〇〇/(i〇x2))x (10x2)位元之記憶體31寫入之碼位元係於橫列方向,以 l〇x2(=mb)位元單位讀出,並供給至替換部32(圖16、 17)。 替換部32係以將讀出自記憶體31之1〇x2(=rnb)位元之螞 位元、至bM ’如圖145所示分配給連續之2(=b)個符元之 l〇x2(-mb)位元之符元位元至μ之方式,來替換 l〇x2(=mb)位元之碼位元1)()至1)丨9。 亦即’替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元yi, 將碼位元1)6分配給符元位元y2, 135786.doc 200937872 將碼位元b 8分配給符元位元y 3 ’ 將碼位元b 1 〇分配給符元位元y 4 ’ 將碼位元bi2分配給符元位元y6 ’ 將碼位元bi4分配給符元位元y5 ’ 將碼位元bi6分配給符元位元y9 ’ 將碼位元bi8分配給符元位元y7, 將碼位元b 1分配給符元位元y丨8, 將瑪位元b3分配給符元位元y丨〇, ^ 將碼位元b5分配給符元位元y丨1, 將碼位元b7分配給符元位元丫12, 將碼位元b 9分配給符元位元y i 3, 將碼位元b i〗分配給符元位元y 14, 將碼位元b13分配給符元位元y16, 將碼位元b15分配給符元位元715, 將碼位元b17分配給符元位元y19 , 將碼位元b〗9分配給符元位元717, ® 而進行替換。 此外,於圖 i45,碼位元b〇,b2,b4,b6,b8bi〇b^ 之替換模式及碼位元nm^bu’bab^b14’16’18 模式兩者均與圖91A之瑪位元bj b替17’ 19之替換 請係表W是碼長__;:^:_ 9/10之LDPC碼,進一步調變方式為1〇24QAM,倍數b為2 之情況下之碼位元之替換例。 圖146之倍數b為2之情況下之碼位元之替換係直接利用 135786.doc -204- 200937872 僅有倍數_之點不同之圖94A之碼位元之替換。因此, 圖146之碼位元之替換係按照圖93之分配規則。 LDPC碼是碼長_64_位元、編碼率為9/H)之LDPC 碼,進一步調變方式為1024QAM、倍數_之情況下於 解多工器25 ’於縱行方向x橫列方向為㈣如 (购)位元之記憶體31寫入之碼位元係於橫列方向以 H>x2(=mb)位元單位讀出,並供給至替換部32(圖μ 17)。 m © 替換部32係以將讀出自記憶體31i10x2(=mb)位元之 位元〜至!^9,如圖146所示分配給連續之2(=b)個符元螞 l〇x2(=mb)位元之符元位元yQ至h之方式,來=< l〇x2(=mb)位元之碼位元b。至比9。 換 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b/t分配給符元位元y丨, 〇 W 將碼位元1)6分配給符元位元y2, 將碼位元b 8分配給符元位元y 3, 將碼位元b!G分配給符元位元, 將碼位元b!2分配給符元位元y6, 將碼位元b 14分配給符元位元y 5, 將碼位元bi6分配給符元位元y9, 將碼位元bis分配給符元位元y7, 將碼位元b 1分配給符元位元y丨8 ’ 135786.doc -205- 200937872 將碼位元b3分配給符元位元yi〇, 將碼位元I)5分配給符元位元y i 1, 將瑪位元1>7分配給符元位元yn, 將碼位元t>9分配給符元位元y i 3, 將碼位元bn分配給符元位元yi4, 將碼位元!^3分配給符元位元716, 將碼位元1^5分配給符元位元yi5, 將碼位元1^7分配給符元位元力9, Ο 將碼位元b!9分配給符元位元y17, 而進行替換。 此外於圖 146,碼位元 b〇,b2,b4,b6,b8,bi〇,bi2,bM,bi6 bi8 之替換模式及碼位元 bl,b3,b5,b7,b9,bn,b】3,bl5,bl7bK_ 模式兩者均與圖94A之碼位元“至匕之替換模式一致。 圖U7係表示LDPC碼是碼長_ i議位元、編碼率為 2/3之LDPC碼,進一步調變方式為4〇96QAM,倍數匕為2之 情況下之碼位元之替換例。 0 圖147之倍數4 2之情況下之碼位元之替換係直接利用 僅有倍數…之點不同之圖97A之碼位元之㈣。因此, 圖147之碼位元之替換係按照圖%之分配規則。 LDPC瑪是瑪長料1620〇位元、編碼率為2/3之LDPC 碼’進步調變方式為4〇96QAM、倍數#2之情況下,於 解多工器25 ’於縱行方向χ橫列方向為(ΐ62〇〇/(ι2χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向以 位元單位讀出,並供給至替換部32(圖16、圖 135786.doc -206 - 200937872 17)。 替換部32係以將讀出自記憶體31之12x2(=mb)位元之碼 位元bQ至b23,如圖147所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元y〇至y23之方式,來替換 12x2(=mb)位元之碼位元bG至b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y! 〇, 將碼位元b2分配給符元位元y〇, ΟThe replacement of the code bits in the case where the multiple b of Fig. 145 is 2 is directly replaced by the code bit of Fig. 91A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of Fig. 145 is in accordance with the distribution rule of Fig. 9. The LDPC code has a code length N of 64,800 bits and a coding rate of 8/92 LDpc code. In the case where the modulation mode is 1024 qAM and the multiple b*2, the multiplexer 25 is in the direction of the x direction in the wale direction. (648〇〇/(i〇x2)) x (10x2) bit memory 31 is written in the horizontal direction, read in l〇x2 (= mb) bit units, and supplied to Replacement unit 32 (Figs. 16, 17). The replacing unit 32 assigns the 蚂x2 (=rnb) bit from the memory 31 to bM 'as shown in FIG. 145 to the consecutive 2 (=b) symbols l 〇 x 2 The (-mb) bit symbol is transferred to μ in order to replace the code bits 1)() of 1〇x2(=mb) bits to 1)丨9. That is, the 'replacement unit 32 assigns the code bit bG to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol yi, respectively. Bit 1)6 is assigned to symbol bit y2, 135786.doc 200937872 assigns code bit b 8 to symbol bit y 3 ' assigns code bit b 1 〇 to symbol bit y 4 ' The bit bi2 is assigned to the symbol bit y6'. The code bit bi4 is assigned to the symbol bit y5'. The code bit bi6 is assigned to the symbol bit y9'. The code bit bi8 is assigned to the symbol bit y7. The code bit b 1 is assigned to the symbol bit y 丨 8 , the mega cell b3 is assigned to the symbol y 丨〇 , ^ the code bit b b is assigned to the symbol y 丨 1 , and the code bit is The element b7 is assigned to the symbol bit 丫12, the code bit b9 is assigned to the symbol yi 3, the code bit bi is assigned to the symbol y 14, and the code bit b13 is assigned to the symbol The bit y16 assigns the code bit b15 to the symbol bit 715, assigns the code bit b17 to the symbol bit y19, and assigns the code bit b 9 to the symbol bit 717, and replaces it. In addition, in FIG. i45, the replacement mode of the code bits b〇, b2, b4, b6, b8bi〇b^ and the code bit nm^bu'bab^b14'16'18 mode are both the position of FIG. 91A. The replacement of the element bj b for the 17' 19 is the LDPC code of the code length __;:^:_ 9/10, and the code bit element in the case where the modulation mode is 1〇24QAM and the multiple b is 2. An alternative. The replacement of the code bits in the case where the multiple b of Fig. 146 is 2 is directly utilized. 135786.doc -204- 200937872 The replacement of the code bits of Fig. 94A differing only in the point of the multiple _. Therefore, the replacement of the code bits of FIG. 146 is in accordance with the allocation rule of FIG. The LDPC code is an LDPC code with a code length of _64_bit and a coding rate of 9/H. The further modulation method is 1024QAM and the multiple _ is in the direction of the multiplexer 25' in the wale direction x course. (4) The code bits written in the memory 31 of the (purchased) bit are read in the horizontal direction in the H>x2 (= mb) bit unit, and supplied to the replacement unit 32 (Fig. 17). The m © replacement unit 32 is to read the bits from the memory 31i10x2 (= mb) bits to ~! ^9, as shown in Fig. 146, is assigned to the consecutive 2 (=b) symbolic l〇x2 (= mb) bits of the symbol bits yQ to h, == l〇x2 (= Mb) the bit element b of the bit. To the ratio of 9. In other words, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b/t to the symbol bit. y丨, 〇W assigns code bit 1)6 to symbol bit y2, assigns code bit b8 to symbol bit y3, and assigns bit bit b!G to symbol bit, The code bit b!2 is assigned to the symbol bit y6, the code bit b 14 is assigned to the symbol bit y 5 , the code bit bi6 is assigned to the symbol bit y9, and the code bit bis is assigned to the symbol Meta-bit y7, assigning code bit b 1 to symbol bit y 丨 8 ' 135786.doc -205- 200937872 assigning code bit b3 to symbol bit yi 〇, assigning code bit I) 5 The symbol bit yi 1, the numerator 1>7 is assigned to the symbol ary yn, the code bit t>9 is assigned to the symbol yi 3 , and the symbol bn is assigned to the symbol 00 Yi4, assigning the code bit !^3 to the symbol bit 716, assigning the code bit 1^5 to the symbol bit yi5, and assigning the code bit 1^7 to the symbol bit force 9, Ο The code bit b!9 is assigned to the symbol bit y17 and replaced. In addition, in FIG. 146, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bM, bi6 bi8 and the code bits bl, b3, b5, b7, b9, bn, b] 3 The bl5, bl7bK_ mode are both consistent with the replacement mode of the code bit of FIG. 94A. Figure U7 shows that the LDPC code is a code length _ i argument, and an LDPC code with a coding rate of 2/3 is further adjusted. The variable mode is 4〇96QAM, and the substitution of the code bit in the case of the multiple 匕 is 2. 0 The replacement of the code bit in the case of the multiple of 4 in Figure 147 is directly using the difference of only the multiples... The code bit of 97A is (4). Therefore, the replacement of the code bit in Figure 147 is in accordance with the allocation rule of Figure %. LDPC Ma is a long-term 1620-bit LDPC code with a coding rate of 2/3 'progressive modulation In the case where the mode is 4〇96QAM and the multiple #2 is written, the memory 31 of the demultiplexer 25' is stored in the direction of the wale direction (ΐ62〇〇/(ι2χ2))χ (12x2) bits. The code bits are read in units of bits in the course direction and supplied to the replacement unit 32 (Fig. 16, Fig. 135786.doc-206 - 200937872 17). The replacement unit 32 is to read 12x2 from the memory 31. (=mb The bit elements bQ to b23 of the bit are replaced by the manner of assigning the symbol bits y〇 to y23 of the consecutive 2 (=b) symbols of 12x2 (= mb) bits as shown in FIG. The code bits bG to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y! 分别, respectively, and assigns the code bit b2 to the symbol bit. Y〇, Ο
將碼位元b4分配給符元位元y 1, 將碼位元b6分配給符元位元y2, 將碼位元b8分配給符元位元y3, 將碼位元b i 〇分配給符元位元y4, 將碼位元b! 2分配給符元位元y 5, 將碼位元b 14分配給符元位元y 6, 將碼位元b! 6分配給符元位元y 8, 將碼位元b i 8分配給符元位元y 7, 將碼位元b2Q分配給符元位元y!!, 將碼位元b22分配給符元位元y9, 將碼位元b!分配給符元位元y22, 將碼位元b3分配給符元位元y!2, 將碼位元b 5分配給符元位元y 1 3 , 將碼位元b7分配給符元位元y丨4, 將碼位元b9分配給符元位元y i 5, 將碼位元b!!分配給符元位元y! 6, 135786.doc -207- 200937872 將碼位元b〗3分配給符元位元y 17, 將碼位元b 15分配給符元位元y丨8, 將碼位元b17分配給符元位元y2〇, 將碼位元b i 9分配給符元位元y丨9, 將碼位元b2 !分配給符元位元y 23, 將碼位元b23分配給符元位元y21, 而進行替換。 此外’於圖 147,碼位元b0,b2,b4,b6,b8,b,0,b12,b14,b16,b18, O b2Q,b22 之替換模式及碼位元 1^1)3,b5,b7,b9,bii,b13,b15,b17,b19, b2i,b23之替換模式兩者均與圖97A之碼位元b〇至bn之替換 模式一致。 圖148係表示LDPC碼是碼長N為64800位元、編碼率為 2/3之LDPC碼’進一步調變方式為4〇96QAM,倍數42之 情況下之碼位元之替換例。 圖148之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖ιοοΑ之碼位元之替換。因此, © 圖148之碼位元之替換係按照囷99之分配規則。 LDPC瑪是碼長N為64800位元、編碼率為2/3iLDpc 碼,進一步調變方式為4096QAM、倍數b為2之情況下,於 解多工器25,於縱行方向x橫列方向為(648〇〇/(ι2χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31<12x2(=mb)位元之碼 135786.doc -208- 200937872 位元bG至b23,如圖148所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元y〇至y23之方式,來替換 12x2(=mb)位元之碼位元bG至b23。 亦即,替換部32係分別 將碼位元bG分配給符元位元y 1 〇, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y 1, 將碼位元b6分配給符元位元y2, 0 將碼位元b8分配給符元位元y3, 將碼位元b 1 〇分配給符元位元y 4, 將碼位元b i 2分配給符元位元y 5, 將碼位元b丨4分配給符元位元y 6, 將碼位元b! 6分配給符元位元y 8, 將碼位元b! 8分配給符元位元y 7, 將碼位元b2〇分配給符元位元y 11, 將碼位元b22分配給符元位元y9, © 將碼位元b!分配給符元位元y22, 將碼位元b3分配給符元位元y!2, 將碼位元b5分配給符元位元y!3, 將碼位元b7分配給符元位元y 14, 將碼位元b9分配給符元位元y 15, 將碼位元b!!分配給符元位元y16, 將碼位元b13分配給符元位元yi7, 將碼位元b 15分配給符元位元y 1 8, 135786.doc -209- 200937872 將碼位元b 17分配給符元位元y 20, 將碼位元b 1 9分配給符元位元y! 9, 將碼位元b2 1分配給符元位元y23, 將碼位元b23分配給符元位元y21, 而進行替換。 此外,於圖148,碼位元The code bit b4 is assigned to the symbol bit y 1, the code bit b6 is assigned to the symbol bit y2, the code bit b8 is assigned to the symbol bit y3, and the code bit bi 〇 is assigned to the symbol Bit y4, assigning code bit b! 2 to symbol bit y 5, assigning code bit b 14 to symbol bit y 6, assigning code bit b! 6 to symbol bit y 8 The code bit bi 8 is assigned to the symbol bit y 7, the code bit b2Q is assigned to the symbol bit y!!, the code bit b22 is assigned to the symbol bit y9, and the code bit b! Assigned to the symbol bit y22, the code bit b3 is assigned to the symbol bit y!2, the code bit b5 is assigned to the symbol bit y 1 3 , and the code bit b7 is assigned to the symbol bit Y丨4, assign code bit b9 to symbol bit yi 5, assign code bit b!! to symbol bit y! 6, 135786.doc -207- 200937872 assign code bit b 3 The symbol bit y 17, assigns the code bit b 15 to the symbol bit y 丨 8 , assigns the code bit b 17 to the symbol y2 〇 , and assigns the code bit bi 9 to the symbol bit . Y丨9, assigning the code bit b2 ! to the symbol bit y 23, and assigning the code bit b23 to the symbol bit y21, and performing replace. In addition, in Figure 147, the replacement pattern of the code bits b0, b2, b4, b6, b8, b, 0, b12, b14, b16, b18, O b2Q, b22 and the code bits 1^1) 3, b5, The replacement modes of b7, b9, bii, b13, b15, b17, b19, b2i, b23 are both identical to the replacement mode of the code bits b〇 to bn of Fig. 97A. Figure 148 is a diagram showing an alternative example of the LDPC code in which the LDPC code of the LDPC code having a code length N of 64,800 bits and a coding rate of 2/3 is further modulated by 4〇96QAM, and the multiple is 42. The replacement of the code bit in the case where the multiple b of Fig. 148 is 2 is directly replaced by the code bit of the figure ιοο which differs only by the multiple b. Therefore, the replacement of the code bits in Figure 148 is in accordance with the allocation rules of 囷99. The LDPC is a code length N of 64,800 bits and a coding rate of 2/3 iLDpc code. When the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction x direction. (648〇〇/(ι2χ2)) 码 (12x2) bit memory 31 written code bits are read in the horizontal direction in units of 12x2 (= mb) bits and supplied to the replacement unit 32 (Fig. 16, Figure 17). The replacing unit 32 is configured to allocate the code 135786.doc - 208 - 200937872 bits bG to b23 read from the memory 31 < 12x2 (= mb) bits, as shown in Fig. 148 to consecutive 2 (= b) characters. The 12x2 (= mb) bit symbol bits y 〇 y y y 23 are replaced by 12 x 2 (= mb) bits of code bits bG to b23. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 1 〇, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y 1 . , the code bit b6 is assigned to the symbol bit y2, 0 the code bit b8 is assigned to the symbol bit y3, the code bit b 1 〇 is assigned to the symbol bit y 4 , and the code bit bi 2 is Assigned to the symbol bit y 5, the code bit b丨4 is assigned to the symbol bit y 6, the code bit b! 6 is assigned to the symbol bit y 8, and the code bit b! 8 is assigned to The symbol bit y 7, the code bit b2 is assigned to the symbol y 11, the code bit b22 is assigned to the symbol y9, and the code bit b! is assigned to the symbol y22. The code bit b3 is assigned to the symbol bit y!2, the code bit b5 is assigned to the symbol bit y!3, the code bit b7 is assigned to the symbol bit y 14, and the code bit b9 is assigned To the symbol bit y 15, the code bit b!! is assigned to the symbol bit y16, the code bit b13 is assigned to the symbol bit yi7, and the code bit b 15 is assigned to the symbol bit y 1 8, 135786.doc -209- 200937872 assigning code bit b 17 to symbol bit y 20, assigning code bit b 1 9 The symbol bit y! 9, the code bit b2 1 is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in Figure 148, the code bit
ι>2〇,ι>22之替換模式及碼位元bi,b3,b5,b7,b9,bn,bi3,bi5,bi7,bAι>2〇, ι>22 replacement mode and code bits bi, b3, b5, b7, b9, bn, bi3, bi5, bi7, bA
b^’bu之替換模式兩者均與圖i〇〇A之碼位元b()ibn之替換 模式一致。 圖149係表示LDPC碼是碼長^^為162〇〇位元、編碼率為 3M之LDPC碼,進一步調變方式為4〇96QAM,倍數之 情況下之碼位元之替換例。 圖14 9之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖1〇3A之碼位元之替換。因此, 圖149之碼位元之替換係按照圖1〇2之分配規則。 LDPC碼是瑪長料162〇〇位元、編碼率為3/4之匕则 碼,進一步調變方式為4〇96QAM、倍數5為2之情況下於 解多工器25 ’於縱行方向χ橫列方向為(162_…2”: ()位元之6己憶體31寫入之碼位元係於橫列方向,以 17)/吻位几單位讀出,並供給至替換部32(圖16、圖 替換部32係 位元b〇至b23 , 12x2(=mb)位 以將讀出自記憶體31之12><2(=灿)位元之碼 如囷149所不分配給連續之2(=b)個符元之 元之符元位元乃至%之方式,來替換 135786.doc -210· 200937872 12x2(=mb)位元之碼位元b〇至b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將瑪位元b4分配給符元位元y6, 將碼位元b6分配給符元位元y!,The replacement mode of b^'bu is identical to the replacement mode of the code bit b()ibn of Fig. Figure 149 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3M, and a further modulation method is 4 〇 96QAM, in the case of a multiple. The replacement of the code bits in the case where the multiple b of Fig. 14 is 2 is directly replaced by the code bits of Fig. 1〇3A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 149 is in accordance with the allocation rule of FIG. The LDPC code is 162 〇〇 bits of Ma Chang material, and the coding rate is 3/4 , code. The further modulation method is 4〇96QAM, and the multiple 5 is 2 in the multiplexer 25' in the longitudinal direction. The direction of the χ course is (162_...2): (6) The code bit written by the 6-bit memory 31 is in the course direction, read out in 17)/snap position, and supplied to the replacement unit 32. (FIG. 16, the replacing unit 32 is a bit b〇 to b23, and the 12x2 (= mb) bit is not allocated to the code read from the memory 12 of the 12<2 (=can) bit, such as 囷149. Replace the code bits b〇 to b23 of 135786.doc -210· 200937872 12x2 (= mb) bits for the consecutive 2 (= b) symbol elements of the symbol or even %. The replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b2 to the symbol bit y, and assigns the mbit b4 to the symbol y6, and the code bit B6 is assigned to the symbol y!,
將碼位元b8分配給符元位元y4, 將碼位元b! 〇分配給符元位元y 5, 將碼位元b! 2分配給符元位元y 2, 將瑪位元b! 4分配給符元位元y 3, 將碼位元b! 6分配給符元位元y 7, 將碼位元b! 8分配給符元位元y! 〇, 將碼位元b2G分配給符元位元y 11, 將碼位元b22分配給符元位元y9, 將碼位元b丨分配給符元位元y2〇, 將碼位元b3分配給符元位元y! 2, 將碼位元b5分配給符元位元y! 8, 將碼位元b7分配給符元位元y! 3, 將碼位元b9分配給符元位元y 16, 將碼位元b!丨分配給符元位元y! 7, 將碼位元b! 3分配給符元位元y 1 4, 將碼位元b ! 5分配給符元位元y 1 5, 將碼位元b ! 7分配給符元位元y ! 9, 將碼位元b ! 9分配給符元位元y22, -211 - 135786.doc 200937872 將碼位元l>2 1分配給符元位元y23, 將碼位元b〗3分配給符元位元y2 j, 而進行替換。 此外,於圖 149,碼位元 b0,b2,b4,b6,b8,b10,b12,b14,b16,bl8, b20,b22之替換模式及碼位元bl,b3,b5,b7,b9,bu,bn,bi5bi7,bi9, hub23之替換模式兩者均與圖103A之碼位元b0至bu之替換 模式一致。 圖150係表示LDPC碼是碼長N為64800位元、編碼率為 Ο 3/4之LDPC碼’進一步調變方式為4096QAM,倍數b為2之 情況下之碼位元之替換例。 圖150之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖1 〇6A之碼位元之替換。因此, 圖150之碼位元之替換係按照圖1〇5之分配規則。The code bit b8 is assigned to the symbol bit y4, the code bit b! 〇 is assigned to the symbol bit y 5 , the code bit b ! 2 is assigned to the symbol bit y 2 , and the m-bit b is 4 is assigned to the symbol bit y 3, the code bit b! 6 is assigned to the symbol bit y 7, the code bit b! 8 is assigned to the symbol bit y! 〇, the code bit b2G is assigned The symbol bit y11 is assigned to the symbol bit y9, the code bit b 丨 is assigned to the symbol y2 〇, and the code bit b3 is assigned to the symbol y! 2 , the code bit b5 is assigned to the symbol bit y! 8, the code bit b7 is assigned to the symbol bit y! 3, and the code bit b9 is assigned to the symbol bit y 16, the code bit b !丨 is assigned to the symbol bit y! 7, the code bit b! 3 is assigned to the symbol bit y 1 4 , the code bit b b 5 is assigned to the symbol bit y 1 5 , and the code bit is b ! 7 is assigned to the symbol bit y ! 9, the code bit b ! 9 is assigned to the symbol bit y22, -211 - 135786.doc 200937872 The code bit l > 2 1 is assigned to the symbol bit y23 , the code bit b 3 is assigned to the symbol bit y2 j and replaced. In addition, in FIG. 149, the replacement modes of the code bits b0, b2, b4, b6, b8, b10, b12, b14, b16, bl8, b20, b22 and the code bits bl, b3, b5, b7, b9, bu The replacement modes of , bn, bi5bi7, bi9, hub23 are both identical to the replacement mode of the code bits b0 to bu of FIG. 103A. Fig. 150 is a diagram showing an alternative example of the code bit in the case where the LDPC code is an LDPC code whose code length N is 64,800 bits and the coding rate is Ο 3/4, and the modulation mode is 4096QAM, and the multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 150 is 2 is directly replaced by the code bits of Fig. 1 〇 6A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 150 is in accordance with the allocation rule of FIG.
LDPC碼是瑪長N為64800位元、編碼率為3/4之LDPC 碼’進一步調變方式為4096QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(12χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶趙3 1之12X2(=mb)位元之碼 位元b〇至bu,如圖150所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元yQ至^之方式,來替換 12x2( = mb)位元之碼位元bG至b23。 亦即,替換部32係分別 135786.doc -212- 200937872 將碼位元b〇分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y6, 將碼位元b6分配給符元位元y丨, 將碼位元b8分配給符元位元y4, 將碼位元b t G分配給符元位元y 5, 將碼位元b丨2分配給符元位元y 2, 將碼位元b! 4分配給符元位元y 3, ❹ 將碼位元b! 6分配給符元位元y 7, 將碼位元b! 8分配給符元位元y 1 〇, 將碼位元b2G分配給符元位元y! 1, 將碼位元b22分配給符元位元y9, 將碼位元b!分配給符元位元y2〇, 將碼位元b3分配給符元位元y i 2, 將碼位元b5分配給符元位元y 18, 將碼位元b7分配給符元位元y!3, 〇 將碼位元b9分配給符元位元>^6, 將碼位元b t!分配給符元位元y! 7, 將碼位元b i 3分配給符元位元y 14, 將碼位元b丨5分配給符元位元y 15, 將碼位元b! 7分配給符元位元y! 9, 將碼位元b ! 9分配給符元位元y22, 將碼位元b2!分配給符元位元y23, 將碼位元b23分配給符元位元y2i, -213- 135786.doc 200937872 而進行替換。 此外’於圖 150,碼位元b〇,b2,b4,b6,b8,bi〇,bi2,bi4,bi6,b】8, b2〇,b22之替換模式及碼位元bi,b3,b5,b7,b9,bn,bi3,bi5,bi7,bi9, bu’t»23之替換模式兩者均與圖ι〇6Α之碼位元之替換 模式一致。 圖151係表示LDPC碼是碼長N為16200位元、編碼率為 4/5之LDPC碼’進一步調變方式為4〇96qA]VI,倍數6為2之 情況下之碼位元之替換例。 Ο 圖151之倍數1?為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖i〇9A之碼位元之替換。因此, 圖1 5 1之碼位元之替換係按照圖108之分配規則。The LDPC code is an LDPC code with a Ma Chang N of 64,800 bits and a coding rate of 3/4. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the longitudinal direction. The code bit written in the memory 31 of the direction (648〇〇/(12χ2)) χ (12x2) bits is in the course direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code bits b to 12 from the 12×2 (= mb) bits of the memory Zhao 3 to 12, and assign 12 to 2 (=b) symbols of the consecutive symbols as shown in FIG. The mb) bits of the bit yQ to ^ are replaced by the code bits bG to b23 of the 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b2 to the symbol bit y〇, and assigns the code bit b4 to the symbol bit y8, respectively, 135786.doc -212- 200937872 The symbol bit y6 assigns the code bit b6 to the symbol bit y丨, assigns the code bit b8 to the symbol bit y4, and assigns the code bit bt G to the symbol bit y 5 , Bit b丨2 is assigned to symbol bit y 2, code bit b! 4 is assigned to symbol bit y 3, 码 code bit b! 6 is assigned to symbol bit y 7, and code bit is allocated The element b! 8 is assigned to the symbol bit y 1 〇, the code bit b2G is assigned to the symbol bit y! 1, the code bit b22 is assigned to the symbol bit y9, and the code bit b! is assigned to The symbol bit y2 〇, the code bit b3 is assigned to the symbol bit yi 2 , the code bit b5 is assigned to the symbol bit y 18 , and the code bit b7 is assigned to the symbol bit y ! 3,分配 assigning the code bit b9 to the symbol bit >^6, assigning the code bit bt! to the symbol bit y! 7, and assigning the code bit bi 3 to the symbol bit y 14, the code The bit b丨5 is assigned to the symbol bit y 15, the code bit b! 7 is assigned to the symbol bit y! 9, and the code bit is b ! 9 is assigned to the symbol bit y22, the code bit b2! is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y2i, -213- 135786.doc 200937872 for replacement. In addition, in Figure 150, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, b] 8, b2〇, b22 and the code bits bi, b3, b5, The replacement modes of b7, b9, bn, bi3, bi5, bi7, bi9, bu't»23 are both consistent with the replacement mode of the code bits of Fig. Figure 151 is a diagram showing an alternative example of the LDPC code in which the code length N is 16,200 bits, the LDPC code of the coding rate is 4/5, the further modulation method is 4〇96qA]VI, and the multiple 6 is 2. .替换 Figure 151 is a multiple of 1? The replacement of the code bits in the case of 2 is directly used. The replacement of the code bits of the figure i〇9A with only the multiple b being 1 is different. Therefore, the replacement of the code bits of Fig. 151 is in accordance with the distribution rule of Fig. 108.
LDPC碼是碼長n為16200位元、編碼率為4/5之LDPC 碼’進一步調變方式為4〇96qAm、倍數b為2之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(12χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 © 17)。 替換部32係以將讀出自記憶體31之12x2(=mb)位元之碼 位TLbo至bu,如圖151所示分配給連續之2(=b)個符元之 12><2(-mb)位元之符元位元至y23之方式,來替換 12x2(=mb)位元之碼位元b(^b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元“, 將碼位元t>2分配給符元位元y〇, 135786.doc -214- 200937872 將碼位元b4分配給符元位元y6, 將碼位元b6分配給符元位元y 1, 將碼位元b8分配給符元位元y4, 將碼位元b i 〇分配給符元位元y 5, 將碼位元b 12分配給符元位元y 2, 將碼位元b! 4分配給符元位元y 3, 將碼位元b! 6分配給符元位元y 7, 將碼位元b! 8分配給符元位元y 1 〇,The LDPC code is an LDPC code having a code length n of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 4〇96qAm and the multiple b is 2, the multiplexer 25 is in the traverse direction x. The code bits written in the memory 31 of the (162 〇〇 / (12 χ 2)) χ (12 x 2) bit are in the course direction, read in 12x2 (= mb) bit units, and supplied to Replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code bits TLbo to bu read from the 12x2 (= mb) bits of the memory 31 to 12 consecutive 2 (= b) symbols as shown in FIG. 151. < 2 ( -mb) the bitwise bit of the bit to y23, replacing the code bit b of the 12x2 (= mb) bit (^b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol, respectively. The meta-bit", assigns the code bit t>2 to the symbol bit y〇, 135786.doc -214- 200937872 assigns the code bit b4 to the symbol bit y6, and assigns the code bit b6 to the symbol Bit y 1, assign code bit b8 to symbol bit y4, assign code bit bi 〇 to symbol bit y 5 , assign code bit b 12 to symbol bit y 2 , and code Bit b! 4 is assigned to symbol bit y 3, code bit b! 6 is assigned to symbol bit y 7, and code bit b! 8 is assigned to symbol bit y 1 〇,
將碼位元b2G分配給符元位元y 11, 將碼位元b22分配給符元位元y9, 將碼位元b 1分配給符元位元y2〇, 將碼位元b3分配給符元位元y 12, 將碼位元b5分配給符元位元yis, 將碼位元b7分配給符元位元y 13, 將碼位元b9分配給符元位元y 16, 將碼位元b η分配給符元位元yi 7, 將碼位元b】3分配給符元位元y 14, 將碼位元b! 5分配給符元位元y 1 5, 將碼位元b17分配給符元位元yi9, 將碼位元b ! 9分配給符元位元y 22, 將碼位元b21分配給符元位元y23 ’ 將碼位元b23分配給符元位元y21 ’ 而進行替換。 此外,於圖 151,碼位元 b〇,b2,b4,b6,b8,bi〇,bi2,bi4,bi6,bi8, -215- 135786.doc 200937872 b—22 之替換模式及碼位元 bib3b5,b7,b9,bii,bi3,bi5,bi7^ b2〗,b23之替換模式兩者均與圖1〇9八之碼位元%至^丨之替換 模式一致。 圖152係表示LDPC碼是碼長Ng 648〇〇位元、編碼率為 4/5之LDPC碼,進一步調變方式為4〇96QAM,倍數b為2之 情況下之碼位元之替換例。 圖152之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖112A之碼位元之替換。因此, © 圖152之碼位元之替換係按照圖111之分配規則。 LDPC碼是碼長N為64800位元 '編碼率為4/5之LDPC 碼’進一步調變方式為4096QAM、倍數b為2之情況下,於 解多工器25 ’於縱行方向X橫列方向為(648〇〇/(12χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31之12x2(=mb)位元之碼 g% ¥ 位兀b〇至bn,如圖152所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元yG至μ之方式,來替換 12x2(=mb)位元之碼位元bG至b23。 亦即,替換部32係分別 將碼位元bG分配給符元位元y 8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y6 ’ 將碼位元be分配給符元位元y 1 ’ 135786.doc •216· 200937872 將碼位元b8分配給符元位元y4, 將碼位元b i q分配給符元位元y 5, 將碼位元b i 2分配給符元位元y 2, 將碼位元b】4分配給符元位元y 3, 將碼位元b! 6分配給符元位元y 7, 將碼位元b i 8分配給符元位元y 1 〇, 將碼位元b2G分配給符元位元y 11, 將碼位元b22分配給符元位元y9,The code bit b2G is assigned to the symbol bit y 11, the code bit b22 is assigned to the symbol bit y9, the code bit b1 is assigned to the symbol bit y2, and the code bit b3 is assigned to the symbol The bit position y 12, the code bit b5 is assigned to the symbol bit yis, the code bit b7 is assigned to the symbol bit y 13, and the code bit b9 is assigned to the symbol bit y 16, the code bit is The element b η is assigned to the symbol bit yi 7, the code bit b]3 is assigned to the symbol bit y 14, the code bit b! 5 is assigned to the symbol bit y 1 5 , and the code bit b17 Assigned to the symbol bit yi9, the code bit b ! 9 is assigned to the symbol bit y 22 , the code bit b21 is assigned to the symbol bit y23 ' and the code bit b23 is assigned to the symbol bit y21 ' And replace it. In addition, in FIG. 151, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, bi8, -215-135786.doc 200937872 b-22 and the code bit bib3b5, B7, b9, bii, bi3, bi5, bi7^b2, and the replacement mode of b23 are both consistent with the replacement mode of the code bits % to ^ of FIG. Figure 152 is a diagram showing an alternative example of the code bit in the case where the LDPC code is a code length Ng 648 、 bit, an LDPC code having a coding rate of 4/5, and a further modulation method is 4 〇 96QAM, and the multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 152 is 2 is directly replaced by the code bit of Fig. 112A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 152 is in accordance with the distribution rule of Fig. 111. The LDPC code is a code length N of 64,800 bits and an LDPC code having a coding rate of 4/5. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25' is in the longitudinal direction X direction. The code bit written in the memory 31 of the direction (648〇〇/(12χ2)) χ (12x2) bits is in the course direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code g% of the 12x2 (= mb) bits read from the memory 31 to bn, and assign it to 12x2 of consecutive 2 (=b) symbols as shown in FIG. The (= mb) bit symbol yG to μ is replaced by the code bits bG to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 8, respectively, assigns the code bit b2 to the symbol bit y, and assigns the code bit b4 to the symbol y6 ' The code bit be assigned to the symbol bit y 1 ' 135786.doc • 216· 200937872 assigns the code bit b8 to the symbol bit y4, assigns the code bit biq to the symbol bit y 5 , and sets the code bit The element bi 2 is assigned to the symbol bit y 2 , the code bit b 4 is assigned to the symbol bit y 3 , the code bit b b 6 is assigned to the symbol bit y 7 , and the code bit bi 8 is used Assigned to the symbol bit y 1 〇, the code bit b2G is assigned to the symbol bit y 11, and the code bit b22 is assigned to the symbol bit y9.
將碼位元b!分配給符元位元y2〇, 將碼位元b3分配給符元位元y 12, 將碼位元b5分配給符元位元y 18, 將碼位元b7分配給符元位元y 13, 將碼位元b9分配給符元位元y 16, 將碼位元b n分配給符元位元y 17, 將碼位元b13分配給符元位元yi4, 將碼位元b! 5分配給符元位元y 1 5, 將碼位元b! 7分配給符元位元y 19, 將碼位元b ! 9分配給符元位元y 22, 將碼位元b2!分配給符元位元y23, 將碼位元b23分配給符元位元y21, 而進行替換。 此外,於圖 152,碼位元b〇,b2,b4,b6,b8,b10,b12,b14,b16,b18, 匕20 >22之替換模式及碼位元 bl,b3,b5, b2i,b23之替換模式兩者均與圖112A之碼位元bQ至bn之替換 -217- 135786.doc 200937872 模式一致。 圖153係表不LDPC碼是碼長>^為162〇〇位元、編碼率為 5/6之LDPC碼,進一步調變方式為4〇96QAM,倍數“2之 情況下之碼位元之替換例。 圖153之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖115A之碼位元之替換。因此, 圖153之碼位元之替換係按照圖114之分配規則。 LDPC碼是碼長>1為16200位元、編碼率為5/6iLDpc 〇 碼,進一步調變方式為4〇96QAM、倍數ba2之情況下,於 解多工器25,於縱行方向X橫列方向為(162〇〇/(12x2))x (12X2)位元之記憶體3 1寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) ° 替換部32係以將讀出自記憶體31212x2(=mb)位元之碼 位元bG至bu ’如圖153所示分配給連續之2(=b)個符元之 〇 12x2(=mb)位元之符元位元至力3之方式,來替換 12x2(=mb)位元之碼位元bQ至b23。 亦即,替換部32係分別 將碼位元bG分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y6, 將碼位元be分配給符元位元y 1, 將碼位元b8分配給符元位元y4, 將竭位元bi〇分配給符元位元ys ’ 135786.doc -218- 200937872 將碼位元b 12分配給符元位元y 2 ’ 將碼位元b〗4分配給符元位元y3, 將碼位元b16分配給符元位元y7, 將碼位元b!8分配給符元位元yio ’ 將碼位元b2G分配給符元位元y 11 ’ 將碼位元b22分配給符元位元y9 ’ 將碼位元b 1分配給符元位元y2〇 ’ 將碼位元b3分配給符元位元y 12 ’The code bit b! is assigned to the symbol bit y2, the code bit b3 is assigned to the symbol bit y 12, the code bit b5 is assigned to the symbol bit y 18, and the code bit b7 is assigned to The symbol bit y 13, assigns the code bit b9 to the symbol bit y 16, assigns the code bit bn to the symbol bit y 17, assigns the code bit b13 to the symbol bit yi4, and sets the code Bit b! 5 is assigned to symbol bit y 1 5, code bit b! 7 is assigned to symbol bit y 19, and code bit b ! 9 is assigned to symbol bit y 22, and code bit is assigned The element b2! is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in FIG. 152, the replacement modes of the code bits b〇, b2, b4, b6, b8, b10, b12, b14, b16, b18, 匕20 > 22 and the code bits bl, b3, b5, b2i, The replacement mode of b23 is consistent with the replacement of the code bits bQ to bn of Fig. 112A - 217 - 135786.doc 200937872 mode. Figure 153 shows that the LDPC code is an LDPC code with a code length of >^ of 162 bits and a coding rate of 5/6, and the modulation mode is 4〇96QAM, and the code bit of the case of the multiple "2" The replacement of the code bit in the case where the multiple b of Fig. 153 is 2 is directly replaced by the code bit of Fig. 115A in which only the multiple b is 1 is different. Therefore, the code bit of Fig. 153 The replacement is in accordance with the allocation rule of Fig. 114. The LDPC code is code length > 1 is 16200 bits, the coding rate is 5/6 iLDpc weight, and the further modulation mode is 4〇96QAM, multiples ba2, in the case of solution multiplexing The memory element 3 written in the memory direction 3 of the (162 〇〇 / (12x2)) x (12X2) bit in the wale direction X direction is in the course direction, with 12x2 (= mb) The bit unit is read and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 is configured to read the code bits bG to bu' from the memory 31212x2 (= mb) bits as shown in FIG. Replace the symbol bits of the 12x2 (= mb) bits bQ to b23 by assigning the symbol bits of the 〇 12x2 (= mb) bits of consecutive 2 (= b) symbols to the force 3 . That is, the replacement unit 32 respectively sets the code bit bG The allocation symbol bit y8 assigns the code bit b2 to the symbol bit y, assigns the code bit b4 to the symbol y6, and assigns the code bit be to the symbol y 1, and sets the code Bit b8 is assigned to symbol bit y4, and bit unit bi〇 is assigned to symbol bit ys ' 135786.doc -218- 200937872 assigning code bit b 12 to symbol bit y 2 ' The element b is assigned to the symbol bit y3, the code bit b16 is assigned to the symbol bit y7, and the code bit b!8 is assigned to the symbol bit yio '. The code bit b2G is assigned to the symbol bit The element y 11 ' assigns the code bit b22 to the symbol bit y9 ' assigns the code bit b 1 to the symbol bit y2 〇 ' assigns the code bit b3 to the symbol bit y 12 '
將碼位元bs分配給符元位元yi8, 將碼位元b7分配給符元位元)^3, 將碼位元b9分配給符元位元y 1.6, 將碼位元b 1 1分配給符元位元y丨7, 將碼位元1)彳3分配給符元位元y 14, 將碼位元b]5分配給符元位元y!5, 將瑪位元b 1 7分配給符元位元y丨9, 將碼位元b 1 9分配給符元位元y 22, 將碼位元b2 1分配給符元位元y23, 將碼位元b23分配給符元位元y21, 而進行替換。 此外’於圖 153 ’ 瑪位元b〇,b2,b4,b6,b8,bi〇,bi2,bi4,bi6,bi8, 匕〇山22之替換模式及碼位元bi,b3,b5,b7,b9,bn,bi3,bi5,bi7,bi9, b2i,b23之替換模式兩者均與圖U5A之碼位元^至…丨之替換 模式一致。 圖154係表示LDPC碼是碼長n為64800位元、編碼率為 135786.doc •219· 200937872 5/6之LDPC碼’進一步調變方式為4〇96qam,倍數b為2之 情況下之碼位元之替換例。 · 圖154之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖118A之碼位元之替換。因此, 圖154之碼位元之替換係按照圖117之分配規則。 LDPC碼是碼長N為64800位元、編碼率為5/6之LDPC 碼,進一步調變方式為4096QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(648〇〇/(12χ2))χ © (12x2)位元之記憶體31寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17) ° 替換部32係以將讀出自記憶體31i12x2(=mb)位元之碼 位元bG至by,如圖154所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元y()至μ之方式,來替換 12x2(=mb)位元之碼位元b〇至b23。 亦即,替換部32係分別 〇 將碼位元b〇分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y6, 將碼位元b6分配給符元位元y i, 將碼位元be分配給符元位元y4, 將碼位元bi〇分配給符元位元y5 ’ 將碼位元bi2分配給符元位元y2 ’ 將碼位元b14分配給符元位元y3, 135786.doc -220- 200937872 將碼位元b 16分配給符元位元y 7 ’ 將碼位元b18分配給符元位元丫10, 將碼位元b2Q分配給符元位元y!!, 將碼位元bn分配給符元位元y9 ’ 將碼位元b!分配給符元位元y20 ’ 將碼位元b3分配給符元位元y 12 ’ 將碼位元b5分配給符元位元y 18, 將碼位元b7分配給符元位元丫!3, 將碼位元b9分配給符元位元乃6, 將碼位元b 1 1分配給符元位元y丨7, 將碼位元b13分配給符元位元;^4, 將碼位元b15分配給符元位元y15, 將碼位元b 1 7分配給符元位元y丨9, 將碼位元b丨9分配給符元位元y 22, 將碼位元b21分配給符元位元723, 將碼位元b23分配給符元位元y21, 而進行替換。 此外’於圖 154,碼位元b0,b2,b4,b6,b8,b10,b12,bi4,bi6,b18, b2〇,b22之替換模式及碼位元 bi,b3,b5,b7,b9,bn,bi3,bi5,bi7,bi9, t>2i,b23之替換模式兩者均與圖n8A之碼位元b〇至bn之替換 模式一致。 圖155係表示LDPC碼是碼長N為16200位元、編碼率為 8/9之LDPC碼’進一步調變方式g4〇96QAM,倍數|^2之 情況下之碼位元之替換例。 135786.doc •221 - 200937872 圖1 55之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖121A之碼位元之替換。因此, 圖155之碼位元之替換係按照圖12〇之分配規則。 LDPC瑪是碼長N為16200位元、編碼率為8/9之LDpc 碼,進一步調變方式為4096QAM、倍數b*2之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(ι2χ2))χ (12x2)位元之s己憶體3 1寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31<12x2(=mb)位元之碼 位元b〇至bn ’如圖155所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元y〇至^之方式,來替換 12x2(=mb)位元之碼位元b〇至b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元7丨0, 將碼位元b2分配給符元位元y〇, 將碼位元分配給符元位元y!, 將碼位元be分配給符元位元y2, 將碼位元be分配給符元位元y3, 將碼位元b 1 〇分配給符元位元y 4, 將碼位元b 12分配給符元位元y 5, 將碼位元b丨4分配給符元位元y 6, 將碼位元bi6分配給符元位元ys, 將碼位元bi8分配給符元位元y7 ’ 135786.doc -222- 200937872 將碼位元b2G分配給符元位元y丨丨, 將碼位元b22分配給符元位元y9, 將碼位元bi分配給符元位元y22, 將碼位元b3分配給符元位元y, 2, 將碼位元b 5分配給符元位元y丨3, 將碼位元b7分配給符元位元714, 將碼位元bp分配給符元位元;/15, 將碼位元b 1〗分配給符元位元y i 6, ^ 將碼位元b 13分配給符元位元y 17, 將碼位元bi5分配給符元位元yu, 將碼位元b 17分配給符元位元y2〇, 將碼位元b!9分配給符元位元yi9, 將碼位元b2 1分配給符元位元y23, 將碼位元b23分配給符元位元y21, 而進行替換。 此外,於圖 155,碼位元 b2〇,b22之替換模式及碼位元 b2!,b23之替換模式兩者均與圖121A之碼位元“至!^〗之替換 模式一致。 圖156係表示LDPC碼是碼長N為64800位元、編碼率為 8/9之LDPC碼,進一步調變方式為4096QAM,倍數b為2之 情況下之碼位元之替換例。 圖156之倍數b為2之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖124A之碼位元之替換。因此, 135786.doc -223- 200937872 圖156之碼位元之替換係按照圖123之分配規則。 LDPC碼是碼長N為64800位元、編碼率為8/9之LDPC 碼,進一步調變方式為4〇96QAM、倍數1)為2之情況下,於 解多工器25,於縱行方向x橫列方向為(648〇〇/(12χ2))χ (12x2)位元之記憶體31寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、圖 17)。 替換部32係以將讀出自記憶體31之12X2(=mb)位元之碼 ❹ 位元%至b23 ’如圖156所示分配給連續之2(=1?)個符元之 12x2(=mb)位元之符元位元y()至μ之方式,來替換 12x2(=mb)位元之碼位元%至b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元丫1〇, 將碼位元b〗分配給符元位元y〇, 將瑪位元b4分配給符元位元yi, ©將碼位元b6分配給符元位元y2, 將碼位元b 8分配給符元位元y 3, 將碼位元b1Q分配給符元位元y4, 將瑪位元b 12分配給符元位元y 5 ’ 將碼位元b14分配給符元位元y6 ’ 將碼位元b 16分配給符元位元y8, 將碼位元b18分配給符元位元y7 ’ 將碼位元b2G分配給符元位元yu ’ 將碼位元b22分配給符元位元y9, 135786.doc •224- 200937872 將碼位元b 1分配給符元位元y22, 將碼位元b3分配給符元位元y 12, 將碼位元bs分配給符元位元y 13, 將碼位元b7分配給符元位元yi4, 將碼位元b9分配給符元位元y i 5, 將碼位元b 1 1分配給符元位元y丨6, 將碼位元bi3分配給符元位元丫17, 將碼位元bl5分配給符元位元y18,The code bit bs is assigned to the symbol bit yi8, the code bit b7 is assigned to the symbol bit)^3, the code bit b9 is assigned to the symbol bit y 1.6, and the code bit b 1 1 is assigned For the symbol bit y丨7, assign the code bit 1)彳3 to the symbol bit y14, and assign the code bit b]5 to the symbol bit y!5, and the mbit b 1 7 Assigned to the symbol bit y丨9, the code bit b 1 9 is assigned to the symbol bit y 22, the code bit b2 1 is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit Yuan y21, and replace it. In addition, in Fig. 153, the replacement pattern of the megabytes b, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, bi8, 匕〇山22 and the code bits bi, b3, b5, b7, The replacement modes of b9, bn, bi3, bi5, bi7, bi9, b2i, b23 are both identical to the replacement mode of the code bits ^ to ... of Figure U5A. Figure 154 is a diagram showing that the LDPC code is a code length n of 64,800 bits and an encoding rate of 135,786.doc • 219·200937872 5/6. The code is further modulated by 4〇96qam and the multiple b is 2. An alternative to a bit. The replacement of the code bits in the case where the multiple b of Fig. 154 is 2 is directly replaced by the code bits of Fig. 118A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 154 is in accordance with the allocation rule of FIG. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The direction is (648〇〇/(12χ2)) χ © (12x2) bit memory 31 is written in the horizontal direction, read in 12x2 (= mb) bit units, and supplied to the replacement Portion 32 (Fig. 16, Fig. 17) The replacing unit 32 assigns the code bits bG to by read from the memory 31i12x2 (= mb) bits to 2 consecutive (=b) as shown in FIG. The 12x2 (= mb) bit symbol y() to μ is replaced by the 12x2 (= mb) bit of the code bits b〇 to b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y6, respectively. The code bit b6 is assigned to the symbol bit yi, the code bit be be is assigned to the symbol bit y4, and the code bit bi is assigned to the symbol bit y5 '. The code bit bi2 is assigned to the symbol bit Element y2' assigns code bit b14 to symbol bit y3, 135786.doc -220- 200937872 assigns code bit b 16 to symbol bit y 7 ' assigns code bit b18 to symbol bit 丫10. Assign the code bit b2Q to the symbol bit y!!, assign the code bit bn to the symbol bit y9 ' Assign the code bit b! to the symbol bit y20 ' Assign the code bit b3 The symbol bit y 12 ' is assigned to the symbol bit y 18 and the code bit b7 is assigned to the symbol bit 丫! 3, the code bit b9 is assigned to the symbol bit 6 , the code bit b 1 1 is assigned to the symbol bit y 丨 7 , the code bit b13 is assigned to the symbol bit ; ^ 4 , the code Bit b15 is assigned to symbol bit y15, code bit b 1 7 is assigned to symbol bit y丨9, code bit b丨9 is assigned to symbol bit y 22, and code bit b21 is assigned To the symbol bit 723, the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in Figure 154, the replacement modes of the code bits b0, b2, b4, b6, b8, b10, b12, bi4, bi6, b18, b2, b22 and the code bits bi, b3, b5, b7, b9, The replacement modes of bn, bi3, bi5, bi7, bi9, t> 2i, b23 are both identical to the replacement mode of the code bits b 到 b of Figure n8A. Figure 155 is a diagram showing an alternative example of the code bit in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and further modulation mode g4 〇 96QAM, multiples |^2. 135786.doc •221 - 200937872 The replacement of the code bits in the case where the multiple b of the Fig. 1 is 2 is directly used. The replacement of the code bits of Fig. 121A differing only by the point that the multiple b is 1. Therefore, the replacement of the code bits of Fig. 155 is in accordance with the distribution rule of Fig. 12. LDPC is an LDpc code with a code length N of 16200 bits and a coding rate of 8/9. In the case where the modulation mode is 4096QAM and multiples b*2, the multiplexer 25 is in the traverse direction x course. The code bit in the direction of (162〇〇/(ι2χ2))χ(12x2) bits is written in the horizontal direction, read in 12x2 (=mb) bit units, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to bn ' read from the memory 31 < 12x2 (= mb) bits to 12x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bitwise symbol y〇 to ^ of the bit is substituted for the 12x2 (= mb) bit of the code bit b〇 to b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 7丨0, the code bit b2 to the symbol bit y〇, and the code bit to the symbol bit y! , the code bit be be assigned to the symbol bit y2, the code bit be be assigned to the symbol bit y3, the code bit b 1 〇 to the symbol bit y 4 , and the code bit b 12 to be allocated The symbol bit y 5 is assigned, the code bit b 丨 4 is assigned to the symbol y y 6, the code bit bi6 is assigned to the symbol ys, and the code bit bi8 is assigned to the symbol y7 ' 135786.doc -222- 200937872 assigning the code bit b2G to the symbol bit y丨丨, assigning the code bit b22 to the symbol bit y9, and assigning the code bit bi to the symbol bit y22, the code Bit b3 is assigned to symbol bit y, 2, code bit b 5 is assigned to symbol bit y 丨 3, code bit b7 is assigned to symbol bit 714, and code bit bp is assigned to symbol Meta-bit; /15, assigning code bit b 1 to symbol bit yi 6, ^ assigning code bit b 13 to symbol bit y 17, assigning code bit bi5 to symbol bit Yu, assign the code bit b 17 to the symbol bit y2 〇, and assign the code bit b! 9 to Yuan bit yi9, the code bit b2 1 assigned to the symbol bit y23, the code bit b23 to the assigned symbol bit y21, and replaced. In addition, in FIG. 155, the replacement mode of the code bits b2, b22 and the replacement mode of the code bits b2!, b23 are both identical to the replacement mode of the code bit "to!" of FIG. 121A. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and an alternative example of the code bit in the case where the modulation is 4096QAM and the multiple b is 2. The multiple b of FIG. The replacement of the code bits in the case of 2 is directly replaced by the code bits of Fig. 124A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 156 of 135786.doc -223- 200937872 According to the allocation rule of Fig. 123. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 8/9, and further modulation is 4〇96QAM, and the multiple 1) is 2, in the case of multiplex multiplexing The memory element written in the memory 31 of the (648 〇〇 / (12 χ 2)) χ (12 x 2) bit in the wx direction x direction is in the course direction, with 12x2 (= mb) bits. The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to read the code from the 12X2 (= mb) bits of the memory 31 to the bit number B2' as shown in Fig. 156. Place Replace the symbol bits y() to μ of 12x2 (= mb) bits of consecutive 2 (=1?) symbols to replace the code bits % to b23 of 12x2 (= mb) bits That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 丫1〇, the code bit b to the symbol bit y〇, and the mbit b4 to the symbol bit. Yuan yi, © assigns code bit b6 to symbol bit y2, assigns code bit b 8 to symbol bit y 3 , assigns code bit b1Q to symbol bit y4 , and converts bit b 12 is assigned to the symbol bit y 5 '. The code bit b14 is assigned to the symbol bit y6 '. The code bit b 16 is assigned to the symbol bit y8, and the code bit b18 is assigned to the symbol bit y7 ' Assigning code bit b2G to symbol bit yu ' assigning code bit b22 to symbol bit y9, 135786.doc • 224- 200937872 assigning code bit b 1 to symbol bit y22, the code bit The element b3 is assigned to the symbol bit y 12, the code bit bs is assigned to the symbol bit y 13, the code bit b7 is assigned to the symbol bit yi4, and the code bit b9 is assigned to the symbol bit yi 5, the code bit b 1 1 is assigned to the symbol bit y 丨 6 , the code bit bi 3 To the symbol bit Ah 17, the code bits allocated to the symbol bits bl5 Y18,
Ο 將碼位元b〗7分配給符元位元y2〇, 將瑪位元卜9分配給符元位元y19 , 將碼位元b2〗分配給符元位元y23, 將碼位元t>23分配給符元位元y2i, 而進行替換。 此外,於圖 156,碼位元b〇b2,b4,b6,b8,bi(),bi2,bi4,bi6,b^, b20,b22之替換模式及碼位元bib3,b5,b7,b9,bii,bi3,bi5,b”,bi9, bz〗’b23之替換模式兩者均與圖124a之碼位元〜至bi丨之替換 模式一致。 圖157係表不LDPC碼是碼長⑽648〇〇位&、編碼率為 9/10之LDPC碼,進—步調變方式為4〇96qam,倍數以2 之情況下之碼位元之替換例。 圖157之倍數…之情況下之碼位元之替換係直接利用 僅有倍數b為1之點不同之圖127a之碼位^之替換。因此, 圖157之碼位元之替換係按照圖m之分配規則。 LDPC碼是碼長以6侧位元、編碼率為咖之· 135786.doc •225- 200937872 碼,進一步調變方式為4096QAM、倍數b為2之情況下,於 解多工器25 ’於縱行方向X橫列方向為(648〇〇/(ΐ2χ2))χ (12X2)位元之δ己憶體3 1寫入之碼位元係於橫列方向,以 12x2(=mb)位元單位讀出,並供給至替換部32(圖16、 17)。 替換部32係以將讀出自記憶體^之^心卜^…位元之碼 位元b〇至bn,如圖157所示分配給連續之2(=b)個符元之 12x2(=mb)位元之符元位元y〇至yu之方式,來替換 12x2(=mb)位元之碼位元bG至b23。 亦即,替換部32係分別 將碼位元b〇分配給符元位元y 1 〇, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y丨, 將碼位元b6分配給符元位元y2, 將碼位元b8分配給符元位元y3, 將碼位元biG分配給符元位元y4, 將碼位元b!2分配給符元位元y5, 將碼位元bi4分配給符元位元y6, 將碼位元b 16分配給符元位元y 8, 將碼位元bis分配給符元位元y7, 將碼位元b2G分配給符元位元y 11, 將碼位元b22分配給符元位元y9, 將碼位元bi分配給符元位元y22, 將碼位元b〗分配給符元位元yi2, 135786.doc -226- 200937872 將碼位元b 5分配給符元位元y 13, 將碼位元b7分配給符元位元yi4, 將碼位元bg分配給符元位元y 15, 將碼位元b 11分配給符元位元y丨6, 將碼位元b 13分配給符元位元y丨7, 將碼位元bis分配給符元位元yis, 將碼位元b 17分配給符元位元y20, 將碼位元bi9分配給符元位元)^9,分配 Assign code bit b 7 to symbol y2 〇, assign mega element 9 to symbol y19, assign code bit b2 to symbol y23, and code bit t> ; 23 is assigned to the symbol y2i, and is replaced. In addition, in FIG. 156, the replacement modes of the code bits b〇b2, b4, b6, b8, bi(), bi2, bi4, bi6, b^, b20, b22 and the code bits bib3, b5, b7, b9, Bii, bi3, bi5, b", bi9, bz] The replacement mode of 'b23' is identical to the replacement mode of the code bit to the bi丨 of Fig. 124a. Fig. 157 shows that the LDPC code is code length (10) 648〇〇 Bit &, LDPC code with a coding rate of 9/10, an alternative to the code bit in the case where the step modulation is 4〇96qam, and the multiple is 2. The code bit in the case of the multiple of Fig. 157 The replacement is directly replaced by the code bit of Fig. 127a in which only the multiple b is 1 is different. Therefore, the replacement of the code bit of Fig. 157 is in accordance with the allocation rule of Fig. m. The LDPC code is the code length of 6 sides. The bit and coding rate are 135786.doc • 225- 200937872 code. If the modulation method is 4096QAM and the multiple b is 2, the X-direction of the multiplexer 25' in the wale direction is ( 648〇〇/(ΐ2χ2))χ (12X2) bit δ mnemonic 3 1 written code bits are in the horizontal direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit 32 (Figures 16, 17). The replacing unit 32 is configured to allocate the code bits b to bn read from the memory of the memory to the bn, as shown in FIG. 157, to 12x2 (= mb) of consecutive 2 (=b) symbols. The bit elements y〇 to yu of the bit are replaced by the code bits bG to b23 of the 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol respectively. Bit y 1 〇, assign code bit b2 to symbol bit y 〇, assign code bit b4 to symbol y 丨, assign code bit b6 to symbol y2, place code bit The element b8 is assigned to the symbol bit y3, the code bit biG is assigned to the symbol bit y4, the code bit b!2 is assigned to the symbol bit y5, and the code bit bi4 is assigned to the symbol bit y6. , the code bit b 16 is assigned to the symbol bit y 8, the code bit bis is assigned to the symbol bit y7, the code bit b2G is assigned to the symbol bit y 11, and the code bit b22 is assigned to The symbol bit y9 assigns the code bit bi to the symbol bit y22, and assigns the code bit b to the symbol bit yi2, 135786.doc -226- 200937872 assigns the code bit b 5 to the symbol Bit y 13, assigning code bit b7 to symbol bit yi4, assigning code bit bg The symbol bit y 15, assigns the code bit b 11 to the symbol y 丨 6 , assigns the code bit b 13 to the symbol y 丨 7 , and assigns the code bis to the symbol Yis, assigning the code bit b 17 to the symbol bit y20, and assigning the code bit bi9 to the symbol bit) ^9,
將碼位元b〗1分配給符元位元y23, 將碼位元b〗3分配給符元位元y21, 而進行替換。 此外,於圖 157,碼位元 b0,b2,b4,b6,b8,bi〇,b12,b〗4,b16,b18, b2〇,b22之替換模式及碼位元 b丨,b3,b5,b7,b9,bi i,bi3,bi5,b17,b19, b2i,b>23之替換模式兩者均與圖127A之碼位元b〇至bu之替換 模式一致。 圖158至圖101係表示利用圖136至圖157所示之倍數匕為】 之情況下之替換,進行倍數b為2之情況下之替換之進行新 替換方式之替換處理所獲得之BER之模擬之結果。 亦即,圖158係表示將碼長μ 162〇〇、編碼率為2。、 3/4、3/5、5/6、8/9分別之LDPC瑪作為對象 式採用1024QAM之情況下之BEr。 : 圖159係表示將碼長ν為64800、始_ « 3/5、5/6、8/9、9/10分別之 LDPC碼作為 42/3、3/4、 式採用1024QAM之情況下之BER。 、象,作為調變方 135786.doc -227- 200937872 圖160係表示將碼長N為162〇0、編碼率為2/3、3/4 3/5、5/6、8/9分別之LDPC碼作為對象,作為調變方式採 用4096QAM之情況下之BER。 圖161係表示將瑪長N為64800、編竭率為2/3、3/4、 3/5、5/6、8/9、9/10分別之LDPC碼作為對象,作為調變方 式採用4096QAM之情況下之BER。 於圖158至圖161,與圖130至圖133相同,橫轴表示 Es/N〇 ’縱軸表示BER。而且’實線表示已進行新替換方式 〇 之替換處理之情況下之BER,點線表示未進行替換處理之 情況下之BER。 從圖158至圖161,新替換方式之替換處理係比較起未進 行替換處理之情況,其BER提升,因此可知對於錯誤之对 受性提升》 接著’圖162係表示圖7之接收裝置12之結構例之區塊 圖》 φ 於圖162,接收裝置12係接收來自發送裝置u(圖7)之調 變信號之資料處理裝置,由正交解調部51、解映射部52、 反交錯器53及LDPC解碼部56所構成。 正交解調部51係接收來自發送裝置u之調變信號,進行 正交解調,將其結果所獲得之信號點(1及(^軸方向分別之 值)供給至解映射部52。 解映射部52係進行使來自正交解調部51之信號點,成為 LDPC碼之碼位元經符元化之符元之解映射,並供給至反 交錯器53。 135786.doc -228- 200937872 反交錯器53係由多工器(MUX)54及縱行扭轉反交錯器55 所構成,進行來自解映射部52之符元之符元位元之反交 錯。 Ο ❹ 亦即,多工器54係將來自解映射部52之符元之符元位元 作為對象,進行對應於圖8之解多工器25所進行之替換處 理之反替換處理(替換處理之逆向處理),亦即進行使藉由 替換處理所替換之LDPC碼之碼位元(符元位元)之位置回到 原本位置之反替換處理,將其結果所獲得之LDPC碼供給 至縱行扭轉反交錯器55。 縱行扭轉反交錯器55係將來自多工器54之LDPC碼作為 對象,進行對應於圖8之縱行扭轉交錯器24所進行之作為 重排處理之縱行扭轉交錯之縱行扭轉反交錯(縱行扭轉交 錯之逆向處理),亦即進行作為使藉由作為重排處理之縱 行扭轉交錯而變更排列之LDPC碼之碼位元,回到原本排 列之反重排處理之例如縱行扭轉反交錯。 具體而言,縱行扭轉反交錯器55係藉由對於與圖。等所 不之記憶體31同樣地構成之反交錯用之記憶體,寫入 LDPC碼之碼位元並進—步讀丨,以進行縱行扭轉反交 錯。 其中’於縱行扭轉反交錯器55’碼位元之寫入係將來自 記憶體31之碼位元之讀㈣之讀出位址,作為寫入位址利 用,於反交錯用之記憶體之橫列方向進行。 一 之讀出係將對記憶體31之碼位元之寫 碼位70 达社1/ 〈寫入位址,作 η立址利用,於反交錯用之記憶體之縱行方向進行。 135786.doc •229· 200937872 縱行扭轉反交錯之結果所獲得之LDPC碼係從縱行扭轉 反交錯器55供給至LDPC解碼部56。 於此’於從解映射部52供給至反交錯器53iLDPC碼, 同位交錯、縱行扭轉交錯及替換處理係以該順序施以,但 於反交錯器53,僅進行對應於替換處理之反替換處理及對 應於縱行扭轉交錯之縱行扭轉反交錯,因此未進行對應於 同位交錯之同位反交錯(同位交錯之逆向處理),亦即未進 行使藉由同位交錯而變更排列之LDPC碼之碼位元回到原 本排列之同位反交錯。 因此’從反交錯器53(之縱行扭轉反交錯器55),對LDPC 解碼部56供給有已進行反替換處理及縱行扭轉反交錯,且 未進行同位反交錯之LDPC碼。 LDPC解碼部56係利用對於圖8之LDPC編碼部21用於 LDPC編碼之檢查矩陣H,至少進行相當於同位交錯之行置 換所獲得之轉換檢查矩陣,來進行來自反交錯器53之 LDPC碼之LDPC解碼,並將其結果所獲得之資料,作為對 象資料之解碼結果輸出。 圖163係說明圖162之接收裝置12所進行之接收處理之流 程圖。 正交解調部51係於步驟8111,接收來自發送裝置u之調 變信號’處理係前進至步驟SU2,進行該調變信號之正交 解調。正交解調部51係將正交解調之結果所獲得之信號點 供給至解映射部52,處理係從步驟S112前進至步驟S113。 於步驟S113 ’解映射部52係進行使來自正交解調部51之 135786.doc 200937872 信號點成為符元之解映射,並供給至反交錯器53,處理係 前進至步驟S114。 於步驟S114,反交錯器53係進行來自解映射部52之符元 之符元位元之反交錯,處理係前進至步驟S115。 亦即’於步驟S114,於反交錯器53,多工器54將來自解 映射部52之符元之符元位元作為對象,進行反替換處理, 將其結果所獲得之LDPC碼之碼位元供給至縱行扭轉反交 錯器55。 縱行扭轉反交錯器55係將來自多工器54之LDPC碼作為 對象’進行縱行扭轉反交錯,並將其結果所獲得之LDPC 碼供給至LDPC解碼部56。 於步驟S115,LDPC解碼部56係利用對於圖8之LDPC編 碼部21用於LDPC編碼之檢查矩陣Η,至少進行相當於同位 交錯之行置換所獲得之轉換檢查矩陣,來進行來自縱行扭 轉反交錯器55之LDPC碼之LDPC解碼,並將其結果所獲得 之資料’作為對象資料之解碼結果輸出,處理終了。 此外’圖163之接收處理係重複進行。 而且,圖162亦與圖8之情況相同,為了便於說明,個別 地構成進行反替換處理之多工器54及進行縱行扭轉反交錯 之縱行扭轉反交錯器55,但多工器5 4與縱行扭轉反交錯器 55亦可—體地構成。 進—步而言,於圖8之發送裝置u不進行縱行扭轉交錯 之If况下,於圖162之接收裝置12無須設置縱行扭轉反交 錯器55。 135786.doc •231 · 200937872 接著’進一步說明關於圖162之LDPC解碼部56所進行之 LDPC解碼。 於圖162之LDPC解碼部56,如上述,利用對於圖8之 LDPC編碼部21用於LDPC編碼之檢查矩陣η,至少進行相 當於同位交錯之行置換所獲得之轉換檢查矩陣,來進行來 自縱行扭轉反交錯器55之進行反替換處理及縱行扭轉反交 錯、且未進行同位反交錯之LDPC碼之LDPC解碼。 ❹The code bit b 1 is assigned to the symbol bit y23, and the code bit b 3 is assigned to the symbol bit y21 for replacement. In addition, in FIG. 157, the replacement modes of the code bits b0, b2, b4, b6, b8, bi, b12, b, 4, b16, b18, b2, and b22 and the code bits b丨, b3, b5, The replacement modes of b7, b9, bi i, bi3, bi5, b17, b19, b2i, b > 23 are both identical to the replacement mode of the code bits b 〇 to bu of Fig. 127A. 158 to 101 show the BER simulation obtained by replacing the case where the multiple 匕 is shown in FIG. 136 to FIG. 157, and replacing the new replacement method in the case where the multiple b is 2 The result. That is, Fig. 158 shows a code length μ 162 〇〇 and a coding rate of 2. LDPC, which is 3/4, 3/5, 5/6, and 8/9, respectively, is a BEr in the case of 1024QAM. : Figure 159 shows the case where the code length ν is 64800, the LDPC codes of the first _ « 3/5, 5/6, 8/9, and 9/10 are used as 42/3, 3/4, and 1024QAM is used. BER. , image, as a modulation side 135786.doc -227- 200937872 Figure 160 shows that the code length N is 162 〇 0, the coding rate is 2/3, 3/4 3/5, 5/6, 8/9 respectively The LDPC code is used as the object, and the BER in the case of 4096QAM is used as the modulation method. Figure 161 shows an LDPC code with a length of 64800 and a compilation rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10 as the modulation method. BER in the case of 4096QAM. In Figs. 158 to 161, the same as Figs. 130 to 133, the horizontal axis represents the Es/N 〇 ’ vertical axis represents the BER. Further, the 'solid line indicates the BER in the case where the replacement method of the new replacement method has been performed, and the dotted line indicates the BER in the case where the replacement processing is not performed. From FIG. 158 to FIG. 161, the replacement processing of the new alternative is compared with the case where the replacement processing is not performed, and the BER is increased, so that the improvement of the error is recognized. Next, FIG. 162 shows the receiving device 12 of FIG. Block diagram of the configuration example φ In Fig. 162, the receiving device 12 receives the modulated signal from the transmitting device u (Fig. 7), and the orthogonal demodulating unit 51, the demapping unit 52, and the de-interlacer 53 and LDPC decoding unit 56 are configured. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device u, performs quadrature demodulation, and supplies the signal points (1 and (the values in the ^-axis directions) obtained as a result to the demapping unit 52. The mapping unit 52 performs demapping of the symbol points from the orthogonal demodulation unit 51 into symbolized symbols of the LDPC code, and supplies them to the deinterleaver 53. 135786.doc -228- 200937872 The deinterleaver 53 is composed of a multiplexer (MUX) 54 and a vertical twist deinterleaver 55, and performs deinterlacing of the symbol bits from the symbols of the demapping unit 52. Ο ❹, that is, a multiplexer In the 54th, the symbol bit from the symbol of the demapping unit 52 is used as an object, and the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing by the multiplexer 25 of FIG. 8 is performed, that is, The LDPC code obtained as a result of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement processing to the original position is supplied to the vertical twist reverse deinterleaver 55. The line twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as an object. The row corresponds to the longitudinal twist reverse staggering (the reverse processing of the longitudinal twist interlacing) performed by the longitudinal twist interleaver 24 of FIG. 8 as a rearrangement process, that is, as a rearrangement The processing is performed by twisting and interleaving to change the code bits of the aligned LDPC code, and returning to the inverse arrangement of the original arrangement, for example, the longitudinal twist de-interlacing. Specifically, the longitudinal torsional de-interlacer 55 is In the same way, the memory 31 is configured to be a memory for deinterleaving, and is written into the code bit of the LDPC code and read-by-step to perform the wandering de-interlacing. The writing of the 55' code bit is performed by using the read address of the read bit (4) of the code bit from the memory 31 as the write address, and in the course direction of the memory for deinterleaving. The reading system will write the code bit 70 of the code bit of the memory 31 to the address 1/<write address, and use it for the η address, in the longitudinal direction of the memory for deinterleaving. 135786.doc • 229· 200937872 LDPC code obtained by the result of longitudinal twist deinterlacing The vertical twist reverse deinterleaver 55 supplies the LDPC decoding unit 56 to the LDPC decoding unit 56. Here, the eigen-interleaving, the wobble interleave, and the replacement processing are applied in this order from the demapping unit 52 to the de-interlacer 53iLDPC code. In the deinterleaver 53, only the inverse replacement processing corresponding to the replacement processing and the vertical torsional deinterlacing corresponding to the longitudinal torsional interleaving are performed, so that the in-phase deinterlacing corresponding to the co-located interleaving (the inverse processing of the co-located interleaving) is not performed. That is, the parity bit of the LDPC code whose alignment is changed by the co-located interleaving is returned to the co-interleave of the original arrangement. Therefore, the 'de-interleaver 53 (the whirling torsional de-interleaver 55) is applied to the LDPC decoding unit 56. An LDPC code having undergone anti-replacement processing and directional twist de-interlacing, and not performing co-located de-interlacing is supplied. The LDPC decoding unit 56 performs the LDPC code from the deinterleaver 53 by performing at least the conversion check matrix obtained by the LDPC encoding of the LDPC encoding unit 21 of FIG. The LDPC decodes and outputs the data obtained as a result of the decoding of the target data. Figure 163 is a flow chart showing the reception processing performed by the receiving device 12 of Figure 162. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device u in step 8111, and proceeds to step SU2 to perform orthogonal demodulation of the modulated signal. The orthogonal demodulation unit 51 supplies the signal point obtained as a result of the orthogonal demodulation to the demapping unit 52, and the processing proceeds from step S112 to step S113. In step S113, the demapping unit 52 performs demapping of the 135786.doc 200937872 signal point from the orthogonal demodulation unit 51 into a symbol, and supplies it to the deinterleaver 53, and the processing proceeds to step S114. In step S114, the deinterleaver 53 performs deinterlacing of the symbol bits from the symbols of the demapping section 52, and the processing proceeds to step S115. That is, in step S114, in the deinterleaver 53, the multiplexer 54 takes the symbol bit from the symbol of the demapping section 52 as an object, performs inverse replacement processing, and obtains the code position of the LDPC code obtained as a result. The element is supplied to the longitudinal twist reverse deinterlacer 55. The whirling torsional deinterleaver 55 performs the wraparound deinterleaving of the LDPC code from the multiplexer 54 as a target, and supplies the LDPC code obtained as a result to the LDPC decoding unit 56. In step S115, the LDPC decoding unit 56 performs at least the conversion check matrix obtained by the row replacement of the parity interleave by using the check matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of FIG. The LDPC decoding of the LDPC code of the interleaver 55, and the data obtained as a result of the result is output as the decoding result of the object data, and the processing ends. Further, the reception processing of Fig. 163 is repeated. Further, Fig. 162 is also the same as the case of Fig. 8. For convenience of explanation, the multiplexer 54 for performing the reverse replacement process and the reticular reverse deinterleaver 55 for performing the slant reverse twisting are separately formed, but the multiplexer 5 4 The longitudinal torsional deinterlacer 55 can also be constructed integrally. Further, in the case where the transmitting device u of Fig. 8 does not perform the wobble interleaving, the receiving device 12 of Fig. 162 does not need to provide the whirling reverse anti-interlacer 55. 135786.doc • 231 · 200937872 Next, the LDPC decoding performed by the LDPC decoding unit 56 of Fig. 162 is further explained. As described above, the LDPC decoding unit 56 of FIG. 162 performs at least the conversion check matrix obtained by the row interleave replacement for the LDPC encoding check matrix η of the LDPC encoding unit 21 of FIG. The LDPC decoding of the LDPC code of the twist reverse deinterleaver 55 is performed by the inverse replacement processing and the diagonal twist deinterleave, and the eccentric deinterlacing is not performed. ❹
於此,一種LDPC解碼先已提案,其藉由利用轉換檢查 矩陣來進行LDPC解碼,可抑制電路規模,同時將動作頻 率壓低在充分可實現之範圍(參考例如日本特開2004-343170號公報)。 因此’首先參考圖164至圖167,來說明關於先被提案之 利用轉換檢查矩陣之LDPC解碼。 圖164係表示碼長N為90、編碼率為2/3之LDPC碼之檢查 矩陣Η之例。 此外,於圖164(於後述之圖165及圖166亦相同)以句點 (.)來表現0。 於圖164之檢查矩陣Η,同位矩陣成為階梯構造。 圖165係表示於圖164之檢查矩陣Η,施以式(11)之列置 換及式(12)之行置換所獲得之檢查矩陣Η·。 列置換:6s+t+第1列—5t+s+第1列 .· ·(11) 行置換:6x+y+第 61 行—>5y+x+第 61 行 · · .(12) 其中,於式(11)及(12),s、t、X、y分別為〇$s<5、 〇St<6、0Sx<5、0St<6之範圍之整數。 135786.doc -232- 200937872 若根據式(11)之列置換,以下述情形進行置換:除以6 餘數為1之第1、7、13、19、25列分別置換為第1、2、3、 4、5列,除以6餘數為2之第2、8、14、20、26列分別置換 為第6、7、8、9、10列。 而且,若根據式(12)之行置換,對於第61行以後(同位矩 陣)’以下述情形進行置換:除以6餘數為1之第61、67、 73、79、85行分別置換為第61、62、63 ' 64、65行,除以 6餘數為2之第62、68、74、80、86行分別置換為第66、 ❹ 67 、 68 、 69 、 70行。 如此,對於圖164之檢查矩陣Η進行列與行之置換所獲得 之矩陣(matrix)為圖165之檢查矩陣Η'。 於此’即使進行檢查矩陣Η之列置換,仍不會影響ldpc 碼之碼位元之排列。 而且,式(12)之行置換係相當於將上述第K+qx+y+1個碼 位兀交錯至第K+Py+X+1個碼位元之位置之同位交錯之分 〇 別設資訊長K為60、巡迴構造之單位之行數p為5及同位長 M(於此為30)之約數9(=]^/1>)為6時之同位交錯。 若對於圖165之檢查矩陣(以下適宜地稱為置換檢查矩 陣)H’’㈣於圖164之檢查輯(以下適宜地稱為原本之檢 查矩陣)H之LDPC碼進行與式(12)同一置換後之矩陣,則輸 出0向量。#即,若於作為原本之檢查矩陣^之匕別c碼P 碼字)之列向量C’⑯以式(12)之行置換所獲得之列向量表 示作c’,則從檢查矩陣之性質來看,HcT成為。向量,因此 H'c'T亦當然成為〇向量。 135786.doc •233- 200937872 根據以上,圖165之轉換檢查矩陣Η,係於原本之檢查矩 陣Η之LDPC碼c,進行式(12)之行置換所獲得之LDPC碼c· 之檢查矩陣。 因此’於原本之檢查矩陣Η之LDPC碼c,進行式(12)之 行置換,利用圖165之轉換檢查矩陣H·,將該行置換後之 LDPC碼c'解碼(LDPC解碼),於該解碼結果施以式(12)之行 置換之反置換,藉此可獲得將原本之檢查矩陣Η之LDPC碼 利用該檢査矩陣Η予以解碼之情況同樣之解碼結果。 圖166係表示以5x5之矩陣為單位隔著間隔之圖165之轉 換檢查矩陣Η·。 於圖166,轉換檢查矩陣η,係以下述矩陣之組合來表 示· 5><5之單位矩陣;該單位矩陣之1之中有1個以上為〇之 矩陣(以下適宜地稱為準單位矩陣);單位矩陣或準單位矩 陣經循環移位(cyclic shift)之矩陣(以下適宜地稱為移位矩 陣);單位矩陣、準單位矩陣或移位矩陣中之2以上之和(以 下適宜地稱為和矩陣);及5x5之0矩陣》 圖166之轉換檢查矩陣η,可由5x5之單位矩陣準單位矩 陣、移位矩陣、和矩陣及〇矩陣來構成。因此,構成轉換 檢查矩陣H,之該等5x5之矩陣以下適宜地稱為構成矩陣。 於由Pxp之構成矩陣所表示之檢查矩陣所表示之LDPC碼 之解碼,可利用P個同時進行校驗節點運算及可變節點運 算之架構(architecture)。 圖167係表示進行該類解碼之解碼裝置之結構例之區塊 135786.doc -234· 200937872 亦即,圖167係表示利用對於圖164之原本之檢查矩陣 H,至少進行式(12)之行置換所獲得之圖166之轉換檢查矩 陣H’,來進行LDPC碼之解碼之解碼裝置之結構例。 圖167之解碼裝置包含:由6個FIF〇 3〇〇1至3〇〇6所組成之 分枝資料儲存用記憶體3〇〇、選擇FIF〇 3〇〇1至3〇〇6之選擇 器301、校驗節點計算部302、2個循環移位電路3〇3及 308、由18個FIFO 304丨至304〗8所組成之分枝資料儲存用記 憶體304、選擇FIF〇 3〇4丨至3〇4ls之選擇器305、儲存接收 資訊之接收資料用記憶體3〇6、可變節點計算部3〇7、解碼 字計算部309、接收資料重排部3 1〇及解碼資料重排部 311 〇 首先’說明關於對分枝資料儲存用記憶體3〇〇及3〇4之資 料儲存方法。 分枝資料儲存用記憶體3〇〇係由將圖166之轉換檢查矩陣 H’之列數30 ’以構成矩陣之列數5除算後之數即6個fif〇 ❿ 300丨至30〇6所構成。FIFO 300y(y=l,2, · · ·,6)係由複數段 數之記憶區域所組成,各段數之記憶區域可同時讀出或寫 入對應於構成矩陣之列數及行數之5個分枝之訊息。而 且’ FIFO 300yi記憶區域之段數為圖166之轉換檢查矩陣 之列方向之1之數目(漢明權重)之最大數即9。 於FIFO 300丨,對應於圖166之轉換檢査矩陣比之第i列至 第5列之1之位置之資料(來自可變節點之訊息心)係儲存為 各列均往橫向填塞之形式(以忽視〇之形式)。亦即,若將第 j列第i行表示作(j,i),則於FIF〇 300,之第1段記憶區域,儲 135786.doc -235- 200937872 存有對應於轉換檢查矩陣Η,從(ι,ι)至(5,5)之5x5之單位矩 陣之1之位置之資料。於第2段記憶區域,儲存有對應於轉 換檢查矩陣Η'從(1,21)至(5,25)之移位矩陣(將5χ5之單位矩 陣往右方僅循環移位3個後之移位矩陣)之丨之位置之資 料。從第3至第8段記憶區域亦同樣與轉換檢查矩陣Η,賦予 對應而儲存有資料。然後,第9段記憶區域,儲存有對應 於轉換檢查矩陣Η,從(1,86)至(5,90)之移位矩陣(將5χ5之單 位矩陣中之第1列之1置換為0,並往左僅循環移位i個後之 移位矩陣)之1之位置之資料。 於FIFO 30〇2,儲存有對應於圖166之轉換檢_查矩陣η'之 第6列至第1 〇列之1之位置之資料。亦即,於FIF〇 3〇〇2之 第1段5己憶區域,儲存有對應於構成轉換檢查矩陣從 (6,1)至(1〇,5)之和矩陣(將5χ5之單位矩陣往右僅循環移位1 個之第1移位矩陣、與將單位矩陣往右僅循環移位2個之第 2移位矩陣之和之和矩陣)之第1移位矩陣之1之位置之資 料。而且,第2段記憶區域,儲存有對應於構成轉換檢查 矩陣H’從(6,1)至(1〇,5)之和矩陣之第2移位矩陣之I之位置 之資料。 亦即’關於權重為2以上之構成矩陣,以權重為1之pxp 之單位矩陣、其要素之1之中有1個以上為〇之準單位矩 陣、或將單位矩陣或準單位矩陣予以循環移位後之移位矩 陣中複數個之和之形式表現該構成矩陣時,對應於該權重 為1之單位矩陣、準單位矩陣或移位矩陣之1之位置之資料 (對應於屬於單位矩陣、準單位矩陣或移位矩陣之分枝之 135786.doc -236- 200937872 訊息)係儲存於同一位址(FIFO 30〇ι至30〇6中之同一 FIFO)。 以下,關於從第3至第9段記憶區域’亦與轉換檢查矩陣 H'賦予對應而儲存有資料。 FIFO 30〇3至3〇〇6亦同樣與轉換檢查矩陣11,賦予對應而储 存有資料。 分枝資料儲存用記憶體304係由以構成矩陣之行數即5, 除以轉換檢查矩陣H,之行數90後之18個FIFO 30七至30418 〇 所構成。FIFO 304x(x=l,2, ···,18)係由複數段數之記憶 區域所組成’於各段之記憶區域可同時讀出或寫入對應於 轉換檢查矩陣H,之列數及行數之5個分枝之訊息。 於FIFO 304丨,對應於圖166之轉換檢查矩陣H'之第1行至 第5行之1之位置之資料(來自校驗節點之訊息係儲存為 各行均往縱向填塞之形式(以忽視〇之形式)。亦即,於 FIFO 304丨之第1段記憶區域,儲存有對應於轉換檢查矩陣 q H’從G,1)至(5,5)之5X5之單位矩陣之1之位置之資料。於第 2段記憶區域,儲存有對應於構成轉換檢查矩陣H,從 至(1 0,5)之和矩陣(將5x5之單位矩陣往右僅循環移位!個之 第1移位矩陣、與將單位矩陣往右僅循環移位2個之第2移 位矩陣之和之和矩陣)之第1移位矩陣之1之位置之資料。 而且,第3段記憶區域,儲存有對應於構成轉換檢查矩陣 H’從(6,1)至(1〇,5)之和矩陣之第2移位矩陣之〗之位置之資 料》 亦即,關於權重為2以上之構成矩陣,以權重為iipxp 135786.doc •237- 200937872 之單位矩陣、其要素之1之中有1個以上為0之準單位矩 陣、或將單位矩陣或準單位矩陣予以循環移位後之移位矩 陣中複數個之和之形式表現該構成矩陣時,對應於該權重 為1之單位矩陣、準單位矩陣或移位矩陣之丨之位置之資料 (對應於屬於單位矩陣、準單位矩陣或移位矩陣之分枝之 訊息)係儲存於同一位址(FIFO 304〗至30418中之同一 FIFO)。 以下,關於從第4及第5段記憶區域,亦與轉換檢查矩陣 H1賦予對應而儲存有資料。該FIFO 304l之記憶區域之段數 係轉換檢查矩陣H,從第1行至第5行之列方向之1之數目(漢 明權重)之最大數即5。 FIFO 3042及3043亦同樣與轉換檢查矩陣H,賦予對應而儲 存資料’分別之長度(段數)為5。FIFO 3044至30412亦同樣 與轉換檢查矩陣H,賦予對應而儲存資料,分別之長度為 3。FIFO 304,3至304^亦同樣與轉換檢查矩陣Ηι賦予對應 而儲存資料,分別之長度為2。 接著’說明關於圖167之解碼裝置之動作。 分枝資料儲存用記憶體300係由6個FIFO 3001至3006所組 成’按照從前段之循環移位電路3〇8所供給之5個訊息d3u 屬於轉換檢查矩陣Η,之何列之資訊(Matrix資料)D3 12,從 FIFO 300丨至30〇6中選擇儲存資料之FIF〇,將5個訊息D3ii 一併順序地儲存於選擇之FIF〇。而且,分枝資料儲存用記 憶體300係於讀出資料時,從FIF〇 3〇〇ι順序地讀出5個訊 息D300, ’並供給至次段之選擇器3〇1。分枝資料儲存用記 135786.doc 200937872 憶體300係於來自FIFO 30〇ι之訊息之讀出終了後,從fif〇 30〇2至30〇6亦順序地讀出訊息,並供給至選擇器3〇 1。 選擇器301係按照選擇信號D301,選擇來自FIFO 3001至 3〇〇6中現在被讀出資料之FIF0之5個訊息,並作為訊息 D3 02供給至校驗節點計算部3 〇2。 校驗卽點什算部302係由5個校驗節點計算器3〇21至3025 所組成’利用透過選擇器3〇 1所供給之訊息d3〇2(D3021至 D3025)(式(7)之訊息Vi),按照式進行校驗節點運算,並 ® 將該校驗節點運算之結果所獲得之5個訊息0303(0303!至 D3 03s)(式⑺之訊息Uj)供給至循環移位電路3〇3。 循環移位電路303係將校驗節點計算部3〇2所求出之5個 訊息03031至〇3035,以對應之分枝在轉換檢查矩陣H,循環 移位幾個原本之單位矩陣之資訊(Matrix資料)D3〇5為基礎 予以循環移位,將其結果作為訊息D3〇4而供給至分枝資料 儲存用記憶體304。 ❹分枝資料儲存用記憶體3〇4係由3〇4ι至3〇4i8所 組成’按照從前段之循環移位電路3〇3所供給之5個訊息 D304屬於轉換檢查矩陣η,之何列之資訊D3〇5,從fif〇 3041至304!8中選擇儲存資料之FIF〇,將5個訊息D3〇4一併 順序地儲存於選擇之FIF〇e而且,分枝資料儲存用記憶體 304係於讀出資料時,從FIF〇 3〇4ι順序地讀出5個訊息 D306,,並供給至次段之選擇器3〇5。分枝資料儲存用記憶 體304係於來自FIF〇 3〇4ι之資料之讀出終了後,從fif〇 3042至304η亦順序地讀出訊息,並供給至選擇器3〇5。 135786.doc 200937872 選擇器305係按照選擇信號D3〇7,選擇來自FIFO 304!至 3041S中現在被讀出資料之fifo之5個訊息,並作為訊息 D308供給至可變節點計算部3〇7及解碼字計算部3〇9。Here, an LDPC decoding has been proposed, which performs LDPC decoding by using a conversion check matrix, and can suppress the circuit scale while suppressing the operating frequency to a sufficiently achievable range (refer to Japanese Laid-Open Patent Publication No. 2004-343170, for example). . Therefore, LDPC decoding with respect to the previously proposed utilization conversion check matrix will be described first with reference to Figs. 164 to 167. Figure 164 is a diagram showing an example of a check matrix LDP of an LDPC code having a code length N of 90 and a coding rate of 2/3. Further, in Fig. 164 (the same applies to Figs. 165 and 166 which will be described later), 0 is represented by a period (.). In the check matrix 图 of Figure 164, the co-located matrix becomes a stepped structure. Fig. 165 is a diagram showing the inspection matrix 图· obtained by the row replacement of the equation (11) and the row replacement of the equation (12) in the inspection matrix 图 of Fig. 164. Column permutation: 6s + t + 1 column - 5t + s + column 1. · (11) Row permutation: 6x + y + 61st line - > 5y + x + 61st line · · (12) where (11) and (12), s, t, X, and y are integers in the range of 〇$s<5, 〇St<6, 0Sx<5, 0St<6, respectively. 135786.doc -232- 200937872 If the substitution is based on the formula (11), the substitution is performed by dividing the first, seventh, thirteenth, 19th, and 25th columns with the remainder of the remainder by 1, and the second, third, and third Columns 4, 5, and columns 2, 8, 14, 20, and 26 divided by 6 are replaced by columns 6, 7, 8, 9, and 10, respectively. Further, if the row is replaced according to the equation (12), the 61st and subsequent (colocated matrix)'s are replaced by the following cases: the 61st, 67th, 73rd, 79th, and 85th lines divided by the 6th remainder are replaced by the 61, 62, 63 '64, 65 lines, divided by 6th, the 62nd, 68th, 74th, 80th, and 86th lines are replaced by the 66th, ❹67, 68th, 69th, and 70th lines, respectively. Thus, the matrix obtained by performing column and row permutation on the inspection matrix 图 of FIG. 164 is the inspection matrix Η' of FIG. Here, even if the column replacement of the check matrix is performed, the arrangement of the code bits of the ldpc code is not affected. Moreover, the row permutation of equation (12) is equivalent to the subdivision of the co-interleaving at the position where the K+qx+y+1 code bits are interleaved to the K+Py+X+1 code bits. The information length K is 60, and the number of rows p of the unit of the tour structure is 5 and the number 9 (=]^/1>) of the same-length length M (here 30) is the co-interlace at 6 o'clock. The LDPC code of the inspection matrix of FIG. 165 (hereinafter referred to as a replacement inspection matrix as appropriate) H''(4) in FIG. 164 (hereinafter suitably referred to as the original inspection matrix) H is subjected to the same replacement as the equation (12). After the matrix, the 0 vector is output. #即, if the column vector obtained by replacing the row vector C'16 with the row of equation (12) as the original check matrix ^ is represented as c', then the nature of the check matrix Look, HcT becomes. Vector, so H'c'T is of course also a 〇 vector. 135786.doc • 233- 200937872 According to the above, the conversion check matrix 图 of FIG. 165 is an inspection matrix of the LDPC code c· obtained by performing the row replacement of the equation (12) on the LDPC code c of the original check matrix. Therefore, the LDPC code c of the original check matrix , is subjected to the row substitution of the equation (12), and the LDPC code c' is decoded (LDPC decoding) by using the conversion check matrix H· of FIG. 165. The decoding result is subjected to the inverse permutation of the row permutation of the equation (12), whereby the decoding result in the case where the LDPC code of the original inspection matrix 利用 is decoded by the inspection matrix 可获得 can be obtained. Figure 166 is a diagram showing the conversion check matrix 图· of Figure 165 with intervals of 5x5 matrix. In FIG. 166, the conversion check matrix η is expressed by a combination of the following matrices: a unit matrix of 5; a matrix of one or more of the unit matrices is a matrix of 〇 (hereinafter suitably referred to as a quasi unit) Matrix); a matrix of cyclic shifts of a unit matrix or a quasi-unit matrix (hereinafter referred to as a shift matrix as appropriate); a sum of 2 or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter suitably The matrix of the matrix of Fig. 166 can be composed of a unit matrix quasi-unit matrix of 5x5, a shift matrix, and a matrix and a unitary matrix. Therefore, the matrix 5x5 which constitutes the conversion check matrix H is hereinafter suitably referred to as a constituent matrix. For the decoding of the LDPC code represented by the check matrix represented by the constituent matrix of Pxp, P architectures for performing check node operations and variable node operations simultaneously can be utilized. Figure 167 is a block diagram showing a configuration example of a decoding apparatus for performing such decoding. 135786.doc - 234 · 200937872 That is, FIG. 167 shows that at least the line of the equation (12) is performed using the original inspection matrix H for FIG. A configuration example of a decoding apparatus for decoding the LDPC code by replacing the conversion check matrix H' of the graph 166 obtained. The decoding device of FIG. 167 includes: a memory for storing branch data stored by six FIFs 〇〇3〇〇1 to 3〇〇6, and a selector for selecting FIF〇3〇〇1 to 3〇〇6 301. The check node calculation unit 302, the two cyclic shift circuits 3〇3 and 308, the branch data storage memory 304 composed of 18 FIFOs 304丨 to 304′8, and the selection FIF〇3〇4丨The selector 305 to 3〇4ls, the received data storage unit 3〇6 storing the received information, the variable node calculation unit 3〇7, the decoded word calculation unit 309, the received data rearrangement unit 3 1〇, and the decoded data rearrangement Section 311 〇 First, the data storage method for the memory 3 〇〇 and 3 〇 4 for the branch data storage is explained. The branch data storage memory 3 is obtained by dividing the number of columns 30' of the conversion check matrix H' of FIG. 166 by the number of columns 5 of the matrix, that is, 6 fif〇❿ 300丨 to 30〇6 Composition. The FIFO 300y (y=l, 2, · · ·, 6) is composed of a plurality of segments of memory regions, and the memory regions of each segment can simultaneously read or write the number of columns and the number of rows corresponding to the constituent matrix. 5 branches of the message. Moreover, the number of segments of the FIFO 300yi memory region is the maximum number of the number of columns (the Hamming weight) of the column of the conversion check matrix of Fig. 166, that is, 9. In the FIFO 300, the data corresponding to the position of the conversion check matrix of FIG. 166 compared to the 1st column to the 5th column (the message heart from the variable node) is stored in the form of horizontally padding each column ( Ignore the form of 〇). That is, if the i-th row of the jth column is represented as (j, i), then in the first segment memory area of the FIF 〇 300, the storage 135786.doc - 235 - 200937872 has a corresponding check matrix Η The data of the position of 1 of the unit matrix of 5x5 of (ι,ι) to (5,5). In the second segment memory area, a shift matrix corresponding to the conversion check matrix Η 'from (1, 21) to (5, 25) is stored (the shift of the unit matrix of 5 χ 5 to the right is only cyclically shifted by 3) Information about the location of the bit matrix). From the third to the eighth segment of the memory area, the data is also stored in correspondence with the conversion check matrix. Then, the 9th segment memory region stores a shift matrix corresponding to the conversion check matrix ( from (1, 86) to (5, 90) (substituting 1 of the 1st column in the unit matrix of 5 χ 5 with 0, And only the data of the position of 1 of the rear shift matrix) is cyclically shifted to the left. In the FIFO 30〇2, data corresponding to the position of the sixth column to the first column of the conversion check_n matrix η' of Fig. 166 is stored. That is, in the 1st section of the FIF〇3〇〇2, the 5th recall area stores the sum matrix corresponding to the transition check matrix from (6,1) to (1〇,5) (the unit matrix of 5χ5 is Information on the position of the first shift matrix of the first shift matrix in which only one of the first shift matrix is cyclically shifted to the right and the sum of the second shift matrices that are cyclically shifted by two to the right. . Further, the second-stage memory area stores data corresponding to the position of I of the second shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (1, 5). That is, 'for a constituent matrix with a weight of 2 or more, a unit matrix of pxp with a weight of 1, one or more of its elements is a quasi-unit matrix of 〇, or a unit matrix or a quasi-unit matrix is cyclically shifted. When the form of the complex sum in the shift matrix after the bit represents the constituent matrix, the data corresponding to the position of the unit matrix, the quasi-unit matrix or the shift matrix of the weight 1 corresponds to the unit matrix, The unit matrix or shift matrix branch 135786.doc -236- 200937872 message) is stored in the same address (the same FIFO in the FIFO 30〇ι to 30〇6). Hereinafter, the data is stored in the memory area ' from the third to the ninth segments as well as the conversion check matrix H'. The FIFOs 30〇3 to 3〇〇6 are also stored in the same manner as the conversion check matrix 11, and data is stored. The branch data storage memory 304 is composed of 18 FIFOs 30 to 30418 以 which are divided by the number of rows constituting the matrix, 5, divided by the conversion check matrix H, and the number of rows 90. FIFO 304x (x=l, 2, ···, 18) is composed of a plurality of segments of memory area. The memory area of each segment can be simultaneously read or written corresponding to the conversion check matrix H, the number of columns and The message of 5 branches of the number of rows. In the FIFO 304, corresponding to the position of the first row to the fifth row of the conversion check matrix H' of FIG. 166 (the message from the check node is stored in the form of vertical filling of each row (to ignore) That is, in the first segment memory area of the FIFO 304, the data corresponding to the position of the unit matrix of 5X5 of the conversion check matrix q H' from G, 1) to (5, 5) is stored. . In the second segment memory region, a sum matrix corresponding to the transition check matrix H, from (1 0, 5), is stored (the fifth matrix matrix of 5x5 is cyclically shifted to the right only! The data of the position of the first shift matrix of the sum matrix of the sum of the two second shift matrices of the two element shift matrices is shifted to the right. Further, the third-stage memory area stores data corresponding to the position of the second shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (1, 5). For a constituent matrix with a weight of 2 or more, a unit matrix with a weight of iipxp 135786.doc • 237- 200937872, a quasi unit matrix with one or more of its elements being 0, or a unit matrix or a quasi-unit matrix The form of the sum of the complex numbers in the shift matrix after cyclic shifting represents the position of the unit matrix, the quasi-unit matrix, or the position of the shift matrix of the weight 1 (corresponding to the unit matrix) The message of the branch of the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO in FIFO 304 to 30418). Hereinafter, data is stored from the fourth and fifth segment memory regions in association with the conversion check matrix H1. The number of segments of the memory area of the FIFO 3041 is the conversion check matrix H, and the maximum number of ones (the Hamming weight) from the first row to the fifth row is five. Similarly, the FIFOs 3042 and 3043 are assigned to the conversion check matrix H, and the length (segment number) of the stored data 'is 5, respectively. The FIFOs 3044 to 30412 are also associated with the conversion check matrix H, and the data is stored, and the length is 3 respectively. The FIFOs 304, 3 to 304^ are also assigned to the conversion check matrix Ηι to store data, each having a length of two. Next, the operation of the decoding apparatus of Fig. 167 will be described. The branch data storage memory 300 is composed of six FIFOs 3001 to 3006. 'The five messages d3u supplied from the previous stage cyclic shift circuit 3〇8 belong to the conversion check matrix, and the information of which column (Matrix) Data) D3 12, select FIF〇 for storing data from FIFO 300丨 to 30〇6, and store 5 messages D3ii sequentially in the selected FIF〇. Further, when the branch data storage memory 300 is used to read data, five pieces of information D300 are sequentially read from the FIF 〇 3〇〇, and supplied to the selector 3〇1 of the second stage. Branch data storage 135786.doc 200937872 The memory 300 is sequentially read from fif〇30〇2 to 30〇6 after the reading of the message from the FIFO 30〇 is completed, and is supplied to the selector. 3〇1. The selector 301 selects five messages of FIF0 from the FIFOs 3001 to 3〇〇6 which are currently read out in accordance with the selection signal D301, and supplies them to the check node calculating unit 3 〇2 as the message D3 02. The check point calculation unit 302 is composed of five check node calculators 3〇21 to 3025 'using the message d3〇2 (D3021 to D3025) supplied by the pass selector 3〇1 (formula (7)) Message Vi), check node operation according to the formula, and + supply 5 messages 0303 (0303! to D3 03s) obtained by the result of the check node operation (message Uj of equation (7)) to the cyclic shift circuit 3 〇 3. The cyclic shift circuit 303 cyclically shifts the information of several original unit matrices by converting the five pieces of information 03031 to 353035 obtained by the check node calculating unit 3〇2 to the conversion check matrix H ( The matrix data is cyclically shifted based on D3〇5, and the result is supplied to the branch data storage memory 304 as the message D3〇4. ❹ Branching data storage memory 3〇4 is composed of 3〇4ι to 3〇4i8 'The five messages D304 supplied by the cyclic shift circuit 3〇3 from the previous stage belong to the conversion check matrix η, which column The information D3〇5 selects the FIF〇 storing the data from fif〇3041 to 304!8, and sequentially stores the five messages D3〇4 in the selected FIF〇e and the branch data storage memory 304. When the data is read, five messages D306 are sequentially read from FIF〇3〇4, and supplied to the selector 3〇5 of the second stage. The branch data storage memory 304 is sequentially read out from fif〇 3042 to 304η after the reading of the data from FIF〇3〇4ι, and is supplied to the selector 3〇5. 135786.doc 200937872 The selector 305 selects five messages of fifo from the FIFO 304! to 3041S which are now read data according to the selection signal D3〇7, and supplies it to the variable node calculation unit 3〇7 as the message D308. The decoded word calculation unit 3〇9.
另一方面’接收資料重排部310係將透過通訊道所接收 之LDPC碼D313,藉由進行式〇2)之行置換來重排,並作 為接收資料D3 14而供給至接收資料用記憶體3〇6。接收資 料用記憶體306係從供給自接收資料重排部31〇之接收資料 D314 ’計算並記憶接收LLR(對數概度比),將該接收llr 每5個一併作為接收值D309而供給至可變節點計算部307及 解碼字計算部309。 可變節點計算部307係由5個可變節點計算器3〇71至3075 所組成’利用透過選擇器305所供給之訊息0308(0308〗至 D3085)(式(1)之訊息Uj)及從接收資料用記憶體3〇6所供給之 5個接收值D309(式(1)之接收值…❶,按照式(1)進行可變節 點運算’將其運算之結果所獲得之訊息D310(D31〇i至 D31〇5)(式(1)之訊息Vi)供給至循環移位電路3〇8。 循環移位電路308係將可變節點計算部307所計算之訊息 D3 10〗至D3 1 〇5,以對應之分枝在轉換檢查矩陣H,循環移位 幾個原本之單位矩陣之資訊為基礎予以循環移位,將其結 果作為訊息D311而供給至分枝資料儲存用記憶體3〇〇。 藉由將以上動作巡迴丨次,可進行LDPC碼之丨次解碼。 圖167之解碼裝置係僅以特定次數將ldPC碼解碼後,於解 碼字計算部309及解碼資料重排部311,求出最終之解碼結 135786.doc • 240- 200937872 亦即’解碼字計算部3〇9係由5個解碼字計算器3〇9ι至 3〇95所組成,利用選擇器3〇5所輸出之⑽訊息職(画丨 至D3085)(式(5)之訊息Uj)及從接收資料用記憶體鳩所供給 之5個接收值卿(式⑺之接收值叫),作為複數次解碼之 最終段,根據式(5)計算解碼結果(解碼字),將其結果所獲 得之解碼資料D3 15供給至解碼資料重排部3丨j。 解碼資料重排部311係藉由將供給自解碼字計算部3〇9之 解碼資料D315作為對象1行式⑽之行置換之反置換, © 卩重排其順序’並作為最終之解碍結果D316而輸出。 如以上,藉由對於檢查矩陣(原本之檢查矩陣)施以列置 換及行置換中之一方或雙方,轉換為能以ρχρ之單位矩 陣其要素之1之中有1個以上為〇之準單位矩陣、將單位 矩陣或準單位矩陣予以循環移位後之移位矩陣、單位矩 陣、準單位矩陣或移位矩陣之複數個之和之和矩陣、ρ叶 之0矩陣之組合,亦即能以構成矩陣之組合來表示之檢查 q 矩陣(轉換檢查矩陣),可將LDPC碼之解碼採用同時進行ρ 個校驗節點運算及可變節點運算之架構(architecture),藉 此,同時進行P個節點運算,可將動作頻率壓低在可實現 之範圍,進行許多重複解碼。 構成圖162之接收裝置12iLDpc解碼部56係與圖167之 解碼裝置相同,藉由同時進行ρ個校驗節點運算及可變節 點運算,以進行LDPC解碼。 亦即,現在若為了簡化說明,將構成圖8之發送裝置n 之LDPC編碼部21所輪出之LDpc碼之檢查矩陣設作例如圖 135786.doc •241 - 200937872 =所示之w陣成為階梯構造之檢查料η,則於發送 、11之同位父錯器23 ,將第K+qx+y+i個碼位元交錯至On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 received through the communication channel by the line replacement of the expression 〇2), and supplies it to the received data memory as the received data D3 14 . 3〇6. The received data memory 306 calculates and memorizes the received LLR (logarithm ratio ratio) from the received data D314' supplied from the received data rearrangement unit 31, and supplies the received llr to the received value D309 every five times. The variable node calculation unit 307 and the decoded word calculation unit 309. The variable node calculation unit 307 is composed of five variable node calculators 3〇71 to 3075 'using the message 0308 (0308 to D3085) supplied by the pass selector 305 (the message Uj of the equation (1)) and the slave The received data is received by the memory 3〇6, the five received values D309 (the received value of the equation (1), 可变, the variable node operation according to the equation (1), the message D310 obtained by the result of the calculation (D31) 〇i to D31〇5) (message Vi of the equation (1)) is supplied to the cyclic shift circuit 3〇8. The cyclic shift circuit 308 sets the messages D3 10 to D3 1 calculated by the variable node calculation unit 307. 5. The corresponding branch is cyclically shifted based on the information of the original unit matrix by cyclically shifting the check matrix H, and the result is supplied to the branch data storage memory 3 as the message D311. The LDPC code can be decoded once by the above operation. The decoding device of Fig. 167 decodes the ldPC code only a specific number of times, and then obtains the decoded word calculation unit 309 and the decoded data rearrangement unit 311. The final decoding knot 135786.doc • 240- 200937872 is also the 'decoding word calculation department 3〇9 series It consists of 5 decoded word calculators 3〇9ι to 3〇95, which are output by the selector (3) message (picture to D3085) (memory Uj of equation (5)) and memory from receiving data. The five received values supplied by the body (called the received value of the equation (7)) are used as the final segment of the complex decoding, and the decoding result (decoded word) is calculated according to the equation (5), and the decoded data D3 obtained by the result is obtained. The decoded data rearrangement unit 311 is inversely replaced by the decoded data D315 supplied from the decoded word calculating unit 3〇9 as a row of the object 1 line (10), © 卩In the order of ', and output as the final distraction result D316. As above, by applying one or both of the column permutation and the row permutation to the inspection matrix (original inspection matrix), it is converted into a unit matrix capable of ρχρ. One or more of the elements 1 is a quasi-unit matrix of 〇, a complex matrix of a shift matrix, a unit matrix, a quasi-unit matrix, or a shift matrix after cyclically shifting the unit matrix or the quasi-unit matrix. Combination with matrix and ρ leaf zero matrix, also The q matrix (conversion check matrix) can be represented by a combination of constituent matrices, and the LDPC code can be decoded by using an architecture of ρ check node operations and variable node operations simultaneously, thereby simultaneously performing P The node operation can reduce the operating frequency to an achievable range and perform a lot of repeated decoding. The receiving device 12iLDpc decoding unit 56 constituting the drawing 162 is the same as the decoding device of FIG. 167, and performs ρ check node operations simultaneously and Variable node operation for LDPC decoding. That is, for the sake of simplicity of explanation, the check matrix of the LDpc code which is circulated by the LDPC encoding section 21 constituting the transmitting apparatus n of Fig. 8 is set as, for example, Fig. 135786.doc • 241 - 200937872 = the w array shown becomes a ladder Constructing the inspection material η, then interleaving the K+qx+y+i code bits to the same,
第Κ7+Χ+1個碼位元之位置之同位交錯資訊長K 、巡迴構造之單位之行數Ρ設作5、同位長Μ之約數 q(=M/P)設作6而進行。 由於該同位交錯係如上述相當於式〇2)之行置換因此 於LDPC解碼部56無須進行式(12)之行置換。The position of the co-located interleaved information length K of the position of the seventh Χ7+Χ+1 code bit, the number of lines of the unit of the tour structure Ρ, 5, the number of the same position long q q (=M/P) is set to 6. Since the co-located interleaving is performed as described above in relation to the line )2), the LDPC decoding unit 56 does not need to perform the line replacement of the equation (12).
因此於圖162之接收裝置12,如上述從縱行扭轉反交 錯器55對於LDPC解碼部56 ,供給有未進行同位反交錯之 LDPC瑪,亦即供給有已進行式(12)之行置換之狀態下之 LDPC碼,於LDPC解碼部%,除未進行式⑴)之行置換以 外,與圖167之解碼裝置均進行同樣之處理。 亦即,圖168係表示圖162之LDpc解碼部%之結構例。 於圖168,LDPC解碼部56係除未設有圖167之接收資料 重排部310以外,與圖167之解碼裝置均同樣地構成,除未 進行式(12)之行置換以外,與圖167之解碼裝置均進行同樣 之處理,因此省略其說明。 如以上,由於LDPC解碼部56不設置接收資料重排部31〇 即可構成,因此可較圖167之解碼裝置刪減規模。 此外,於圖I64至圖168,為了簡化說明,分別將LDpc 碼之碼長N設作90、資訊長K設作60、巡迴構造之單位之 行數(構成矩陣之列數及行數)P設作5、同位長μ之約數 q(=M/P)設作6,但碼長Ν、資訊長Κ、巡迴構造之單位之 行數P及約數q(=M/P)之各個不限定於上述值。 135786.doc -242- 200937872 亦即,於圖8之發送裝置u , lDPC編碼部2丨係輸出例如 刀別而言碼長N設作64800或16200、資訊長K設作N-Pq(-N-M)、巡迴構造之單位之行數p設作36〇、約數q設作 Μ/P之LDPC碼,但於圖168之解碼部56將該類ldpc 碼作為對象,同時進行P個校驗節點運算及可變節點運 算,藉此進行LDPC解碼之情況下亦可適用。 接著,上述一連串處理係藉由硬體進行,或藉由軟體進 行均可。藉由軟體進行一連串處理之情況時,構成該軟體 之程式安裝於泛用電腦等。 因此,圖169係表示安裝有執行上述一連串處理之程式 之電腦之一實施型態之結構例。 程式可事先記錄於内建在電腦之作為記錄媒體之硬碟 705 或 ROM 703。 或者,程式可預先暫時或永久地儲存(記錄)於軟碟、 CD-:R〇M(Compact Disc Read Only Memory :微型碟片唯讀 s己憶體)、MO(Magneto 〇pticai :磁光)碟片、DVD(Dighal Versatile Disc:數位多功能碟片)、磁性碟片半導體記 憶體等可移式圮錄媒體711。該類可移式記錄媒體7丨丨可作 為所謂套裝軟體來提供。 此外,程式係除了從如上述之可移式記錄媒體711安裝 至電腦以外,可從下載頁面,經由數位衛星播放用之人工 衛星,以無線傳輸至電腦,經由LAN(L〇cal Area Netw〇rk: 區域網路)' 網際網路之網路,以有線傳輸至電腦’於電 腦,以通訊部708接收如此傳輸而來之程式,並安裝於内 135786.doc -243- 200937872 建之硬碟705。 電腦内建有CPU(Central Processing Unit :中央處理單 元)702。於CPU 702,經由匯流排701連接有輸出入介面 710,若經由輸出入介面710,並由使用者將鍵盤或滑鼠、 微音器等所構成之輸入部707予以操作等,以輸入指令, 貝|J CPU 702係按照其而執行儲存於ROM(Read Only Memory:唯讀記憶體)703之程式。或者,CPU 702係將儲 存於硬碟705之程式、從衛星或網路傳輸並以通訊部708接 〇 收而安裝於硬碟705之程式、或從裝載於磁碟機709之可移 式記錄媒體711讀出並安裝於硬碟705之程式,載入RAM (Random Access Memory :隨機存取記憶體)704而執行。 藉此,CPU 702係進行按照上述流程圖之處理、或進行藉 由上述區塊圖之結構所進行之處理。然後,CPU 702係根 據必要,將其處理結果經由例如輸出入介面710,從以 LCD(Liquid Crystal Display :液晶顯示器)或揚聲器等所構 成之輸出部706輸出,或者從通訊部708發送,並進一步使 其記錄於硬碟705等。 於此,本說明書中記述用以使電腦進行各種處理之程式 之處理步驟,未必要按照作為流程圖所記載之順序而循時 間序列予以處理,其亦包含並列或個別地執行之處理(例 如並列處理或依物件之處理)。 而且,程式係藉由1台電腦處理或藉由複數台電腦予以 分散處理均可。進一步而言,程式亦可傳輸至遠方之電腦 而執行0 135786.doc • 244- 200937872 接著,進一步說明關於藉由發送裝置11之LDPC編碼部 2 1所進行之LDPC編碼之處理。 例如於DVB-S.2之規格,規定有64800位元及16200位元 之2種碼長N之LDPC碼。 然後,關於碼長N為64800位元之LDPC碼,規定有11個 編碼率 1/4、1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6、8/9 及9/10,關於碼長N為16200位元之LDPC碼,規定有10個 編碼率 1/4、1/3、2/5、1/2、3/5、2/3、3/4、4/5、5/6 及 Ο 8/9。 LDPC編碼部21係按照依每碼長N及每編碼率所準備之檢 查矩陣Η,藉由該類碼長N為64800位元或16200位元之各 編碼率之LDPC碼進行編碼(失誤訂正編碼)。 亦即,LDPC編碼部21係依每碼長N及每編碼率,記憶用 以生成檢查矩陣Η之後述之檢查矩陣初始值表。 於此,於DVB-S.2之規格,如上述規定有64800位元及 16200位元之2種碼長Ν之LDPC碼,分別關於碼長Ν為 64800位元之LDPC碼規定有11個編碼率,關於碼長N為 16200位元之LDPC碼規定有10個編碼率。 因此,發送裝置11為進行依據DVB-S.2之規格之處理之 裝置之情況時,於LDPC編碼部2 1記憶有關於碼長N為 64800位元之LDPC碼之分別對應於11個編碼率之檢查矩陣 初始值表、及關於碼長N為16200位元之LDPC碼之分別對 應於10個編碼率之檢查矩陣初始值表。 LDPC編碼部21係根據例如操作者之操作等,來設定 135786.doc •245· 200937872 LDPC碼之碼長N及編碼率r»於此,以下適宜地將LDPC編 碼部21所設定之碼長n及編碼率r,分別亦稱為設定碼長N 及設定編碼率r。 LDPC編碼部21係根據對應於設定碼長N及設定編碼率r 之檢查矩陣初始值表,將對應於根據設定碼長N及設定編 碼率r之資訊長K(=Nr=碼長N-同位長M)之資訊矩陣HA之1 之要素,以每360行(巡迴構造之單位之行數P)之週期配置 於行方向,生成檢查矩陣Η。 然後’ LDPC編碼部2 1係從供給至發送裝置11之圖像資 料或聲音資料等作為發送對象之對象資料,擷取資訊長Κ 份之資訊位元。進一步而言,LDPC編碼部21係根據檢查 矩陣Η ’算出對於資訊位元之同位位元,生成1碼長份之碼 字(LDPC碼)。 亦即’ LDPC編碼部21係依次運算符合下式之碼字c之同 位位元。Therefore, the receiving apparatus 12 of Fig. 162 supplies the LDPC decoding unit 56 to the LDPC decoding unit 56 as described above, and supplies LDPC Ma which is not subjected to the co-deinterlacing, that is, the line replacement of the equation (12) is supplied. The LDPC code in the state is processed in the same manner as the decoding apparatus of FIG. 167 except that the LDPC decoding unit % is replaced by the line of the equation (1). That is, Fig. 168 is a diagram showing an example of the configuration of the LDpc decoding unit % of Fig. 162. In FIG. 168, the LDPC decoding unit 56 is configured similarly to the decoding device of FIG. 167 except that the received data rearrangement unit 310 of FIG. 167 is not provided, except that the row replacement of the equation (12) is not performed, and FIG. Since the decoding apparatus performs the same processing, the description thereof will be omitted. As described above, since the LDPC decoding unit 56 is not provided with the received data rearrangement unit 31, the decoding apparatus of Fig. 167 can be reduced in size. In addition, in FIGS. I64 to 168, in order to simplify the description, the code length N of the LDpc code is set to 90, the information length K is set to 60, and the number of rows of the tour structure unit (the number of columns and the number of rows of the matrix) P Let 5 be the divisor q (=M/P) set to 6, but the code length Ν, information length Κ, the number of rows of the unit of the tour structure P and the number q (=M/P) are not limited. Above the above values. 135786.doc -242- 200937872 That is, in the transmitting device u of FIG. 8, the lDPC encoding unit 2 outputs, for example, the code length N is set to 64800 or 16200, and the information length K is set to N-Pq (-NM). The row number p of the unit of the patrol structure is set to 36 〇, and the number q is set as the LDPC code of Μ/P, but the decoding unit 56 of FIG. 168 takes the ldpc code as the object and performs P check node operations at the same time. And the variable node operation can also be applied in the case of performing LDPC decoding. Then, the series of processes described above can be performed by hardware or by software. When a series of processing is performed by software, the program constituting the software is installed in a general-purpose computer or the like. Therefore, Fig. 169 is a diagram showing an example of a configuration in which one type of computer is installed with a program for executing the above-described series of processes. The program can be recorded in advance on a hard disk 705 or ROM 703 built in a computer as a recording medium. Alternatively, the program can be temporarily or permanently stored (recorded) on a floppy disk, CD-: R〇M (Compact Disc Read Only Memory), MO (Magneto 〇pticai: magneto-optical) A removable recording medium 711 such as a disc, a DVD (Dighal Versatile Disc), a magnetic disc semiconductor memory, or the like. This type of portable recording medium 7 can be provided as a so-called package software. In addition, the program is installed in the portable recording medium 711 as described above to the computer, and can be wirelessly transmitted to the computer via the LAN from the download page via the artificial satellite for digital satellite broadcasting, via the LAN (L〇cal Area Netw〇rk : Regional Network) 'Internet network, wired to the computer' on the computer, the communication unit 708 receives the program transmitted from this, and installed in the internal 135786.doc -243- 200937872 hard disk 705 . A CPU (Central Processing Unit) 702 is built in the computer. In the CPU 702, an input/output interface 710 is connected via the bus bar 701, and an input command 707 composed of a keyboard, a mouse, a microphone, or the like is operated by the user via the input/output interface 710, and an instruction is input. The Bay|J CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance therewith. Alternatively, the CPU 702 is a program that is stored in the hard disk 705, transmitted from a satellite or a network, and installed on the hard disk 705 by the communication unit 708, or from a portable recording loaded on the disk drive 709. The medium 711 reads and installs the program on the hard disk 705, and loads it into a RAM (Random Access Memory) 704 to execute it. Thereby, the CPU 702 performs processing in accordance with the above-described flowchart or processing performed by the above-described block diagram. Then, the CPU 702 outputs the processing result from the output unit 706 composed of an LCD (Liquid Crystal Display) or a speaker or the like via the input/output interface 710, for example, or from the communication unit 708, and further. Make it recorded on the hard disk 705 or the like. Here, the processing steps of the program for causing the computer to perform various processes are described in the present specification, and it is not necessary to process them in time series according to the sequence described in the flowchart, and also includes processing performed in parallel or individually (for example, juxtaposition Handling or handling by object). Moreover, the program can be processed by one computer or distributed by a plurality of computers. Further, the program can also be transmitted to a remote computer to execute 0 135786.doc • 244- 200937872 Next, the processing of LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11 will be further explained. For example, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and Ο 8/9. The LDPC encoding unit 21 performs encoding by using an LDPC code of a code length N of 64800 bits or 16200 bits in accordance with an inspection matrix 每 prepared per code length N and per coding rate (error correction coding) ). In other words, the LDPC encoding unit 21 stores a check matrix initial value table which will be described later, based on the code length N and the coding rate. Here, in the specification of DVB-S.2, as described above, there are two kinds of code lengths of 64800 bits and 16200 bits, and 11 codes are respectively specified for the LDPC code with a code length of 64800 bits. The rate is about 10 encoding rates for an LDPC code having a code length N of 16,200 bits. Therefore, when the transmitting apparatus 11 is a device that performs processing according to the specifications of DVB-S.2, the LDPC encoding unit 21 stores that the LDPC codes having a code length N of 64,800 bits correspond to 11 encoding rates, respectively. The check matrix initial value table and the LDPC code having a code length N of 16,200 bits respectively correspond to a check matrix initial value table of 10 coding rates. The LDPC encoding unit 21 sets the code length N and the encoding rate r» of the LDPC code according to the operation of the operator, for example, and the code length n set by the LDPC encoding unit 21 is appropriately selected hereinafter. And the coding rate r, which is also referred to as a set code length N and a set code rate r, respectively. The LDPC encoding unit 21 corresponds to the information length K (=Nr=code length N-co-located according to the set code length N and the set coding rate r according to the check matrix initial value table corresponding to the set code length N and the set coding rate r. The element of the information matrix HA of the length M) is arranged in the row direction every cycle of 360 lines (the number of rows P of the circuit structure), and the inspection matrix 生成 is generated. Then, the LDPC encoding unit 2 1 extracts the information bits of the information from the image data or the sound data supplied to the transmitting device 11 as the target data to be transmitted. Further, the LDPC encoding unit 21 calculates a code word (LDPC code) of one code long by calculating the parity bit for the information bit based on the check matrix Η '. That is, the LDPC encoding unit 21 sequentially calculates the parity bits of the code word c conforming to the following equation.
Hc^O 於此’上式中,c表示作為碼字(LDPC碼)之列向量,CT 表示列向量c之轉置。 作為LDPC碼(1碼字)之列向量(;中,以列向量a表示資訊 位元之部分’並且以列向量T表示同位位元之部分之情況 下’列向量c可藉由作為資訊位元之列向量a及作為同位位 元之列向量T,並以式C=[A|T]來表示。 而且,檢查矩陣Η可藉由LDPC碼之碼位元中對應於資訊 位元之部分之資訊矩陣、及對應於同位位元之同位矩陣 135786.doc 200937872 Ητ ’來表示為式H=[HA|HT](資訊矩陣Ha之要素設為左側要 素’同位矩陣Ητ之要素設為右側要素之矩陣)。 進一步而言,例如於DVB-S.2之規格,檢查矩陣 H=[HA|HT]之同位矩陣Ητ成為階梯構造。 檢查矩陣Η及作為LDPC碼之列向量c=[A|T]必須符合式 HcT=0,作為構成符合該式Hct=〇之歹向量c=[A丨τ]之同位 位元之列向量T,可藉由於檢查矩陣H=[HA|HT]之同位矩降 Ητ成為階梯構造之情況下,從式HcT=〇之行向量Hct之第j 列之要素’依序使各列之要素成為〇而可逐次地求出。 LDPC編碼部21若對於資訊位元A求出同位位元τ,則將 藉由該資訊位元A及同位位元T所表示之碼字C=[A|T]作為 資訊位元A之LDPC編碼結果而輸出。 如以上’ LDPC編碼部21係記憶有各碼長N及對應於各編 碼率r之檢查矩陣初始值表,設定碼長n之設定編碼率Γ之 LDPC編碼利用從該設定碼長n及對應於設定編碼率j·之檢 查矩陣初始值表所生成之檢查矩陣Η來進行。 檢查矩陣初始值表係將檢查矩陣Η之對應於根據LDPC碼 (藉由檢查矩陣Η所定義之LDPC碼)之碼長N及編碼率r之資 訊長K之資訊矩陣HA之1之要素之位置,以每360行(巡迴構 造之單位之行數P)表示之表,依各碼長N及各編碼率r之檢 查矩陣Η逐一事先編製。 圖170至圖215係表示包含DVB-S.2之規格所規定之檢查 矩陣初始值表之用以生成各種檢查矩陣Η之檢查矩陣初始 值表。 135786.doc 247- 200937872 亦即’圖170係表示DVB-S.2之規格所規定之對於瑪長N 為16200位元之編碼率1>為2/3之檢查矩陣Η之檢查矩陣初始 值表。 圖171至圖173係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為2/3之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖172係接續於圖171之圖,圖173係接續於圖172 之圖。 〇 圖174係表示DVB-S.2之規格所規定之對於碼長Ν為 16200位元之編碼率r為3Μ之檢查矩陣Η之檢查矩陣初始值 表。 圖175至圖178係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為3Μ之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖176係接續於圖175之圖,圖177係接續於圖176 之圖。而且,圖178係接續於圖177之圖。 圖179係表示DVB-S.2之規格所規定之對於碼長Ν為 16200位元之編碼率r為4/5之檢查矩陣Η之檢查矩陣初始值 表。 圖180至圖183係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為4/5之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖181係接續於圖180之圖,圖182係接續於圖181 之圖。而且,圖183係接續於圊182之圖。 135786.doc • 248- 200937872 圖184係表示DVB-S.2之規格所規定之對於碼長N為 16200位元之編碼率r為5/6之檢查矩陣Η之檢查矩陣初始值 表。 圖185至圖188係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為5/6之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖186係接續於圖185之圖,圖187係接續於圖186 之圖。而且,圖188係接續於圖187之圖。 Ο 圖189係表示DVB-S.2之規格所規定之對於碼長Ν為 16200位元之編碼率r為8/9之檢查矩陣Η之檢查矩陣初始值 表。 圖190至圖193係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為8/9之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖191係接續於圖190之圖,圖192係接續於圖191 之圖。而且,圖193係接續於圖192之圖。 圖194至圖197係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為9/10之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖195係接續於圖194之圖,圖196係接續於圖195 之圖。而且,圖197係接續於圖196之圖。 圖198及圖199係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為1/4之檢查矩陣Η之檢查矩陣初 始值表。 135786.doc -249- 200937872 此外,圖199係接續於圖198之圖。 圖200及圖201係表示DVB-S.2之規格所規定之對於碼長 N為64800位元之編碼率r為1/3之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖201係接續於圖200之圖。 圖202及圖203係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為2/5之檢查矩陣Η之檢查矩陣初 始值表。 ❹ 此外,圖203係接續於圖202之圖。 圖204至圖206係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為1/2之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖205係接續於圖204之圖,圖206係接續於圖205 之圖。 圖207至圖209係表示DVB-S.2之規格所規定之對於碼長 Ν為64800位元之編碼率r為3/5之檢查矩陣Η之檢查矩陣初 始值表。 此外,圖208係接續於圖207之圖,圖209係接續於圖208 之圖。 圖210係表示DVB-S.2之規格所規定之對於碼長Ν為 16200位元之編碼率r為1/4之檢查矩陣Η之檢查矩陣初始值 表。 圖211係表示DVB-S.2之規格所規定之對於碼長Ν為 16200位元之編碼率r為1/3之檢查矩陣Η之檢查矩陣初始值 135786.doc -250- 200937872 表〇 . 圖212係表示DVB-S.2之規格所規定之對於碼長n為 1 6200位元之編碼率Γ為2/5之檢查矩陣Η之檢查矩陣初始值 表。 圖213係表示DVB-S.2之規格所規定之對於碼長ν為 1位元之編碼率r為1/2之檢查矩陣Η之檢查矩陣初始值 表。 圖214係表示DVB-S.2之規格所規定之對於碼長ν為 1 6200位元之編碼率r為3/5之檢查矩陣Η之檢查矩陣初始值 表。 圖215係表示可取代圖214之檢查矩陣初始值表來利用之 碼長Ν為16200位元之對於編碼率r為3/5之檢查矩陣Η之檢 查矩陣初始值表。 發送裝置11之LDPC編碼部21係利用檢查矩陣初始值 表’如以下求出檢查矩陣Η。 亦即’圖216係表示從檢查矩陣初始值表求出檢查矩陣η 之方法。 此外,圖216之檢查矩陣初始值表係表示對於圖ι7〇所示 之DVB-S.2之規格所規定之碼長Ν為16200位元之編碼率r為 2/3之檢查矩陣η之檢查矩陣初始值表。 檢查矩陣初始值表係如上述,將對應於根據Ldpc碼之 碼長Ν及編碼率r之資訊長κ之資訊矩陣ηα2 1之要素之位 置’以每360行(巡迴構造之單位之行數Ρ)表示之表,於其 第1列,檢查矩陣Η之第l+36〇x(i-l)行之1之要素之列號碼 135786.doc •251 _ 200937872 (檢查矩陣Η之第1列之列號碼設作〇之列號碼)僅排列有該 第l + 360x(i-l)行之行所具有之行權重之數目。 於此’檢查矩陣Η之對應於同位長Μ之同位矩陣Ητ係成 為階梯構造’其係事先已決定。若根據檢查矩陣初始值 表,可求出檢查矩陣Η中之對應於資訊長κ之資訊矩陣 ΗΑ。 檢查矩陣初始值表之列數k+Ι係依資訊長κ而不同。 於資訊長K與檢查矩陣初始值表之列數k+1間,下式之 〇 關係成立。 K=(k+l)x360 於此’上式之360為巡迴構造之單位之行數p。 於圖216之檢查矩陣初始值表’從第1列至第3列排列有 13個數值,從第4列至第k+Ι列(於圖216為第30列)排列有3 個數值。 因此,從圖216之檢查矩陣初始值表所求出之檢查矩陣H ❹ 之行權重係從第1行至第1+36〇χ(3-1)-1行為13,從第 1 + 3 60><(3-1)行至第1^行為3。 圖216之檢查矩陣初始值表之第1列為〇、2〇84、ι613、 1548、1286、1460、3196、4297、2481、3369、3451、 4620、2622 ’此係表示於檢查矩陣Η之第1行,列號碼為 0 、 2084 、 1613 、 1548 、 1286 ' 1460 、 3196 、 4297 、 2481、3369、3451、4620、2622之列之要素為!(且其他要 素為0)。 而且,圖216之檢查矩陣初始值表之第2列為1、122、 135786.doc •252· 200937872 1516、3448、2880、1407、1847、3799、3529、373、 971、4358、3108,此係表示於檢查矩陣H之第361(=1 + 36〇χ(2 — 1))行’列號碼為 1、122、1516、3448、2880、 1407、1847、3799、3529、373、971、4358、3108之列之 要素為1。 如以上,檢查矩陣初始值表係將檢查矩陣Η之資訊矩陣 ΗΑ之1之要素之位置以每360行表示。 檢查矩陣Η之第1+360x(i-l)行以外之行,亦即從第 2+36〇x(i-l)行至第36〇xi行之各行係將藉由檢查矩陣初始 值表所決定之第l+36〇x(i-l)行之1之要素’按照同位長μ 往下方向(行之下方向)週期性地予以循環移位而配置。 亦即’例如第2+36〇x(i-l)行係將第i+36〇x(i-l)行往下方 向僅循環移位M/360(=q),接著之第3+36〇χ(Μ)行係將第 l+36〇x(i-l)行往下方向僅循環移位2><M/360(=2xq)(將第 2+36〇x(i-l)行往下方向僅循環移位M/360(=q))。 現在’若將檢查矩陣初始值表之第i列(從上算起第Η固) 之第j行(左起第j個)之數值表示作hjj,並且將檢查矩陣η 之第w行之第j個之1之要素之列號碼表示作Hw_j,則檢查矩 陣Η之第1+36〇χ(i-Ι)行以外之行之第w行之1之要素之列號 碼11叫可由下式求出。Hc^O In the above equation, c denotes a column vector as a codeword (LDPC code), and CT denotes a transposition of the column vector c. As the column vector of the LDPC code (1 codeword) (in the case where the column vector a represents the portion of the information bit ' and the column vector T represents the portion of the parity bit, the column vector c can be used as the information bit The column vector a and the column vector T as the parity bits are represented by the formula C=[A|T]. Moreover, the check matrix can be represented by the portion of the code bit of the LDPC code corresponding to the information bit. The information matrix and the parity matrix corresponding to the parity bit 135786.doc 200937872 Ητ 'is expressed as the formula H=[HA|HT] (the element of the information matrix Ha is set to the left element 'the element of the same matrix Ητ is set to the right element Further, for example, in the specification of DVB-S.2, the parity matrix Ητ of the check matrix H=[HA|HT] becomes a ladder structure. The check matrix Η and the column vector LDPC code are c=[A| T] must conform to the formula HcT=0, as the column vector T constituting the parity of the 歹 vector c=[A丨τ] according to the formula Hct=〇, which can be due to the parity of the check matrix H=[HA|HT] When the moment drop Η is a step structure, the elements of the jth column from the HcT=〇 row vector Hct are sequentially made to the elements of each column. The LDPC encoding unit 21 obtains the parity word τ for the information bit A, and then the code word C=[A| represented by the information bit A and the parity bit T. T] is output as the LDPC coding result of the information bit A. As described above, the LDPC encoding unit 21 stores the code length N and the check matrix initial value table corresponding to each coding rate r, and sets the code rate of the code length n. The LDPC code is performed by using the check matrix Η generated from the set code length n and the check matrix initial value table corresponding to the set code rate j·. The check matrix initial value table checks the matrix Η corresponding to the LDPC code. The position of the element of the information matrix HA1 of the information length N (the LDPC code defined by the matrix )) and the information length K of the coding rate r is expressed in every 360 lines (the number of rows of the circuit in the tour structure) The table is prepared in advance according to the code length N and the check matrix r of each coding rate r. Figures 170 to 215 show the check matrix initial value table specified by the specification of DVB-S.2 for generating various checks. Matrix matrix check matrix initial value table. 135786.doc 247- 200937872 ie ' Fig. 170 is a table showing the initial value of the check matrix of the check matrix & of the code length 1 of 16200 bits for the length of the DVB-S.2, which is defined by the specification of DVB-S.2. Fig. 171 to Fig. 173 show the DVB. The check matrix initial value table of the check matrix 编码 for the code length r of 64800 bits, which is defined by the specification of S.2, is 2/3. Further, Fig. 172 is continued from Fig. 171, Fig. 173 The connection is continued from Figure 172. 〇 Figure 174 is a table showing the initial value of the check matrix of the check matrix 对于 for the code length r of 16200 bits, which is defined by the specification of DVB-S.2. Fig. 175 to Fig. 178 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits, which is defined by the specification of DVB-S.2. In addition, FIG. 176 is continued from FIG. 175, and FIG. 177 is continued from FIG. Moreover, Figure 178 is continued from the diagram of Figure 177. Figure 179 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 16200 bits, which is defined by the specification of DVB-S.2, which is 4/5. Fig. 180 to Fig. 183 are diagrams showing the check matrix initial value table of the check matrix 编码 for which the code length Ν is 64,800 bits and the code rate r is 4/5 as defined in the specification of DVB-S.2. In addition, FIG. 181 is continued from FIG. 180, and FIG. 182 is continued from FIG. Moreover, Fig. 183 is a diagram continued from 圊182. 135786.doc • 248- 200937872 Figure 184 is a table showing the initial value of the check matrix for the check matrix 编码 with a code length N of 16200 bits and a code rate r of 5/6 as defined by the specification of DVB-S.2. Fig. 185 to Fig. 188 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length r of 64800 bits with a code length r of 5/6 as defined by the specification of DVB-S.2. In addition, FIG. 186 is continued from FIG. 185, and FIG. 187 is continued from FIG. Moreover, Figure 188 is continued from the diagram of Figure 187. Ο Figure 189 is a table showing the initial value of the check matrix for the check matrix 编码 with a code length 16 of 16200 bits and a code rate r of 8/9 as defined by the specification of DVB-S.2. Fig. 190 to Fig. 193 are diagrams showing the check matrix initial value table of the check matrix 编码 of the code rate r of 64/800 with a code length 为 of 8/9 as defined by the specification of DVB-S.2. In addition, FIG. 191 is continued from FIG. 190, and FIG. 192 is continued from FIG. Moreover, FIG. 193 is continued from the diagram of FIG. Fig. 194 to Fig. 197 are diagrams showing the check matrix initial value table of the check matrix 编码 for the coding rate r of the code length 64 of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 195 is continued from FIG. 194, and FIG. 196 is continued from FIG. Moreover, Figure 197 is continued from the diagram of Figure 196. Fig. 198 and Fig. 199 show the check matrix initial value table of the check matrix 对于 for which the code rate 64 is 64,800 bits and the code rate r is 1/4 as defined by the specification of DVB-S.2. 135786.doc -249- 200937872 In addition, Figure 199 is continued from Figure 198. Fig. 200 and Fig. 201 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length N of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 201 is continued from the diagram of FIG. Fig. 202 and Fig. 203 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length r of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 203 is continued from the diagram of FIG. Fig. 204 to Fig. 206 are diagrams showing the check matrix initial value table of the check matrix 为 for the code rate 64 of 64,800 bits, which is 1/2 of the specification of DVB-S.2. In addition, FIG. 205 is continued from the diagram of FIG. 204, and FIG. 206 is continued from the diagram of FIG. Fig. 207 to Fig. 209 are diagrams showing the check matrix initial value table of the check matrix 对于 for the code length 64 of 64,800 bits with a code length r of 3/5 as defined by the specification of DVB-S.2. In addition, FIG. 208 is continued from the diagram of FIG. 207, and FIG. 209 is continued from the diagram of FIG. Fig. 210 is a table showing the initial value of the check matrix of the check matrix 为 for the code rate r of 16200 bits, which is defined by the specification of DVB-S.2, which is 1/4. Figure 211 shows the check matrix initial value of the check matrix 135 135786.doc -250- 200937872 Table 〇 for the code rate r of 16200 bits with a code length 16 of DVB-S.2. The 212 series indicates an inspection matrix initial value table of an inspection matrix 编码 for a coding rate Γ of 2 6200 bits having a code length n of DVB-S.2. Figure 213 is a table showing the initial value of the check matrix of the check matrix 为 for the code rate r of 1 bit, which is defined by the specification of DVB-S.2. Figure 214 is a table showing the initial value of the check matrix of the check matrix 对于 for the code rate r of 166 bits with a code length ν of 3/5 as defined by the specification of DVB-S.2. Figure 215 is a table showing the initial value of the check matrix of the check matrix 编码 with a code length r of 3/5, which can be used in place of the check matrix initial value table of Figure 214. The LDPC encoding unit 21 of the transmitting device 11 obtains the check matrix 如 by using the check matrix initial value table ' as follows. That is, Fig. 216 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. In addition, the check matrix initial value table of FIG. 216 indicates that the check matrix η of the code rate r of 2,200, which is a code length of 16200 bits, which is specified by the specification of DVB-S.2 shown in FIG. Matrix initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix ηα2 1 according to the code length Ν of the Ldpc code and the information length κ of the Ldpc code, every 360 lines (the number of rows of the tour structure unit Ρ In the first column, check the column number of the 1st line of the l+36〇x(il) of the matrix 135 135786.doc •251 _ 200937872 (Check the column number of the first column of the matrix) Set as the number of the column) only the number of rows of the line of the l + 360x (il) line. In this case, the parity matrix 对应τ corresponding to the co-located long Μ is formed into a step structure ’, which is determined in advance. According to the check matrix initial value table, the information matrix 对应 corresponding to the information length κ in the check matrix 可 can be obtained. The number of columns k+Ι of the check matrix initial value table differs depending on the information length κ. Between the information length K and the number k+1 of the check matrix initial value table, the 〇 relationship of the following formula holds. K = (k + l) x 360 where 360 of the above formula is the number of rows p of the unit of the tour structure. The check matrix initial value table in Fig. 216 has 13 values arranged from the 1st column to the 3rd column, and three values are arranged from the 4th column to the k+th column (the 30th column in Fig. 216). Therefore, the check weight H ❹ of the check matrix H 求出 obtained from the check matrix initial value table of FIG. 216 is from the 1st line to the 1+36〇χ(3-1)-1 behavior 13 from the 1st + 3 60>;< (3-1) line to the first 1 action 3. The first column of the check matrix initial value table of FIG. 216 is 〇, 2〇84, ι613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 'this is expressed in the check matrix Η 1 line, the column number is 0, 2084, 1613, 1548, 1286 '1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are the elements! (and other elements are 0). Moreover, the second column of the check matrix initial value table of FIG. 216 is 1, 122, 135786.doc • 252·200937872 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108. Indicated in the 361th (=1 + 36 〇χ (2 - 1)) row of the inspection matrix H, the column numbers are 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, The element of 3108 is 1. As above, the check matrix initial value table will check the position of the element of the matrix of the matrix 以 1 per 360 lines. Check the line other than the 1+360x(il) line of the matrix ,, that is, the line from the 2+36〇x(il) line to the 36th 〇 line will be determined by checking the matrix initial value table. The element 1 of the l+36〇x(il) line is periodically cyclically shifted in accordance with the same-length length μ (downward direction of the line). That is, for example, the 2+36〇x(il) line only shifts the i+36〇x(il) line downward by only M/360 (=q), followed by the 3+36〇χ ( Μ) The line system rotates the l+36〇x(il) line downward only by 2><M/360(=2xq) (the second 2+36〇x(il) line is only looped downward Shift M/360 (=q)). Now, if the value of the jth row (jth from the left) of the i-th column of the matrix initial value table (from the top) is expressed as hjj, and the first w-row of the matrix η is checked. If the number of the elements of the j1 is expressed as Hw_j, the column number 11 of the element of the wth line of the line other than the 1+36〇χ(i-Ι) line of the matrix 检查 is checked by the following formula. Out.
Hw.j=mod{hu+ m〇d((w-l),P)xqsM} 於此,m〇d(x,y)係意味以y除以χ後之餘數。 而且,P為上述巡迴構造之單位之行數,例如於Dvb-S.2之規格為360。進一步而言,q係藉由以巡迴構造之單 135786.doc • 253 - 200937872 位之行數P(=360)除算同位長Μ所獲得之值M/360。 LDPC編碼部21係藉由檢查矩陣初始值表,特定出檢查 矩陣Η之第l+36〇x(i-l)行之1之要素之列號碼。 進一步而言,LDPC編碼部21係求出檢查矩陣Η之第 1 + 36〇\(丨-1)行以外之行之第评行之1之要素之列號碼!^.3, 生成藉由以上所獲得之列號碼之要素設作1之檢查矩陣Η。 接著,說明關於藉由發送裝置11之解多工器25之替換部 32所進行之替換處理之LDPC碼之碼位元之替換方式,亦 〇 即LDPC碼之碼位元與表示符元之符元位元之分配模式(以 下亦稱位元分配模式)之變化。 於解多工器25,LDPC碼之碼位元係於縱行方向X橫列方 向為(N/(mb))x(mb)位元之記憶體31之縱行方向寫入,其後 以mb位元單位,於橫列方向讀出。進一步而言,於解多工 器25,在替換部32替換於記憶體31之橫列方向讀出之mb位 元之碼位元,替換後之碼位元成為(連續)b個符元之mb位 元之符元位元。 亦即,替換部32係將從讀出自記憶體3 1之橫列方向之 mb位元之碼位元之最高位位元算起第i +1位元作為碼位元 bi,並且將從(連續)b個符元之mb位元之符元位元之最高位 位元算起第i+Ι位元作為符元位元yi,按照特定之位元分配 模式來替換mb位元之碼位元b〇至bmb.!。 圖217係表示於LDPC碼是碼長N為64800位元、編碼率為 5/6或9/10之LDPC碼,進一步調變方式為4096Q AM、倍數 b為1之情況下可採用之位元分配模式之例。 135786.doc • 254· 200937872 LDPC碼是碼長N為64800位元、編碼率為5/6或9/1〇之 LDPC碼,進一步調變方式為4〇96QAM、倍數^丨之情況 下,於解多工器25,於縱行方向x橫列方向為 (64800/(12χ1))χ (12><1)位元之記憶體31寫入之碼位元係於 橫列方向,以12x1 (=mb)位元單位讀出,並供給至替換部 32 〇 替換部32係以將讀出自記憶體31之12><1(=1111))位元之碼 位元b〇至bu ’如圖217所示分配給i(=b)個符元之 12xl(=mb)位元之符元位元y。至yn之方式,來替換 12xl(=mb)位元之碼位元bQ至bn。 亦即’若根據圖217,替換部32係就碼長N為64800位元 之LDPC碼中之編碼率為5/6之LDPC碼、及編碼率為9/10之 LDPC碼而言,關於任一 LDPC碼均分別: 將碼位元bG分配給符元位元y8, 將碼位元bh分配給符元位元y〇, 將碼位元b2分配給符元位元y6, 將碼位元b3分配給符元位元y i, 將碼位元b4分配給符元位元y4, 將碼位元b5分配給符元位元y5, 將碼位元b6分配給符元位元y2, 將碼位元b7分配給符元位元y3, 將碼位元b8分配給符元位元y7, 將碼位元b9分配給符元位元y 1 〇, 將碼位元1)1()分配給符元位元yu, 135786.doc •255 - 200937872 將碼位元b!!分配給符元位元y 9, 而進行替換。 圖218係表示於LDPC碼是碼長N為64800位元、編碼率為 5/6或9/10之LDPC碼,進一步調變方式為4096QAM、倍數 b為2之情況下可採用之位元分配模式之例。 LDPC碼是碼長N為64800位元、編碼率為5/6或9/10之 LDPC碼,進一步調變方式為4096QAM、倍數b為2之情況 下,於解多工器25,於縱行方向X橫列方向為(64800/ 〇 (12x2))x( 12x2)位元之記憶體31寫入之碼位元係於橫列方 向,以12x2(=mb)位元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體31之12x2(=mb)位元之碼 位元bG至b23,如圖21 8所示分配給連續2(=b)個符元之 12x2(=mb)位元之符元位元yG至y23之方式,來替換 12x2(=mb)位元之碼位元b〇至b23。 亦即,若根據圖218,替換部32係就碼長N為64800位元 之LDPC碼中之編碼率為5/6之LDPC碼、及編碼率為9/10之 LDPC碼而言,關於任一LDPC碼均分別: 將碼位元bG分配給符元位元y8, 將碼位元b2分配給符元位元y〇, 將碼位元b4分配給符元位元y6, 將碼位元b6分配給符元位元y!, 將碼位元b8分配給符元位元y4, 將碼位元b! 〇分配給符元位元y 5, 將碼位元b 12分配給符元位元y 2, 135786.doc -256- 200937872 將碼位元bi4分配給符元位元y3 ’ 將碼位元bi6分配給符元位元y7 ’ 將碼位元b 18分配給符元位元y 1 〇 ’ 將碼位元b2G分配給符元位元yii ’ 將碼位元b22分配給符元位元y9 ’ 將碼位元卜分配給符元位元y2G ’ 將碼位元b3分配給符元位元y 1 2, 將碼位元bs分配給符元位元y 18 ’ © 將碼位元b7分配給符元位元)^3, 將碼位元bg分配給符元位元y! 6, 將碼位元b 11分配給符元位元y 17 ’ 將碼位元b 13分配給符元位元y 14 ’ 將碼位元b15分配給符元位元丫15, 將碼位元bi7分配給符元位元y19, 將碼位元b 1 9分配給符元位元y 22, 將碼位元b2 1分配給符元位元y23, ❹ 將碼位元b23分配給符元位元y21, 而進行替換。 於此’圖21 8之位元分配模式係直接利用倍數i之情 況下之圖217之位元分配模式。亦即,於圖218,碼位元 b〇,b2,· · ·,t>22對符元位元yi之分配方式及碼位元 bi,t>3,· · .,b23對符元位元力之分配方式兩者均與圖217之 碼位元b〇至bn對符元位元yi之分配方式相同。 圖219係表示調變方式為1024(^八]^,且1^?(:碼是碼長1^ 135786.doc -257- 200937872 為16200位元、編碼率為3/4、5/6或8/9之LDPC碼,倍數b 為2之情況,及LDPC碼是碼長N為64800位元、編碼率為 3/4、5/6或9/10之LDPC碼,倍數b為2之情況下可採用之位 元分配模式之例。 LDPC碼是碼長N為16200位元、編碼率為3/4、5/6或8/9 之LDPC碼,進一步調變方式為1024QAM、倍數b為2之情 況下,於解多工器25,於縱行方向X橫列方向為(16200/ (1〇χ2))χ(1〇χ2)位元之記憶體31寫入之碼位元係於橫列方 © 向,以l〇x2(=mb)位元單位讀出,並供給至替換部32。 而且,LDPC碼是碼長N為64800位元、編碼率為3/4、 5/6或9/10之LDPC碼,進一步調變方式為1024QAM、倍數 b為2之情況下,於解多工器25,於縱行方向X橫列方向為 (64800/( 1〇χ2))χ( 10x2)位元之記憶體31寫入之碼位元係於 橫列方向,以l〇x2(=mb)位元單位讀出,並供給至替換部 32 ° 替換部32係以將讀出自記憶體31之l〇x2(=mb)位元之碼 W 位元1)〇至b19,如圖219所示分配給連續2(=b)個符元之 l〇x2(=mb)位元之符元位元y〇至y19之方式,來替換 1 〇x2(=mb)位元之碼位元bG至bi9。 亦即,若根據圖219,替換部32係就碼長N為16200位元 之LDPC碼中之編碼率為3/4之LDPC碼、編碼率為5/6之 LDPC碼及編碼率為8/9之LDPC碼,以及碼長N為64800位 元之LDPC碼中之編碼率為3/4之LDPC碼、編碼率為5/6之 LDPC碼及編碼率為9/10之LDPC碼而言,關於任一 LDPC碼 135786.doc -258 - 200937872 均分別: 將碼位元b〇分配給符元位元y8, 將碼位元b】分配給符元位元y3 ’ 將碼位元b2分配給符元位元y7, 將碼位元b3分配給符元位元y 1(), 將碼位元b4分配給符元位元y19, 將碼位元b5分配給符元位元y4, 將碼位元%分配給符元位元y9, 將碼位元1)7分配給符元位元y5, 將碼位元b8分配給符元位元yn, 將碼位元b9分配給符元位元y6, 將碼位元131{)分配給符元位元丫14, 將碼位元b!丨分配給符元位元y! t, 將碼位元b12分配給符元位元y2, 將碼位元b丨3分配給符元位元乃8, 將碼位元b14分配給符元位元y16, 將碼位元b15分配給符元位元y15, 將碼位元1?〗6分配給符元位元y〇, 將碼位元b17分配給符元位元y丨, 將碼位元b18分配給符元位元713, 將碼位元b19分配給符元位元乂^, 而進行替換。 圖220係表示調變方式為4096QAM,且LDPC碼是碼長N 為162〇0位元、編碼率為5/6或8/9之LDPC碼,倍數b為2之 135786.doc -259- 200937872 情況’及LDPC竭是碼長n為64800位元、編碼率為5/6或 9/10之LDPC碼,倍數b為2之情況下可採用之位元分配模 式之例。 LDPC碼是碼長N為16200位元、編碼率為5/6或8/9之 LDPC碼’進一步調變方式為4〇96qam、倍數b為2之情況 下,於解多工器25,於縱行方向X橫列方向為(16200/ (12x2))x(12x2)位元之記憶體31寫入之碼位元係於橫列方 向,以12x2(=mb)位元單位讀出,並供給至替換部32。 ❹ 而且’ LDPC^是碼長N為64800位元、編碼率為5/6或 9/10之LDPC碼’進一步調變方式為4〇96qAM、倍數以2 之情況下,於解多工器25,於縱行方向X橫列方向為 (64800/(12x2))x(12x2)位元之記憶體31寫入之碼位元係於 橫列方向’以12x2(=mb)位元單位讀出,並供給至替換部 32。 替換部32係以將讀出自記憶體31之I2x2(=mb)位元之碼 位元bG至bn,如圖220所示分配給連續2(=b)個符元之 ❹ 12x2( = mb)位元之符元位元y。至y23之方式,來替換 12><2(=mb)位元之碼位元bQ至b23。 亦即’若根據圖220,替換部32係就碼長N為16200位元 之LDPC碼中之編碼率為5/6之LDPC碼及編碼率為8/9之 LDPC碼,以及碼長N為64800位元之LDPC碼中之編碼率為 5/6之LDPC碼及編碼率為9/10之LDPC碼而言,關於任一 LDPC碼均分別: 將碼位元b 〇分配給符元位元y t 〇, 135786.doc -260- 200937872 將碼位元b!分配給符元位元y! 5, 將碼位元b2分配給符元位元y4, 將碼位元b 3分配給符元位元y 19 ’ 將碼位元b4分配給符元位元y21, 將碼位元b5分配給符元位元y!6, 將碼位元b6分配給符元位元y23, 將碼位元b7分配給符元位元y 18, 將碼位元b8分配給符元位元y 11, Ο 將碼位元b9分配給符元位元y 14, 將碼位元b! 〇分配給符元位元y22, 將碼位元b u分配給符元位元y 5, 將碼位元b i 2分配給符元位元y 6, 將碼位元b! 3分配給符元位元y! 7, 將碼位元b 14分配給符元位元y! 3, 將碼位元b ! 5分配給符元位元y 20, 將碼位元b i 6分配給符元位元y 1, 將碼位元b! 7分配給符元位元y 3, 將碼位元b! 8分配給符元位元y 9, 將碼位元b ! 9分配給符元位元y 2, 將碼位元b2G分配給符元位元y7, 將碼位元b21分配給符元位元y8, 將碼位元b22分配給符元位元y!2, 將碼位元b23分配給符元位元y〇, 而進行替換。 •261 - 135786.doc 200937872 若根據圖2 1 7至圖220所示之位元分配模式,則關於複數 種類之LDPC碼可採用同一位元分配模式,而且關於該複 數種類之LDPC碼之任一種,均可使對於錯誤之耐受性成 為所需性能。 亦即,圖221至圖224係表示按照圖217至圖220之位元分 配模式進行替換處理之情況下之BER(Bit Error Rate :位元 錯誤率)之模擬結果。 此外,於圖221至圖224,橫軸表示Es/N〇(每1符元之信號 Ο 電力對雜訊電力比),縱軸表示BER。 而且,實線表示已進行替換處理之情況下之BER,1點 短劃線表示未進行替換處理之情況下之BER。 圖221係表示針對碼長N為64800、編碼率分別為5/6及 9/10之LDPC碼,作為調變方式採用4096QAM,倍數b設作 1,按照圖2 1 7之位元分配模式進行替換處理之情況下之 BER。 圖222係表示針對碼長N為64800、編碼率分別為5/6及 w 9/10之LDPC碼,作為調變方式採用4096QAM,倍數b設作 2,按照圖2 1 8之位元分配模式進行替換處理之情況下之 BER。 此外,於圖221及圖222,附有三角形標記之曲線圖表示 關於編碼率為5/6之LDPC碼之BER,附有星標(星形標記) 之曲線圖表示關於編碼率為9/10之LDPC碼之BER。 圖223係表示針對碼長N為16200、編碼率分別為3/4、 5/6及8/9之LDPC碼及碼長N為64800、編碼率分別為3/4、 135786.doc -262- 200937872 5/6及9/10之1^1>(:碼,作為調變方式採用1〇24(^入]^,倍數 b設作2,按照圖219之位元分配模式進行替換處理之情況 下之BER。 此外,於圖223,附有星標之曲線圖表示關於碼長 64800、編碼率為9/l〇2LDPC碼之BER,附有朝上之三角 形標記之曲線圖表示關於碼長N為64800、編碼率為5/6之 LDPC碼之BER。而且’附有正方形標記之曲線圖係表示 關於碼長N為64800、編碼率為3/4iLDpc碼之BER。 進一步而s ’於圖223,附有圓圈標記之曲線圖表示關 於碼長N為1620〇、編碼率為8/9之LDPC碼之BER,附有朝 下之二角形標記之曲線圖表示關於碼長N為16200、編碼率 為5/6之LDPC碼之BERe而且,附有正號標記之曲線圖係 表示關於碼長N為16200、編碼率為3/4之LDPC碼之BER » 圖224係表示針對碼長N為16200、編碼率分別為5/6及 8/9之LDPC碼及碼長n為64800、編碼率分別為5/6及9/10之 LDPC碼’作為調變方式採用4〇96qAM,倍數b設作2,按 照圖220之位元分配模式進行替換處理之情況下之ber。 此外’於圖224 ’附有星標之曲線圖表示關於碼長n為 64800、編碼率為9/1〇之LDPC碼之BER,附有朝上之三角 形標記之曲線圓表示關於碼長N為64800、編碼率為5/6之 LDPC碼之BER 〇 而且’於圖224,附有圓圈標記之曲線圖表示關於碼長n 為16200、編碼率為8/9之LDpc碼之BER,附有朝下之三角 形標記之曲線圖表示關於碼長N為16200、編碼率為5/6之 135786.doc -263 - 200937872 L D P C 碼之 B E R 〇 若根據圖221至圖224,關於複數種類之LDPC碼可採用 同一位元分配模式,而且關於採用同一位元分配模式之複 數種類之LDPC碼之任一種,均可使對於錯誤之耐受性成 為所需性能。 亦即,關於碼長或編碼率不同之複數種類之LDPC碼, 分別採用該LDPC碼所專用之位元分配模式之情況時,雖 可使對於錯誤之耐受性極為高性能,但必須就不同種類之 O LDPC碼逐一變更位元分配模式。 另一方面,若根據圖217至圖220之位元分配模式,關於 碼長或編碼率不同之複數種類之LDPC碼各個可採用同一 位元分配模式,關於複數種類之LDPC碼各個,無須如採 用該LDPC碼所專用之位元分配模式之情況,就不同種類 之LDPC碼逐一變更位元分配模式。 進一步而言,若根據圖217至圖220之位元分配模式,關 於複數種類之LDPC碼各個,即使稍微不及採用該LDPC碼 所專用之位元分配模式之情況,但即使如此仍可使對於錯 誤之耐受性為高性能。 亦即,例如調變方式為4096QAM之情況下,就碼長N為 64800、編碼率分另ij為5/6及9/10之LDPC碼而言,關於任一 LDPC碼均可採用圖217或圖218之同一位元分配模式。然 後,如此,即使採用同一位元分配模式,仍可使對於錯誤 之耐受性為高性能。 進一步而言,例如調變方式為1024QAM之情況下,就碼 135786.doc -264- 200937872 長N為16200、編碼率分別為3/4、5/6及8/9之LDPC碼,及 碼長N為64800、編碼率分別為3/4、5/6及9/10之LDPC碼而 言,關於任一 LDPC碼均可採用圖219之同一位元分配模 式。然後,如此’即使採用同一位元分配模式,仍可使對 於錯誤之耐受性為高性能。 而且’例如調變方式為4096QAM之情況下,就碼長N為 16200、編碼率分別為5/6及8/9之LDPC碼,及碼長N為 64800、編碼率分別為5/6及9/10之LDPC碼而言,關於任一 〇 LDPC碼均可採用圖220之同一位元分配模式。然後,如 此’即使採用同一位元分配模式,仍可使對於錯誤之耐受 性為高性能。 進一步說明關於位元分配模式之變化。 圖225係表示於LDPC碼是碼長N為16200或64800位元、 編碼率由例如從圖170至圖215所示之檢查矩陣初始值表所 生成之檢查矩陣Η所定義之LDPC碼之編碼率中之3/5以外 之LDPC碼,進一步調變方式為qPSK、倍數b為1之情況下 可採用之位元分配模式之例 LDPC碼是碼長N為16200或64800位元、編碼率為3/5以 外之LDPC碼’進一步調變方式為qPSK、倍數之情況 下’於解多工器25,於縱行方向X橫列方向為 (>4/(2><1))><(2><1)位元之記憶體31寫入之碼位元係於橫列方 向’以2x1 (==mb)位元單位讀出,並供給至替換部32。 替換部3 2係以將讀出自記憶體3 1之2 X 1 (=mb)位元之瑪位 元〜及!^ ’如圖225所示分配給i(=b)個符元之2xl(=mb)位 135786.doc -265- 200937872 元之符元位元y〇及yi之方式,來替換2x1 (=mb)位元之碼位 元b〇及bi ° 亦即,若根據圖225,替換部32係分別: 將碼位元bG分配給符元位元y〇, 將碼位元b!分配給符元位元y!, 而進行替換。 此外,該情況下,亦可思慮不進行替換,碼位元1?()及1)1 分別直接作為符元位元yc及yi。 〇 圖226係表示於LDPC碼是碼長N為16200或64800位元、 編碼率為3/5以外之LDPC碼,進一步調變方式為16Q AM、 倍數b為2之情況下可採用之位元分配模式之例。 LDPC碼是碼長N為16200或64800位元、編碼率為3/5以 外之LDPC碼,進一步調變方式為16QAM、倍數b為2之情 況下,於解多工器25,於縱行方向X橫列方向為(Ν/(4χ2))χ (4x2)位元之記憶體3 1寫入之碼位元係於橫列方向,以 4x2(=mb)位元單位讀出,並供給至替換部32。 ® 替換部32係以將讀出自記憶體31之4x2(=mb)位元之碼位 元bG至b7,如圖226所示分配給連續2(=b)個符元之 4x2(=mb)位元之符元位元y〇至y7之方式,來替換4x2(=mb) 位元之碼位元bG至b7。 亦即,若根據圖226,替換部32係分別: 將碼位元bG分配給符元位元y7, 將碼位元b 1分配給符元位元y 1, 將碼位元b2分配給符元位元y4, 135786.doc -266- 200937872 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y5, 將碼位元b5分配給符元位元y3, 將碼位元b6分配給符元位元y6, 將碼位元b7分配給符元位元y〇, 而進行替換。 圖227係表示調變方式為64QAM,且LDPC碼是碼長N為 16200或64800位元、編碼率為3/5以外之LDPC碼,倍數b Ο 為2之情況下可採用之位元分配模式之例。 LDPC碼是碼長N為16200或64800位元、編碼率為3/5以 外之LDPC碼,進一步調變方式為64QAM、倍數b為2之情 況下,於解多工器25,於縱行方向X橫列方向為(Ν/(6χ2))χ (6x2)位元之記憶體3 1寫入之碼位元係於橫列方向,以 6x2(=mb)位元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體31之6x2(=mb)位元之碼位 元bQ至bn,如圖227所示分配給連續2(=b)個符元之 ® 6x2(=mb)位元之符元位元y〇至yi丨之方式,來替換6x2(=mb) 位元之瑪位元bG至b!!。 亦即,若根據圖227,替換部32係分別: 將碼位元bG分配給符元位元y!!, 將碼位元b i分配給符元位元y 7, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元)^〇, 將碼位元b4分配給符元位元y6, 135786.doc -267- 200937872 將碼位元b5分配給符元位元y2, 將碼位元b6分配給符元位元y9, 將碼位元b7分配給符元位元y5, 將碼位元bs分配給符元位元y j, 將瑪位元bg分配給符元位元y8, 將碼位元bi〇分配給符元位元y4, 將碼位元b 1 1分配給符元位元y〇, 而進行替換。 圖228係表示調變方式為256QAM,且LDPC碼是碼長N 為64800位元、編碼率為3/5以外之LDPC碼,倍數b為2之 情況下可採用之位元分配模式之例。 LDPC碼是碼長N為64800位元、編碼率為3/5以外之 ldpc碼,進一步調變方式為256QAM、倍數ba2之情況 下,於解多工器25,於縱行方向X橫列方向為(648〇〇/ (8x2))x(8x2)位元之記憶體31寫入之碼位元係於橫列方 向,以8x2(=mb)位元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體3128x2(=mb)位元之碼位 元bG至bls,如圖228所示分配給連續2(=b)個符元之 8x2(=mb)位元之符元位元y〇至yi5之方式,來替換8χ2(=_ 位元之碼位元bG至b15。 亦即,若根據圖228,替換部32係分別: 將碼位元bG分配給符元位元yi5 , 將碼位元b〗分配給符元位元yi, 將碼位元bz分配給符元位元713, 135786.doc -268- 200937872 將碼位元b3分配給符元位元y3, 將碼位元b4分配給符元位元y8, 將碼位元b5分配給符元位元y u ’ 將碼位元b6分配給符元位元y9, 將碼位元b7分配給符元位元y5, 將碼位元1)8分配給符元位元丫1(), 將碼位元b9分配給符元位元y6, 將碼位元bi〇分配給符元位元y4, 將碼位元b 1〗分配給符元位元y7, 將碼位元b12分配給符元位元712, 將碼位元b ! 3分配給符元位元y 2, 將碼位元b14分配給符元位元丫14, 將碼位元b15分配給符元位元y〇, 而進行替換。 圖229係表示調變方式為256qam,且LDPC碼是碼長N 為16200位元、編碼率為3/5以外之LDpc碼,倍數b為1之 情況下可採用之位元分配模式之例。 LDPC碼是碼長n為162〇0位元、編碼率為3/5以外之 ldpc碼,進一步調變方式為256QAM、倍數bai之情況 下於解多工器25,於縱行方向X橫列方向為(16200/ (8 1))χ(8χ1)位兀之記憶體31寫入之碼位元係於橫列方 向,以8Xl(=mb)位元單位讀出,並供給至替換部32。 —替換部32係以將讀出自記憶體31之8><1(=响位元之瑪位 心。至b7,如圖229所示分配給】㈣個符元之“=_位 135786.doc •269· 200937872 元之符元位元y〇至y?之方式,來替換8><i(=mb)位元之碼位 元b〇至b7。 亦即’若根據圖229,替換部32係分別: 將碼位元b〇分配給符元位元y7, 將碼位元心分配給符元位元y3, 將碼位元t>2分配給符元位元yi, 將碼位元b>3分配給符元位元y5, 將碼位元b4分配給符元位元y2, 將碼位元bs分配給符元位元y6, 將碼位元b6分配給符元位元h, 將碼位元b7分配給符元位元乃, 而進行替換。 圖230係表示於LDPC碼是碼長N為16200或64800位元、 編碼率為3/5之LDPC碼,進一步調變方式為QPSK、倍數b 為1之情況下可採用之位元分配模式之例。 LDpC碼是碼長N為16200或04800位元、編碼率為3/5之 LDPC碼,進一步調變方式為QPSK、倍數b為1之情況下, 於解多工器25,於縱行方向x橫列方向為(Ν/(2χ 位兀之s己憶體3 1寫入之碼位元係於橫列方向,以2χ丨(=mb) 位元單位讀出,並供給至替換部32。 替換邛32係以將讀出自記憶體31之2><1(=11^)位元之碼位 兀〜及卜,如圖230所示分配給1(=13)個符元之2xl(=mb)位 元之符元位元丫。及乃之方式,來替換2xl(=mb)位元之碼位 元b〇及bj。 135786.doc -270 200937872 亦即,若根據圖230,替換部32係分別: 將碼位元bG分配給符元位元y〇, 將碼位元b i分配給符元位元y i, 而進行替換。 此外,該情況下,亦可思慮不進行替換,碼位元1)〇及b, 分別直接作為符元位元yc及y 1。 圖231係表示於LDPC碼是碼長N為64800位元、編碼率為 3/5之LDPC碼,進一步調變方式為16QAM、倍數b為2之情 〇 況下可採用之位元分配模式之例。 LDPC碼是碼長N為64800位元、編碼率為3/5之LDPC 碼,進一步調變方式為16QAM、倍數b為2之情況下,於解 多工器25,於縱行方向X橫列方向為(64800/(4χ2))χ(4χ2)位 元之記憶體3 1寫入之碼位元係於橫列方向,以4x2(=mb)位 元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體31之4x2(=mb)位元之碼位 元b〇至b7,如圖23 1所示分配給連續2(=b)個符元之 ❿ 4><2(=mb)位元之符元位元丫〇至77之方式,來替換4x2(=mb) 位元之碼位元bG至b7。 亦即,若根據圖23 1,替換部32係分別: 將碼位元bG分配給符元位元y〇, 將碼位元b!分配給符元位元y 5, 將碼位元b2分配給符元位元y 1, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元y4, 135786.doc -271 - 200937872 將碼位元b5分配給符元位元y7, 將碼位元b6分配給符元位元y3, 將碼位元b7分配給符元位元y6, 而進行替換。 圖232係表示於LDPC碼是碼長N為16200位元、編碼率為 3/5之LDPC碼,進一步調變方式為16QAM、倍數b為2之情 況下可採用之位元分配模式之例。Hw.j=mod{hu+ m〇d((w-l), P)xqsM} Here, m〇d(x, y) means dividing y by the remainder after χ. Further, P is the number of rows of the above-described tour structure, and for example, the specification of Dvb-S.2 is 360. Further, q is obtained by dividing the value M/360 obtained by the isometric length by the number of rows P (=360) of the 135786.doc • 253 - 200937872 bits. The LDPC encoding unit 21 specifies the column number of the element of the first + + 36 〇 x (i - 1) row of the check matrix 藉 by checking the matrix initial value table. Further, the LDPC encoding unit 21 obtains the column number of the element of the first comment line of the line other than the 1 + 36 〇 ((-1) line of the check matrix !! ^.3, Generate an inspection matrix 设 set to 1 by the elements of the column number obtained above. Next, a description will be given of an alternative manner of the code bit of the LDPC code by the replacement unit 32 of the demultiplexer 25 of the transmitting device 11, that is, the code bit of the LDPC code and the symbol of the symbol. The change of the allocation mode of the meta-bit (hereinafter also referred to as the bit allocation mode). In the demultiplexer 25, the code bits of the LDPC code are written in the wale direction of the memory 31 in the direction of the X direction of the X direction (N/(mb)) x (mb) bits, and thereafter The mb bit unit is read in the horizontal direction. Further, in the demultiplexer 25, the replacement bit 32 is replaced with the code bit of the mb bit read in the course direction of the memory 31, and the replaced code bit becomes (continuous) b symbols. The oct bit of the mb bit. That is, the replacing unit 32 counts the i-th +1 bit from the most significant bit of the code bit of the mb bit read from the course direction of the memory 3 as the code bit bi, and will Continuously) the highest bit of the mb bit of the b-bit symbol, the i-th bit is calculated as the symbol bit yi, and the code position of the mb bit is replaced according to the specific bit allocation pattern. Yuan b〇 to bmb.!. Figure 217 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10, and the bit can be used when the modulation mode is 4096Q AM and the multiple b is 1. An example of a distribution model. 135786.doc • 254· 200937872 LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 5/6 or 9/1〇. Further modulation is 4〇96QAM, multiples丨, The multiplexer 25 is written in the direction of the x direction in the x direction (64800 / (12 χ 1)) χ (12 >< 1) bits of the memory 31 written in the horizontal direction, to 12x1 The (=mb) bit unit is read and supplied to the replacement unit 32. The replacement unit 32 is configured to read the code bits b from the 12><1 (=1111) bits of the memory 31 to the bu ' The symbol bit y assigned to the 12xl (= mb) bit of i (= b) symbols is as shown in FIG. To the yn mode, replace the code bits bQ to bn of 12xl (= mb) bits. That is, according to FIG. 217, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having a coding rate of 9/10 in an LDPC code having a code length N of 64,800 bits. An LDPC code is respectively assigned: a code bit bG is assigned to a symbol bit y8, a code bit bh is assigned to a symbol bit y, a code bit b2 is assigned to a symbol bit y6, and a code bit is assigned B3 is assigned to the symbol bit yi, the code bit b4 is assigned to the symbol bit y4, the code bit b5 is assigned to the symbol bit y5, and the code bit b6 is assigned to the symbol bit y2, the code is Bit b7 is assigned to symbol bit y3, code bit b8 is assigned to symbol bit y7, code bit b9 is assigned to symbol bit y 1 〇, and code bit 1)1() is assigned to The symbol bit yu, 135786.doc • 255 - 200937872 assigns the code bit b!! to the symbol bit y 9, and replaces it. Figure 218 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The bit modulation can be used in the case where the modulation mode is 4096QAM and the multiple b is 2. An example of a pattern. The LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the traversing. The code bit written by the memory 31 in the direction X direction of the (64800/〇(12x2))x(12x2) bit is in the course direction, read out in 12x2 (=mb) bit units, and supplied To the replacement unit 32. The replacing unit 32 assigns the code bits bG to b23 read from the 12x2 (= mb) bits of the memory 31 to 12x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bit elements yG to y23 of the bit are replaced by the code bits b〇 to b23 of 12x2 (= mb) bits. That is, according to FIG. 218, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and an LDPC code having a coding rate of 9/10. An LDPC code is respectively assigned: a code bit bG is assigned to a symbol bit y8, a code bit b2 is assigned to a symbol bit y, a code bit b4 is assigned to a symbol bit y6, and a code bit is assigned B6 is assigned to the symbol bit y!, the code bit b8 is assigned to the symbol bit y4, the code bit b! 〇 is assigned to the symbol bit y 5 , and the code bit b 12 is assigned to the symbol bit Element y 2, 135786.doc -256- 200937872 assigning code bit bi4 to symbol bit y3 ' assigning code bit bi6 to symbol bit y7 ' assigning code bit b 18 to symbol bit y 1 〇 'Assign code bit b2G to symbol bit yii ' Assign code bit b22 to symbol bit y9 ' Assign code bit B to symbol bit y2G ' Assign code bit b3 to character The meta-bit y 1 2, the code bit bs is assigned to the symbol y 18 ' © to assign the code bit b7 to the symbol bit ^3, and the code bit bg is assigned to the symbol y! 6, assign code bit b 11 to symbol bit y 17 ' The element b 13 is assigned to the symbol bit y 14 '. The code bit b15 is assigned to the symbol bit 丫 15, the code bit bi7 is assigned to the symbol y19, and the code bit b 1 9 is assigned to the symbol The bit y 22 assigns the code bit b2 1 to the symbol bit y23, and assigns the code bit b23 to the symbol bit y21 for replacement. Here, the bit allocation pattern of Fig. 21 is a bit allocation pattern of Fig. 217 in the case where the multiple i is directly used. That is, in FIG. 218, the code bit b〇, b2, . . . , t>22 is assigned to the symbol bit yi and the code bit bi, t > 3, · · ·, b23 is the symbol bit The distribution method of Yuanli is the same as the allocation of the symbol bits b〇 to bn of FIG. 217 to the symbol bits yi. Figure 219 shows that the modulation mode is 1024 (^8)^, and 1^?(: code is code length 1^ 135786.doc -257- 200937872 is 16200 bits, coding rate is 3/4, 5/6 or 8/9 LDPC code, the case where the multiple b is 2, and the LDPC code is an LDPC code with a code length N of 64,800 bits, a coding rate of 3/4, 5/6 or 9/10, and a multiple b is 2. An example of a bit allocation pattern that can be used. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, 5/6 or 8/9, and further modulation is 1024QAM, and the multiple b is In the case of 2, in the demultiplexer 25, the code bit written in the memory 31 in the direction of the X direction of the X direction (16200 / (1 〇χ 2)) χ (1 〇χ 2) bit is attached to The horizontal direction © is read out in units of l〇x2 (= mb) and supplied to the replacement unit 32. Moreover, the LDPC code has a code length N of 64,800 bits and a coding rate of 3/4, 5/6. Or 9/10 LDPC code, if the modulation mode is 1024QAM and the multiple b is 2, in the multiplexer 25, the direction of the X direction in the wale direction is (64800/(1〇χ2)) χ ( The code bits written by the 10x2) bit memory 31 are in the horizontal direction, read in units of l〇x2 (= mb) bits, and supplied to The 32° replacement unit 32 is configured to transfer the code W bit 1 read from the memory 31x2 (= mb) bit to the b19, and is assigned to consecutive 2 (=b) characters as shown in FIG. Replace the code bits bG to bi9 of 1 〇x2 (= mb) bits by the way of the symbol y〇 to y19 of the l〇x2 (= mb) bit. That is, according to FIG. 219, The replacing unit 32 is an LDPC code having an encoding rate of 3/4 in an LDPC code having a code length N of 16,200 bits, an LDPC code having a coding rate of 5/6, and an LDPC code having an encoding rate of 8/9, and a code length. N is an LDPC code with a coding rate of 3/4 in an LDPC code of 64,800 bits, an LDPC code with a coding rate of 5/6, and an LDPC code with a coding rate of 9/10, with respect to any LDPC code 135786.doc -258 - 200937872 are respectively assigned: the code bit b〇 is assigned to the symbol bit y8, the code bit b] is assigned to the symbol bit y3 ', and the code bit b2 is assigned to the symbol bit y7, the code is Bit b3 is assigned to symbol bit y 1(), code bit b4 is assigned to symbol bit y19, code bit b5 is assigned to symbol bit y4, and code bit % is assigned to symbol bit Element y9, assigning code bit 1)7 to symbol bit y5, and assigning code bit b8 to symbol bit yn, The code bit b9 is assigned to the symbol bit y6, the code bit element 131{) is assigned to the symbol bit 丫14, and the code bit b!丨 is assigned to the symbol bit y!t, the code bit b12 Assigned to the symbol bit y2, the code bit b丨3 is assigned to the symbol bit 8 , the code bit b14 is assigned to the symbol bit y16, and the code bit b15 is assigned to the symbol bit y15. The code bit 1? 6 is assigned to the symbol bit y, the code bit b17 is assigned to the symbol bit y, the code bit b18 is assigned to the symbol bit 713, and the code bit b19 is assigned. Replace the symbol bit 乂^. Figure 220 shows that the modulation mode is 4096QAM, and the LDPC code is an LDPC code with a code length N of 162 〇 0 bits, a coding rate of 5/6 or 8/9, and a multiple b of 135786.doc -259- 200937872 The case 'and the LDPC are examples of the bit allocation pattern that can be used in the case where the code length n is 64,800 bits, the coding rate is 5/6 or 9/10, and the multiple b is 2. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6 or 8/9. In the case where the modulation method is 4〇96qam and the multiple b is 2, the multiplexer 25 is used in the multiplexer 25, The code bit written in the memory 31 in the wale direction X direction of the (16200/(12x2)) x (12x2) bit is in the course direction, and is read in units of 12x2 (= mb) bits, and It is supplied to the replacement unit 32. ❹ and 'LDPC^ is an LDPC code with a code length N of 64800 bits and a coding rate of 5/6 or 9/10'. Further modulation is 4〇96qAM, and the multiple is 2, in the multiplexer 25 The code bit written in the memory 31 in the X direction of the X direction of the (64800/(12x2)) x (12x2) bit in the wale direction is read in the horizontal direction 'in 12x2 (= mb) bit units And supplied to the replacement unit 32. The replacing unit 32 is configured to assign the code bits bG to bn read from the I2x2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 220 ❹ 12x2 (= mb) The bit y of the bit. In the manner of y23, the code bits bQ to b23 of 12<2 (= mb) bits are replaced. That is, according to FIG. 220, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having an encoding rate of 8/9 in an LDPC code having a code length N of 16,200 bits, and a code length N being In the 64800-bit LDPC code, the LDPC code with a coding rate of 5/6 and the LDPC code with a coding rate of 9/10 are respectively associated with any LDPC code: the code bit b 〇 is assigned to the symbol bit Yt 〇, 135786.doc -260- 200937872 assign code bit b! to symbol bit y! 5, assign code bit b2 to symbol bit y4, assign code bit b 3 to symbol bit The element y 19 ' assigns the code bit b4 to the symbol bit y21, the code bit b5 to the symbol bit y!6, and the code bit b6 to the symbol bit y23, the code bit b7 Assigned to symbol y 18, assign code bit b8 to symbol y 11, Ο assign code bit b9 to symbol y 14, and assign code bit b! 〇 to symbol Element y22, assigning code bit bu to symbol bit y 5, assigning code bit bi 2 to symbol bit y 6, assigning code bit b! 3 to symbol bit y! 7, The code bit b 14 is assigned to the symbol bit y! 3, and the code bit b ! 5 is assigned to the symbol Element y 20, assigning code bit bi 6 to symbol bit y 1, assigning code bit b! 7 to symbol bit y 3, and assigning code bit b! 8 to symbol bit y 9 , the code bit b 9 is assigned to the symbol bit y 2 , the code bit b2G is assigned to the symbol bit y7 , the code bit b21 is assigned to the symbol bit y8 , and the code bit b22 is assigned to The symbol bit y!2 assigns the code bit b23 to the symbol bit y, and replaces it. • 261 - 135786.doc 200937872 According to the bit allocation pattern shown in Fig. 21 to Fig. 220, the same bit allocation mode can be used for the LDPC code of the plural type, and any one of the LDPC codes of the plural type is used. Both can make the tolerance to the error the required performance. That is, Figs. 221 to 224 show simulation results of BER (Bit Error Rate) in the case where replacement processing is performed in accordance with the bit allocation pattern of Figs. 217 to 220. Further, in Figs. 221 to 224, the horizontal axis represents Es/N 〇 (signal per 1 symbol Ο power to noise power ratio), and the vertical axis represents BER. Further, the solid line indicates the BER in the case where the replacement processing has been performed, and the one-dot dash indicates the BER in the case where the replacement processing is not performed. Figure 221 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. 4096QAM is used as the modulation method, and the multiple b is set to 1, according to the bit allocation mode of Fig. 2.1. Replace the BER in the case of processing. Figure 222 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and w 9/10 respectively. 4096QAM is used as the modulation method, and the multiple b is set to 2, according to the bit allocation pattern of Figure 2 The BER in the case of replacement processing. Further, in FIGS. 221 and 222, a graph with a triangular mark indicates a BER with respect to an LDPC code having a coding rate of 5/6, and a graph with a star mark (star mark) indicates that the coding rate is 9/10. The BER of the LDPC code. Figure 223 shows an LDPC code and a code length N of 64800 for a code length N of 16200 and a coding rate of 3/4, 5/6, and 8/9, respectively, and a coding rate of 3/4, 135786.doc -262- 200937872 5/6 and 9/10 1^1> (: code, as a modulation method, 1〇24(^入)^, multiple b is set to 2, and the replacement processing according to the bit allocation mode of Fig. 219 is performed. In addition, in Fig. 223, a graph with a star indicates a BER with a code length of 64800 and a coding rate of 9/l 〇 2 LDPC code, and a graph with an upward triangular mark indicates a code length N. It is 64800, the BER of the LDPC code with a coding rate of 5/6, and the curve with the square mark indicates the BER with a code length N of 64800 and a coding rate of 3/4 iLDpc code. Further s ' in Figure 223 The graph with the circle mark indicates the BER of the LDPC code with the code length N of 1620 〇 and the coding rate of 8/9, and the graph with the downward-facing digonal mark indicates that the code length N is 16200, and the coding rate is The BER of the 5/6 LDPC code and the graph with the positive sign indicates the BER of the LDPC code with a code length N of 16200 and a coding rate of 3/4. For an LDPC code with a code length N of 16200 and a coding rate of 5/6 and 8/9, and an LDPC code with a code length n of 64800 and a coding rate of 5/6 and 9/10 respectively, 4 is used as the modulation method. 96qAM, the multiple b is set to 2, and ber is replaced in accordance with the bit allocation pattern of Fig. 220. Further, the graph with the star attached to Fig. 224 shows that the code length n is 64800 and the coding rate is 9. The BER of the LDPC code of /1〇, the curve circle with the upward triangular mark indicates the BER of the LDPC code with a code length N of 64800 and a coding rate of 5/6 and is shown in Figure 224 with a circle mark. The graph shows the BER of the LDpc code with a code length n of 16200 and a coding rate of 8/9, and a graph with a downward triangle mark indicating that the code length N is 16200 and the coding rate is 5/6. -263 - 200937872 BER of LDPC code 〇 According to Figures 221 to 224, the same bit allocation mode can be used for the LDPC code of the plural type, and any one of the LDPC codes of the plural type using the same bit allocation mode The tolerance to errors can be made to the desired performance. That is, with regard to code length or coding rate In the case where the LDPC codes of the plural types are respectively used in the bit allocation mode dedicated to the LDPC code, although the tolerance to errors is extremely high, the bits of the different types of O LDPC codes must be changed one by one. Distribution mode. On the other hand, according to the bit allocation pattern of FIG. 217 to FIG. 220, the same bit allocation mode can be adopted for each of the plurality of types of LDPC codes having different code lengths or encoding rates, and it is not necessary to adopt the respective types of LDPC codes. In the case of the bit allocation mode dedicated to the LDPC code, the bit allocation pattern is changed one by one for different types of LDPC codes. Further, according to the bit allocation pattern of FIG. 217 to FIG. 220, for each of the plural types of LDPC codes, even if the bit allocation mode dedicated to the LDPC code is slightly used, even if this is still possible, the error can be made. The tolerance is high performance. That is, for example, in the case where the modulation mode is 4096QAM, for an LDPC code having a code length N of 64800 and a coding rate of ij of 5/6 and 9/10, any LDPC code can be used as shown in FIG. 217 or Figure 218 shows the same bit allocation pattern. Then, even with the same bit allocation mode, the tolerance to errors can be made high performance. Further, for example, in the case where the modulation mode is 1024QAM, the code 135786.doc -264- 200937872 has a length N of 16200, and an LDPC code with a coding rate of 3/4, 5/6, and 8/9, respectively, and a code length. For an LDPC code in which N is 64800 and encoding rates are 3/4, 5/6, and 9/10, respectively, the same bit allocation pattern of FIG. 219 can be used for any LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance. Moreover, for example, in the case where the modulation method is 4096QAM, the code length N is 16200, the coding rate is 5/6 and 8/9 LDPC codes, and the code length N is 64800, and the coding rates are 5/6 and 9 respectively. For the LDPC code of /10, the same bit allocation pattern of FIG. 220 can be used for any 〇LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance. Further explanation of the change in the bit allocation pattern. Figure 225 is a diagram showing the coding rate of the LDPC code defined by the check matrix 生成 generated by the check matrix generated from the check matrix initial value table shown in Figs. 170 to 215, where the LDPC code is a code length N of 16,200 or 64,800 bits. The LDPC code other than 3/5, the case where the modulation mode is qPSK and the multiple b is 1, the LDPC code can be used. The LDPC code has a code length N of 16200 or 64800 bits and a coding rate of 3. The LDPC code other than /5 'further modulation mode is qPSK, multiplier' in the demultiplexer 25, and the X direction in the wale direction is (>4/(2><1))><(2><1) The bit code written by the memory 31 of the bit is read in the column direction '2x1 (== mb) bit unit and supplied to the replacement unit 32. The replacing unit 3 2 assigns the megabytes ~ and !^ ' read from the 2 X 1 (= mb) bits of the memory 3 1 to 2x1 of i (= b) symbols as shown in FIG. 225 ( = mb) 135786.doc -265- 200937872 yuan symbol y 〇 and yi way, to replace the 2x1 (= mb) bit of the code bit b 〇 and bi °, that is, according to Figure 225, The replacing unit 32 respectively assigns the code bit bG to the symbol bit y, and assigns the code bit b! to the symbol bit y!, and replaces it. In addition, in this case, it is also possible to consider not to replace, and the code bits 1?() and 1)1 are directly used as the symbol bits yc and yi, respectively. Figure 226 shows that the LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5. The bit modulation can be used when the modulation mode is 16Q AM and the multiple b is 2. An example of a distribution model. The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The memory element in which the X-direction is (Ν/(4χ2)) χ (4x2) bits is written in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to Replacement section 32. The ® replacement unit 32 is configured to assign the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to 4x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bit elements y〇 to y7 of the bit are replaced by the code bits bG to b7 of the 4x2 (= mb) bits. That is, according to FIG. 226, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol. The meta-bit y4, 135786.doc -266- 200937872 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit y5, and the code bit b5 to the symbol bit y3 The code bit b6 is assigned to the symbol bit y6, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Figure 227 shows that the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5, and the bit allocation mode can be used when the multiple b Ο is 2. An example. The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The memory level in which the X-direction is (Ν/(6χ2)) χ (6x2) bits is written in the horizontal direction, read in units of 6x2 (= mb) bits, and supplied to Replacement section 32. The replacing unit 32 is configured to assign the code bits bQ to bn of the 6x2 (= mb) bits read from the memory 31 to the consecutive 2 (= b) symbols of the standard 6x2 (= mb) as shown in FIG. The bitwise symbol y〇 to yi丨 of the bit replaces the gigabit bG to b!! of the 6x2 (= mb) bit. That is, according to FIG. 227, the replacing unit 32 assigns the code bit bG to the symbol bit y!!, assigns the code bit bi to the symbol bit y 7, and assigns the code bit b2 to The symbol bit y3, the code bit b3 is assigned to the symbol bit), the code bit b4 is assigned to the symbol y6, 135786.doc -267- 200937872 assigns the code bit b5 to the symbol Bit y2, assign code bit b6 to symbol bit y9, assign code bit b7 to symbol bit y5, assign code bit bs to symbol bit yj, and assign mbit bg to The symbol bit y8 assigns the code bit bi〇 to the symbol bit y4, and assigns the code bit b 1 1 to the symbol bit y〇 for replacement. Figure 228 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 3/5, and a multiple of b can be used. The LDPC code is an ldpc code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and a multiple of ba2, the multiplexer 25 is in the direction of the X direction in the wale direction. The code bits written for the memory 31 of (648 〇〇 / (8x2)) x (8x2) bits are in the course direction, read out in 8x2 (= mb) bit units, and supplied to the replacement portion 32. . The replacing unit 32 is configured to assign the code bits bG to bls read from the memory 3128x2 (= mb) bits to the 8x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The symbol bits y〇 to yi5 are substituted for 8χ2 (=_bits of code bits bG to b15. That is, if according to FIG. 228, the replacement unit 32 respectively: assigns the code bit bG to the symbol Bit yi5, assigning code bit b to symbol yi, assigning code bit bz to symbol 713, 135786.doc -268- 200937872 assigning code bit b3 to symbol y3 , the code bit b4 is assigned to the symbol bit y8, the code bit b5 is assigned to the symbol bit yu ', the code bit b6 is assigned to the symbol bit y9, and the code bit b7 is assigned to the symbol bit Element y5, assigning code bit 1)8 to symbol bit 丫1(), assigning code bit b9 to symbol bit y6, and assigning code bit bi〇 to symbol bit y4, Bit b 1 is assigned to symbol bit y7, code bit b12 is assigned to symbol bit 712, code bit b 3 is assigned to symbol bit y 2 , and bit bit b14 is assigned to symbol The bit 丫14 assigns the code bit b15 to the symbol y〇, and performs Change. Figure 229 shows an example in which the modulation mode is 256qam, and the LDPC code is an LDpc code having a code length N of 16,200 bits and an encoding rate of 3/5, and the bit b is 1 in the case where the multiple b is 1. The LDPC code is an ldpc code with a code length n of 162 〇 0 bits and a coding rate of 3/5. The further modulation mode is 256QAM, the multiple bai is used in the multiplexer 25, and the traversing direction is X. The code bit written in the memory 31 of the direction (16200/(8 1)) χ (8χ1) is stored in the horizontal direction, read out in 8X1 (= mb) bit units, and supplied to the replacement unit 32. . The replacement unit 32 is to read "8" from the memory 31 < 1 (= the position of the position of the ring to the b7, as shown in FIG. 229) to the "four" symbol "=_ bit 135786. Doc • 269 · 200937872 yuan symbol y 〇 to y? way to replace 8 < i (= mb) bits of code bits b 〇 b b. That is, if according to Figure 229, replace The part 32 is respectively: assigning the code bit b〇 to the symbol bit y7, assigning the code bit heart to the symbol bit y3, and assigning the code bit t>2 to the symbol bit yi, the code bit The element b>3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y2, the code bit bs is assigned to the symbol bit y6, and the code bit b6 is assigned to the symbol bit h The code bit b7 is assigned to the symbol bit and replaced. Figure 230 shows that the LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5, and further modulation mode. An example of a bit allocation pattern that can be used when QPSK is a multiple b. The LDpC code is an LDPC code with a code length N of 16200 or 04800 bits and a coding rate of 3/5, and the modulation method is QPSK. When the multiple b is 1, the solution is more The direction of the horizontal direction x of the device 25 is (Ν/(2χ 兀 己 3 3 3 3 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入And supplied to the replacement unit 32. The replacement 邛32 is used to read the code bits 兀~ and 卜 from the 2><1 (=11^) bits of the memory 31, as shown in Fig. 230 to 1 (= 13) The symbol of the 2xl (= mb) bit of the symbol, and the way to replace the 2xl (= mb) bits of the code bits b and bj. 135786.doc -270 200937872 That is, according to Fig. 230, the replacing unit 32 assigns the code bit bG to the symbol bit y, and assigns the code bit bi to the symbol bit yi, and replaces it. Alternatively, the replacement may be performed, and the code bits 1) and b are directly used as the symbol bits yc and y 1. Figure 231 shows that the LDPC code has a code length N of 64,800 bits and a coding rate of 3/5. The LDPC code is an example in which the bit modulation mode is 16QAM and the multiple b is 2. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 3/5. , further modulation mode is 16QAM, multiple b is 2 In the case of the multiplexer 25, the memory bits written in the memory 3 of the (64800/(4 χ 2)) χ (4 χ 2) bits in the wales X direction are in the course direction, The 4x2 (= mb) bit unit is read out and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits b to 4 from the 4x2 (= mb) bits of the memory 31, as shown in Fig. 23 1 to the consecutive 2 (= b) symbols & 4 ><; 2 (= mb) bit symbol bit 丫〇 to 77, to replace the 4x2 (= mb) bit code bits bG to b7. That is, according to FIG. 23, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, assigns the code bit b! to the symbol bit y 5, and assigns the code bit b2. The symbol bit y1 is assigned to the symbol bit y2, and the code bit b4 is assigned to the symbol y4, 135786.doc -271 - 200937872 assigns the code bit b5 to the symbol The bit y7 assigns the code bit b6 to the symbol bit y3, and assigns the code bit b7 to the symbol bit y6 for replacement. Figure 232 shows an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a bit allocation pattern which can be employed in the case where the modulation method is 16QAM and the multiple b is 2.
LDPC碼是碼長N為16200位元、編碼率為3/5之LDPC 碼,進一步調變方式為16QAM、倍數b為2之情況下,於解 多工器25,於縱行方向X橫列方向為(16200/(4χ2))χ(4χ2)位 元之記憶體3 1寫入之碼位元係於橫列方向,以4x2(=mb)位 元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體31之4x2(=mb)位元之碼位 元bG至b7,如圖232所示分配給連續2(=b)個符元之 4x2(=mb)位元之符元位元yG至y7之方式,來替換4x2(=mb) 位元之碼位元bG至b7。 亦即,若根據圖232,替換部32係分別: 將碼位元bG分配給符元位元y7, 將碼位元b 1分配給符元位元y 1, 將碼位元b2分配給符元位元y4, 將碼位元b3分配給符元位元y2, 將碼位元b4分配給符元位元ys, 將碼位元b5分配給符元位元y3, 將碼位元b6分配給符元位元y6, 135786.doc -272- 200937872 將碼位元b7分配給符元位元y〇, 而進行替換。 圖233係表示調變方式為64QAM,且LDPC碼是碼長Ν為 64800位元、編碼率為3/5之LDPC碼,倍數b為2之情況下 可採用之位元分配模式之例。 LDPC碼是碼長N為64800位元、編碼率為3/5之LDPC 碼,進一步調變方式為64QAM、倍數b為2之情況下,於解 多工器25,於縱行方向X橫列方向為(64800/(6x2))x(6x2)位 Ο 元之記憶體31寫入之碼位元係於橫列方向,以6x2(=mb)位 元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體3 1之6><2(=mb)位元之碼位 元b〇至bn,如圖233所示分配給連續2(=b)個符元之 6x2(=mb)位元之符元位元y〇至y〗!之方式,來替換6><2(=mb) 位元之碼位元b〇至b丨!。 亦即,若根據圖233,替換部32係分別: 將碼位元b〇分配給符元位元y2, ◎ 將碼位元b!分配給符元位元y 7, 將碼位元b2分配給符元位元y6, 將碼位元b3分配給符元位元y9, 將碼位元b4分配給符元位元y〇, 將碼位元b5分配給符元位元y3, 將碼位元b6分配給符元位元y 1, 將碼位元b7分配給符元位元y8, 將碼位元b8分配給符元位元y4, 135786.doc -273 - 200937872 將碼位元%分配給符元位元yn, 將碼位元b1Q分配給符元位元y5, 將碼位元b丨丨分配給符元位元yi〇, 而進行替換。 圖234係表示調變方式為64qam,且LDPC碼是碼長N為 16200位元、編碼率為3/5iLDpc碼,倍數^^為之之情況下 可採用之位元分配模式之例。 ⑶^碼是碼長N為16200位元、編碼率為3/5之LDPC © 碼,進一步調變方式為64QAM、倍數b為2之情況下,於解 多工器25,於縱行方向X橫列方向為(16200/(6χ2))χ(6χ2)位 元之s己憶體3 1寫入之碼位元係於橫列方向,以6x2(=mb)位 元單位讀出’並供給至替換部3 2。 替換部32係以將讀出自記憶體31之6x2(=mb)位元之碼位 元bG至bll ’如圖234所示分配給連續2(=b)個符元之 6 2( mb)位元之符元位元yGiyn之方式,來替換&2(=@^() 位元之碼位元13()至1)11 〇 ❹ 亦即,若根據圖234,替換部32係分別: 將碼位元bG分配給符元位元yn, 將碼位元b!分配給符元位元y7, 將碼位元b>2分配給符元位元y3, 將碼位元h分配給符元位元丫1〇, 將碼位元t>4分配給符元位元y 6, 將碼位元t>5分配給符元位元y2, 將碼位元be分配給符元位元y9, 135786.doc •274- 200937872 將碼位元b7分配給符元位元y5, 將碼位元b8分配給符元位元y 1, 將碼位元b9分配給符元位元y8, 將碼位元bίο分配給符元位元y4, 將碼位元b 1!分配給符元位元y 〇, 而進行替換。 圖235係表示調變方式為256QAM,且LDPC碼是碼長N 為64800位元、編碼率為3/5之LDPC碼,倍數b為2之情況 〇 下可採用之位元分配模式之例。 LDPC碼是碼長N為64800位元、編碼率為3/5之LDPC 碼,進一步調變方式為256QAM、倍數b為2之情況下,於 解多工器25,於縱行方向X橫列方向為(64800/(8χ2))χ(8χ2) 位元之記憶體31寫入之碼位元係於橫列方向,以8x2(=mb) 位元單位讀出,並供給至替換部32。 替換部32係以將讀出自記憶體3 1之8x2(=mb)位元之碼位 元bQ至b15,如圖235所示分配給連續2(=b)個符元之 ® 8><2(=mb)位元之符元位元yG至yi5之方式,來替換8x2(=mb) 位元之碼位元b〇至b! 5。 亦即,若根據圖235,替換部32係分別: 將碼位元bG分配給符元位元y2, 將碼位元b 1分配給符元位元y 11, 將碼位元b2分配給符元位元y3, 將碼位元b3分配給符元位元y4, 將碼位元b4分配給符元位元y〇, 135786.doc -275- 200937872 將碼位元b5分配給符元位元y9, 將碼位元b6分配給符元位元y丨, 將碼位元b7分配給符元位元y8, 將碼位元b8分配給符元位元y! 〇, 將碼位元b9分配給符元位元y! 3, 將碼位元b1()分配給符元位元y7, 將碼位元b〗!分配給符元位元y14, 將碼位元bu分配給符元位元y6, ® 將碼位元bl3分配給符元位元y丨5, 將碼位元b 14分配給符元位元y 5, 將碼位元1^5分配給符元位元丫12, 而進行替換。 圖236係表示調變方式為256QAM,且LDPC碼是碼長^^ 為16200位元、編碼率為3/5iLDpc碼,倍數b為l之情況 下可採用之位元分配模式之例。The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the wales. The memory bit written in the memory of the (16200/(4χ2)) χ(4χ2) bit is written in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to the replacement unit 32. . The replacing unit 32 assigns the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to the 4x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The meta-bits yG to y7 of the meta-elements replace the code-bits bG to b7 of the 4x2 (= mb) bits. That is, according to FIG. 232, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol. The meta-bit y4 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit ys, the code bit b5 to the symbol bit y3, and the code bit b6. The symbol bit y6, 135786.doc -272- 200937872 is assigned to the symbol bit y〇, and is replaced. Figure 233 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length Ν of 64,800 bits and a coding rate of 3/5, and a multiple of b can be used. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is arranged in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(6x2)) x (6x2) bits are in the course direction, read out in units of 6x2 (= mb) bits, and supplied to the replacement unit 32. . The replacing unit 32 is configured to allocate the code bits b to 6 from the 6 >< 2 (= mb) bits of the memory 3 1 to bn as shown in Fig. 233 to 2 consecutive (= b) symbols. 6x2 (= mb) bit symbol y 〇 to y〗! In this way, replace the code bits b6 to b丨 of the 6<2(=mb) bits! . That is, according to FIG. 233, the replacing unit 32 assigns the code bit b〇 to the symbol bit y2, ◎ assigns the code bit b! to the symbol bit y 7, and assigns the code bit b2. For the symbol bit y6, the code bit b3 is assigned to the symbol bit y9, the code bit b4 is assigned to the symbol bit y, and the code bit b5 is assigned to the symbol y3, and the code bit is The element b6 is assigned to the symbol bit y 1, the code bit b7 is assigned to the symbol bit y8, and the code bit b8 is assigned to the symbol bit y4, 135786.doc -273 - 200937872 assigns the code bit % To the symbol element yn, the code bit b1Q is assigned to the symbol bit y5, and the code bit b丨丨 is assigned to the symbol bit yi〇 for replacement. Fig. 234 shows an example in which the modulation mode is 64qam, and the LDPC code is a bit allocation mode in which the code length N is 16,200 bits and the coding rate is 3/5 iLDpc code, and the multiple is ^^. (3) The code is an LDPC © code with a code length N of 16200 bits and a coding rate of 3/5. In the case where the modulation mode is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction X. The horizontal direction is (16200/(6χ2)) χ(6χ2) bits of the suffix 3 1 written code bits are in the horizontal direction, read out in 6x2 (= mb) bit units and supplied To the replacement part 3 2 . The replacing unit 32 assigns the code bits bG to bll ' read from the 6x2 (= mb) bits of the memory 31 to the 6 2 (mb) bits of consecutive 2 (= b) symbols as shown in FIG. In the manner of the meta-symbol yGiyn, the replacement of the & 2 (=@^() bit of the code bit 13() to 1) 11 〇❹, that is, according to FIG. 234, the replacement unit 32 is respectively: The code bit bG is assigned to the symbol bit yn, the code bit b! is assigned to the symbol bit y7, the code bit b>2 is assigned to the symbol bit y3, and the code bit h is assigned to the symbol The bit element 丫1〇, the code bit element t>4 is assigned to the symbol bit y 6, the code bit element t>5 is assigned to the symbol bit y2, and the code bit element be is assigned to the symbol bit y9 , 135786.doc • 274- 200937872 assign code bit b7 to symbol bit y5, assign code bit b8 to symbol bit y 1, assign code bit b9 to symbol bit y8, put code Bit b ίο is assigned to symbol y4, and code bit b 1! is assigned to symbol y 〇 for replacement. Figure 235 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and the multiple b is 2. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is disposed in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(8χ2)) χ (8χ2) bits are in the course direction, read out in 8x2 (= mb) bit units, and supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bQ to b15 read from the 8x2 (= mb) bits of the memory 3 1 to the consecutive 2 (= b) symbols of the symbol 8 8 as shown in FIG. 235; < 2 (= mb) bits of the symbol bits yG to yi5, to replace the 8x2 (= mb) bits of the code bits b 〇 to b! That is, according to FIG. 235, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y2, assigns the code bit b1 to the symbol bit y 11, and assigns the code bit b2 to the symbol. The bit y3, the code bit b3 is assigned to the symbol y4, and the code bit b4 is assigned to the symbol y〇, 135786.doc -275- 200937872 assigns the code bit b5 to the symbol bit Y9, the code bit b6 is assigned to the symbol bit y丨, the code bit b7 is assigned to the symbol bit y8, the code bit b8 is assigned to the symbol bit y! 〇, and the code bit b9 is allocated To the symbol bit y! 3, assign the code bit b1() to the symbol bit y7, and the code bit b! Assigned to the symbol bit y14, the code bit bu is assigned to the symbol bit y6, the code bit bl3 is assigned to the symbol bit y丨5, and the code bit b 14 is assigned to the symbol bit y 5. The code bit 1^5 is assigned to the symbol bit 丫12, and is replaced. Figure 236 shows an example in which the modulation mode is 256QAM, and the LDPC code is a bit allocation mode in which the code length ^^ is 16200 bits, the coding rate is 3/5iLDpc code, and the multiple b is l.
〇 LDPC碼是碼長叫1620〇位元、編碼率為3/5之LDPC 碼,進一步調變方式為256QAM、倍數1?為1之情況下,於 解多工器25,於縱行方向x橫列方向為(162〇〇/(8χΐ))χ(8川 位兀之記憶體31寫入之碼位元係於橫列方向,以8χΐ㈣^ 位元單位讀出,並供給至替換部32。 替換部32係以將讀出自u + p w 貝W目》己隐體3 1之8 x 1 (=mb)位元之碼位 b?如圖236所不分配給丨卜15)個符元之8xl(=mb)位 元之符元位元y〇”7之方式’來替換8,mb)位元之碼位 元b〇至by。 135786.doc •276· 200937872 亦即’若根據圖236,替換部32係分別: 將瑪位元b〇分配給符元位元y7, 將碼位元b !分配給符元位元y 3, 將碼位元b2分配給符元位元y 1, 將碼位元b3分配給符元位元y5, 將碼位元b4分配給符元位元y2, 將碼位元b5分配給符元位元y6, 將碼位元1>6分配給符元位元y4, 將碼位元b7分配給符元位元y〇, 而進行替換。 接著’說明關於構成接收裝置12之反交錯器53。 圖237係說明構成反交錯器53之多工器54之處理之圖。 亦即’圖237A係表示多工器54之功能性結構例。 多工器54係由反替換部1〇〇1及記憶體1002所構成。 多工器54係將供給自前段之解映射部52之符元之符元位 元作為對象,進行對應於發送裝置丨丨之解多工器25所進行 之替換處理之反替換處理(替換處理之逆向處理),亦即進 行使藉由替換處理所替換之LDPC碼之碼位元(符元位元)之 位置回到原本位置之反替換處理,將其結果所獲得之 LDPC碼供給至後段之縱行扭轉反交錯器55。 亦即,於多工器54,對反替換部1〇〇1,以(連續)b個符 元之單位供給有該b個符元之mb位元之符元位元 y〇,yi,· · ·,ymb-i 0 反替換部1001係進行使mb位元之符元位元…至〜…回到 135786.doc •277· 200937872 原本之mb位元之碼位元b0,bl,. · .,^丨之排列⑼構㈣ 送裝置U側之解多工器25之替換部32之替換進行前之碼位 元bG至bmw之排列)之反替換,並輸出其結果所獲得之 位元之碼位元bG至bmH。 記憶體10 0 2係與構成發送裝置i丨側之解多工器2 5之記憶 體31相同,含有於横列(row)(橫)方向記憶〇11)位元,並且: 縱行(column)(縱)方向記憶N/(mb)位元之記憶容量。亦 即,記憶體1002係由記憶N/(mb)位元之mb個縱行所構成。 其中,於記憶體1002,在從發送裝置u之解多工器乃之 記憶體31進行碼位元之讀出之方向,進行反替換部1〇〇1所 輸出之LDPC碼之碼位元之寫入,在往記憶體3丨進行碼位 元之寫入之方向,進行寫入於記憶體1〇〇2之碼位元之讀 出。 亦即,於接收裝置12之多工器54,如圖237A所示,將反 替換。卩1001所輸出之LDPC碼之碼位元以.mb位元單位於橫 列方向之寫入’係從記憶體1〇〇2之第1列往下列依次進 行。 然後’若1碼長份之碼位元之寫入終了,則於多工器 54 ’從s己憶體1 〇〇2 ’將碼位元從縱行方向讀出,並供給至 後段之縱行扭轉反交錯器5 5。 於此’圖237B係表示從記憶體1〇〇2之碼位元之讀出之 圖。 於多工器54,LDPC碼之碼位元在構成記憶體1〇〇2之縱 行從上往下方向(縱行方向)之讀出係從左朝向右方向之縱 135786.doc •278 · 200937872 行進行。 接著,參考圖238來說明構成接收裝置12之反交錯器53 之縱行扭轉反交錯器55之處理。 圖238係表示多工器54之記憶體1002之結構例。 記憶體1002具有於縱行(縱)方向記憶„^位元,並且於橫 列(橫)方向記憶N/(mb)位元之記憶容量,由mb個縱行所構 成。 縱行扭轉反交錯器55係對於記憶體1〇〇2,控制將LDpc © 碼之碼位元寫入於橫列方向、於縱行方向讀出時之開始讀 出位置’藉此進行縱行扭轉反交錯。 亦即於縱行扭轉反交錯器5 5 ,針對複數縱行分別適宜 地變更開始瑪位元之讀出之開始讀出位置,藉此進行使縱 行扭轉父錯所重排之碼位元之排列回到原本排列之反重排 處理。 於此,圖238係表示調變方式為16QAM且倍數b為1之情 ◎ 況下之„己憶體1 〇〇2之結構例。因此,i符元之位元數瓜為4 位元,而且記憶體1〇〇2係以4(=mb)個縱行所構成。 縱行扭轉反交錯器55係(取代多工器54)從記憶 體1002之 第1列朝向下列’依次進行替換部1〇〇1所輸出iLDpc碼之 碼位元往橫列方向之寫入。 然後’若1碼長份之碼位元之寫入終了,縱行扭轉反交 錯器55係從左朝向右方向之縱行,將碼位元從記憶體1002 進行從上往下方向(縱行方向)之讀出。 其中’縱行扭轉反交錯器55係將發送裝置11側之縱行扭 135786.doc •279· 200937872 轉交錯器24寫入碼位元之開妒耷 .s , 3 <阀始冩位置,作為碼位元之開始 讀出位置,從記憶體1〇〇2進行碼位元之讀出。 亦即,若將各縱行之開頭(最上面)之位置之位址設為 〇以升序之整數表示縱行方向之各位置之位址,則於調 變方式為16QAM且倍數b為1之情況下,於縱行扭轉反交錯 器55 ’關於最左縱行,將開始讀出位置設作位址為〇之位 置關於(左起)第2縱行,將開始讀出位置設作位址為2之 位置,關於第3縱行,將開始讀出位置設作位址為4之位 置,關於第4縱行,將開始讀出位置設作位址為7之位置。 此外,關於開始讀出位置是位址為〇之位置以外之位置 之縱行,將碼位元之讀出進行至最下面之位置後,返回開 頭(位址為〇之位置)’進行即將至開始讀出位置前之位置為 止之讀出。然後,其後進行從下一(右)縱行之讀出。 藉由進行如以上之縱行扭轉反交錯,縱行扭轉交錯所重 排之碼位元之排列會回到原本排列。 接著,圖239係表示接收裝置12之其他結構例之區塊 圖。 於圖239 ’接收裝置12係接收來自發送裝置丨丨之調變信 號之資料處理裝置’由正交解調部51、解映射部52、反交 錯器53及LDPC解碼部1〇21所構成。 正交解調部51係接收來自發送裝置11之調變信號,進行 正交解調,將其結果所獲得之符元(I及Q軸方向分別之值) 供給至解映射部52。 解映射部52係進行使來自正交解調部51之符元成為 135786.doc -280· 200937872 LDPC碼之碼位元之解映射,並供給至反交錯器53 ^ 反交錯器53係由多工器(Μυχ)54、縱行扭轉反交錯器55 及同位反交錯器1〇1丨所構成,進行來自解映射部“之 LDPC碼之碼位元之反交錯。 亦即,多工器54係將來自解映射部52之LDpc碼作為對 象,進行對應於發送裝置U之解多工器25所進行之替換處 理之反替換處理(替換處理之逆向處理),亦即進行使藉由 替換處理所替換之碼位元之位置回到原本位置之反替換處 © 理,並將其結果所獲得之LDPC碼供給至縱行扭轉反交錯 器55。 縱行扭轉反交錯器55係將來自多工器54之LDPC碼作為 對象,進行對應於發送裝置灯之縱行扭轉交錯器24所進行 之作為重排處理之縱行扭轉交錯之縱行扭轉反交錯。 縱行扭轉反交錯之結果所獲得之LDPC碼係從縱行扭轉 反交錯器55供給至同位反交錯器。 ^ 同位反交錯器101丨係將縱行扭轉反交錯器55之縱行扭轉 反交錯後之碼位元作為對象,進行對應於發送裝置丨丨之同 位交錯器23所進行之同位交錯之同位反交錯(同位交錯之 逆向處理),亦即進行使藉由同位交錯變更排列之LDPC碼 之碼位元回到原本排列之同位反交錯。 同位反交錯之結果所獲得之LDPC碼係從同位反交錯器 1011供給至LDPC解碼部1021。 因此’於圖239之接收裝置12,對LDPC解碼部1021供給 有已進行反替換處理、縱行扭轉反交錯及同位反交錯之 135786.doc -281 · 200937872 LDPC碼,亦即供給有藉由按照檢查矩陣Η之LDPC編碼所 獲得之LDPC碼。 LDPC解碼部1021係利用發送裝置11之LDPC編碼部21用 於LDPC編碼之檢查矩陣Η本身、或對於該檢查矩陣Η至少 進行相當於同位交錯之行置換所獲得之轉換檢查矩陣,來 進行來自反交錯器53之LDPC碼之LDPC解碼,並將其結果 所獲得之資料,作為對象資料之解碼結果輸出。 於此,於圖239之接收裝置12,由於從反交錯器53(之同 © 位反交錯器1011)對於LDPC解碼部1021,供給藉由按照檢 查矩陣Η之LDPC編碼所獲得之LDPC碼,因此於發送裝置 11之LDPC編碼部21利用LDPC編碼所用之檢查矩陣Η本 身,來進行該LDPC碼之LDPC解碼之情況時,LDPC解碼 部1021可由例如藉由於每1個節點依次進行訊息(校驗節點 訊息、可變節點訊息)之運算之全串列譯碼(full serial decoding)方式進行LDPC解碼之解碼裝置,或藉由針對所 有節點同時(並列)進行訊息之運算之全並行譯碼(full ® parallel decoding)方式進行LDPC解碼之解碼裝置來構成。 而且,於LDPC解碼部1021,利用對於發送裝置11之 LDPC編碼部21用於LDPC編碼之檢查矩陣Η,至少進行相 當於同位交錯之行置換所獲得之轉換檢查矩陣,來進行 LDPC碼之LDPC解碼之情況時,可由同時進行Ρ(或Ρ之1以 外之約數)個校驗節點運算及可變節點運算之架構 (architecture)之解碼裝置,且含有藉由對LDPC碼施以與用 以獲得轉換檢查矩陣之行置換同樣之行置換,以重排該 135786.doc 282- 200937872 LDPC碼之碼位元之接收資料重排部31〇之解碼裝置來構 成。 此外,於圖239,為了便於說明,分別個別地構成進行 反替換處理之多工器54、進行縱行扭轉反交錯之縱行扭轉 反交錯器55及進行同位反交錯之同位反交錯器1〇11,但多 工器54、縱行扭轉反交錯器55及同位反交錯器1〇11之2以 上可與發送裝置11之同位交錯器23、縱行扭轉交錯器24及 解多工器25同樣地一體地構成。 © 接著,圖240係表示可適用於接收裝置12之接收系統之 第1結構例之區塊圖。 於圖240,接收系統係由取得部1101、傳送道解碼處理 部1102及資訊源解碼處理部11〇3所構成。 取得部1101係經由例如地面數位播放、衛星數位播放、 CATV網、網際網路和其他網路等未圖示之傳送道,取得 包含將節目之圖像資料或聲音資料等對象資料至少予以 LDPC編碼所獲得之LDPC碼之信號,並供給至傳送道解碼 ◎處理部1102。 於此’於取得部1101所取得之信號例如從播放台經由地 波、衛星波、CATV(Cable Television :有線電視)網等播 放而來之情況下’取得部1101係以調階器或STB(Set Top Box:機上盒)等所構成。而且,取得部lioi所取得之信號 例如從網頁伺服器’如 IPTV(Internet Protocol Television : 網路協定電視)以多點播送發送而來之情況下,取得部 1101係以例如NIC(Network Interface Card :網路介面卡)等 135786.doc -283 - 200937872 網路I/F(Inter face :介面)所構成。 傳送道解碼處理部1102係對於取得部丨1〇1經由傳送道所 取得之信號,施以至少包含訂正在傳送道所產生之失誤之 處理之傳送道解碼處理,將其結果所獲得之信號供給至資 訊源解碼處理部1103。 亦即,取得部1101經由傳送道所取得之信號係藉由至少 進行用以訂正在傳送道所產生之失誤之失誤訂正編碼所獲 得之信號,傳送道解碼處理部1102係對於該類信號,施以 © 例如失誤訂正處理等傳送道解碼處理。 於此’作為失誤訂正編碼有例如LDPC編碼或李德所羅 門編碼等。於此,作為失誤訂正編碼至少進行lDPC編 碼。 而且,傳送道解碼處理可能包含調變信號之解調等。 資訊源解碼處理部1103係對於經施以傳送道解瑪處理之 信號,施以至少包含將壓縮之資訊伸張為原本資訊之處理 之資訊源解碼處理。 ❹ 亦即,於取得部1101經由傳送道所取得之信號,為了減 少作為資訊之圖像或聲音等之資料量,可能施以壓縮資訊 之壓縮編碼,該情況下,資訊源解碼處理部1103係對於經 施以傳送道解碼處理之信號,施以將壓縮之資訊伸張為原 本資訊之處理(伸張處理)等資訊源解碼處理。 此外,於取得部110〗經由傳送道所取得之信號未施以壓 縮編碼之情況下,於資訊源解碼處理部1103,不進行將壓 縮之資訊伸張為原本資訊之處理。 135786.doc -284- 200937872 於此,作為伸張處理有例如mpeg譯碼等。而且,傳送 道解碼處理除了伸張處理以外,可能包含解拌碼等。 如以上所構成之接收系統,於取得部1101,例如對於圖 像或聲音等資料,施以mpeg編碼等壓縮編碼,並進一步 經由傳送道取得經施以LDPC編碼等失誤訂正編碼之信 號’並供給至傳送道解碼處理部11 02。 於傳送道解碼處理部1102,對於來自取得部1101之信 號,作為傳送道解碼處理而施以例如與正交解調部51或解 © *射部52、反交錯器53、LDPC解碼部56(或LDPC解碼部 1021)同樣之處理,其結果所獲得之信號供給至資訊源解 碼處理部11 〇3。 於資訊源解碼處理部1103,對於來自傳送道解碼處理部 1102之彳§號,施以1^[1>£(}譯碼等資訊源解碼處理,輸出其 結果所獲得之圖像或聲音。 如X上之圖240之接收系統可適用於例如接收作為數位 ❹ 播放之電視播放之電視調階器等。 此外,取得部lioi、傳送道解碼處理部11〇2及資訊源解 碼處理部1103分別可作為丨個獨立之裝置(硬體(1(: (Integrated Circuit:積體電路)等)或軟體模組)而構成。 而且,關於取得部1101、傳送道解碼處理部n〇2及資訊 源解碼處理部1103,可將取得部11〇1與傳送道解碼處理部 1102之集纟、或冑送道解碼處理部11〇2與資訊源解碼處理 部11〇3之集合、取得部1101、傳送道解碼處理部ιι〇2及資 訊源解碼處理部1103之集合作為丨個獨立之裝置而構成。 135786.doc -285· 200937872 圖241係表示可適用於接收裝置12之接收系統之第2結構 例之區塊圖。 此外,圖中’關於與圖240之情況相對應之部分係附上 同一符號,於以下適宜地省略其說明。 圖241之接收系統係於含有取得部1101、傳送道解碼處 理部1102及資訊源解碼處理部1103之點,與圖24〇之情沉 共通’於新設有輸出部1111之點,與圖240之情況相異。 輸出部1111係例如顯示圖像之顯示裝置或輸出聲音之揚 〇 聲器’其輸出從資訊源解碼處理部1103所輸出之作為信號 之圖像或聲音等。亦即’輸出部U11係顯示圖像或輸出聲 音。 如以上之圖241之接收系統可適用於例如接收作為數位 播放之電視播放之TV(電視受像機)、或接收廣播播放之廣 播接收機等。 此外’於取得部1101所取得之信號未施以壓縮編碼之情 況下,傳送道解碼處理部1102所輸出之信號係供給至輸出 ❹部1 m » 圖242係表示可適用於接收裝置12之接收系統之第3結構 例之區塊圖。 此外’圖中,關於與圖240之情況相對應之部分係附上 同一符號,於以下適宜地省略其說明。 圖242之接收系統係於含有取得部11〇1及傳送道解喝處 理部1102之點,與圖240之情況共通。 其中,圖242之接收系統係於未設有資訊源解碼處理部 135786.doc -286· 200937872 11 03而新設有記錄部ii21之點,與圖24〇之情況相異。 s己錄部1121係將傳送道解瑪處理部1102所輸出之作洗 (例如MPEG之TS之TS封包),記錄於(使其記憶於)光碟片 或硬碟(磁性碟片)、快閃記憶體等記錄(記憶)媒體。 如以上之圖242之接收系統可適用於將電視播放予以錄 像之錄影機等。 此外’於圖242,接收系統係設置資訊源解碼處理部 1103而構成,於資訊源解碼處理部11〇3,能以記錄部1121 記錄經施以資訊源解碼處理後之信號,亦即藉由譯碼所獲 得之圖像或聲音。 此外’本發明之實施型態不限定於上述實施型態,於不 脫離本發明之要旨之範圍内可予以各種變更。 【圖式簡單說明】 圖1係說明LDPC碼之檢查矩俾H之圖。 圖2係說明LDPC碼之解碼程序之流程圖。 圖3係表示LDPC碼之檢查矩陣之例之圖。 圖4係表示檢查矩陣之丁&111161>圖之圖。 圖5係表示可變節點之圖。 圖6係表示校驗節點之圖。 圖7係表示適用本發明之傳送系統之一實施型態之結構 例之圖。 圖8係表示發送裝置丨〗> α , 衣置1 1之結構例之區塊圖。 圖9係表示檢查矩陣之圖。 圖10係表示同位矩陣之圖。 I35786.doc •287· 200937872 圖1 ΙΑ、B係表示DVB-S.2之規格所規定之LDPC碼之檢 查矩陣及行權重之圖。 圖12A、B係表示16QAM之信號點配置之圖。 圖13係表示64QAM之信號點配置之圖。 圖14係表示64QAM之信號點配置之圖。 圖15係表示64QAM之信號點配置之圖。 圖16A-D係說明解多工器25之處理之圖。 圖17A、B係說明解多工器25之處理之圖。 © 圖1 8係表示關於LDPC碼之解碼之Tanner圖之圖。 圖19A、B係表示成為階梯構造之同位矩陣Ητ及對應於 該同位矩陣Ητ之Tanner圖之圖。 圖20係表示對應於同位交錯後之LDPC碼之檢查矩陣Η之 同位矩陣Ητ之圖。 圖21A、Β係表示轉換檢查矩陣之圖。 圖22係說明縱行扭轉交錯器24之處理之圖。 圖23係表示縱行扭轉交錯所必要之記憶體3 1之縱行數及 ® 開始寫位置之位址之圖。 圖24係表示縱行扭轉交錯所必要之記憶體3 1之縱行數及 開始寫位置之位址之圖。 圖25係說明發送處理之流程圖。 圖26A、B係表示在模擬所採用之通訊道之模型之圖。 圖27係表示在模擬所獲得之錯誤率與顫振之都卜勒頻率 fd之關係之圖。 圖28係表示在模擬所獲得之錯誤率與顫振之都卜勒頻率 135786.doc • 288- 200937872 fd之關係之圖。 圖29係表示LDPC編碼部21之結構例之區塊圖。 圖3 0係說明LDPC編碼部21之處理之流程圖。 圖31係表示編碼率2/3、碼長16200之檢查矩陣初始值表 之圖。 圖32係表示編碼率2/3、碼長64800之檢查矩陣初始值表 之圖。 圖33係表示編碼率2/3、碼長64800之檢查矩陣初始值表 ❹ 之圖。 圖34係表示編碼率2/3、碼長64800之檢查矩陣初始值表 之圖。 圖35係表示編碼率3/4、碼長16200之檢查矩陣初始值表 之圖。 圖36係表示編碼率3/4、碼長64800之檢查矩陣初始值表 之圖。 圖37係表示編碼率3/4、碼長64800之檢查矩陣初始值表 ❿之圖。 圖38係表示編碼率3/4、碼長64800之檢查矩陣初始值表 之圖。 圖39係表示編碼率3/4、碼長64800之檢查矩陣初始值表 之圖。 圖40係表示編碼率4/5、碼長16200之檢查矩陣初始值表 之圖。 圖41係表示編碼率4/5、碼長64800之檢查矩陣初始值表 135786.doc -289- 200937872 之圖。 圖42係表示編碼率4/5、碼長64800之檢查矩陣初始值表 之圖。 圖43係表示編碼率4/5、碼長64800之檢查矩陣初始值表 之圖。 圖44係表示編碼率4/5、碼長64800之檢查矩陣初始值表 之圖。 圖45係表示編碼率5/6、碼長16200之檢查矩陣初始值表 〇 之圖。 圖46係表示編碼率5/6、碼長64800之檢查矩陣初始值表 之圖。 圖47係表示編碼率5/6、碼長64800之檢查矩陣初始值表 之圖。 圖48係表示編碼率5/6、碼長64800之檢查矩陣初始值表 之圖。 圖49係表示編碼率5/6、碼長64800之檢查矩陣初始值表 ❿之圖。 圖50係表示編碼率8/9、碼長16200之檢查矩陣初始值表 之圖。 圖51係表示編碼率8/9、碼長64800之檢查矩陣初始值表 之圖。 圖52係表示編碼率8/9、碼長64800之檢查矩陣初始值表 之圖。 圖53係表示編碼率8/9、碼長64800之檢查矩陣初始值表 135786.doc -290- 200937872 之圖。 圖54係表示編碼率8/9、碼長64800之檢查矩陣初始值表 之圖。 圖55係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之圖。 圖56係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之圖。 圖57係表示編碼率9/10、碼長64800之檢查矩陣初始值 © 表之圖。 圖58係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之圖。 圖59係說明從檢查矩陣初始值表求出檢查矩陣Η之方法 之圖。 圖60Α〜C係說明現行方式之替換處理之圖。 圖61Α〜C係說明現行方式之替換處理之圖。 圖62A、B係表示以1024QAM調變碼長16200、編碼率 ® 2/3之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖63係表示以1024QAM調變碼長16200、編碼率2/3之 LDPC碼之情況下之分配規貝丨J之圖。 圖64A、B係表示以1024QAM調變碼長16200、編碼率 2/3之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖65A、B係表示以1024QAM調變碼長64800、編碼率 135786.doc -291 - 200937872 2/3之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖66係表示以1024QAM調變碼長64800、編碼率2/3之 LDPC碼之情況下之分配規貝ij之圖。 圖67A、B係表示以1024QAM調變碼長64800、編碼率 2/3之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖68A、B係表示以1024QAM調變碼長16200、編碼率 〇 3/4之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖69係表示以1024QAM調變碼長16200、編碼率3/4之 LDPC碼之情況下之分配規貝ij之圖。 圖70A、B係表示以1024QAM調變碼長16200、編碼率 3/4之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖71A、B係表示以1024QAM調變碼長64800、編碼率 ❹ 3/4之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖72係表示以1024QAM調變碼長64800、編碼率3/4之 LDPC碼之情況下之分配規貝ij之圖。 圖73A、B係表示以1024QAM調變碼長64800、編碼率 3/4之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖74A、B係表示以1024QAM調變碼長16200、編碼率 135786.doc -292- 200937872 4/5之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖75係表示以1024QAM調變碼長16200、編碼率4/;5之 LDPC碼之情況下之分配規貝|J之圖。 圖76A、B係表示以1024QAM調變碼長16200、編碼率 4/5之LDPC碼,且倍數b為1之情況下之按照分配規則之瑪 位元之替換之圖。 圖77A、B係表示以1024QAM調變碼長64800、編竭率 © 4/5之LDPC碼之情況下之碼位元群組及符元位元群紐之 圖。 圖78係表示以l〇24QAM調變碼長64800、編碼率4/5之 LDPC瑪之情況下之分配規貝1j之圖。 圖79A、B係表示以1024QAM調變碼長64800、編碼率 4/5之LDPC碼’且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖80A、B係表示以1024QAM調變碼長162〇〇、編碼率 ❹ 5/6之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖81係表示以1024QAM調變碼長162〇〇、編碼率5/6之 LDPC碼之情況下之分配規貝1J之圖。 圖82A、B係表示以1024QAM調變螞長162〇〇、編碼率 5/6之LDPC碼’且倍數13為丨之情況下夂按照分配規則之碼 位元之替換之圖。 圖83A、B係表示a1〇24QAM調變螞長648〇〇、編碼率 135786.doc •293 200937872 5/6之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖84係表示以1024QAM調變碼長64800、編碼率5/6之 LDPC碼之情況下之分配規貝ij之圖。 圖85A、B係表示以1024QAM調變碼長64800、編碼率 5/6之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖86A、B係表示以1024QAM調變碼長16200、編碼率 Ο 8/9之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖87係表示以1024QAM調變碼長16200、編碼率8/9之 LDPC碼之情況下之分配規貝|J之圖。 圖88A、B係表示以1024QAM調變碼長16200、編碼率 8/9之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖89A、B係表示以1024QAM調變碼長64800、編碼率 ^ 8/9之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖90係表示以1024QAM調變碼長64800、編碼率8/9之 LDPC碼之情況下之分配規貝ij之圖。 圖91A、B係表示以1024QAM調變碼長64800、編碼率 8/9之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖92A、B係表示以1024QAM調變碼長64800、編碼率 135786.doc -294- 200937872 9/10之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖93係表示以1024QAM調變碼長64800、編碼率9/10之 LDPC碼之情況下之分配規貝丨J之圖。 圖94A、B係表示以1024QAM調變碼長64800、編碼率 9/10之LDPC碼,且倍數b為1之情況下之按照分配規則之 碼位元之替換之圖。 圖95A、B係表示以4096QAM調變碼長16200、編碼率 Ο 2/3之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖96係表示以4096QAM調變碼長16200、編碼率2/3之 LDPC碼之情況下之分配規貝ij之圖。 圖97A、B係表示以4096QAM調變碼長16200、編碼率 2/3之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖98A、B係表示以4096QAM調變碼長64800、編碼率 2/3之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖99係表示以4096QAM調變碼長64800、編碼率2/3之 LDPC碼之情況下之分配規貝ij之圖。 圖100A、B係表示以4096QAM調變碼長64800、編碼率 2/3之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖101A、B係表示以4096QAM調變碼長16200、編碼率 135786.doc -295 - 200937872 3/4之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖102係表示以4096QAM調變碼長16200、編碼率3/4之 LDPC碼之情況下之分配規貝ij之圖。 圖103A、B係表示以4096QAM調變碼長16200、編碼率 3/4之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖104A、B係表示以4096QAM調變碼長64800、編碼率 Ο 3/4之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖105係表示以4096QAM調變碼長64800、編碼率3/4之 LDPC碼之情況下之分配規貝1J之圖。 圖106A、B係表示以4096QAM調變碼長64800、編碼率 3/4之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖107A、B係表示以4096QAM調變碼長16200、編碼率 W 4/5之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖108係表示以4096QAM調變碼長16200、編碼率4/5之 LDPC碼之情況下之分配規貝ij之圖。 圖109A、B係表示以4096QAM調變碼長16200、編碼率 4/5之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖110A、B係表示以4096QAM調變碼長64800、編碼率 135786.doc -296· 200937872 4/5之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖111係表示以4096QAM調變碼長64800、編碼率4/5之 LDPC碼之情況下之分配規貝|J之圖。 圖112A、B係表示以4096QAM調變碼長64800、編碼率 4/5之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖113A、B係表示以4096QAM調變碼長16200、編碼率 Ο 5/6之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖114係表示以4096QAM調變碼長16200、編碼率5/6之 LDPC碼之情況下之分配規貝ij之圖。 圖115A、B係表示以4096QAM調變碼長16200、編碼率 5/6之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖116A、B係表示以4096QAM調變碼長64800、編碼率 〇 w 5/6之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖117係表示以4096QAM調變碼長64800、編碼率5/6之 LDPC碼之情況下之分配規貝|J之圖。 圖118A、B係表示以4096QAM調變碼長64800、編碼率 5/6之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖119A、B係表示以4096QAM調變碼長16200、編碼率 135786.doc -297- 200937872 8/9之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖120係表示以4096QAM調變碼長16200、編碼率8/9之 LDPC碼之情況下之分配規貝ij之圖。 圖121A、B係表示以4096QAM調變碼長16200、編碼率 8/9之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖122A、B係表示以4096QAM調變碼長64800、編碼率 〇 8/9之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖123係表示以4096QAM調變碼長64800、編碼率8/9之 LDPC碼之情況下之分配規貝之圖。 圖124A、B係表示以4096QAM調變碼長64800、編碼率 8/9之LDPC碼,且倍數b為1之情況下之按照分配規則之碼 位元之替換之圖。 圖125A、B係表示以4096QAM調變碼長64800、編碼率 w 9/10之LDPC碼之情況下之碼位元群組及符元位元群組之 圖。 圖126係表示以4096QAM調變碼長64800、編碼率9/10之 LDPC碼之情況下之分配規貝ij之圖。 圖127A、B係表示以4096QAM調變碼長64800、編碼率 9/10之LDPC碼,且倍數b為1之情況下之按照分配規則之 碼位元之替換之圖。 圖128係表示1024QAM之信號點配置之圖。 135786.doc -298· 200937872 圖129係表示4096QAM之信號點配置之圖。 圖130係表示已進行替換處理之情況及未進行之情況下 之BER之模擬結果之圖。 圖131係表示已進行替換處理之情況及未進行之情況下 之BER之模擬結果之圖。 圖132係表示已進行替換處理之情況及未進行之情況下 之BER之模擬結果之圖。 圖133係表示已進行替換處理之情況及未進行之情況下 Ο 之BER之模擬結果之圖。 圖134A-C係說明倍數b為1之情況下之碼位元之替換之 圖。 圖135A〜C係說明直接利用倍數b為1之情況下之碼位元 之替換模式之倍數b為2之情況下之碼位元之替換之圖。 圖136係表示以1024QAM調變碼長16200、編碼率2/3之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖137係表示以1024QAM調變碼長64800、編碼率2/3之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖138係表示以1024QAM調變碼長16200、編碼率3/4之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖139係表示以1024QAM調變碼長64800、編碼率3/4之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖140係表示以1024QAM調變碼長16200、編碼率4/5之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖141係表示以1024QAM調變碼長64800、編碼率4/5之 135786.doc -299- 200937872 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖142係表示以1024QAM調變碼長16200、編碼率5/6之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖143係表示以1024QAM調變碼長64800、編碼率5/6之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖144係表示以1024QAM調變碼長16200、編碼率8/9之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖145係表示以1024QAM調變碼長64800、編碼率8/9之 ❹ LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖146係表示以1024QAM調變碼長64800、編碼率9/10之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖147係表示以4096QAM調變碼長16200、編碼率2/3之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖148係表示以4096QAM調變碼長64800、編碼率2/3之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖149係表示以4096QAM調變碼長16200、編碼率3/4之 W LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖150係表示以4096QAM調變碼長64800、編碼率3/4之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖151係表示以4096QAM調變碼長16200、編碼率4/5之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖152係表示以4096QAM調變碼長64800、編碼率4/5之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖153係表示以4096QAM調變碼長16200、編碼率5/6之 135786.doc • 300- 200937872 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖154係表示以4096QAM調變碼長64800、編碼率5/6之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖155係表示以4096QAM調變碼長16200、編碼率8/9之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖156係表示以4096QAM調變碼長64800、編碼率8/9之 LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖157係表示以4096QAM調變碼長64800、編碼率9/10之 ❹ LDPC碼,且倍數b為2之情況下之碼位元之替換之圖。 圖158係表示已進行替換處理之情況及未進行之情況下 之BER之模擬結果之圖。 圖1 59係表示已進行替換處理之情況及未進行之情況下 .之BER之模擬結果之圖。 圖160係表示已進行替換處理之情況及未進行之情況下 之BER之模擬結果之圖。 圖1 61係表示已進行替換處理之情況及未進行之情況下 〇 w 之BER之模擬結果之圖。 圖162係表示接收裝置12之結構例之區塊圖。 圖163係說明接收處理之流程圖。 圖164係表示LDPC碼之檢查矩陣之例之圖。 圖1 65係表示於檢查矩陣施以列置換及行置換後之矩陣 (轉換檢查矩陣)之圖。 圖166係表示分割為5x5單位之轉換檢查矩陣之圖。 圖167係表示匯總P個進行節點運算之解碼裝置之結構例 135786.doc •301 - 200937872 之區塊圖。 圖168係表示LDPC解碼部56之結構例之區塊圖。 圖1 69係表示適用本發明之電腦之一實施型態之結構例 之區塊圖。 圖170係表示編碼率2/3、碼長16200之檢查矩陣初始值 表之例之圖。 圖171係表示編碼率2/3、碼長64800之檢查矩陣初始值 表之例之圖。 〇 圖172係表示編碼率2/3、碼長64800之檢查矩陣初始值 表之例之圖。 圖173係表示編碼率2/3、碼長64800之檢查矩陣初始值 表之例之圖。 圖174係表示編碼率3/4、碼長16200之檢查矩陣初始值 表之例之圖。 圖175係表示編碼率3/4、碼長64800之檢查矩陣初始值 表之例之圖。 ❹ 圖176係表示編碼率3/4、碼長64800之檢查矩陣初始值 表之例之圖。 圖177係表示編碼率3/4、碼長64800之檢查矩陣初始值 表之例之圖。 圖178係表示編碼率3/4、碼長64800之檢查矩陣初始值 表之例之圖。 圖1 79係表示編碼率4/5、碼長16200之檢查矩陣初始值 表之例之圖。 135786.doc -302- 200937872 圖180係表示編碼率4/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖181係表示編碼率4/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖182係表示編碼率4/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖183係表示編碼率4/5、碼長64800之檢查矩陣初始值 表之例之圖。 〇 圖184係表示編碼率5/6、碼長16200之檢查矩陣初始值 表之例之圖。 圖185係表示編碼率5/6、碼長64800之檢查矩陣初始值 表之例之圖。 圖186係表示編碼率5/6、碼長64800之檢查矩陣初始值 表之例之圖。 圖187係表示編碼率5/6、碼長64800之檢查矩陣初始值 表之例之圖。 ® 圖188係表示編碼率5/6、碼長64800之檢查矩陣初始值 表之例之圖。 圖189係表示編碼率8/9、碼長16200之檢查矩陣初始值 表之例之圖。 圖190係表示編碼率8/9、碼長64800之檢查矩陣初始值 表之例之圖。 圖191係表示編碼率8/9、碼長64800之檢查矩陣初始值 表之例之圖。 135786.doc -303 - 200937872 圖192係表示編碼率8/9、碼長64800之檢查矩陣初始值 表之例之圖。 圖193係表示編碼率8/9、碼長64800之檢查矩陣初始值 表之例之圖。 圖194係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之例之圖。 圖195係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之例之圖。 © 圖196係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之例之圖。 圖197係表示編碼率9/10、碼長64800之檢查矩陣初始值 表之例之圖。 圖198係表示編碼率1/4、碼長64800之檢查矩陣初始值 表之例之圖。 圖199係表示編碼率1/4、碼長64800之檢查矩陣初始值 表之例之圖。 w 圖200係表示編碼率1/3、碼長64800之檢查矩陣初始值 表之例之圖。 圖201係表示編碼率1/3、碼長64800之檢查矩陣初始值 表之例之圖。 圖202係表示編碼率2/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖203係表示編碼率2/5、碼長64800之檢查矩陣初始值 表之例之圖。 135786.doc -304- 200937872 圖204係表示編碼率1/2、碼長64800之檢查矩陣初始值 表之例之圖。 圖205係表示編碼率1/2、碼長64800之檢查矩陣初始值 表之例之圖。 圖206係表示編碼率1/2、碼長64800之檢查矩陣初始值 表之例之圖。 圖207係表示編碼率3/5、碼長64800之檢查矩陣初始值 表之例之圖。 〇 圖208係表示編碼率3/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖209係表示編碼率3/5、碼長64800之檢查矩陣初始值 表之例之圖。 圖2 10係表示編碼率1/4、碼長16200之檢查矩陣初始值 表之例之圖。 圖211係表示編碼率1/3、碼長16200之檢查矩陣初始值 表之例之圖。 ® 圖212係表示編碼率2/5、碼長16200之檢查矩陣初始值 表之例之圖。 圖213係表示編碼率1/2、碼長16200之檢查矩陣初始值 表之例之圖。 圖214係表示編碼率3/5、碼長16200之檢查矩陣初始值 表之例之圖。 圖215係表示編碼率3/5、碼長16200之檢查矩陣初始值 表之其他例之圖。 135786.doc -305- 200937872 圖21 6係說明從檢查矩陣初始值表求出檢查矩陣Η之方法 之圖。 圖217係表示碼位元之替換例之圖。 圖218係表示碼位元之替換例之圖。 圖219係表示碼位元之替換例之圖。 圖220係表示碼位元之替換例之圖。 圖221係表示BER之模擬結果之圖。 圖222係表示BER之模擬結果之圖。 Ο 圖223係表示BER之模擬結果之圖。 圖224係表示BER之模擬結果之圖。 圖225係表示碼位元之替換例之圖。 圖226係表示碼位元之替換例之圖。 圖227係表示碼位元之替換例之圖。 圖228係表示碼位元之替換例之圖。 圖229係表示碼位元之替換例之圖。 圖230係表示碼位元之替換例之圖。 ® 圖23 1係表示碼位元之替換例之圖。 圖232係表示碼位元之替換例之圖。 圖233係表示碼位元之替換例之圖。 圖234係表示碼位元之替換例之圖。 圖2 3 5係表示碼位元之替換例之圖。 圖236係表示碼位元之替換例之圖。 圖237Α、Β係說明構成反交錯器53之多工器54之處理之 圖。 135786.doc -306- 200937872 圖238係說明縱行扭轉反交錯器55之處理之圖。 圖239係表示接收裝置12之其他結構例之區塊圖。 圖24〇係表示可適用於接收裝置12之接收系統之第1結構 例之區塊圖》 圖241係表示可適用於接收裝置12之接收系統之第2結構 例之區塊圖。 圖242係表示可適用於接收裝置12之接收系統之第3結構 例之區塊圖。 〇 【主要元件符號說明】 11 發送裝置 12 接收裝置 21 L D P C編碼部 22 位元交錯器 23 同位交錯器 24 縱行扭轉交錯器 25 解多工器 26 映射部 27 正交調變部 31 記憶體 32 替換部 51 正交解調部 52 解映射部 53 反交錯器 54 多工器 135786.doc 200937872 〇 ❹〇 LDPC code is an LDPC code with a code length of 1620 〇 bits and a coding rate of 3/5. Further modulation mode is 256QAM, multiple 1 is 1; in the case of multiplexer 25, in the traverse direction x The horizontal direction is (162 〇〇 / (8 χΐ)) χ (the code bits written by the memory 31 of the 8 兀 系 are in the course direction, are read out in 8 χΐ (four) ^ bit units, and are supplied to the replacement unit 32. The replacing unit 32 is configured to read the code bits b of the 8 x 1 (= mb) bits from the u + pw 目 己 己 3 3 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图The 8xl (= mb) bit symbol y 〇 "7 way" to replace the 8, mb) bit of the code bit b 〇 to by. 135786.doc • 276 · 200937872 that is, according to the figure 236. The replacing unit 32 is respectively: assigning the m-bit b〇 to the symbol bit y7, assigning the code bit b! to the symbol bit y3, and assigning the code bit b2 to the symbol bit y1 The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit y6, and the code bit 1>6 is assigned to the symbol Meta-bit y4, assigning code bit b7 to symbol bit y〇, and replacing Next, the deinterlacer 53 constituting the receiving device 12 will be described. Fig. 237 is a view for explaining the processing of the multiplexer 54 constituting the deinterleaver 53. That is, Fig. 237A shows a functional configuration example of the multiplexer 54. The multiplexer 54 is composed of the inverse replacement unit 1〇〇1 and the memory 1002. The multiplexer 54 is configured to correspond to the transmitting device by using the symbol bit supplied from the symbol of the previous demapping unit 52. The reverse replacement processing (reverse processing of the replacement processing) performed by the multiplexer 25 is performed, that is, the position of the code bit (symbol bit) of the LDPC code replaced by the replacement processing is performed. Returning to the reverse replacement processing of the original position, the LDPC code obtained as a result is supplied to the vertical twist reverse deinterleaver 55 of the subsequent stage. That is, in the multiplexer 54, the reverse replacement unit 1〇〇1 is (continuous The units of b symbols are supplied with the 00 bits of the b symbols y 〇, yi, · · ·, ymb-i 0 The inverse replacement unit 1001 performs the 00 bit symbol position Yuan...to~...back to 135786.doc •277· 200937872 Original mb bit code bit b0, bl,. The arrangement of the (9) structure (4) the replacement of the replacement unit 32 of the demultiplexer 25 on the U side of the sending device is reversed by the arrangement of the preceding code bits bG to bmw, and the bit obtained by the result is output. The code bits bG to bmH. The memory 10 0 2 is the same as the memory 31 constituting the demultiplexer 25 on the side of the transmitting device i, and is contained in the row (horizontal) direction memory 11) bit And: The memory capacity of the N/(mb) bit is stored in the column (longitudinal) direction. That is, the memory 1002 is composed of mb wales of memory N/(mb) bits. In the memory 1002, the code bit of the LDPC code outputted by the inverse replacement unit 1〇〇1 is performed in the direction in which the memory 31 of the demultiplexer of the transmitting device u reads the code bit. Writing is performed in the direction in which the memory bit is written to the memory 3, and the code bit written in the memory 1〇〇2 is read. That is, the multiplexer 54 of the receiving device 12, as shown in Fig. 237A, will be reversed. The code bits of the LDPC code outputted by 卩1001 are written in the order of .mb bits in the direction of the row from the first column of the memory 1〇〇2 to the following. Then, if the writing of the code bit of 1 code long is finished, the multiplexer 54 'reads the code bit from the waling direction from the suffix 1 〇〇 2 ' and supplies it to the rear section. The line twist reverse deinterlacer 5 5 . Here, Fig. 237B shows a reading from the code bits of the memory 1〇〇2. In the multiplexer 54, the code bits of the LDPC code are read from the top to the bottom (the wale direction) in the wales constituting the memory 1 〇〇 2 from the left to the right 135786.doc • 278 • 200937872 is carried out. Next, the processing of the whirling reverse deinterleaver 55 constituting the deinterleaver 53 of the receiving device 12 will be described with reference to FIG. 238 is a diagram showing an example of the structure of the memory 1002 of the multiplexer 54. The memory 1002 has a memory capacity in the longitudinal (longitudinal) direction and a memory capacity of N/(mb) bits in the horizontal (horizontal) direction, and is composed of mb wales. For the memory 1〇〇2, the device controls the write position of the code bit of the LDpc © code in the course direction and the readout position when reading in the wale direction. That is, the whirling reverse deinterleaver 5 5 is configured to appropriately change the start reading position of the start of the m-bit reading for the plurality of wales, thereby performing the arrangement of the code bits rearranged by the wandering parent error. Returning to the inverse rearrangement process of the original arrangement. Here, Fig. 238 shows a configuration example of the "remembered body 1 〇〇 2" in the case where the modulation method is 16QAM and the multiple b is 1. Therefore, the number of bits of the i symbol is 4 bits, and the memory 1〇〇2 is composed of 4 (= mb) vertical lines. The whirling torsional deinterlacer 55 (instead of the multiplexer 54) sequentially writes the code bits of the iLDpc code output from the replacement unit 1〇〇1 in the course direction from the first column of the memory 1002 toward the following. Then, if the writing of the code bit of 1 code long is finished, the whirling reverse deinterleaver 55 is a wales from the left to the right direction, and the code bit is moved from the memory 1002 from the top to the bottom (the wales) Read out of direction). The 'longitudinal torsional de-interlacer 55 is used to write the twentieth 135786.doc • 279· 200937872 interleaver 24 on the side of the transmitting device 11 into the opening of the code bit. s , 3 <The valve start position is read as the start position of the code bit, and the code bit is read from the memory 1〇〇2. That is, if the address of the position of the beginning (topmost) of each wales is set to the address of each position in the waling direction in an ascending integer, the modulation mode is 16QAM and the multiple b is 1. In the case of the walep reverse deinterleaver 55' with respect to the leftmost wales, the start reading position is set to the position where the address is 〇, and the second directional line (from the left) is set, and the read position is set as the address. For the position of 2, for the third wales, the start reading position is set to the position where the address is 4, and with respect to the 4th ordinate, the start reading position is set to the position where the address is 7. Further, regarding the start of the read position is a wales having a position other than the position of the 〇, the reading of the code bit is performed to the lowest position, and the return to the beginning (the address is the position of 〇) is performed until Readout before reading the position before the position is read. Then, the reading from the next (right) wales is performed thereafter. By performing the whirling de-interlacing as above, the arrangement of the code bits rearranged by the wobble interleaving will return to the original arrangement. Next, Fig. 239 is a block diagram showing another configuration example of the receiving device 12. In Fig. 239, the receiving device 12 receives the modulation signal from the transmitting device ’. The data processing device ’ is composed of a quadrature demodulating unit 51, a demapping unit 52, a reverse interleave 53 and an LDPC decoding unit 1〇21. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device 11, performs quadrature demodulation, and supplies the obtained symbols (values in the I and Q-axis directions) to the demapping unit 52. The demapping unit 52 performs the step of making the symbol from the orthogonal demodulation unit 51 135786. Doc -280· 200937872 The demapping of the code bits of the LDPC code is supplied to the deinterleaver 53 ^ The deinterleaver 53 is composed of a multiplexer 54, a longitudinal torsion deinterleaver 55 and a co-located deinterlacer 1 In other words, the multiplexer 54 performs the deinterlacing of the code bits of the LDPC code from the demapping unit. That is, the multiplexer 54 performs the LDpc code from the demapping unit 52 as the target, and corresponds to the transmitting device U. The inverse replacement processing (reverse processing of the replacement processing) performed by the multiplexer 25, that is, the reverse replacement of the position of the code bit replaced by the replacement processing is returned to the original position, and The LDPC code obtained as a result thereof is supplied to the whirling reverse deinterleaver 55. The whirling reverse deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs a whirling twist interleaver corresponding to the transmitting device lamp. The longitudinal torsional de-interlacing of the longitudinal torsion interleaving performed as a rearrangement process by 24 is performed. The LDPC code obtained as a result of the longitudinal torsional deinterlacing is supplied from the longitudinal torsional deinterlacer 55 to the in-phase deinterlacer. De-interlacer 101 The code bit element after the whirling de-interlacing of the inverse deinterleaver 55 is used as a target, and the co-interleave (the inverse processing of the co-located interleaving) corresponding to the co-interleave performed by the co-interleaver 23 of the transmitting device is performed, that is, The parity bit of the LDPC code arranged by the co-located interleave is returned to the original depolarization of the original arrangement. The LDPC code obtained as a result of the de-interlacing is supplied from the parrot deinterleaver 1011 to the LDPC decoding unit 1021. In the receiving device 12 of FIG. 239, the LDPC decoding unit 1021 is supplied with 135786 which has undergone reverse replacement processing, vertical reverse deinterlacing, and co-deverse interleaving. Doc -281 · 200937872 The LDPC code, that is, the LDPC code obtained by LDPC coding according to the check matrix. The LDPC decoding unit 1021 performs the LDPC encoding unit LDPC encoding unit 21 for the LDPC coded check matrix Η itself or the conversion check matrix obtained by performing at least the parity interleave row replacement for the check matrix ,. The LDPC code of the LDPC code of the interleaver 53 is decoded, and the data obtained as a result is output as a decoding result of the object data. Here, in the receiving apparatus 12 of FIG. 239, since the LDPC code obtained by the LDPC encoding according to the check matrix is supplied to the LDPC decoding section 1021 from the deinterleaver 53 (the same bit deinterleaver 1011), When the LDPC encoding unit 21 of the transmitting apparatus 11 performs LDPC decoding of the LDPC code by using the check matrix Η itself used for LDPC encoding, the LDPC decoding unit 1021 can sequentially perform a message (check node) by, for example, one node. Decoding device for performing LDPC decoding in the full serial decoding mode of the operation of the message, variable node message, or full parallel decoding (full ®) for simultaneously (parallel) the operation of the message for all nodes The parallel decoding method is configured by a decoding device that performs LDPC decoding. Further, the LDPC decoding unit 1021 performs LDPC decoding of the LDPC code by performing at least the conversion check matrix obtained by the row replacement of the co-interleave by the LDPC encoding unit 21 for the LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11. In the case of a decoding device capable of performing an architecture of a check node operation and a variable node operation at the same time, and including the conversion of the LDPC code to obtain a conversion Check the row of the matrix to replace the same row permutation to rearrange the 135786. Doc 282- 200937872 The decoding device of the received data rearrangement unit 31 of the LDPC code is constructed. Further, in FIG. 239, for convenience of explanation, the multiplexer 54 for performing the reverse replacement processing, the vertical twist reverse deinterleaver 55 for performing the tangent reverse deinterlacing, and the paraxial deinterlacer for the co-located deinterlacing are individually configured. 11. However, 2 or more of the multiplexer 54, the whirling reverse deinterleaver 55, and the in-situ deinterleaver 1〇11 may be the same as the co-interleaver 23, the whirling twist interleaver 24, and the demultiplexer 25 of the transmitting device 11. The ground is composed in one piece. © Fig. 240 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. In Fig. 240, the receiving system is composed of an obtaining unit 1101, a channel decoding processing unit 1102, and an information source decoding processing unit 11〇3. The acquisition unit 1101 obtains, by means of, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, Internet, and other networks, a transmission channel including at least LDPC encoding of image data such as image data or audio data of the program. The signal of the obtained LDPC code is supplied to the channel decoding ◎ processing unit 1102. In the case where the signal acquired by the acquisition unit 1101 is played back from the broadcast station via a ground wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 1101 is a level adjuster or an STB ( Set Top Box: Set-top box). In the case where the signal acquired by the acquisition unit lio is transmitted by multicast from a web server such as IPTV (Internet Protocol Television), the acquisition unit 1101 is, for example, an NIC (Network Interface Card: Network interface card), etc. 135786. Doc -283 - 200937872 Network I/F (Interface: interface). The transmission channel decoding processing unit 1102 applies a channel decoding process including at least a process of making a mistake in the transmission path to the signal acquired by the acquisition unit 丨1〇1 via the transmission channel, and supplies the signal obtained as a result. The information source decoding processing unit 1103 is used. In other words, the signal obtained by the acquisition unit 1101 via the transmission channel is a signal obtained by at least performing error correction coding for correcting the error generated by the transmission path, and the transmission channel decoding processing unit 1102 applies the signal to the signal. The channel decoding processing is performed by, for example, error correction processing. Here, as the error correction code, there are, for example, LDPC code or Lie Solomon code. Here, at least the lDPC encoding is performed as the error correction code. Moreover, the transmission channel decoding process may include demodulation of a modulated signal or the like. The information source decoding processing unit 1103 applies an information source decoding process including at least a process of stretching the compressed information into the original information for the signal subjected to the channel gamma processing. That is, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding of compressed information in order to reduce the amount of data such as images or sounds of information. In this case, the information source decoding processing unit 1103 is For the signal subjected to the channel decoding processing, information source decoding processing such as processing (stretching processing) of compressing the information into the original information is performed. Further, when the signal acquired by the acquisition unit 110 via the transmission path is not subjected to compression coding, the information source decoding processing unit 1103 does not perform the process of extending the compressed information into the original information. 135786. Doc-284-200937872 Here, as the stretching processing, for example, mpeg decoding or the like is used. Moreover, the channel decoding processing may include a descrambling code or the like in addition to the stretching processing. In the reception system configured as described above, the acquisition unit 1101 performs compression coding such as MPEG encoding on data such as images and audio, and further acquires a signal of error correction coding such as LDPC coding via the transmission path and supplies it. To the transmission channel decoding processing unit 102. The channel decoding processing unit 1102 applies, for example, to the orthogonal demodulation unit 51 or the demodulation unit 52, the deinterleaver 53, and the LDPC decoding unit 56 as the channel decoding processing for the signal from the acquisition unit 1101 ( Alternatively, the LDPC decoding unit 1021) performs the same processing, and the signal obtained as a result is supplied to the information source decoding processing unit 11 〇3. The information source decoding processing unit 1103 applies an information source decoding process such as decoding to the channel decoding processing unit 1102, and outputs an image or sound obtained as a result. The receiving system of the diagram 240 on X can be applied to, for example, a television level adjuster that receives a television broadcast as a digital video player. Further, the acquisition unit lioi, the transmission channel decoding processing unit 11〇2, and the information source decoding processing unit 1103 respectively It can be configured as a separate device (hardware (1 (: Integrated Circuit), etc.) or a software module). Further, the acquisition unit 1101, the channel decoding processing unit n〇2, and the information source The decoding processing unit 1103 can transmit the acquisition unit 11〇1 and the set of the transmission channel decoding processing unit 1102, or the set of the channel decoding processing unit 11〇2 and the information source decoding processing unit 11〇3, and the acquisition unit 1101. The set of the channel decoding processing unit ιι〇2 and the information source decoding processing unit 1103 is configured as a separate device. Doc-285-200937872 Figure 241 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. In the drawings, the parts corresponding to those in the case of Fig. 240 are attached with the same reference numerals, and the description thereof will be omitted as appropriate. The receiving system of FIG. 241 is the point where the receiving unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 are included, and is similar to the case where the output unit 1111 is newly provided, and FIG. 240 The situation is different. The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs an audio, and outputs an image or sound as a signal output from the information source decoding processing unit 1103. That is, the output unit U11 displays an image or outputs a sound. The receiving system as shown in Fig. 241 above can be applied to, for example, a TV (television receiver) that receives television broadcast as digital broadcast, or a broadcast receiver that receives broadcast broadcast, and the like. Further, when the signal acquired by the acquisition unit 1101 is not subjected to compression coding, the signal output from the transmission channel decoding processing unit 1102 is supplied to the output port 1 m. Fig. 242 shows the reception applicable to the reception device 12. Block diagram of the third structural example of the system. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 240, and the description thereof will be omitted as appropriate. The receiving system of Fig. 242 is the same as the case of Fig. 240, in the point that the acquisition unit 11〇1 and the channel decanting unit 1102 are included. The receiving system of FIG. 242 is not provided with the information source decoding processing unit 135786. Doc -286· 200937872 11 03 and the new recording unit ii21 is different from the case of Fig. 24〇. The s recording unit 1121 records the washing (for example, the TS packet of the MPEG TS) outputted by the channel gamma processing unit 1102, and records (memorizes) the optical disk or the hard disk (magnetic disk), flashing. Record (memory) media such as memory. The receiving system as shown in Fig. 242 above can be applied to a video recorder or the like which records a television broadcast. Further, in FIG. 242, the receiving system is configured by the information source decoding processing unit 1103, and the information source decoding processing unit 11〇3 can record the signal subjected to the information source decoding processing by the recording unit 1121, that is, by Decode the image or sound obtained. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining a check matrix H of an LDPC code. Figure 2 is a flow chart showing the decoding procedure of the LDPC code. Fig. 3 is a view showing an example of a check matrix of an LDPC code. Fig. 4 is a view showing a graph of the check matrix &111161>. Figure 5 is a diagram showing a variable node. Figure 6 is a diagram showing a check node. Fig. 7 is a view showing an example of a configuration of an embodiment of a transport system to which the present invention is applied. Fig. 8 is a block diagram showing a configuration example of the transmission device &> α and the clothing set 11. Figure 9 is a diagram showing an inspection matrix. Fig. 10 is a view showing a parity matrix. I35786. Doc •287· 200937872 Figure 1 ΙΑ, B is DVB-S. The check matrix and row weight map of the LDPC code specified in the specification of 2. 12A and B are diagrams showing the signal point arrangement of 16QAM. Figure 13 is a diagram showing the signal point configuration of 64QAM. Figure 14 is a diagram showing the signal point configuration of 64QAM. Figure 15 is a diagram showing the signal point configuration of 64QAM. 16A-D are diagrams illustrating the processing of the multiplexer 25. 17A and B are diagrams for explaining the processing of the multiplexer 25. © Fig. 1 8 is a diagram showing a Tanner graph of decoding of an LDPC code. 19A and 19B are diagrams showing a parity matrix Ητ which is a step structure and a Tanner graph corresponding to the parity matrix Ητ. Figure 20 is a diagram showing the parity matrix Ητ of the check matrix 对应 corresponding to the LDPC code after the co-located interleaving. Fig. 21A and Fig. 21 are views showing a conversion check matrix. Fig. 22 is a view showing the processing of the whirling twist interleaver 24. Fig. 23 is a view showing the number of wales of the memory 3 1 and the address of the start writing position of the memory 3 1 necessary for the whirling of the wales. Fig. 24 is a view showing the number of wales of the memory 3 1 and the address at which the writing position is started, which are necessary for the whirling of the wagger. Fig. 25 is a flow chart showing the transmission processing. 26A and 26B are diagrams showing a model of a communication channel used in the simulation. Fig. 27 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency fd of the flutter. Figure 28 shows the error rate obtained by the simulation and the flutter frequency of the flutter 135786. Doc • 288- 200937872 Diagram of the relationship between fd. FIG. 29 is a block diagram showing a configuration example of the LDPC encoding unit 21. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21. Fig. 31 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 16200. Figure 32 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 33 is a view showing a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 34 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 35 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200. Fig. 36 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 37 is a diagram showing the initial value of the check matrix of the coding rate of 3/4 and the code length of 64,800. Fig. 38 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 39 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 40 is a view showing a check matrix initial value table of a coding rate of 4/5 and a code length of 16200. Figure 41 is a table showing the initial value of the check matrix of the coding rate of 4/5 and the code length of 64,800. Doc -289- 200937872. Fig. 42 is a view showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Figure 43 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 44 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 45 is a view showing an initial value of the check matrix of a coding rate of 5/6 and a code length of 16,200. Fig. 46 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 47 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 48 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 49 is a diagram showing the initial value of the check matrix of the coding rate of 5/6 and the code length of 64,800. Fig. 50 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 16200. Figure 51 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 52 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 53 is a table showing the initial value of the check matrix of the coding rate of 8/9 and the code length of 64,800. Doc -290- 200937872 Picture. Fig. 54 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 55 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 56 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 57 is a diagram showing the initial value of the inspection matrix of the coding rate of 9/10 and the code length of 64800. Fig. 58 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 59 is a view for explaining a method of obtaining a check matrix 从 from a check matrix initial value table. Figures 60A through C are diagrams illustrating the replacement process of the current mode. Fig. 61Α~C are diagrams showing the replacement processing of the current mode. 62A and B are diagrams showing a group of code bits and a group of symbol bits in the case where an LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 63 is a diagram showing the distribution rule in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 64A and Fig. 64 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 2/3 is modulated by 1024QAM and the multiple b is 1. 65A and B show a modulation code length of 64800 with a 1024QAM and a coding rate of 135786. Doc -291 - 200937872 2/3 LDPC code in the case of the code bit group and the symbol bit group. Fig. 66 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 67A and Fig. 67 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 2/3 is modulated by 1024QAM and the multiple b is 1. Fig. 68A and Fig. 68 are diagrams showing a group of code bits and a group of symbol bits in the case where the LDPC code having a code length of 16200 and a coding rate of / 3/4 is modulated by 1024QAM. Fig. 69 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM. Fig. 70A and Fig. 70 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 3/4 is modulated by 1024QAM and the multiple b is 1. 71A and FIG. 7B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of /3/4 is modulated by 1024QAM. Fig. 72 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM. Fig. 73A and Fig. 73 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 3/4 is modulated by 1024QAM and the multiple b is 1. Figure 74A, B shows the modulation code length of 16200 with 1024QAM, coding rate 135786. Doc -292- 200937872 4/5 LDPC code in the case of the code bit group and the symbol bit group. Fig. 75 is a diagram showing the distribution rule |J in the case where the LDPC code having a code length of 16200 and a coding rate of 4/;5 is modulated by 1024QAM. 76A and FIG. 76B are diagrams showing the replacement of the megabits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 1024QAM and the multiple b is 1. 77A and 77B are diagrams showing a code bit group and a symbol bit group in the case of 1024QAM modulation code length 64800 and LDPC code of 4/5/5. Fig. 78 is a diagram showing the distribution rule 1j in the case where the LDPC Ma is modulated by a code length of 64800 and a coding rate of 4/5. 79A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the 1024CAM modulation code length 64800, the coding rate 4/5 LDPC code', and the multiple b is 1. 80A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 162 〇〇 and an encoding rate of / 5/6 is modulated by 1024QAM. Fig. 81 is a diagram showing an allocation rule 1J in the case where an LDPC code having a code length of 162 〇〇 and a coding rate of 5/6 is modulated by 1024QAM. Fig. 82A and Fig. 82 are diagrams showing the replacement of the code bits in accordance with the allocation rule in the case where the LDPC code ′ of the coding length of 162 〇〇 and the coding rate of 5/6 is modulated by 1024QAM and the multiple 13 is 丨. Fig. 83A and Fig. B show the a1〇24QAM modulation length 648〇〇, coding rate 135786. Doc • 293 200937872 5/6 LDPC code in the case of the code bit group and the symbol bit group. Fig. 84 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM. 85A and FIG. 85 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 1. 86A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM. Fig. 87 is a diagram showing an allocation rule |J in the case where an LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM. 88A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 1024QAM and the multiple b is 1. 89A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 4.8/9 is modulated by 1024QAM. Fig. 90 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 1024QAM. 91A and FIG. 26B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 1024QAM and the multiple b is 1. Figure 92A and Figure B show the modulation code length of 64800 with 1024QAM and the coding rate of 135786. Doc -294- 200937872 9/10 LDPC code in the case of the code bit group and the symbol bit group. Fig. 93 is a diagram showing the distribution rule in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM. Fig. 94A and Fig. 94 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM and the multiple b is 1. Fig. 95A and Fig. 95 are diagrams showing a group of code bits and a group of symbol bits in the case where the LDPC code having a code length of 16200 and a coding rate of / 2/3 is modulated by 4096QAM. Fig. 96 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM. 97A and FIG. 97B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 1. 98A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM. Fig. 99 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM. Figs. 100A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 1. Figure 101A, B shows the modulation code length of 16200 with 4096QAM, coding rate 135786. Doc -295 - 200937872 The diagram of the code bit group and the symbol bit group in the case of the 3/4 LDPC code. Fig. 102 is a diagram showing a distribution rule ij in the case where an LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM. Fig. 103A and Fig. 103 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 1. Figs. 104A and B are views showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of / 3/4 is modulated by 4096QAM. Fig. 105 is a diagram showing an allocation rule 1J in the case where an LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM. Fig. 106A and Fig. 106 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 1. 107A and B are diagrams showing a group of code bits and a group of symbol bits in the case where an LDPC code having a code length of 16200 and a coding rate of W 4/5 is modulated by 4096QAM. Fig. 108 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM. Figs. 109A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 4096QAM and the multiple b is 1. Figure 110A, B shows the modulation code length of 64800 with 4096QAM, coding rate 135786. Doc -296· 200937872 4/5 LDPC code in the case of the code bit group and the symbol bit group. Fig. 111 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM. Fig. 112A and Fig. 4B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 1. 113A and FIG. 31B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of / 5/6 is modulated by 4096QAM. Fig. 114 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM. Figs. 115A and 1B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 1. Fig. 116A and Fig. 116 are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate 〇 w 5/6 is modulated by 4096QAM. Figure 117 is a diagram showing the allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM. Fig. 118A and Fig. 118 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 1. Figure 119A, B shows the modulation code length of 16200 with 4096QAM, coding rate 135786. Doc -297- 200937872 The figure of the code bit group and the symbol bit group in the case of the 8/9 LDPC code. Fig. 120 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM. 121A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 4096QAM and the multiple b is 1. Figs. 122A and B are views showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of / 8/9 is modulated by 4096QAM. Figure 123 is a diagram showing an allocation rule in the case where an LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM. Fig. 124A and Fig. 124 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 4096QAM and the multiple b is 1. Figs. 125A and B are views showing a code bit group and a symbol bit group in the case where an LDPC code having a code length of 64800 and a coding rate of w 9/10 is modulated by 4096QAM. Figure 126 is a diagram showing a distribution rule ij in the case where an LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 4096QAM. 127A and BB are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 4096QAM and the multiple b is 1. Figure 128 is a diagram showing the signal point configuration of 1024QAM. 135786. Doc -298· 200937872 Figure 129 is a diagram showing the signal point configuration of 4096QAM. Fig. 130 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 131 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 132 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Figure 133 is a diagram showing the simulation results of the BER after the replacement process has been performed and the case where the process has not been performed. Figures 134A-C are diagrams showing the replacement of the code bits in the case where the multiple b is 1. Figs. 135A to CG are diagrams showing the replacement of the code bits in the case where the multiple b of the replacement mode of the code bit in the case where the multiple b is 1 is used. Figure 136 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Figure 137 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Figure 138 is a diagram showing replacement of code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Figure 139 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Fig. 140 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. Figure 141 shows the modulo code length of 64800 with 1024QAM and the coding rate of 4/5. Doc -299- 200937872 LDPC code, and the replacement of the code bits in the case of multiple b is 2. Figure 142 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Figure 143 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Figure 144 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. Figure 145 is a diagram showing the replacement of the code bits in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. Figure 146 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM and the multiple b is 2. Figure 147 is a diagram showing replacement of code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Figure 148 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Figure 149 is a diagram showing the replacement of the code bits in the case where the W LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Fig. 150 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Figure 151 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Figure 152 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Figure 153 shows the 4096QAM modulation code length of 16200 and the coding rate of 5/6. Doc • 300- 200937872 LDPC code, and the replacement of the code bits in the case of multiple b is 2. Figure 154 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Figure 155 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figure 156 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figure 157 is a diagram showing the replacement of the code bits in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 4096QAM and the multiple b is 2. Figure 158 is a diagram showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 1 59 shows the case where the replacement process has been performed and the case where it has not been performed. A diagram of the simulation results of the BER. Fig. 160 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 1 is a diagram showing the simulation results of the BER of the 〇 w in the case where the replacement process has been performed and the case where the replacement process has not been performed. Fig. 162 is a block diagram showing a configuration example of the receiving device 12. Figure 163 is a flow chart illustrating the receiving process. Figure 164 is a diagram showing an example of a check matrix of an LDPC code. Fig. 1 is a diagram showing a matrix (conversion check matrix) after the column replacement and row replacement are applied to the inspection matrix. Figure 166 is a diagram showing a conversion check matrix divided into 5x5 units. Figure 167 is a diagram showing an example of a structure in which P decoding devices performing node operations are summarized. Doc • Block diagram of 301 - 200937872. 168 is a block diagram showing a configuration example of the LDPC decoding unit 56. Fig. 1 is a block diagram showing a configuration example of an embodiment of a computer to which the present invention is applied. Fig. 170 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 16,200. Figure 171 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. 〇 Fig. 172 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 173 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 174 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 16200. Figure 175 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. ❹ Figure 176 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 177 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 178 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Fig. 1 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 16200. 135786. Doc -302- 200937872 Fig. 180 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 181 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 182 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 183 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. 〇 Fig. 184 is a diagram showing an example of an initial value of a check matrix of a coding rate of 5/6 and a code length of 16200. Figure 185 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 186 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 187 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. ® Figure 188 is a diagram showing an example of the initial value of the inspection matrix with a coding rate of 5/6 and a code length of 64,800. Figure 189 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 16200. Figure 190 is a diagram showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 191 is a diagram showing an example of an initial value of a check matrix of a coding rate of 8/9 and a code length of 64,800. 135786. Doc -303 - 200937872 Figure 192 is a diagram showing an example of an initial value of the check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 193 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 194 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 195 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. © Fig. 196 is a diagram showing an example of an initial value of the check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 197 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 198 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. Figure 199 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. w Fig. 200 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 64,800. Fig. 201 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 64,800. Fig. 202 is a diagram showing an example of a check matrix initial value table of a coding rate of 2/5 and a code length of 64,800. Figure 203 is a diagram showing an example of a check matrix initial value table of a coding rate of 2/5 and a code length of 64,800. 135786. Doc -304- 200937872 Fig. 204 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 64,800. Figure 205 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 64,800. Fig. 206 is a view showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 64,800. Figure 207 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. 〇 Figure 208 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Figure 209 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Fig. 2 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 16,200. Figure 211 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 16200. ® Figure 212 is a diagram showing an example of an initial value of the check matrix of a coding rate of 2/5 and a code length of 16200. Figure 213 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 16,200. Figure 214 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 16200. Figure 215 is a diagram showing another example of the check matrix initial value table of the coding rate 3/5 and the code length 16200. 135786. Doc -305- 200937872 Fig. 21 6 is a diagram illustrating a method of obtaining a check matrix 从 from a check matrix initial value table. Figure 217 is a diagram showing an alternative of a code bit. Figure 218 is a diagram showing an alternative of a code bit. Figure 219 is a diagram showing an alternative of a code bit. Figure 220 is a diagram showing an alternative of a code bit. Figure 221 is a diagram showing the simulation result of BER. Figure 222 is a diagram showing the simulation result of the BER. Ο Figure 223 is a diagram showing the simulation results of BER. Figure 224 is a diagram showing the simulation result of BER. Figure 225 is a diagram showing an alternative of a code bit. Figure 226 is a diagram showing an alternative of a code bit. Figure 227 is a diagram showing an alternative of a code bit. Figure 228 is a diagram showing an alternative of a code bit. Figure 229 is a diagram showing an alternative of a code bit. Figure 230 is a diagram showing an alternative of a code bit. ® Figure 23 1 is a diagram showing an alternative to a code bit. Figure 232 is a diagram showing an alternative of a code bit. Figure 233 is a diagram showing an alternative of a code bit. Figure 234 is a diagram showing an alternative of a code bit. Figure 2 3 5 shows a diagram of an alternative to a code bit. Figure 236 is a diagram showing an alternative of a code bit. Fig. 237A and Β are diagrams showing the processing of the multiplexer 54 constituting the deinterleaver 53. 135786. Doc-306-200937872 Figure 238 is a diagram illustrating the processing of the whirling torsional deinterlacer 55. Figure 239 is a block diagram showing another configuration example of the receiving device 12. Fig. 24 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. Fig. 241 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. Figure 242 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12. 〇[Main component symbol description] 11 Transmitting device 12 Receiving device 21 LDPC encoding unit 22 Bit interleaver 23 Co-located interleaver 24 Vertical twist interleaver 25 Demultiplexer 26 Mapping unit 27 Quadrature modulation unit 31 Memory 32 Substitution unit 51 orthogonal demodulation unit 52 demapping unit 53 deinterleaver 54 multiplexer 135786. Doc 200937872 〇 ❹
55 縱行扭轉反交錯器 56 LDPC解碼部 300 分枝資料儲存用記憶體 301 選擇器 302 校驗節點計算部 303 循環移位電路 304 分枝資料儲存用記憶體 305 選擇器 306 接收資料用記憶體 307 可變節點計算部 308 循環移位電路 309 解碼字計算部 310 接收資料重排部 311 解碼資料重排部 601 編碼處理部 602 記憶部 611 編碼率設定部 612 初始值表讀出部 613 檢查矩陣生成部 614 資訊位元讀出部 615 編碼同位運算部 616 控制部 701 匯流排 702 CPU 135786.doc -308- 20093787255 vertical twist deinterleaver 56 LDPC decoding unit 300 branch data storage memory 301 selector 302 check node calculation unit 303 cyclic shift circuit 304 branch data storage memory 305 selector 306 receiving data memory 307 variable node calculation unit 308 cyclic shift circuit 309 decoded word calculation unit 310 received data rearrangement unit 311 decoded data rearrangement unit 601 coding processing unit 602 memory unit 611 coding rate setting unit 612 initial value table reading unit 613 inspection matrix Generating unit 614 Information bit reading unit 615 Coding unit calculating unit 616 Control unit 701 Bus bar 702 CPU 135786.doc -308- 200937872
703 ROM 704 RAM 705 硬碟 706 輸出部 707 輸入部 708 通訊部 709 磁碟機 710 輸出入介面 711 可移式記錄媒體 1001 反替換部 1002 記憶體 1011 同位反交錯器 1021 LDPC解碼部 1101 取得部 1102 傳送道解碼處理部 1103 資訊源解碼處理部 1111 輸出部 1121 記錄部 135786.doc 309-703 ROM 704 RAM 705 Hard disk 706 Output unit 707 Input unit 708 Communication unit 709 Disk drive 710 Input/output interface 711 Portable recording medium 1001 Reverse replacement unit 1002 Memory 1011 Parrot deinterleaver 1021 LDPC decoding unit 1101 Acquisition unit 1102 Transmission channel decoding processing unit 1103 Information source decoding processing unit 1111 Output unit 1121 Recording unit 135786.doc 309-
Claims (1)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007304690 | 2007-11-26 | ||
JP2007304689 | 2007-11-26 | ||
JP2008070467 | 2008-03-18 | ||
JP2008155789 | 2008-06-13 | ||
JP2008185605 | 2008-07-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200937872A true TW200937872A (en) | 2009-09-01 |
Family
ID=40678521
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW97145355A TW200937872A (en) | 2007-11-26 | 2008-11-24 | Data processing device and data processing method |
Country Status (2)
Country | Link |
---|---|
TW (1) | TW200937872A (en) |
WO (1) | WO2009069626A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI513252B (en) * | 2009-10-30 | 2015-12-11 | Ericsson Telefon Ab L M | Method and apparatus for merging bit probability information in serial localization with indecision |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7165205B2 (en) * | 2004-05-14 | 2007-01-16 | Motorola, Inc. | Method and apparatus for encoding and decoding data |
KR20060097503A (en) * | 2005-03-11 | 2006-09-14 | 삼성전자주식회사 | Channel interleaving/de-interleaving apparatus in a communication system using a low density parity check code and control method thereof |
JP2007214783A (en) * | 2006-02-08 | 2007-08-23 | Kddi Corp | Transmission device, reception device, and transmitting method |
-
2008
- 2008-11-24 TW TW97145355A patent/TW200937872A/en unknown
- 2008-11-26 WO PCT/JP2008/071397 patent/WO2009069626A1/en active Application Filing
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI513252B (en) * | 2009-10-30 | 2015-12-11 | Ericsson Telefon Ab L M | Method and apparatus for merging bit probability information in serial localization with indecision |
Also Published As
Publication number | Publication date |
---|---|
WO2009069626A1 (en) | 2009-06-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI459724B (en) | Data processing device and data processing method | |
TWI390856B (en) | Data processing device and data processing method | |
TWI538415B (en) | Data processing device and data processing method | |
TWI410055B (en) | Data processing device, data processing method and program product for performing data processing method on computer | |
JP5630282B2 (en) | Data processing apparatus and data processing method | |
JP5664919B2 (en) | Data processing apparatus and data processing method | |
TWI377793B (en) | ||
TWI497920B (en) | Data processing device and data processing method | |
JP5672489B2 (en) | Data processing apparatus and data processing method | |
JP5500379B2 (en) | Data processing apparatus and data processing method | |
JP5505725B2 (en) | Data processing apparatus and data processing method | |
JP5630283B2 (en) | Data processing apparatus and data processing method | |
TWI389460B (en) | Data processing device and data processing method | |
WO2012147623A1 (en) | Data processing device and data processing method | |
WO2012098984A1 (en) | Data-processing device and data-processing method | |
WO2012002238A1 (en) | Data processing device and data processing method | |
JP2012151656A (en) | Data processing device and data processing method | |
TW200947880A (en) | Data process device and data process method | |
WO2012050020A1 (en) | Data processing device, and data processing method | |
TW200937872A (en) | Data processing device and data processing method | |
JP2012235269A (en) | Data processing device and data processing method | |
JP2012004873A (en) | Data processor and data processing method | |
WO2012002237A1 (en) | Data processing device and data processing method | |
TW200947881A (en) | Data processing device and data processing method | |
JP2012239130A (en) | Data processing device and data processing method |