TW200937872A - Data processing device and data processing method - Google Patents

Abstract

A data processing device and method in which resistance to an error of data can be improved. A demultiplexer (25) rearranges mb bits of code bits and defines the rearranged code bits as b pieces of symbols of symbol bits according to an assignment rule to assign the code bits of an LDPC code to symbol bits representing symbols. The assignment rule defines groups grouped into the code bits and the symbol bits according to error probability as a code bit group and a symbol bit group, respectively, a combination of the code bit group and the symbol bit group of symbol bits to assign the code bits of the code bit group, and the number of bits of code bits and symbol bits. The data processing device and method can be applied to, e.g., a transmission system or the like to transmit an LDPC code.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus and a data processing method, and more particularly to a data processing apparatus and a data processing method which can improve the tolerance to errors such as data. [Prior Art] The LDPC code has a high degree of error correction capability, and has been widely used in recent years for transmission methods including, for example, DVB (Digital Video Broadcasting φ)-S.2 satellite digital broadcasting in Europe ( For example, Non-Patent Document 1). Moreover, the LDPC code is also reviewed for use in the next generation of terrestrial digital broadcasting. According to recent research, the LDPC code system is the same as the turbo code, and as the code length increases, the performance close to the Shannon limit is obtained. Moreover, since the LDPC code has a property that the minimum distance is proportional to the code length, it has a good probability of error in the characteristics of the block, and further advantages are also obtained by observing the decoding characteristics of the turbo code or the like. The so-called error floor phenomenon. Hereinafter, the LDPC code of this type will be specifically described. Further, the LDPC code is a linear code and is not necessarily binary, but is described here as a binary. The biggest feature of the LDPC code is that the parity check matrix (parity check matrix) defining the LDPC code is loose. Here, the loose matrix refers to a matrix with a very small number of matrix elements "1" (most of the elements are matrixes of 0). Fig. 1 is a diagram showing an example of a check matrix LDP of an LDPC code. 135786.doc 200937872 In the check matrix of Figure 1, the weight of each row (the weight of the row) ("1" the weight) is "3", and the weight of each column (column weight) is "6" . The encoding is performed by the LDPC code (LDPC encoding), for example, according to the check matrix Η, and the generating matrix G is multiplied for the binary information bits, thereby generating a codeword (LDPC code). . Specifically, the coding apparatus that performs LDPC coding first calculates a generation matrix G in which the equation GHT = 0 is established between the transposed matrix Ητ of the check matrix 。. In the case where the 'generating matrix G is a K>N matrix, the encoding device multiplies the bit matrix (vector u) of the information bits composed of K bits by the generating matrix G, and generates N bits. The code word c(=uG) composed of the code word (LDPC code) generated by the encoding device is received on the receiving side via a specific communication channel. The decoding system of the LDPC code is called Gallager. Probabilistic Decoding (Probabilistic Decoding) algorithm can be used by a variable node (also known as a message node) and a check node. The message propagation algorithm of the probability transfer (belief pr〇pagati〇n) on the Tanner graph is performed. Here, the variable node and the check node are also simply referred to as nodes in the following. FIG. 2 is a decoding procedure of the LDPC code. In addition, the value of the third code bit of the LDPC code (1 code word) received by the receiving side represented by the log-like probability ratio (log like Uh〇〇d rati〇) is suitably hereinafter "0" The real value of the degree is called the received value..." Moreover, the message output from the check node is set to Uj 'The message output from the variable node is set to 135786.doc 200937872 First, in the decoding of the LDPC code, As shown in FIG. 2, in step SH, the LDPC code is received, the message (check node message) Uj is initialized to "〇", and the variable k which is determined as the integer of the counter of the repeated processing is initialized to "〇" And proceeding to step S12. In step S12, the operation (variable node operation) of equation (1) is performed by the received value uGi ' obtained by receiving the LDpc code to obtain a message (variable node information) Vi, and further obtains the message Φ Uj by performing the operation (check node operation) according to the equation (2) according to the message L '. [1] dv-1

Vi=U〇j+ Σ Uj j=1 • · · (1) [Number 2] tanh

Ui : Vtanh

Vi

• (2) Here, the dv and de of the equations (1) and (2) respectively indicate that the number of the longitudinal (row) and the horizontal (column) of the inspection matrix h can be arbitrarily selected. The parameters are, for example, in the case of the code (3, 6), dv = 3, and de = 6. In addition, the variable node operation of equation (1) and the check node operation of (2) are not branched from the desired output (edge: edge) (the line connecting the variable node and the check node) The input message is the object of the operation, so the calculation range is from 1 to dv-l, or from 1 to dc-l. Moreover, the check node operation of the equation (2) is actually performed by a function r(Vi, V2) which is not previously produced by the equation (3) which is 疋 786786.doc 200937872 for 2 inputs V1, v2. The table was carried out continuously (regressively) as shown in the formula (4). [Equation 3] x=2tanh~i {tanh (ν,/2) tanh (v2/2) J =R (Vl, v2) • · · (3) [Number 4] uj =R (V!,R ( V2, R (v3, _ . . . . ( ( ( ( ( ( ( ( ( ( In step Si3, it is determined whether the variable ^^ is greater than a specific number of repeated decodings C. In step S13, if the variable k is not greater than 〇, the process returns to step S12, and the same process is repeated below. Further, if it is determined in step s13 that the variable k is larger than 匚, the process proceeds to step S14', and the operation shown in the equation (5) is performed to obtain and output the message Vi as the final output decoding result, and the decoding process of the LDpc code is performed. end. Φ [number 5] dy

Vi=U〇i+ Σ Uj j=1 • · · (5) Here, the operation of equation (5) is different from the variable node operation of the equation, using the message Uj from all the branches connected to the variable node. get on. 3 is a diagram showing an inspection matrix ( of a (3, 6) LDPC code (coding rate 1/2, code length 12) in the inspection matrix η of FIG. 3, which is the same as the figure ,, respectively, the weight of the row is 135786. Doc 200937872 is 3, with a weight of 6. Figure 4 is a Tanner diagram showing the inspection matrix of Figure 3. Here, in Fig. 4, the check node is represented by "+ ", and the variable node is represented by "=". The check node and the variable node correspond to the column and row of the check matrix 11, respectively. The knot between the node and the variable node is branch (edge: edge), which is equivalent to the element of the check matrix "1 ·, that is, when the element of the i-th row of the j-th column of the check matrix is 丨, Figure 4, by branching from the upper i-th variable node ("=" node) and from the top ❿" check node (" + ” node). The branching system indicates that the meta-bit corresponding to the variable node has a constraint condition corresponding to the check node. The variable node operation and the check node operation are repeated for the sum product operation method (Sum pr〇d(10) Algorithm) of the decoding method of the LDPC code. Figure 5 shows the variable node operation performed at the variable node. In the variable node, the message corresponding to the branch to be calculated is read by the message from the remaining branches connected to the variable node... and ", and the variable of the formula (1) using the receiving parameter u〇i The node calculation is performed in the same manner. The message corresponding to the other branches is also obtained in the same manner. Fig. 6 shows the check node operation performed by the check node. Here, the check node operation of the equation (2) is available. The relationship between axb=eXp{ln(丨a|)+ln(|bl)bsign(a)xsign(b) is rewritten as ^(6), where Sign(x) is 1 and is at χ< 〇时为,i. " 135786.doc -10- 200937872 [Number 6] d〇-1

Uj=2tanh-1 JT tanh

Vi .-1 : 2tanh' : 2tanh_1 exp exp Σ In f dR-1

Tanh I

Vi Σ - In tanhl ^xVsign(tanh(-y lvj| dc -1x Π sign(Vj) i=1 • (6) Ο Further, at x2 0, if the function Φ(χ) is defined as the formula (Kx ) = ln(tanh(x/2)), then the formula φ-丨(x):=2tanh-丨(eX) holds, so the equation (6) can be transformed into the equation (7).

Ui = 0 \ dc-1 ;Σ 0(|Vi|)l X Π sign(Vj) (7) --· v7 / In the check node, the check node operation of equation (2) is according to equation (7) To perform the check, that is, at the check node, such as 囷6, the message Uj corresponding to the branch to be calculated is by using the message VI'V2'V3'V4 from the remaining branch connected to the check node. The check node operation of the formula (7) of V5 is obtained. The message corresponding to the other branches is also obtained in the same manner. Further, the function φ(χ) of the equation (7) can also be expressed as Κχ1 = φ1 (χ). The function φ(χ)μ1(χ) is mounted on the hard LUT (L〇〇k Up Table), but both become the same LUT. - Lookup table) 装装情情135786.doc 200937872 [Non-Patent Document 1] DVB-S.2 ·· ETSI ΕΝ 302 307 Vl.1.2 (2006-06) [Summary of the Invention] [Problems to be Solved by the Invention] LDPC The code is used in the DVB-S.2 specification for satellite digital broadcasting or the DVB-T.2 specification for terrestrial digital broadcasting of the next generation. Further, the LDPC code is intended to be used in the next-generation CATV (Cable Television) digital broadcasting specification DVB-C.2. ® is played in digital format according to DVB specifications such as DVB-S.2, and the LDPC code is used as a symbol of quadrature modulation (digital modulation) such as QPSK (Quadrature Phase Shift Keying). ), the symbol is mapped to a signal point and sent. In the symbolization of the LDPC code, the replacement of the code bits of the LDPC code is performed in units of code bits of 2 bits or more, and the replaced code bit is used as the bit of the symbol. The replacement of the code bits for the symbolization of the LDPC code has been proposed in various ways, but requires a new way of improving the tolerance of the proposal for errors. The present invention has been made in view of such a situation, and it is possible to improve the tolerance to errors in data such as LDPC codes. [Technical means for solving the problem] The data processing device or the data processing method according to an aspect of the present invention is an LDPC (Low Density Parity Check) of the N-bit length of the memory code in the course direction and the wale direction. The m-bit of the 135786.doc -12-200937872 LDPC code of the aforementioned 135786.doc -12-200937872 LDPC code written in the preceding direction of the memory unit of the code bit is used as the symbol And a specific positive integer " is also b, just s reminiscent of the system is in the above-mentioned horizontal direction memory mb bit, and in the narration direction memory N / (mb) bit; the aforementioned LDpc code of the code The element is written in the longitudinal direction of the memory mechanism, and then read in the direction of the row; and has a replacement mechanism or a replacement step, which is a code of mb bits read in the direction of the direction of the memory mechanism. In the case where the bit is used as the b preceding symbols, the code bits of the mb bit® are replaced according to the allocation rule for assigning the code bits of the LDPC code to the symbol bits of the preceding symbols. , after replacing the code bit as the preceding symbol bit The LDPC code is DVB-S.2 or DVB-T.2, and the code length N is 16200 bits, and the coding rate is 2/32 LDpc code; the m-bit is 1 〇 bit, and the aforementioned integer b is 2; one bit of the aforementioned code bit is mapped as one of the 24 signal points determined by 1024QAM as one of the preceding symbols; the memory mechanism contains 1 〇 x 2 bits in the horizontal direction. 2 纵 纵 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The bit i-th is calculated as the bit bi, and the symbol bits of the 10x2 bits of the consecutive two preceding symbols are set from the highest bit to the first +1 bit. The element yi may be replaced by the following allocation rules: assigning the bit bo to the bit ys, assigning the bit t > 2 to the bit yQ, and assigning the bit b4 to the bit y 1 'the bit W is allocated to bit y2, bit b8 is assigned to bit, bit b1G is assigned to bit y4, bit bl2 is assigned to bit y6, bit bM is assigned to bit ys 'bit bl6 Assigned to bit y9 Assigning bit b 1 s to bit y7 'Assign bit b! to bit y丨8, assigning bit b3 to 135786.doc -13- 200937872 to bit y 1G, assigning bit bs to Bit y] 丨, assign bit b7 to bit yi2 'Assign bit b9 to bit yn, bit bn to bit y14, bit bn to bit y10 'bit b15 Assigned to bit y15, bit 1^7 is assigned to bit yls' and bit b19 is assigned to bit yi7. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64,800 bits and a coding rate of 2/3; the m-bit is 10 bits, and The integer b is 2; the 10 bits of the code bit are mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism includes the 丨〇X2 bit in the horizontal direction. In the case where the 20 wales 'memorize 64800/(10x2) bits in the wale direction, the code bits of 1 〇x2 bits read in the course direction of the memory mechanism are counted from the highest bit The i+th bit is set to the bit bi, and the symbol bit of the 10x2 bit of the consecutive two preceding symbols is set from the highest bit to the i+1th bit as the bit yi ' The following replacement is performed according to the foregoing allocation rule: assigning bit bG to bit y8, assigning bit b>2 to bit yQ, assigning bit W to bit yi 'allocating bit b6 to bit Y2, the bit b8 is assigned to the bit, the bit b1G is assigned to the bit y4, the bit b is assigned to the bit y6, and the bit b is assigned to the bit y5, the bit b! 6 assigned to the bit Y9, assigning the bit bis to the bit y?, assigning the bit b! to the bit yi8, assigning the bit b>3 to the bit y1Q, and assigning the bit b5 to the bit yn, the bit... Assigned to bit y' assigns bit b > 9 to bit yi3, bit b! Assigned to the bit, the bit b!3 is assigned to the bit, the bit b15 is assigned to the bit yi5 'the bit b!7 is assigned to the bit y19, and the bit be is assigned to the bit yn 〇135786. Doc -14· 200937872 Further, the foregoing LDPC code is an LDPC code having a code length N of 16200 bits and a coding rate of 3/4 as defined by the specifications of DVB-S.2 or DVB-T.2; The element is 1 ' bit ' and the integer b is 2; 1 〇 bit of the aforementioned code bit is mapped as one of the aforementioned symbols to any one of 24 signal points determined by 1024Q AM; the foregoing memory The mechanism contains 20 wales of 1 〇 x 2 bits in the horizontal direction, and 162 〇〇 / (1 〇 x 2) bits in the longitudinal direction. 'Reading in the direction of the memory mechanism The code bit of the 1〇x2 bit is set from the highest bit to the i+th bit to be the bit bi, and the 2 consecutive symbols are 10><2-bit symbol bit is calculated from the highest bit and the i+1th bit is set to bit yi, and the following replacement can be performed according to the foregoing allocation rule: assigning bit bQ to bit y6, Bit b2 is assigned to bit y4, bit t>4 is assigned to bit y8 'bit is assigned to bit y5, bit bS is assigned to bit yt), bit b1Q is assigned to bit Y2, the bit b12 is assigned to the bit y!, the bit bi4 is assigned to the bit y3, the bit b16 is assigned to the bit y9 'the bit bis is assigned to the bit y7, and the bit bi is assigned to the bit Element y16, assigning bit h to bit y14, bit b5 to bit y18, bit 157 to bit ' assigning bit b9 to bit y1(), assigning bit bn to Bit y! 2, assigning bit bi 3 to bit y 丨丨, assigning bit b 丨 5 to bit 丫 13 ' assigning bit bi7 to bit y19, assigning bit b 9 Bit yi? ° Moreover, the aforementioned LDPC code is MPEG-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64800 bits, and the coding rate is 3/4 LDPC code; the m-bit is 10-bit, and the aforementioned integer b is 2; 10 bits of the aforementioned code bit are taken as 1 One of the 1024 signal points determined by 1024QAM is mapped to any one of 135786.doc -15-200937872; the memory mechanism contains 20 vertical lines of 1 〇 x 2 bits in the horizontal direction. In the case of the row direction memory 64800/(1 0x2) bit, the iQ position of the 10x2 bit code bit read from the course direction of the memory mechanism is set from the highest bit bit. Bit bj, and the symbol bits of 1 〇χ 2 bits of two consecutive symbols are counted from the highest bit and the +1 +1 bit is set to bit yi ' can be respectively performed according to the foregoing allocation rule Replacement: assign bit bG to bit, assign bit b2 to bit y4, assign bit W to bit ys, assign bit b0 to bit y5, and assign bit b8 © to bit Yuan y, assigning bit b1() to bit y2, bit b12 to bit y!, assigning bit bM to bit ys ' assign bit bl6 to bit Μ, bit Bls is assigned to bit y7, bit b! is assigned to bit yi6, bit t>3 is assigned to bit y 〖4', bit is assigned to bit y-8, bit b7 is assigned to bit Yuan yls 'Assign bit #>9 to bit y 1(), bit bn to bit y!2 'Assign bit b丨3 to bit y丨丨, assign bit b]5 to The bit yi3 assigns the bit b!7 to the bit y19 and the bit bi9 to the bit yn. Further, the LDPC code is defined by the specifications of DVB-S.2 or DVB-T.2. The code length N is 16200 bits, and the coding rate is 4/5 LDPC code; the m-bit is 10 bits, and the aforementioned integer b is 2; the position of the above-mentioned code bit is 1 as one of the aforementioned symbols Mapped to any of the 24 signal points determined by 1024QAM, the memory mechanism contains 20 vertical lines in the horizontal direction memory 丨〇x2 position, and 162〇〇/ρ〇χ2 in the longitudinal direction. In the case of a bit, the iQ2 bit of the code bit read in the direction of the memory mechanism is set to the bit ^ from the highest bit, and will be connected 135786.doc -16 - 200937872 Continued the symbol of the 1st and 2nd bits of the two preceding symbols, the i+1th bit from the highest bit is set to the bit yi ' can be carried out according to the above allocation rules Replacement as follows: assign bit bG Bit y6, bit b2 is assigned to bit y4, bit t>4 is assigned to bit ys, bit t>6 is assigned to bit ys, bit is assigned to bit y, bit is set The element b1G is assigned to the bit yz, the bit bl2 is assigned to the bit y ! , the bit b ! 4 is assigned to the bit y 3 , the bit b 6 is assigned to the bit , and the bit bls is assigned to the bit Element y7, bit b is assigned to bit y16, bit t>3 is assigned to bit y M ', bit b5 is assigned to bit yu, bit is assigned to bit, bit b9 is assigned Give the bit yi. , the bit bn is assigned to the bit yi2, the bit bn is assigned to the bit yu, the bit, 5 is assigned to the bit y 〗 3 'the bit bn is assigned to the bit y 〗 9, the bit bb The LDPC code assigned to the bit 丫17 ° and the aforementioned LDPC code system DVB-S.2 or DVB-T.2 has a code length N of 64,800 bits and a coding rate of 4/5; The bit element is 10 bits, and the integer b is 2; 1 〇 bit of the above code bit is mapped as one of the aforementioned symbols to any one of 24 signal points determined by 1024QAM; the foregoing memory The mechanism contains 20 wales that store 1 〇χ 2 bits in the horizontal direction, and 648 〇〇 / (1 〇χ 2) bits in the longitudinal direction, which will be read in the course direction of the memory mechanism. The code bit of the 1 〇χ 2 bit is set to the bit element... from the most significant bit, and the symbol bits of the 10x2 bits of the consecutive 2 narrations are from the highest bit. From the first calculation, the i+1th bit 7C is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: assigning the bit bG to the bit %, assigning the bit 匕 to the bit, and allocating the bit W Give bit h, place bit Assigned to bit y5, assigns bit 匕 135786.doc •17· 200937872 to bit yG, bit b q to bit y2, bit b! 2 to bit y 1, bit The element b!4 is assigned to the bit y3, the bit b16 is assigned to the bit y9', the bit b8 is assigned to the bit y7, the bit b! is assigned to the bit y16, and the bit b>3 is assigned The bit y is 4, the bit b5 is assigned to the bit y18, the bit 匕7 is assigned to the bit y丨5', the bit b9 is assigned to the bit y G, and the bit b 1 ! is assigned The bit yu 'is assigned the bit bn to the bit yn, the bit b15 to the bit yi3, the bit b1? to the bit y19', and the bit b19 to the bit yi7 0 © further, The foregoing LDPC code is a LDPC code with a code length N of 16200 bits and a coding rate of 5/6 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 10 bits, and the aforementioned integer b is 2; 1 前述 bit of the aforementioned code bit is mapped to one of 24 signal points determined by 1024QAM as one of the aforementioned symbols; the memory mechanism is stored in the horizontal direction memory 丨〇 x2 bit 20 vertical lines of the yuan' memory in the longitudinal direction 16200/(1 In the case of 0x2) bit, the i-th bit of the code bit of the 1〇X2 bit read out in the course direction of the memory mechanism is set to the bit bi from the highest bit, and The i-th bit of the first two symbols of the preceding symbol is calculated from the highest-order bit, and the i+1th bit is set to the bit yi ', and the following replacement may be performed according to the foregoing allocation rule: The element bG is assigned to the bit y0, the bit b2 is assigned to the bit y4, the bit b»4 is assigned to the bit ys, the bit b6 is assigned to the bit y5, and the bit be is assigned to the bit yG, Assigning bit b1Q to bit y2, assigning bit bl2 to bit yi 'place bit 1^4 to bit y3, bit b16 to bit y9, assign bit b!8 Bit y7 'is assigned bit b! to bit y16, bit h is assigned to bit, bit bs is assigned to bit yi8, bit 匕135786.doc -18- 200937872 is assigned to bit y 〖5, assign bit W to bit yiQ, bit bn to bit ylz, bit bu to bit yn, bit bl5 to bit 丫3, assign bit bw Give bit yis, assign bit bi9 to bit And the above-mentioned LDPC code is DVB-S.2 or DVB-T.2, the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64,800 bits, and the coding rate is 5/6 of the lDP code; the aforementioned bite is 10 bits. And the integer b is 2; the 1st bit of the code bit is mapped as one of the 1024 signal points determined by 1024QAM as one of the symbols; the memory mechanism is stored in the horizontal direction memory In the case where the tw〇χ2 bit 20 traverses memory 64800/(10x2) bits in the wale direction, the code bits of 1 〇X2 bits read from the course of the memory mechanism are The i+th bit is set to the bit bi from the highest bit, and the i+1th bit of the 10x2 bit of the consecutive two symbols is set from the highest bit. The bit yi ' can be replaced by the following allocation rules: assigning the bit b 给 to the bit ' assigning the bit t > 2 to the bit y4 and assigning the bit 1 > 4 to the bit ' Bit b6 is assigned to bit y5, bit is assigned to bit yG, bit b1G is assigned to bit, bit b12 is assigned to bit y!, bit bw is assigned to bit, bit is allocated B16 points The allocation bit y9' assigns the bit b!8 to the bit y*7, the bit b! to the bit y16, and the bit b>3 to the bit 'assign the bit b>5 to the bit Element y18, assigning bit b7 to bit yi5 'is assigning bit b? to bit y1(), assigning bit to bit y! 2, and assigning bit b 13 to bit y 11 ' The bit b is assigned to the bit y 13 ', the bit b! 7 is assigned to the bit y 19, and the bit b is 9 is assigned to the bit yi7 ° 135786.doc -19- 200937872 Further, the aforementioned LDPC The code length of the code system DVB-S.2 or DVB-T.2 is 16200 bits, and the coding rate is 8/92 LDpc code; the aforementioned m bit το is 10 bits, and the aforementioned integer 1) is 2 The first bit of the code bit is mapped to one of the 24 signal points determined by 1〇24QAM as one of the symbols, and the memory mechanism includes 1〇χ2 bits in the horizontal direction. 20 vertical lines, remembering 162〇〇/(1〇> in the longitudinal direction <2) In the case of a bit, the code bit of the 丨〇χ2 bit read out in the course direction of the memory mechanism is set from the highest bit to the i-th bit as the bit bi And, for example, the symbol of the 10x2 bit of the symbol of the second symbol is incremented from the highest bit and the i+1th bit is set to the bit yi ', and the following replacement may be performed according to the foregoing allocation rule: The bit bG is assigned to the bit y8, the bit b2 is assigned to the bit y0, and the bit b4 is assigned to the bit y! 'The bit b6 is assigned to the bit y2, and the bit b8 is assigned to the bit y3 The bit b1G is allocated to the bit y4, the bit b12 is assigned to the bit y6, the bit b14 is assigned to the bit y5, the bit b16 is assigned to the bit y9, and the bit b18 is assigned to the bit y7 , assigning bit b! to bit y18, assigning bit b3 to bit y 1(), assigning bit b5 to bit yn, and assigning bit b7 ❹ to bit y 12 to place the bit Assigned to bit y 13, assign bit bi! to bit y14, bit bi3 to bit yi6, bit bi5 to bit y 1 5 ' assign bit b 1 7 to bit y 1 9 'Assign bit b 1 9 to bit yu Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64,800 bits and an encoding rate of 8/9; the m-bit is 10 bits, and The integer b is 2; the 10 bits of the m-bit are mapped as one of the aforementioned symbols to any of 1024786.doc • 20· 200937872 of 1024 signal points determined by 1024QAM; the memory mechanism is included in the course The direction memory is 20 twentieth of 1 〇χ 2 bits, and in the case of memory 64800/g 〇χ 2) bits in the longitudinal direction, the code of 1 〇χ 2 bits read in the direction of the memory mechanism is read. The i+1th bit from the highest bit is set to the bit bi, and the iq bit of the 10x2 bit of the preceding two symbols is counted from the highest bit. The element is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit ys, the bit h is allocated to the bit, and the bit b4 is assigned to the bit yi, and the bit is allocated Assigning to the bit element, assigning the bit h 〇 to the bit element, assigning the bit No to the bit w, assigning the bit bl2 to the bit 兀ye, and assigning the bit b!4 to the bit ys Assigning bit b16 to bit y9, bit b1S to bit y7, bit bl to bit yi8, bit b3 to bit yiG, bit bs to bit 1. Assign bit b7 to bit yi2 'Assign bit b to bit yn, assign bit b" to bit yu' to assign bit bu to bit yi6 and bit b15 to bit Yuan yis 'Assign bit b1? to bit, and bit b19 to bit yi7〇Θ Further, the aforementioned LDPC code is the code length specified by the specification of DVB-S.2 or DVB-T.2 N is 64800 bits, and the coding rate is 9/10 LDPC code; the m-bit is 1 〇 bit ' and the aforementioned integer b is 2; 1 前述 bit of the above-mentioned code bit is mapped as one of the aforementioned symbols Any one of the 1024 signal points determined by 1〇24QAM; the memory mechanism contains 20 vertical lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction. 'The code bits of the 10 χ 2 bits read out from the direction of the memory mechanism are set to the bit bi from the highest bit, and 135786.doc • 21· 200937872 will be connected The symbol of the 10x2 bit of the two symbols is set from the highest bit and the i+th bit is set to the bit yi. The following replacement can be performed according to the foregoing allocation rule: assigning the bit bG to Bit y8, assigning bit b2 to bit y, assigning bit b>4 to bit y!, assigning bit b6 to bit y2, and assigning bit b8 to bit y3, bit The element b! is assigned to the bit y4, the bit bj 2 is assigned to the bit y0, the bit b 14 is assigned to the bit y 5 , and the bit b ! 6 is assigned to the bit ' assigning the bit b18 to Bit y7, assigning bit b! to bit y 18 ' assigns bit b3 to bit y 〇, assigns bit b5 to bit yn, © assigns bit t > 7 to bit y 12 'Assign bit b9 to bit y〗 3, assign bit bii to bit, assign bit b13 to bit y16, and bit b15 to bit y! 5 'put bit b丨7 is assigned to bit y丨9, and bit b! 9 is assigned to bit yi7. Moreover, the aforementioned LDPC code is a LDPC code having a code length N of 16200 bits and a coding rate of 2/3 as defined by the specifications of DVB-S.2 or DVB-T.2; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the preceding symbols; the memory mechanism includes 12X2 bits in the horizontal direction. In the case where 24 wales 'memorize 162 〇〇/(12 χ 2) bits in the wale direction, 12 will be read in the course direction of the memory mechanism described above><2-bit code bit The i+th bit is set to bit bi from the most significant bit, and 12 of the preceding symbols will be consecutive><2 bit symbolic element The i+1th bit is set to bit yi from the highest bit, and the following replacement can be performed according to the foregoing allocation rule: assigning bit bQ to bit y1 ( ), assigning the bit || to the bit yQ, assigning the bit b4 to the bit yi, assigning the bit to the bit, and assigning the bit 58 135786.doc •22-200937872 to the bit y3 ' Bits b1() are assigned to bit y4, bit b12 is assigned to bit y5', bit b14 is assigned to bit y6, bit b16 is assigned to bit y8', bit b 18 is assigned to bit Element y7, assigning bit b2G to bit y丨j, assigning bit b22 to bit y9, assigning bit b! to bit y22, and assigning bit b3 to bit y 12 'put bit B5 is assigned to bit y13, bit b7 is assigned to bit yi4, bit b9 is assigned to bit y15, bit bn is assigned to bit y16, bit b13 is assigned to bit y17, bit is allocated B15 is assigned to bit y18, bit b17 is assigned to bit y2G, bit b19 is assigned to bit y19, bit b21 is assigned to bit y23, and bit b23 is assigned to bit y21. Further, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64800 bits and a coding rate of 2/3; the m-bit is 12 bits. And the integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism is stored in the horizontal direction memory 丨 2X2 bit In the case of 24 vertical lines of the element, in the case of memory 64800/(12x2) bits in the longitudinal direction, the 12x2 bit code bits read in the course direction of the memory mechanism are counted from the highest bit. The i+1th bit is set to the bit bj, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the highest bit to the i+1th bit as the bit yi, which can be The foregoing allocation rules respectively perform the following substitutions: assigning the bit bQ to the bit y1Q, assigning the bit 匕 to the bit y〇, assigning the bit % to the bit yi, and assigning the bit b6 to the bit y2, Assigning a bit to bit ys ' allocates bit b1Q to bit y4, bit bl2 to bit ys, bit bw to bit y6, and bit bl6 to bit Ys, assigning the bit bls to the bit y?, assigning the bit b2Q to the bit yn, 135786.doc -23· 200937872 assigning the bit bn to the bit 'allocating the bit b to the bit y22, The bit h is assigned to the bit yu, the bit bs is assigned to the bit yu, the bit b is assigned to the bit y! 4 'the bit b9 is assigned to the bit y〗 5 'Bit b! Assigned to bit y 1 6 'distribute bit b ! 3 to bit y 丨 7 , assign bit b ! 5 to bit y s ' to assign bit bn to bit y2G, bit bl9 Assigned to bit yi9, bit b>2丨 is assigned to bit y23, and bit b23 is assigned to bit y2 1. Moreover, 'the foregoing LDPC code is DVB-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 16200 bits, and the coding rate is 3/4 LDPC code; the m-bit is 12 bits' and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism is stored in the course direction 丨2><24 twentieth of 2 bits' memory 162 〇〇/(i2x2) bits in the wale direction, the 12x2 bit code bits read from the course direction of the memory mechanism are The i+th bit is set to the bit bi from the highest bit, and the i+1th bit of the 12x2 bit of the preceding two symbols is set from the highest bit. The bit yi may be replaced by the following allocation rules: assigning the bit bo to the bit y8, assigning the bit b2 to the bit yG, and assigning the bit t»4 to the bit y6 'the bit B6 is assigned to bit yi, bit b8 is assigned to bit y4, bit b1Q is assigned to bit y5, bit b12 is assigned to bit, bit b14 is assigned to bit y3, bit b16 is assigned Assigned to bit y7, bit unit bu is assigned to bit y1(), bit b2G is assigned to bit yu, bit 1>22 is assigned to bit y 9, bit b! is assigned to bit y 2Q, assigning bit b3 to bit y12 'Assign bit fc>5 to bit y18, bit b7 to bit y 13 'Assign bit b9 to bit y 16, bit bit b!! Assigned to 135786.doc •24- 20093787 2 element yn ' assigns bit bn to bit yu, bit bi5 to bit yi5 ' assigns bit bp to bit y!9, bit bi9 to bit y22, assigns bit The bit number is 3, and the bit b23 is assigned to the bit. "Furthermore, the code length N specified by the specifications of the aforementioned LDPC DVB-S.2 or DVB-T.2 is 64,800 bits, and the code is The rate is 3/4 iLDpc code; the m-bit is 12-bit ' and the aforementioned integer b is 2; 12 bits of the above-mentioned code bit are mapped as one of the aforementioned symbols to 4096 signal points determined by 4〇96QAM Any one of the above; the memory mechanism contains 24 wales of memory 12 χ 2 β bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction, which will be in the direction of the memory mechanism The code bit of the read 2 χ 2 bit is set from the highest bit to the i + Ι bit as the bit bi, and the symbol bits of the 12x2 bits of the 2 consecutive symbols are from the highest bit. The i+1th bit from the bit count is set to the bit yi, and the following replacement may be performed according to the foregoing allocation rule: the bit b〇 is allocated to the bit y8, and the bit b2 is assigned to the bit y〇. The bit t>4 is assigned to the bit y6, the bit b6 is assigned to the bit y, the bit ©bS is assigned to the bit y4', the bit b1G is assigned to the bit y5, and the bit b12 is assigned Bit y2' assigns bit b14 to bit y3, bit b16 to bit 丫7, bit b18 to bit y1(), bit b2G to bit, bit b22 Assigned to bit y9, bit b! is assigned to bit y2G, bit is assigned to bit y12, bit b5 is assigned to bit y18, bit b7 is assigned to bit y 1 3, bit is set Element b9 is assigned to bit y! 6, assigning bit b!! to bit y17, bit b13 to bit y14, bit b15 to bit yi5, bit b17 to bit Yi9, the bit bi9 is assigned to the bit y22, the bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y21 β 135786.doc -25- 200937872 Moreover, the aforementioned LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 16200 bits, and the coding rate is 4/52 LDpc code; the aforementioned melon position 兀* is 12 bits, and the aforementioned integer bg2; 12 bits of the aforementioned code bit element Determined as a symmetry symbol and mapped to 4096QAM 4096 signal points according to any one of; the memory means comprising memory 12χ2 bits in the course direction of the wales 24, in the longitudinal direction of the memory 162〇〇 / (12 ><2) In the case of a bit element, the code bit of the 丨2χ2 bit read out in the course direction of the memory mechanism is set to the bit bi from the highest bit bit, And the second i-th symbol of the 12x2 bit of the preceding symbol is calculated from the highest-order bit, and the i+1th bit is set as the bit yi, and the following replacement may be performed according to the foregoing allocation rule. Yuan, b〇 is assigned to bit ys 'Band bit b2 is assigned to bit, bit b»4 is assigned to bit y0, bit b6 is assigned to bit y, bit b8 is assigned to bit Y4 'Assign bit b1G to bit y5, bit b12 to bit y2' assign bit b 4 to bit y3, bit b16 to bit y7, assign bit b18 to The bit y1() assigns the bit b2Q to the bit yn, assigns the bit b>22 to the bit y9', assigns the bit b! to the bit y2Q, and assigns the bit b3 to the bit y 12 , assigning bit b5 to bit y 〗 8, assigning bit b7 to bit y 13 ' assigning bit b9 to bit y 16, assigning bit b 1 to bit y17, bit Bi3 is assigned to bit y14, and bit bi5 is assigned to bit y! 5. The bit b i 7 is assigned to the bit y 〗 9, the bit b! 9 is assigned to the bit y22, the bit b2 丨 is assigned to the bit y23, and the bit b23 is assigned to the bit y21. Further, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 64800 bits and a coding rate of 4/5; the m-bit is 12 bits. And the aforementioned integer b is 2; 12 bits of the aforementioned code bit 135786.doc • 26-200937872 are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 409 6Q AM; the foregoing memory mechanism 24 wales containing 12 χ 2 bits in the horizontal direction memory 648 〇〇 / (12 χ 2) bits in the wale direction 丨 2 χ 2 bits read in the course direction of the memory mechanism The code bit is set to the bit bi from the highest bit, and the symbol bits of the 12x2 bits of the two consecutive symbols are counted from the highest bit. The bit is set to the bit yi ', and the following replacement can be performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, the bit b2 is assigned to the bit y, and the bit b4 is assigned to the bit y0. The bit b6 is assigned to the bit yi, the bit 1 > 8 is assigned to the bit y4 'the bit b1G is assigned to the bit y5, and the bit b12 is assigned to the bit y2, the bit b] 4 is assigned to bit y3, bit b16 is assigned to bit y*7 'bit element bu is assigned to bit y1(), bit b2G is assigned to bit yu, bit b is assigned to bit ' Assigning the bit ratio to bit y2(), assigning bit b3 to bit y, 2' assigning bit bs to bit y18, and assigning bit 1^7 to bit y!3, bit b>9 is assigned to bit y 16, and bit b!! is assigned to bit y 〖7', bit bn is assigned to bit y14, bit b15 is assigned to bit yis, bit bn is assigned to The bit y is 9, the bit b19 is assigned to the bit y22, the bit b2 ! is assigned to the bit y23 'the bit b23 is assigned to the bit y2 J. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16200 bits and a coding rate of 5/6; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 bits of memory 12x2 bits in the horizontal direction. In the case of a vertical line, in the case of a memory of 16200/(12x2) bits in the wale direction, I35786.doc -27· 200937872 will read the 12x2 bit code bit from the highest position in the direction of the memory mechanism. The bit i + Ι bit is set to bit bj, and 12 consecutive symbols of the preceding symbol will be 12><2 bit symbolic element The i+1th bit is set as the bit yi from the highest bit, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, The bit 52 is assigned to the bit), the bit b4 is assigned to the bit y6, the bit b6 is assigned to the bit y 1, the bit b8 is assigned to the bit y4, and the bit b1G is assigned to the bit Y5, the bit b12 is allocated to the bit y2, the bit b14 is assigned to the bit y3, the bit b16 is assigned to the bit O y7, and the bit b 18 is assigned to the bit y 1 〇, the bit b2 〇 is allocated to bit yn, bit b22 is assigned to bit y9, bit b 1 is assigned to bit y2G, bit b>3 is assigned to bit y12, and bit b5 is assigned to bit y18, Bit b7 is assigned to bit yn, bit b9 is assigned to bit y16, bit bn is assigned to bit yi7', bit b13 is assigned to bit y14, bit b15 is assigned to bit yi5' The bit b17 is assigned to the bit y19, the bit b19 is assigned to the bit y22, the bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y2j. Further, 'the aforementioned LDPC code is DVB-S.2 or DVB-T.2, and the code length N is 64 800 bits, and the coding rate is 5/6 LDPC code; the aforementioned m bit is 12 a bit, and the integer b is 2; 12 bits of the code bit are mapped as one of the 4096 signal points determined by 4096Q AM as one of the symbols; the memory mechanism is stored in the horizontal direction memory In the case where the 24 wales of 丨2χ2 bits are memory 64800/(12x2) bits in the wale direction, the 12-bit 2-bit code bits read from the course of the memory mechanism are from the highest bit. From the first calculation, the i+Ι bit is set to the bit 匕, and the symbol bits of the 12 χ 2 bits of the preceding two symbols are counted from the highest bit. 135786.doc -28- 200937872 1+1 The bit is set to the bit yi, and the following replacement can be performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, the bit b2 is assigned to the bit y0, and the bit t > 4 is assigned to the bit y6 Assigning bit b6 to bit y, assigning bit t > 8 to bit 'allocating bit b 〇 to bit y5, assigning bit b12 to bit y2, allocating bit b14 To the bit y3, the bit b16 is assigned to the bit y*7', the bit b18 is assigned to the bit y1G, the bit b2G is assigned to the bit yn, and the bit b22 is assigned to the bit y9, the bit is allocated b丨 is assigned to bit y2Q, bit 1>3 is assigned to bit ylz, bit b5 is assigned to bit y18, bit !^ is assigned to bit y! 3 'bit b9 is assigned to bit Yuan yi 6, will be bit b! Assigned to bit yi? 'Assign bit b13 to bit y14, bit b15 to bit y〗 5, bit b17 to bit y19, bit b19 to bit y22, Bit b21 is assigned to bit y23, and bit b23 is assigned to bit y21. Moreover, the foregoing LDPC code is a LDPC code having a code length N defined by a specification of DVB-S.2 or DVB-T.2 of 16200 bits and an encoding rate of 8/9; the m-bit is 12 bits, and The integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 bits of memory 12X2 bits in the horizontal direction. In the case where the traverse 'memorizes 16200/(12x2) bits in the wale direction, the 12-bit 2-bit code bits read in the course direction of the memory mechanism are counted from the highest bit i+ The Ι bit is set to the bit bi, and the symbol bits of the 12x2 bits of the consecutive two preceding symbols are set from the highest bit to the i+1th bit as the bit yi 'can be according to the foregoing allocation rule The following replacement is performed: assigning bit bG to bit y丨Q, assigning bit b2 to bit, assigning bit t>4 to bit y!, and assigning bit b6 to bit y2, Assigning bit b8 135786.doc -29- 200937872 to bit y3 'Assign bit bi〇 to bit y4, bit b12 to bit y5, bit b14 to bit y6, will The element b16 is assigned to the bit y8, the bit b18 is assigned to the bit y7 'the bit b2G is assigned to the bit yi j , the bit bn is assigned to the bit y9 , and the bit bi is assigned to the bit y22 , Bit b3 is assigned to bit y 〗 2 'Band bit b5 is assigned to bit y 〗 3, bit b7 is assigned to bit yi4, bit b9 is assigned to bit y15, bit bn is assigned to bit Yuan 丫 16, assigning bit b13 to bit y17, bit b15 to bit yis, bit b17 to bit y2 〇, bit b19 to bit y19, 位 bit b2 Assigned to bit y23, bit b23 is assigned to bit y2 J » Further, the code length N specified by the specification of LDPC code system DVB-S.2 or DVB-T.2 is 64800 bits, An LDPC code having a coding rate of 8/9; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096 Q AM as one of the aforementioned symbols. Any of the six signal points; the memory mechanism contains 24 wales of 2x2 bits in the horizontal direction memory, and 64800/(12x2) bits in the longitudinal direction, which will be in the memory mechanism Horizontal side The read 12 bits of 12 X 2 bits are set from the most significant bit to the i-th bit, and the symbol bits of the 12x2 bits of the preceding two consecutive symbols are The 1+1th bit from the highest bit is set to the bit yi ', and the following replacement can be performed according to the foregoing allocation rule. The bit bG is assigned to the bit y丨Q, and the bit b2 is assigned to the bit y. 〇, assigning bit 1 > 4 to bit y 1 'allocating bit b6 to bit y 2 , assigning bit I 8 to bit ' assigning bit blG to bit y4, bit Bl2 is assigned to bit ys, bit b14 is assigned to bit y6, bit b16 is assigned to bit ys 'bit bit b! 8 is assigned to bit y7' and bit b2Q is assigned to bit yn, 135786 .doc -30- 200937872 assigns bit t»22 to bit y9, bit b! to bit y22, bit 1>3 to bit y 1 2 ' assign bit b5 to bit Yuan yn, assigning bit b7 to bit yi4, bit b9 to bit y15, bit b!丨 to bit yi6, bit b13 to bit yn, bit b15 Give bit yis, assign bit b17 to bit y2〇, Assigned to the bits b19 membered y19, the bit b2 i assigned to the bit y23 'y2 bits allocated to bit b23 ,. Moreover, 'the aforementioned LDPC code is DVB-S.2 or DVB-T.2, and the code length N specified by the specification of DVB-S.2 or DVB-T.2 is 64,800 bits, and the coding rate is 9/10. The m-bit element is 12 bits. And the integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 12χ2 bits in the horizontal direction. In the case of 24 wales 'memory 64800/(12x2) bits in the wale direction, the 12 X 2 bit code bits read in the course direction of the memory mechanism are counted from the most significant bits. The i+th bit is set to the bit bj, and the symbol of the 12x2 bit of the consecutive two symbols is set from the highest bit to the i+i bit as the bit yi ' According to the foregoing allocation rule, the following replacement is respectively performed: assigning the bit bG to the bit y, ❶, assigning the bit b2 to the bit yG, assigning the bit t > 4 to the bit y], and allocating the bit b6 To the bit y2, the bit b8 is assigned to the bit y3 'the bit b! 〇 is assigned to the bit y4, the bit b 12 is assigned to the bit ys 'the bit b14 is assigned to the bit y6, the bit is bit Yuan b16 allocation To bit ys, bit b18 is assigned to bit y7, bit b2G is assigned to bit yu, bit bn is assigned to bit y9, bit b is assigned to bit y22, bit 1&gt 3 is assigned to bit y!2, bit b5 is assigned to bit y i3, bit b7 is assigned to bit, bit b9 is assigned to bit y15, bit b! 1 is assigned to bit 135786 .doc 31 200937872 yuan y〗 6, assigning the bit bls to the bit yn, assigning the bit bi5 to the bit yi8, assigning the bit b17 to the bit y2Q, and assigning the bit h to the bit ^, will be bit The element bZ1 is assigned to the bit force 3, and the bit is assigned to the bit force 1. In one aspect of the present invention, a code bit of an LDpc (L〇w Density Parity Check) code having a code length of N bits is written in the foregoing longitudinal direction of the memory mechanism, and thereafter Read in the horizontal direction, the code bits of the X-ray bits read in the direction of the memory of the memory mechanism are referred to as b symbols. At that time, the code bits of the aforementioned mb bits are replaced by the above-mentioned β, and the replaced code bits are used as the aforementioned symbol bits. Further, the data processing device may be an independent device or an internal block constituting one device. [Embodiment] [Effects of the Invention] According to the present invention, tolerance to errors can be improved. Fig. 7 is a view showing an example of a configuration of an embodiment in which the transmission system to which the present invention is applied (the system refers to a plurality of devices _ logically aggregated, regardless of whether or not the devices of the respective structures are in the same casing). In Fig. 7, the transmission system is constituted by a transmitting device 接收 and a receiving device 12. The transmitting device 11 performs, for example, transmission (playback) (transmission) of a television broadcast program. That is, the transmitting device 11 is, for example, an image data to be transmitted as an image data or a voice material of a television broadcast program, and is encoded as LDPC. The code is transmitted via a communication channel i 3 such as a satellite line or a ground wave, a CATV network, or the like. 135786.doc • 32- 200937872 The receiving device 12 is, for example, a pacer or a television receiver that receives a television broadcast program, an STB (Set Top Box), and receives an LDPC transmitted from the transmitting device 11 via the communication channel 13. The code is decoded into the object data and output. Here, the LDPC code used in the transmission system of Fig. 7 is known to have an extremely high capability in the AWGN (Additive White Gaussian Noise) communication channel. However, in the communication channel 13 of the ground wave or the like, a burst error ❹ or erasure may occur. For example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, D/U (Desired to Undesired Ratio) is OdB (not required = echo power and required = main path) In a multipath environment with equal power, there is a delay based on the echo (path outside the main path), and the power of the specific symbol becomes 0 (erase). Moreover, even if it is a flutter (a delay is 0 and a channel with an echo of the Dopper frequency is added), in the case where D/U is OdB, W is specific to the frequency of the Doppler. The power of the entire OFDM symbol at the time is 0 (erased). Further, since the receiving device 12 side receives the wiring condition of the receiving unit (not shown) such as an antenna from the transmitting device 11 to the receiving device 12 or the power supply of the receiving device 12, the cluster may also occur. Make a mistake. On the other hand, in the decoding of the LDPC code, the row of the check matrix ,, even the variable node corresponding to the code bit of the LDPC code, is performed as shown in the above-mentioned FIG. 5 135786.doc -33- 200937872 There is a variable node of the formula (1) of the LDPC code (the received value u〇i) is added to the p-point operation, so if the position of the variable node is used, the error occurs. 'The accuracy of the information obtained is reduced. After the decoding of the LDPC code, the check node performs the check node operation by using the message obtained by the variable node connected to the check node, so the right-connected complex variable node (The corresponding LdPc quark bit) The number of check nodes that become an error (including erasure) increases, and the performance of decoding deteriorates. That is, for example, if the check node is connected to the variable node of the check node and two or more of the variable nodes become erased, the probability that the probability of returning the value 所有 to all the variable nodes and the probability of 1 is equal probability. In this case, the check node of the message that sends back the equal probability does not contribute to the decoding process (the variable node operation and the check node operation of the 1 set). As a result, the number of repetitions of the decoding process is required, and the decoding is performed. Performance degradation 'further, 1^)1} (: the power consumption of the receiving device 12 of the decoding of the code is increased. Therefore, in the transmission system of FIG. 7, the performance of the AWGN communication channel is to be maintained] Fig. 8 is a diagram showing an example of the configuration of the transmitting apparatus 11 of Fig. 7. Fig. 8 'The transmitting apparatus 11 is composed of an LDPC encoding unit 21, a bit interleaver 22, a mapping unit 26, and orthogonal The LDPC encoding unit 21 supplies the target data to the LDPC coder 21. The LDPC encoding unit 21 forms a step structure for the target data supplied to the LDPC code, that is, the parity matrix corresponding to the LDPC code. The check matrix performs LDPC encoding 'outputs the object data as the LDPC code of the information 135786.doc -34- 200937872 bit. That is, the LDPC encoding section 21 performs encoding of the object data into, for example, DVB-S.2 or DVB-T. LDPC as specified in .2 specifications The LDPC code of the code outputs the LDPC code obtained by the result. Here, the specification of DVB-T.2 is intended to adopt the LDPC code specified by the specification of DVB-S.2. The specification of DVB-S.2 is specified. The LDPC code is an IRA (Irregular Repeat Accumulate) code, and the parity matrix of the check matrix of the LDPC code is a ladder structure. The same G-bit matrix and the ladder structure will be described later. For example, "Irregular Repeat_Accumulate Codes, "H. Jin, A. Khandekar, and RJ McEliece, in

Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 1-8, Sept. 2000 The LDPC code output from the LDPC encoding unit 21 is supplied to the bit interleaver 22. The bit interleaver 22 interleaves the data. The data processing device is composed of a parity interleaver 23, a column twist interleaver 24, and a demultiplexer (DEMUX) 25. The parity interleaver 23 performs co-located interleaving, interleaving the parity bits of the LDPC code from the LDPC encoding section 21 to the positions of other parity bits, and supplies the parity interleaved LDPC code to the vertical twist interleaver 24. The whirling twist interleaver 24 performs wobble interleaving for the LDPC code from the co-located interleaver 23, and supplies the LDPC code which is twisted and interleaved to the multiplexer 25 from 135786.doc -35 - 200937872. In other words, the LDPC code is mapped to the mapping unit 26, which will be described later, and the code bits of two or more bits of the LDPC code are mapped to signal points representing one symbol of the quadrature modulation and transmitted. The vertical twist interleaver 24' is not included in one symbol 'as a rearrangement from the same position in order to make the complex digital bit of the ldpc code corresponding to one of the ones of the check matrix used by the ldpC encoding unit 21 The rearrangement processing of the code bits of the LDPC code of the interleaver 23 is performed, for example, by the wobble interleave described later. © The multiplexer 25 is a replacement process for replacing the position of the code bit of 2 or more LDPC codes of the symbol with respect to the LDPC code from the vertical twist interleaver 24, thereby obtaining the enhanced financial benefit for AWGN. Sexual LDPC code. Then, the demultiplexer 25 supplies the code bits of 2 or more of the ldpc code obtained by the replacement processing to the mapping unit 26 as symbols. The mapping unit 26 maps the symbols from the demultiplexer 25 to the respective signal points determined by the modulation method of the quadrature modulation (multi-value modulation) by the orthogonal modulation unit 27. That is, the mapping unit 26 maps the LDPC code from the demultiplexer 25 into an IQ plane defined by the I axis representing the I component in phase with the carrier and the Q axis representing the Q component orthogonal to the carrier. The signal point determined by modulation in the (IQ constellation). Here, as a modulation method of the quadrature modulation performed by the quadrature modulation unit 27, for example, a modulation method including a modulation method defined by the specification of DVB-T, that is, QPSK (Quadrature Phase Shift Keying), for example, QPSK (Quadrature Phase Shift Keying) : Quadrature phase key shift) or 16QAM (Quadrature Amplitude Modulation: positive 135786.doc • 36-200937872 cross-amplitude modulation), 64QAM, 256QAM, 1024QAM, 4096QAM, etc. The quadrature modulation unit 27 preliminarily sets the orthogonal modulation by a certain modulation method in accordance with, for example, the operation of the operator of the transmission device 11. Further, in the quadrature modulation unit 27, for example, 4PAM (Pulse Amplitude Modulation) and other orthogonal modulation can be performed. The symbol mapped to the signal point by the mapping unit 26 is supplied to the orthogonal modulation unit 27°. The orthogonal modulation unit 27 performs carrier wave in accordance with the signal point (the symbol mapped to the © signal point) from the mapping unit 26 The quadrature modulation is performed, and the modulated signal obtained as a result is transmitted via the communication channel 13 (FIG. 7). Next, Fig. 9 shows an inspection matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of Fig. 8. The check matrix Η is an LDGM (Low-Density Generation Matrix) structure, which can be obtained by the information matrix Ha corresponding to the information bit in the code bit of the LDPC code, and the parity matrix corresponding to the parity bit. Ητ is expressed as the formula H=[HA|HT] (the elements of the information matrix HA are set to the left side element, and the elements of the parity matrix Ητ are set to the matrix of the right element). Here, the number of bits of information bits and the number of bits of the parity bits in the code bits of one LDPC code (1 code word) are respectively referred to as information length K and parity length, and one LDPC code. The number of bits of the code bit is called the code length Ν (=Κ+Μ). The information length and the same length of the LDPC code of a certain code length are determined by the coding rate. Moreover, check the matrix of the matrix Η series X behavior. Then, the information matrix HA is a matrix of ΜχΚ, and the parity matrix Ητ is a matrix of ΜχΜ. 135786.doc •31· 200937872

Figure 10 is a diagram showing the parity matrix Ητ of the check matrix LDP of the LDPC code specified by the specifications of DVB-S.2 (and DVB-T.2). The parity matrix of the inspection matrix LDP of the LDPC code defined by the specification of DVB-S.2 is as shown in Fig. 10, and the elements which become 1 are arranged in a so-called stepped structure. The column weight of the co-located matrix Ητ is 1 for the first column and 2 for the remaining columns. Moreover, the weight of the row is 1 for the last row and 2 for all remaining behaviors. The LDPC code © which the above-mentioned parity matrix Ητ is a ladder structure check matrix η can be easily generated by using the check matrix Η. That is, the LDPC code (1 code word) is represented by the column vector c, and the row vector obtained by transposing the column vector is represented as CT. Moreover, the portion of the information bit in the column vector c of the LDPC code is represented by the column vector ,, and the portion of the parity bit is represented by the column vector τ. In this case, the column vector c can be used as a column of information bits.

The quantity A and the column vector 同 as a parity bit are expressed by the equation c==[A|T] (the element of the column vector A is set to the left element ‘the column vector T is set to the right element column vector). Check matrix Η and column vector C=[A|T] as LDPC code must conform to ΤΓ

Hc_〇' as the column vector τ constituting the parity bit of the column vector C=[A|T] satisfying the formula HcT=0 can be obtained by the parity matrix ht of the check matrix H=[HA|HT] In the case of the step structure shown in the figure, the elements of the first column of the row vector HC of the equation HcT=0 are sequentially obtained by sequentially making the elements of the respective columns 〇.

Figure 11 shows the check matrix and row weights of the LDPC 135786.doc -38- 200937872 code specified by the specifications of DVB-S.2 (and DVB-T.2). That is, Fig. 11 is a check matrix LDP of the LDPC code defined by the specifications of DVB-S.2. Separately, regarding the check matrix Η from the first row, the row weight is X, and for the next 行3 rows, the row weight is 3, and for the subsequent Μ-1 row, the row weight is 2, about the last 1 Line, the row weight is 1. Here, ΚΧ+Κ3+Μ-1 + 1 is equal to the code length Ν. For the specifications of DVB-S.2, the number of lines ΚΧ, Κ3 and Μ (colocated length), and the line weight X X are defined as shown in Figure 11Β. That is, Fig. 11 is a line number ΚΧ, Κ3 and Μ, and a row weight X of each coding rate of the LDPC code defined by the specification of DVB-S.2. In the specification of DVB-S.2, there are LDPC codes with a length of 64,800 bits and 16,200 bits. Then, as shown in FIG. 11A, regarding the LDPC code having a code length Ν of 64,800 bits, 11 coding rates (nominal rate) of 1/4, 1/3, 2/5, 1/2 are specified. 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, for an LDPC code with a code length N of 16,200 bits, 10 encoding rates of 1/4 are specified. 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6 and 8/9. Regarding the LDPC code, it is known that the code bit corresponding to the row having the larger row weight of the check matrix has a lower error rate. The inspection matrix 规定 specified in the specification of DVB-S.2 shown in FIG. 11 has a larger row weighting tendency as the row on the head side (left side), and therefore, regarding the LDPC code corresponding to the inspection matrix ,, The more the code bit at the beginning, the stronger the error (tolerance to the error), the more the last bit of the code bit, the more vulnerable the error is 135786.doc -39- 200937872. Next, Fig. 12 shows an arrangement on the plane of 16 symbols (corresponding signal points) in the case of 16QAM2 by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 12A shows the symbol of 16QAM. In 16QAM, 1 symbol represents 4 bits, and there are 16 (= 24) symbols. Then, the 16 symbols are arranged around the origin of the IQ plane and in a square shape of 4x4 in the direction of the j direction. Now, if the bit string represented by 1 symbol is counted from the highest bit bit © the bit of the 1+1th bit is represented as the bit yi, the 4 bit represented by the 1 symbol of 16QAM The highest bit can be expressed as bit eight, force, yes, ^. In the case where the modulation method is 16QAM, the 4-bit code bit of the LDPC code is used as the symbol (symbol value) of the 4-bit yQ to y3. Fig. 12B shows the bit boundary of the 4-bit (hereinafter also referred to as symbol bit) yG to y3 indicated by the symbol of m16QAM, respectively. Here, the bit boundary @ of the symbol element yi (in Figure 12 is 丨 = 〇, 1, 2, 3) means that the symbol yi becomes the symbol of 〇 and the boundary of the symbol of 1 . As shown in FIG. 12B, with respect to the highest-order symbol bit yQ of the four-character bit eight to ys represented by the symbol of 16QAM, only the i-axis of the Q-axis of the plane becomes the bit boundary, regarding the second The symbol element yi (the second from the highest bit) is only the bit boundary of the i-axis of the IQ plane. Further, regarding the third symbol bit y2, two of the 4x4 symbols from the left to the first row and the second row, and two of the third row and the fourth row become the bit boundary. Further, s 'About the fourth symbol element y3, 4x4 symbols, from the above, between the first column and the second column, and between the third column and the fourth column become the bit 135786.doc 200937872 Yuanjie line. The symbol of the symbol is not in the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ High probability). Now, if the bit that is not easy to make mistakes (for the wrong strength) is called "strong position" and the position of the valley error (for the wrong position) is called "weak position": then the symbol of 16QAM The 4 symbol bits ^. At the highest level, the highest position is 7〇 y 〇 and the 2nd slave is - ❹

The 7L bit TLyi becomes a strong bit, and the 3rd symbol bit h and the 4th symbol bit become weak bits. Figs. 13 to 15 show the arrangement on the IQ plane of 64 symbols (corresponding signal points) in the case where 64QAM is performed by the quadrature modulation unit 27 of Fig. 8. The 64QAM ’1 symbol table is not 6 bits, and there are 64 (=26) symbols. Then, 64 symbols are arranged centering on the origin of the IQ plane, and the direction of the direction is 8x8 square. The symbolic element of the symbol of 64QAM is from the highest bit, and can be used as the sequence 70 yG, yi, y2, y3, y4, y5. In the case where the modulation method is 64QAM, the LDPC code code & the 6-bit element is used as the 6-bit symbolic element ^ to the ys symbol. Here, FIG. 13 is a view showing a bit boundary of the highest bit symbol y 〇 and the second symbol bit of the symbol bit ^ to the symbol of 64QAM, respectively; FIG. 14 shows Regarding the bit boundary of the third symbol bit and the fourth symbol bit 兀^3, FIG. 15 shows the bit boundary for the fifth symbol bit h and the sixth symbol bit y5, respectively. As shown in Fig. 13, respectively, the bit boundary of the highest bit and the second bit 135786.doc • 41-200937872 bit yi are one. And, as shown in Fig. 14, respectively The bit boundary of the third symbol bit d and the fourth symbol bit is two; as shown in FIG. I5, respectively, regarding the fifth symbol bit h and the sixth symbol bit y5 The bit boundary is four. Therefore, regarding the symbolic bit "to" of the symbol of 64QAM, the highest bit position 7Gy〇 and the second symbol bit yi become strong bits, and the third symbol is the third symbol. The bit h and the fourth symbol bit become the next strong bit. Then the 0th symbol bit y4 and the 6th bit bit force become the weak bit. From Fig. 12, further from Fig. 13 Figure 15 shows that 'about orthogonal tuning The sign bit of the symbol has a tendency that the high bit becomes a strong bit and the low bit becomes a weak bit. Here, as illustrated in Fig. 11, the LDPC outputted by the LDPC encoding unit 21 (Fig. 8) The code 'has a code bit element that is strong against the error and a code bit element that is inferior to the error. Moreover, as illustrated in FIGS. 12 to 15 , the symbol of the sign το of the orthogonal modulation performed by the quadrature modulation unit 27 is described. Bits, there are strong bits and weak bits. Therefore, if the error bit of the LDPC code is assigned to the weak symbol of the quadrature modulated symbol, it is the tolerance for the error. Sexuality is reduced. Therefore, an interleaver is proposed which interleaves LDPC by assigning the LDpc code to the error-sense code bit 70 to the strong bit (symbol bit) of the quadrature-modulated symbol. The code multiplexer of the code is processed by the multiplexer 25 of Fig. 8. Fig. 16 is a diagram illustrating the processing of the multiplexer 25 of Fig. 8. 135786.doc -42- 200937872 16A is a functional structure example of the solution (4). The multiplexer 25 is constructed by the memory 3丨 and the replacement unit 32. The oblique "remembered body 31' is supplied with the 2kLDpc code from the LDpc coding unit. The memory 31 is contained in the horizontal (r〇w) (horizontal) direction memory and the longitudinal (column) (longitudinal) The memory capacity of the directional memory N/(mb) bit is written in the wale direction of the LDPC code supplied thereto, and is read in the course direction and supplied to the replacement unit 32. Here, N (=information length K + co-located length M) is the code length of the above table *LDpc code. Moreover, m is the number of bits of the code bit of the LDPC code which becomes 1 symbol; b is a specific positive integer, It is used to multiply the claws by multiples. The multiplexer 25 is as described above, and the LDPC code bit is used as a symbol (symbol) multiple b to indicate the number of symbols obtained by the demultiplexer 25 by the so-called 丨 符 。. Fig. 16A shows the structure W of the demultiplexer in the case where the modulation method is 64QAM, and the number of bits of the megablock of the LDpc code which becomes the i symbol is 6111 is 6 bits. Further, in Fig. 16A, the multiple ^^ is 丨, so the memory 31 has a memory capacity in the wale direction X of the Ν/(6χ l)x (6x 1) bit. Here, the course direction of the memory 31 is a memory area in which the 丨 bit extends in the waling direction, and is hereinafter referred to as a wales as appropriate. In Fig. 16, the memory 31 is composed of 6 (= 6 x 1) vertical lines. In the demultiplexer 25, the code bits of the LDPC code are written from the top to the bottom (the wale direction) in the wales constituting the memory 31. The 135786.doc *43-200937872 lines are from the left to the right. get on. Then, the right code bit 7G is written to the bottom of the rightmost vertical line, and is read out from the first column constituting all the wales of the memory 31 in the horizontal direction by 6 bits (mb bits). The code is only supplied to the replacement unit 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 6-bit memory of the memory 31, and the 6-bit obtained as a result is used as the 6-symbol y〇 representing the symbol of 64QAM. Yi, y2, y3, y4, y5 and output. That is, from the memory 31, the code bit ^ of the mb bit (here, 6 bits 0) is read in the course direction, and if the code bit of the mb bit read from the memory 31 is the highest The bit bit counts the first bit (i = 〇, l, · · ., mb - l), and represents the bit position of the 6-bit read from the memory 31 in the course direction. The meta-system is represented by the highest-order bit, which can be expressed as bits b, bi, b2, b3, b4, b5. The relationship between the weights of the rows illustrated in FIG. 11 is that the code bits in the direction of the bit bG are the code bits for the error strength, and the code bits in the direction of the bit elements become the code bits for the error weakness. . The replacement unit 32' 4 causes the code bit b of the 6-bit from the memory 31. To the strong bit of the error weakening in b5, n to the strong bit in the symbol y〇 to ys of the _ ship , , , , , , , , , ys ys ys ys ys ys ys ys ys Replacement of the location. Here, as an alternative to how to replace the 6-bit code bits b〇 to b5 from the memory 31 and assign them to the 6-symbol bits or even the symbols, there are various ways to propose from each company. Fig. 16B shows a first alternative, and Fig. 16C shows a second alternative. Fig. 16D shows a third alternative. 135786.doc 200937872 is shown in Fig. 16B to Fig. 6D (Fig. 17 which will be described later) The same), the line segment... and the line segment of y_i are intended to assign the code bit b; to the symbol y of the symbol (replaced to the position of the symbol y). As a first alternative to Fig. 16B, any one of the three types of alternatives is proposed, and as a second alternative of Fig. 16C, any one of the two types of alternatives is proposed. As a third alternative of Fig. 16D, it is proposed to sequentially select six types of replacement methods for use. Fig. 17 is a diagram showing the multiplexing in the case where the modulation method is 64qAM (hence, the number of bits m of the code bit mapped to the 1-element LDPC code is 6 bits as in Fig. 16) and the multiple 匕 is 2. The configuration example of the device 25 and the fourth alternative. When the multiple b is 2, the memory 31 has a memory capacity of Ν/(6χ2)χ(6χ2) bits in the wale direction, and is composed of 12 (=6χ2) wales. Fig. 17 shows the order in which the LDPC codes of the memory 31 are written. In the demultiplexer 25, as illustrated in FIG. 16, the code bits of the LDPC code are written from the top to the bottom (the wale direction) in the wales constituting the memory 3 1 from the left to the right. get on. Then, if the code bit is written to the bottom of the rightmost vertical line, the code is read from the first column of all the wales constituting the memory 31 to the horizontal direction in units of 12 bits (mb bits). The bit is supplied to the replacement unit 32. The replacing unit 32 performs a replacement process of replacing the position of the code bit from the 12-bit memory of the memory 31 with the fourth alternative, and obtains the 12-bit 兀 obtained as a result of the symbol of 64QAM ( b symbols;) 12 bits, 135786.doc -45· 200937872, which is the 6-symbol yojbyhysjhys representing the 1 symbol of 64QAM and the 6-symbol bit representing the next symbol. The force is 72, 73^475 and is output. Here, Fig. 17B shows a fourth alternative of the replacement process performed by the replacement unit 32 of Fig. 17A. Further, in the case where the multiple b is 2 (the same applies to the case of 3 or more), in the replacement processing, the code bits of the mb bits are allocated to the symbol bits of the mb bits of the consecutive b symbols. Including the figure 17, the i+1th bit from the highest bit of the mb bit of the consecutive b symbols is represented as a bit (symbol bit) for convenience of explanation. Yi. Moreover, what kind of replacement method is appropriate, that is, how to improve the error rate of the AWGN communication channel is different depending on the coding rate, code length, modulation mode, etc. of the lDpc code. Next, the co-interleaving by the parity interleaver 23 of Fig. 8 will be explained with reference to Figs. 18 to 2B. Fig. 18 is a Tanner diagram (part) showing a check matrix of an LDPC code. If the check node is as shown in FIG. 8, two or more of the variable nodes (corresponding code bits) connected to the check node are simultaneously erased and the like, and the pair is connected to the check node. For all variable nodes, the probability of returning the value 〇 and the probability of i are equal probability messages. Therefore, if the complex variable nodes connected to the same check node become erased at the same time, the decoding performance deteriorates. However, the LDPC code of the specification of DVB-S.2 outputted by the LDPC encoding section 21 of Fig. 8 is the ira code, and the parity matrix ht of the check matrix 成为 is a ladder structure as shown in Fig. 10 . Fig. 19 is a view showing a tandem map of a matrix Ητ & which corresponds to the same position J35786.doc -46 · 200937872 matrix Ητ. That is, Fig. 19A shows the parity matrix Ητ which is a step structure; Fig. 19 shows the parity matrix HT^Tannei^ corresponding to Fig. 19A. In the case where the co-located matrix Ητ is a ladder structure, in the Tanner graph of the co-located matrix ', the contiguous code bit (the parity bit) of the row corresponding to the element having the value of the parity matrix Ητ of the LDPC code is used. The variable node of the message is connected to the same check node. Therefore, if the above-mentioned adjacent parity bits become errors at the same time due to clumping errors or erasures, etc., they are connected to complex variable nodes corresponding to the complex multiplicative bits that become erroneous (using the same bit to obtain the information) The check node of the variable node sends the probability of the value 与 and the probability of 1 to the equal probability message back to the variable node connected to the check node, so the decoding performance is degraded. Then, when the length of the cluster (the number of bits that become the error due to the burst) is large, the decoding performance is further deteriorated. Therefore, the 'co-located interleaver 23 (Fig. 8) performs the co-interleaving in which the parity bits of the LDPC code from the LDPC encoding unit 21 are interleaved to the positions of the other parity bits in order to prevent the deterioration of the above-described decoding performance. Figure 20 is a diagram showing the parity matrix ht of the check matrix η of the LDPC code corresponding to the co-interleave 23 of the co-located interleaver 23 of Figure 8 . Here, the information matrix Ha of the inspection matrix η corresponding to the LDPC code defined by the specification of DVB_S 2 output by the LDPC encoding unit 21 is a tour configuration. The tour structure refers to a structure in which a row is consistent with the cycle of other rows, and includes, for example, in each P row, the position of each row of the P row is the first 135786.doc •47-200937872 row of the p row, only The structure of the position after the cyclic shift in the row direction is a value proportional to the value q obtained by subtracting the same length. Hereinafter, the P row of the tour structure is appropriately referred to as the number of rows of the tour structure. The LDPC code defined by the specification of DVB-S.2 outputted by the LDPC encoding unit 21 is as shown in Fig. 11, and has two types of LDPC codes of code length N of 64,800 bits and 16,200 bits. Now, if we look at the LDPC code in which the code length N of the two types of LDPC codes of 64800 bits and 16200 bits is 64800 bits, the code length N © is the encoding of the 64800-bit LDPC code. The rate is 11 as illustrated in Figure 11. Regarding the LDPC code in which the code length N of each of the 11 coding rates is 64,800 bits, in either case, the specification of the unit of DVB-S.2 stipulates that the number of rows P of the unit of the tour structure is the divisor of the same length. One of the covenants except one and the third is 60. Further, regarding the LDPC codes in which the code lengths of the 11 coding rates are 64,800 bits, the parity is expressed by the value "^9><?=9<360, which is different depending on the coding rate. The value other than the prime number. Therefore, the value 9 is also the same as the number of rows P of the unit of the patrol structure, and the other one of the divisors of the same length, and the other one of the divisors, by the unit of the tour structure. The number of 同 is calculated by the same-digit length ( (the product of the divisor and the q is the same-length length M). The co-interleaver 23 is as described above, if the information length is set to K, and the value is 0 or more and less than P When the integer is set to X, and an integer of 0 or more and less than q is set to y, the K+1 to K+M (=N) code bits of the LDPC code from the LDPC encoding unit 21 are used as the parity interleave. The Κ+qx+y+l 135786.doc -48- 200937872 code bits in the same bit are interleaved to the position of the K+Py+x+1 code bits. Since the variable nodes (corresponding co-located bits) connected to the same check node are only separated by the number of rows P of the unit of the tour structure, that is, only 360 bits apart, When the length of the burst is less than 360 bits, the multiple of the variable nodes connected to the same check node can be prevented from becoming a wrong state at the same time, and the result can improve the tolerance to the burst error. +qx+y+l code bits are interleaved to the Κ+Py+x+l code LDP bit position, and the LDPC code after the parity interleaving is performed with the original check matrix Κ+qx+y The LDPC code of the check matrix (hereinafter also referred to as the conversion check matrix) obtained by the row replacement of the +1 row and the Py+x+l row is identical. Moreover, the parity matrix of the conversion check matrix is as shown in FIG. A pseudo-tour structure in which the P line (360 lines in Fig. 20) is used as a unit appears. Here, the pseudo-tour structure means that a part of the circuit structure is a structure of the tour structure. The LDPC code specified for the specification of DVB-S.2 Checking the w matrix, the conversion check matrix obtained by the row replacement corresponding to the co-interlace is part of 360 rows X360 rows in the right corner portion (the shift matrix described later), and only one element of 1 is missing. 0 element), so non- (complete) tour structure In addition, the conversion check matrix of FIG. 20 is a replacement for the original check matrix Η, except for the row substitution corresponding to the co-interleaving, and the column for forming the matrix of the conversion check matrix described later. Matrix after (column replacement) 135786.doc -49- 200937872 Next, with reference to FIG. 21 to FIG. 24, the longitudinal twist interleaving as a rearrangement process by the whirling twist interleaver 24 of FIG. 8 will be described. In the transmitting apparatus 11 of FIG. 8, in order to increase the frequency utilization efficiency, two bits or more of the code bits of the LDPC code are transmitted as one symbol as described above. In other words, for example, when two bits of the code bit are used as one symbol, the modulation method is used as a modulation when, for example, QPSK is used, and four bits of the code bit are used as i symbols. The method utilizes, for example, 16qAM. In this case, when two or more bits of the code bit are transmitted as the first symbol, the code bit of the symbol is erased (erased). Therefore, in order to improve the decoding performance, the probability that the plurality of variable nodes (corresponding code bits) connected to the same check node are simultaneously erased must be avoided, and the code bit corresponding to one symbol must be avoided. The variable nodes are connected to the same check node. On the other hand, as described above, the inspection matrix η of the LDPC code defined by the D specification of Dvb_s.2 outputted by the LDPC encoding unit 21 has a tour matrix structure, and the parity matrix Ητ has a ladder structure. Then, as shown in Fig. 2, the check matrix of the LDPC code after the co-interleaving, that is, the conversion check matrix, also exhibits a tour structure in the parity matrix (correctly, as described above, a pseudo-tour structure). Figure 21 shows a conversion check matrix. That is, Fig. 21A shows a conversion check matrix of the check matrix H of the LDPC code having a code length n of 64,800 bits and a coding rate (1) of 3/4. In Fig. 21A', in the conversion check matrix, the position of the element having a value of 1 is represented by a point 135786.doc -50· 200937872 (·). Fig. 21B shows the processing performed by the demultiplexer 25 (Fig. 8) by using the LDpc code of the conversion check matrix of Fig. 21A, that is, the LDPC code which is interleaved. In Fig. 21B, the modulation mode is set to 16QAM, and the DMA block of the LDpc code which constitutes the multiplexer 25 is written in the wale direction. In the four vertical lines constituting the memory 31, the code bit system ® written in the wale direction is read in the horizontal direction and is read into one symbol in units of four bits. In this case, 'a 4-bit code bit that becomes a symbol> 8(),]81,; 82, 83 may become a code bit 70 corresponding to j of any of the columns of the post-conversion check matrix of FIG. 21A. In this case, respectively, corresponding to the code bit, the variable point of 813233 is connected to the same check node. Therefore, in the case where the code bit of the 4-bit symbol of the 1-bit element 8 〇山132,83 becomes the code bit corresponding to the 〗 column of any of the columns of the post-conversion check matrix, if the symbol is erased Then, the same check node connected to the variable node corresponding to the code bit can not find an appropriate message, and the result 'decoding performance deteriorates. The coding rate other than the coding rate of 3/4 is also the same, and the complex digital bit corresponding to the complex variable node connected to the same check node may be one symbol of 16QAM. Therefore, the 'twist twist interleaver 24 performs the bitwise twist interleaving of the code bits of the LDPC code interleaved from the co-located interleaver 23 so as to correspond to any one of the columns of the conversion check matrix. Complex digital 135786.doc 51 200937872 Bits are not included in 1 symbol. Fig. 22 also shows the longitudinal twisting and staggering, i.e., Fig. 22 shows the solution 17). Picture. The memory 31 of the tool 25 (Fig. 16, the circle 31 is as illustrated in Fig. 16, has memory in the longitudinal (longitudinal) direction] and memorizes the memory of the N/(mb) bit in the horizontal (horizontal) direction. Capacity, consisting of W wales. Then, the longitudinal twisting interleaver 24 is for memory

The body 3 control converts the code bits of the LDPC code into the writ direction in the wale direction K when the K write position ', thereby performing the wobble interleave. That is, in the vertical twist interleaver 24, for each of the plurality of wales, the start write position of the start code bit is appropriately changed so that the complex position of the first symbol is read in the horizontal direction. , does not become corresponding to the code bit located in any one of the columns of the conversion check matrix (rearrangement of the code bits of the LDPC code, so that the complex bits corresponding to any of the columns in the check matrix are not included in The same symbol). The circle 22 is a configuration example of the memory 31 in the case where the modulation mode is 16QAM and the multiple b is as shown in Fig. 16. Therefore, the number of bits of the code bit of the LDPC code that is used as the symbol is the bucket position ^, and 1 memory? ! It consists of 4 (= mb) wales. The whirch twist interleaver 24 (instead of the demultiplexer 25 of FIG. 16) is a vertical line from the left to the right direction, and performs 1^1) 1) (: code bits are coded from 4 constituting the memory 31) The wales are written from the top to the bottom (the waling direction). Then, if the writing of the code bits to the rightmost wales is finished, the walt twist interleaver 24 is from all the wales constituting the memory 3 1 In the first column, the code bit is read out in units of 4 bits (10) bits in the horizontal row 135786.doc • 52· 200937872, and is output to the demultiplexer 25 as the LDPC code after the wobble interleaving. Replacement portion 32 (circle 16 17). Wherein, in the whirling twist interleaver 24, "the wire at the position of the beginning (topmost) of each wales is set to 〇, and the address of each position in the wale direction is expressed in ascending integer, and the leftmost wales are , the write start position is set as the address of the address, and the second write line (from the left) is set to the position where the address is set to 2, and for the 3rd line, the write position is set as the bit. The address is the position of 4, and for the 4th ordinate, the write position will be set as the address for the position. In addition, regarding the starting position where the writing position is a position other than the position of the address, the code bit is written to the lowermost position, and the beginning is returned (the address is the position of the 〇), and the writing position is started immediately. Write to the previous position. Then, the writing to the next (right) wales is performed thereafter. By performing the wobble interleaving as described above, the code length N defined by the specification of DVB S2 is 1^)1> of the coding rate of 64800 (: code can be avoided in the plural connected to the same-check node The complex-matrix of the variable node is used as the symbol of 16QAM (contained in the same symbol), and the decoding performance of the erased communication channel can be improved. The circle 23 is the code specified by the specification of DVB_S2. The LDPC code of the η encoding rate of the long material 6 qing, the number of wales of the memory 31 and the address of the starting writing position necessary for the vertical twisting interleaving according to each modulation mode. Since the multiple b is 1, and In the case of the modulation method, for example, in the case of the number of bits of the i-symbol -: bit, according to Fig. 23, the memory system contains two wales of 2xl (= mb) bits in the horizontal direction. Line 135786.doc -53- 200937872 Direction memory 64800 / (2x1) bit β j After " 2 hidden lines of the hidden body 31, respectively, the starting position of the first vertical line is set as the address of the position 'The start position of the second wales is set to the position where the address is 2. In addition, as for example, the multiplexer 25 (Fig. 8) Conversion processing using the alternative embodiment of FIG. 16] to the third alternative embodiment of any of - when the situation, etc. 'becomes a multiple of 1 b.

Since the multiple b is 2, and qPSK is used as the modulation method, if the number of bits of the ^τ is 2 bits, according to Fig. 23, the memory contains 2x2 bits in the horizontal direction. The four wales store 64800/(2x2) bits in the wale direction. Then, among the four wales of the memory 31, the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start write position of the line is set to the position where the address is *, and the start write position of the *th vertical line is set to the position where the address is 7. Further, when the fourth alternative of Fig. 17 is used as an alternative to the replacement processing of the demultiplexer 25 (Fig. 8), the multiple b becomes 2. Since the multiple b is 1, and the modulation method is, for example, 丨6qAM, when the number of bits of the 1-symbol m is 4 bits, according to FIG. 23, the memory 31 contains 4x1 bits in the horizontal direction. 4 vertical lines of the Yuan, remembering 64800/(4χ 1) bits in the longitudinal direction. Then, in the four wales of the memory 31, the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start of the write position is set to the address of 4, the 4th 135786.doc •54·200937872 The start position of the wales is set to the address of 7. Since the multiple b is 2, and 16HAM is used as the modulation method, for example, when the number of bits of the one symbol is 4 bits, according to FIG. 23, the memory 31 contains 8 bits of 4 bits in the horizontal direction. Longitudinal, remembering 6480〇/(4χ2) bits in the longitudinal direction. Then, among the eight wales of the memory 31, the start write position of the ninth wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position where the address is 0, and the third vertical The start position of the line is set to the position of the address 2, the start position of the 4th ordinate is set to the position where the address is 4, and the start position of the waling is set to the position where the address is 4, the 6th vertical The start write position of the line is set to the position where the address is 5, and the start write position of the seventh vertical line is set as the address for the position, and the start write position of the eighth vertical line is set to the position of the address 7. Since the multiple 1) is used as the modulation method and 64QAM is used as the modulation method, for example, when the number of bits of the 1 symbol is 6 bits, according to FIG. 23, the memory 31 contains 6 bits of the memory in the horizontal direction. Longitudinal, remembering 64800/(6x1) bits in the wale direction. Then, among the six wales of the memory 31, the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position of the address 2, the third vertical The start position of the line is set to the position where the address is 5, the start position of the 4th vertical line is set to the position where the address is 9, and the write position of the 5th vertical line is set to the position of the address of 1〇, the sixth position. The start position of the wales is set to the position of the address 13. Since the multiple b is 2, and the modulation method is, for example, 64QAM, if the number of bits of the 1 symbol is 6 bits, according to FIG. 23, the memory 135786.doc -55· 200937872 31 is included in the course. The direction stores 12 vertical lines of 6x2 bits, and stores 648〇〇/(6x2) bits in the longitudinal direction. Then, in the 12 wales of the memory 3 1 , the start write position of the first wales is set as the address of the 〇, and the start write position of the second traverse is set to the position where the address is 0. The write start position of the wales is set to the position where the address is 2, the start write position of the 4th ordinate is set to the position where the address is 2, and the start write position of the 5th vertical line is set to the position where the address is 3, the sixth position The start position of the wales is set to the address of 4, the start position of the 7th ordinate is set to the address of 4, and the write position of the 8th traverse is set to the position of 5 The write position of the ninth vertical line is set to the position where the address is 5, the start write position of the first vertical line is set to the address of the address 7, and the start write position of the first vertical line is set as the address. At the position of 8, the start position of the 12th wales is set to the position of the address 9. Since the multiple b is 1, and the modulation method is, for example, 256qam, the number of bits of the first symbol „! is 8 bits, and according to FIG. 23, the memory 31 contains 8×1 bits in the horizontal direction. The 8 vertical lines of the element store 64800/(8x1) bits in the wale direction. ❹ Then, in the 8 wales of the memory 31, the start write position of the 丨 丨 设 is set as the address of the 〇 The write position of the 2nd wales is set to the address of 〇. The write position of the 3rd ordinate is set to the address of 2, and the write position of the 4th trajectory is set to the address of 4. Position, the start position of the 5th ordinate is set to the address of 4, the start position of the 6th ordinate is set to the address of 5, and the write position of the 7th traverse is set to the address of 7. Position, the start position of the 8th wales is set to the position of the address 7. Since the multiple b is 2' and the modulation method is used, for example, 256qAM, because 135786.doc -56- 200937872 is a 1-bit bit In the case where the number m is 8 bits, according to Fig. 23, the memory 31 contains 16 vertical lines in which 8 χ 2 bits are stored in the course direction, and is recorded in the waling direction. 64800/(8x2) bit. Then, in the 16 wales of the memory 3 1 , the start write position of the 丨 丨 设 is set as the address of the 〇, and the write position of the 2nd ordinate is set as the bit. The address is 2, the write position of the 3rd vertical line is set to the position where the address is 2, the write position of the 4th vertical line is set to the position where the address is 2, and the write position of the 5th vertical line is set as the write position. The address of the address is 2, the write position of the sixth vertical line is set to the position where the address is 3, and the write position of the 7th vertical line is set to the position where the address is 7, and the write position of the eighth vertical line is started. The address is set to the position of 15, the write position of the ninth wales is set to the address of 16, and the write position of the first wales is set to the address of 20, the beginning of the ut. The write position is set to the address of the address 22, the start write position of the 12th vertical line is set to the position of the address of ^, and the start write position of the 13th vertical line is set to the position of the address of 27, the second vertical line The start write position is set to the position where the address is 27, the start write position of the 15th vertical line is set to the position of the address 28, and the start write position of the 16th vertical line is set to the position of the address of 3 2 Since the multiple b is 1, and the modulation method is, for example, 1〇24QAM, when the number of bits of the 1 symbol is (7) bits, according to FIG. 23, the memory 3 1 is stored in the horizontal direction. The 纵 丨〇 记忆 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 The address of the address is 〇, the write position of the 2nd ordinate is set to the address of 3, and the write position of the 3rd trajectory is set to the address of 6, 135786.doc -57· 200937872 4 The write start position of the wales is set to the address of 8, the start write position of the 5th ordinate is set to the address of the address 11, and the start write position of the sixth traverse is set to the position of the address of 13, the first The start position of the 7 wales is set to the position where the address is ^, the start write position of the 8th wales is set to the position of the address 17, and the start write position of the ninth walt is set to the position of the address of 18, The first write position of the first wales is set to the position of the address 20. Since the multiple b is 2, and the modulation method is, for example, 1〇24QAM, when the number m of the 1-symbol is 1〇, the memory © 31 is included in the course direction according to FIG. It memorizes 20 vertical lines of 10x2 bits and memorizes 64800/(1〇χ2) bits in the longitudinal direction. Then, in the 20 wales of the memory 3 1 , the start write position of the ith wales is set as the address of the 〇, and the start write position of the second row is set as the address of the address 1, the third The start position of the wales is set to the position where the address is 3, the start position of the 4th rowth is set to the position where the address is 4, and the start position of the 5th traverse is set to the position where the address is 5, the sixth position The start position of the wales is set to the position where the address is 6, the start position of the seventh rowth is set to the address of the address 6, and the start write position of the eighth trajectory is set to the position of the address of 9, The write position of the ninth wales is set to the address of 13, the start write position of the first wales is set to the address of 14, and the start write position of the utitudinal line is set to address 14 Position, the start position of the ">2 wales is set to the address of 丨6, the start write position of the 13th traverse is set to the position of the address 21, and the start write position of the twentieth line is set as the address. For the position of 21, the start position of the 15th wales is the position where the address is 23, and the start of the 16th traverse is set to the position of 25, and the start of the 7th wales The location is set to the address 135786.doc -58 · 200937872. The beginning of the 18th traverse is set to the address of 26, and the write position of the 19th traverse is set to the location of 28. The start position of the 20th wales is set to the position where the address is 30. Since the multiple b is 1, and the modulation method is, for example, 4096QAM, if the number of bits of the 1 symbol is 丨] bit, if according to FIG. 23, the memory 3 1 is stored in the horizontal direction. 2 纵 丨 2 纵 , , 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 64 64 64 64 64 64 64 64 64 64 64 64 64 Then, in the 12 wales of the memory 3 1 , the writing position of the first waling is set to the position of 〇, and the writing position of the second traverse is set to the position of 0. 3 The starting position of the vertical line is set to the position where the address is 2, the writing position of the 4th vertical line is set to the position where the address is 2, and the writing position of the 5th vertical line is set to the position of the address of 3, The start position of the sixth vertical line is set to the position where the address is 4, the start write position of the seventh vertical line is set to the position where the address is 4, and the start write position of the eighth vertical line is set to the position of the address of 5. The write position of the ninth wales is set to the position where the address is 5, and the start of the first 〇 写 写 写 叹 叹 叹 叹 位 位 位 , , 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第For the position of 8, the start position of the 12th wales is set to the position where the address is 9. Since the multiple b is 2, and the modulation method is, for example, 4〇96QAm, the case where the number 111 of the 1 symbol is 12 bits, if the memory 31 is 3, the memory is stored in the horizontal direction according to FIG. 24 vertical lines of the Yuan, remembering 64800/(12x2) bits in the longitudinal direction. Then, among the 24 wales of the memory 3, the start of the 丨 丨 又 又 又 又 位置 , , , , , , , , , , , 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The start position of the wales is set to the address of 8, 135786.doc •59· 200937872 The start position of the 4th wales is set to the address of 8 and the write position of the 5th ordinate is set as the bit. The address of the address is 8 'the start position of the sixth vertical line is set to the address of 8, the start position of the 7th vertical line is set as the address (4), and the write position of the 8th vertical line is set as the position. The address is 1 ,, the start position of the ninth wales is set to the address of 10, and the start write position of the 1st wales is set to the address of 12, and the write position of the U walt is started. The address is set to the position of 13, and the write position of the 12th vertical line is set to the address of "the position, and the write position of the 13th vertical line is set to the position of the address of 17," The start write position is set to the address of 19, the start position of the 15th traverse is set to the address of 21, and the write position of the 16th trajectory is set to the address of 2 In the position of 2, the writing position of the 17th waling is set as the position of the phantom, the writing position of the 18th ordinate is set to the position where the address is %, and the writing position of the first traverse is set as the address. For the position of 37, the start write position of the 2nd wales is set to the position of 39, the start write position of the 21st walt is set to the address of 40, and the write position of the 22nd walt is set as the start position. The address is the position of 〇, and the write position of the 23rd rowth is set to the position where the address is u, and the write position of the first trajectory is set to the position of the address 41. Fig. 24 is for DVB_S.2 The code length N specified by the specification is the LDPC code of the encoding rate of l62oo, and the number of vertical lines of the memory 31 and the address of the start writing position necessary for the vertical twisting interleaving are expressed in each modulation mode. If 1' is used as the modulation method, for example, QpSK is used. Therefore, in the case where the bit number t of the i symbol is 2 bits, according to Fig. 24, the memory 31 contains 2 wales of 2x1 bits in the course direction. , memory 16200/(2x1) bits in the wale direction. 135786.doc •60- 200937872 Then, in the 2 wales of memory 3 1 The first write position is set to the position of the address, and the write position of the second vertical line is set to the position where the address is 0. Since the multiple b is 2, and as a modulation method, for example, QpSK is used. Therefore, in the case where the number m of the symbol is 2 bits, according to Fig. 24, the memory 3^ contains 4 vertical lines of 2 X2 bits in the horizontal direction and 16200/ in the vertical direction. 2x2) Bits. Then, in the 4 wales of the memory 3 1 , the write bit of the 丨 丨 © © © © © © © ' ' ' ' ' ' ' ' ' ' ' ' ' ' 第 第 第 第 第 第 第 第 第 第 第 第For the position of 2, the start position of the 3rd rowth is set to the position where the address is 3, and the start write position of the 4th traverse is set to the position where the address is 3. Since the multiple b is 1, and the modulation method is, for example, 16QAM, if the number of bits of the 1-symbol is 4 bits, according to FIG. 24, the memory 31 contains 4×1 bits in the horizontal direction. A vertical line that memorizes 16200/(4 xl) bits in the wale direction. 〇 Then, among the four wales of memory 31, respectively! The write start position of the wales is set to the position where the address is 0. The start write position of the 2nd wales is set to the address of 2, and the write position of the 3rd ordinate is set to the position of the address of 3, * The start position of the wales is set to the position where the address is 3. Since the multiple b is 2, and the modulation method is, for example, 16QAM, the number of bits of the symbol is 1! "In the case of 4 bits, if the memory is based on the graph %, the memory system contains 4x2 in the horizontal direction. The eight vertical lines of the bit store 16200/(4x2) bits in the wale direction. Then, in the 8 wales of the 6 mnemonic body 3, the writing position of the 丨 丨 135 135 786.doc -61 - 200937872 is set as the address of the 〇, and the writing position of the 2nd ordinate is set. The address is the location of the 〇 'the third write start position is set to the address of 〇, the start position of the fourth traverse is set to the address of 1, the start position of the fifth trajectory The address is set to the position of 7, the start position of the sixth vertical line is set to the address of 20, and the write position of the seventh vertical line is set to the position of the address of 2 ' 'the beginning of the eighth vertical line The write location is set to the location of the address 21. Since the multiple b is 1, and the modulation method is, for example, 64qam, if the number of bits of the 1 symbol is 6 bits, 'If the memory 3 1 is stored in the horizontal direction, 6 X according to FIG. 24 6 vertical lines of 1 bit, memory 16200/(6 XI) bits in the longitudinal direction. Then, in the six wales of the memory 3 1 , the start write position of the first wales is set to the position where the address is 0, and the start write position of the second traverse is set to the position of the address ' 3 The write bit at the beginning of the wales is set to the position where the address is 2, the start write position of the 4th rowth is set to the position where the address is 3, and the start write position of the 5th traverse is set to the position where the address is 7. The start position of the sixth vertical line is set to the position where the address is 7. Since the multiple b is 2, and the modulation method is, for example, 64QAM, the number of bits of the 1 symbol is „! is 6 bits, and according to FIG. 24, the memory 31 is stored in the horizontal direction to store 6×2 bits. The 12 vertical lines of the element store 16200/(6x2) bits in the longitudinal direction. Then, in the 12 vertical lines of the memory 31, the start writing position of the first walt is set as the address of the 〇, The write position of the second wales is set to the position of 〇, the write position of the third traverse is set to the position of 〇, and the write position of the fourth traverse is set to the position of address 2. , 5th vertical opening 135786.doc •62· 200937872 The initial writing position is set to the address of 2, the beginning of the 6th vertical writing position is set to the address of 2, the beginning of the 7th vertical line The position is set to the position where the address is 3'. The write position of the 8th vertical line is set to the position where the address is 3, and the start write position of the 9th vertical line is set to the position where the address is 3, and the first vertical line is The start write position is set to the address of 6, the start write position of the 11th vertical line is set to the address of the address 7, and the start write position of the 12th vertical line is set as the address is 7. Since the multiple b is 1 ' and the modulation method is, for example, 256qam, if the number of bits of the 1 symbol is 8 bits, according to Fig. 24, the memory 31 is included in the course. The direction stores 8 octets of 8x1 bits, and memorizes 16200/(8x1) bits in the wales direction. Then, among the 8 wales of the memory 31, the start write position of the 丨 丨 is set as the address. In the position of the 纵, the write position of the 2nd ordinate is set to the address of 〇 'the start position of the 3rd row is set as the address of 〇, and the write position of the 4th traverse is set as the address For the position of 1, the write position of the fifth wales is set to the position of the address 7, and the start of the sixth traverse is set to the position where the address ❿ is 20, and the write position of the seventh traverse is set as the start position. The address is 2〇, and the write position of the 8th ordinate is set to the address of 2丨. Since the multiple b is 1, and the modulation method is, for example, 1024qam, the number of bits of the 1 symbol is clamped. In the case of the element, according to FIG. 24, the memory 3 1 contains 10 vertical lines of 1 〇 x 1 bit in the horizontal direction, in the longitudinal direction. The memory is 16200/(10x1) bits. Then, in the memory 3 1 of 1 纵 纵, the write position of the first wales is set as the address of 〇, and the write position of the 2nd ordinate is started. The position where the address is 1 is 'the start position of the 3rd vertical line is set to the position where the address is 2, 135786.doc -63 - 200937872 The write position of the 4th vertical line is set to the position where the address is 2, The start position of the fifth wales is set to the position where the address is 3, the start write position of the sixth traverse is set to the position where the address is 3, and the start write position of the seventh traverse is set to the position of the address of 4. The write position of the 8th wales is set to the position where the address is 4, the start write position of the ninth wales is set to the address of 5, and the start write position of the 1st wales is set to the address of 7 position. Since the multiple b is 2, and the modulation method is, for example, 1〇24QAM, if the number of fingers of the 1st 70 is the i 〇 bit, the memory type body 31 is included in the course direction according to Fig. 24 It memorizes 20 vertical lines of 10X2 bits and memorizes 16200/(10x2) bits in the longitudinal direction. Then, in the 20 wales of the memory 3 1 , the start write position of the ith walt is set as the address of the 〇, and the start write position of the second row is set as the address of the ,, the third The start position of the wales is set to the position of 〇, the start position of the 4th rowth is set to the position where the address is 2, and the start write position of the ideographic trajectory is set to the position where the address is 2' 6 The starting position of the vertical line is set to ◎ the position of the address is 2, the writing position of the 7th vertical line is set to the position where the address is 2, and the writing position of the 8th vertical line is set to the position of the address of 2, The start position of the ninth wales is set to the position where the address is 5, the start write position of the first wales is set to the position of the address 5, and the start write position of the utitudinal line is set to the address of 5 Position, the start position of the 12th wales is set to the position of the address, the start position of the 13th traverse is set to the address of 5, and the start position of the 14th traverse is set to the address of 7 At the position, the write position of the 15th wales is set to the position of the address 7, the start position of the 16th wales is set to the position of the address 7, and the write position of the 17th ordinate is started. The address is set to the position of 7, the first write position of the 135786.doc 200937872 18 wales is set to the address of 8, the beginning of the 19th traverse is set to the address of 8, the 20th vertical The start of the line write position is set to the address of 1 〇. Since the multiple b is 1, and the modulation method is, for example, 4〇96qaM, when the number m of the 1-symbol is 丨2 bits, the memory 31 is included in the course direction according to FIG. 24 Memorize 2 wales of i2x i bits and remember 16200/( 12x1) bits in the wales. Then, in the two wales of the memory 3 1 , the write position of the first wales is set to the position of the address, and the write position of the second traverse is set to the address of the address of 0. The write position of the third vertical line is set to the position of the address, the write position of the fourth vertical line is set to the position of the address 2, and the write position of the fifth vertical line is set to the position of the address of 2. The write position of the sixth vertical line is set to the position where the address is 2, the start write position of the seventh vertical line is set to the position where the address is 3, and the start write position of the eighth vertical line is set to the address of 3 The start write position of the position 9th wales is set to the position where the address is 3, the start write bit q of the 1st vertical line is set to the position where the address is 6, and the start write position of the 11th vertical line is set as the address. For the position of 7, the start position of the second wales is set to the position of the address 7. Since the multiple b is 2, and the modulation method is, for example, 4〇96QAM, if the number of bits of the 1 symbol is mg12 bits, the memory 31 is stored in the course of the direction according to Fig. 24)) <2 The 24 vertical lines of the bit store 16200/(12x2) bits in the wale direction. Then, among the 24 wales of the memory 31, the start write position of the ith wales is set as the address of the 〇, and the start write position of the second traverse is set as the address of the ,, the third vertical The start of the write position is set to the address of 〇, 135786.doc 200937872 The start position of the 4th traverse is set to the address of 〇, and the write position of the 5th trajectory is set as the address. Position, the start position of the sixth vertical line is set to the position where the address is 0. 'The start position of the 7th vertical line is set to the address where the address is ''. The start position of the 8th vertical line is set as the address is 1 At the position, the start position of the ninth wales is set to the position where the address is 1, the start position of the 丨〇 丨〇 is set to the position where the address is 1, and the start of the utitudinal write position is set as the address. For the position of 2, the start position of the 12th wales is set to the position where the address is 2, the start write position of the 13th wales is set to the position where the address is 2, and the start of the utitudinal line is set to be the write position. The address of the address is 3, the write position of the 15th vertical line is set to the address of the address 7, and the start write position of the 16th vertical line is set to the position of the address of 9, The write position of the 17th wales is set to the position where the address is 9, the start position of the 18th wales is set to the position of the address 9, and the start of the 19th traverse is set to the position of the address of 10. The write position of the 2nd vertical line is set to the address of 10, the start write position of the 21st vertical line is set to the address of 1〇, and the start write position of the 22nd vertical line is set as the address is In the position of the 丨〇, the write position of the 23rd wales is set to the position of 1 ,, and the write position of the wales is set to the position of 1 1 . Next, the transmission processing performed by the transmitting apparatus u of Fig. 8 will be described with reference to the flowchart of Fig. 25. The LDPC encoding unit 21 supplies the target data to the step si〇i, encodes the target data into an LDPC code, and supplies the LDpc code to the bit interleaver 22'. The processing proceeds to step S102. The bit interleaver 22 is in step S102, and the LDPC code from the LDPC encoding unit 21 is subjected to bit interleaving, and the 135786.doc -66 - 200937872 LDPC code symbolized symbol is interleaved. The processing is supplied to the mapping unit %, and the processing proceeds to step S103. That is, in step S102, in the bit interleaver 22, the parity interleaver takes the LDPC code from the LDPC composing unit 21 as an object, and performs the same position.

Wrong, the co-interleaved LDPC code is supplied to the longitudinal twisted calcium 24. The S-wound twisting interleaver 24 performs the wobble interleaving from the co-located interleaver 232LDpc code and supplies it to the demultiplexer 25. The demultiplexer 25 replaces the code bits of the LDPC code which are longitudinally twisted and interleaved by the wobble interleaver 24, and performs the symbol bit of the replaced code bit as a symbol (representing the symbol Replacement processing of bits). Here, the replacement processing by the demultiplexer 25 can be performed in accordance with the "the fourth to fourth alternatives shown in FIG. 17, and can also be performed according to the allocation rule. The allocation rule is used. The rule of assigning a code bit of 1^1)1> (: code to a symbol bit representing a symbol, which will be described later in detail. The symbol obtained by the replacement processing of the multiplexer 25 is obtained. The signal is supplied from the demultiplexer 25 to the mapping unit 26. The mapping unit 26 is in step 8103, and maps the symbols from the demultiplexer to the modulation method of the quadrature modulation by the quadrature modulation unit 27. The determined signal point is supplied to the quadrature modulation unit 27' processing unit and proceeds to step sl4. The quadrature modulation unit 27 performs the orthogonality of the carrier in accordance with the signal point from the mapping unit % in step S104. Modulation, the processing proceeds to step sl5, the modulated signal obtained by the result of the quadrature modulation is transmitted, and the processing is terminated. 135786.doc -67- 200937872 In addition, the transmission processing of FIG. 25 is repeated in the pipeline. As above, the LDPC can be improved by performing the co-interleaving or the longitudinal twisting interleaving. The complex number of bits is transmitted as a symbol or the financial error of the clumping error. In the case of this figure, in Figure 8, for the sake of convenience, the blocks that are co-located in the same way are co-located. The interleaver 23 and the whirling torsional whirling interleaver 24 are formed, but the in-situ interleaver 23 and the whirling torsion device μ may be integrally formed.

That is, the co-located interleaving and the directional intertwial interleaving can be performed by the code bit to write and read the memory, and can be converted by inputting the bit (10) into the address of the code bit. It is represented by a matrix of addresses (read addresses) from which the code bits are read. Therefore, if the matrix obtained by multiplying the matrix representing the co-located interlace and the matrix representing the wobble interleaving of the wales are obtained in advance, the co-located interleaving can be obtained by using the (four)-converted code bit 疋', and the co-located interleaving is performed in advance. The latter LDPC code is the result of the twisted interleaving. Further, the demultiplexer H23 and the longitudinal twist interleaver (10) external demultiplexer 25 may be integrally formed. That is, the #change process performed by the demultiplexer 25 can also be expressed by converting the write address of the memory 31 of the memory LDPC into a matrix of read addresses. Therefore, if a matrix representing the co-located interlace, a matrix representing the wobble interleave, and a matrix obtained by the matrix representing the replacement process are obtained in advance, the parity interleaving, the wobble interleaving, and the replacement can be performed by the matrix. 135786.doc •68· 200937872. Further, regarding the co-interlacing and the whirling twisting, only one or both of them may not be performed. Next, with reference to Figs. 26 to 28, an simulation of the measurement error rate (bit error rate) performed with respect to the transmitting apparatus 11 of Fig. 8 will be described. The analog system uses a communication channel with D/U for OdB with flutter. Ο Figure 26 shows the model of the communication channel used for the simulation. That is, Fig. 26A shows a model of the flutter used in the simulation. Further, Fig. 26B shows a model of the chattering channel of the flutter represented by the model of Fig. 26A. Further, in Fig. 26B, Η represents the model of the flutter of Fig. 26A. Further, in Fig. 26, Ν denotes ICI (Inter Carrier Interference), and in the simulation, the expected value E[N2] of the power is approximated by AWGN. Fig. 27 and Fig. 28 show the relationship between the error rate obtained by the simulation and the frequency of the flutter 〇 ¥ frequency & Further, Fig. 27 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 16QAM and the coding rate (r) is (3/4), and the alternative is the first alternative. Further, Fig. 28 shows the relationship between the error rate and the Doppler frequency fd in the case where the modulation method is 64QAM and the coding rate (r) is (5/6), and the alternative is the first alternative. Further, in FIGS. 27 and 28, the thick line indicates the relationship between the error rate in the case of performing the co-located interleaving, the longitudinal torsional interleaving, and the replacement processing, and the relationship between the I35786.doc -69-200937872 Buhler frequency fd, thin line The relationship between the error rate and the Doppler frequency fd in the case of performing the interleave interleaving, the wobble interleave, and the replacement processing in the replacement process. As shown in any of Figs. 27 and 28, it can be seen that the case where all of the co-located interleaving, the whirling twist interleaving, and the replacement processing are performed is a case where only the replacement processing is performed, and the error rate is increased (smaller). Next, the LDPC encoding unit 21 of Fig. 8 will be further explained. As illustrated in Fig. 11, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64,800 bits and 〇16,200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and 8/9 (Fig. 11B). The LDPC encoding unit 21 encodes the LDPC code of each of the code lengths of 64800 bits or 16200 bits according to the check matrix 准备 prepared for each code length N and per coding rate (error correction) coding). FIG. 29 shows an example of the configuration of the LDPC encoding unit 21 of FIG. The LDPC encoding unit 21 is composed of an encoding processing unit 601 and a storage unit 602. The encoding processing unit 601 is composed of a coding rate setting unit 611, an initial value table reading unit 612, a check matrix generating unit 613, an information bit reading unit 614, a coded parity calculating unit 615, and a control unit 616, and supplies them. The LDPC code of the target data to the LDPC encoding unit 21 is supplied to the bit interleaver 22 (Fig. 8) by the 135786.doc -70-200937872 LDPC code obtained as a result. In other words, the coding rate setting unit 611 sets the code length N and the coding rate of the LDPC code based on, for example, the operation of the operator. The initial value table reading unit 612 reads out the check matrix initial value table described later in accordance with the code length N and the coding rate set by the coding rate setting unit 611 from the storage unit 602. The check matrix generation unit 613 is arranged in accordance with the cycle of the check matrix initial value table ' read in the initial direction table reading unit 612 every 36 lines (the number of rows P of the circuit structure). The check matrix η is generated based on the code length N set by the coding rate setting unit 6 and the information length κ (= code length N - parity length 之) of the information matrix HAil and stored in the memory unit 6 2. The information bit reading unit 614 reads (takes) the information bits of the information length K from the object information supplied to the LDPC encoding unit 21. The coding co-located operation unit 615 reads the inspection matrix H generated by the inspection matrix generation unit 613 from the storage unit 602, and calculates the parity bit of the information bit read by the information bit reading unit 614 based on the specific expression to generate a parity bit. Code word (ldpc code). The control unit 616 controls each block constituting the encoding processing unit 6A. The memory unit 602 stores a complex check matrix initial value table corresponding to the complex code rates shown in Fig. n for the two code lengths N of 64800 bits and 16200 bits, respectively. Further, the storage unit 602 temporarily stores the data necessary for the processing of the encoding processing unit 601. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21 of Fig. 29. In step S201, the coding rate setting unit 611 determines (sets) the code length N and the coding rate r to be coded by LDpc 135786.doc 71 200937872. In step S202, the initial value table reading unit 612 reads out a predetermined check matrix initial value table corresponding to the code length N and the coding rate determined by the coding rate setting unit 611 from the storage unit 6〇2. In step S203, the check matrix generation unit 613 obtains (generates) the code length N determined by the coding rate setting unit 611 by using the check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612. And the inspection matrix H of the LDPC code of the encoding rate is supplied to the memory unit 6〇2 and stored. In step S204, the information bit reading unit 614 reads the information length K corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611 from the target data supplied to the LDPC encoding unit 21. The information bit of (=Nxr) is read from the storage unit 602 by the check matrix Η obtained by the check matrix generation unit 613, and supplied to the coded parity calculation unit 615. In step S205, the coded co-located operation unit 615 sequentially calculates the parity bits of the code word C conforming to the equation (8).

HcT = 〇 · · · (8) where (8) ’ c denotes a column vector as a martensial (LDPC code), and CT denotes a transpose of the column vector c. Here, as described above, in the column vector LDP of the LDPC code (1 code word), the column vector A represents a portion of the information bit, and in the case where the column vector τ represents a portion of the parity bit, the column vector c can be It is represented by the column vector A as the information bit and the column vector T as the parity bit, and is represented by the formula c=[a|T]. Check matrix Η and column vector c=[A|T] as LDPC code must conform to 135786.doc -72- 200937872

HcT=0, as the column vector T constituting the parity bit of the column vector c=[A|T] conforming to the equation HcT=0 can be obtained by the parity matrix Ητ of the check matrix H=[HA|HT] In the case of the step structure shown in the figure, the elements of the first column of the row vector HcT of the equation HcT=0 are sequentially obtained by sequentially making the elements of the respective columns zero. When the coded co-located operation unit 61 5 finds the co-located bit T for the information bit A, the code word c=[A|T] represented by the information bit A and the co-located bit T is used as the information bit A. The LDPC coded result is output. 〇 In addition, the codeword c is 64800 bits or 16200 bits. Thereafter, in step 8206, the control unit 616 determines whether or not [??: encoding. In the case where it is determined in step S206 that the LDPC encoding is not finished, that is, for example, if there is still object data to be LDPC-encoded, The processing returns to step S201, and the processing of steps S201 to S206 is repeated as follows. Further, in the case where it is determined in step S206 that the LDPC encoding is ended, that is, for example, in the case where there is no object data to be LDPC-encoded, the LDPC encoding unit 21 is terminated. As described above, the inspection matrix initial value table corresponding to each code length N and each coding rate r is prepared, and the LDPC encoding unit 21 encodes the LDPC encoding the specific coding rate r of the specific code length N, which corresponds to the The check matrix generated by the check matrix initial value table of the specific code length N and the specific coding rate r is performed. The check matrix initial value table checks the matrix Η corresponding to the LDPC code according to the LDPC code (by checking the matrix Η) The code length of the code N and the information of the code rate r. The position of the element of the information matrix HA (Fig. 9) 1 is expressed in units of 360 lines (the number of rows of the circuit of the tour structure), according to each code. Long N and each code 135786.doc -73- 200937872 The check matrix of rate r is prepared one by one. Fig. 31 to Fig. 58 show the table of initial values of several check matrices specified by the specifications of DVB-S.2. That is, Fig. 31 shows DVB. -S.2 specification specifies the code length Ν is 16200 bits of code rate|> is 2/3 check matrix η check matrix initial # Value table ® Figure 32 to Figure 34 shows DVB-S The specification of .2 is for the check matrix of the code length Ν 64800 bits, which is 2/3, and the check matrix initial check value table. 11 In addition, 'Fig. 33 is connected to Fig. 32, Fig. 34 The diagram is continued from Fig. 33. Fig. 35 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 162 〇〇 for the code length r of 3/4 as defined by the specification of DVB-S.2. Fig. 36 to Fig. 39 show the check matrix initial value table of the check matrix 编码 for the code length 64 64800 bits with a code length 为 of 3/4 as defined by the specification of DVB-S.2 ❹ In addition, 'Fig. 37 Figure 38 is a view continuing from Figure 37. Figure 39 is a view subsequent to Figure 38. Figure 40 shows the specification of DVB-S.2 for a code length of 16200. The bit rate r of the bit is the check matrix initial value table of the check matrix of 4/5. Fig. 41 to Fig. 44 show the coding rate for the code length 64 64800 bits specified by the specification of DVB-S.2. r is a check matrix initial value table of 4/5 check matrix. In addition, Fig. 42 is continued from Fig. 41, and Fig. 43 is continued from Fig. 42 135786.doc-74-200937872. Moreover, Fig. 44 is a view subsequent to Fig. 43. Fig. 45 is a table showing the check matrix initial value of the check matrix 编码 for the code rate r of i/62. Fig. 46 to Fig. 49 are diagrams showing the check matrix initial value table of the inspection matrix 编码 for the coding rate 1* of 5/6 of Ma ChangΝ, which is defined by the specification of DVB-S.2. Further, Fig. 47 is a view continuing from Fig. 46, and Fig. 48 is a view continuing from Fig. 47. Moreover, Fig. 49 is continued from Fig. 48. Figure 50 is a table showing the initial value of the check matrix of the check matrix 编码 with a code length 16 of 16200 bits and a code rate of 8/9 as defined by the specification of DVB-S.2. Fig. 51 to Fig. 54 are diagrams showing the initial value of the check matrix of the check matrix of 8/9 as defined by the specification of DVB-S.2 for the code rate 64 64800 bits. Further, Fig. 52 is continued from Fig. 51, and Fig. 53 is continued from Fig. 52. Moreover, Fig. 54 is continued from Fig. 53. Fig. 55 to Fig. 58 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length Ν ® 64800 bits with a code rate r of 9/10 as defined by the specification of DVB-S.2. Further, Fig. 56 is continued from Fig. 55, and Fig. 57 is continued from Fig. 56. Moreover, Fig. 58 is continued from Fig. 57. The inspection matrix generation unit 613 (FIG. 29) obtains the inspection matrix 如 by using the inspection matrix initial value table as follows. That is, Fig. 59 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. 135786.doc -75- 200937872 In addition, the check matrix initial value table of Fig. 59 indicates the code length 1 <[ 162 〇〇 bit code rate] specified for the specification of DVB-S.2 shown in Fig. 31 Check the matrix initial value table for the 2/3 check matrix. The check matrix initial value table is as described above, and corresponds to the position of the element after the information matrix Ha (Fig. 9) according to the code length N of the LDpc code and the information rate r, for every 360 lines (tour structure) The table of the number of rows of the unit p), in its column i, check the chain of the elements of the i-th row of the matrix ( (the number of the column in the first column of the inspection matrix is set as the column number) © The number of lines of the line that has the 1+36〇x(il) line. Here, since the parity matrix Ητ ( FIG. 9 ) corresponding to the parity M of the check matrix 决定 is determined as shown in FIG. 19 , if the check matrix initial value table ' can be obtained, the check matrix Η corresponds to the information length κ . The information matrix Ηα (Fig. 9) 〇 Check the matrix initial value table number k + Ι is different depending on the information length. The relationship of the equation (9) holds between the information length K and the number k+1 of the check matrix initial value table. K = (k + l) x 360 • (9) Here, 360 of the equation (9) is the number of rows P of the unit of the tour structure illustrated in Fig. 20. In the inspection matrix initial value table of Fig. 59, i 3 numerical values are arranged from the first column to the third column, and three values are arranged from the fourth column to the k+1th column (the 30th column in Fig. 59).

Therefore, the check weight of the check matrix H 135786.doc • 76· 200937872 obtained from the check matrix initial value table of Fig. 59 is from the 1st line to the 1+36〇x(3-1)-1 behavior 13, From the l+36〇x(3-l) line to the Kth act 3. The first column of the check matrix initial value table of Fig. 59 is 0 ' 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622, which is shown in the first row of the check matrix Η The elements whose column numbers are 0, 2084, 1613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, and 2622 are ι (and other elements are 0). Ο Moreover, the second column of the check matrix initial value table of Fig. 59 is 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3 108 'This is shown in the inspection matrixΗ The 361th (=1 + 36〇x(2 - 1)) row, column number is 1, 122, 1 5 16, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108 The factor is 1. As shown above, the inspection matrix initial value table will check the position of the element of the information matrix Ηα of the matrix 以 in every 360 rows. Check the line other than the 1+360x(il) line of the matrix ,, that is, the line from the 2+36〇x(il) line to the 36th 〇 line will be determined by checking the matrix initial value table. The element of 1 + 36 〇 x (il) line is cyclically shifted according to the same length μ in the downward direction (downward direction of the line). That is to say, 'for example, the 2+36〇χ(Μ) line will only shift the head of the ((10)(1)丨) row downwards by M/360(=q) 'then the first line will be the l+36〇x ( Il) The line is only cyclically shifted by 2xM/36〇(=2xq) in the downward direction (the second 2+3 60><〇1) line is rotated only downwards]^/36〇(=(1)) 135786.doc •77- 200937872 Now, if the value of the jth row (jth from the left) of the third column (the first one from the top) of the check matrix initial value table is expressed as hij, and will be checked The column number of the element of the jth i of the wth row of the matrix 表示 is expressed as ^^·, and then the 1st line of the line other than the l+3 6〇x(il) line of the matrix 检查 is checked. The number 11 of the element number can be obtained by the formula (1〇).

Hw.j=mod{hi)j+ mod((w-l), P)xq, M} (10) where 'mod(x, y) means the remainder after dividing y by x. Further, p is the number of rows of the above-described tour structure, and the specification of DVB_© S.2 is, for example, 360 as described above. Further, q is a value M/360 obtained by dividing the co-located length M by the number of rows P (= 360) of the unit of the tour structure. The check matrix generation unit 613 (FIG. 29) specifies the column number 0 of the element of the 1st + 36 〇 x (M) line of the check matrix 藉 by checking the matrix initial value table. Further, the check matrix generation The part 613 (圊29) obtains the column number Hw-j ' of the element 1 of the first row of the line other than the 1+36〇x(il) line of the inspection matrix H according to the equation (1〇) and generates The element of the column number obtained by the above is taken as the inspection matrix 1 of 1. However, dvB-C. 2, which is a specification for the next-generation CATV digital broadcast, is estimated to have a high coding rate of, for example, 2/3 to 9/10 and a modulation method such as 1〇24qAm or 4096QAM. In the case of a high coding rate or a multi-signal modulation method, generally, the communication path 13 (Fig. 7) is less tolerant to errors, and therefore countermeasures for improving the tolerance to errors should be applied. 135786.doc •78· 200937872 As a countermeasure to improve the tolerance to errors, for example, the replacement processing by the multiplexer 25 (Fig. 8). In the replacement process, as an alternative to replacing the code bit of the LDPC code, for example, the above-described first to fourth alternatives are provided, but the proposal is required to be more resistant to errors than the first to fourth alternatives. The way to improve it. Therefore, in the demultiplexer 25 (Fig. 8), as illustrated in Fig. 25, the replacement processing can be performed in accordance with the allocation rule. 〇 Hereinafter, the replacement processing according to the distribution rule will be described, and the replacement processing by the alternative method (hereinafter also referred to as the current method) which has been proposed will be described before. Referring to Fig. 60 and Fig. 61, the replacement processing in the case where the demultiplexer 25 assumes that the replacement processing is performed in the current manner will be described. Fig. 60 is a diagram showing an example of replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. That is, FIG. 60A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a code rate of 3/5, and a further modulation method is 16QAM, and the multiple b is 2, and the current mode is replaced. One example. In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the 16 signal points determined by 16QAM as one symbol. Further, when the code length N is 64,800 bits and the multiple b is 2, the memory 3 1 of the multiplexer 25 (FIG. 16, FIG. 17) contains 4x2 (= mb) bits in the horizontal direction. 8 vertical lines of the Yuan, memory 64800/(4x2) 135786.doc -79- 200937872 bits in the longitudinal direction. In the demultiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 3 1 , and if the writing of the 64800 bit code bit (1 code word) is finished, it is written in the memory 31. The code bits are read in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is configured to assign a code bit read from a 4x2 (= mb) bit of the memory 31, for example, as shown in Fig. 60A to a 4x2 (= mb) bit of 2 consecutive (= b) symbols. The meta-bit yG, yi, y2, y3, y4, y5, y6, y7i Ο mode replaces the code bits b〇 to b7 of 4x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol bit y4. The code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit ys, the code bit b5 is assigned to the symbol bit y3, and the code bit b6 is assigned to the symbol bit Y6, the code bit b7 is assigned to the symbol bit y〇, and is replaced. Fig. 60B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and a further modulation method is 64QAM, and the multiple b is 2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped as one symbol to any of the 64 signal points determined by 64QAM. 135786.doc -80. 200937872 0 Solution multiplex ^ Ma Chang NA 648G (H ^, in the case of multiples, recall 6 axe; memory 31 (Figure 16, 17) is contained in the horizontal direction of the record of the 12 vertical lines of the ' Longitudinal direction memory 64800/(4)) ❹

More than 1 m5, the code bit of the LDPC code is written in the vertical direction of the memory 31. If the writing of the 64-bit mbit (1 code word) is finished, the code bit written in the memory 31 is written. The element system is read out in the horizontal direction, in units of 6x2 (= mb) bits, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is a code bit b〇, b 丨, 匕 2, 1) 3, 1) 4, 1) 5, 1) 6, 137, 1) 8 which will be read from the memory. , 1) 9, 1) 丨 0 mountain 11, for example, as shown in Fig. 6〇3, the symbol of the 6x2 (=mb) bits of consecutive 2 (=b) symbols 丫〇 '71, 丫 2 '3' and 4, 丫5, 丫6, 丫7, 丫8, 丫9,71〇, 丫" way, replace 6><2(=1^) bits of code bits to b 1丨. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y, respectively, and assigns the m-bit b 1 to the symbol bit y7 and the code bit b2 to the symbol bit y3. The code bit b3 is assigned to the symbol bit y丨0, the code bit b4 is assigned to the symbol bit y6, the code bit b 5 is assigned to the symbol bit y 2 , and the code bit b6 is assigned to The symbol bit y9 assigns the code bit b7 to the symbol bit y5, and the code bit b8 to the symbol bit y, 135786.doc -81 · 200937872 assigns the code bit t>9 to the symbol The bit y8 assigns the megabyte b to the symbol y*, and assigns the Byte bn to the symbol ”, and replaces it. Figure 60C shows that the LDPC code has a code length n of 64,800. An example of the replacement processing of the current mode in the case where the LDPC code of the bit rate and the coding rate is 3/5 is further modulated by 256QAM and the multiple b is 2. When the modulation mode is 256QAM, the code bit is 8 The (=m) bit system is mapped to one of the 256 signal points determined by 256QAM for one character 7°. In the case of progress, the code length N is 64800 bits, and the multiple b is 2. , solution multiplexer 25 The memory 31 (Fig. 16, Fig. 17) contains 16 vertical lines of 8x2 (-mb) bits in the horizontal direction, and stores 648 〇〇 / (8 >< 2) bits in the wale direction. - In the multiplexer 25, the code bit of the LDPC code is written in the vertical direction of the memory 31, and if the writing of the 64800 bit code bit (the code word) is finished, it is written in the memory. The code bits of 31 are read in the horizontal direction, read in 8x2 (= mb) bit units, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is to be read from the memory 3128><; 2 (== mb) bit code _ o'bi'bs'bhbhbs'be'b^'bs'bs'bw'bH'b^babAb", for example, as shown in Figure 6〇c for consecutive 2 (=b) The symbol of the 8x2 (:=mb) bit of the symbol 疋y〇'y], y2, y3, y4, y5, y6, y7, y8, y9, y] 0, y", The yi2, yi3, yi4, yi5t* type replaces the code bits bG to b15 of the 8x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y丨5, respectively, and assigns the code bit b! to the symbol bit y, respectively, to assign the m-bit to the symbol bit y丨5, respectively. t > 2 is assigned to the symbol bit y 〗 3, the code bit element t > 3 is assigned to the symbol bit y3, the code bit element t > 4 is assigned to the symbol bit y8, and the code bit b5 is assigned to The symbol bit yn ' is assigned to the symbol bit y9, and the code bit b7 is assigned to the symbol bit y5.

The code bit b8 is assigned to the symbol bit y1(), the code bit b9 is assigned to the symbol bit y6, the code bit bi〇 is assigned to the symbol bit y4, and the code bit b丨 is assigned. The symbol bit y 7, the numerator b 12 is assigned to the symbol y 12 , the code bit b 13 is assigned to the symbol y 2 , and the modulo b 14 is assigned to the symbol y 14, the code bit b 15 is assigned to the symbol bit y 〇 and replaced. Fig. 61 is a diagram showing an example of a replacement process of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. That is, FIG. 61A shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5 and a further modulation method is 16qam and a multiple b is 2. . In the case where the modulation method is 16QAM, the 4 (=m) bits of the code bit are mapped to one of the signal points determined by 16QAM as one symbol, 135786.doc • 83· 200937872. In the case of the step, the code length N is 16,200 bits, and in the case of the multiple bg2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains the memory 4x2 (= mb) bits in the horizontal direction. The 8 vertical lines store ΐ62〇〇/(4χ2) bits in the longitudinal direction. " In the multiplexer 25, the code bit of the LDPC code is written in the wale direction of the memory 31, and if the writing of the 16200 bit code bit (1 code word) is finished, it is written in the memory The code bits of 31 are read in the horizontal direction, read in the 4x2 (= mb) bit \\ position, and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is a code bit b〇, b丨, 1^2, 1) 3, 1) 4, 135, 1) which is read from the 4><2 (=1111) bits of the memory 31. 6,1)7, for example, the symbol bits yG, yi, y2, y3, y4, y5, y6 assigned to 4x2 (= mb) bits of consecutive 2 (=1) symbols as shown in Fig. 61. , y< mode, replacing the 4x2 (= mb) bit of the code bit b〇 to Bu. That is, the replacing unit 32 assigns the code elements bG to by to the symbol bit 7 as in the case of the above-described Fig. 60A. Replace to 77. φ Fig. 61B shows an example of the replacement processing of the current mode in the case where the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3/5, and a further modulation method is 64QAM and a multiple of ba2. In the case where the modulation method is 64QAM, the 6 (=m) bits of the code bit are mapped to one of the 64 signal points determined by 64QAM as one symbol. Further, when the code length N is 16,200 bits and the multiple b is 2, the memory 31 of the multiplexer 25 (Fig. 16, Fig. 17) contains 6x2 (= mb) bits in the horizontal direction. 12 vertical lines, memory 162〇〇/(6χ2) in the longitudinal direction 135786.doc • 84 - 200937872 bits " in the solution of the multi-guard 25, the code bits of the LDPC code are written in the memory 31 In the traverse direction, if the 162 〇〇 之 码 字 ) 终 则 则 & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & & It is supplied to the replacement unit 32 (Fig. 16 and Fig. 17 is a replacement unit 32 for assigning a code bit _ from the memory of the memory 31 to the < 2 (=1^) bit, for example, as shown in Fig. 61B to the continuous 2 ('Function of the symbol "2 (= called bit element symbol bit © y〇'yi'y2'y3'y4, y5, yG7, y8, y9, y1〇, yil way, replace 6x2 (= mb The code bits bG to bu are the same. In other words, for the case of the (4) 32 series, the code bits 兀 and 匕 are assigned to the symbol bits y, and are replaced. Fig. 61C shows The LDPC code is an LDPC code with a code length of _62 bits and a coding rate of 3/5. The modulation method is 256 _, an example of the replacement processing of the current mode in the case of multiple (4). In the case where the G-wide mode is 256QAM, the bits of the code bit are mapped to 256QAM by one, and one symbol. For any of the 256 signal points determined, the code length N is 16,200 bits, and the multiples b*!, the memory 31 of the multiplexer 25 (@16, Fig. 17) is included in the course. Direction note:::(=, 8 vertical lines of bit, memory in the direction of the vertical direction (10). ·]) multiplexer 25, the code bit of the LDPC code is written in the memory (4) to the vertical (or) (6) 00 bit The end of the writing of the meta-coded bit code of the element is written as I35786.doc -85- 200937872. The code bit in the memory 3 1 is in the horizontal direction, in units of 8 x 1 (= mb). The readout is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is a code bit boAbbhbhbobhl^, which is read from the 8x1 (= mb) bit of the memory 31, for example, as shown in Fig. 61C. The way to allocate the 8xl (= mb) bits of the symbol (1, 丫 2, 丫 3, 丫 4, ) ^ 5, 丫 6, 77 assigned to l (= b) symbols 8 X1 (= mb) bits of code bits b〇 to b7. That is, the replacement unit 32 Do not assign the parity bit b〇 to the symbol bit y7, 分配 assign the code bit b to the symbol bit y3, assign the code bit b2 to the symbol bit yi, and assign the code bit b3 to The symbol bit y 5 assigns the code bit t>4 to the symbol bit y2, the code bit b5 to the symbol bit y6, and the code bit 1)6 to the symbol bit y4. The code bit b7 is assigned to the symbol bit y〇 and replaced. 〇 Next, explain the replacement process according to the distribution rule (hereinafter also referred to as the replacement process of the new replacement method). 62 to 64 are diagrams illustrating a new alternative. In the new alternative, the replacement unit 32 of the demultiplexer 25 replaces the code bits of the mb bits in accordance with a predetermined allocation rule. The allocation rule is a rule for assigning the code bits of the LDPC code to the symbol bits. The allocation rule stipulates that the combination of the code bit group of the code bit element and the symbol bit group of the symbol bit element of the code bit element of the code bit group is 135786.doc -86 - 200937872 a set of groups; and a code bit group of the group set, and a code bit of the symbol bit group and a bit number of the symbol bit (hereinafter also referred to as a group bit number). Here, the code bit system is as described above, and there is a difference in the error probability, and the symbol bit is also different in the error probability. The code bit group is grouped according to the error probability to distinguish the groups of code bits, and the symbol bit group is grouped according to the error probability to distinguish the group of symbol bits. Fig. 62 is a diagram showing that the LDPC code is a code length >! is 162 bits, and the coding rate is 2/3 ® 1〇1> (: code, further modulation is 1024QAM, and the multiple b is 1. The code bit group and the symbol bit group. In this case, the code position of the 1〇xl (== mb) bit read from the memory 31 is based on the difference in error probability, as shown in Fig. 62A. The group shown can be divided into 4 code bit groups 〇131, 0匕2, 〇1)3, 〇134. Here, the code bit group Gbi is a group in which the subscript i is smaller, and the error probability of the code bit belonging to the code bit group Gbj is better (smaller). In FIG. 62A, respectively, the code bit group Gbi is the code bit %, and the ® code bit group Gbz is the code bit 1?1,1?2,153,1)4,135 belongs to, code The bit group Gbs is a code bit element belonging to the 'code bit group Gh code bit genus. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the 1〇xl (=mb) bit are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 62B. Metagroups Gyi, Gy2, Gy3, Gy4, Gy5. Here, the 'symbol bit group Gyi is the same as the code bit group, and the smaller the subscript i is, the more the error probability of the symbol bit belonging to the symbol bit group Gy i is 135786.doc •87 200937872 Good group. In FIG. 62B, respectively, the symbol bit group ^... is a symbol bit bit, and the symbol bit group Gyz is a symbol element belonging to the seventh bit, and the symbol bit group Gy; The bit element belongs to, the symbol element group Gy4 is a symbol element y6, y? belongs to, the symbol element group Gys is a symbol element 78, and 丫9 belongs. Fig. 63 is a diagram showing an allocation rule in the case where the LDPC code is an LDPC code having a code length of N*162 bits and a coding rate of 2/3, and the modulation method is 1〇24QAM, and the multiple ^^ is i. In the allocation rule of Fig. 63, the combination of the code bit group Gbl and the symbol bit group Gys is defined as one group set. Then, the number of group bits of the group set is defined as 1 bit. Here, the group set and its group bit number are collectively referred to as group group information. Then, for example, a group set of the code bit group Gbl and the symbol bit group Gy5, and a group bit number of the group set, that is, 1 bit, are described as group set information (Gb^Gy^ l) » In the distribution rule of Figure 63, in addition to the group collection information, group collection information (Gb2, Gy丨, 2), (Gb2, Gy2, 2), (Gb2, Gy3, l), ( Gb3, Gy4, l), (Gb4, Gy3, l), (Gb4, Gy4, l), (Gb4, Gy5, l). For example, the group collection information (〇1?1, 〇75, 1) means that 1 bit of the code bit belonging to the code bit group Gb! is assigned to the symbol belonging to the symbol bit group Gy. 1 bit of the bit. Therefore, the allocation rule in Fig. 63 is defined as follows: According to the group set information (Gb^Gy^l) '1 bit of the code bit of the error probability first good maze group Gb! The probability of error is 5th 135786.doc • 88 - 200937872 The 1st bit of the symbol of the good (worst) symbol group Gys; according to the group collection information (Gb^GyiJ), the probability of error 2 2 bits of the code bit of the good code bit group Gt>2, allocated to the 2 bit of the symbol bit of the first good symbol bit group Gyi of the error probability; (Gb2, Gy2, 2), assigning the 2 bits of the code bit of the second good symbol bit group Gbz of the error probability to the symbol bit of the second good symbol bit group Gy2 of the error probability 2 bits; according to the group set information (Gb2, Gy3, l), the 1st bit of the code bit of the 2nd good code bit group Gt>2 of the error probability is assigned to the error probability 3rd 1 bit of the symbol element of the good symbol element group Gy3; according to the group set information (Gb^Ghj), the code bit of the 3rd good code bit group Gt> 1 The element is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (Gb>4, Gy3, l), the error probability is 4th good. One bit of the code bit of the code bit group Gb4 is assigned to one bit of the symbol bit of the third good symbol bit group of the error probability; 〇 according to the group set information (Gt > 4, Gy4, 1), assigns 1 bit of the code bit of the 4th good code bit group Gin of the error probability to the symbol bit of the 4th good symbol bit group Gy* of the error probability. Bits; and according to the group set information, assign the 1st bit of the imaginary bit of the 4th good code bit group Gb>4 of the error probability to the 5th good symbol bit group Gy5 of the error probability One bit of the symbol bit. As described above, the code bit group is grouped according to the error probability to group the code bit groups, and the symbol bit group is grouped according to the error probability to group the symbol bits 135786.doc -89- 200937872 group. Therefore, the allocation rule can also be said to combine the error probability of the specified code bit with the error probability of the symbol bit to which the code bit is assigned. Thus, the allocation rule for specifying the combination of the error probability of the code bit element and the error probability of assigning the symbol bit of the code bit element is determined by improving the tolerance to the error by, for example, measuring the BER simulation or the like (for Tolerance of noise). In addition, even if the allocation of the code bits of a certain code bit group is changed in the bit of the same symbol bit group, (almost) does not affect the resistance to errors. Therefore, in order to improve the tolerance to errors, the group set information of the BER (Bit Error Rate) is specified, that is, the code bit group of the specified code bit group and the code bit group are allocated. The combination of the symbol group of the symbol bit of the group of code bits (group set), the code bit group of the group set, and the code bit and the character of the symbol bit group respectively The number of bits of the meta-bit (group bit number), as an allocation rule, assigns a code bit to the symbol bit according to the allocation rule to replace the code bit. ® Among them, according to the allocation rule, the specific allocation method of which code bits are assigned to which symbols must be determined before the transmitting device 11 and the receiving device 12 (Fig. 7). Figure 64 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 63. That is, FIG. 64A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the further modulation method is 1024QAM, and the multiple b is 1, and the allocation rule according to FIG. 63 is used. The first example of the replacement of the code bit. 135786.doc -90- 200937872 LDPC code is code length N is 16200 bits, coding rate is 2/3iLDpc code, further modulation mode is 1024QAM, multiple case, in solution multiplexer 25, in the longitudinal direction X The code direction written by the memory 31 of the (162〇〇/(ι〇χΐ))χ(ι〇χΐ) bit is in the horizontal direction, in the order of l〇xl (= mb) bits. It is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits bQ to h of the l〇x1 (= mb) bits read from the memory 3 according to the allocation rule of FIG. 63, for example, as shown in FIG. 64A to © l (=b) The symbol bits of the symbol 〇xl (= mb) bits are ... to replace the code bits bQ to b9 of the l 〇 xl (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 8, respectively, assigns the m-bit b 1 to the symbol bit y, and assigns the code bit b2 to the symbol y.丨, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit bs is assigned to the symbol bit y4, and the code bit be is assigned to the symbol The bit y6 assigns the code bit b7 to the symbol bit y5, assigns the m-bit bg to the symbol bit y9, and assigns the code bit b9 to the symbol bit to be replaced. 64B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and the modulation method is i〇24QAM, and the multiple 1 is 135786.doc •91 - 200937872 in the case of i. The second example of replacement of the code bits according to the distribution rule of FIG. 63. According to Fig. 64B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 63: Bit bG is assigned to symbol bit y9, code bit b! is assigned to symbol bit y 2, code bit b2 is assigned to symbol bit y3, * code bit b3 is assigned to symbol bit Element y 1, © assigns code bit b4 to symbol bit ys, assigns code bit b5 to symbol bit y, assigns bit b6 to symbol y7, and w1 Assigned to the symbol bit y4, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. Here, the code bit bj shown in Figs. 64A and 64B is assigned to the symbol bit yj in accordance with the allocation rule of Fig. 63 (according to the allocation rule). ® Figure 65 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3. The further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the 10X 1 (= mb) bits read from the memory 3 1 are group-divided into 4 code bit groups according to the difference in error probability as shown in FIG. 65A. Gbl, Gb2, Gb3, Gb4. In FIG. 65A, respectively, the code bit group Gbi is the code bit b〇, the code bit group Gb2 is the code bit b! to b5, and the code bit group Gb3 is the code 135786.doc -92- 200937872 The bit ben belongs to, and the code bit group Gb4 is the code bit element to the heart. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 65B. The meta group (^1, (^2, (^3, (^4, (^5. in Fig. 65B' is the same as Fig. 62B, respectively, the symbol bit group Gy, the symbol bit bit belongs to , symbol element group Gy2 symbol element y2, y3 belongs to the 'character bit group Gy3 system symbol element y4, y5 belongs., symbol element group Gy* system symbol element y0 , y7 belongs to, the symbol element group Gy5 is a symbol element ❹, y9 belongs to Fig. 66 shows that the LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 2/3, further modulating The method is 1〇24qAM, the allocation rule in the case of multiples. In the allocation rule of Figure 66, group group information (Gb2, Gy1, 2), (Gb2, Gy252), (Gb2, Gy3, l) is specified. 5 (Gb3, Gy4, l), (Gb4, Gy3, l), (Gb4, Gy4, l), (Gb4, Gy5, l). That is, the allocation rules in Fig. 66 are as follows: ® according to the group Set information (GbbGy^l) 'Assign the error probability to the 1st good code bit group Gb丨 of the code bit The probability 5th good symbol group Gy5 symbolic bit 1 bit; according to the group set information (Gl> 2, Gyi, 2), the error probability 2nd good code bit group Gh The 2 bits of the megabyte are assigned to the 2nd bit of the symbolic component of the error probability yth; the group of information (Gb2, Gy2, 2) will be wrong. Probability 2nd good maze 7C group G b2 code position 7〇 2 digits το, assigned to the error probability 2nd good 135786.doc -93· 200937872 Good symbol meta-group Gy2 symbolic bit 2 bits; according to the group set information (Gb2, Gy3, l), assign 1 bit of the code bit of the second good code bit group Gb2 of the error probability to the symbol 3 of the error probability One bit of the symbol bit of the bit group Gy3; according to the group set information (Gb3, Gy4, l), the one bit of the code bit of the third bit of the error bit group Gb3 of the error probability, Assigned to the 1-bit of the symbol bit of the fourth-perfect symbol group Gy4 of the error probability; according to the group set information (Gb4, Gy3, l), the error probability is the fourth best © code bit group Group Gb4 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability; according to the group set information (Gb4, Gy4, l), the error probability is 4: 1 bit of the code bit of the good code bit group Gb4, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and according to the group set information ( Gb4, Gy5, l), assigning 1 bit of the code bit of the 4th good code bit group Gb4 of the error probability to the symbol bit of the 5th good symbol bit group Gy5 of the error probability 1 bit. ® Figure 67 is an alternative representation of the code bits in accordance with the allocation rules of Figure 66. That is, FIG. 67A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 1024QAM, and the multiple b is 1 according to the allocation rule of FIG. 66. The first example of the replacement of the code bit. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25 is disposed in the X direction of the traversing direction. The direction is (64800/(10xl))x(10xl) 135786.doc -94- 200937872 The memory of the bit 3 1 is written in the direction of the queue, in l〇xl (= mb) bit unit It is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the code bits bQ to h read from the l〇x1 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. 66, for example, as shown in FIG. 67 and assigns U=b) symbols. The i10x1 (= rnb) bit symbol bit % to is replaced by the code bit b() to b9 of the l〇xl (= mb) bit. That is, the replacing unit 32 assigns the code bit bQ to the symbol bit y 8, respectively, assigns the code bit bi to the symbol bit y, and assigns the code bit b2 to the symbol yi, The code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y 3 , the code bit b5 is assigned to the symbol bit y4 , and the code bit b6 is assigned to the symbol bit Y6, the code bit b7 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. 67B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3. The further modulation method is i〇24QAM, and the multiple b is 1, and the code according to the allocation rule of FIG. 66 is used. The second example of the replacement of the bit. According to FIG. 67B, the replacement unit 32 is based on the allocation rule of FIG. 66, and the code bits bG to b9 of 1 〇X 1 (= mb) bits read from the memory 3 1 are divided into 135786.doc • 95. - 200937872 Do not replace the following: assign code bit b〇 to symbol bit y9, assign code bit 1^ to symbol bit y2, and assign code bit b2 to symbol bit 丫3, Assigning the drink bit b3 to the symbol bit y 1, assigning the code bit b4 to the symbol bit y5, assigning the code bit b5 to the symbol bit y, and assigning the code bit b6 to the symbol The bit y7 assigns the code bit b7 to the symbol bit y4, the code bit b8 to the symbol bit y8, and the code bit bp to the symbol bit y6. Figure 68 is a diagram showing that the LDP C code is a code bit group of 16200 bits and an encoding rate of 3/4. The further modulation method is i〇24QAM, and the multiples b is 1 Meta-bit group. In this case, the position of the 1 〇X 1 (= mb) bit read from the memory 3 1 is grouped into 4 code bit groups according to the difference in error probability as shown in FIG. 68A. Groups 0131, 0132, 0153, 0154. In FIG. 68A, respectively, the code bit group 〇1>1 is the code bit bQ, the code bit group Gt>2 is the code bit b! to b6, and the code bit group Gb3 is coded. The bit b7 belongs to, and the code bit group Gb4 belongs to the code bits b8 and b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol bits as shown in FIG. 68B. Metagroups Gyi, Gy2, Gy3, Gy4, Gy5. 68B, as in FIG. 62B, respectively, the symbol bit group Gy 135786.doc 96- 200937872 is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit group. , the symbol element group Gys is a symbol element bit, the symbol element 3 group Gy* is a symbol element y0, y7 belongs to, the symbol element group is a symbol element ys, y9 belongs. Fig. 69 is a diagram showing an allocation rule in the case where the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3/4, and a further modulation method is 1〇24QAM, and the multiple 1 is 1. In the distribution rule of Figure 69, there is a group set information® (Gb25Gyi52), (Gb2, Gy2, l), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3jGy2, l), (Gb4 , Gy4, l), (Gb4, Gy5, l). That is, the allocation rule in Fig. 69 is defined as follows: According to the group set information (Gbi, Gy4, l), the 1st bit of the code bit of the error probability i-th good code bit group Gb is allocated. Give the bit error of the 4th good symbol group Gy* of the error probability bit bit; according to the group set information (Gt>2, Gyi, 2), the error probability is 2nd good _ code bit The 2-bit of the code bit of the meta-group Gb:j is allocated to the 2-bit of the symbol bit of the symbol i-good symbol group Gy!; according to the group set information (Gl>2 , Gy2, l), assigning the 1-bit ' of the code bit of the second good code bit group Gb>2 of the error probability to the symbol bit of the second good symbol bit group Gy2 of the error probability 1 bit; according to the group set information (Gb>2, Gy3, 2) 'Assign the 2 bits of the code bit of the second good code bit group Gb2 of the error probability to the third probability of error probability 2 bits of the symbol bit of the symbol group Gy3; according to the group set information (Gb2, Gy5, 1), the error probability is the second best 135786.doc -97- 200937872 code bit group Gh Code 1 bit of the bit, assigned to the 1st bit of the symbol bit of the error probability $th good symbol bit group Gy5, according to the group set information (Gb^Ghl), the error probability is 3rd good 1 bit of the code bit of the code bit group Gh is assigned to the 1st bit of the symbol bit of the second good symbol group Gyz of the error probability; according to the group set information (Gb^Gy ^l) '1 bit of the code bit of the 4th good code bit group Gh of the error probability is assigned to 1 bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability And according to the group set information (〇1) 4, 〇 75, 1), assign the bit position of the code bit of the error probability 4th good code bit group GW to the error probability 5th good The unit of the symbol bit of the symbolic group Gys. Figure 70 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 69. That is, FIG. 70A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 1〇24qAM, and the multiple b is 1 according to FIG. 69. The first example of the replacement of the code bits of the allocation rule 0 LDPC code is an LDPC code with a code length N of 1 6200 bits and a coding rate of 3/4, and further modulation mode is 1024QAM, and the multiple ^ is 丄The code locator written by the multiplexer 25' in the direction of the X direction of the multiplexer (162 〇〇 / (1 〇χ (l 〇 xl) bits) is in the course direction. Read out in l〇xl (= mb) bit units and supply it to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 3 2 reads out from the memory 3 according to the allocation rule of Fig. 69. The code bits bQ to bp of the xl (= mb) bits are allocated to 135786.doc • 98 - 200937872 l (= b) symbols i 〇 xl (= mb) bits as shown in Fig. 7 〇 a The symbol bit is ... to replace the code bit % to b9 of the l〇xl (= mb) bit. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, respectively, The code bit b] is assigned to the symbol bit y4, and the code bit b2 is assigned to the symbol bit y8. The m-bit b3 is assigned to the p-bit y5, the code-bit b4 is assigned to the p-bit y0, 码 the code-bit b5 is assigned to the p-bit y2, and the code-bit 1) is assigned to the symbol The bit y is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. The LDPC code is an LDpC code with a code length N of 16,200 bits and a coding rate of ❾ 3/4. The further modulation mode is 1024QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. 69 The second example is replaced. According to FIG. 70B, the replacement unit 32 performs the allocation rules of FIG. 69 for the code bits % to b9 of the l〇xi (= mb) bits read from the memory 31, respectively. The following replacement: assigning the code bit bG to the symbol bit y7, assigning the code bit bi to the symbol bit y9, assigning the mbit b2 to the symbol bit y4, and assigning the code bit b3 to The symbol bit y!, 1357E6.doc 200937872 assigns the code bit b4 to the symbol bit y5, the code bit b5 to the symbol bit y〇, and the code bit b6 to the symbol bit y2 , will be the code position B7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. Fig. 71 shows that the LDPC code has a code length N of 64800 bits, The LDPC code with a coding rate of 3/4 is further modulated by 1024qAM, and the code bit group and the symbol bit group in the case of multiple bg! In this case, the code bits of the l〇x1 (= mb) bits read from the memory 31 are grouped into 4 code bit groups as shown in FIG. 71A according to the difference in error probability. ?1,01)2,0133,01)4. In Figure 7 1 A 'respectively' the code bit group 〇1?1 code bit b0 belongs, the code bit group Gbz is the code bit ratio to ^^ belongs, the code bit group Gb3 code The bit by belongs to, and the code bit group Gb4 is associated with the code bits 158 and 1>9.调 When the modulation mode is 1024QAM 'When the multiple b is 1, the symbol of the i〇xi(=mb) bit is based on the difference in error probability, and can be grouped into 5 symbols as shown in Fig. 71β. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 71B, as in FIG. 62B, respectively, the symbol bit group belongs to the symbol bit, the symbol bit group Gy2 is the symbol bit y2, y3 belongs to, and the symbol bit group Gya belongs to The symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element ye, y7 belongs to, the symbol element group Gy5 is the symbol element ys, y9 belongs. Figure 72 is a diagram showing that the LDPC code is an LDPC code having a code length of 648 bits and a coding rate of 3/4 135786.doc -100. 200937872, and the modulation is further modulated by 1024QAM, and the multiple b is 1. rule. The allocation rule in Fig. 72 specifies group information (GbbGy^l), (Gb25Gy1, 2), (Gb2, Gy2, l), (Gb2, Gy3, 2) 5 (Gb2, Gy5, l), ( Gb3, Gy2, l), (Gb4, Gy4, l), (Gb4, Gy5, l). That is, the allocation rule in FIG. 72 is defined as follows: According to the group set information (Gbi, Gy4, l) 'Assign 1 bit of the code bit of the first good code bit group Gb 1 of the error probability' Give the error probability the fourth good Ο Ο Ο Ο Ο G G G G G G ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The 2 bits of the code bit of the group Gb2 are assigned to the error probability [2 bits of the symbol element of the good symbol bit group Gyi; according to the group set information (Gbz, Gy2, l), Error probability 2nd good code bit group Gb2 code bit 1 bit 'as assigned to error probability 2nd good symbol bit group Gy2 symbol bit 1 bit; ❹ According to group Aggregate information (Gt > 2, Gy3, 2) 'Assign the 2 bits of the code bit of the 2nd good code bit group Gh>2 of the error probability to the 3rd good symbol bit group of the error probability 2 bits of the symbol element of Gy3; according to the group set information (Gb2, Gy5, l) 'Assign the error probability to the 1st bit of the code bit of the 2nd good horse bit group Gh, to the wrong The probability 5th good symbol bit group Gy5 is 1 bit of the symbol bit; according to the group set information (Gb3, Gy2, l), the error probability 3rd good code bit group Gb>3 The 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 2nd good symbol bit group Gy2 of the error probability; 135786.doc -101 - 200937872 According to the group collection information (Gtu'Gy ^l), assigning 1 bit of the code bit of the 4th good code bit group Gb>4 of the error probability to the symbol bit of the 4th good symbol bit group Gy* of the error probability 1 bit; and according to the group set information (Gb>4, Gy5, l), the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is assigned to the error probability 5th good The unit of the symbol bit of the symbolic group Gys. Figure 73 is a diagram showing an alternative of the megabits according to the allocation rule of Figure 72. That is, Fig. 73A shows that the LDPC code is an LDPC code having a code length n of 64,800 bits and a code rate of 3/4, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to Fig. 72. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an ldpc code having a code length N of 64,800 bits and a coding rate of 3/4. In the case where the modulation method is 1024QAM and the multiple bgi, the multiplexer 25 is in the direction of the X direction in the wale direction. (648〇〇/(1〇χΐ))χ (1 0 X 1) bit memory 3 1 written code bits are in the horizontal direction, read in 1〇Xl (= mb) bit units And supplied to the replacement unit 32 (FIG. 16, FIG. V17). The replacement unit 32 reads the code bits bG to h from the l〇x1 (=mb) bits of the memory 31 in accordance with the allocation rule of FIG. For example, as shown in FIG. 73A, the symbol bits assigned to U=b) symbols 21〇xl (=mb) bits are replaced by the code bits bG to b9 of the l〇xl (=mb) bits. . That is, the replacing unit 32 assigns the megabyte b 给 to the symbol y6, and assigns the megabyte b 1 to the symbol y4, 135786.doc • 102- 200937872 assigns the code bit b2 to The symbol bit y8 assigns the code bit b3 to the symbol bit y5, the code bit b4 to the symbol bit y, and the code bit b5 to the symbol y2, and the code bit B6 is assigned to the symbol bit y丨, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7.

And replace it. 73B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and further modulation is 1024QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 73B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the l〇x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 72: The bit bG is assigned to the symbol bit y7, the code bit bi is assigned to the symbol bit y 9, the code bit b2 is assigned to the symbol bit y4, and the code bit b3 is assigned to the symbol bit y !, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y〇, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol The bit y3 assigns the code bit b8 to the symbol y8, 135786.doc -103· 200937872 assigns the code bit b9 to the symbol bit ". Figure 74 shows that the LDPC code is the code length > For a 162-bit LDPC code with a coding rate of 4/5, the further modulation method is 1〇24QAM, and the code bit group and the symbol bit group in the case of multiples. In this case, The code bits 〇* of the 21〇xl (=mb) bits read by the memory 31 are grouped into three code bit groups Gb, Gb2, Gb3 according to the difference in error probability as shown in FIG. 74A. In Figure 74A, respectively, the code bit The group is called the code bit to ^ is the genus 'code bit group is still 2 code bit ^ belongs, the code bit group is called the code bit b8 and b9 belongs. The modulation mode is 1〇24QAM, multiple 1 In the case of 1, the 〇 xi (= mb) bit symbol bit is based on the difference in error probability, as shown in FIG. 74B, the group can be divided into 5 symbol bit groups Gy, such as you. In Fig. 74B, in contrast to Fig. 62B, respectively, the symbol bit group μ 兀 TG TG ' ' TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG TG The symbol element group Gy3 is represented by the symbol element (4), the symbol element group Gy4_ meta-bit y6, y7 belongs to, the #元位元巧5-character element ys, y9 belongs. The round 75 series table 7FLDPC code is a 16-bit code, the coding rate is still LDPC code, and the further modulation method is 1〇24QAM, and the allocation rule in the case of multiples is as shown in Fig. 75. Group collection information (Gbl, Gyi, 2), (Gb1, Gy2, l), (Gb1, Gy3, 2) J (Gb1, Gy4, 1) 5 (GbijGy5) 1)} (Gb2j^ (Gb3, Gy4, l), (Gb3, Gy5, l) 〇 135786.doc -104. 200937872 That is, the distribution rules in Figure 75, The following is as follows: According to the group collection information (Gb, Gyi, 2) 'Assign the error probability to the best < 2 bit of the code bit group Gb!' to the error probability 1st ^ The bit position of the meta-bit group Gy! is 2 bits; according to the group set information (Gb^Gy^l), the code probability of the error probability 丄良良#< code bit group Gb! 1 bit, assigned to 1 bit of the symbol bit of the error probability 2nd good symbol bit group Gy2;

❹ According to the group set information (Gb^Gy^) 'Assign the error probability i-th good code bit group Gb, the 2-bit code bit is assigned to the error probability third good symbol bit group 2 bits of the symbol element of Gy3; according to the group set information (Gbi, Gy4, l) 'Assign the error probability 1st good code bit group Gb, 1 bit of the code bit to Error probability 4th good symbol group Gy4 symbol bit 1 bit; according to group set information (Gb), Gy5, l), the error probability i is good code group Gl ^1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy 5 of the error probability; according to the group set information (Gb^Gy^l), The bit of the code bit of the second good code bit group Gbz of the error probability is assigned to the 1-bit of the symbol bit of the second good symbol bit group Gyz of the error probability; The information (Gb3, Gy4, l) assigns the unit of the code bit of the 3rd good code bit group Gh of the error probability to the symbol of the 4th good symbol group Gy* of the error probability. 1 bit of bit And according to the group set information (Gb^Gy5, 〗), assign the error bit of the code bit of the third good symbol bit group Gh to the error probability. 5 135786.doc -105· 200937872 Good One bit of the symbol bit of Gys. Figure 76 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 75. That is, FIG. 76A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the allocation rule. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 1024QAM and the multiple b is 1, the multiplexer 25 is in the traverse direction x. The code bit written in the memory 31 of the direction (162〇〇/(1〇χ1))χ(l〇xl) bit is in the course direction, and is read out in l〇xl (=mb) bit units. And supplied to the replacement unit 32 (FIG. 16, FIG. 17). The replacing unit 32 assigns the code bits read from the 1 〇 x 1 (= mb) bits of the memory 31 to bp ' according to the allocation rule of FIG. 75, for example, as shown in FIG. 76A to U=b) symbols. I〇xi (= mb) bit symbol bit... to replace the code bits b〇 to b9 of l〇xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y6, assigns the m-bit b! to the symbol bit y 4, and assigns the code bit b2 to the symbol bit y 8, respectively. The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y 〇, the megabyte b5 is assigned to the symbol y2, and the code bit 1 > 6 is assigned to the symbol The meta-bit y!, 135786.doc -106- 200937872 assigns the code bit b7 to the symbol bit y3, the code bit b8 to the symbol bit y9, and the code bit b9 to the symbol bit Y7, and replace it. 76B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and further modulation is 1024QAM, and when the multiple b is 1, the code bit according to the allocation rule of FIG. 75 is used. The second example of replacement. According to FIG. 76B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10 X 1 (= mb) bits read from the memory 3 1 in accordance with the allocation rule of FIG. 75: The code bit bG is assigned to the symbol bit y9, the code bit bi is assigned to the symbol bit y 7, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Element y 1, assigning code bit b4 to symbol bit y5, assigning code bit b5 to symbol bit y〇, w assigning code bit b6 to symbol bit y4, and using code bit b7 The symbol bit y2 is assigned, the code bit b8 is assigned to the symbol bit y8, and the code bit b9 is assigned to the symbol bit y6. 77 is a diagram showing that an LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code position 135786.doc • 107· 200937872 of the l〇xl (= mb) bit read from the memory 31 is grouped into 3 according to the difference in error probability as shown in FIG. 77A. One code bit group GbhGbhGbs. In Fig. 77A', respectively, the code bit group 〇1>1 is the code bit bG, the code bit group Gb>2 is the code bit b! to b7, and the code bit group Gb3 is coded. Bits b8 and b9 belong. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the i〇xi(=mb) bit are different according to the error probability. As shown in FIG. 77B, the group can be divided into 5 symbol bits. Metagroups Gy丨, Gy2, Gy3, Gy4, Gy5. In Fig. 77B, which is the same as Fig. 62B, respectively, the symbol element group Gy! is represented by the 'character bit group Gy2, the symbol bit y2, and the y3 belongs to the 'symbol bit The group Gy3 is a symbol element y4, y5 belongs to, the symbol element group Gy4 is a symbol element y6, y7 belongs to, and the symbol element group Gy5 is a symbol element y%y9 belongs to. Fig. 78 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method of 1024QAM and a multiple b of 1. ◎ The distribution rule in Figure 78 specifies group information (Gb2, Gylj2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3, Gy4, l) ), (Gb3, Gy5, l) °, that is, the allocation rule in Figure 78, as follows: According to the group set information (Gb, Gy4, l), the error probability first good code bit group Gb The 1 bit of the code bit is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb2, Gy!, 2), The probability of error is the second best 135786.doc •108·200937872 The 2-bit element of the code bit group Gb2 is assigned to the symbol bit of the first good symbol group Gy! 2 bits; according to the group set information (Gb2, Gy2, 2), the 2 bits of the code bit of the second good code bit group Gb2 of the error probability are assigned to the second good symbol bit of the error probability. 2 bits of the symbol element of the meta group Gy2; according to the group set information (Gb2, Gy3, 2), the 2 bits of the code bit of the second good code bit group Gb2 of the error probability are allocated Give the symbol probability of the third good symbol group Gy3 of the error probability 2 bits of the element; © according to the group set information (Gb2, Gy5, l), the 1st bit of the code bit of the 2nd good code bit group Gb2 of the error probability is assigned to the error probability 5th good 1 bit of the symbol bit of the symbol group Gy5; 1 bit of the code bit of the 3rd good code bit group Gb3 of the error probability according to the group set information (Gb3, Gy4, l) Yuan, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; and the 3rd good code bit of the error probability according to the group set information (Gb3, Gy5, l) The 1-bit of the code bit of the meta-group Gb3 is assigned to the 1-bit of the symbol bit of the error probability 5 ® good symbol bit group Gy5. Figure 79 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 78. That is, FIG. 79A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and the further modulation method is 1024QAM, and the multiple b is 1 in accordance with the allocation rule of FIG. The first example of the replacement of the code bit 0 LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 4/5, and further modulation mode is 1024QAM, and the multiple b is 1, 135786.doc -109- 200937872 The multiplexer 25' is written in the direction of the wales in the direction of the horizontal direction (64800/^ 〇χ (l〇xl) bits of the memory 31 written in the horizontal direction, to The 〇xl (= mb) bit unit is read and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads the 10><1 from the memory 31 in accordance with the allocation rule of Fig. 78. = !1113) The bit position of the bit 1)() to 159, for example, the symbol bit assigned to the l〇xl(=mb) bit of l(=b) symbols as shown in Fig. 79. To replace the code bits bG to b9 of l〇xl (= mb) bits. © that is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 6, respectively, and assigns the code bit b 1 to the symbol bit y 4 and the code bit b2 to the symbol bit. y 8, assign code bit b3 to symbol bit y5, assign code bit b4 to symbol bit y 〇, assign code bit b5 to symbol bit y2, and code bit 1) Assigned to the symbol bit yi, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7 for replacement. . 79B is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5. The further modulation method is 1〇24qam, and the multiple b is 1 according to the distribution rule of FIG. The second example of replacement of code bits. According to FIG. 79B, the replacing unit 32 is in accordance with the allocation rule of FIG. 78, and the code bits ❶ 135786.doc • 110· 200937872 are read from the memory 31 by the code bits b❶ to b of 1〇xl (= mb) bits. The following substitutions are made: the knife assigns the code bit bG to the symbol bit y7, the code bit b! to the symbol bit yi, and the code bit t>2 to the symbol bit y3. The code bit I)3 is assigned to the symbol bit y4, the code bit I)4 is assigned to the symbol bit y 5 , and the code bit b5 is assigned to the symbol bit y 〇, ® the code bit B6 is assigned to the symbol bit y 2, the code bit b7 is assigned to the symbol bit y 9, the code bit b8 is assigned to the symbol bit y 8, and the code bit b9 is assigned to the symbol bit y6 . 80 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and a further modulation method is 1〇24QAM, and a multiple of 1) is a code bit group and a symbol. Meta-bit group. In this case, the code bits of the 1〇x1 (=mb) bit read from the memory 31 are group-divided into 4 code bit groups according to the difference in error probability as shown in FIG. 80A. GbhGbzAbsAN. 80A, respectively, the code bit group Gbi belongs to the code bit %, the code bit group Gb2 is the code bit b! to by, and the code bit group Gb3 belongs to the code bit bs. The code bit group Gb4 is a code bit element ^ belongs. When the modulation mode is 1024QAM 'when the multiple b is 1, the 10xl (:=mb) bit symbol is based on the difference in error probability, as shown in Figure 8 〇B, the group can be divided into 5 symbols. The bit group Gy丨, Gy2, Gy3, Gy4, Gy5. -Ill. 135786.doc 200937872 In Fig. 80B, as in Fig. 62B, respectively, the 'character bit group Gyi is the meta-bit yQ, yi belongs to the 'character bit group Gy2-character bit The heart belongs to, the symbol element group Gys is the symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element bit "Mountain belongs, the symbol element group Gy5 system symbol element ys Y9 belongs to Fig. 81. The LDPC code is an LDPC code whose code length is N*162〇〇 and the coding rate is 5/6. The further modulation is 1〇24QAM, and the multiple 1 is 1 Rules The distribution rules in Figure 81 specify group information (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy5, l), (Gb3, Gy5, l), (Gb4, Gy4, l). That is, the allocation rule in Figure 81 is defined as follows: According to the group set information (Gb^Gy^l), the error probability first good code group The 1 bit of the code bit of the group Gbi is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb2, Gyi, 2) ' Error probability 2nd good code bit group Gb2 code position 2 bits of the element, assigned to the 2nd bit of the symbol element Gy丨 of the first good symbol group of the error probability; according to the group set information (Gb>2, Gy2, 2) 'The error probability 2 bits of the code bit of the second good code bit group Gb2, allocated to the 2 bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; according to the group set information ( Gb2, Gy3, 2) 'The 2 bits of the code bit of the second good symbol bit group Gb2 of the error probability are assigned to the symbol bit of the symbol group Gy3 of the third good error probability group. 2 bits; 135786.doc • 112· 200937872 According to the group set information (Gb^Gy^l), the unit of the code bit of the second good symbol group Gbz of the error probability is assigned to the error probability. The 5th good symbol group Gy5 symbol bit unit; according to the group set information (Gb3, Gys, l), the code probability of the 3rd good code bit group Gbs The 丨 丨 丨 , , , , , 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元 元The 1st bit of the code bit of the 4th good code bit group GW is assigned to the error probability. 4 © 1 bit of the symbol bit of the good symbol bit group Gy*. An alternative example of the code bit according to the allocation rule of Fig. 81. That is, Fig. 82A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and further modulation is 1〇24QAM. In the case where the multiple b is 1, the first example of the replacement of the code bits according to the allocation rule of FIG. 81 is used. The LDPC code is an LDpc code with a code length N of 16200 bits and a coding rate of 5/6. In the case where the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25' is in the longitudinal direction X horizontally. The code direction of the column direction is (162〇〇/(1〇xi))x (10 χ 1) bits. The code bits written in the row are in the horizontal direction, with l〇xl (= mb) bits. The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 assigns the m-bit b〇 to 1> 9' read from the memory 3's l〇xl (= mb) bit in accordance with the allocation rule of Fig. 81, for example, as shown in Fig. 82A to l (=b). The symbolic bits "to" of the i〇xi (= mb) bits of the symbol are replaced by the code bits b〇 to b9 of the l〇xl (= mb) bits. 135786.doc -113 - 200937872 Ο That is, the 'replacement unit 32 assigns the code bit b〇 to the symbol bit y6, respectively, and assigns the code bit b! to the symbol bit y4 to assign the code bit b2 to the symbol The meta-bit y8 assigns the code bit b3 to the symbol bit y5, the code bit b4 to the symbol bit y, the code bit b5 to the symbol bit y2, and the code bit b6 to the symbol The bit yi assigns the code bit b7 to the symbol bit y3. The code bit b8 is assigned to the symbol bit y9. The code bit b9 is assigned to the symbol bit y7 for replacement. 82B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a bat rate of 5/6, and the further modulation method is 1024QA]VI. In the case of multiples, the replacement of the code bits according to the allocation rule of FIG. 81 is performed. The second example. According to FIG. 82B, the replacing unit 32 performs the following steps according to the allocation rule of FIG. 81, and the stitches of the i〇xl (= mb) bits read from the memory 31 are respectively ~~%. Replace: assign the code bit b〇 to the symbol bit y7, assign the code bit b! to the symbol bit y8, assign the code bit b2 to the symbol bit y3, and assign the code bit b3 to The symbol bit y4 assigns the code bit b4 to the symbol bit y 5 and the code bit b5 to the symbol bit y 〇, 135786.doc • 114· 200937872 assigns the code bit b6 to the symbol The bit y2 assigns the code bit b7 to the symbol bit y 1, assigns the code bit b8 to the symbol bit y9, and assigns the code bit b9 to the symbol bit y6. 83 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and the modulation bit is 1024QAM, and the multiple of b is 1 and the code bit group and the symbol bit are Group. In this case, the code bit source of the l〇xl (= mb) bit read from the memory 31 can be grouped into 4 code bit groups as shown in FIG. 83A according to the difference in error probability. Gb 1, Gb2, Gb3, Gb4. In FIG. 83A, respectively, the code bit group Gb 1 belongs to the code bit b〇, the code bit group Gb2 belongs to the code bits b! to b7, and the code bit group Gb3 is the code bit. Bs belongs to, and the code bit group Gb4 belongs to the code bit b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of the l〇xl (=mb) bits are different according to the error probability, and can be grouped into 5 symbol positions as shown in FIG. 83B. The meta group Gy^Gy^Gy^Gy^Gys. In Fig. 83B, the same as Fig. 62B, respectively, the symbol bit group Gy! is represented by the symbol bit yG, yi, and the symbol bit group Gy2 is the symbol bit y2, y3 belongs to The meta-bit group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy4 is the symbol element y6, y7 belongs to, and the symbol element group Gy5 is the symbol element ys, y9 belongs. Fig. 84 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6, and a further modulation method of 1024QAM and a multiple b of 1. 135786.doc -115- 200937872 The distribution rule in Figure 84 specifies the group collection information (GbiGy4i), (〇^5〇Υι, 2), (0525072, 2), (0^, 〇Υ 3, 2), (〇^,〇Υ5,ι)?(<31)3 j} ? (Gb4, Gy4, 1). That is, the allocation rule in FIG. 84 is defined as follows: According to the group set information (Gb!, Gy4, 1), the 1 bit of the code bit of the coded bit group Gh of the first error probability group is allocated. Give 1 bit of the symbol bit of the symbol group Gy4 with a good probability of error; according to the group set information (Gb2, Gy!, 2) 'The error probability is 2nd good © code bit group The 2 bits of the code bit of the group Gh are allocated to the 2 bits of the symbol bit of the symbol i-good symbol group Gy of the error probability; according to the group set information (Gb2, Gy2, 2), Assigning 2 bits of the code bit of the second good symbol bit group Gh of the error probability to the 2 bits of the symbol bit of the second good symbol bit group Gy2 of the error probability; The set information (Gb2, Gy3, 2) assigns the 2 bits of the code bit of the second good code bit group Gb2 of the error probability to the symbol of the error probability 3^good symbol bit group Gy3 2 bits of the meta-bit; 分配 According to the group set information (Gb2, Gys, l), assign 1 bit of the code bit of the 2nd good code bit group Gb2 of the error probability to the error probability of $ 1 bit of the symbol element of the good symbol group Gy5; according to the group set information (Gh>3, Gy5, 1), the code position of the 3rd good code bit group Gbs of the error probability 1 bit of the element, assigned to the 1st bit of the symbol bit of the error probability ^^good symbol bit group Gy5; and according to the group set information (Gb^Gy4,1), the error probability is 4th A good bit of the bit group Gb>4 is allocated to the error probability. * I35786.doc • 116· 200937872 A good bit of the symbol bit of the symbol group. Figure 85 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 84. That is, FIG. 85A shows that the LDPC code is an LDPC code having a code length of 648 bits and a coding rate of 5/6, and further modulation is 1〇24QAM, and the multiple b is 1 according to FIG. 84. The first example of the replacement of the code bits of the distribution rule

LDPC code 疋 code length n is 64800 bits, encoding rate is 5/6 LDPC code, further modulation mode is 1〇24QAM, multiple 1) is 1 in the case of © multiplexer 25, in the vertical line The direction of the X direction is (6480 0 / ( l 〇 xl)) x (10 X 1) bits of the memory 3 丨 written code bits are in the horizontal direction with l 〇 xl (* ~ mb) bits The unit is read out and supplied to the replacement unit 32 (Fig. 16, 圊 17). The replacing unit 32 assigns the code bit b() read from the l〇xl (= mb) bit of the memory 3 1 to & according to the allocation rule of FIG. 84, for example, as shown in FIG. 85A to U=b). The symbol of the i〇xl (=rnb) bit of the symbol is "to replace the code bit b() of the l〇xl (= mb) bit to b9. That is, the replacement section 32 The stone horse bit bG is assigned to the symbol bit y6, the code bit b is assigned to the symbol y 4 , the code bit b2 is assigned to the symbol y8 , and the code bit b3 is allocated For the symbol bit y5, the code bit b4 is assigned to the symbol bit y, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to the symbol bit yi ' 135786.doc • 117· 200937872 assigns the code bit b7 to the symbol bit y3, assigns the code bit b8 to the symbol bit y9, and assigns the code bit b9 to the symbol bit y7 for replacement. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6. The further modulation method is 1024QAM, and the multiple of the code bits of the allocation rule of FIG. The second case.

According to Fig. 85B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 84: The bit bG is assigned to the symbol bit y7, the code bit b! is assigned to the symbol bit y 8, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Y4, the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol The meta-bit y 1, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y6. 86 is a diagram showing that an LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and a further modulation method is 1024QAM, and a multiple of b is a code bit group and a symbol bit. Group. In this case, the code bits 135786.doc -118- 200937872 of the l〇xl (= mb) bit read from the memory 31 are grouped into 5 according to the difference in error probability as shown in FIG. 86A. One code bit group Gbi, Gb2, Gb3, Gb4, Gl>5. In Fig. 86A, respectively, 'the code bit group 〇1) 1 is the code bit b〇, the code bit group Gt>2 is the code bit b! belongs to, the code bit group 〇b3 code Bits b2 to b>7 belong to the 'code bit group Gb>4 code bit 1)8, and the code bit group Gb is associated with the code bit bg. When the modulation mode is 1024QAM and the multiple b is 1, the symbol of the i〇xi(=mb) bit is different according to the error probability. As shown in Fig. 86B, the group can be divided into 5 symbols. The bit group 0丫1, 0丫2, 0丫3, 0丫4, 0丫5. 86B 'same as FIG. 62B', respectively, the symbol bit group Gy丨 symbol bit yG, y〗 belongs to, the symbol bit group Gy2 is the symbol bit y2, y3 belongs to the 'character The meta-bit group Gy3 is a symbol element y4, y5 belongs to, the symbol element group Gy* is a symbol element y6, y·; belongs to, the symbol-bit group 〇75-character bit ys , y9 belongs. 8 is a diagram showing an LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and the modulation mode is 1024QAM, and the multiple b is 1. In the allocation rule of Figure 87, there is a group collection information..., 々""), (Gb2, Gy!, l), (Gb3, Gyi5l), (Gb3, Gy2, 2), (Gb3, Gy3, 2) , (Gb3, Gy4, l), (Gb4, Gy5, l), (Gb5, Gy4, l). That is, the allocation rule in FIG. 87 is defined as follows: According to the group set information (Gbl5Gy5, l), the 1st bit of the code bit of the coded bit group Gb! of the error probability is assigned to the error. Probability 5th good symbol group Gy 5 symbol 1 bit; 135786.doc .119· 200937872 According to the group collection information (Gt^Gyhl), the error probability is 2nd good code position The code bit of the meta group Gb2! The bit is assigned to the error probability ^^good symbol bit group Gy, the 1-bit element of the symbol bit; according to the group set information (Gb^Gy^l), the error probability is the third good code The unit of the code bit of the bit group Gh is allocated to the bit element of the symbol bit of the symbol bit group Gy with good error probability; according to the group set information (Gb3, Gy2, 2), assigning the error probability 3rd good code bit to the 2 bit of the code bit of the group Gh, and assigning it to the error probability 2nd good ® good symbol bit group Gy Bits; according to the group set information (Gb3, Gy3, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are assigned to the 3rd good symbol bit of the error probability. 2 bits of the symbol bit of the group Gy3; according to the group set information, assign the bit position of the code bit of the 3rd good code bit group Gb3 of the error probability to the symbol bit with good error probability 1 bit of the symbol group of the meta group Gy4; 分配 according to the group set information (Gb^GhD, the error probability is the 4th good code bit το group Gh the code bit element, the allocation Give the probability probability of the $th good symbol group (the i bit of the symbol of Jy5; 4 and according to the group collection information (10)...^丨), the error probability of the $good symbol group The i-bit of the code bit of Gb5 is assigned to the bit element of the symbol bit group Gy, which has a good probability probability P. Figure 88 shows the code bit element according to the allocation rule of Fig. 87. In other words, FIG. 88A shows that the LDPC code is a code length Ng 162 bit, and the LDPC code with an encoding rate of 8/9 is 1 〇 24 qam, and the multiple 135786.doc 200937872 b is 1. In the case of the first example of the replacement of the code bits according to the allocation rule of FIG. 87, the LDPC code is an ldpc code with a length of 16200 bits and a coding rate of 8/9. Further modulation is l〇24QAM. When the multiple b is 1, the memory 31 of the (ΐ62〇〇/(1〇χ1))χ(1〇χ1) bit is written in the demultiplexer 25 in the wale direction X. The code bits are in the course direction, read out in units of l〇xl (= mb) bits and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads according to the allocation rule of Fig. 87. From memory The code bit of the l〇xl (=mb) bit is ~ to !^, for example, the symbol bit assigned to the i〇x bit of 1 (-b) symbol as shown in Fig. 88A To replace the code bits b() to b9 of the l〇xl (= mb) bits. That is, the replacement unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit bi For the symbol bit y, assign the code bit b 2 to the symbol bit y!, assign the code bit b3 to the symbol bit y2, and assign the code bit b4 to the symbol bit y3, The code bit b5 is assigned to the symbol bit y4, the code bit b6 is assigned to the symbol bit y6', the code bit b7 is assigned to the symbol bit y5, and the code bit b8 is assigned to the symbol bit y9 , the code bit b9 is assigned to the symbol bit y7, and is replaced. 135786.doc -121 - 200937872 Figure 88B shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 8/9. The further modulation method is 1024QAM, and the multiple b is 1. The second example of the replacement of the code bits of the distribution rule. According to Fig. 88B, the replacing unit 32 performs the following replacement for the code bits bG to b9 of the 10X 1 (= mb) bits read from the memory 3 in accordance with the allocation rule of Fig. 87: The bit bG is assigned to the symbol bit ys», the code bit b 1 is assigned to the symbol bit y 1, © the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol Bit y4, assign code bit b4 to symbol bit y5, assign code bit b5 to symbol bit y 〇, assign code bit b6 to symbol y2, assign code bit b7 To the symbol bit y7, the code bit b 8 is assigned to the symbol bit y 8, and the code bit b9 is assigned to the symbol bit y6. ❹ FIG. 89 shows that the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 8/9, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the l〇x1 (= mb) bits read from the memory 31 are group-divided into 5 code bit groups Gbi according to the difference in error probability as shown in FIG. 89A. , Gb2, Gb3, Gb4, Gb5. 89A, respectively, the code bit group 01^ is the code bit bG, the code bit group Gb2 belongs to the mbit bi, and the code bit group Gb3 is the code bit 135786.doc -122 - 200937872 h to b belongs, the code bit group 〇 134 is the code bit b8, and the code bit group Gb5 belongs to the mbit b9. When the modulation mode is 1024QAM and the multiple b is 1, the symbol bits of l〇xi(=mb) bits are different according to the error probability. As shown in Figure 8 9B, the group can be divided into 5 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 89B, as in FIG. 62B, respectively, the symbol bit group Gyi is associated with the symbol bit yG, yi, and the symbol bit group Gy2 is the symbol bit y2, and the y3 belongs to the 'character bit. The meta-group Gy3 is a symbol element y4, y5 belongs to, the symbol element bit © group Gy4 is a symbol element y0, y7 belongs to, the symbol element group Gy5 is a symbol element ys, y9 belongs. Fig. 90 is a diagram showing an LDPC code which is an LDPC code having a code length N of 64,800 bits and an encoding rate of 8/9, and a further modulation method of 1 〇 24QAM and a multiple b of 1. In the distribution rule of FIG. 90, group collection information (Gbi, Gy5 l), (Gb2, Gy1, l), (Gb3, Gyi, l), (Gb3, Gy252), (Gb3, Gy3, 2), (Gb3, Gy4, l)i (Gb4, Gy5, l), (Gb5, Gy4, l). That is, the allocation rule in Fig. 90 is defined as follows: According to the group set information (Gbi, Gy, 1, 1) '1 bit of the code bit of the error probability first good code bit group Gb! , assigned to the 1st bit of the symbol bit of the fifth-perfect symbol group Gy5 of the error probability; according to the group set information (Gb2, Gyi, l), the error probability second good symbol group One bit of the code bit of the group Gb2 is assigned to the 1-bit of the symbol bit of the first good symbol bit group of the error probability; according to the group set information (Gb^Gy^l), the error is Probability 3rd good 135786.doc 200937872 Code bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the first good symbol bit group According to the group set information (Gb3, Gy2, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are assigned to the 2nd good symbol bit group with the error probability 2 bits of the symbol bit of Gy2; according to the group set information (Gb3, Gy3, 2), the 2 bits of the code bit of the 3rd good code bit group Gb3 of the error probability are allocated The error probability is the third good symbol bit group Gy3 symbol bit 2 bit; 〇 according to the group set information (Gb3, Gy4, l), the error probability third good code bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gb4, Gy5, l), the error probability 1 bit of the code bit of the 4th good code bit group Gb4, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; (Gb5, Gy4, l), assigning the 1st bit of the code bit of the 5th good code bit group Gb5 of the error probability to the symbol of the error probability 4 ® good symbol bit group Gy4 One yuan of yuan. Figure 91 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 90. That is, FIG. 91A shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and the further modulation method is 1024QAM, and the multiple b is 1 in accordance with the distribution rule of FIG. The first example of the replacement of the code bit. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 8/9. When the modulation mode is 1024QAM and the multiple b is 1, the multiplexer 25 is solved at 135786.doc -124-200937872. In the wale direction, the direction of the column is (64800/^ 〇χ1)) χ (l〇xl) bits of the memory 31 are written in the horizontal direction, in the order of l〇xl (-mb) The unit is read out and supplied to the replacing unit 32 (Fig. 16, Fig. 17). The replacing unit 32 reads the code position of the l〇xl (= mb) bit from the memory 3 in accordance with the allocation rule of Fig. 90. The elements bQ to h, for example, are assigned to l(xb) bits of l(=b) symbols as shown in Fig. 91A, to replace l〇xl(=mb) bits. The code bits 1^ to b9. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit b to the symbol bit y, and sets the code bit. The element b is assigned to the symbol bit yj, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, and the code bit b5 is assigned to the symbol bit y4. The code bit b6 is assigned to the symbol bit y6,

A assigns the code bit b 7 to the symbol bit y 5 , assigns the code bit b8 to the symbol bit y9 , and assigns the code bit b9 to the symbol bit y 7 for replacement. 91B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9. The further modulation method is 1〇24QAM, and the multiple b is 1 in the case of the allocation rule according to FIG. The second example of the replacement of the bit. According to FIG. 91B, the replacement unit 32 is in accordance with the allocation rule of FIG. 90, and the code bits ^ to , respectively, read from the memory 31 of 135786.doc -125-200937872 The following replacement is performed: the code bit b〇 is assigned to the symbol bit y9, the code bit b1 is assigned to the symbol bit y!, the code bit ba is assigned to the symbol bit y3, and the code bit is The element b3 is assigned to the symbol bit y4, the code bit is assigned to the symbol bit y 5 , the code bit b5 is assigned to the symbol bit y , and the code bit b 6 is assigned to the symbol bit . y 2, the code bit b? is assigned to the symbol bit, the code bit bs is assigned to the symbol bit y8, and the code bit bg is assigned to the symbol bit y6. FIG. 92 shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and a further modulation method is 1024QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the l〇xi (=mb) bit read from the memory 31 are group-divided into three code bit groups Gb according to the difference in error probability as shown in FIG. 92A. !, Gb2, Gb3. In Fig. 92A', respectively, the code bit group Gb is associated with the code bit b〇, the code bit group Gt> 2 is the code bit b! to bs, and the code bit group Gb3 is the code bit. Yuan b9 belongs. The modulation mode is 1024QAM, and the multiple b is 1. The i〇xi(=mb) bit symbol is based on the difference in error probability. As shown in Fig. 92B, the group can be divided into 5 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5. 135786.doc • 126· 200937872 In Fig. 92B, as in Fig. 62B, respectively, the symbol bit group Gyi is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2. , y3 belongs to the 'character bit group Gy3 system symbol element y4, y5 belongs to, the symbol element group Gy* is the symbol element y6, y? belongs to, the symbol element group Gy5 symbol Bits ys, y9 belong. Fig. 93 shows an LDPC code in which the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and the modulation method is i〇24QAM, and the multiple b is 1. The distribution rule in Figure 93 specifies group information (Gbi, Gy5 l), (Gb2}Gy1, 2), (Gb2, Gy2, 2), (Gb2, Gy3i) 2), (Gb2, Gy4, l) ), (Gb2, Gy5, l), (Gb3, Gy4, l) ° That is, the distribution rule in Figure 93 is as follows: According to the group collection information (Gb^Gy^l) 'The error probability is 1st good 1 bit of the code bit of the Gigabit group Gbi is assigned to the 1st bit of the symbol bit of the symbol 5th good symbol bit group Gy5; according to the group set information (Gb2, Gy 〖, 2), the 2 bits of the code bit of the second good symbol bit group Gh of the error probability are assigned to the 2 bits of the symbol bit of the symbol group Gy! According to the group set information (Gb2, Gy2, 2), the 2 bits of the code bit of the second good code bit group Gbz of the error probability are assigned to the second good symbol bit group with the wrong probability. 2 bits of the symbol bit of the group Gy2; according to the group set information (Gb2, Gy3, 2), the 2 bits of the code bit of the second good code bit group Oh of the error probability are assigned to the error Probability 3rd good symbolic group of bits of Gy3, 2 digits of symbolic bits; 135786.do c • 127- 200937872 According to the group set information (Gbz, Gy4, l), the 1st bit of the megabit of the 2nd good code bit group Gb2 of the error probability is assigned to the 4th good symbol of the error probability. The bit element of the symbol group of the bit group Gy*; according to the group set information (Gt > 2, Gy5, l), the code bit of the second good code bit group Gb2 of the error probability The bit element is assigned to the bit element of the symbol bit of the fifth good symbol bit group Gys of the error probability; and the third probability code of the error probability according to the group set information (Gb3, Gy4, l) The τ bit of the code bit of the bit το group Gb3 is assigned to the 1-bit of the symbol bit of the error probability 4 ® good symbol bit group Gy4. Figure 94 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 93. That is, FIG. 94A shows that the LDPC code is an LDPC code having a code length of 1^ of 648 bits and a coding rate of 9/10, and the further modulation method is 1〇24QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an LDpc code with a code length N of 64,800 bits and a coding rate of 9/1 ,. In the case where the modulation method is l〇24QAM and the multiple is 】, the multiplexer 25 is in the traverse direction. The code bit written in the memory 31 of the X-direction direction is (648〇〇/(1〇><1)> (10x1) bits in the course direction, l〇xl(=mb) The bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 3 2 reads the l〇xl (= mb) bit from the memory 3 1 according to the allocation rule of Fig. 93. The code bits bG to b?, for example, are assigned to the symbol bits of l=x1 (= mb) bits of U=b) symbols as shown in Fig. 94A. To y9, to replace the code bits bG to b9 of the l〇xl (= mb) bits. 135786.doc -128- 200937872 That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, assigns the code bit b to the symbol bit y, and assigns the code bit b2 to The symbol bit y!, the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b5 is assigned to the symbol bit y4, and the code bit is assigned 1) 彡 is assigned to symbol octet 8, © assigns code bit b7 to symbol y5, assigns code bit be to symbol y9, and assigns bit b9 to y7 , and replace it. 94B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10. The further modulation method is i〇24QAM, and the multiple b is 1, the code according to the allocation rule of FIG. The second example of the replacement of the bit. According to FIG. 94B, the replacing unit 32 performs the following replacement for the code bits bQ to h of the l〇x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 93: Bit b〇 is assigned to symbol bit y8, code bit 1^ is assigned to symbol bit y6, code bit b2 is assigned to symbol bit y 9, and code bit b3 is assigned to symbol bit Element y4, assigning code bit b4 to symbol bit y 5, 135786.doc • 129· 200937872 assigning code bit to symbol bit y〇, and assigning code bit b6 to symbol bit y2, The code bit b7 is assigned to the symbol bit y 1, the code bit b8 is assigned to the symbol bit y3, and the code bit b9 is assigned to the symbol bit y7. 95 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the 12xl (= mb) bits read from the memory 31 are group-divided into 3 code bit groups 01> according to the difference in error probabilities as shown in FIG. 95A. ; 1,012,0匕3. In FIG. 95A, respectively, the code bit group Gb! belongs to the code bit b〇, the code bit group Gb2 belongs to the code bits bi to b7, and the code bit group Gb3 is the code bit b8 to Th ! belongs. When the modulation mode is 4096QAM and the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability. As shown in Fig. 95B, the group can be divided into 6 symbol bits. Groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 95B, respectively, the symbol bit group Gy is a symbol element y 〇, yi belongs to, the symbol bit group Gy2 is a symbol element y2, y3 belongs to, and the symbol element group belongs to Gy3 is a symbol element y4, y5 belongs to, a symbol element group Gy4 is a symbol element y6, y7 belongs to, a symbol element group Gy5 is a symbol element y8, y9 belongs to a 'character bit group Group Gy6 is a symbol element yi〇, yii belongs to. Figure 96 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 2/3, and the modulation method is 4096QAM, and the multiple b is 1 135786.doc • 130-200937872 . In the distribution rule of Fig. 96, group gather information (Gbi Gy6 l), (Gb25Gyl52), (Gb2, Gy252), (Gb2jGy352), (Gb2> Gy45i) 5 (Gb3Gy4jl) 5 (Gb3, Gy5, 2) are specified. , (Gb3, Gy6, l). That is, the allocation rule in FIG. 96 is defined as follows: According to the group set information (Gb^Gy^l), the 1-bit '1' of the code bit of the error probability i-th good code bit group Gb! Give the error probability the sixth good symbol group Gy6 of the symbol bit 1 bit; © according to the group set information (Gb2, Gyi, 2) 'the wrong probability second good matriary group The 2 bits of the code bit of Gbz are assigned to the 2 bit of the symbol bit of the first good symbol bit group Gy 1 of the error probability; according to the group set information (Gt > 2, Gy2, 2) 'Assign the 2 bits of the code bit of the second good code bit group Gh of the error probability to the 2 bit of the symbol bit of the second good symbol bit group Gyz of the error probability; The group set information (GbhGyy) assigns the 2 bits of the code bit of the 2nd good weight bit group of the error probability to the symbol bit of the symbol group Gy3 of the 3rd good error probability group. 2-bit; according to the group set information (Gb^Gkl), the symbol bit of the code bit of the second good code bit 7L group Gbz of the error probability is assigned to the fourth symbol of the error probability 1 bit of the symbol bit of the bit group Gy*; according to the group set information (GbhGki), the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the error probability 4th The good bit element group Gy* is the bit element of the symbol bit; according to the group set information (Gb3, Gy5, 2), the error probability is the third best 135786.doc -131 · 200937872 code bit 2 bits of the code bit of the group Gb3, assigned to (4) (4) 2 bits of the symbol bit of the good symbol bit group Gys; meaning and according to the group set information (Gl^Gy^), will be wrong The i-bit of the code bit of the probability good third bit group Gb3 is assigned to the 1-bit of the symbol bit of the sixth symbol of the error probability bit Gye. Figure 97 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 96. That is, FIG. 97A shows an LDPC code in which the LDPC code is code length \ 162 〇〇 bit coding rate is 2/3, and the step-by-step modulation method is 4 〇 96 qam, and the multiple of the factor b is 1 according to the figure. The first example of the replacement of the code bits of the distribution rule of 96. The LDPC code is 162 bits in code length >^, and the encoding rate is 2/3 [ο% code, further modulation is 4〇96QAM, in the case of multiples in the multiplexer 25, in the vertical line The direction X direction of the direction is (162 〇〇 / (12 χΐ)) χ (12 X 1) bits of the suffix 3 1 written code bits are in the horizontal direction, with 12xl (= mb) bits The unit reads 'and supplies to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 reads the code of the 12><1 (=11113) bits from the memory 3 in accordance with the allocation rule of Fig. 96. Bits 1)() to 1)11, for example, the symbol bits y〇 to yu assigned to the i2xl (=mb) bits of l(-b) symbols as shown in Fig. 97 and 8, in place of 12xl (= Mb) The bitwise bit of the bit to bn. That is, the 'replacement unit 32 assigns the code bit bQ to the symbol bit, respectively, the code bit b to the symbol bit y, and the code bit b2 to the symbol yi, 135786.doc -132- 200937872 assigning code bit b3 to symbol bit y2, assigning code bit b4 to symbol bit y3, and assigning code bit b 5 to symbol bit y 4, the code Bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, code bit b8 is assigned to symbol bit y8, and code bit b9 is assigned to symbol bit y7. The code bit b 1 〇 is assigned to the symbol bit y 11, and the code bit bn is assigned to the symbol bit y9 for replacement. 97B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 2/3, and further modulation is 4096QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to Fig. 97B, the replacing unit 32 performs the following replacement for the 12x1 (= mb) bit code bits bG to bn ' read from the memory 31 in accordance with the allocation rule of Fig. 96: The bit bG is assigned to the symbol bit y 11, the code bit b! is assigned to the symbol bit y 1, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit Element y4, assigning code bit b4 to symbol bit y5, assigning code bit b 5 to symbol bit y 〇, assigning code bit b6 to symbol y2, and assigning bit b7 The symbol bit y7, 135786.doc • 133· 200937872 assigns the code bit b8 to the symbol bit y9, the code bit b9 to the symbol bit y6, and the code bit bi 〇 to the symbol The bit y 1 〇 assigns the code bit b! 1 to the symbol y 8 . Figure 98 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and the further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the 12 X 1 (= mb) bits read from the memory 3 1 are group-divided into 3 code bit groups according to the difference in error probability as shown in FIG. 98A. Group Gbi, Gb2, Gb3. In FIG. 98A, respectively, the code bit group Gth is a code bit b〇, the code bit group Gb2 is a code bit bi to b7, and the code bit group Gb3 is a code bit b8 to bu. Own. When the modulation mode is 4096QAM and the multiple b is 1, the symbol bits of the 12xl (= mb) bits are different according to the error probability. As shown in FIG. 98B, the group can be divided into 6 symbol bit groups. Group Gy^Gj^Gy^Gy^Gy^Gys. In Fig. 98B, as in the case of Fig. 95B, respectively, the symbol bit group Gy! is represented by the symbol bit y^y!, and the symbol bit group Gy2 is the symbol bit y2, y3. Affiliation, the symbol element group Gy3 is a symbol element y4, y5 belongs to the 'character bit group Gy4 is a symbol element y6, y7 belongs to, the symbol element group Gy5 is a symbol element y8, Y9 belongs to, the symbol element group Gy6 is the symbol element yi〇, yii belongs. Figure 99 shows an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method of 4096QAM, a multiple b of 1 135786.doc -134-200937872 . In the distribution rule of FIG. 99, group group information (Gb2, Gy1, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, l), (Gb3, Gy4, l) > (Gb3, Gy5, 2), (Gb3, Gy6, l). That is, the distribution rule of Yu圊99 is as follows: According to the group set information (Gbi, Gy6, 1) 'Assign the 1st bit of the malt unit of the error probability first good code bit group Gb! Give the 1st bit of the symbol bit of the 6th good symbol group Gy6 of the error probability; ❹ According to the group set information (Gb2, Gy ι, 2) 'The second probability of the error probability group The 2 bits of the code bit of the group Gt>2 are assigned to the 2 bit of the symbol bit of the first good symbol group Gy of the error probability; according to the group set information (Gb2, Gy2, 2 And assigning the 2-bit ' of the code bit of the second good symbol bit group Gbz of the error probability to the 2-bit of the symbol bit of the second good symbol bit group Gy2 of the error probability; Group set information (Gb2, Gy3, 2) 'Assort the 2 bits of the code bit of the second good code bit group Gh of the error probability to the 3rd good symbol bit group Gys of the error probability 2 bits of the symbol bit; according to the group set information (GbhGykl), assign the i bit of the code bit of the second good code bit group Gh of the error probability to the error probability < 4: 1 bit of the symbol element of the good symbol element group Gy4; according to the group set information (Gb^Gy^l), the code bit of the error probability third good code bit group Gh 1 bit, assigned to the 1st bit of the symbol bit of the error probability **good symbol bit group Gy*; according to the group set information (Gb3, Gy5, 2), the error probability is 3rd good 135786.doc -135- 200937872 The bit position of the code bit group Gh is allocated to the 2nd bit of the symbol bit of the 5th good symbol bit group Gys; The group set information (Gb^Gy^l) assigns the 1st bit of the code bit of the 3rd good code bit group Gh of the error probability to the 6th good symbol bit group Gy0 of the error probability. The bit of the symbol element. Figure 100 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 99. That is, FIG. 100A shows that the LDPC code is an LDPC code whose code length is 648 bits and the coding rate is 2/3, and the further modulation method is 4〇96qAM, and the multiple 〇b is 1. The first example of the replacement of the code bits according to the distribution rule of FIG.

The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 2/3. In the case where the modulation method is 4096QAM and a multiple, the direction of the X direction of the demultiplexer 25' in the wale direction is ( 648〇〇/(12χ1))χ (12 X 1) bit memory 3 [Writing code bits are read in the horizontal direction in units of 12><1 (=011)), and Supply to the replacement unit 32 (Figs. 16 and 17) 〇❿ The replacement unit 32 reads the code bits from the 12><1 (=1111) bits of the memory 3 in accordance with the allocation rule of Fig. 99 | 3() to 1)]1, for example, as shown in Fig. 1 to assign U=b) symbols to 12><1 (=〇11) bits of the symbol bits" to m, Replace the code bit b of the 12xl (= mb) bit (>ibii. That is, the 'replacement unit 32 assigns the code bit b〇 to the symbol bit respectively. 〇, assign the code bit b to the symbol The bit y, assigning the code bit to the symbol yi, 135786.doc • 136· 200937872 assigning the code bit b3 to the symbol y2 and the code bit b4 to the y3 , the code bit b5 is assigned to the symbol bit y4, the code bit b6 is assigned to the symbol bit y5, and the code bit b7 is allocated. To the symbol bit y6, the code bit b8 is assigned to the symbol bit y8, the code bit b9 is assigned to the symbol bit y7, and the code bit b 1 〇 is assigned to the symbol bit y 11.

The code bit b 1 ! is assigned to the symbol bit y 9 and replaced. 100B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 2/3, and a further modulation method is 4096QAM, and a multiple of b is 1 in the case of a code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 100B, the replacing unit 32 performs the following replacement for the code bits bG to bn of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 99: bG is assigned to the symbol bit yi 1, the code bit b丨 is assigned to the symbol bit y 1, the code bit b2 is assigned to the symbol bit y3, and the code bit b3 is assigned to the symbol bit y4 , the code bit b4 is assigned to the symbol bit y5, the code bit b5 is assigned to the symbol bit y〇, the code bit b6 is assigned to the symbol bit y2, and the code bit b7 is assigned to the symbol Bit y7, 135786.doc -137- 200937872 assigns code bit b 8 to symbol bit y 9, assigns code bit b9 to symbol bit y6, and assigns bit bit bio to symbol bit 710. Assign the code bit b π to the symbol bit y 8. Figure 101 is a diagram showing that the LDPC code is an LDPC code whose code length N is 16,200 bits and the coding rate is 3/4. The further modulation method is 4096QAM, and the multiple is j is the code bit group and the symbol bit. Group. In this case, the code bit source of the I2x1 (= mb) bit read from the memory 31 is grouped into four code bit groups GbhGbhGbhGbc according to the difference in error probability as shown in FIG. 101A. 101A 'respectively, the code bit group code bit % belongs to the 'code bit group Gbz code bit element... to the subordinate, the code bit group Gb3 is the code bit bs belongs to the 'code bit group The group GW system code bits b9 to b! 1 belong. When the modulation mode is 4096QAM 'when the multiple b is 1, the symbol bits of the I2xl (= mb) bits are different according to the error probability, as shown in Figure 〇1B, the group can be divided into 6 symbol bits. Metagroups Gy丨, Gy2, Gy3, Gy4, Gy5, Gy6. 101B is the same as the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit yz, y3 belongs to ' The symbol element group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy* is the symbol element y6, y7 belongs to, the symbol element group 〇) ^5 system symbol element Ys, y9 belongs to, the symbol element group Gy6 is the symbol element y1G, yu belongs. Figure 102 is a diagram showing an LDPC code which is an LDPC code having a code length N of 16,200 bits and a coding rate of 3M, a further modulation method of 4096QAM, and a multiple b of 135786.doc • 138·200937872. The allocation rule in Fig. 102 specifies group information (Gb^Gy^l), (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, l), (Gb3, Gy4, l)' (Gb4, Gy5, l), (Gb4, Gy6, 2). That is, the allocation rule in FIG. 102 is defined as follows: According to the group set information (Gb, Gy5, 1) '1 bit of the code bit of the first good code bit group Gb 1 of the error probability' Assigned to the 1-bit of the symbol bit of the fifth-perfect symbol group Gy5 of the error probability; © according to the group set information (Gb2, Gyi, 2) 'The second probability of the error probability group The 2 bits of the code bit of the group Gt>2 are assigned to the 2 bit of the symbol bit of the first good symbol bit group Gy! of the error probability; according to the group set information (Gl>2, Gy2 2), assigning the 2-bit ' of the code bit of the second good code bit group Gt>2 of the error probability to the second bit symbol group Gy of the error probability, the symbol bit 2 bit; according to the group set information (Gb>2, Gy3, 2) 'Assign the 2nd bit of the code bit of the 2nd good weight bit group Gh of the error probability to the 3rd good error probability 2 bits of the symbol bit of the symbol element group Gy3; according to the group set information (Gb2, Gy4, l), the second good code bit of the error probability is 1 bit of the code bit of the group Gb2 Yuan, minute Give the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (Gb3, Gy4, l), the error probability 3rd good code bit το group The unit of the code bit of Gh is assigned to the 1st bit of the symbol bit of the 4th good symbol bit group Gy* of the error probability; according to the group set information (GbhGys'l), the error probability 4th good 135786.doc -139- 200937872 1 bit of the code bit of the code bit group Gin, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability And according to the group set information (Gb4, Gy6, 2), assign the 2 bits of the code bit of the 4th good code bit group Gh of the error probability to the 6th good symbol bit group of the error probability Group 2 of the symbol of Gy6. Figure 103 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1-2. That is, FIG. 103A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and the further modulation method is 4〇96QAM, and the multiple is €) b is 1 according to the figure} The first example of the replacement of the code bits of the allocation rule of 〇2. The LDPC code is an LDpc code with a code length N of 16,200 bits and a coding rate of 3/4. In the case where the modulation method is 4096QAM and the multiple 1) is 1, the multiplexer 25 is in the traverse direction and is horizontally traversed. The column direction is (162 〇〇 / (12 χΐ)) χ (12 X 1) bits of memory 艎 3 1 written code bits are in the horizontal direction, read in 12xl (-mb) bit units, and It is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the code bits 1x from the 12x1 (= mb) bits of the memory 31 in accordance with the allocation rule of FIG. Up to 1311, for example, the symbol bits of i2xl (= mb) bits assigned to l (=b) symbols as shown in Fig. 1〇3-8 are replaced by 丫^ to replace the code of 12xl (=mb) bits. Bit to bu. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b! to the symbol bit y, and assigns the code bit to the symbol y6. 135786.doc -140- 200937872 assign code bit b3 to symbol bit y!, assign code bit b4 to symbol bit y4, assign code bit b5 to symbol bit y5, place code bit The element b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y 1 〇 , assign the code bit b! 〇 to the symbol y! 1,

The code bit b i! is assigned to the symbol bit y 9, and replaced. FIG. 103B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, and further modulation is 4096QAM, and the multiple b is 1, the code bit according to the allocation rule of FIG. The second example of replacement. According to FIG. 103B, the replacing unit 32 performs the following replacement for the code bits bG to b!丨' of the 12 X 1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. : assigning the code bit bG to the symbol bit y9, assigning the code bit b! to the symbol bit y 1, assigning the code bit b2 to the symbol bit y3, and assigning the code bit b3 to the symbol The bit position y4 assigns the code bit b4 to the symbol bit y5, the code bit b5 to the symbol bit y, and the code bit b6 to the symbol y2, and the code bit b7 Assigned to the symbol bit y7, 135786.doc -141 - 200937872 assigns the code bit bg to the symbol bit y6, and assigns the code bit b 9 to the symbol bit y丨J, the code bit b 1 〇 is assigned to the symbol element y丨〇, and the code bit bl! is assigned to the symbol element y8. Figure 104 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the code bits of the χ丨2 χ丨 (= mb) bits read from the memory 31 are group-divided into 3 code bit groups Gb according to the difference in error probability as shown in FIG. 104A. ^Gb^Gh. In FIG. 104A, respectively, the code bit group Gbi code bit % belongs to the 'code bit group Gh code bit to the ^, the code bit group Gb3 is the code bit b9 to bn Own. When the modulation mode is 4096QAM 'when the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability, as shown in Figure 〇4B, the group can be divided into 6 symbols. The meta group GybGyhGyhGy^GyhGye. In FIG. 104B, as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit y Q, y 1 belongs to, and the symbol bit group Gy 2 is a symbol bit y2. Y3 belongs to the 'character bit group Gys system symbol element y4, y5 belongs to, the symbol element group Gy4 is the symbol element y6, y7 belongs to, the symbol element group Gy5 is the symbol element ys , y9 belongs to, the symbol element group GW system symbol element value belongs to. 105 is a diagram showing an LDPC code in which an LDPC code having a code length N of 64,800 bits and a coding rate of 3/4, and a further modulation method of 1〇24qAM, multiples #i of 135786.doc • 142-200937872 . The distribution rule in FIG. 105 specifies group information (Gh Gwj), (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, 2), (Gb3, Gy5, l), (Gb3, Gy6, 2). That is, the allocation rule in FIG. 105 is defined as follows: According to the group set information (Gb!, Gy5, l) '1 bit of the code bit of the error probability first good code bit group Gb! The 1st bit of the symbol element assigned to the symbol element group Gy 5 of the error probability 5th; Ο According to the group set information (Gb2, Gyi, 2) 'The error probability is 2nd good code point The 2-bit ' of the code bit of the meta-group Gt>2 is assigned to the 2-bit of the symbol bit of the error probability i-th good symbol bit group Gy; according to the group set information (Gb2, Gy2) 2) 'The 2 bits of the code bit of the second good code bit group Gt>2 of the error probability are assigned to the symbol bit of the second good symbol bit group Gy2 of the error probability 2 Bit; according to the group set information (Gb2, Gy3, 2) 'Assign the 2nd bit of the code bit of the 2nd good code bit group Gh»2 of the error probability to the error probability 3rd good® 2 bits of the symbol bit of the symbol element group Gy3; according to the group set information (Gb>2, Gy4, 2) 'the code point of the second good code bit group Gt> 2 yuan of yuan, The second bit of the symbol bit of the 4th good symbol group Gy4 of the error probability is assigned; according to the group set information (Gb3, Gys, l), the error probability third good symbol bit group Gb3 1 bit of the code bit, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; and according to the group set information (Gb3, Gy6, 2), the error Probability 3rd good 135786.doc • 143- 200937872 The code bit group Gh 2 bits of the code bit are assigned to the 2nd bit of the symbolic bit of the 6th good symbol bit group Gy6 of the error probability yuan. Figure 106 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1 〇 5. That is, FIG. 106A shows that the LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 3/4, and the modulation mode is 4096QAM, and the multiple b is 1 according to the allocation according to FIG. The first example of the replacement of the ruled code bits. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 3/4. In the case where the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is in the traversing direction and the horizontal direction is X. The memory of the (648〇〇/(12x1))x (12 X 1) bit is stored in the horizontal direction, read in 12xl (= mb) bits, and Supply to the replacement unit 32 (FIG. 16, FIG. 17) The replacement unit 32 reads the code bits b (^bn, 12x1 (=mb) bits from the memory 3j according to the allocation rule of FIG. For example, as shown in Fig. 1〇6A, the symbol bits 7〇 to 711 of 12xl (= mb) bits allocated to 1 (=b) symbols are replaced with the code bits b of 12xl (= mb) bits ( That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b to the symbol bit y, and assigns the code bit b2 to the symbol. Bit y6, assigning code bit b3 to symbol bit yi, assigning code bit b4 to symbol bit y4, and assigning code bit b5 to symbol bit y5, 135786.doc • 144. 200937872 The code bit b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, and the code bit is B8 is assigned to the symbol bit y 7, the code bit b9 is assigned to the symbol bit 丫1〇, the code bit b 1 〇 is assigned to the symbol bit y丨丨, and the code bit bi丨 is assigned to Figure 106B shows that the LDPC is an LDpC code with a code length N of 64,800 bits and a male rate of 3/4. The further modulation is 4096QAM, and the multiple b is 1. The second example of replacing the code bit according to the allocation rule of Fig. 105. According to Fig. 106B, the replacing unit 32 is for the 12x1 (= mb) bit read from the memory 31 in accordance with the allocation rule of Fig. 105. The code bits bG to bn of the element are respectively replaced by: assigning the m-bit b〇 to the symbol bit y9, and assigning the code bit b 1 to the symbol bit y 1, and the code bit b 2 Assigned to the symbol bit y 3 , the code bit b3 is assigned to the symbol bit y4 , the code bit b4 is assigned to the symbol bit y 5 , and the code bit b5 is assigned to the symbol bit y 〇 . The code bit is assigned to the symbol bit y2, the code bit 1)7 is assigned to the symbol bit y7, the code bit 1)8 is assigned to the symbol bit y6, and the code bit b9 is assigned to the symbol The meta-bit y丨1, the code bit 1)1() Assigned to the symbol bit 71〇, 135786.doc • 145- 200937872 Assign the code bit b!! to the symbol bit y 8. Figure 107 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Group. In this case, the difference between the error bit probability of the I2x1 (= mb) bit read from the memory 31 can be grouped into three code bit groups Gb^GbhGbs as shown in FIG. 107A. » In Fig. 107A, respectively, the 'code bit group code bit % to, © the 'code bit group Gh code bit % % belongs to, the code bit group Gb3 is the code bit b 1 〇 and b 11 belongs. When the modulation mode is 4096QAM and the multiple b is 1, the 12x1 (=mb) bit symbol is based on the difference in error probability. As shown in Figure 1, the group can be divided into 6 symbol groups. Groups Gy丨, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 107B, as in the case of FIG. 95B, respectively, the symbol bit group Gy is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2, and y3 belongs to ' The symbol element group Gy3 is represented by the symbol element y4, y5, the symbol element group Gy4 is the symbol element ye, y7 belongs to, the symbol element group day "signature element bit ys, y9 Affiliation, symbol group Gy6 is a symbol element yiQ, y" belongs. Figure 108 shows that the LDPC code is an LDPC code with a code length N of 16,200 bits and a coding rate of 4/5. 4096QAM, the allocation rule in the case where the multiple b is 1. The allocation rule in Fig. 108 specifies group information (Gbi, Gyi 2), (Gbi, Gy2, 2), (Gb1, Gy352), (Gb1, Gy4,2)}(Gb1,Gy5,l),(Gb2,Gy6,l), 135786.doc •146· 200937872 (Gb3,Gy5,l),(Gb3,Gy6,l). That is, 'Figure 108 The allocation rule is as follows: According to the group set information (〇1?1, 〇71, 2), the 2 bits of the code bit of the error probability 1st good code bit group Gbi are allocated to the 蛉 崎, the knife is wrong, the probability of the i-th good symbol group Gy, the symbol element 2 bits; according to the group set information (Gb^Gy2), the 2nd bit of the code bit of the error probability bit group Gb! is assigned to the second symbol of the error probability 2 bits of the symbol bit of the bit group Gyz; © According to the group set information (GbuGysJ) 'Assign the error probability jth good code bit group Gh 2 bits of the code bit' to the error The probability 3rd sound is good, the bit group Gy3 is 2 bits of the symbol bit; according to the group set information (Gb^Gy4.) 'the error probability is the i-th good code bit group Gb, 2 bits of the code bit, assigned to the 2nd bit of the symbol bit of the 4th good symbol bit group Gy4 of the error probability; according to the group set information (Gbi, Gy, 1) 'The error probability 1st good 1 1 bit of the code bit of the code bit group Gh, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; (Gb>2, Gy6, l), assigning the 1-bit of the code bit of the second-perfect code bit group Gb2 of the error probability to the symbol of the sixth-perfect symbol bit group Gy6 of the error probability Bit 1 bit; according to the group set information (Gb3, Gys, l), assign 1 bit of the code bit of the error probability 3rd good mother bit group Gt>3 to the error probability 5th good 1 bit of the symbol bit of Gy 5; and according to the group set information (01?3, 〇76,1), the error probability is 3rd good 135786.doc • 147- 200937872 One bit of the code bit of the bit group Gb3 is assigned to one bit of the symbol bit of the sixth bit symbol group Gy6 of the error probability. Figure 109 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 1-8. That is, FIG. 109A shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 4/5, and the further modulation method is 4096QAM, and the multiple b is 1 according to the allocation rule of FIG. The first example of the replacement of the code bit. LDPC is an LDPC code with a code length N of 16200 bits and a coding rate of 4/5. In the case where the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is in the traversing direction, and the horizontal direction is X. The code bits written in the memory 31 of the column direction (丨62〇〇/(12x1))X (12x1) bits are in the course direction, read out in 12xl (=mb) bit units, and supplied to The replacing unit 32 (FIG. 16, FIG. 17) 〇 replacing unit 3 2 reads the code bits bG to bn of 12x1 (= mb) bits from the memory 3 1 according to the allocation rule of FIG. 1 , 8 , for example, i〇9A is assigned to symbolic bits 7() to 丫11 of 12xl (= mb) bits of l (=b) symbols, to replace the code bits of Kxibmb) bits to bn. That is, the replacing unit 32 assigns the code bit bo to the symbol bit y8, the code bit bi to the symbol bit y, and the code bit b2 to the symbol y 6, respectively. The code bit b3 is assigned to the symbol bit y !, the code bit b4 is assigned to the symbol bit y4, and the code bit b5 is assigned to the symbol bit y5, 135786.doc -148 - 200937872 B6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the mate bs is assigned to the peg y7, and the code bit b9 is assigned to the peg y 1〇, The code bit Sb1G is assigned to the symbol bit yn, and the code bit b! i is assigned to the symbol bit y9, and is replaced. FIG. 1098 indicates that 1^?(1; the block is the code length)^ is 16200 bits. The second example in which the coding rate is a 4/5 iLDPC code, and the modulation method is 4096QAM, and the multiple b is 1, the replacement of the code bits according to the allocation rule of FIG. 108. If the replacement unit is according to FIG. 109B, According to the distribution rule of FIG. 108, for the code bits b〇 to b!! of the Ι2χ 1 (= mb) bits read from the memory 3 1 , the following replacement is performed respectively: The code bit b 〇 Assigned to the symbol y6, The code bit b 1 to the symbol bit y !, allocating the code bit b2 to the symbol bit y3,

A assigns the code bit b3 to the symbol bit y4, assigns the code bit b4 to the symbol bit y5, assigns the code bit b5 to the symbol bit y0, and assigns the code bit b6 to the symbol bit The element y2 assigns the code bit unit to the symbol bit y7, assigns the m-bit bs to the symbol bit y9, and assigns the code bit b9 to the symbol bit y 11 '. The code bit b! Assigned to the symbol bit yi〇' 135786.doc -149- 200937872 The code bit bn is assigned to the symbol bit y8. Figure 110 shows an LDPC code with an LDPC code length N of 64,800 bits and a coding rate of 4/5, and a further modulation method of 4096QAM, a multiple of 13 is a code bit group and a symbol bit. Meta group. In this case, the code bits of the i2xl (==inb) bits read from the memory 31 are grouped into 5 code bit groups according to the difference in error probability as shown in FIG. 11A. GbhGbhGbhGbhGbs. In FIG. 110A, respectively, the code bit group Gbi is the code bit %, the code bit group Gb2 is the code bit\ belongs, and the code bit group Gb3 is the code bit bz to bs. The code bit group oh belongs to the code bit %, and the code bit group Gb5 is the code bit bi〇 and bi! When the modulation method is 4096QAM and the multiple b is 1, the 12xl (= mb) bit symbol is based on the difference in error probability. As shown in Figure 可, the group can be divided into 6 symbol groups. Group (^1, (^2, (^3, (^4, (^5, (^6. in Fig. 110B, which is the same as the case of Fig. 95B, respectively, the symbol element group Gyi symbol) The bit yQ, yi belongs to, the symbol element group Gy2 is a symbol element Μ yuan Μ," belongs, the symbol element group Gys is a symbol element y4, y5 belongs to, the symbol element group Gy* The symbol element ye, y7 belongs to, the symbol element group (^5 is the symbol element belongs to, the symbol element group Gy6 is the symbol element yiQ, yn belongs to. Figure 111 shows that the LDPC code is The code length Na 648 〇〇 bit encoding rate is 4/5 LDPC code, and the further modulation mode is 4 〇 96QAM, the allocation rule in the case of multiple 1. The allocation rule in FIG. 111 specifies group group information ( Gbi, Gy5 l), 135786.doc • 150- 200937872 (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy2, 2), (Gb3, Gy352), (Gb3 > Gy4 2) ( Gb4, Gy6, l), (Gb5, Gy5, l), (Gb5, Gy6, l). ' That is, the distribution rules in Figure 111, As follows: According to the group set information (Gb^Gy^l), the code bit of the i-th good code bit group Gb of the error probability is assigned to the fifth bit of the error probability. 1 bit of the symbol bit of the group Gy5; according to the group set information (Gb^Gy^l) '1 bit of the code bit of the second good code bit group Gt> Assigned to the error probability ι 良 © The good symbol meta-group Gy! The 1-bit symbol; according to the group collection information (Gb^Gy^l), the error probability is the third good code position The ι bit of the code bit of the meta-group Gb>3 is assigned to the 1-bit of the symbol bit of the error probability J-good symbol group; according to the group set information (Gt>3, Gy2 2), assigning the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability to the second bit symbol group Gy of the error probability; Bits; according to the group set information (Gb3, Gy3, 2), assign the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability to the 3rd good symbol bit of the error probability Group Gy; 2 bits; according to the group set information (Gb3, Gy4, 2), assign the error probability 3rd good code bit to the 2 bits of the code bit of the group Gbs to the 4th good symbol of the error probability 2 bits of the symbol group of the meta group Gy*; according to the group set information, the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability is assigned to the sixth error probability. The ι bit of the symbol bit of the symbol group Gw; 135786.doc -151 · 200937872 According to the group set information (Gb5, Gys, l), the error probability fifth good symbol group 1 bit of the code bit of Gb>5, assigned to the 1st bit of the symbol bit of the symbol 5th good symbol group Gy5 of the error probability; and according to the group set information (Gt>5, Gy6, l), assigning 1 bit of the code bit of the 5th good code bit group Gb>5 of the error probability to 1 bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability yuan. Figure 112 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure ill. That is, 'FIG. 112A shows that the LDPC code is an LDPC code with a code length N of 64,800 bits and a code rate of 4/5. The further modulation method is 4〇96QAM, and the multiple 1 is in accordance with FIG. 111. The first example of the replacement of the code bits of the allocation rule.

LDPC is an LDPC code with a code length N of 64,800 bits and a coding rate of 4/5. In the case where the modulation is 4096QAM and the multiple b is 1, the multiplexer 25 is in the X direction in the wales. The direction is (648〇〇/(ΐ2χΐ))χ (12 1) bits of the suffix 3 1 written code bits are in the horizontal direction, read in 12xl (= mb) bit units 'and Supply to the replacement unit 32 (Fig. 16, Fig. 17) The replacement unit 3 2 reads the code bit % from the 12xl (= mb) bits of the memory 3 J to bn ' according to the allocation rule of Fig. 11 For example, as shown in Fig. 112A, the symbol bits yG to yu of the i2x1 (= mb) bits assigned to the l (= b) symbols are replaced with the code bits % to bn of the 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, and assigns the bit b! to the symbol bit y, respectively, 135786.doc • 152-200937872 assigns the megabyte b For the symbol bit y6, the code bit b3 is assigned to the symbol bit yj, the code bit b4 is assigned to the symbol bit y4, and the code bit b5 is assigned to the symbol bit y5, and the code bit is assigned B6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y丨〇. © Assign the code bits b, 〇 to the symbol bits y, i, and assign the code bits b to the symbol y9 for replacement. Figure 112B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 4/5, and further modulation is 4096qAM, and the multiple b is 1, the code bit according to the allocation rule of Fig. 111 The second example of replacement. According to FIG. 1 UB, the replacement unit 32 performs the following replacement for the code bits from the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 111, d U 1 W : assigning the code bit b〇 to the symbol bit y9, assigning the code bit b! to the symbol bit yi, assigning the code bit b2 to the symbol bit y 3, and assigning the mbit b3 to The symbol bit y4 assigns the code bit b4 to the symbol bit y 5 , assigns the code bit bs to the symbol bit y , and assigns the m place b6 to the symbol bit y 2, 135786. Doc -153 - 200937872 assigning code bit b7 to symbol bit y7 ' assigning code bit 1) 8 to symbol bit y6, and assigning code bit b9 to symbol bit yn ' will be code bit 131() is assigned to symbol bit 710' to assign code bit b1] to symbol bit y8. Figure 113 is a diagram showing that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and a further modulation method is 4096QAM, and a multiple of b is a code bit group and a symbol bit. Group. © In this case, the code bits of the 12x1 (= mb) bits read from the memory 31 are grouped into 4 code bit groups Gb1 according to the difference in error probability, as shown in FIG. 113A. Gb2, Gb3, Gb4. In FIG. 113A, respectively, the code bit group Gbl is associated with the code bit ^, the code bit group Gh is the code bit to be !)8 belongs to, the code bit group Gb3 is the code bit bp belongs to The code bit group Gh is a code bit and belongs to bn. When the modulation mode is 4096QAM and the multiple b is 1, the i2xl (= mb) ❹ bit symbol is based on the difference in error probability. As shown in FIG. 113B, the group can be divided into 6 symbol bits. Groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 113B, as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yG, yi belongs to, and the symbol bit group is a symbol bit yz, y3 belongs to, and The meta-bit group is a symbol element y4, y5 belongs to, the symbol bit group Gh is a symbol element Υ6, & belongs to, the symbol element group Gy5 is a symbol element bit belongs to The meta-bit group Gy6 is a symbol element yiG, yu belongs to it. Figure 114 is a diagram showing an LDPC code whose code length is 162 〇〇 bit code rate 135786.doc -154 - 200937872 5/6, and the modulation method is 4096QAM, and the multiple is i is i. . In the allocation rule of Fig. 114, group group information (Gbi Gy5 ^ (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb25Gy4, 2), (Gb3, Gy6 1) (Gb4, Gy5, l), (Gb4, Gy6, l). That is, the allocation rule in Figure 114 is as follows: According to the group collection information (Gb, Gy5, l), the error probability is i good code bit group Gth code bit 1 bit 'assigned to error probability 5th good © good symbol bit group Gy 5 symbol bit 1 bit; according to group set Information (Gl>2, Gy!, 2) 'Assign the 2nd bit of the code bit of the 2nd good maze group Gt>2 of the error probability to the symbol group Gy with the wrong probability probability 2 bits of the symbol bit of i; according to the group set information (Gb2, Gy, 2), the 2 bits of the code bit of the 2nd good code bit group Gbz of the error probability are assigned to the error 2nd bit of the symbolic second bit symbol group Gy2; ❹ According to the group set information (Gb2, Gy3, 2) 'The error probability second good code bit group Gh 2 bits of the code bit, assigned to the 3rd good symbol group Gy with the wrong probability 2 bits of the symbol element of 3; according to the group set information (Gb2, Gy4, 2), the 2nd bit of the code bit of the second good code bit tl group Gh of the error probability is assigned to the error probability The 4th good symbol element group Gy4 is a 2-bit symbol; according to the group set information, the 1st bit of the code bit of the 3rd good code bit group Gb3 of the error probability is allocated. Give the error probability the sixth good symbol group Gy6 symbolic bit 1 bit; 135786.doc -155- 200937872 According to the group collection information (Gb4, Gys, l) 'The error probability is 4th good 1 bit of the code bit of the code bit group GW, assigned to the 1st bit of the symbol bit of the 5th good symbol bit group Gys of the error probability; and according to the group set information (Gb> 4, Gy6, l), assigning the 1st bit of the code bit of the 4th good code bit group Gh of the error probability to the symbol bit of the 6th good symbol bit group Gy0 of the error probability Figure 115 is an alternative to the code bit according to the allocation rule of Figure 114. That is, Figure 115A shows that the LDPC code is a length of 16200 bits and a code rate of 5/6. The first example of the replacement of the code bits according to the allocation rule of Fig. 114 in the case where the DPC code is further modulated by 4〇96QAM and the multiple b is 1. The LDPC is a code length N of 16,200 bits and a coding rate. In the case where the 5/6 LDpc code 'further modulation mode is 4096QAM and the multiple b is 1, the demultiplexer 25' is in the direction of the X direction (162〇〇/(12χ1))χ ( The code bits written by the 12x1) bit memory 31 are read in the order of 12x l (-mb) bits in the course direction and supplied to the replacement unit 32 (Fig. μ, Fig. V 17). The replacing unit 3 2 allocates the code bits b() to b11 from the 12x1 (= mb) bits of the memory 3 1 according to the allocation rule of FIG. 114, for example, as shown in FIG. U5A, to l(=b) The symbol y of the I2xl (= mb) bit of the symbol. To yn, replace the code bits bQ to bn of 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, respectively, and assigns the code bit bi to the symbol bit y, 135786.doc -156- 200937872 assigns the code bit b2 to the symbol The bit y6 assigns the code bit b3 to the symbol y!, assigns the code bit b4 to the symbol y4, and assigns the code bit b5 to the symbol y5, and the code bit 1 6 is assigned to symbol bit y2, code bit b7 is assigned to symbol bit y 3, code bit b8 is assigned to symbol bit y7, and code bit b9 is assigned to symbol bit y 1 〇, 分配 The code bit 1?1() is assigned to the symbol bit yn, and the code bit bi! is assigned to the symbol bit y9 for replacement. Figure 115B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6, and further modulation is 4096QAM. When the multiple b is 1, the code bit according to the allocation rule of Fig. 114 is used. The second example of replacement. According to FIG. 115B, the replacing unit 32 performs the following replacement for the code bits bQ to bu of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 114: bG is assigned to the symbol bit y9, the code bit b] is assigned to the symbol bit y, the code bit b2 is assigned to the symbol y3, and the code bit b3 is assigned to the symbol y4. The code bit b4 is assigned to the symbol bit y 5 , the code bit b5 is assigned to the symbol bit y 〇 , and the code bit b6 is assigned to the symbol bit y2 , 135786.doc -157- 200937872 Bit b7 is assigned to symbol bit y7, code bit be be assigned to symbol bit y6, code bit b9 is assigned to symbol bit yi!, and code bit bi is assigned to symbol bit丫10, the code bit b 1 is assigned to the symbol bit y 8 . Figure 11 shows that the LDPC code is an LDPC code with a code length N of 64 8 00 bits and a coding rate of 5/6, and the modulation mode is 4096QAM, and the code bit group and the symbol bit in the case of the multiple i Meta group. ® In this case, the difference between the error vectors of the I2xl (= mb) bits read from the memory 31 can be grouped into 3 code bit groups Gbi as shown in Fig. 116A. Gb2, Gb3 » In Fig. 116A, respectively, the code bit group Gb is the code bit b〇, the code bit group Gbz is the code bit to the !)9, the code bit group Gb3 is The code bit 1 > 1 () and bn belong. When the modulation mode is 4096QAM and the multiple b is 1, the symbol bits of the 12xl (= mb) bits are grouped into six symbol bit groups according to the difference in error probability as shown in FIG. 116B. Group Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In FIG. 116B, as in the case of FIG. 95B, respectively, the symbol bit group Gy is a symbol bit yQ, yi belongs to, and the symbol bit group Gy2 is a symbol bit yZ, y3 belongs to, The symbol element group Gy3 is represented by the symbol element y4, ys belongs to, the symbol element group Gy* is the symbol element y0, y7 belongs to, and the symbol element group symbol 兀, y9 belongs to , the symbol element group Gy6 is a symbol element belongs to. Figure 7 shows that the LDPC code is LDPC code with a code length of ^^ of 648, and the coding rate is 135786.doc -158· 200937872 5/6. The further modulation method is 4〇96QAM, and the multiple is 1? The distribution rules in the case. In the allocation rule of FIG. 117, group group information (Gbi, Gy5, 1}, (Gb2, Gyi, 2), (Gb2, Gy2, 2), (Gb2, Gy3, 2), (Gb2, Gy4, 2), (Gb2, Gy6, l), (Gb3, Gy5, l), (Gb3, Gy6, l) 〇 That is, the allocation rule in Figure 117 is specified as follows: According to the group collection information (Gb^Gy^ l), assigning the 1-bit ' of the code bit of the first good code bit group Gb 1 to the error probability 5th good © the good symbol bit group Gy5 Bit; according to the group set information (Gb2, Gy!, 2) 'The second bit of the code bit of the error probability second good code bit group Gb>2 is assigned to the first probability of the error probability The bit group Gy, the 2 bit of the symbol bit; according to the group set information (Gbz, Gy2, 2), the 2nd bit of the code bit of the second good code bit group Gb2 of the error probability Yuan, assigned to the 2nd bit of the symbol bit of the second good symbol group Gy2 of the error probability; © according to the group set information (Gb2, Gy3, 2) 'The second probability of the error probability 2 bits of the code bit of the meta-group Gb2, assigned to the third probability of error probability The good symbol meta-group Gy is the 2-bit symbol; according to the group collection information (Gb2, Gy4, 2) 'The error probability second good code group Gt> 2 code The 2-bit of the bit is assigned to the 2-bit of the symbol bit of the fourth-perfect symbol group Gy4 of the error probability; according to the group set information (Gl>2, Gy6, 1), the error probability 1 bit of the code bit of the second good code bit group Gb2, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group Gy6 of the error probability; 135786.doc -159- 200937872 According to the group set information (Gb3, Gys, l), the unit of the code bit of the 3rd good code bit group Gh of the error probability is assigned to the 5th good symbol bit group of the error probability. 1 bit of the symbol bit of Gys; and according to the group set information (Gb^G^D, assign the error bit of the code bit of the 3rd good code bit group Gbs of the error probability to the error Fig. 118 is an alternative example of the code bit according to the allocation rule of Fig. 117. That is, Fig. 118A shows an LDPC code. The code length N is 64800 bits, the docking code rate is 5/6 LDPC code, and the further modulation mode is 4〇96qAM, and the multiple b is 1 in the case of replacing the code bit according to the allocation rule of FIG. The first example of the LDPC code is an LDpc code having a code length N of 64,800 bits and a coding rate of 5/6. In the case where the modulation method is 4096QAM and the multiple b is 1, the multiplexer 25 is on the traverse. The direction X direction of the direction is (648〇〇/(12χ1))χ (12 X 1) bits of the suffix 3 1 written horses are in the horizontal direction, with 12xl (= mb) bits The unit is read out and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b() from the 12x1 (= mb) bits of the memory 3 i to the bu according to the allocation rule of FIG. 117, for example, as shown in FIG. 118A, assigns 1 (=b) characters. The symbol bits y〇 to yn of the l2xl (= mb) bits of the element are substituted for the code bits b〇 to bn of the 12xl (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, respectively, and assigns the code bit b! to the symbol bit yG, 135786.doc -160· 200937872 assigns the code bit b2 to Symbol bit y 6, assign code bit b3 to symbol bit y, assign code bit b4 to symbol y4, assign code bit b5 to symbol y5, place code bit The element b6 is assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y! , © assigns the code bit b 1 〇 to the symbol bit y 1 J, and assigns the code bit b 1 1 to the symbol bit y9 for replacement. Figure 118B shows that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6. The further modulation method is 4096QAM, and the multiple 1 is a code position according to the allocation rule of Fig. 117 in the case of i. The second example of the replacement of Yuan. According to FIG. 118B, the replacing unit 32 performs the following replacement for the code bits bG to bn, W of the 12x1 (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 117: The element b〇 is assigned to the symbol bit y9, the code bit b 1 is assigned to the symbol bit y J , the code bit b is assigned to the symbol bit y 3 , and the code bit b3 is assigned to the symbol Bit y4, the numerator b4 is assigned to the symbol y5, the symbol bs is assigned to the symbol y, and the symbol is assigned to the symbol y2, 135786.doc -161 - 200937872 assigns the code bit b7 to the symbol bit y7, assigns the code bit b8 to the symbol bit yn, assigns the code bit b 9 to the symbol bit y 6, and assigns the code bit b 1〇 The symbol bit yi 给 is assigned to the symbol bit y8. Figure 119 is a diagram showing that the LDPC code is a code bit group and a symbol bit in the case where the code length N is 16,200 bits and the coding rate is 8/9, and the further modulation method is 4096QAM, and the multiple b is 1. Group. In this case, the code bits of the I2x1 (= mb) bits read from the memory 31 are group-divided into 5 code bits 7C group Gb 1 according to the difference in error probability as shown in FIG. 119A. , Gb2, Gb3, Gb4, Gb5. 119A, respectively, the code bit group Gb is the code bit group b belongs to the 'code bit group Gb2 code bit b! belongs to, the code bit group Gb3 is the code bit h to belong to The 'code bit group Gb4 is the code bit 1) 1() belongs to, and the code bit group Gb is the code bit bn. When the modulation method is 4096 Q AM 'when the multiple b is 1, the 12x1 (= mb) bit symbol is based on the difference in error probability, as shown in Figure 9B, the group can be divided into 6 symbols. The bit group is 1,0丫2, 〇73,0丫4, 〇75, 〇76. In FIG. 119B, as in the case of FIG. 95B, respectively, the symbol bit group Gyi is associated with the symbol bit, and the symbol bit group Gy2 is the symbol bit y2, y3 belongs to the symbol bit. Group Gy3 is a symbol element y4, y5 belongs to, symbol element group Gy4 is a symbol element y6, y7 belongs to, symbol element group Gy5 is a symbol element ys, y9 belongs to 'female position The meta-group Gy6 is a symbol element yi〇, yii belongs to. 135786.doc -162- 200937872 圊120 indicates that the LDPC code is an LDPC code with a code length N of 16200 bits and a compilation rate of 8/9. The further modulation method is 4096QAM, and the multiple ^^ is! : Distribution rules in the case. The distribution rule in Fig. 120 specifies group information (Gb2, Gyi, l), (Gb3, Gyi, l), (Gb3, Gy2, 2), (Gb3, Gy3, 2), (Gb3, Gy4, 2), (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, l). That is, the distribution rule in Figure 120 is as follows: According to the group collection information (Gb, Gy6, l), the error probability is the first! 1 bit of the code bit of the good © code bit group Gbi, assigned to the 1st bit of the symbol bit of the 6th good symbol bit group G y6 of the error probability; according to the group set information ( Gbz, Gyi, l), assigning the bit position of the code bit of the second good code bit group Gh of the error probability to the symbol bit of the error probability ^ good symbol bit group Gy丨 bit; according to the group set information (Gb3, Gyi, l), the bit of the code bit of the third good code bit group Gbs of the error probability is assigned to the error probability '" The symbolic bit group Gyi is the symbol bit! Bits; Sense® assigns the error probability to the error probability <2nd good according to the group set information (Gb3, Gy2, 2), the 2 bits of the code bit of the 3rd good code bit group Gh of the error probability 2 bits of the symbol element of the symbol element group Gy; 2 bits of the code bit of the code bit group Gbs with the wrong probability probability according to the group set information (Gb3, Gy3, 2) Yuan, assigned to the 2nd bit of the symbol bit of the 3rd good symbol bit group Gy3 of the error probability; according to the group set information (Gb3, Gy4, 2) 'The error probability 3rd code bit group The 2 bits of the code bit of the group Gh are assigned to the error probability '" Didouliang 135786.doc -163· 200937872 The 2nd bit of the symbolic element of the good symbolic group Gy*; Group assembly information (team-mountain, assigning the error probability to the 1st bit of the code bit of the 3rd good-horse group Gb3 to the error: the 5th good symbol-bit group Gb The meta-bit of the element; according to the group set information (GhGy6, 〗), assigns the i-bit of the code bit of the fourth-order error bit group Gb4 of the error probability to the symbolic bit with good error probability I 1 bit of the symbol group of the meta group Gy0; and the code bit of the code bit group Gb5 according to the group set information ((^,(^(1)' will be the wrong probability) 1 bit, assigned to the bit element of the symbol bit of the symbolic group of the fifth good symbol bit Gys of Fig. 120. Fig. 121 is an alternative example of the code bit element according to the allocation rule of Fig. 120. FIG. 121A shows an LDPC code in which the LDPC code is a code length N*162 〇〇 bit and a coding rate of 8/9. The further modulation method is 4〇96QAM, and the multiple b is 1 in accordance with the allocation rule according to FIG. The first example is the replacement of the code bit. ❹ The LDPC code is an LDpc code with a code length N of 16200 bits and a coding rate of 8/9. When the modulation mode is 4096QAM and the multiple b is 1, the solution is solved. The multiplexer 25 writes the code bits written in the memory 31 of the (162 〇〇 / (12 >< ι)) χ (12 x 1) bits in the wale direction x column direction in the course direction by 12 x 1 The (= mb) bit unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 reads the 12x1 (= mb) bits from the memory 3 j in accordance with the allocation rule of Fig. 120. Code bit to bn, for example Figure 1 The symbol bits yQ to yn assigned to the i2xi (= mb) bits of l (= b) symbols as shown in Fig. 21A are replaced by 135786.doc -164 - 200937872 for the position of 12xl (= mb) bits. The unit b〇 to bii. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit yio ', respectively, assigns the code bit b 1 to the symbol bit y 〇, and assigns the code bit b2 to The symbol bit y, ' assigns the code bit b to the symbol bit y2', assigns the code bit b4 to the symbol bit y3, and assigns the parity bit bs to the symbol bit y4, ❾ the code Bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, code bit bs is assigned to symbol bit y8, and code bit b9 is assigned to symbol bit y7. The code bit b 1 〇 is assigned to the symbol bit y 丨, and the code bit th ] is assigned to the symbol y9 for replacement. 121 FIG. 121B shows that the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 8/9, and the further modulation method is 4〇96qam, and the multiple b is 1 according to the distribution rule of FIG. The second example of replacement of code bits. According to FIG. 121B, the replacing unit 32 performs the following replacement for the code bits b() to bn of the i2xi (= mb) bit read from the § memory 31 according to the allocation rule of FIG. 12B. : assigning the code bit bG to the symbol bit yu, assigning the code bit ratio to the symbol bit yi, and assigning the code bit bz to the symbol bit y3, 135786.doc • 165· 200937872 B3 is assigned to the symbol bit y4, the code bit t»4 is assigned to the symbol bit y 5, the code bit b5 is assigned to the symbol bit y 〇, and the code bit 1?6 is assigned to the symbol Bit y2, code bit b7 is assigned to symbol bit y7, code bit b8 is assigned to symbol bit y9, code bit b9 is assigned to symbol bit y6, and beacon bit b 1 〇 Assigned to the symbol y! 〇, © assigns the tilde b 1 1 to the symbol y8. Figure 122 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 8/9, and a further modulation method is 4096QAM, and the code bit group and the symbol bit in the case where the multiple b is 1. Meta group. In this case, the code bits of the 12X 1 (= mb) bits read from the memory 3 1 are group-divided into 5 code bit groups Gbi according to the difference in error probability as shown in FIG. 122A. , Gb2, Gb3, Gb4, Gb5. 122A 'respectively' the code bit group Gbi code bit b〇 belongs to the 'code bit group Gb> 2 code bit unit bi belongs to the 'code bit group' (}b3 code bit h The code bit group GW is associated with the code bit 151(), and the code bit group Gb5 is the code bit bn. The modulation mode is 4096QAM, and the multiple b is 1, i2xl (= The mb) bit symbol is based on the difference in error probability, and can be grouped into six symbol bit groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6 as shown in Fig. 122B. As in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yQ, y! belongs to, and the symbol bit group Gy2 is a symbol bit 135786.doc -166- 200937872 yuan yz , y3 belongs to the 'character bit group Gw system symbol element belongs to, the symbol element group Gy* is the symbol element ye, y7 belongs, the symbol element group symbol s, y9 Affiliation, symbol group Gy6 is a symbol element yiQ, y" belongs to Fig. 123 shows that the LDPC code is an LDPC code with a code length n of 64800 bits and a coding rate of 8/9, and the modulation mode is further 4〇96QAM, allocation in the case of multiples Then, in the distribution rule of Figure 123, the group collection information © (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy252), (Gb3, Gy3, 2), (Gb3, Gy4) is specified. , 2), (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, 1). That is, the distribution rule in Figure 123 is defined as follows: According to the group collection information (Gb^Gy ^l), assigning 1 bit of the code bit of the error probability bit i-th good code bit group Gb to 1 bit of the symbol bit of the 6th good symbol bit group Gye of the error probability According to the group set information (Gb^Gy^l), the 1st bit of the code bit of the 2nd good code bit group Gb2 of the error probability is assigned to the error probability i-th good symbol bit group One bit of the symbol bit of the group Gy!; according to the group set information (Gb^Gy^l), the one bit of the code bit of the third good code bit group Gh of the error probability is assigned to Error probability ^^good symbol group Gy! symbol element bit; according to group set information (Gb3, Gy2, 2) 'The error probability third good code bit group Gb&gt 2 bits of the code bit of 3; assigned to the symbol of the wrong symbol group Gyz 2 bits of the bit; according to the group set information (Gb3, Gy3, 2) 'The error probability is 3rd good 135786.doc •167·200937872 code bit group Gfc»3 of the code bit 2 bits , assigned to the 2-bit of the symbol element of the third-perfect symbol group Gy3 of the error probability; according to the group set information (Gb3, Gy4, 2), the error probability third good symbol group The 2 bits of the code bit of the group Gt>3 are allocated to the 2 bit of the symbol bit of the symbol 4th group of the error probability group Gy4; according to the group set information (Gl>3, Gy5, l), assigning 1 bit of the code bit of the 3rd good code bit group Gbs of the error probability to 1 bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; According to the group set information (Gt > 4, Gy6, 1), the 1st bit of the code bit of the 4th good code bit group GW of the error probability is assigned to the 6th good symbol bit group of the error probability. One bit of the symbol bit of the group Gy6; and according to the group set information (Gb^Gy^l), assign the 1 bit of the code bit of the 5th good code bit group Gbs of the error probability to Error probability 5 Good symbol bits of the symbol bit group of Gys 1 yuan. Figure 124 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 123. That is, FIG. 124A shows that the LDPC code is an LDPC code having a code length of Ng 648 〇〇 bits and a coding rate of 8/9, and the further modulation method is 4 〇 96QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the distribution rule. The LDPC code is an LDpc code with a code length N of 64,800 bits and a coding rate of 8/9. In the case where the modulation method is 4096QAM and the multiple bgi, the direction of the multiplexer 25' in the wale direction X is (648〇〇/(ΐ2χΐ))χ (12 X 1) bits of the suffix 3 1 written code bits are in the horizontal direction, read in 12xl (= mb) bit units, and supplied To the replacement unit 32 (FIG. 16, FIG. 135786.doc-168-200937872), the replacement unit 32 b) the code bit b read from the memory of the memory 3i to the bn according to the allocation rule of FIG. 123 For example, as shown in FIG. 124A, the symbol bits y〇 to yn of the i2xi (= mb) bits allocated to 1 (=b) symbols are replaced by the code bits b to 12xl (= mb) bits. Bn. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y10, the code bit b to the symbol bit y 0, and the code bit b2 to the symbol bit y 1 . , the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b5 is assigned to the symbol bit y4, and the code bit b6 is assigned to the symbol bit Element y5, assigning code bit b7 to symbol bit y6, assigning code bit b8 to symbol bit y8, assigning code bit b9 to symbol bit y7, and assigning code bit b1Q to The symbol bit yn is assigned by assigning the code bit b ii to the symbol bit y9 '. Figure 124B shows that the LDPC code is an LDPC code with a code length N of 64800 bits and 7C* and a coding rate of 8/9. The further modulation method is 4096QAM, and the multiple b is 1 according to the code of the distribution rule of Fig. 123. The second example of the replacement of the bit. According to FIG. 124B, the replacing unit 32 performs the lowering of the code bits bG to bn, 135786.doc - 169 - 200937872 of the 12xl (= mb) bits read from the memory 31 in accordance with the allocation rule of FIG. 123, respectively. Replacement: assign code bit bG to symbol bit yi t, assign code bit b! to symbol bit y!, assign code bit b2 to symbol y3, and code bit b3 Assigned to the symbol bit y4, the code bit b4 is assigned to the symbol bit y 5 , the megabyte b5 is assigned to the symbol y 〇 , and the code bit b6 is assigned to the symbol y y 2 , 〇 The code bit b7 is assigned to the symbol bit y7, the exhaust bit be is assigned to the symbol bit y9, the code bit t>9 is assigned to the symbol bit y6, and the m-bit b 1 〇 is assigned to The symbol bit y is assigned to the symbol bit y8. Figure 125 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a depletion rate of 9/10, and the further modulation method is 4 〇 96QAM, and the megabit group and the symbol bit in the case of the multiple bAi Meta group. In this case, the code bits of the I2x1 (= mb) bits read from the memory 31 are grouped into 5 code bit groups GbhGbhGbhGb^ according to the difference in error probability as shown in FIG. 125A. Gbs. In FIG. 125A, respectively, the code bit group Gbi is a code bit, belongs to, the code bit group Gh is a code bit ratio, and the code bit group Gb3 is a code bit bz to b belongs to the 'code. The bit group Gb4 is a code bit!^. Affiliation, the code bit group Gb5 is a code bit b! The modulation mode is 4096QAM, in the case of multiples, 12xl (post) 135786.doc -170. The symbol of the 200937872 bit is based on the difference in error probability, as shown in Fig. 125B, the group can be divided into 6 symbols. Bit groups Gyi, Gy2, Gy3, Gy4, Gy5, Gy6. In the case of FIG. 125B', as in the case of FIG. 95B, respectively, the symbol bit group Gy! is a symbol bit yG, yi belongs to, and the symbol bit group Gy2 is a symbol bit y2, ys belongs to The symbol element group GY3 is a symbol element y4, y5 belongs to, the symbol element group Gy is a symbol element y0, y7 belongs to, the symbol element group Gy5 is a symbol element 丫8, It belongs to the 'female element group Gy6 system symbol element yiQ, yu belongs. Figure 126 shows an LDPC code which is an LDPC code having a code length N of 64,800 bits and a coding rate of 9/10, and a further modulation method of 4 〇 96qA]vi, in the case of a multiple. In the allocation rule of Figure 126, group aggregation information (Gb2, Gy1, l), (Gb3, Gy1, l), (Gb3, Gy2, 2), (Gb3, Gy3j2), (Gb3, Gy4, 2) are specified. , (Gb3, Gy5, l), (Gb4, Gy6, l), (Gb5, Gy5, l). That is, the allocation rule in Figure 126 is defined as follows: According to the group set information (Gth'Gye'l), the error probability jth good code bit is allocated to the 1 bit of the code bit of the group Gb丨. Give the 1st bit of the symbol bit of the 6th good symbol bit group Gy0 of the error probability; according to the group set information (Gb^Gy^l), the second good code bit of the error probability is the group Gbz The 1 bit of the code bit is assigned to the bit error element of the error probability bit group; Gy, according to the group set information (Gb3, Gyi, l), Assigning 1 bit of the code bit of the 3rd good code bit group Gh of the error probability to the 1st bit of the symbol bit of the first bit of the error probability group Gy!; 135786 .doc -17! · 200937872 According to the group set information (Gb3, Gy2, 2), the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability is assigned to the 2nd good error probability. 2 bits of the symbol bit of the symbol element group Gy2; according to the group set information (Gb3, Gy3, 2), the 2nd bit of the code bit of the 3rd good code bit group Gb3 of the error probability yuan, The second bit of the symbol bit assigned to the third bit symbol group Gy3 of the error probability; the third bit of the error probability group according to the group set information (Gb3, Gy4, 2) The 2 bits of the code bit of Gb3 are allocated to the 2nd bit of the symbol bit of the 4th good symbolic group Gy4 of the error probability; according to the group set information (Gb3, Gy5, l), Assigning 1 bit of the code bit of the 3rd good code bit group Gb3 of the error probability to the 1st bit of the symbol bit of the 5th good symbol bit group Gy5 of the error probability; The set information (Gb4, Gy6, l) assigns the 1st bit of the code bit of the 4th good code bit group Gb4 of the error probability to the symbol of the 6th good symbol bit group Gy6 of the error probability. 1 bit of the bit; and according to the group set information (Gb5, Gy5, l), the 1st bit of the code bit of the code bit group Gb5 of the 5th good error probability is assigned to the error probability 5th A good one of the symbol bits of Gy 5 of the symbol group. Figure 127 is a diagram showing an alternative of the code bits in accordance with the allocation rule of Figure 126. That is, FIG. 127A shows that the LDP C code is an LDPC code having a code length N of 64800 bits and 7 〇 and a coding rate of 9/10, and the further modulation method is 4096QAM, and the multiple b is 1 according to FIG. The first example of the replacement of the code bits of the allocation rule.

The LDPC code is an LDPC with a code length N of 64,800 bits and a coding rate of 9/10. 135786.doc -172- 200937872 code 'When the modulation mode is 4096QAM and the multiple b is 1, the multiplexer 25 is used. The code bits written in the memory 31 of the (64800/(12x1)) x (12x 1) bits in the wale direction X direction are in the course direction, and are read out in 12xl (= mb) bit units. And supplied to the replacement unit 32 (FIG. 16, kj circle 17). The replacement unit 3 2 reads the code bit bQ from the 12x1 (= mb) bit of the memory 3 1 according to the allocation rule of FIG. Bn, for example, the symbol bits y❹ to yn of 12xl (= mb) bits allocated to l (=b) symbols as shown in FIG. 127A, in place of the code bits b of 11 (= mb) bits Bn. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 分别10, the code bit b1 to the symbol bit y, and the code bit b2 to the symbol yj. , the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, the code bit b 5 is assigned to the symbol bit y 4, ❹ the code bit is assigned to the symbol The bit position y5 assigns the code bit b7 to the symbol bit y6, the code bit bg to the symbol bit y8, and the code bit b9 to the symbol bit y7, and the code bit b 1 〇 is assigned to the symbol bit y丨丨, and the code bit b 1 1 is assigned to the symbol bit y9 for replacement.囷 127B indicates that the LDPC code has a code length N of 64,800 bits and a coding rate of 135,786.doc • 173 - 200937872 9/10 of 1^卩 (: code, further modulation is 4096 (^) ^, multiple 1 In the case of 1 , the second example 0 of the replacement of the code bit according to the allocation rule of FIG. 126 is as follows. According to FIG. 127B, the replacing unit 32 is for the 12x1 read from the memory 31 according to the allocation rule of FIG. The code bits pG to bn of the (= mb) bit are respectively replaced by the following: the code bit bG is assigned to the symbol bit y! i, and the code bit b is assigned to the symbol bit y! © assign code bit b2 to symbol bit y3, code bit b3 to symbol bit y4, code bit b4 to symbol bit y5, and code bit b5 to symbol bit Element y, assigning code bit b6 to symbol bit y2, assigning code bit b7 to symbol bit y7, assigning code bit b8 to symbol bit y9, and assigning code bit b9 to The symbol bit y6, ® assigns the code bit 1)1() to the symbol bit 丫10, and the code bit bi! to the symbol bit y8. As described above, as a replacement process of the new alternative, six types of code length N of 64,800 bits and encoding ratios of 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are respectively described. The LDPC code is replaced by 12 types in the case of modulation of two types of 1024QAM and 4096QAM, and the code length N is 16,200 bits, and the coding rate is 2/3, 3/4, respectively. The LDPC code of the 5/5, 5/6, and 8/9 types is replaced by the 〇 〇 〇 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 135 In the total description of the type 22 replacement processing, the 22-type replacement processing is an alternative to the replacement code bit, and can be performed by using any of the four types of replacement methods, for example, by using four types of replacement methods. That is, in the case of an LDPC code having a modulation code length of 64800 or 16200 bits and a coding rate of 3/4, 4/5 or 5/6 in 1024QAM, the replacement processing can be expressed, for example, as shown in FIG. The alternatives are as follows: assign the code bit b〇 to the symbol bit y6, assign the code bit b! to the symbol bit y 4, and assign the code bit b2 to the symbol bit y8, The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y, the code bit b5 is assigned to the symbol bit y2, and the code bit b6 is assigned to the symbol bit y!, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y9, and the code bit b9 is assigned to the symbol bit y7. Moreover, in the case of an LDPC code having a code length N of 64800 or 16200 bits and a coding rate of 3/4, 4/5 or 5/6 in 4096QAM, the replacement processing can be expressed, for example, as shown in FIG. 103A or the like. The alternatives are as follows: assign the code bit b〇 to the symbol bit y8, the code bit b! to the symbol bit y 〇, and the code bit b2 to the symbol y6, the code Bit b3 is assigned to symbol bit y!, 135786.doc -175- 200937872 assigns code bit b4 to symbol bit y4, code bit b5 to symbol bit y5, and code bit b6 Assigned to the symbol bit y2, the code bit b7 is assigned to the symbol bit y3, the code bit b8 is assigned to the symbol bit y7, and the code bit b9 is assigned to the symbol bit y! 〇, The code bit b! 〇 is assigned to the symbol bit y 1!, and the code bit b!! is assigned to the symbol bit y 9.

Further, an LDPC code having a modulation code length N of 64800 or 16200 bits, a coding rate of 2/3 or 8/9, or an LDPC having a code length N of 64,800 bits and an encoding rate of 9/10 is used. In the case of a code, the replacement processing can be performed as follows, for example, in the alternative manner shown in FIG. 64A or the like: assigning the code bit bG to the symbol bit y8 and the code bit b to the symbol bit y 〇, The code bit b2 is assigned to the symbol bit y], the code bit b3 is assigned to the symbol bit y2, the code bit b4 is assigned to the symbol bit y3, and the code bit b5 is assigned to the symbol bit The element y4 assigns the code bit b6 to the symbol bit y6, the code bit b7 to the symbol bit y5, the code bit b8 to the symbol bit y9, and the code bit b9 to the symbol The meta-bit y7. Moreover, the LDPC code with a code length N of 64800 or 16200 bits, a coding rate of 2/3 or 8/9, or a code length N of 64800 bits, 409678.doc -176·200937872 code rate is modified by 4096QAM. In the case of an LDPC code of 9/10, the replacement processing can be performed as follows, for example, in the alternative manner shown in Fig. 97A, etc.: The code bit bG is assigned to the symbol bit y 1 〇, and the code bit b! For the symbol bit y 〇, the code bit b2 is assigned to the symbol bit y!, the code bit b3 is assigned to the symbol bit y2, and the code bit b4 is assigned to the symbol bit y3, and the code is assigned Bit b 5 is assigned to symbol bit y 4, 码 code bit b6 is assigned to symbol bit y5, code bit b7 is assigned to symbol bit y6, and code bit b8 is assigned to symbol bit The element y8 assigns the code bit b9 to the symbol bit y7, the code bit b! 〇 to the symbol bit y!!, and the code bit b η to the symbol bit y 9. In the above, the new replacement method will be described with respect to the case where the modulation method is 1024QAM and the case of 4096QAM, and the configuration of the symbol (corresponding signal point) of each modulation method ® will be described below. Fig. 128 is a diagram showing the arrangement on the IQ plane of 1024 symbols (corresponding signal points) in the case where 1024QAM is performed by the quadrature modulation unit 27 of Fig. 8. That is, Fig. 128 shows a method of arranging the arrangement of symbols of 1024QAM inductively from the configuration of the symbol of 256QAM of DVB-T.2. Further, in Fig. 128, (i, q) indicates the coordinates (I coordinate and Q coordinate) on the IQ plane of the symbol. Moreover, C256(i,q) denotes a coordinate (i is also referred to as a symbol number) of a 256-symbol 135786.doc-177-200937872 element of 256QAM which is serially attached to the coordinate (i). , q) The position of the symbol (attached to the symbol) symbol number. Hereinafter, the symbol of 256QAM located at the position of the coordinate (i, q) is also referred to as the Cwdq) symbol. Further, C1024(i, q) is a symbol number indicating a symbol located at a position of a coordinate (i, q) among 1024 symbols of 1024QAM. Hereinafter, the symbol of 1024QAM located at the position of the coordinate (i, q) is also referred to as the C1〇24(i,q) character 7t 0 ❹ Now, if all 256 symbols of 256QAM are moved in parallel on the iq plane In the first quadrant, the C256(i,q) symbols of the 256QAM after the parallel movement become the CiV24(i,q)=C256(i,q) symbols of 1024QAM. Further, if 256 symbols of 25 6QAM in the first quadrant are moved in parallel, for the I-axis symmetric movement, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C of the 1024QAM. 024(i,-q)=C256(i,q)+256 symbols. Moreover, if 256 ® symbols of 256QAM that have been moved in parallel in the first quadrant are moved symmetrically about the Q axis, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C of 1024QAM.丨〇24(-i,q)=C256(i,q)+ 256x2 symbols. Further, if 256 symbols of 25 6QAM have been moved in parallel in the first quadrant, and the symmetric movement of the origin, the C256 (i, q) symbols of the 256QAM after the symmetric movement become the C1024 of 1024QAM ( -i, -q) = C256(i, q) + 256x3 symbols. In addition, with respect to the above Xth symbol, the value of X in the binary representation is 135786.doc •178- 200937872 The value of the symbol (signal point to which the symbol is mapped). For example, in the case of C256(i,q)=25, the symbol value of the Cwdq) symbol is 0001 1001 B (B indicates that the previous value is 2 in only), and for example, Ci〇24(i,q) In the case of =823, the symbol value of the 'Ci〇24(i,q) symbols is 1100110111B. Further, for example, the 256th 2th symbol (i, q > 0) of the second quadrant (I < 0, Q > 0) is located at the C256 of 256 symbols τ ο of 256 QAM that has been moved in parallel in the first quadrant. (i, q) symbols, for the position of the q-handle after Ο line-symmetric movement 'The Ci_24(-i,q)=c;25eii,q>+256x2 symbolic value beer The upper 2 bits of the value of Czwdq) are represented by the 2-bit, and the value of 2 of 256x2, that is, the value of 10B is added by the 2-bit. In 1024QAM, the number m of 1 symbol is 10, and the symbol of 1 symbol is represented from the highest bit (yojb· · y6, y7, y8, y9) 〇 for example Ci〇24(i,q In the case of =823, the symbolic value of the 'Ci〇24(i,q) symbols, that is, the 10-bit symbolic element (y〇, yi, y2, y3, y4, y5, y6, Y7, y8, y9^ ^ (1,1,M,1,1,G,1,1,1). Then, as illustrated in Fig. 62 to Fig. 94, respectively, the symbol bit y〇^ It belongs to the symbol element group Gy!, the symbol element y^y3 belongs to the symbol element group Gyz, and the symbol element y^y5 belongs to the symbol element group, and the symbol element ye, y7 It belongs to the symbol bit group Gy4, and the symbol bit y8, y9 belongs to the symbol bit group Gy5. Further, the subscript j belongs to the smaller symbol group of the symbol group. The better the probability (the resistance to the error is). 135786.doc -179· 200937872 Figure 129 shows the 4096 symbols (corresponding signal points) of the 4096QAM with the quadrature modulation unit 27 of Fig. 8 In the IQ plane, the configuration on the IQ plane. In addition, in Figure 129, C4〇96(i,q) represents 4〇96 characters of 4096QAM. The symbol number of the symbol located at the position of the coordinate (i, q). Below, the symbol of 4096QAM located at the position of the coordinate (i, q) is also called the C4〇96(i,q) symbol. Now, if all 1024 symbols of 1024QAM described in FIG. 128 are moved in parallel in the first quadrant on the IQ plane, the C1024(i, q) symbols of the 1024QAM after the parallel movement become 4096QAM. The first C4096(i,q) = Cl〇24(i,q) symbols. Further, if the 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically for the I-axis, the symmetric movement The C 024 (i, q) symbols of the subsequent 1024QAM become the C4096 (i, -q) = C1C) 24 (i, q) + 1024 symbols of 4096QAM. Moreover, if 1024 symbols of 1,024QAM that have been moved in parallel in the first quadrant are moved symmetrically about the Q axis, the C1024(i,q) symbols of the 1024QAM® after the symmetric movement become the first of 4096QAM. C4096(-i,q)= C1024(i,q)+l〇24x2 symbols. Further, if 1024 symbols of 1024QAM that have been moved in parallel in the first quadrant are moved symmetrically to the origin, the C!〇24(i,q) symbols of the 1024QAM after the symmetric movement become the first of 4096QAM. C4〇96(_i,-q)= C 1 024(i,q)+l〇24x3 symbols. The symbol bits of the symbols of 1024QAM (Fig. 128) and 4096QAM (Fig. 129) are also the same as those described in Fig. 12, and there are strong bits and weak 135786.doc -180-200937872 potential bits. Figs. 130 to 133 show the results of the simulation of the BER (Bit Error Rate) in the case where the replacement processing of the new replacement method has been performed and the case where the replacement processing has not been performed. That is, FIG. 130 shows that an LDPC code having a code length N of 16,200, a coding rate of 2/3, 3/4, 3/5, 5/6, and 8/9 is used as a target, and 1024QAM is used as a modulation method. BER in case. FIG. 131 is a view showing an LDPC code having a code length N of 64,800, a coding rate of 2/3, 3/4, 〇3/5, 5/6, 8/9, and 9/10 as a modulation method. BER in the case of 1024QAM. FIG. 132 is a diagram showing an LDPC code having a code length N of 16,200, a coding rate of 2/3, 3/4, 3/5, 5/6, and 8/9 as a target, and 4096QAM is used as a modulation method. BER. Figure 133 shows an LDPC code with a code length N of 64800 and a coding rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10 as the object, and 4096QAM is used as the modulation method. The BER in the case. ❹ In addition, in FIGS. 130 to 133, the multiple b is 1. Further, in Figs. 130 to 133, the horizontal axis represents Es/N 〇 (signal power to noise power ratio per symbol), and the vertical axis represents BER. Further, the solid line indicates the BER in the case where the replacement processing of the new replacement method has been performed, and the dotted line indicates the BER in the case where the replacement processing is not performed. From Fig. 130 to Fig. 133, the replacement processing of the new alternative is compared with the case where the replacement processing is not performed, and the BER is increased, so that the resistance to errors is improved. 135786.doc -181 - 200937872 In addition, in the present embodiment, for convenience of explanation, the code bit from the memory (4) is used as the object for the odor treatment, but the replacement processing can be controlled by The memory is written or read by it. That is, the 'replacement processing can be performed by, for example, controlling the address of the read code bit (read address)' from the memory bit in the order of the replaced code bit. ❹ However, although FIG. 62 to FIG. 127 illustrate a new alternative as a replacement method of the code bit in the case where the multiple 13 is 1, the multiple of 1 is a direct replacement of the code bit in the case of 丨The replacement of the code bits in the case where the value of the multiple b*2 or more (which must be the approximate number of the code length N) is utilized. Referring to Fig. 134 and Fig. 135, the replacement of the symbols in the case where the multiple 1) is 1 is directly used for the replacement of the code bits in the case where the multiple b is a value of 2 or more. Figure 134 is a diagram for explaining the replacement of the code bits in the case where the multiple b is 1. Further, in Fig. 134 (the same applies to Fig. 135 to be described later), the code length N of the LDPC code is set to, for example, 24 bits for simplification of explanation. Further, the modulation method is, for example, 4 (=m) bits of a code bit as one symbol and mapped to QPSK of any of the four signal points. When the code length N is 24 bits, the multiple b is 1, and the 4 (=m) bits of the code bit become 1 symbol, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) is Four wales containing 4x l (= mb) bits in the horizontal direction are stored, and 24/(4xl) bits are stored in the wales. Now, if the code bit of the 24-bit LDPC code is represented from the beginning as 135786.doc -182- 200937872 ~u, C, a, · · . . , v, w, x, then the 24-bit LDpc code The code bits & to the four wales of the memory 3 , are sequentially written in the wale direction as shown in FIG. 134A. That is, FIG. 134A shows the state of writing the "bit LDPC code" of the four wales of the memory 31. The code is written in the third wales of the four wales of the memory 31, respectively. The bits a, b, C, d'e, f' are written with the code bits g, hijk in the second vertical line, and the code bits m, n, 〇, p are written in the third vertical line. , q, r ' is written in the fourth vertical line with code bits S, t, U, V, W, X. In addition, in Figure 134 (also in Figure 135), in order to easily understand the code bits from the vertical The reading order of the lines is shown below the wales with the code bits first written. If the writing of the 24-bit code bits & to the end of the memory 31 is completed, the memory is written in the memory. The code bit aix of 31 is in the course direction, and is read out in 4x1 (= mb) bit units and supplied to the replacement unit 32 (Fig. 16, circle 17). The replacement unit 32 is performed from the memory 3 The code bit bi of the 4>l (= mb) bit read in the course direction, for example, the code bit element assigned to the symbol bit yi of 1 (=1> symbol) as shown in FIG. 134B Replacement of bi. That is, 'Fig. 134B shows that the 4-bit code bit b is assigned to one symbol. An alternative to the bit yi. The following replacement is performed in FIG. 134B': the code bit b〇 read from the first vertical line is assigned to the symbol bit, and the code bit from the second vertical line is read. Bi is assigned to the symbol bit 丫, 'The code bit 匕 read from the 3rd ordinate is assigned to the symbol ys ′', and the code bit b3 read from the 4th row is assigned to the symbol 135786. Doc -183- 200937872 Bit y〇〇...code...symbol... The result of replacing the 4xl (= mb) bit of the coded bit heart read from the memory (4) in the horizontal direction according to the replacement mode of the graph test One symbol is formed by the symbol bits y 〇, y 丨, y2, y3 shown in Fig. 134C. That is, Fig. 134C shows the replacement of Fig. 134A by replacing the replacement pattern according to Fig. U4B. The symbol obtained by the written code bit.

For example, in Figure 134A, in the first! The code bits a, g, m, s (arranged) written in the following column (_: course) are replaced by the replacement mode according to Fig. 34B, as shown in Fig. 134C. At the bottom, the symbol of the arrangement of the symbol bits s, g, a, m is obtained. Further, for example, in FIG. 134A, the code bits b, h, n, t written in the second column from the bottom of the first to fourth wales are replaced by the replacement mode according to FIG. 134B. Under the 134C, the second symbol is shown, which becomes the symbol of the arrangement of the symbol bits t, h, b, and n. Figure 135 is a diagram illustrating the direct use of the multiple of Figure 134! In the case where the multiple of the replacement mode of the code bit b is 2, the replacement of the code bit is shown. Further, in Fig. 135, the point where only the multiple b is not i and is 2 is different from the case of Fig. 134. Therefore, the code length N of the LDPC code is 24 bits, and the 4 (=m) bits of the modulation mode code bit are mapped as one symbol to the pPSK of any of the four signal points. When the code length N is 24 bits, the multiple b is 2, and the 4 (=m) bits of the code bit become j symbols, the memory 31 of the multiplexer 25 (FIG. 16, FIG. 17) is 135786.doc •184· 200937872 Contains 8 vertical lines that store 4x2 (=mb) bits in the horizontal direction and 24/(4χ2) bits in the longitudinal direction. The 24-bit LDPC code code bit & χ is the 8 vertical lines of the memory 3 ’ as shown in Fig. 13 5 依次 in the wale direction. That is, Fig. 135A shows the state of writing to the 24-bit LDPC code of the eight wales of the memory 31. In addition, in FIG. 135A', for the sake of convenience, eight vertical lines are referred to as a first vertical line, a third vertical line, a fifth vertical line, a seventh vertical line, a second vertical line, a fourth vertical line, and a sixth vertical line. The order of the line and the eighth line is shown. In FIG. 5, respectively, the first vertical line of the eight vertical lines of the memory 31 is written with the code bits a, b, c, and the second vertical line is written with the code bits d, e, f, Write the code bit g, h, i in the third vertical line, write the code bit jk in the fourth vertical line, and write the code bit m, n, 〇 in the fifth vertical 于 in the sixth vertical line Write code bits p, q, r, write code bits s, t, u in the 7th ordinate, and write the code bits in the 8th ordinate if the code bits for the 24-bit of the memory 31 The writing of the element 3 to 乂 is finished, and the code bit & 乂 is written in the course direction, read in 4x2 (= mb) and is supplied to the replacing unit 32. (Fig. 16 and Fig. 17) The 〇 replacing unit 32 performs 4 2 (-mbhi 码 code bit 卜, which is read from the memory 31 in the course direction, for example, as shown in Fig. 35β, and is assigned to continuous 2 (b). Replacement of the code bit bi of the symbol element yi of the symbol. That is, Fig. 135B shows an alternative example of assigning the code bit bi of the 8-bit to the symbol bit yi of two consecutive symbols. Here, in Figure 5, the symbolic element is the symbolic element in the 2 symbols of the successor, and the symbolic element is ~ The symbolic symbol of the second symbol in the second symbol 135786.doc -185· 200937872. In Fig. 135B, the code bit in the case where the multiple b shown in Fig. 134B is 1 is directly used. Replacement mode. That is, in Fig. 135B, the replacement of the following replacement mode is respectively performed: the code bit b〇 read from the first vertical line is assigned to the symbol bit yz, and the code position from the third vertical line is read. The element bz is assigned to the symbol bit yi, and the code bit feu read from the fifth vertical line is assigned to the symbol bit ys, and the code bit from the seventh vertical line is read and assigned to the symbol bit yG; The replacement mode (the arrangement mode of the arrow in Fig. 135B) is the same as the replacement mode of the code bit in the case where the multiple b is 1 shown in Fig. 134B, and the replacement mode is replaced by the following replacement mode in Fig. 135B. : assigning the code bit bi read from the second vertical line to the symbol bit y0, and assigning the code bit t > 3 read from the fourth vertical line to the symbol bit ys, which will be read from the sixth vertical line The code bit bS is assigned to the symbol bit y? 'The code bit element read from the 8th vertical line is assigned to the symbol bit y4; the replacement mode is also shown in FIG. 134B. The replacement mode of the code bits in the case where the multiple 6 is i is the same. 码 The code bits of the 4x2 (= mb) bits read from the memory 31 in the course direction ^ 〇, 1 > 1, 52 , 133, 匕4山5, 匕6, 137 are replaced by the replacement mode of Fig. 1358, and the result is obtained by the symbol y(), y1, y2, y3, y4, y5, y6, y7 shown in Fig. 135C. Two consecutive symbols are constructed. That is, 'FIG. 135C shows a symbol obtained by replacing the code bit written as shown in FIG. 135A by the replacement mode of FIG. 135B. For example, in FIG. 135A, the positions a, g, m, s, d, j, p, v written in the lowermost column of the first to eighth wales are by the arrangement according to FIG. 135B. Replacement mode 135786.doc -186- 200937872 Replace 'to the symbol shown in the bottom of Figure 135C, the symbol of the arrangement of the symbol bit ^ claw and the symbol of the symbol element v, j, d, p . Moreover, for example, in Fig. 135A, the code bits b, h, n, t, e, k, q, w written in the second column are counted under the first to eighth vertical lines, according to Fig. 135B. The replacement mode is replaced by 'in order to be the second one as shown in Fig. 135C, and the arrangement of the symbols of the symbol bits t, h, b, n and the arrangement of the symbol bits w, k, e, q Fu Yuan. As can be seen from the comparison of FIG. 134C and FIG. 135C, if the replacement of the code bit © when the multiple bg2 is used in the replacement mode in the case where the multiple b is 1, the multiple of b is obtained. A symbol consisting of an arrangement of the same symbol bits (code bits). Therefore, when the replacement of the code bit in the case where the multiple b is 2 is directly used in the case of the substitution mode in the case where the multiple b is 1, the tolerance to the error and the multiple b are caused by the replacement. *〗 The situation is equally tolerant. Further, the order in which the symbols consisting of the same symbol bit arrangement can be obtained is that the case where the multiple b is 1 may be different from the case of 2. Next, as described above, a specific example of replacement of the code bit in the case where the multiple b of the replacement mode in the case where the multiple 1 is 1 is used is directly used will be described. Figure 136 is a diagram showing an alternative example of the LDPC code in which the LDPC code is 162 〇〇 bit code rate 2/3 LDPC code 'in the step modulation mode is 1 〇 24QAM, in the case of a multiple. The replacement of the code bits in the case where the multiple b of Fig. 136 is 2 is directly replaced by the code bit of Fig. 64A in which only the multiples are different. Therefore, the replacement of the code bits of FIG. 136 is in accordance with the allocation rule of FIG. 135786.doc -187- 200937872 LDPC code is an LDPC code with a code length N of 16200 bits and a coding rate of 2/3. In the case of further modulation mode 1024QAM and multiple b&2, in the multiplexer 25, The code bit written in the memory 31 in the wx direction x direction (1.6 〇〇 / (1 〇χ 2)) χ (10 x 2) bits is in the course direction, l〇x2 (= mb) The bit unit is read out and supplied to the replacement unit 32 (Figs. 16, 17). The replacing unit 32 is configured to assign the code bits 13 from the 1⁄2 bit position of the memory 31 to be, as shown in FIG. 136, to 2 consecutive (=b) one ❹i〇x2 (= mb). The bitwise symbol of the bit is ~ to y9, and the code bit of the two l〇x2 (= mb) bits is "to !^. That is, the replacement section 32 respectively sets the code bit b" Assigned to the symbol bit y8, the code bit b2 is assigned to the symbol bit y 〇, the code bit b4 is assigned to the symbol bit y 丨, and the megabyte t>6 is assigned to the symbol y2 , the code bit is assigned to the symbol bit y3, the code bit b 1 〇 is assigned to the symbol bit y 4 , the code bit b b 2 is assigned to the symbol bit y 6 , and the code bit is assigned b 14 is assigned to the symbol bit y 5 , the code bit b 16 is assigned to the symbol bit y 9, the code bit b 8 is assigned to the symbol bit y 7, and the code bit bi is assigned to the symbol Meta-bit; ^8, assigning code bit b3 to symbol bit y丨〇' assigning code bit bs to symbol bit y 11, 135786.doc -188- 200937872 assigning code bit b7 to The symbol bit 丫12 assigns the code bit b9 to the symbol bit 713, and assigns the code bit bu to the symbol y14. The code bit b丨3 is assigned to the symbol bit y_i6, the code bit b 1 5 is assigned to the symbol bit y丨5, and the code bit b 7 is assigned to the symbol bit y丨9, The code bit b 9 is assigned to the symbol bit y 丨 7 and the two are replaced.

❹ In addition, in FIG. 136, the replacement pattern of the code bits b〇, b2, b4, b6, b8, bl〇, bi2, bi4, bi6, bi8 and the code bit b丨, 1) 3, 1 > 5, 137 The replacement modes of 1) 9, 1) 丨丨, 1313, 1) 15, 1) 丨 7, 15 丨 9 are both identical to the replacement mode of the code bits bo to bp of Fig. 64A. Figure 137 is a diagram showing that the LDPC code is an LDPC code having a code length of 1^ of 648 bits and a coding rate of 2/3. Further modulation is 1〇24 (^八河, multiple ^^ is] An alternative to the code bit. The replacement of the code bit in the case where the multiple b of Fig. 137 is 2 is directly replaced by the code bit of Fig. 67A in which only the multiple b is 1; therefore, Fig. 137 The replacement of the code bit is in accordance with the distribution rule of the figure. LDPC is the code length of 6 side bits, the coding rate is 2/3 [Zema, the step-step modulation mode is 1024QAM, multiple (4)) Multi-H25 in the wale direction, the direction of the horizontal direction is (6-small (1〇Χ2)-bit memory 31 written by the code bit in the course direction, read in 1〇X2(=mb) bit units The replacement unit 32 is supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to read the code 135786.doc 200937872 from the 10><2 (=11113) bits of the memory 31 to B19, as shown in FIG. 137, is assigned to the manner of the symbol bits y〇 to yi9 of the consecutive 2 (=b) symbols of l〇x2 (= mb) bits, replacing 1 〇 x2 (= mb) The code bits bG to b19 of the bit. That is, the replacement unit 32 is respectively The code bit bG is assigned to the symbol bit y8, the code bit b2 is assigned to the symbol bit y, the code bit b4 is assigned to the symbol bit y 1, and the code bit b6 is assigned to the symbol Bit y2, ❹

The code bit b8 is assigned to the symbol bit y3, the code bit b! 〇 is assigned to the symbol bit y 4 , and the code bit b 12 is assigned to the symbol bit y 6, and the code bit b 14 Assigned to the symbol bit y 5, the code bit b! 6 is assigned to the symbol y 9, the code bit b! 8 is assigned to the symbol y 7, and the code bit b! is assigned to the symbol Meta-bit y 18, assigning code bit b3 to symbol bit y 1 〇, assigning code bit b5 to symbol bit y 11, assigning code bit b7 to symbol bit y 12, The code bit b9 is assigned to the symbol bit y 13, the code bit bu is assigned to the symbol bit y 14, the code bit b13 is assigned to the symbol bit y!6, and the code bit b! 5 is assigned. The symbol bit y 15, the code bit b] is assigned to the symbol y 19, and the code bit b 19 is assigned to the symbol y 17, 135786.doc -190 - 200937872 for replacement. Both the #t!Iir'^bl, b3, b5^ modes are consistent with the replacement pattern of the code bits recognized to % in Fig. 67A. Figure m shows an LDPC code which is an LDPC code with a code length of 162 bits and a bit rate of 3M, and a further modulation method of 1 〇 24qam, a multiple of _. ❹

The replacement of the code bits in the case of the multiple of 4 in Fig. 138 is directly used. The replacement of the code bits of Fig. 70A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 138 is in accordance with the allocation rule of FIG. The LDPC code code length N is 16200 bits, and the coding rate is 3/4. The ldpC code is adjusted to 1024QAM and the multiple b is 2. In the case of the multiplexer 25, the direction of the X direction is in the direction of the X direction. The code bits written for the memory 31 of (162 〇〇 / (1 〇χ 2)) χ (10 X 2) bits are in the course direction, read out in units of 10x2 (= mb) bits, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to be ' read from the i〇X2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. The symbol y of the x2 (= mb) bit. In the manner of y19, the code bits bG to b19 of 10x2 (= mb) bits are replaced. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y 6, respectively, assigns the code bit b to the symbol bit y4, and assigns the code bit to the symbol bit ys, 135786. .doc -191 - 200937872 Assigning code bit b6 to symbol bit y5 ' 分配 Assigning code bit b 8 to symbol bit y 〇 ' Assigning code bit 131 () to symbol bit y2 ' Assigning code bit b12 to symbol bit yi ' assigning code bit b14 to symbol bit y3 ' assigning code bit b 16 to symbol bit y 9, assigning code bit b18 to symbol Bit y7' assigns code bit b! to symbol bit yl6, code bit b3 to symbol bit y14, code bit b5 to symbol bit 18' and code bit b7 Assigned to the symbol bit y15, the code bit b9 is assigned to the symbol bit y1 〇, the code bit b ! 1 is assigned to the symbol bit y 5 2 , and the megabyte b! 3 is assigned to the symbol Bit y 1 ,, assign code bit 1^5 to symbol bit 丫13, assign code bit b!7 to symbol bit 719, and assign code bit 1^9 to symbol bit 717, and replace it. In addition, in Figure 138 ^^^D〇, b2, b4, b6, b8, bl〇b, the replacement mode and the mbit bl, b3, b5, b7, b9, bii, bi3, bi5'b2, Abl6, The bl8 mode is replaced with the code bit % to % of FIG. 70A: 'The replacement of Equation 7 II 139 indicates that the LDPC code is LDPC* whose code length N is "_bit I-: Markov rate is 3/4" 'The further modulation is i〇24qam, and the substitution of the code bit in the case of multiple 。. 135786.doc -192- 200937872 The substitution of the mega-bit in the case of the multiple b of Figure 139 is directly The replacement of the code bits of Fig. 73A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 139 is in accordance with the allocation rule of Fig. 72. The LDPC code length n is 64800 bits, coding When the LDpc code rate of 3/4 is 1024QAM and the multiple b is 2, in the multiplexer 25, the direction of the x direction in the wale direction is (64800/(10χ2)) χ (10x2). The code bits written by the memory 31 of the bit are read in units of l〇x2 (= mb) bits in the course direction and supplied to the replacement unit 32 (Fig. 16, Fig. 17). To read the code from the memory 3121 〇 x 2 (= mb) bits Bits 1)() to 1)19, as shown in FIG. 139, are assigned to the symbolic bits yQ to ^ of the consecutive 2 (=b) symbols of l〇x2 (= mb) bits. Replace the code bits of l〇x2 (= mb) bits ~ to !^. That is, the 'replacement unit 32 assigns the code bit bG to the symbol bit y6, respectively, and assigns the code bit b2 to the symbol bit. Element y4, code bit b4 is assigned to symbol bit y8, code bit 136 is assigned to symbol bit y5, and code bit b8 is assigned to symbol bit y 〇, code bit b1() Assigned to the symbol bit y2, the code bit 13>2 is assigned to the symbol bit y!, the code bit b14 is assigned to the symbol bit y3, and the code bit b16 is assigned to the symbol bit y9 ' The code bit b18 is assigned to the symbol bit y7, 135786.doc • 193- 200937872 The code bit b 1 is assigned to the symbol bit y] 6, and the code bit b is assigned to the symbol y 丨4. Assign code bit b5 to symbol bit y丨8, assign code bit b7 to symbol bit y丨5, assign code bit b9 to symbol bit y1〇, and code bit b 1丨 is assigned to the symbol bit y丨2, the code bit b 1 3 is assigned to the symbol bit y丨1, and the code bit b 1 5 is assigned to The meta-bit y丨3, © assigns the code bit bp to the symbol bit 丫19, and assigns the code bit b 1 9 to the symbol bit y! 7, and replaces it. Further, in Figure 139, the code Replacement patterns and code bits of bits b〇, b2, b4, b6, b8, b1(), b12, b14, b16, b18 1)1,1)3,1>5,137,59,1)11 The replacement mode of 1) 13, 1315, 1), 7, 1) 19 is identical to the replacement mode of the code bits bG to bp of FIG. 73A. Figure 140 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a codec ratio of 4/5, and a further modulation method is 1〇24QAM, and the multiple b is 2; . The replacement of the code bit in the case where the multiple b of Fig. 140 is 2 is directly replaced by the code bit of Fig. 76A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 140 is in accordance with the distribution rule of FIG. The LDPC code is an LDpc code with a code length N of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the walody direction. The memory bit written by the memory 31 in the direction of (162 〇〇 / (1 〇χ 2)) χ (10x2) bits is in the horizontal direction with 135786.doc -194 - 200937872 l〇x2 (= mb) bits The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacing unit 32 is configured to allocate the code bits bG to b! 9 read from the i〇x2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 〇x2 (= mb) bit symbol bit to ^ way, to replace the l〇x2 (= mb) bit of the code bit heart to ^ ^. That is, the replacing unit 32 assigns the mom bit bQ to the symbol bit y6, respectively.

The code bit b2 is assigned to the symbol bit y 4 , the megabyte b4 is assigned to the symbol y8 , the code bit b6 is assigned to the symbol y5 , and the code bit b8 is assigned to the symbol bit . Element y〇, assigning the code bit bio to the symbol bit y2, assigning the code bit bi2 to the symbol bit y!, assigning the code bit b14 to the symbol bit y3, and allocating the code bit bi6 For the symbol bit y9, the code bit b18 is assigned to the symbol bit y7, the code bit b1 is assigned to the symbol bit y, and the code bit b] is assigned to the symbol bit y. 4, the code bit b is assigned to the symbol bit y18, the code bit b7 is assigned to the symbol bit y! 5, the mate b9 is assigned to the symbol bit yi 〇, the m-bit bii Assigned to the symbol bit 丫12, the code bit b!3 is assigned to the symbol yn, 135786.doc -195- 200937872 assigns the code bit b15 to the symbol 丫13, the code bit b 1 7 is assigned to the symbol bit y丨9, and the code bit b19 is assigned to the symbol bit y17 for replacement. In addition, in FIG. 140, the replacement pattern of the megabytes b〇, b2, b4, b6, b8, bi〇, bi2bi4, bl6bi8 and the code bits bl, b3, b5, b7, b9, bn, bi3, bi5, bi7X_ Both modes are identical to the replacement pattern of the code bits b0 to % of Fig. 76A. Figure 141 is a diagram showing an alternative example of the LDPC code in which the code length N is 64,800 bits, the code is stepped on the old 幺-之, the step-by-step modulation method is bribe QAM, and the multiple is =. The replacement of the code bit in the case where the multiple b of Fig. 141 is 2 is directly replaced by the code bit of Fig. 79A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 141 is in accordance with the allocation rule of FIG. The LDPC code has a code length N of 64,800 bits and a coding rate of 4/52 LDpc code. The further modulation mode is 1024QAM and the multiple bg2 is used in the demultiplexer 25, and the direction of the x direction in the wale direction is (64800/). The (10x2))x (10X2) bit memory 31 is written in the horizontal direction, read out in units of i〇x2 (= mb) bits, and supplied to the replacement unit 32 (FIG. 16, Fig. 17) The 〇 replacing unit 32 is configured to allocate the code bits ^ to 9, read from the l 〇 x 2 (= mb) bits of the memory 31, as shown in Fig. 141 to consecutive 2 (=1?) Replace the symbol bits % to \9 of 10x2 (= mb) bits by the symbol yQ to μ of the l〇x2 (= mb) bit of the symbol. That is, the replacing unit 3 2 assigns the code bit bG to the symbol bit y6, assigns the code bit b2 to the symbol bit y4, and assigns the code bit b4 to the symbol, respectively, 135786.doc •196·200937872 The meta-bit y8 assigns the code bit b6 to the symbol bit y5, the code bit b8 to the symbol bit y, and the code bit b! 〇 to the symbol y 2, the code The bit b! 2 is assigned to the symbol bit y!, the code bit b] is assigned to the symbol bit y 3, © the code bit b16 is assigned to the symbol bit y9, and the code bit bi 8 Assigned to symbol bit y 7, assign code bit b! to symbol bit y 16, assign code bit b3 to symbol y 14, and assign code bit b5 to symbol y 18, assigning the code bit b7 to the symbol bit y 15, assigning the code bit b9 to the symbol bit y 1 〇, and assigning the code bit b 丨 to the symbol bit y 12, ❹ Bit b13 is assigned to symbol bit yn, code bit b! 5 is assigned to symbol bit y 1 3, and code bit b 丨 7 is assigned to symbol bit y 19, and code bit b! 9 is assigned to the symbol bit y 17, and is replaced. Further, in Fig. 141, both the replacement mode of the code bit and the replacement mode of the code bit are identical to the replacement mode of the code bits b 到 b9 of Fig. 79A. 135786.doc -197- 200937872 Figure 142 shows that the LDPC code is an LDPC code with a code length of 162 bits and a coding rate of 5/6. The code position in the case of the step-by-step modulation mode is qam, and the multiple is ^2. A replacement for the yuan. In the case of a multiple of 142, the replacement of the code bits is directly (4). The replacement of the code bits of Fig. 82A differing only in the case where the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 142 is in accordance with the allocation rule of FIG.

The G LDPC code is an LDpc with a code length N of 16200 bits and a coding rate of 5/6. The further modulation mode is 1024QAM and the multiple b is 2. In the case of the multiplexer 25, the X direction in the wale direction The direction is (162 〇〇 / (1 〇χ 2)) χ (10 X 2) bits § 体 体 3 1 written code bits are in the horizontal direction, with l 〇 x 2 (= mb) bits The unit is read and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to assign the code bits 13 to be from the ioupmb) bits of the memory 31 to be, as shown in Fig. 142. Replace the code bits ^ to b19 of the 10x2 (= mb) bits by the continuous 2 (= b) symbols of the l〇x2 (= mb) bits of the symbol yG to y". That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, assigns the code bit b to the symbol bit y4, and assigns the code bit b4 to the symbol bit y8, and sets the code. Bit b6 is assigned to symbol bit y5, code bit bg is assigned to symbol bit y〇, code bit b1G is assigned to symbol bit y2, and code bit b is assigned to symbol bit Yuan y!, 135786.doc -198- 200937872 assigns the code bit b14 to the symbol bit y3, and divides the code bit b16 For the symbol bit y9, the code bit b18 is assigned to the symbol bit y7, the code bit b is assigned to the symbol bit y16, and the code bit b3 is assigned to the symbol bit y14, and the code bit is The element b5 is assigned to the symbol bit y丨8, the code bit b7 is assigned to the symbol bit 715, the code bit b9 is assigned to the symbol bit 710, and the code bit b" is assigned to the symbol bit. Element 712, assigning code bit b 1 3 to symbol bit y丨J, assigning code bit b15 to symbol bit yn, and assigning bit bit b17 to symbol bit 3^19, The bit b!9 is assigned to the symbol bit y17 and is replaced. In addition, in FIG. 142, the replacement pattern of the code bits b〇, b2, b4, b6, b8, bi〇, bu and the code bit b 丨, b3, b5, b7, b9, bn, b13>babh14'16'" ❹ mode are both replaced with the replacement mode 2 of the code bit bjb9 of Fig. 82A: the replacement figure 143 indicates that the LDPC code is the code length 6 side Bit, code (4) 5/6 LDPC Ma, further modulation method is 1〇24qam, and the multiple of b is 2. The code bit in the case where the multiple b is 2 The replacement is directly utilized with only a multiple of 13 The point is different from the replacement of the code bits in Fig. 85A. Therefore, the replacement of the code bits in Fig. 143 is in accordance with the distribution rule of the picture. The LDPC code is LDpc 135786 with a code length of 648 bits and a coding rate of 5/6. Doc •199· 200937872 Code 'When the modulation method is 1024QAM and the multiple b is 2, the multiplexer 25 is solved, and the direction of the X direction in the wale direction is (648〇〇/(1〇>^^ ( 1 〇 2) The bit code written by the suffix 31 of the bit is in the course direction, read out in units of 10x2 (-mb) bits, and supplied to the replacement unit 32 (Fig. 17, Fig. 17)

The replacing unit 32 is configured to allocate the code bits 1 to be from the memory 3121 〇 x 2 (= mb) bits to be as shown in FIG. 143 to the consecutive 2 (= b) symbols l 〇 x 2 ( =mb) The way of the bit y{) to y]9 of the bit replaces the code bits bG to b丨9 of the 10x2 (= mb) bit. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y6, assigns the code bit b to the symbol bit y4, and assigns the code bit b4 to the symbol bit y8, The code bit b6 is assigned to the symbol bit y5, the code bit b8 is assigned to the symbol bit y, the code bit bi〇 is assigned to the symbol bit y2, and the mbit b 12 is assigned to the symbol Bit y 1, assign code bit b14 to symbol bit y3, assign code bit bi6 to symbol bit y9, assign code bit b 18 to symbol bit y 7, and use code bit b 1 is assigned to the symbol bit y 16 ' to assign the code bit to the symbol bit yi4, the code bit b5 is assigned to the symbol bit yi8 ' to assign the code bit b7 to the symbol bit yi5 ' 135786 .doc -200- 200937872 assign code bit b9 to symbol bit y ι〇, assign code bit bh! to symbol bit y 〗 2, assign code bit b! 3 to symbol bit y! ι, assign code bit b15 to symbol bit 丫13, assign code bit bi7 to symbol bit yi9, and assign code bit b19 to symbol y17 for replacement. In addition, in Figure i43, the replacement of the code bits b0, b2, b4, b6, b8, bl〇, bi2, bi4, b, 6, bi8 © and the replacement of the code bits bl, b3, b55, b17, b19 Both modes are identical to the replacement mode of the code bits bo to b9 of Fig. 85A. Figure 144 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and a further modulation method is 1 〇 24 q Am and a multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 144 is 2 is directly replaced by the code bit of Fig. 88A in which only the multiple b is ι. Therefore, the replacement of the code bits of Fig. M4 is in accordance with the allocation rule of Fig. 87. The LDPC code is a code length >^ is 162 bits, and the coding rate is 8/9 [then code, further modulation is 1024QAM, and the multiple 5 is 2 in the case of the multiplexer 25, in the vertical line The code bits written by the memory 31 whose direction x direction is (16200/(10χ2)) χ (i〇x2) bits are read in the order of (mb) bits in the course direction and supplied to the replacement. Part 32 (Fig. 16, circle 17). The replacing unit 32 assigns the symbol % to bl9 ' read from the lGx2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 44. 135786.doc 200937872 l The 〇x2(=mb) bit symbol y〇 to yi9 is replaced by the code 位b〇 to b!9 of the 1 〇x2 (= mb) bit. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y 1, respectively. The code bit b6 is assigned to the symbol bit y2, and the code bit b8 is assigned to the symbol bit y3.

The code bit b! 〇 is assigned to the symbol bit y 4 , the code bit b ! 2 is assigned to the symbol bit y 6, the code bit bi 4 is assigned to the symbol bit y 5 , and the code bit is The element bi 6 is assigned to the symbol bit y 9, the code bit b 18 is assigned to the symbol bit y 7, the code bit b 1 is assigned to the symbol bit y! 8, and the code bit b3 is assigned to The symbol bit y 1 〇, the code bit b5 is assigned to the symbol bit y 11, the code bit b7 is assigned to the symbol bit y 12, and the code bit b9 is assigned to the symbol bit y 13, The code bit element th! is assigned to the symbol bit y 14, the code bit b! 3 is assigned to the symbol bit y 16, the code bit bi 5 is assigned to the symbol bit y 15, and the code bit is Bi 7 is assigned to the symbol bit y 19, and the code bit b丨9 is assigned to the symbol bit y 17, and replaced. 135786.doc -202- 200937872 In addition, >Vn ISJ it η· -^^b0sb2,b4,b6,b8,b10jbl2}bl4jbl6) bl8 replacement mode and code bit b丨, hkhbd丨丨, b丨Jab丨do The replacement mode is consistent with the replacement mode of the code bit % to FIG. 88A. Figure 145 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length N of 648 〇〇 bits and a coding rate of 8/9, and the modulation mode is 1 〇 24QAM, and the multiple b is 2. .

The replacement of the code bits in the case where the multiple b of Fig. 145 is 2 is directly replaced by the code bit of Fig. 91A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of Fig. 145 is in accordance with the distribution rule of Fig. 9. The LDPC code has a code length N of 64,800 bits and a coding rate of 8/92 LDpc code. In the case where the modulation mode is 1024 qAM and the multiple b*2, the multiplexer 25 is in the direction of the x direction in the wale direction. (648〇〇/(i〇x2)) x (10x2) bit memory 31 is written in the horizontal direction, read in l〇x2 (= mb) bit units, and supplied to Replacement unit 32 (Figs. 16, 17). The replacing unit 32 assigns the 蚂x2 (=rnb) bit from the memory 31 to bM 'as shown in FIG. 145 to the consecutive 2 (=b) symbols l 〇 x 2 The (-mb) bit symbol is transferred to μ in order to replace the code bits 1)() of 1〇x2(=mb) bits to 1)丨9. That is, the 'replacement unit 32 assigns the code bit bG to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol yi, respectively. Bit 1)6 is assigned to symbol bit y2, 135786.doc 200937872 assigns code bit b 8 to symbol bit y 3 ' assigns code bit b 1 〇 to symbol bit y 4 ' The bit bi2 is assigned to the symbol bit y6'. The code bit bi4 is assigned to the symbol bit y5'. The code bit bi6 is assigned to the symbol bit y9'. The code bit bi8 is assigned to the symbol bit y7. The code bit b 1 is assigned to the symbol bit y 丨 8 , the mega cell b3 is assigned to the symbol y 丨〇 , ^ the code bit b b is assigned to the symbol y 丨 1 , and the code bit is The element b7 is assigned to the symbol bit 丫12, the code bit b9 is assigned to the symbol yi 3, the code bit bi is assigned to the symbol y 14, and the code bit b13 is assigned to the symbol The bit y16 assigns the code bit b15 to the symbol bit 715, assigns the code bit b17 to the symbol bit y19, and assigns the code bit b 9 to the symbol bit 717, and replaces it. In addition, in FIG. i45, the replacement mode of the code bits b〇, b2, b4, b6, b8bi〇b^ and the code bit nm^bu'bab^b14'16'18 mode are both the position of FIG. 91A. The replacement of the element bj b for the 17' 19 is the LDPC code of the code length __;:^:_ 9/10, and the code bit element in the case where the modulation mode is 1〇24QAM and the multiple b is 2. An alternative. The replacement of the code bits in the case where the multiple b of Fig. 146 is 2 is directly utilized. 135786.doc -204- 200937872 The replacement of the code bits of Fig. 94A differing only in the point of the multiple _. Therefore, the replacement of the code bits of FIG. 146 is in accordance with the allocation rule of FIG. The LDPC code is an LDPC code with a code length of _64_bit and a coding rate of 9/H. The further modulation method is 1024QAM and the multiple _ is in the direction of the multiplexer 25' in the wale direction x course. (4) The code bits written in the memory 31 of the (purchased) bit are read in the horizontal direction in the H>x2 (= mb) bit unit, and supplied to the replacement unit 32 (Fig. 17). The m © replacement unit 32 is to read the bits from the memory 31i10x2 (= mb) bits to ~! ^9, as shown in Fig. 146, is assigned to the consecutive 2 (=b) symbolic l〇x2 (= mb) bits of the symbol bits yQ to h, == l〇x2 (= Mb) the bit element b of the bit. To the ratio of 9. In other words, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b/t to the symbol bit. y丨, 〇W assigns code bit 1)6 to symbol bit y2, assigns code bit b8 to symbol bit y3, and assigns bit bit b!G to symbol bit, The code bit b!2 is assigned to the symbol bit y6, the code bit b 14 is assigned to the symbol bit y 5 , the code bit bi6 is assigned to the symbol bit y9, and the code bit bis is assigned to the symbol Meta-bit y7, assigning code bit b 1 to symbol bit y 丨 8 ' 135786.doc -205- 200937872 assigning code bit b3 to symbol bit yi 〇, assigning code bit I) 5 The symbol bit yi 1, the numerator 1>7 is assigned to the symbol ary yn, the code bit t>9 is assigned to the symbol yi 3 , and the symbol bn is assigned to the symbol 00 Yi4, assigning the code bit !^3 to the symbol bit 716, assigning the code bit 1^5 to the symbol bit yi5, and assigning the code bit 1^7 to the symbol bit force 9, Ο The code bit b!9 is assigned to the symbol bit y17 and replaced. In addition, in FIG. 146, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bM, bi6 bi8 and the code bits bl, b3, b5, b7, b9, bn, b] 3 The bl5, bl7bK_ mode are both consistent with the replacement mode of the code bit of FIG. 94A. Figure U7 shows that the LDPC code is a code length _ i argument, and an LDPC code with a coding rate of 2/3 is further adjusted. The variable mode is 4〇96QAM, and the substitution of the code bit in the case of the multiple 匕 is 2. 0 The replacement of the code bit in the case of the multiple of 4 in Figure 147 is directly using the difference of only the multiples... The code bit of 97A is (4). Therefore, the replacement of the code bit in Figure 147 is in accordance with the allocation rule of Figure %. LDPC Ma is a long-term 1620-bit LDPC code with a coding rate of 2/3 'progressive modulation In the case where the mode is 4〇96QAM and the multiple #2 is written, the memory 31 of the demultiplexer 25' is stored in the direction of the wale direction (ΐ62〇〇/(ι2χ2))χ (12x2) bits. The code bits are read in units of bits in the course direction and supplied to the replacement unit 32 (Fig. 16, Fig. 135786.doc-206 - 200937872 17). The replacement unit 32 is to read 12x2 from the memory 31. (=mb The bit elements bQ to b23 of the bit are replaced by the manner of assigning the symbol bits y〇 to y23 of the consecutive 2 (=b) symbols of 12x2 (= mb) bits as shown in FIG. The code bits bG to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y! 分别, respectively, and assigns the code bit b2 to the symbol bit. Y〇, Ο

The code bit b4 is assigned to the symbol bit y 1, the code bit b6 is assigned to the symbol bit y2, the code bit b8 is assigned to the symbol bit y3, and the code bit bi 〇 is assigned to the symbol Bit y4, assigning code bit b! 2 to symbol bit y 5, assigning code bit b 14 to symbol bit y 6, assigning code bit b! 6 to symbol bit y 8 The code bit bi 8 is assigned to the symbol bit y 7, the code bit b2Q is assigned to the symbol bit y!!, the code bit b22 is assigned to the symbol bit y9, and the code bit b! Assigned to the symbol bit y22, the code bit b3 is assigned to the symbol bit y!2, the code bit b5 is assigned to the symbol bit y 1 3 , and the code bit b7 is assigned to the symbol bit Y丨4, assign code bit b9 to symbol bit yi 5, assign code bit b!! to symbol bit y! 6, 135786.doc -207- 200937872 assign code bit b 3 The symbol bit y 17, assigns the code bit b 15 to the symbol bit y 丨 8 , assigns the code bit b 17 to the symbol y2 〇 , and assigns the code bit bi 9 to the symbol bit . Y丨9, assigning the code bit b2 ! to the symbol bit y 23, and assigning the code bit b23 to the symbol bit y21, and performing replace. In addition, in Figure 147, the replacement pattern of the code bits b0, b2, b4, b6, b8, b, 0, b12, b14, b16, b18, O b2Q, b22 and the code bits 1^1) 3, b5, The replacement modes of b7, b9, bii, b13, b15, b17, b19, b2i, b23 are both identical to the replacement mode of the code bits b〇 to bn of Fig. 97A. Figure 148 is a diagram showing an alternative example of the LDPC code in which the LDPC code of the LDPC code having a code length N of 64,800 bits and a coding rate of 2/3 is further modulated by 4〇96QAM, and the multiple is 42. The replacement of the code bit in the case where the multiple b of Fig. 148 is 2 is directly replaced by the code bit of the figure ιοο which differs only by the multiple b. Therefore, the replacement of the code bits in Figure 148 is in accordance with the allocation rules of 囷99. The LDPC is a code length N of 64,800 bits and a coding rate of 2/3 iLDpc code. When the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction x direction. (648〇〇/(ι2χ2)) 码 (12x2) bit memory 31 written code bits are read in the horizontal direction in units of 12x2 (= mb) bits and supplied to the replacement unit 32 (Fig. 16, Figure 17). The replacing unit 32 is configured to allocate the code 135786.doc - 208 - 200937872 bits bG to b23 read from the memory 31 < 12x2 (= mb) bits, as shown in Fig. 148 to consecutive 2 (= b) characters. The 12x2 (= mb) bit symbol bits y 〇 y y y 23 are replaced by 12 x 2 (= mb) bits of code bits bG to b23. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 1 〇, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y 1 . , the code bit b6 is assigned to the symbol bit y2, 0 the code bit b8 is assigned to the symbol bit y3, the code bit b 1 〇 is assigned to the symbol bit y 4 , and the code bit bi 2 is Assigned to the symbol bit y 5, the code bit b丨4 is assigned to the symbol bit y 6, the code bit b! 6 is assigned to the symbol bit y 8, and the code bit b! 8 is assigned to The symbol bit y 7, the code bit b2 is assigned to the symbol y 11, the code bit b22 is assigned to the symbol y9, and the code bit b! is assigned to the symbol y22. The code bit b3 is assigned to the symbol bit y!2, the code bit b5 is assigned to the symbol bit y!3, the code bit b7 is assigned to the symbol bit y 14, and the code bit b9 is assigned To the symbol bit y 15, the code bit b!! is assigned to the symbol bit y16, the code bit b13 is assigned to the symbol bit yi7, and the code bit b 15 is assigned to the symbol bit y 1 8, 135786.doc -209- 200937872 assigning code bit b 17 to symbol bit y 20, assigning code bit b 1 9 The symbol bit y! 9, the code bit b2 1 is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in Figure 148, the code bit

ι>2〇, ι>22 replacement mode and code bits bi, b3, b5, b7, b9, bn, bi3, bi5, bi7, bA

The replacement mode of b^'bu is identical to the replacement mode of the code bit b()ibn of Fig. Figure 149 is a diagram showing an alternative example of the LDPC code in which the LDPC code is an LDPC code having a code length of 162 bits and a coding rate of 3M, and a further modulation method is 4 〇 96QAM, in the case of a multiple. The replacement of the code bits in the case where the multiple b of Fig. 14 is 2 is directly replaced by the code bits of Fig. 1〇3A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 149 is in accordance with the allocation rule of FIG. The LDPC code is 162 〇〇 bits of Ma Chang material, and the coding rate is 3/4 , code. The further modulation method is 4〇96QAM, and the multiple 5 is 2 in the multiplexer 25' in the longitudinal direction. The direction of the χ course is (162_...2): (6) The code bit written by the 6-bit memory 31 is in the course direction, read out in 17)/snap position, and supplied to the replacement unit 32. (FIG. 16, the replacing unit 32 is a bit b〇 to b23, and the 12x2 (= mb) bit is not allocated to the code read from the memory 12 of the 12<2 (=can) bit, such as 囷149. Replace the code bits b〇 to b23 of 135786.doc -210· 200937872 12x2 (= mb) bits for the consecutive 2 (= b) symbol elements of the symbol or even %. The replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b2 to the symbol bit y, and assigns the mbit b4 to the symbol y6, and the code bit B6 is assigned to the symbol y!,

The code bit b8 is assigned to the symbol bit y4, the code bit b! 〇 is assigned to the symbol bit y 5 , the code bit b ! 2 is assigned to the symbol bit y 2 , and the m-bit b is 4 is assigned to the symbol bit y 3, the code bit b! 6 is assigned to the symbol bit y 7, the code bit b! 8 is assigned to the symbol bit y! 〇, the code bit b2G is assigned The symbol bit y11 is assigned to the symbol bit y9, the code bit b 丨 is assigned to the symbol y2 〇, and the code bit b3 is assigned to the symbol y! 2 , the code bit b5 is assigned to the symbol bit y! 8, the code bit b7 is assigned to the symbol bit y! 3, and the code bit b9 is assigned to the symbol bit y 16, the code bit b !丨 is assigned to the symbol bit y! 7, the code bit b! 3 is assigned to the symbol bit y 1 4 , the code bit b b 5 is assigned to the symbol bit y 1 5 , and the code bit is b ! 7 is assigned to the symbol bit y ! 9, the code bit b ! 9 is assigned to the symbol bit y22, -211 - 135786.doc 200937872 The code bit l > 2 1 is assigned to the symbol bit y23 , the code bit b 3 is assigned to the symbol bit y2 j and replaced. In addition, in FIG. 149, the replacement modes of the code bits b0, b2, b4, b6, b8, b10, b12, b14, b16, bl8, b20, b22 and the code bits bl, b3, b5, b7, b9, bu The replacement modes of , bn, bi5bi7, bi9, hub23 are both identical to the replacement mode of the code bits b0 to bu of FIG. 103A. Fig. 150 is a diagram showing an alternative example of the code bit in the case where the LDPC code is an LDPC code whose code length N is 64,800 bits and the coding rate is Ο 3/4, and the modulation mode is 4096QAM, and the multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 150 is 2 is directly replaced by the code bits of Fig. 1 〇 6A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 150 is in accordance with the allocation rule of FIG.

The LDPC code is an LDPC code with a Ma Chang N of 64,800 bits and a coding rate of 3/4. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the longitudinal direction. The code bit written in the memory 31 of the direction (648〇〇/(12χ2)) χ (12x2) bits is in the course direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code bits b to 12 from the 12×2 (= mb) bits of the memory Zhao 3 to 12, and assign 12 to 2 (=b) symbols of the consecutive symbols as shown in FIG. The mb) bits of the bit yQ to ^ are replaced by the code bits bG to b23 of the 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, assigns the code bit b2 to the symbol bit y〇, and assigns the code bit b4 to the symbol bit y8, respectively, 135786.doc -212- 200937872 The symbol bit y6 assigns the code bit b6 to the symbol bit y丨, assigns the code bit b8 to the symbol bit y4, and assigns the code bit bt G to the symbol bit y 5 , Bit b丨2 is assigned to symbol bit y 2, code bit b! 4 is assigned to symbol bit y 3, 码 code bit b! 6 is assigned to symbol bit y 7, and code bit is allocated The element b! 8 is assigned to the symbol bit y 1 〇, the code bit b2G is assigned to the symbol bit y! 1, the code bit b22 is assigned to the symbol bit y9, and the code bit b! is assigned to The symbol bit y2 〇, the code bit b3 is assigned to the symbol bit yi 2 , the code bit b5 is assigned to the symbol bit y 18 , and the code bit b7 is assigned to the symbol bit y ! 3,分配 assigning the code bit b9 to the symbol bit >^6, assigning the code bit bt! to the symbol bit y! 7, and assigning the code bit bi 3 to the symbol bit y 14, the code The bit b丨5 is assigned to the symbol bit y 15, the code bit b! 7 is assigned to the symbol bit y! 9, and the code bit is b ! 9 is assigned to the symbol bit y22, the code bit b2! is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y2i, -213- 135786.doc 200937872 for replacement. In addition, in Figure 150, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, b] 8, b2〇, b22 and the code bits bi, b3, b5, The replacement modes of b7, b9, bn, bi3, bi5, bi7, bi9, bu't»23 are both consistent with the replacement mode of the code bits of Fig. Figure 151 is a diagram showing an alternative example of the LDPC code in which the code length N is 16,200 bits, the LDPC code of the coding rate is 4/5, the further modulation method is 4〇96qA]VI, and the multiple 6 is 2. .替换 Figure 151 is a multiple of 1? The replacement of the code bits in the case of 2 is directly used. The replacement of the code bits of the figure i〇9A with only the multiple b being 1 is different. Therefore, the replacement of the code bits of Fig. 151 is in accordance with the distribution rule of Fig. 108.

The LDPC code is an LDPC code having a code length n of 16,200 bits and a coding rate of 4/5. In the case where the modulation method is 4〇96qAm and the multiple b is 2, the multiplexer 25 is in the traverse direction x. The code bits written in the memory 31 of the (162 〇〇 / (12 χ 2)) χ (12 x 2) bit are in the course direction, read in 12x2 (= mb) bit units, and supplied to Replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code bits TLbo to bu read from the 12x2 (= mb) bits of the memory 31 to 12 consecutive 2 (= b) symbols as shown in FIG. 151. < 2 ( -mb) the bitwise bit of the bit to y23, replacing the code bit b of the 12x2 (= mb) bit (^b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol, respectively. The meta-bit", assigns the code bit t>2 to the symbol bit y〇, 135786.doc -214- 200937872 assigns the code bit b4 to the symbol bit y6, and assigns the code bit b6 to the symbol Bit y 1, assign code bit b8 to symbol bit y4, assign code bit bi 〇 to symbol bit y 5 , assign code bit b 12 to symbol bit y 2 , and code Bit b! 4 is assigned to symbol bit y 3, code bit b! 6 is assigned to symbol bit y 7, and code bit b! 8 is assigned to symbol bit y 1 〇,

The code bit b2G is assigned to the symbol bit y 11, the code bit b22 is assigned to the symbol bit y9, the code bit b1 is assigned to the symbol bit y2, and the code bit b3 is assigned to the symbol The bit position y 12, the code bit b5 is assigned to the symbol bit yis, the code bit b7 is assigned to the symbol bit y 13, and the code bit b9 is assigned to the symbol bit y 16, the code bit is The element b η is assigned to the symbol bit yi 7, the code bit b]3 is assigned to the symbol bit y 14, the code bit b! 5 is assigned to the symbol bit y 1 5 , and the code bit b17 Assigned to the symbol bit yi9, the code bit b ! 9 is assigned to the symbol bit y 22 , the code bit b21 is assigned to the symbol bit y23 ' and the code bit b23 is assigned to the symbol bit y21 ' And replace it. In addition, in FIG. 151, the replacement mode of the code bits b〇, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, bi8, -215-135786.doc 200937872 b-22 and the code bit bib3b5, B7, b9, bii, bi3, bi5, bi7^b2, and the replacement mode of b23 are both consistent with the replacement mode of the code bits % to ^ of FIG. Figure 152 is a diagram showing an alternative example of the code bit in the case where the LDPC code is a code length Ng 648 、 bit, an LDPC code having a coding rate of 4/5, and a further modulation method is 4 〇 96QAM, and the multiple b is 2. The replacement of the code bits in the case where the multiple b of Fig. 152 is 2 is directly replaced by the code bit of Fig. 112A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 152 is in accordance with the distribution rule of Fig. 111. The LDPC code is a code length N of 64,800 bits and an LDPC code having a coding rate of 4/5. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25' is in the longitudinal direction X direction. The code bit written in the memory 31 of the direction (648〇〇/(12χ2)) χ (12x2) bits is in the course direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit. 32 (Fig. 16, Fig. 17). The replacing unit 32 is configured to allocate the code g% of the 12x2 (= mb) bits read from the memory 31 to bn, and assign it to 12x2 of consecutive 2 (=b) symbols as shown in FIG. The (= mb) bit symbol yG to μ is replaced by the code bits bG to b23 of 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit bG to the symbol bit y 8, respectively, assigns the code bit b2 to the symbol bit y, and assigns the code bit b4 to the symbol y6 ' The code bit be assigned to the symbol bit y 1 ' 135786.doc • 216· 200937872 assigns the code bit b8 to the symbol bit y4, assigns the code bit biq to the symbol bit y 5 , and sets the code bit The element bi 2 is assigned to the symbol bit y 2 , the code bit b 4 is assigned to the symbol bit y 3 , the code bit b b 6 is assigned to the symbol bit y 7 , and the code bit bi 8 is used Assigned to the symbol bit y 1 〇, the code bit b2G is assigned to the symbol bit y 11, and the code bit b22 is assigned to the symbol bit y9.

The code bit b! is assigned to the symbol bit y2, the code bit b3 is assigned to the symbol bit y 12, the code bit b5 is assigned to the symbol bit y 18, and the code bit b7 is assigned to The symbol bit y 13, assigns the code bit b9 to the symbol bit y 16, assigns the code bit bn to the symbol bit y 17, assigns the code bit b13 to the symbol bit yi4, and sets the code Bit b! 5 is assigned to symbol bit y 1 5, code bit b! 7 is assigned to symbol bit y 19, and code bit b ! 9 is assigned to symbol bit y 22, and code bit is assigned The element b2! is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in FIG. 152, the replacement modes of the code bits b〇, b2, b4, b6, b8, b10, b12, b14, b16, b18, 匕20 > 22 and the code bits bl, b3, b5, b2i, The replacement mode of b23 is consistent with the replacement of the code bits bQ to bn of Fig. 112A - 217 - 135786.doc 200937872 mode. Figure 153 shows that the LDPC code is an LDPC code with a code length of >^ of 162 bits and a coding rate of 5/6, and the modulation mode is 4〇96QAM, and the code bit of the case of the multiple "2" The replacement of the code bit in the case where the multiple b of Fig. 153 is 2 is directly replaced by the code bit of Fig. 115A in which only the multiple b is 1 is different. Therefore, the code bit of Fig. 153 The replacement is in accordance with the allocation rule of Fig. 114. The LDPC code is code length > 1 is 16200 bits, the coding rate is 5/6 iLDpc weight, and the further modulation mode is 4〇96QAM, multiples ba2, in the case of solution multiplexing The memory element 3 written in the memory direction 3 of the (162 〇〇 / (12x2)) x (12X2) bit in the wale direction X direction is in the course direction, with 12x2 (= mb) The bit unit is read and supplied to the replacement unit 32 (Fig. 16, Fig. 17). The replacement unit 32 is configured to read the code bits bG to bu' from the memory 31212x2 (= mb) bits as shown in FIG. Replace the symbol bits of the 12x2 (= mb) bits bQ to b23 by assigning the symbol bits of the 〇 12x2 (= mb) bits of consecutive 2 (= b) symbols to the force 3 . That is, the replacement unit 32 respectively sets the code bit bG The allocation symbol bit y8 assigns the code bit b2 to the symbol bit y, assigns the code bit b4 to the symbol y6, and assigns the code bit be to the symbol y 1, and sets the code Bit b8 is assigned to symbol bit y4, and bit unit bi〇 is assigned to symbol bit ys ' 135786.doc -218- 200937872 assigning code bit b 12 to symbol bit y 2 ' The element b is assigned to the symbol bit y3, the code bit b16 is assigned to the symbol bit y7, and the code bit b!8 is assigned to the symbol bit yio '. The code bit b2G is assigned to the symbol bit The element y 11 ' assigns the code bit b22 to the symbol bit y9 ' assigns the code bit b 1 to the symbol bit y2 〇 ' assigns the code bit b3 to the symbol bit y 12 '

The code bit bs is assigned to the symbol bit yi8, the code bit b7 is assigned to the symbol bit)^3, the code bit b9 is assigned to the symbol bit y 1.6, and the code bit b 1 1 is assigned For the symbol bit y丨7, assign the code bit 1)彳3 to the symbol bit y14, and assign the code bit b]5 to the symbol bit y!5, and the mbit b 1 7 Assigned to the symbol bit y丨9, the code bit b 1 9 is assigned to the symbol bit y 22, the code bit b2 1 is assigned to the symbol bit y23, and the code bit b23 is assigned to the symbol bit Yuan y21, and replace it. In addition, in Fig. 153, the replacement pattern of the megabytes b, b2, b4, b6, b8, bi〇, bi2, bi4, bi6, bi8, 匕〇山22 and the code bits bi, b3, b5, b7, The replacement modes of b9, bn, bi3, bi5, bi7, bi9, b2i, b23 are both identical to the replacement mode of the code bits ^ to ... of Figure U5A. Figure 154 is a diagram showing that the LDPC code is a code length n of 64,800 bits and an encoding rate of 135,786.doc • 219·200937872 5/6. The code is further modulated by 4〇96qam and the multiple b is 2. An alternative to a bit. The replacement of the code bits in the case where the multiple b of Fig. 154 is 2 is directly replaced by the code bits of Fig. 118A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits of FIG. 154 is in accordance with the allocation rule of FIG. The LDPC code is an LDPC code with a code length N of 64,800 bits and a coding rate of 5/6. In the case where the modulation method is 4096QAM and the multiple b is 2, the multiplexer 25 is in the X direction of the traversing direction. The direction is (648〇〇/(12χ2)) χ © (12x2) bit memory 31 is written in the horizontal direction, read in 12x2 (= mb) bit units, and supplied to the replacement Portion 32 (Fig. 16, Fig. 17) The replacing unit 32 assigns the code bits bG to by read from the memory 31i12x2 (= mb) bits to 2 consecutive (=b) as shown in FIG. The 12x2 (= mb) bit symbol y() to μ is replaced by the 12x2 (= mb) bit of the code bits b〇 to b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit y8, the code bit b2 to the symbol bit y, and the code bit b4 to the symbol y6, respectively. The code bit b6 is assigned to the symbol bit yi, the code bit be be is assigned to the symbol bit y4, and the code bit bi is assigned to the symbol bit y5 '. The code bit bi2 is assigned to the symbol bit Element y2' assigns code bit b14 to symbol bit y3, 135786.doc -220- 200937872 assigns code bit b 16 to symbol bit y 7 ' assigns code bit b18 to symbol bit 丫10. Assign the code bit b2Q to the symbol bit y!!, assign the code bit bn to the symbol bit y9 ' Assign the code bit b! to the symbol bit y20 ' Assign the code bit b3 The symbol bit y 12 ' is assigned to the symbol bit y 18 and the code bit b7 is assigned to the symbol bit 丫! 3, the code bit b9 is assigned to the symbol bit 6 , the code bit b 1 1 is assigned to the symbol bit y 丨 7 , the code bit b13 is assigned to the symbol bit ; ^ 4 , the code Bit b15 is assigned to symbol bit y15, code bit b 1 7 is assigned to symbol bit y丨9, code bit b丨9 is assigned to symbol bit y 22, and code bit b21 is assigned To the symbol bit 723, the code bit b23 is assigned to the symbol bit y21 for replacement. In addition, in Figure 154, the replacement modes of the code bits b0, b2, b4, b6, b8, b10, b12, bi4, bi6, b18, b2, b22 and the code bits bi, b3, b5, b7, b9, The replacement modes of bn, bi3, bi5, bi7, bi9, t> 2i, b23 are both identical to the replacement mode of the code bits b 到 b of Figure n8A. Figure 155 is a diagram showing an alternative example of the code bit in the case where the LDPC code is an LDPC code having a code length N of 16,200 bits and an encoding rate of 8/9, and further modulation mode g4 〇 96QAM, multiples |^2. 135786.doc •221 - 200937872 The replacement of the code bits in the case where the multiple b of the Fig. 1 is 2 is directly used. The replacement of the code bits of Fig. 121A differing only by the point that the multiple b is 1. Therefore, the replacement of the code bits of Fig. 155 is in accordance with the distribution rule of Fig. 12. LDPC is an LDpc code with a code length N of 16200 bits and a coding rate of 8/9. In the case where the modulation mode is 4096QAM and multiples b*2, the multiplexer 25 is in the traverse direction x course. The code bit in the direction of (162〇〇/(ι2χ2))χ(12x2) bits is written in the horizontal direction, read in 12x2 (=mb) bit units, and supplied To the replacement unit 32 (Fig. 16, Fig. 17). The replacing unit 32 assigns the code bits b to bn ' read from the memory 31 < 12x2 (= mb) bits to 12x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bitwise symbol y〇 to ^ of the bit is substituted for the 12x2 (= mb) bit of the code bit b〇 to b23. That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 7丨0, the code bit b2 to the symbol bit y〇, and the code bit to the symbol bit y! , the code bit be be assigned to the symbol bit y2, the code bit be be assigned to the symbol bit y3, the code bit b 1 〇 to the symbol bit y 4 , and the code bit b 12 to be allocated The symbol bit y 5 is assigned, the code bit b 丨 4 is assigned to the symbol y y 6, the code bit bi6 is assigned to the symbol ys, and the code bit bi8 is assigned to the symbol y7 ' 135786.doc -222- 200937872 assigning the code bit b2G to the symbol bit y丨丨, assigning the code bit b22 to the symbol bit y9, and assigning the code bit bi to the symbol bit y22, the code Bit b3 is assigned to symbol bit y, 2, code bit b 5 is assigned to symbol bit y 丨 3, code bit b7 is assigned to symbol bit 714, and code bit bp is assigned to symbol Meta-bit; /15, assigning code bit b 1 to symbol bit yi 6, ^ assigning code bit b 13 to symbol bit y 17, assigning code bit bi5 to symbol bit Yu, assign the code bit b 17 to the symbol bit y2 〇, and assign the code bit b! 9 to Yuan bit yi9, the code bit b2 1 assigned to the symbol bit y23, the code bit b23 to the assigned symbol bit y21, and replaced. In addition, in FIG. 155, the replacement mode of the code bits b2, b22 and the replacement mode of the code bits b2!, b23 are both identical to the replacement mode of the code bit "to!" of FIG. 121A. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 8/9, and an alternative example of the code bit in the case where the modulation is 4096QAM and the multiple b is 2. The multiple b of FIG. The replacement of the code bits in the case of 2 is directly replaced by the code bits of Fig. 124A in which only the multiple b is 1 is different. Therefore, the replacement of the code bits in Fig. 156 of 135786.doc -223- 200937872 According to the allocation rule of Fig. 123. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 8/9, and further modulation is 4〇96QAM, and the multiple 1) is 2, in the case of multiplex multiplexing The memory element written in the memory 31 of the (648 〇〇 / (12 χ 2)) χ (12 x 2) bit in the wx direction x direction is in the course direction, with 12x2 (= mb) bits. The unit is read out and supplied to the replacement unit 32 (Figs. 16 and 17). The replacement unit 32 is configured to read the code from the 12X2 (= mb) bits of the memory 31 to the bit number B2' as shown in Fig. 156. Place Replace the symbol bits y() to μ of 12x2 (= mb) bits of consecutive 2 (=1?) symbols to replace the code bits % to b23 of 12x2 (= mb) bits That is, the replacing unit 32 assigns the code bit b〇 to the symbol bit 丫1〇, the code bit b to the symbol bit y〇, and the mbit b4 to the symbol bit. Yuan yi, © assigns code bit b6 to symbol bit y2, assigns code bit b 8 to symbol bit y 3 , assigns code bit b1Q to symbol bit y4 , and converts bit b 12 is assigned to the symbol bit y 5 '. The code bit b14 is assigned to the symbol bit y6 '. The code bit b 16 is assigned to the symbol bit y8, and the code bit b18 is assigned to the symbol bit y7 ' Assigning code bit b2G to symbol bit yu ' assigning code bit b22 to symbol bit y9, 135786.doc • 224- 200937872 assigning code bit b 1 to symbol bit y22, the code bit The element b3 is assigned to the symbol bit y 12, the code bit bs is assigned to the symbol bit y 13, the code bit b7 is assigned to the symbol bit yi4, and the code bit b9 is assigned to the symbol bit yi 5, the code bit b 1 1 is assigned to the symbol bit y 丨 6 , the code bit bi 3 To the symbol bit Ah 17, the code bits allocated to the symbol bits bl5 Y18,

分配 Assign code bit b 7 to symbol y2 〇, assign mega element 9 to symbol y19, assign code bit b2 to symbol y23, and code bit t&gt ; 23 is assigned to the symbol y2i, and is replaced. In addition, in FIG. 156, the replacement modes of the code bits b〇b2, b4, b6, b8, bi(), bi2, bi4, bi6, b^, b20, b22 and the code bits bib3, b5, b7, b9, Bii, bi3, bi5, b", bi9, bz] The replacement mode of 'b23' is identical to the replacement mode of the code bit to the bi丨 of Fig. 124a. Fig. 157 shows that the LDPC code is code length (10) 648〇〇 Bit &, LDPC code with a coding rate of 9/10, an alternative to the code bit in the case where the step modulation is 4〇96qam, and the multiple is 2. The code bit in the case of the multiple of Fig. 157 The replacement is directly replaced by the code bit of Fig. 127a in which only the multiple b is 1 is different. Therefore, the replacement of the code bit of Fig. 157 is in accordance with the allocation rule of Fig. m. The LDPC code is the code length of 6 sides. The bit and coding rate are 135786.doc • 225- 200937872 code. If the modulation method is 4096QAM and the multiple b is 2, the X-direction of the multiplexer 25' in the wale direction is ( 648〇〇/(ΐ2χ2))χ (12X2) bit δ mnemonic 3 1 written code bits are in the horizontal direction, read out in 12x2 (= mb) bit units, and supplied to the replacement unit 32 (Figures 16, 17). The replacing unit 32 is configured to allocate the code bits b to bn read from the memory of the memory to the bn, as shown in FIG. 157, to 12x2 (= mb) of consecutive 2 (=b) symbols. The bit elements y〇 to yu of the bit are replaced by the code bits bG to b23 of the 12x2 (= mb) bits. That is, the replacing unit 32 assigns the code bit b〇 to the symbol respectively. Bit y 1 〇, assign code bit b2 to symbol bit y 〇, assign code bit b4 to symbol y 丨, assign code bit b6 to symbol y2, place code bit The element b8 is assigned to the symbol bit y3, the code bit biG is assigned to the symbol bit y4, the code bit b!2 is assigned to the symbol bit y5, and the code bit bi4 is assigned to the symbol bit y6. , the code bit b 16 is assigned to the symbol bit y 8, the code bit bis is assigned to the symbol bit y7, the code bit b2G is assigned to the symbol bit y 11, and the code bit b22 is assigned to The symbol bit y9 assigns the code bit bi to the symbol bit y22, and assigns the code bit b to the symbol bit yi2, 135786.doc -226- 200937872 assigns the code bit b 5 to the symbol Bit y 13, assigning code bit b7 to symbol bit yi4, assigning code bit bg The symbol bit y 15, assigns the code bit b 11 to the symbol y 丨 6 , assigns the code bit b 13 to the symbol y 丨 7 , and assigns the code bis to the symbol Yis, assigning the code bit b 17 to the symbol bit y20, and assigning the code bit bi9 to the symbol bit) ^9,

The code bit b 1 is assigned to the symbol bit y23, and the code bit b 3 is assigned to the symbol bit y21 for replacement. In addition, in FIG. 157, the replacement modes of the code bits b0, b2, b4, b6, b8, bi, b12, b, 4, b16, b18, b2, and b22 and the code bits b丨, b3, b5, The replacement modes of b7, b9, bi i, bi3, bi5, b17, b19, b2i, b &gt; 23 are both identical to the replacement mode of the code bits b 〇 to bu of Fig. 127A. 158 to 101 show the BER simulation obtained by replacing the case where the multiple 匕 is shown in FIG. 136 to FIG. 157, and replacing the new replacement method in the case where the multiple b is 2 The result. That is, Fig. 158 shows a code length μ 162 〇〇 and a coding rate of 2. LDPC, which is 3/4, 3/5, 5/6, and 8/9, respectively, is a BEr in the case of 1024QAM. : Figure 159 shows the case where the code length ν is 64800, the LDPC codes of the first _ « 3/5, 5/6, 8/9, and 9/10 are used as 42/3, 3/4, and 1024QAM is used. BER. , image, as a modulation side 135786.doc -227- 200937872 Figure 160 shows that the code length N is 162 〇 0, the coding rate is 2/3, 3/4 3/5, 5/6, 8/9 respectively The LDPC code is used as the object, and the BER in the case of 4096QAM is used as the modulation method. Figure 161 shows an LDPC code with a length of 64800 and a compilation rate of 2/3, 3/4, 3/5, 5/6, 8/9, and 9/10 as the modulation method. BER in the case of 4096QAM. In Figs. 158 to 161, the same as Figs. 130 to 133, the horizontal axis represents the Es/N 〇 ’ vertical axis represents the BER. Further, the 'solid line indicates the BER in the case where the replacement method of the new replacement method has been performed, and the dotted line indicates the BER in the case where the replacement processing is not performed. From FIG. 158 to FIG. 161, the replacement processing of the new alternative is compared with the case where the replacement processing is not performed, and the BER is increased, so that the improvement of the error is recognized. Next, FIG. 162 shows the receiving device 12 of FIG. Block diagram of the configuration example φ In Fig. 162, the receiving device 12 receives the modulated signal from the transmitting device u (Fig. 7), and the orthogonal demodulating unit 51, the demapping unit 52, and the de-interlacer 53 and LDPC decoding unit 56 are configured. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device u, performs quadrature demodulation, and supplies the signal points (1 and (the values in the ^-axis directions) obtained as a result to the demapping unit 52. The mapping unit 52 performs demapping of the symbol points from the orthogonal demodulation unit 51 into symbolized symbols of the LDPC code, and supplies them to the deinterleaver 53. 135786.doc -228- 200937872 The deinterleaver 53 is composed of a multiplexer (MUX) 54 and a vertical twist deinterleaver 55, and performs deinterlacing of the symbol bits from the symbols of the demapping unit 52. Ο ❹, that is, a multiplexer In the 54th, the symbol bit from the symbol of the demapping unit 52 is used as an object, and the inverse replacement processing (reverse processing of the replacement processing) corresponding to the replacement processing by the multiplexer 25 of FIG. 8 is performed, that is, The LDPC code obtained as a result of returning the position of the code bit (symbol bit) of the LDPC code replaced by the replacement processing to the original position is supplied to the vertical twist reverse deinterleaver 55. The line twist deinterleaver 55 takes the LDPC code from the multiplexer 54 as an object. The row corresponds to the longitudinal twist reverse staggering (the reverse processing of the longitudinal twist interlacing) performed by the longitudinal twist interleaver 24 of FIG. 8 as a rearrangement process, that is, as a rearrangement The processing is performed by twisting and interleaving to change the code bits of the aligned LDPC code, and returning to the inverse arrangement of the original arrangement, for example, the longitudinal twist de-interlacing. Specifically, the longitudinal torsional de-interlacer 55 is In the same way, the memory 31 is configured to be a memory for deinterleaving, and is written into the code bit of the LDPC code and read-by-step to perform the wandering de-interlacing. The writing of the 55' code bit is performed by using the read address of the read bit (4) of the code bit from the memory 31 as the write address, and in the course direction of the memory for deinterleaving. The reading system will write the code bit 70 of the code bit of the memory 31 to the address 1/<write address, and use it for the η address, in the longitudinal direction of the memory for deinterleaving. 135786.doc • 229· 200937872 LDPC code obtained by the result of longitudinal twist deinterlacing The vertical twist reverse deinterleaver 55 supplies the LDPC decoding unit 56 to the LDPC decoding unit 56. Here, the eigen-interleaving, the wobble interleave, and the replacement processing are applied in this order from the demapping unit 52 to the de-interlacer 53iLDPC code. In the deinterleaver 53, only the inverse replacement processing corresponding to the replacement processing and the vertical torsional deinterlacing corresponding to the longitudinal torsional interleaving are performed, so that the in-phase deinterlacing corresponding to the co-located interleaving (the inverse processing of the co-located interleaving) is not performed. That is, the parity bit of the LDPC code whose alignment is changed by the co-located interleaving is returned to the co-interleave of the original arrangement. Therefore, the 'de-interleaver 53 (the whirling torsional de-interleaver 55) is applied to the LDPC decoding unit 56. An LDPC code having undergone anti-replacement processing and directional twist de-interlacing, and not performing co-located de-interlacing is supplied. The LDPC decoding unit 56 performs the LDPC code from the deinterleaver 53 by performing at least the conversion check matrix obtained by the LDPC encoding of the LDPC encoding unit 21 of FIG. The LDPC decodes and outputs the data obtained as a result of the decoding of the target data. Figure 163 is a flow chart showing the reception processing performed by the receiving device 12 of Figure 162. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device u in step 8111, and proceeds to step SU2 to perform orthogonal demodulation of the modulated signal. The orthogonal demodulation unit 51 supplies the signal point obtained as a result of the orthogonal demodulation to the demapping unit 52, and the processing proceeds from step S112 to step S113. In step S113, the demapping unit 52 performs demapping of the 135786.doc 200937872 signal point from the orthogonal demodulation unit 51 into a symbol, and supplies it to the deinterleaver 53, and the processing proceeds to step S114. In step S114, the deinterleaver 53 performs deinterlacing of the symbol bits from the symbols of the demapping section 52, and the processing proceeds to step S115. That is, in step S114, in the deinterleaver 53, the multiplexer 54 takes the symbol bit from the symbol of the demapping section 52 as an object, performs inverse replacement processing, and obtains the code position of the LDPC code obtained as a result. The element is supplied to the longitudinal twist reverse deinterlacer 55. The whirling torsional deinterleaver 55 performs the wraparound deinterleaving of the LDPC code from the multiplexer 54 as a target, and supplies the LDPC code obtained as a result to the LDPC decoding unit 56. In step S115, the LDPC decoding unit 56 performs at least the conversion check matrix obtained by the row replacement of the parity interleave by using the check matrix 用于 for LDPC encoding by the LDPC encoding unit 21 of FIG. The LDPC decoding of the LDPC code of the interleaver 55, and the data obtained as a result of the result is output as the decoding result of the object data, and the processing ends. Further, the reception processing of Fig. 163 is repeated. Further, Fig. 162 is also the same as the case of Fig. 8. For convenience of explanation, the multiplexer 54 for performing the reverse replacement process and the reticular reverse deinterleaver 55 for performing the slant reverse twisting are separately formed, but the multiplexer 5 4 The longitudinal torsional deinterlacer 55 can also be constructed integrally. Further, in the case where the transmitting device u of Fig. 8 does not perform the wobble interleaving, the receiving device 12 of Fig. 162 does not need to provide the whirling reverse anti-interlacer 55. 135786.doc • 231 · 200937872 Next, the LDPC decoding performed by the LDPC decoding unit 56 of Fig. 162 is further explained. As described above, the LDPC decoding unit 56 of FIG. 162 performs at least the conversion check matrix obtained by the row interleave replacement for the LDPC encoding check matrix η of the LDPC encoding unit 21 of FIG. The LDPC decoding of the LDPC code of the twist reverse deinterleaver 55 is performed by the inverse replacement processing and the diagonal twist deinterleave, and the eccentric deinterlacing is not performed. ❹

Here, an LDPC decoding has been proposed, which performs LDPC decoding by using a conversion check matrix, and can suppress the circuit scale while suppressing the operating frequency to a sufficiently achievable range (refer to Japanese Laid-Open Patent Publication No. 2004-343170, for example). . Therefore, LDPC decoding with respect to the previously proposed utilization conversion check matrix will be described first with reference to Figs. 164 to 167. Figure 164 is a diagram showing an example of a check matrix LDP of an LDPC code having a code length N of 90 and a coding rate of 2/3. Further, in Fig. 164 (the same applies to Figs. 165 and 166 which will be described later), 0 is represented by a period (.). In the check matrix 图 of Figure 164, the co-located matrix becomes a stepped structure. Fig. 165 is a diagram showing the inspection matrix 图· obtained by the row replacement of the equation (11) and the row replacement of the equation (12) in the inspection matrix 图 of Fig. 164. Column permutation: 6s + t + 1 column - 5t + s + column 1. · (11) Row permutation: 6x + y + 61st line - &gt; 5y + x + 61st line · · (12) where (11) and (12), s, t, X, and y are integers in the range of 〇$s&lt;5, 〇St&lt;6, 0Sx&lt;5, 0St&lt;6, respectively. 135786.doc -232- 200937872 If the substitution is based on the formula (11), the substitution is performed by dividing the first, seventh, thirteenth, 19th, and 25th columns with the remainder of the remainder by 1, and the second, third, and third Columns 4, 5, and columns 2, 8, 14, 20, and 26 divided by 6 are replaced by columns 6, 7, 8, 9, and 10, respectively. Further, if the row is replaced according to the equation (12), the 61st and subsequent (colocated matrix)'s are replaced by the following cases: the 61st, 67th, 73rd, 79th, and 85th lines divided by the 6th remainder are replaced by the 61, 62, 63 '64, 65 lines, divided by 6th, the 62nd, 68th, 74th, 80th, and 86th lines are replaced by the 66th, ❹67, 68th, 69th, and 70th lines, respectively. Thus, the matrix obtained by performing column and row permutation on the inspection matrix 图 of FIG. 164 is the inspection matrix Η' of FIG. Here, even if the column replacement of the check matrix is performed, the arrangement of the code bits of the ldpc code is not affected. Moreover, the row permutation of equation (12) is equivalent to the subdivision of the co-interleaving at the position where the K+qx+y+1 code bits are interleaved to the K+Py+X+1 code bits. The information length K is 60, and the number of rows p of the unit of the tour structure is 5 and the number 9 (=]^/1&gt;) of the same-length length M (here 30) is the co-interlace at 6 o'clock. The LDPC code of the inspection matrix of FIG. 165 (hereinafter referred to as a replacement inspection matrix as appropriate) H''(4) in FIG. 164 (hereinafter suitably referred to as the original inspection matrix) H is subjected to the same replacement as the equation (12). After the matrix, the 0 vector is output. #即, if the column vector obtained by replacing the row vector C'16 with the row of equation (12) as the original check matrix ^ is represented as c', then the nature of the check matrix Look, HcT becomes. Vector, so H'c'T is of course also a 〇 vector. 135786.doc • 233- 200937872 According to the above, the conversion check matrix 图 of FIG. 165 is an inspection matrix of the LDPC code c· obtained by performing the row replacement of the equation (12) on the LDPC code c of the original check matrix. Therefore, the LDPC code c of the original check matrix , is subjected to the row substitution of the equation (12), and the LDPC code c' is decoded (LDPC decoding) by using the conversion check matrix H· of FIG. 165. The decoding result is subjected to the inverse permutation of the row permutation of the equation (12), whereby the decoding result in the case where the LDPC code of the original inspection matrix 利用 is decoded by the inspection matrix 可获得 can be obtained. Figure 166 is a diagram showing the conversion check matrix 图· of Figure 165 with intervals of 5x5 matrix. In FIG. 166, the conversion check matrix η is expressed by a combination of the following matrices: a unit matrix of 5; a matrix of one or more of the unit matrices is a matrix of 〇 (hereinafter suitably referred to as a quasi unit) Matrix); a matrix of cyclic shifts of a unit matrix or a quasi-unit matrix (hereinafter referred to as a shift matrix as appropriate); a sum of 2 or more of a unit matrix, a quasi-unit matrix, or a shift matrix (hereinafter suitably The matrix of the matrix of Fig. 166 can be composed of a unit matrix quasi-unit matrix of 5x5, a shift matrix, and a matrix and a unitary matrix. Therefore, the matrix 5x5 which constitutes the conversion check matrix H is hereinafter suitably referred to as a constituent matrix. For the decoding of the LDPC code represented by the check matrix represented by the constituent matrix of Pxp, P architectures for performing check node operations and variable node operations simultaneously can be utilized. Figure 167 is a block diagram showing a configuration example of a decoding apparatus for performing such decoding. 135786.doc - 234 · 200937872 That is, FIG. 167 shows that at least the line of the equation (12) is performed using the original inspection matrix H for FIG. A configuration example of a decoding apparatus for decoding the LDPC code by replacing the conversion check matrix H' of the graph 166 obtained. The decoding device of FIG. 167 includes: a memory for storing branch data stored by six FIFs 〇〇3〇〇1 to 3〇〇6, and a selector for selecting FIF〇3〇〇1 to 3〇〇6 301. The check node calculation unit 302, the two cyclic shift circuits 3〇3 and 308, the branch data storage memory 304 composed of 18 FIFOs 304丨 to 304′8, and the selection FIF〇3〇4丨The selector 305 to 3〇4ls, the received data storage unit 3〇6 storing the received information, the variable node calculation unit 3〇7, the decoded word calculation unit 309, the received data rearrangement unit 3 1〇, and the decoded data rearrangement Section 311 〇 First, the data storage method for the memory 3 〇〇 and 3 〇 4 for the branch data storage is explained. The branch data storage memory 3 is obtained by dividing the number of columns 30' of the conversion check matrix H' of FIG. 166 by the number of columns 5 of the matrix, that is, 6 fif〇❿ 300丨 to 30〇6 Composition. The FIFO 300y (y=l, 2, · · ·, 6) is composed of a plurality of segments of memory regions, and the memory regions of each segment can simultaneously read or write the number of columns and the number of rows corresponding to the constituent matrix. 5 branches of the message. Moreover, the number of segments of the FIFO 300yi memory region is the maximum number of the number of columns (the Hamming weight) of the column of the conversion check matrix of Fig. 166, that is, 9. In the FIFO 300, the data corresponding to the position of the conversion check matrix of FIG. 166 compared to the 1st column to the 5th column (the message heart from the variable node) is stored in the form of horizontally padding each column ( Ignore the form of 〇). That is, if the i-th row of the jth column is represented as (j, i), then in the first segment memory area of the FIF 〇 300, the storage 135786.doc - 235 - 200937872 has a corresponding check matrix Η The data of the position of 1 of the unit matrix of 5x5 of (ι,ι) to (5,5). In the second segment memory area, a shift matrix corresponding to the conversion check matrix Η 'from (1, 21) to (5, 25) is stored (the shift of the unit matrix of 5 χ 5 to the right is only cyclically shifted by 3) Information about the location of the bit matrix). From the third to the eighth segment of the memory area, the data is also stored in correspondence with the conversion check matrix. Then, the 9th segment memory region stores a shift matrix corresponding to the conversion check matrix ( from (1, 86) to (5, 90) (substituting 1 of the 1st column in the unit matrix of 5 χ 5 with 0, And only the data of the position of 1 of the rear shift matrix) is cyclically shifted to the left. In the FIFO 30〇2, data corresponding to the position of the sixth column to the first column of the conversion check_n matrix η' of Fig. 166 is stored. That is, in the 1st section of the FIF〇3〇〇2, the 5th recall area stores the sum matrix corresponding to the transition check matrix from (6,1) to (1〇,5) (the unit matrix of 5χ5 is Information on the position of the first shift matrix of the first shift matrix in which only one of the first shift matrix is cyclically shifted to the right and the sum of the second shift matrices that are cyclically shifted by two to the right. . Further, the second-stage memory area stores data corresponding to the position of I of the second shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (1, 5). That is, 'for a constituent matrix with a weight of 2 or more, a unit matrix of pxp with a weight of 1, one or more of its elements is a quasi-unit matrix of 〇, or a unit matrix or a quasi-unit matrix is cyclically shifted. When the form of the complex sum in the shift matrix after the bit represents the constituent matrix, the data corresponding to the position of the unit matrix, the quasi-unit matrix or the shift matrix of the weight 1 corresponds to the unit matrix, The unit matrix or shift matrix branch 135786.doc -236- 200937872 message) is stored in the same address (the same FIFO in the FIFO 30〇ι to 30〇6). Hereinafter, the data is stored in the memory area ' from the third to the ninth segments as well as the conversion check matrix H'. The FIFOs 30〇3 to 3〇〇6 are also stored in the same manner as the conversion check matrix 11, and data is stored. The branch data storage memory 304 is composed of 18 FIFOs 30 to 30418 以 which are divided by the number of rows constituting the matrix, 5, divided by the conversion check matrix H, and the number of rows 90. FIFO 304x (x=l, 2, ···, 18) is composed of a plurality of segments of memory area. The memory area of each segment can be simultaneously read or written corresponding to the conversion check matrix H, the number of columns and The message of 5 branches of the number of rows. In the FIFO 304, corresponding to the position of the first row to the fifth row of the conversion check matrix H' of FIG. 166 (the message from the check node is stored in the form of vertical filling of each row (to ignore) That is, in the first segment memory area of the FIFO 304, the data corresponding to the position of the unit matrix of 5X5 of the conversion check matrix q H' from G, 1) to (5, 5) is stored. . In the second segment memory region, a sum matrix corresponding to the transition check matrix H, from (1 0, 5), is stored (the fifth matrix matrix of 5x5 is cyclically shifted to the right only! The data of the position of the first shift matrix of the sum matrix of the sum of the two second shift matrices of the two element shift matrices is shifted to the right. Further, the third-stage memory area stores data corresponding to the position of the second shift matrix constituting the sum matrix of the transition check matrix H' from (6, 1) to (1, 5). For a constituent matrix with a weight of 2 or more, a unit matrix with a weight of iipxp 135786.doc • 237- 200937872, a quasi unit matrix with one or more of its elements being 0, or a unit matrix or a quasi-unit matrix The form of the sum of the complex numbers in the shift matrix after cyclic shifting represents the position of the unit matrix, the quasi-unit matrix, or the position of the shift matrix of the weight 1 (corresponding to the unit matrix) The message of the branch of the quasi-unit matrix or the shift matrix is stored in the same address (the same FIFO in FIFO 304 to 30418). Hereinafter, data is stored from the fourth and fifth segment memory regions in association with the conversion check matrix H1. The number of segments of the memory area of the FIFO 3041 is the conversion check matrix H, and the maximum number of ones (the Hamming weight) from the first row to the fifth row is five. Similarly, the FIFOs 3042 and 3043 are assigned to the conversion check matrix H, and the length (segment number) of the stored data 'is 5, respectively. The FIFOs 3044 to 30412 are also associated with the conversion check matrix H, and the data is stored, and the length is 3 respectively. The FIFOs 304, 3 to 304^ are also assigned to the conversion check matrix Ηι to store data, each having a length of two. Next, the operation of the decoding apparatus of Fig. 167 will be described. The branch data storage memory 300 is composed of six FIFOs 3001 to 3006. 'The five messages d3u supplied from the previous stage cyclic shift circuit 3〇8 belong to the conversion check matrix, and the information of which column (Matrix) Data) D3 12, select FIF〇 for storing data from FIFO 300丨 to 30〇6, and store 5 messages D3ii sequentially in the selected FIF〇. Further, when the branch data storage memory 300 is used to read data, five pieces of information D300 are sequentially read from the FIF 〇 3〇〇, and supplied to the selector 3〇1 of the second stage. Branch data storage 135786.doc 200937872 The memory 300 is sequentially read from fif〇30〇2 to 30〇6 after the reading of the message from the FIFO 30〇 is completed, and is supplied to the selector. 3〇1. The selector 301 selects five messages of FIF0 from the FIFOs 3001 to 3〇〇6 which are currently read out in accordance with the selection signal D301, and supplies them to the check node calculating unit 3 〇2 as the message D3 02. The check point calculation unit 302 is composed of five check node calculators 3〇21 to 3025 'using the message d3〇2 (D3021 to D3025) supplied by the pass selector 3〇1 (formula (7)) Message Vi), check node operation according to the formula, and + supply 5 messages 0303 (0303! to D3 03s) obtained by the result of the check node operation (message Uj of equation (7)) to the cyclic shift circuit 3 〇 3. The cyclic shift circuit 303 cyclically shifts the information of several original unit matrices by converting the five pieces of information 03031 to 353035 obtained by the check node calculating unit 3〇2 to the conversion check matrix H ( The matrix data is cyclically shifted based on D3〇5, and the result is supplied to the branch data storage memory 304 as the message D3〇4. ❹ Branching data storage memory 3〇4 is composed of 3〇4ι to 3〇4i8 'The five messages D304 supplied by the cyclic shift circuit 3〇3 from the previous stage belong to the conversion check matrix η, which column The information D3〇5 selects the FIF〇 storing the data from fif〇3041 to 304!8, and sequentially stores the five messages D3〇4 in the selected FIF〇e and the branch data storage memory 304. When the data is read, five messages D306 are sequentially read from FIF〇3〇4, and supplied to the selector 3〇5 of the second stage. The branch data storage memory 304 is sequentially read out from fif〇 3042 to 304η after the reading of the data from FIF〇3〇4ι, and is supplied to the selector 3〇5. 135786.doc 200937872 The selector 305 selects five messages of fifo from the FIFO 304! to 3041S which are now read data according to the selection signal D3〇7, and supplies it to the variable node calculation unit 3〇7 as the message D308. The decoded word calculation unit 3〇9.

On the other hand, the received data rearrangement unit 310 rearranges the LDPC code D313 received through the communication channel by the line replacement of the expression 〇2), and supplies it to the received data memory as the received data D3 14 . 3〇6. The received data memory 306 calculates and memorizes the received LLR (logarithm ratio ratio) from the received data D314' supplied from the received data rearrangement unit 31, and supplies the received llr to the received value D309 every five times. The variable node calculation unit 307 and the decoded word calculation unit 309. The variable node calculation unit 307 is composed of five variable node calculators 3〇71 to 3075 'using the message 0308 (0308 to D3085) supplied by the pass selector 305 (the message Uj of the equation (1)) and the slave The received data is received by the memory 3〇6, the five received values D309 (the received value of the equation (1), 可变, the variable node operation according to the equation (1), the message D310 obtained by the result of the calculation (D31) 〇i to D31〇5) (message Vi of the equation (1)) is supplied to the cyclic shift circuit 3〇8. The cyclic shift circuit 308 sets the messages D3 10 to D3 1 calculated by the variable node calculation unit 307. 5. The corresponding branch is cyclically shifted based on the information of the original unit matrix by cyclically shifting the check matrix H, and the result is supplied to the branch data storage memory 3 as the message D311. The LDPC code can be decoded once by the above operation. The decoding device of Fig. 167 decodes the ldPC code only a specific number of times, and then obtains the decoded word calculation unit 309 and the decoded data rearrangement unit 311. The final decoding knot 135786.doc • 240- 200937872 is also the 'decoding word calculation department 3〇9 series It consists of 5 decoded word calculators 3〇9ι to 3〇95, which are output by the selector (3) message (picture to D3085) (memory Uj of equation (5)) and memory from receiving data. The five received values supplied by the body (called the received value of the equation (7)) are used as the final segment of the complex decoding, and the decoding result (decoded word) is calculated according to the equation (5), and the decoded data D3 obtained by the result is obtained. The decoded data rearrangement unit 311 is inversely replaced by the decoded data D315 supplied from the decoded word calculating unit 3〇9 as a row of the object 1 line (10), © 卩In the order of ', and output as the final distraction result D316. As above, by applying one or both of the column permutation and the row permutation to the inspection matrix (original inspection matrix), it is converted into a unit matrix capable of ρχρ. One or more of the elements 1 is a quasi-unit matrix of 〇, a complex matrix of a shift matrix, a unit matrix, a quasi-unit matrix, or a shift matrix after cyclically shifting the unit matrix or the quasi-unit matrix. Combination with matrix and ρ leaf zero matrix, also The q matrix (conversion check matrix) can be represented by a combination of constituent matrices, and the LDPC code can be decoded by using an architecture of ρ check node operations and variable node operations simultaneously, thereby simultaneously performing P The node operation can reduce the operating frequency to an achievable range and perform a lot of repeated decoding. The receiving device 12iLDpc decoding unit 56 constituting the drawing 162 is the same as the decoding device of FIG. 167, and performs ρ check node operations simultaneously and Variable node operation for LDPC decoding. That is, for the sake of simplicity of explanation, the check matrix of the LDpc code which is circulated by the LDPC encoding section 21 constituting the transmitting apparatus n of Fig. 8 is set as, for example, Fig. 135786.doc • 241 - 200937872 = the w array shown becomes a ladder Constructing the inspection material η, then interleaving the K+qx+y+i code bits to the same,

The position of the co-located interleaved information length K of the position of the seventh Χ7+Χ+1 code bit, the number of lines of the unit of the tour structure Ρ, 5, the number of the same position long q q (=M/P) is set to 6. Since the co-located interleaving is performed as described above in relation to the line )2), the LDPC decoding unit 56 does not need to perform the line replacement of the equation (12).

Therefore, the receiving apparatus 12 of Fig. 162 supplies the LDPC decoding unit 56 to the LDPC decoding unit 56 as described above, and supplies LDPC Ma which is not subjected to the co-deinterlacing, that is, the line replacement of the equation (12) is supplied. The LDPC code in the state is processed in the same manner as the decoding apparatus of FIG. 167 except that the LDPC decoding unit % is replaced by the line of the equation (1). That is, Fig. 168 is a diagram showing an example of the configuration of the LDpc decoding unit % of Fig. 162. In FIG. 168, the LDPC decoding unit 56 is configured similarly to the decoding device of FIG. 167 except that the received data rearrangement unit 310 of FIG. 167 is not provided, except that the row replacement of the equation (12) is not performed, and FIG. Since the decoding apparatus performs the same processing, the description thereof will be omitted. As described above, since the LDPC decoding unit 56 is not provided with the received data rearrangement unit 31, the decoding apparatus of Fig. 167 can be reduced in size. In addition, in FIGS. I64 to 168, in order to simplify the description, the code length N of the LDpc code is set to 90, the information length K is set to 60, and the number of rows of the tour structure unit (the number of columns and the number of rows of the matrix) P Let 5 be the divisor q (=M/P) set to 6, but the code length Ν, information length Κ, the number of rows of the unit of the tour structure P and the number q (=M/P) are not limited. Above the above values. 135786.doc -242- 200937872 That is, in the transmitting device u of FIG. 8, the lDPC encoding unit 2 outputs, for example, the code length N is set to 64800 or 16200, and the information length K is set to N-Pq (-NM). The row number p of the unit of the patrol structure is set to 36 〇, and the number q is set as the LDPC code of Μ/P, but the decoding unit 56 of FIG. 168 takes the ldpc code as the object and performs P check node operations at the same time. And the variable node operation can also be applied in the case of performing LDPC decoding. Then, the series of processes described above can be performed by hardware or by software. When a series of processing is performed by software, the program constituting the software is installed in a general-purpose computer or the like. Therefore, Fig. 169 is a diagram showing an example of a configuration in which one type of computer is installed with a program for executing the above-described series of processes. The program can be recorded in advance on a hard disk 705 or ROM 703 built in a computer as a recording medium. Alternatively, the program can be temporarily or permanently stored (recorded) on a floppy disk, CD-: R〇M (Compact Disc Read Only Memory), MO (Magneto 〇pticai: magneto-optical) A removable recording medium 711 such as a disc, a DVD (Dighal Versatile Disc), a magnetic disc semiconductor memory, or the like. This type of portable recording medium 7 can be provided as a so-called package software. In addition, the program is installed in the portable recording medium 711 as described above to the computer, and can be wirelessly transmitted to the computer via the LAN from the download page via the artificial satellite for digital satellite broadcasting, via the LAN (L〇cal Area Netw〇rk : Regional Network) 'Internet network, wired to the computer' on the computer, the communication unit 708 receives the program transmitted from this, and installed in the internal 135786.doc -243- 200937872 hard disk 705 . A CPU (Central Processing Unit) 702 is built in the computer. In the CPU 702, an input/output interface 710 is connected via the bus bar 701, and an input command 707 composed of a keyboard, a mouse, a microphone, or the like is operated by the user via the input/output interface 710, and an instruction is input. The Bay|J CPU 702 executes a program stored in a ROM (Read Only Memory) 703 in accordance therewith. Alternatively, the CPU 702 is a program that is stored in the hard disk 705, transmitted from a satellite or a network, and installed on the hard disk 705 by the communication unit 708, or from a portable recording loaded on the disk drive 709. The medium 711 reads and installs the program on the hard disk 705, and loads it into a RAM (Random Access Memory) 704 to execute it. Thereby, the CPU 702 performs processing in accordance with the above-described flowchart or processing performed by the above-described block diagram. Then, the CPU 702 outputs the processing result from the output unit 706 composed of an LCD (Liquid Crystal Display) or a speaker or the like via the input/output interface 710, for example, or from the communication unit 708, and further. Make it recorded on the hard disk 705 or the like. Here, the processing steps of the program for causing the computer to perform various processes are described in the present specification, and it is not necessary to process them in time series according to the sequence described in the flowchart, and also includes processing performed in parallel or individually (for example, juxtaposition Handling or handling by object). Moreover, the program can be processed by one computer or distributed by a plurality of computers. Further, the program can also be transmitted to a remote computer to execute 0 135786.doc • 244- 200937872 Next, the processing of LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11 will be further explained. For example, in the specification of DVB-S.2, there are two LDPC codes of code length N of 64800 bits and 16200 bits. Then, regarding the LDPC code having a code length N of 64,800 bits, 11 coding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/ are specified. 5, 5/6, 8/9 and 9/10, regarding the LDPC code with a code length N of 16,200 bits, there are 10 coding rates of 1/4, 1/3, 2/5, 1/2, 3/ 5, 2/3, 3/4, 4/5, 5/6 and Ο 8/9. The LDPC encoding unit 21 performs encoding by using an LDPC code of a code length N of 64800 bits or 16200 bits in accordance with an inspection matrix 每 prepared per code length N and per coding rate (error correction coding) ). In other words, the LDPC encoding unit 21 stores a check matrix initial value table which will be described later, based on the code length N and the coding rate. Here, in the specification of DVB-S.2, as described above, there are two kinds of code lengths of 64800 bits and 16200 bits, and 11 codes are respectively specified for the LDPC code with a code length of 64800 bits. The rate is about 10 encoding rates for an LDPC code having a code length N of 16,200 bits. Therefore, when the transmitting apparatus 11 is a device that performs processing according to the specifications of DVB-S.2, the LDPC encoding unit 21 stores that the LDPC codes having a code length N of 64,800 bits correspond to 11 encoding rates, respectively. The check matrix initial value table and the LDPC code having a code length N of 16,200 bits respectively correspond to a check matrix initial value table of 10 coding rates. The LDPC encoding unit 21 sets the code length N and the encoding rate r» of the LDPC code according to the operation of the operator, for example, and the code length n set by the LDPC encoding unit 21 is appropriately selected hereinafter. And the coding rate r, which is also referred to as a set code length N and a set code rate r, respectively. The LDPC encoding unit 21 corresponds to the information length K (=Nr=code length N-co-located according to the set code length N and the set coding rate r according to the check matrix initial value table corresponding to the set code length N and the set coding rate r. The element of the information matrix HA of the length M) is arranged in the row direction every cycle of 360 lines (the number of rows P of the circuit structure), and the inspection matrix 生成 is generated. Then, the LDPC encoding unit 2 1 extracts the information bits of the information from the image data or the sound data supplied to the transmitting device 11 as the target data to be transmitted. Further, the LDPC encoding unit 21 calculates a code word (LDPC code) of one code long by calculating the parity bit for the information bit based on the check matrix Η '. That is, the LDPC encoding unit 21 sequentially calculates the parity bits of the code word c conforming to the following equation.

Hc^O In the above equation, c denotes a column vector as a codeword (LDPC code), and CT denotes a transposition of the column vector c. As the column vector of the LDPC code (1 codeword) (in the case where the column vector a represents the portion of the information bit ' and the column vector T represents the portion of the parity bit, the column vector c can be used as the information bit The column vector a and the column vector T as the parity bits are represented by the formula C=[A|T]. Moreover, the check matrix can be represented by the portion of the code bit of the LDPC code corresponding to the information bit. The information matrix and the parity matrix corresponding to the parity bit 135786.doc 200937872 Ητ 'is expressed as the formula H=[HA|HT] (the element of the information matrix Ha is set to the left element 'the element of the same matrix Ητ is set to the right element Further, for example, in the specification of DVB-S.2, the parity matrix Ητ of the check matrix H=[HA|HT] becomes a ladder structure. The check matrix Η and the column vector LDPC code are c=[A| T] must conform to the formula HcT=0, as the column vector T constituting the parity of the 歹 vector c=[A丨τ] according to the formula Hct=〇, which can be due to the parity of the check matrix H=[HA|HT] When the moment drop Η is a step structure, the elements of the jth column from the HcT=〇 row vector Hct are sequentially made to the elements of each column. The LDPC encoding unit 21 obtains the parity word τ for the information bit A, and then the code word C=[A| represented by the information bit A and the parity bit T. T] is output as the LDPC coding result of the information bit A. As described above, the LDPC encoding unit 21 stores the code length N and the check matrix initial value table corresponding to each coding rate r, and sets the code rate of the code length n. The LDPC code is performed by using the check matrix Η generated from the set code length n and the check matrix initial value table corresponding to the set code rate j·. The check matrix initial value table checks the matrix Η corresponding to the LDPC code. The position of the element of the information matrix HA1 of the information length N (the LDPC code defined by the matrix )) and the information length K of the coding rate r is expressed in every 360 lines (the number of rows of the circuit in the tour structure) The table is prepared in advance according to the code length N and the check matrix r of each coding rate r. Figures 170 to 215 show the check matrix initial value table specified by the specification of DVB-S.2 for generating various checks. Matrix matrix check matrix initial value table. 135786.doc 247- 200937872 ie ' Fig. 170 is a table showing the initial value of the check matrix of the check matrix & of the code length 1 of 16200 bits for the length of the DVB-S.2, which is defined by the specification of DVB-S.2. Fig. 171 to Fig. 173 show the DVB. The check matrix initial value table of the check matrix 编码 for the code length r of 64800 bits, which is defined by the specification of S.2, is 2/3. Further, Fig. 172 is continued from Fig. 171, Fig. 173 The connection is continued from Figure 172. 〇 Figure 174 is a table showing the initial value of the check matrix of the check matrix 对于 for the code length r of 16200 bits, which is defined by the specification of DVB-S.2. Fig. 175 to Fig. 178 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length 64 of 64,800 bits, which is defined by the specification of DVB-S.2. In addition, FIG. 176 is continued from FIG. 175, and FIG. 177 is continued from FIG. Moreover, Figure 178 is continued from the diagram of Figure 177. Figure 179 is a table showing the initial value of the check matrix of the check matrix 编码 for the code length r of 16200 bits, which is defined by the specification of DVB-S.2, which is 4/5. Fig. 180 to Fig. 183 are diagrams showing the check matrix initial value table of the check matrix 编码 for which the code length Ν is 64,800 bits and the code rate r is 4/5 as defined in the specification of DVB-S.2. In addition, FIG. 181 is continued from FIG. 180, and FIG. 182 is continued from FIG. Moreover, Fig. 183 is a diagram continued from 圊182. 135786.doc • 248- 200937872 Figure 184 is a table showing the initial value of the check matrix for the check matrix 编码 with a code length N of 16200 bits and a code rate r of 5/6 as defined by the specification of DVB-S.2. Fig. 185 to Fig. 188 are diagrams showing the check matrix initial value table of the check matrix 编码 for the code length r of 64800 bits with a code length r of 5/6 as defined by the specification of DVB-S.2. In addition, FIG. 186 is continued from FIG. 185, and FIG. 187 is continued from FIG. Moreover, Figure 188 is continued from the diagram of Figure 187. Ο Figure 189 is a table showing the initial value of the check matrix for the check matrix 编码 with a code length 16 of 16200 bits and a code rate r of 8/9 as defined by the specification of DVB-S.2. Fig. 190 to Fig. 193 are diagrams showing the check matrix initial value table of the check matrix 编码 of the code rate r of 64/800 with a code length 为 of 8/9 as defined by the specification of DVB-S.2. In addition, FIG. 191 is continued from FIG. 190, and FIG. 192 is continued from FIG. Moreover, FIG. 193 is continued from the diagram of FIG. Fig. 194 to Fig. 197 are diagrams showing the check matrix initial value table of the check matrix 编码 for the coding rate r of the code length 64 of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 195 is continued from FIG. 194, and FIG. 196 is continued from FIG. Moreover, Figure 197 is continued from the diagram of Figure 196. Fig. 198 and Fig. 199 show the check matrix initial value table of the check matrix 对于 for which the code rate 64 is 64,800 bits and the code rate r is 1/4 as defined by the specification of DVB-S.2. 135786.doc -249- 200937872 In addition, Figure 199 is continued from Figure 198. Fig. 200 and Fig. 201 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length N of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 201 is continued from the diagram of FIG. Fig. 202 and Fig. 203 show the check matrix initial value table of the check matrix 对于 for the coding rate r of the code length r of 64,800 bits as defined by the specification of DVB-S.2. In addition, FIG. 203 is continued from the diagram of FIG. Fig. 204 to Fig. 206 are diagrams showing the check matrix initial value table of the check matrix 为 for the code rate 64 of 64,800 bits, which is 1/2 of the specification of DVB-S.2. In addition, FIG. 205 is continued from the diagram of FIG. 204, and FIG. 206 is continued from the diagram of FIG. Fig. 207 to Fig. 209 are diagrams showing the check matrix initial value table of the check matrix 对于 for the code length 64 of 64,800 bits with a code length r of 3/5 as defined by the specification of DVB-S.2. In addition, FIG. 208 is continued from the diagram of FIG. 207, and FIG. 209 is continued from the diagram of FIG. Fig. 210 is a table showing the initial value of the check matrix of the check matrix 为 for the code rate r of 16200 bits, which is defined by the specification of DVB-S.2, which is 1/4. Figure 211 shows the check matrix initial value of the check matrix 135 135786.doc -250- 200937872 Table 〇 for the code rate r of 16200 bits with a code length 16 of DVB-S.2. The 212 series indicates an inspection matrix initial value table of an inspection matrix 编码 for a coding rate Γ of 2 6200 bits having a code length n of DVB-S.2. Figure 213 is a table showing the initial value of the check matrix of the check matrix 为 for the code rate r of 1 bit, which is defined by the specification of DVB-S.2. Figure 214 is a table showing the initial value of the check matrix of the check matrix 对于 for the code rate r of 166 bits with a code length ν of 3/5 as defined by the specification of DVB-S.2. Figure 215 is a table showing the initial value of the check matrix of the check matrix 编码 with a code length r of 3/5, which can be used in place of the check matrix initial value table of Figure 214. The LDPC encoding unit 21 of the transmitting device 11 obtains the check matrix 如 by using the check matrix initial value table ' as follows. That is, Fig. 216 shows a method of obtaining the inspection matrix η from the inspection matrix initial value table. In addition, the check matrix initial value table of FIG. 216 indicates that the check matrix η of the code rate r of 2,200, which is a code length of 16200 bits, which is specified by the specification of DVB-S.2 shown in FIG. Matrix initial value table. The check matrix initial value table is as described above, and corresponds to the position of the element of the information matrix ηα2 1 according to the code length Ν of the Ldpc code and the information length κ of the Ldpc code, every 360 lines (the number of rows of the tour structure unit Ρ In the first column, check the column number of the 1st line of the l+36〇x(il) of the matrix 135 135786.doc •251 _ 200937872 (Check the column number of the first column of the matrix) Set as the number of the column) only the number of rows of the line of the l + 360x (il) line. In this case, the parity matrix 对应τ corresponding to the co-located long Μ is formed into a step structure ’, which is determined in advance. According to the check matrix initial value table, the information matrix 对应 corresponding to the information length κ in the check matrix 可 can be obtained. The number of columns k+Ι of the check matrix initial value table differs depending on the information length κ. Between the information length K and the number k+1 of the check matrix initial value table, the 〇 relationship of the following formula holds. K = (k + l) x 360 where 360 of the above formula is the number of rows p of the unit of the tour structure. The check matrix initial value table in Fig. 216 has 13 values arranged from the 1st column to the 3rd column, and three values are arranged from the 4th column to the k+th column (the 30th column in Fig. 216). Therefore, the check weight H ❹ of the check matrix H 求出 obtained from the check matrix initial value table of FIG. 216 is from the 1st line to the 1+36〇χ(3-1)-1 behavior 13 from the 1st + 3 60&gt;;&lt; (3-1) line to the first 1 action 3. The first column of the check matrix initial value table of FIG. 216 is 〇, 2〇84, ι613, 1548, 1286, 1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 'this is expressed in the check matrix Η 1 line, the column number is 0, 2084, 1613, 1548, 1286 '1460, 3196, 4297, 2481, 3369, 3451, 4620, 2622 are the elements! (and other elements are 0). Moreover, the second column of the check matrix initial value table of FIG. 216 is 1, 122, 135786.doc • 252·200937872 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, 3108. Indicated in the 361th (=1 + 36 〇χ (2 - 1)) row of the inspection matrix H, the column numbers are 1, 122, 1516, 3448, 2880, 1407, 1847, 3799, 3529, 373, 971, 4358, The element of 3108 is 1. As above, the check matrix initial value table will check the position of the element of the matrix of the matrix 以 1 per 360 lines. Check the line other than the 1+360x(il) line of the matrix ,, that is, the line from the 2+36〇x(il) line to the 36th 〇 line will be determined by checking the matrix initial value table. The element 1 of the l+36〇x(il) line is periodically cyclically shifted in accordance with the same-length length μ (downward direction of the line). That is, for example, the 2+36〇x(il) line only shifts the i+36〇x(il) line downward by only M/360 (=q), followed by the 3+36〇χ ( Μ) The line system rotates the l+36〇x(il) line downward only by 2&gt;&lt;M/360(=2xq) (the second 2+36〇x(il) line is only looped downward Shift M/360 (=q)). Now, if the value of the jth row (jth from the left) of the i-th column of the matrix initial value table (from the top) is expressed as hjj, and the first w-row of the matrix η is checked. If the number of the elements of the j1 is expressed as Hw_j, the column number 11 of the element of the wth line of the line other than the 1+36〇χ(i-Ι) line of the matrix 检查 is checked by the following formula. Out.

Hw.j=mod{hu+ m〇d((w-l), P)xqsM} Here, m〇d(x, y) means dividing y by the remainder after χ. Further, P is the number of rows of the above-described tour structure, and for example, the specification of Dvb-S.2 is 360. Further, q is obtained by dividing the value M/360 obtained by the isometric length by the number of rows P (=360) of the 135786.doc • 253 - 200937872 bits. The LDPC encoding unit 21 specifies the column number of the element of the first + + 36 〇 x (i - 1) row of the check matrix 藉 by checking the matrix initial value table. Further, the LDPC encoding unit 21 obtains the column number of the element of the first comment line of the line other than the 1 + 36 〇 ((-1) line of the check matrix !! ^.3, Generate an inspection matrix 设 set to 1 by the elements of the column number obtained above. Next, a description will be given of an alternative manner of the code bit of the LDPC code by the replacement unit 32 of the demultiplexer 25 of the transmitting device 11, that is, the code bit of the LDPC code and the symbol of the symbol. The change of the allocation mode of the meta-bit (hereinafter also referred to as the bit allocation mode). In the demultiplexer 25, the code bits of the LDPC code are written in the wale direction of the memory 31 in the direction of the X direction of the X direction (N/(mb)) x (mb) bits, and thereafter The mb bit unit is read in the horizontal direction. Further, in the demultiplexer 25, the replacement bit 32 is replaced with the code bit of the mb bit read in the course direction of the memory 31, and the replaced code bit becomes (continuous) b symbols. The oct bit of the mb bit. That is, the replacing unit 32 counts the i-th +1 bit from the most significant bit of the code bit of the mb bit read from the course direction of the memory 3 as the code bit bi, and will Continuously) the highest bit of the mb bit of the b-bit symbol, the i-th bit is calculated as the symbol bit yi, and the code position of the mb bit is replaced according to the specific bit allocation pattern. Yuan b〇 to bmb.!. Figure 217 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10, and the bit can be used when the modulation mode is 4096Q AM and the multiple b is 1. An example of a distribution model. 135786.doc • 254· 200937872 LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 5/6 or 9/1〇. Further modulation is 4〇96QAM, multiples丨, The multiplexer 25 is written in the direction of the x direction in the x direction (64800 / (12 χ 1)) χ (12 &gt;&lt; 1) bits of the memory 31 written in the horizontal direction, to 12x1 The (=mb) bit unit is read and supplied to the replacement unit 32. The replacement unit 32 is configured to read the code bits b from the 12&gt;&lt;1 (=1111) bits of the memory 31 to the bu ' The symbol bit y assigned to the 12xl (= mb) bit of i (= b) symbols is as shown in FIG. To the yn mode, replace the code bits bQ to bn of 12xl (= mb) bits. That is, according to FIG. 217, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having a coding rate of 9/10 in an LDPC code having a code length N of 64,800 bits. An LDPC code is respectively assigned: a code bit bG is assigned to a symbol bit y8, a code bit bh is assigned to a symbol bit y, a code bit b2 is assigned to a symbol bit y6, and a code bit is assigned B3 is assigned to the symbol bit yi, the code bit b4 is assigned to the symbol bit y4, the code bit b5 is assigned to the symbol bit y5, and the code bit b6 is assigned to the symbol bit y2, the code is Bit b7 is assigned to symbol bit y3, code bit b8 is assigned to symbol bit y7, code bit b9 is assigned to symbol bit y 1 〇, and code bit 1)1() is assigned to The symbol bit yu, 135786.doc • 255 - 200937872 assigns the code bit b!! to the symbol bit y 9, and replaces it. Figure 218 is a diagram showing that the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 5/6 or 9/10. The bit modulation can be used in the case where the modulation mode is 4096QAM and the multiple b is 2. An example of a pattern. The LDPC code is an LDPC code having a code length N of 64800 bits and a coding rate of 5/6 or 9/10. In the case where the modulation mode is 4096QAM and the multiple b is 2, the multiplexer 25 is used in the traversing. The code bit written by the memory 31 in the direction X direction of the (64800/〇(12x2))x(12x2) bit is in the course direction, read out in 12x2 (=mb) bit units, and supplied To the replacement unit 32. The replacing unit 32 assigns the code bits bG to b23 read from the 12x2 (= mb) bits of the memory 31 to 12x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bit elements yG to y23 of the bit are replaced by the code bits b〇 to b23 of 12x2 (= mb) bits. That is, according to FIG. 218, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 in an LDPC code having a code length N of 64,800 bits, and an LDPC code having a coding rate of 9/10. An LDPC code is respectively assigned: a code bit bG is assigned to a symbol bit y8, a code bit b2 is assigned to a symbol bit y, a code bit b4 is assigned to a symbol bit y6, and a code bit is assigned B6 is assigned to the symbol bit y!, the code bit b8 is assigned to the symbol bit y4, the code bit b! 〇 is assigned to the symbol bit y 5 , and the code bit b 12 is assigned to the symbol bit Element y 2, 135786.doc -256- 200937872 assigning code bit bi4 to symbol bit y3 ' assigning code bit bi6 to symbol bit y7 ' assigning code bit b 18 to symbol bit y 1 〇 'Assign code bit b2G to symbol bit yii ' Assign code bit b22 to symbol bit y9 ' Assign code bit B to symbol bit y2G ' Assign code bit b3 to character The meta-bit y 1 2, the code bit bs is assigned to the symbol y 18 ' © to assign the code bit b7 to the symbol bit ^3, and the code bit bg is assigned to the symbol y! 6, assign code bit b 11 to symbol bit y 17 ' The element b 13 is assigned to the symbol bit y 14 '. The code bit b15 is assigned to the symbol bit 丫 15, the code bit bi7 is assigned to the symbol y19, and the code bit b 1 9 is assigned to the symbol The bit y 22 assigns the code bit b2 1 to the symbol bit y23, and assigns the code bit b23 to the symbol bit y21 for replacement. Here, the bit allocation pattern of Fig. 21 is a bit allocation pattern of Fig. 217 in the case where the multiple i is directly used. That is, in FIG. 218, the code bit b〇, b2, . . . , t&gt;22 is assigned to the symbol bit yi and the code bit bi, t &gt; 3, · · ·, b23 is the symbol bit The distribution method of Yuanli is the same as the allocation of the symbol bits b〇 to bn of FIG. 217 to the symbol bits yi. Figure 219 shows that the modulation mode is 1024 (^8)^, and 1^?(: code is code length 1^ 135786.doc -257- 200937872 is 16200 bits, coding rate is 3/4, 5/6 or 8/9 LDPC code, the case where the multiple b is 2, and the LDPC code is an LDPC code with a code length N of 64,800 bits, a coding rate of 3/4, 5/6 or 9/10, and a multiple b is 2. An example of a bit allocation pattern that can be used. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/4, 5/6 or 8/9, and further modulation is 1024QAM, and the multiple b is In the case of 2, in the demultiplexer 25, the code bit written in the memory 31 in the direction of the X direction of the X direction (16200 / (1 〇χ 2)) χ (1 〇χ 2) bit is attached to The horizontal direction © is read out in units of l〇x2 (= mb) and supplied to the replacement unit 32. Moreover, the LDPC code has a code length N of 64,800 bits and a coding rate of 3/4, 5/6. Or 9/10 LDPC code, if the modulation mode is 1024QAM and the multiple b is 2, in the multiplexer 25, the direction of the X direction in the wale direction is (64800/(1〇χ2)) χ ( The code bits written by the 10x2) bit memory 31 are in the horizontal direction, read in units of l〇x2 (= mb) bits, and supplied to The 32° replacement unit 32 is configured to transfer the code W bit 1 read from the memory 31x2 (= mb) bit to the b19, and is assigned to consecutive 2 (=b) characters as shown in FIG. Replace the code bits bG to bi9 of 1 〇x2 (= mb) bits by the way of the symbol y〇 to y19 of the l〇x2 (= mb) bit. That is, according to FIG. 219, The replacing unit 32 is an LDPC code having an encoding rate of 3/4 in an LDPC code having a code length N of 16,200 bits, an LDPC code having a coding rate of 5/6, and an LDPC code having an encoding rate of 8/9, and a code length. N is an LDPC code with a coding rate of 3/4 in an LDPC code of 64,800 bits, an LDPC code with a coding rate of 5/6, and an LDPC code with a coding rate of 9/10, with respect to any LDPC code 135786.doc -258 - 200937872 are respectively assigned: the code bit b〇 is assigned to the symbol bit y8, the code bit b] is assigned to the symbol bit y3 ', and the code bit b2 is assigned to the symbol bit y7, the code is Bit b3 is assigned to symbol bit y 1(), code bit b4 is assigned to symbol bit y19, code bit b5 is assigned to symbol bit y4, and code bit % is assigned to symbol bit Element y9, assigning code bit 1)7 to symbol bit y5, and assigning code bit b8 to symbol bit yn, The code bit b9 is assigned to the symbol bit y6, the code bit element 131{) is assigned to the symbol bit 丫14, and the code bit b!丨 is assigned to the symbol bit y!t, the code bit b12 Assigned to the symbol bit y2, the code bit b丨3 is assigned to the symbol bit 8 , the code bit b14 is assigned to the symbol bit y16, and the code bit b15 is assigned to the symbol bit y15. The code bit 1? 6 is assigned to the symbol bit y, the code bit b17 is assigned to the symbol bit y, the code bit b18 is assigned to the symbol bit 713, and the code bit b19 is assigned. Replace the symbol bit 乂^. Figure 220 shows that the modulation mode is 4096QAM, and the LDPC code is an LDPC code with a code length N of 162 〇 0 bits, a coding rate of 5/6 or 8/9, and a multiple b of 135786.doc -259- 200937872 The case 'and the LDPC are examples of the bit allocation pattern that can be used in the case where the code length n is 64,800 bits, the coding rate is 5/6 or 9/10, and the multiple b is 2. The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 5/6 or 8/9. In the case where the modulation method is 4〇96qam and the multiple b is 2, the multiplexer 25 is used in the multiplexer 25, The code bit written in the memory 31 in the wale direction X direction of the (16200/(12x2)) x (12x2) bit is in the course direction, and is read in units of 12x2 (= mb) bits, and It is supplied to the replacement unit 32. ❹ and 'LDPC^ is an LDPC code with a code length N of 64800 bits and a coding rate of 5/6 or 9/10'. Further modulation is 4〇96qAM, and the multiple is 2, in the multiplexer 25 The code bit written in the memory 31 in the X direction of the X direction of the (64800/(12x2)) x (12x2) bit in the wale direction is read in the horizontal direction 'in 12x2 (= mb) bit units And supplied to the replacement unit 32. The replacing unit 32 is configured to assign the code bits bG to bn read from the I2x2 (= mb) bits of the memory 31 to the consecutive 2 (= b) symbols as shown in FIG. 220 ❹ 12x2 (= mb) The bit y of the bit. In the manner of y23, the code bits bQ to b23 of 12&lt;2 (= mb) bits are replaced. That is, according to FIG. 220, the replacing unit 32 is an LDPC code having an encoding rate of 5/6 and an LDPC code having an encoding rate of 8/9 in an LDPC code having a code length N of 16,200 bits, and a code length N being In the 64800-bit LDPC code, the LDPC code with a coding rate of 5/6 and the LDPC code with a coding rate of 9/10 are respectively associated with any LDPC code: the code bit b 〇 is assigned to the symbol bit Yt 〇, 135786.doc -260- 200937872 assign code bit b! to symbol bit y! 5, assign code bit b2 to symbol bit y4, assign code bit b 3 to symbol bit The element y 19 ' assigns the code bit b4 to the symbol bit y21, the code bit b5 to the symbol bit y!6, and the code bit b6 to the symbol bit y23, the code bit b7 Assigned to symbol y 18, assign code bit b8 to symbol y 11, Ο assign code bit b9 to symbol y 14, and assign code bit b! 〇 to symbol Element y22, assigning code bit bu to symbol bit y 5, assigning code bit bi 2 to symbol bit y 6, assigning code bit b! 3 to symbol bit y! 7, The code bit b 14 is assigned to the symbol bit y! 3, and the code bit b ! 5 is assigned to the symbol Element y 20, assigning code bit bi 6 to symbol bit y 1, assigning code bit b! 7 to symbol bit y 3, and assigning code bit b! 8 to symbol bit y 9 , the code bit b 9 is assigned to the symbol bit y 2 , the code bit b2G is assigned to the symbol bit y7 , the code bit b21 is assigned to the symbol bit y8 , and the code bit b22 is assigned to The symbol bit y!2 assigns the code bit b23 to the symbol bit y, and replaces it. • 261 - 135786.doc 200937872 According to the bit allocation pattern shown in Fig. 21 to Fig. 220, the same bit allocation mode can be used for the LDPC code of the plural type, and any one of the LDPC codes of the plural type is used. Both can make the tolerance to the error the required performance. That is, Figs. 221 to 224 show simulation results of BER (Bit Error Rate) in the case where replacement processing is performed in accordance with the bit allocation pattern of Figs. 217 to 220. Further, in Figs. 221 to 224, the horizontal axis represents Es/N 〇 (signal per 1 symbol Ο power to noise power ratio), and the vertical axis represents BER. Further, the solid line indicates the BER in the case where the replacement processing has been performed, and the one-dot dash indicates the BER in the case where the replacement processing is not performed. Figure 221 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and 9/10, respectively. 4096QAM is used as the modulation method, and the multiple b is set to 1, according to the bit allocation mode of Fig. 2.1. Replace the BER in the case of processing. Figure 222 shows an LDPC code with a code length N of 64800 and a coding rate of 5/6 and w 9/10 respectively. 4096QAM is used as the modulation method, and the multiple b is set to 2, according to the bit allocation pattern of Figure 2 The BER in the case of replacement processing. Further, in FIGS. 221 and 222, a graph with a triangular mark indicates a BER with respect to an LDPC code having a coding rate of 5/6, and a graph with a star mark (star mark) indicates that the coding rate is 9/10. The BER of the LDPC code. Figure 223 shows an LDPC code and a code length N of 64800 for a code length N of 16200 and a coding rate of 3/4, 5/6, and 8/9, respectively, and a coding rate of 3/4, 135786.doc -262- 200937872 5/6 and 9/10 1^1&gt; (: code, as a modulation method, 1〇24(^入)^, multiple b is set to 2, and the replacement processing according to the bit allocation mode of Fig. 219 is performed. In addition, in Fig. 223, a graph with a star indicates a BER with a code length of 64800 and a coding rate of 9/l 〇 2 LDPC code, and a graph with an upward triangular mark indicates a code length N. It is 64800, the BER of the LDPC code with a coding rate of 5/6, and the curve with the square mark indicates the BER with a code length N of 64800 and a coding rate of 3/4 iLDpc code. Further s ' in Figure 223 The graph with the circle mark indicates the BER of the LDPC code with the code length N of 1620 〇 and the coding rate of 8/9, and the graph with the downward-facing digonal mark indicates that the code length N is 16200, and the coding rate is The BER of the 5/6 LDPC code and the graph with the positive sign indicates the BER of the LDPC code with a code length N of 16200 and a coding rate of 3/4. For an LDPC code with a code length N of 16200 and a coding rate of 5/6 and 8/9, and an LDPC code with a code length n of 64800 and a coding rate of 5/6 and 9/10 respectively, 4 is used as the modulation method. 96qAM, the multiple b is set to 2, and ber is replaced in accordance with the bit allocation pattern of Fig. 220. Further, the graph with the star attached to Fig. 224 shows that the code length n is 64800 and the coding rate is 9. The BER of the LDPC code of /1〇, the curve circle with the upward triangular mark indicates the BER of the LDPC code with a code length N of 64800 and a coding rate of 5/6 and is shown in Figure 224 with a circle mark. The graph shows the BER of the LDpc code with a code length n of 16200 and a coding rate of 8/9, and a graph with a downward triangle mark indicating that the code length N is 16200 and the coding rate is 5/6. -263 - 200937872 BER of LDPC code 〇 According to Figures 221 to 224, the same bit allocation mode can be used for the LDPC code of the plural type, and any one of the LDPC codes of the plural type using the same bit allocation mode The tolerance to errors can be made to the desired performance. That is, with regard to code length or coding rate In the case where the LDPC codes of the plural types are respectively used in the bit allocation mode dedicated to the LDPC code, although the tolerance to errors is extremely high, the bits of the different types of O LDPC codes must be changed one by one. Distribution mode. On the other hand, according to the bit allocation pattern of FIG. 217 to FIG. 220, the same bit allocation mode can be adopted for each of the plurality of types of LDPC codes having different code lengths or encoding rates, and it is not necessary to adopt the respective types of LDPC codes. In the case of the bit allocation mode dedicated to the LDPC code, the bit allocation pattern is changed one by one for different types of LDPC codes. Further, according to the bit allocation pattern of FIG. 217 to FIG. 220, for each of the plural types of LDPC codes, even if the bit allocation mode dedicated to the LDPC code is slightly used, even if this is still possible, the error can be made. The tolerance is high performance. That is, for example, in the case where the modulation mode is 4096QAM, for an LDPC code having a code length N of 64800 and a coding rate of ij of 5/6 and 9/10, any LDPC code can be used as shown in FIG. 217 or Figure 218 shows the same bit allocation pattern. Then, even with the same bit allocation mode, the tolerance to errors can be made high performance. Further, for example, in the case where the modulation mode is 1024QAM, the code 135786.doc -264- 200937872 has a length N of 16200, and an LDPC code with a coding rate of 3/4, 5/6, and 8/9, respectively, and a code length. For an LDPC code in which N is 64800 and encoding rates are 3/4, 5/6, and 9/10, respectively, the same bit allocation pattern of FIG. 219 can be used for any LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance. Moreover, for example, in the case where the modulation method is 4096QAM, the code length N is 16200, the coding rate is 5/6 and 8/9 LDPC codes, and the code length N is 64800, and the coding rates are 5/6 and 9 respectively. For the LDPC code of /10, the same bit allocation pattern of FIG. 220 can be used for any 〇LDPC code. Then, even if the same bit allocation mode is employed, the tolerance to errors can be made high performance. Further explanation of the change in the bit allocation pattern. Figure 225 is a diagram showing the coding rate of the LDPC code defined by the check matrix 生成 generated by the check matrix generated from the check matrix initial value table shown in Figs. 170 to 215, where the LDPC code is a code length N of 16,200 or 64,800 bits. The LDPC code other than 3/5, the case where the modulation mode is qPSK and the multiple b is 1, the LDPC code can be used. The LDPC code has a code length N of 16200 or 64800 bits and a coding rate of 3. The LDPC code other than /5 'further modulation mode is qPSK, multiplier' in the demultiplexer 25, and the X direction in the wale direction is (&gt;4/(2&gt;&lt;1))&gt;&lt;(2&gt;&lt;1) The bit code written by the memory 31 of the bit is read in the column direction '2x1 (== mb) bit unit and supplied to the replacement unit 32. The replacing unit 3 2 assigns the megabytes ～ and !^ ' read from the 2 X 1 (= mb) bits of the memory 3 1 to 2x1 of i (= b) symbols as shown in FIG. 225 ( = mb) 135786.doc -265- 200937872 yuan symbol y 〇 and yi way, to replace the 2x1 (= mb) bit of the code bit b 〇 and bi °, that is, according to Figure 225, The replacing unit 32 respectively assigns the code bit bG to the symbol bit y, and assigns the code bit b! to the symbol bit y!, and replaces it. In addition, in this case, it is also possible to consider not to replace, and the code bits 1?() and 1)1 are directly used as the symbol bits yc and yi, respectively. Figure 226 shows that the LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5. The bit modulation can be used when the modulation mode is 16Q AM and the multiple b is 2. An example of a distribution model. The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The memory element in which the X-direction is (Ν/(4χ2)) χ (4x2) bits is written in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to Replacement section 32. The ® replacement unit 32 is configured to assign the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to 4x2 (= mb) of consecutive 2 (= b) symbols as shown in FIG. The bit elements y〇 to y7 of the bit are replaced by the code bits bG to b7 of the 4x2 (= mb) bits. That is, according to FIG. 226, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol. The meta-bit y4, 135786.doc -266- 200937872 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit y5, and the code bit b5 to the symbol bit y3 The code bit b6 is assigned to the symbol bit y6, and the code bit b7 is assigned to the symbol bit y〇 for replacement. Figure 227 shows that the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5, and the bit allocation mode can be used when the multiple b Ο is 2. An example. The LDPC code is an LDPC code having a code length N of 16,200 or 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction. The memory level in which the X-direction is (Ν/(6χ2)) χ (6x2) bits is written in the horizontal direction, read in units of 6x2 (= mb) bits, and supplied to Replacement section 32. The replacing unit 32 is configured to assign the code bits bQ to bn of the 6x2 (= mb) bits read from the memory 31 to the consecutive 2 (= b) symbols of the standard 6x2 (= mb) as shown in FIG. The bitwise symbol y〇 to yi丨 of the bit replaces the gigabit bG to b!! of the 6x2 (= mb) bit. That is, according to FIG. 227, the replacing unit 32 assigns the code bit bG to the symbol bit y!!, assigns the code bit bi to the symbol bit y 7, and assigns the code bit b2 to The symbol bit y3, the code bit b3 is assigned to the symbol bit), the code bit b4 is assigned to the symbol y6, 135786.doc -267- 200937872 assigns the code bit b5 to the symbol Bit y2, assign code bit b6 to symbol bit y9, assign code bit b7 to symbol bit y5, assign code bit bs to symbol bit yj, and assign mbit bg to The symbol bit y8 assigns the code bit bi〇 to the symbol bit y4, and assigns the code bit b 1 1 to the symbol bit y〇 for replacement. Figure 228 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and an encoding rate of 3/5, and a multiple of b can be used. The LDPC code is an ldpc code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and a multiple of ba2, the multiplexer 25 is in the direction of the X direction in the wale direction. The code bits written for the memory 31 of (648 〇〇 / (8x2)) x (8x2) bits are in the course direction, read out in 8x2 (= mb) bit units, and supplied to the replacement portion 32. . The replacing unit 32 is configured to assign the code bits bG to bls read from the memory 3128x2 (= mb) bits to the 8x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The symbol bits y〇 to yi5 are substituted for 8χ2 (=_bits of code bits bG to b15. That is, if according to FIG. 228, the replacement unit 32 respectively: assigns the code bit bG to the symbol Bit yi5, assigning code bit b to symbol yi, assigning code bit bz to symbol 713, 135786.doc -268- 200937872 assigning code bit b3 to symbol y3 , the code bit b4 is assigned to the symbol bit y8, the code bit b5 is assigned to the symbol bit yu ', the code bit b6 is assigned to the symbol bit y9, and the code bit b7 is assigned to the symbol bit Element y5, assigning code bit 1)8 to symbol bit 丫1(), assigning code bit b9 to symbol bit y6, and assigning code bit bi〇 to symbol bit y4, Bit b 1 is assigned to symbol bit y7, code bit b12 is assigned to symbol bit 712, code bit b 3 is assigned to symbol bit y 2 , and bit bit b14 is assigned to symbol The bit 丫14 assigns the code bit b15 to the symbol y〇, and performs Change. Figure 229 shows an example in which the modulation mode is 256qam, and the LDPC code is an LDpc code having a code length N of 16,200 bits and an encoding rate of 3/5, and the bit b is 1 in the case where the multiple b is 1. The LDPC code is an ldpc code with a code length n of 162 〇 0 bits and a coding rate of 3/5. The further modulation mode is 256QAM, the multiple bai is used in the multiplexer 25, and the traversing direction is X. The code bit written in the memory 31 of the direction (16200/(8 1)) χ (8χ1) is stored in the horizontal direction, read out in 8X1 (= mb) bit units, and supplied to the replacement unit 32. . The replacement unit 32 is to read "8" from the memory 31 &lt; 1 (= the position of the position of the ring to the b7, as shown in FIG. 229) to the "four" symbol "=_ bit 135786. Doc • 269 · 200937872 yuan symbol y 〇 to y? way to replace 8 &lt; i (= mb) bits of code bits b 〇 b b. That is, if according to Figure 229, replace The part 32 is respectively: assigning the code bit b〇 to the symbol bit y7, assigning the code bit heart to the symbol bit y3, and assigning the code bit t&gt;2 to the symbol bit yi, the code bit The element b&gt;3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y2, the code bit bs is assigned to the symbol bit y6, and the code bit b6 is assigned to the symbol bit h The code bit b7 is assigned to the symbol bit and replaced. Figure 230 shows that the LDPC code is an LDPC code with a code length N of 16200 or 64800 bits and a coding rate of 3/5, and further modulation mode. An example of a bit allocation pattern that can be used when QPSK is a multiple b. The LDpC code is an LDPC code with a code length N of 16200 or 04800 bits and a coding rate of 3/5, and the modulation method is QPSK. When the multiple b is 1, the solution is more The direction of the horizontal direction x of the device 25 is (Ν/(2χ 兀 己 3 3 3 3 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入 写入And supplied to the replacement unit 32. The replacement 邛32 is used to read the code bits 兀~ and 卜 from the 2&gt;&lt;1 (=11^) bits of the memory 31, as shown in Fig. 230 to 1 (= 13) The symbol of the 2xl (= mb) bit of the symbol, and the way to replace the 2xl (= mb) bits of the code bits b and bj. 135786.doc -270 200937872 That is, according to Fig. 230, the replacing unit 32 assigns the code bit bG to the symbol bit y, and assigns the code bit bi to the symbol bit yi, and replaces it. Alternatively, the replacement may be performed, and the code bits 1) and b are directly used as the symbol bits yc and y 1. Figure 231 shows that the LDPC code has a code length N of 64,800 bits and a coding rate of 3/5. The LDPC code is an example in which the bit modulation mode is 16QAM and the multiple b is 2. The LDPC code is an LDPC code with a code length N of 64800 bits and a coding rate of 3/5. , further modulation mode is 16QAM, multiple b is 2 In the case of the multiplexer 25, the memory bits written in the memory 3 of the (64800/(4 χ 2)) χ (4 χ 2) bits in the wales X direction are in the course direction, The 4x2 (= mb) bit unit is read out and supplied to the replacement unit 32. The replacing unit 32 is configured to allocate the code bits b to 4 from the 4x2 (= mb) bits of the memory 31, as shown in Fig. 23 1 to the consecutive 2 (= b) symbols & 4 &gt;&lt;; 2 (= mb) bit symbol bit 丫〇 to 77, to replace the 4x2 (= mb) bit code bits bG to b7. That is, according to FIG. 23, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y, assigns the code bit b! to the symbol bit y 5, and assigns the code bit b2. The symbol bit y1 is assigned to the symbol bit y2, and the code bit b4 is assigned to the symbol y4, 135786.doc -271 - 200937872 assigns the code bit b5 to the symbol The bit y7 assigns the code bit b6 to the symbol bit y3, and assigns the code bit b7 to the symbol bit y6 for replacement. Figure 232 shows an example in which the LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5, and a bit allocation pattern which can be employed in the case where the modulation method is 16QAM and the multiple b is 2.

The LDPC code is an LDPC code having a code length N of 16,200 bits and a coding rate of 3/5. In the case where the modulation method is 16QAM and the multiple b is 2, the multiplexer 25 is in the X direction in the wales. The memory bit written in the memory of the (16200/(4χ2)) χ(4χ2) bit is written in the horizontal direction, read in units of 4x2 (= mb) bits, and supplied to the replacement unit 32. . The replacing unit 32 assigns the code bits bG to b7 read from the 4x2 (= mb) bits of the memory 31 to the 4x2 (= mb) bits of consecutive 2 (= b) symbols as shown in FIG. The meta-bits yG to y7 of the meta-elements replace the code-bits bG to b7 of the 4x2 (= mb) bits. That is, according to FIG. 232, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y7, assigns the code bit b 1 to the symbol bit y 1, and assigns the code bit b2 to the symbol. The meta-bit y4 assigns the code bit b3 to the symbol bit y2, the code bit b4 to the symbol bit ys, the code bit b5 to the symbol bit y3, and the code bit b6. The symbol bit y6, 135786.doc -272- 200937872 is assigned to the symbol bit y〇, and is replaced. Figure 233 shows an example in which the modulation mode is 64QAM, and the LDPC code is an LDPC code having a code length Ν of 64,800 bits and a coding rate of 3/5, and a multiple of b can be used. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 64QAM and the multiple b is 2, the multiplexer 25 is arranged in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(6x2)) x (6x2) bits are in the course direction, read out in units of 6x2 (= mb) bits, and supplied to the replacement unit 32. . The replacing unit 32 is configured to allocate the code bits b to 6 from the 6 &gt;&lt; 2 (= mb) bits of the memory 3 1 to bn as shown in Fig. 233 to 2 consecutive (= b) symbols. 6x2 (= mb) bit symbol y 〇 to y〗! In this way, replace the code bits b6 to b丨 of the 6&lt;2(=mb) bits! . That is, according to FIG. 233, the replacing unit 32 assigns the code bit b〇 to the symbol bit y2, ◎ assigns the code bit b! to the symbol bit y 7, and assigns the code bit b2. For the symbol bit y6, the code bit b3 is assigned to the symbol bit y9, the code bit b4 is assigned to the symbol bit y, and the code bit b5 is assigned to the symbol y3, and the code bit is The element b6 is assigned to the symbol bit y 1, the code bit b7 is assigned to the symbol bit y8, and the code bit b8 is assigned to the symbol bit y4, 135786.doc -273 - 200937872 assigns the code bit % To the symbol element yn, the code bit b1Q is assigned to the symbol bit y5, and the code bit b丨丨 is assigned to the symbol bit yi〇 for replacement. Fig. 234 shows an example in which the modulation mode is 64qam, and the LDPC code is a bit allocation mode in which the code length N is 16,200 bits and the coding rate is 3/5 iLDpc code, and the multiple is ^^. (3) The code is an LDPC © code with a code length N of 16200 bits and a coding rate of 3/5. In the case where the modulation mode is 64QAM and the multiple b is 2, the multiplexer 25 is in the traverse direction X. The horizontal direction is (16200/(6χ2)) χ(6χ2) bits of the suffix 3 1 written code bits are in the horizontal direction, read out in 6x2 (= mb) bit units and supplied To the replacement part 3 2 . The replacing unit 32 assigns the code bits bG to bll ' read from the 6x2 (= mb) bits of the memory 31 to the 6 2 (mb) bits of consecutive 2 (= b) symbols as shown in FIG. In the manner of the meta-symbol yGiyn, the replacement of the &amp; 2 (=@^() bit of the code bit 13() to 1) 11 〇❹, that is, according to FIG. 234, the replacement unit 32 is respectively: The code bit bG is assigned to the symbol bit yn, the code bit b! is assigned to the symbol bit y7, the code bit b&gt;2 is assigned to the symbol bit y3, and the code bit h is assigned to the symbol The bit element 丫1〇, the code bit element t&gt;4 is assigned to the symbol bit y 6, the code bit element t&gt;5 is assigned to the symbol bit y2, and the code bit element be is assigned to the symbol bit y9 , 135786.doc • 274- 200937872 assign code bit b7 to symbol bit y5, assign code bit b8 to symbol bit y 1, assign code bit b9 to symbol bit y8, put code Bit b ίο is assigned to symbol y4, and code bit b 1! is assigned to symbol y 〇 for replacement. Figure 235 shows an example in which the modulation mode is 256QAM, and the LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5, and the multiple b is 2. The LDPC code is an LDPC code having a code length N of 64,800 bits and a coding rate of 3/5. In the case where the modulation method is 256QAM and the multiple b is 2, the multiplexer 25 is disposed in the X direction of the traversing direction. The code bits written in the memory 31 of the direction (64800/(8χ2)) χ (8χ2) bits are in the course direction, read out in 8x2 (= mb) bit units, and supplied to the replacement unit 32. The replacing unit 32 assigns the code bits bQ to b15 read from the 8x2 (= mb) bits of the memory 3 1 to the consecutive 2 (= b) symbols of the symbol 8 8 as shown in FIG. 235; &lt; 2 (= mb) bits of the symbol bits yG to yi5, to replace the 8x2 (= mb) bits of the code bits b 〇 to b! That is, according to FIG. 235, the replacing unit 32 respectively assigns the code bit bG to the symbol bit y2, assigns the code bit b1 to the symbol bit y 11, and assigns the code bit b2 to the symbol. The bit y3, the code bit b3 is assigned to the symbol y4, and the code bit b4 is assigned to the symbol y〇, 135786.doc -275- 200937872 assigns the code bit b5 to the symbol bit Y9, the code bit b6 is assigned to the symbol bit y丨, the code bit b7 is assigned to the symbol bit y8, the code bit b8 is assigned to the symbol bit y! 〇, and the code bit b9 is allocated To the symbol bit y! 3, assign the code bit b1() to the symbol bit y7, and the code bit b! Assigned to the symbol bit y14, the code bit bu is assigned to the symbol bit y6, the code bit bl3 is assigned to the symbol bit y丨5, and the code bit b 14 is assigned to the symbol bit y 5. The code bit 1^5 is assigned to the symbol bit 丫12, and is replaced. Figure 236 shows an example in which the modulation mode is 256QAM, and the LDPC code is a bit allocation mode in which the code length ^^ is 16200 bits, the coding rate is 3/5iLDpc code, and the multiple b is l.

〇 LDPC code is an LDPC code with a code length of 1620 〇 bits and a coding rate of 3/5. Further modulation mode is 256QAM, multiple 1 is 1; in the case of multiplexer 25, in the traverse direction x The horizontal direction is (162 〇〇 / (8 χΐ)) χ (the code bits written by the memory 31 of the 8 兀 系 are in the course direction, are read out in 8 χΐ (four) ^ bit units, and are supplied to the replacement unit 32. The replacing unit 32 is configured to read the code bits b of the 8 x 1 (= mb) bits from the u + pw 目 己 己 3 3 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图 如图The 8xl (= mb) bit symbol y 〇 "7 way" to replace the 8, mb) bit of the code bit b 〇 to by. 135786.doc • 276 · 200937872 that is, according to the figure 236. The replacing unit 32 is respectively: assigning the m-bit b〇 to the symbol bit y7, assigning the code bit b! to the symbol bit y3, and assigning the code bit b2 to the symbol bit y1 The code bit b3 is assigned to the symbol bit y5, the code bit b4 is assigned to the symbol bit y2, the code bit b5 is assigned to the symbol bit y6, and the code bit 1&gt;6 is assigned to the symbol Meta-bit y4, assigning code bit b7 to symbol bit y〇, and replacing Next, the deinterlacer 53 constituting the receiving device 12 will be described. Fig. 237 is a view for explaining the processing of the multiplexer 54 constituting the deinterleaver 53. That is, Fig. 237A shows a functional configuration example of the multiplexer 54. The multiplexer 54 is composed of the inverse replacement unit 1〇〇1 and the memory 1002. The multiplexer 54 is configured to correspond to the transmitting device by using the symbol bit supplied from the symbol of the previous demapping unit 52. The reverse replacement processing (reverse processing of the replacement processing) performed by the multiplexer 25 is performed, that is, the position of the code bit (symbol bit) of the LDPC code replaced by the replacement processing is performed. Returning to the reverse replacement processing of the original position, the LDPC code obtained as a result is supplied to the vertical twist reverse deinterleaver 55 of the subsequent stage. That is, in the multiplexer 54, the reverse replacement unit 1〇〇1 is (continuous The units of b symbols are supplied with the 00 bits of the b symbols y 〇, yi, · · ·, ymb-i 0 The inverse replacement unit 1001 performs the 00 bit symbol position Yuan...to~...back to 135786.doc •277· 200937872 Original mb bit code bit b0, bl,. The arrangement of the (9) structure (4) the replacement of the replacement unit 32 of the demultiplexer 25 on the U side of the sending device is reversed by the arrangement of the preceding code bits bG to bmw, and the bit obtained by the result is output. The code bits bG to bmH. The memory 10 0 2 is the same as the memory 31 constituting the demultiplexer 25 on the side of the transmitting device i, and is contained in the row (horizontal) direction memory 11) bit And: The memory capacity of the N/(mb) bit is stored in the column (longitudinal) direction. That is, the memory 1002 is composed of mb wales of memory N/(mb) bits. In the memory 1002, the code bit of the LDPC code outputted by the inverse replacement unit 1〇〇1 is performed in the direction in which the memory 31 of the demultiplexer of the transmitting device u reads the code bit. Writing is performed in the direction in which the memory bit is written to the memory 3, and the code bit written in the memory 1〇〇2 is read. That is, the multiplexer 54 of the receiving device 12, as shown in Fig. 237A, will be reversed. The code bits of the LDPC code outputted by 卩1001 are written in the order of .mb bits in the direction of the row from the first column of the memory 1〇〇2 to the following. Then, if the writing of the code bit of 1 code long is finished, the multiplexer 54 'reads the code bit from the waling direction from the suffix 1 〇〇 2 ' and supplies it to the rear section. The line twist reverse deinterlacer 5 5 . Here, Fig. 237B shows a reading from the code bits of the memory 1〇〇2. In the multiplexer 54, the code bits of the LDPC code are read from the top to the bottom (the wale direction) in the wales constituting the memory 1 〇〇 2 from the left to the right 135786.doc • 278 • 200937872 is carried out. Next, the processing of the whirling reverse deinterleaver 55 constituting the deinterleaver 53 of the receiving device 12 will be described with reference to FIG. 238 is a diagram showing an example of the structure of the memory 1002 of the multiplexer 54. The memory 1002 has a memory capacity in the longitudinal (longitudinal) direction and a memory capacity of N/(mb) bits in the horizontal (horizontal) direction, and is composed of mb wales. For the memory 1〇〇2, the device controls the write position of the code bit of the LDpc © code in the course direction and the readout position when reading in the wale direction. That is, the whirling reverse deinterleaver 5 5 is configured to appropriately change the start reading position of the start of the m-bit reading for the plurality of wales, thereby performing the arrangement of the code bits rearranged by the wandering parent error. Returning to the inverse rearrangement process of the original arrangement. Here, Fig. 238 shows a configuration example of the "remembered body 1 〇〇 2" in the case where the modulation method is 16QAM and the multiple b is 1. Therefore, the number of bits of the i symbol is 4 bits, and the memory 1〇〇2 is composed of 4 (= mb) vertical lines. The whirling torsional deinterlacer 55 (instead of the multiplexer 54) sequentially writes the code bits of the iLDpc code output from the replacement unit 1〇〇1 in the course direction from the first column of the memory 1002 toward the following. Then, if the writing of the code bit of 1 code long is finished, the whirling reverse deinterleaver 55 is a wales from the left to the right direction, and the code bit is moved from the memory 1002 from the top to the bottom (the wales) Read out of direction). The 'longitudinal torsional de-interlacer 55 is used to write the twentieth 135786.doc • 279· 200937872 interleaver 24 on the side of the transmitting device 11 into the opening of the code bit. s , 3 &lt;The valve start position is read as the start position of the code bit, and the code bit is read from the memory 1〇〇2. That is, if the address of the position of the beginning (topmost) of each wales is set to the address of each position in the waling direction in an ascending integer, the modulation mode is 16QAM and the multiple b is 1. In the case of the walep reverse deinterleaver 55' with respect to the leftmost wales, the start reading position is set to the position where the address is 〇, and the second directional line (from the left) is set, and the read position is set as the address. For the position of 2, for the third wales, the start reading position is set to the position where the address is 4, and with respect to the 4th ordinate, the start reading position is set to the position where the address is 7. Further, regarding the start of the read position is a wales having a position other than the position of the 〇, the reading of the code bit is performed to the lowest position, and the return to the beginning (the address is the position of 〇) is performed until Readout before reading the position before the position is read. Then, the reading from the next (right) wales is performed thereafter. By performing the whirling de-interlacing as above, the arrangement of the code bits rearranged by the wobble interleaving will return to the original arrangement. Next, Fig. 239 is a block diagram showing another configuration example of the receiving device 12. In Fig. 239, the receiving device 12 receives the modulation signal from the transmitting device ’. The data processing device ’ is composed of a quadrature demodulating unit 51, a demapping unit 52, a reverse interleave 53 and an LDPC decoding unit 1〇21. The orthogonal demodulation unit 51 receives the modulated signal from the transmitting device 11, performs quadrature demodulation, and supplies the obtained symbols (values in the I and Q-axis directions) to the demapping unit 52. The demapping unit 52 performs the step of making the symbol from the orthogonal demodulation unit 51 135786. Doc -280· 200937872 The demapping of the code bits of the LDPC code is supplied to the deinterleaver 53 ^ The deinterleaver 53 is composed of a multiplexer 54, a longitudinal torsion deinterleaver 55 and a co-located deinterlacer 1 In other words, the multiplexer 54 performs the deinterlacing of the code bits of the LDPC code from the demapping unit. That is, the multiplexer 54 performs the LDpc code from the demapping unit 52 as the target, and corresponds to the transmitting device U. The inverse replacement processing (reverse processing of the replacement processing) performed by the multiplexer 25, that is, the reverse replacement of the position of the code bit replaced by the replacement processing is returned to the original position, and The LDPC code obtained as a result thereof is supplied to the whirling reverse deinterleaver 55. The whirling reverse deinterleaver 55 takes the LDPC code from the multiplexer 54 as a target, and performs a whirling twist interleaver corresponding to the transmitting device lamp. The longitudinal torsional de-interlacing of the longitudinal torsion interleaving performed as a rearrangement process by 24 is performed. The LDPC code obtained as a result of the longitudinal torsional deinterlacing is supplied from the longitudinal torsional deinterlacer 55 to the in-phase deinterlacer. De-interlacer 101 The code bit element after the whirling de-interlacing of the inverse deinterleaver 55 is used as a target, and the co-interleave (the inverse processing of the co-located interleaving) corresponding to the co-interleave performed by the co-interleaver 23 of the transmitting device is performed, that is, The parity bit of the LDPC code arranged by the co-located interleave is returned to the original depolarization of the original arrangement. The LDPC code obtained as a result of the de-interlacing is supplied from the parrot deinterleaver 1011 to the LDPC decoding unit 1021. In the receiving device 12 of FIG. 239, the LDPC decoding unit 1021 is supplied with 135786 which has undergone reverse replacement processing, vertical reverse deinterlacing, and co-deverse interleaving. Doc -281 · 200937872 The LDPC code, that is, the LDPC code obtained by LDPC coding according to the check matrix. The LDPC decoding unit 1021 performs the LDPC encoding unit LDPC encoding unit 21 for the LDPC coded check matrix Η itself or the conversion check matrix obtained by performing at least the parity interleave row replacement for the check matrix ,. The LDPC code of the LDPC code of the interleaver 53 is decoded, and the data obtained as a result is output as a decoding result of the object data. Here, in the receiving apparatus 12 of FIG. 239, since the LDPC code obtained by the LDPC encoding according to the check matrix is supplied to the LDPC decoding section 1021 from the deinterleaver 53 (the same bit deinterleaver 1011), When the LDPC encoding unit 21 of the transmitting apparatus 11 performs LDPC decoding of the LDPC code by using the check matrix Η itself used for LDPC encoding, the LDPC decoding unit 1021 can sequentially perform a message (check node) by, for example, one node. Decoding device for performing LDPC decoding in the full serial decoding mode of the operation of the message, variable node message, or full parallel decoding (full ®) for simultaneously (parallel) the operation of the message for all nodes The parallel decoding method is configured by a decoding device that performs LDPC decoding. Further, the LDPC decoding unit 1021 performs LDPC decoding of the LDPC code by performing at least the conversion check matrix obtained by the row replacement of the co-interleave by the LDPC encoding unit 21 for the LDPC encoding by the LDPC encoding unit 21 of the transmitting device 11. In the case of a decoding device capable of performing an architecture of a check node operation and a variable node operation at the same time, and including the conversion of the LDPC code to obtain a conversion Check the row of the matrix to replace the same row permutation to rearrange the 135786. Doc 282- 200937872 The decoding device of the received data rearrangement unit 31 of the LDPC code is constructed. Further, in FIG. 239, for convenience of explanation, the multiplexer 54 for performing the reverse replacement processing, the vertical twist reverse deinterleaver 55 for performing the tangent reverse deinterlacing, and the paraxial deinterlacer for the co-located deinterlacing are individually configured. 11. However, 2 or more of the multiplexer 54, the whirling reverse deinterleaver 55, and the in-situ deinterleaver 1〇11 may be the same as the co-interleaver 23, the whirling twist interleaver 24, and the demultiplexer 25 of the transmitting device 11. The ground is composed in one piece. © Fig. 240 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. In Fig. 240, the receiving system is composed of an obtaining unit 1101, a channel decoding processing unit 1102, and an information source decoding processing unit 11〇3. The acquisition unit 1101 obtains, by means of, for example, terrestrial digital broadcasting, satellite digital broadcasting, CATV network, Internet, and other networks, a transmission channel including at least LDPC encoding of image data such as image data or audio data of the program. The signal of the obtained LDPC code is supplied to the channel decoding ◎ processing unit 1102. In the case where the signal acquired by the acquisition unit 1101 is played back from the broadcast station via a ground wave, a satellite wave, a CATV (Cable Television) network, or the like, the acquisition unit 1101 is a level adjuster or an STB ( Set Top Box: Set-top box). In the case where the signal acquired by the acquisition unit lio is transmitted by multicast from a web server such as IPTV (Internet Protocol Television), the acquisition unit 1101 is, for example, an NIC (Network Interface Card: Network interface card), etc. 135786. Doc -283 - 200937872 Network I/F (Interface: interface). The transmission channel decoding processing unit 1102 applies a channel decoding process including at least a process of making a mistake in the transmission path to the signal acquired by the acquisition unit 丨1〇1 via the transmission channel, and supplies the signal obtained as a result. The information source decoding processing unit 1103 is used. In other words, the signal obtained by the acquisition unit 1101 via the transmission channel is a signal obtained by at least performing error correction coding for correcting the error generated by the transmission path, and the transmission channel decoding processing unit 1102 applies the signal to the signal. The channel decoding processing is performed by, for example, error correction processing. Here, as the error correction code, there are, for example, LDPC code or Lie Solomon code. Here, at least the lDPC encoding is performed as the error correction code. Moreover, the transmission channel decoding process may include demodulation of a modulated signal or the like. The information source decoding processing unit 1103 applies an information source decoding process including at least a process of stretching the compressed information into the original information for the signal subjected to the channel gamma processing. That is, the signal acquired by the acquisition unit 1101 via the transmission path may be subjected to compression coding of compressed information in order to reduce the amount of data such as images or sounds of information. In this case, the information source decoding processing unit 1103 is For the signal subjected to the channel decoding processing, information source decoding processing such as processing (stretching processing) of compressing the information into the original information is performed. Further, when the signal acquired by the acquisition unit 110 via the transmission path is not subjected to compression coding, the information source decoding processing unit 1103 does not perform the process of extending the compressed information into the original information. 135786. Doc-284-200937872 Here, as the stretching processing, for example, mpeg decoding or the like is used. Moreover, the channel decoding processing may include a descrambling code or the like in addition to the stretching processing. In the reception system configured as described above, the acquisition unit 1101 performs compression coding such as MPEG encoding on data such as images and audio, and further acquires a signal of error correction coding such as LDPC coding via the transmission path and supplies it. To the transmission channel decoding processing unit 102. The channel decoding processing unit 1102 applies, for example, to the orthogonal demodulation unit 51 or the demodulation unit 52, the deinterleaver 53, and the LDPC decoding unit 56 as the channel decoding processing for the signal from the acquisition unit 1101 ( Alternatively, the LDPC decoding unit 1021) performs the same processing, and the signal obtained as a result is supplied to the information source decoding processing unit 11 〇3. The information source decoding processing unit 1103 applies an information source decoding process such as decoding to the channel decoding processing unit 1102, and outputs an image or sound obtained as a result. The receiving system of the diagram 240 on X can be applied to, for example, a television level adjuster that receives a television broadcast as a digital video player. Further, the acquisition unit lioi, the transmission channel decoding processing unit 11〇2, and the information source decoding processing unit 1103 respectively It can be configured as a separate device (hardware (1 (: Integrated Circuit), etc.) or a software module). Further, the acquisition unit 1101, the channel decoding processing unit n〇2, and the information source The decoding processing unit 1103 can transmit the acquisition unit 11〇1 and the set of the transmission channel decoding processing unit 1102, or the set of the channel decoding processing unit 11〇2 and the information source decoding processing unit 11〇3, and the acquisition unit 1101. The set of the channel decoding processing unit ιι〇2 and the information source decoding processing unit 1103 is configured as a separate device. Doc-285-200937872 Figure 241 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. In the drawings, the parts corresponding to those in the case of Fig. 240 are attached with the same reference numerals, and the description thereof will be omitted as appropriate. The receiving system of FIG. 241 is the point where the receiving unit 1101, the channel decoding processing unit 1102, and the information source decoding processing unit 1103 are included, and is similar to the case where the output unit 1111 is newly provided, and FIG. 240 The situation is different. The output unit 1111 is, for example, a display device that displays an image or a speaker that outputs an audio, and outputs an image or sound as a signal output from the information source decoding processing unit 1103. That is, the output unit U11 displays an image or outputs a sound. The receiving system as shown in Fig. 241 above can be applied to, for example, a TV (television receiver) that receives television broadcast as digital broadcast, or a broadcast receiver that receives broadcast broadcast, and the like. Further, when the signal acquired by the acquisition unit 1101 is not subjected to compression coding, the signal output from the transmission channel decoding processing unit 1102 is supplied to the output port 1 m. Fig. 242 shows the reception applicable to the reception device 12. Block diagram of the third structural example of the system. In the drawings, the same reference numerals are attached to the portions corresponding to those in the case of Fig. 240, and the description thereof will be omitted as appropriate. The receiving system of Fig. 242 is the same as the case of Fig. 240, in the point that the acquisition unit 11〇1 and the channel decanting unit 1102 are included. The receiving system of FIG. 242 is not provided with the information source decoding processing unit 135786. Doc -286· 200937872 11 03 and the new recording unit ii21 is different from the case of Fig. 24〇. The s recording unit 1121 records the washing (for example, the TS packet of the MPEG TS) outputted by the channel gamma processing unit 1102, and records (memorizes) the optical disk or the hard disk (magnetic disk), flashing. Record (memory) media such as memory. The receiving system as shown in Fig. 242 above can be applied to a video recorder or the like which records a television broadcast. Further, in FIG. 242, the receiving system is configured by the information source decoding processing unit 1103, and the information source decoding processing unit 11〇3 can record the signal subjected to the information source decoding processing by the recording unit 1121, that is, by Decode the image or sound obtained. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram for explaining a check matrix H of an LDPC code. Figure 2 is a flow chart showing the decoding procedure of the LDPC code. Fig. 3 is a view showing an example of a check matrix of an LDPC code. Fig. 4 is a view showing a graph of the check matrix &amp;111161&gt;. Figure 5 is a diagram showing a variable node. Figure 6 is a diagram showing a check node. Fig. 7 is a view showing an example of a configuration of an embodiment of a transport system to which the present invention is applied. Fig. 8 is a block diagram showing a configuration example of the transmission device &&gt; α and the clothing set 11. Figure 9 is a diagram showing an inspection matrix. Fig. 10 is a view showing a parity matrix. I35786. Doc •287· 200937872 Figure 1 ΙΑ, B is DVB-S. The check matrix and row weight map of the LDPC code specified in the specification of 2. 12A and B are diagrams showing the signal point arrangement of 16QAM. Figure 13 is a diagram showing the signal point configuration of 64QAM. Figure 14 is a diagram showing the signal point configuration of 64QAM. Figure 15 is a diagram showing the signal point configuration of 64QAM. 16A-D are diagrams illustrating the processing of the multiplexer 25. 17A and B are diagrams for explaining the processing of the multiplexer 25. © Fig. 1 8 is a diagram showing a Tanner graph of decoding of an LDPC code. 19A and 19B are diagrams showing a parity matrix Ητ which is a step structure and a Tanner graph corresponding to the parity matrix Ητ. Figure 20 is a diagram showing the parity matrix Ητ of the check matrix 对应 corresponding to the LDPC code after the co-located interleaving. Fig. 21A and Fig. 21 are views showing a conversion check matrix. Fig. 22 is a view showing the processing of the whirling twist interleaver 24. Fig. 23 is a view showing the number of wales of the memory 3 1 and the address of the start writing position of the memory 3 1 necessary for the whirling of the wales. Fig. 24 is a view showing the number of wales of the memory 3 1 and the address at which the writing position is started, which are necessary for the whirling of the wagger. Fig. 25 is a flow chart showing the transmission processing. 26A and 26B are diagrams showing a model of a communication channel used in the simulation. Fig. 27 is a graph showing the relationship between the error rate obtained by the simulation and the Bucher frequency fd of the flutter. Figure 28 shows the error rate obtained by the simulation and the flutter frequency of the flutter 135786. Doc • 288- 200937872 Diagram of the relationship between fd. FIG. 29 is a block diagram showing a configuration example of the LDPC encoding unit 21. Fig. 30 is a flow chart for explaining the processing of the LDPC encoding unit 21. Fig. 31 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 16200. Figure 32 is a diagram showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 33 is a view showing a check matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 34 is a view showing an inspection matrix initial value table of a coding rate of 2/3 and a code length of 64,800. Fig. 35 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 16200. Fig. 36 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 37 is a diagram showing the initial value of the check matrix of the coding rate of 3/4 and the code length of 64,800. Fig. 38 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 39 is a view showing an inspection matrix initial value table of a coding rate of 3/4 and a code length of 64,800. Fig. 40 is a view showing a check matrix initial value table of a coding rate of 4/5 and a code length of 16200. Figure 41 is a table showing the initial value of the check matrix of the coding rate of 4/5 and the code length of 64,800. Doc -289- 200937872. Fig. 42 is a view showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Figure 43 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 44 is a diagram showing an inspection matrix initial value table of a coding rate of 4/5 and a code length of 64,800. Fig. 45 is a view showing an initial value of the check matrix of a coding rate of 5/6 and a code length of 16,200. Fig. 46 is a view showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 47 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 48 is a diagram showing an inspection matrix initial value table of a coding rate of 5/6 and a code length of 64,800. Figure 49 is a diagram showing the initial value of the check matrix of the coding rate of 5/6 and the code length of 64,800. Fig. 50 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 16200. Figure 51 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 52 is a diagram showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 53 is a table showing the initial value of the check matrix of the coding rate of 8/9 and the code length of 64,800. Doc -290- 200937872 Picture. Fig. 54 is a view showing an inspection matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Fig. 55 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 56 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 57 is a diagram showing the initial value of the inspection matrix of the coding rate of 9/10 and the code length of 64800. Fig. 58 is a view showing a table of initial values of inspection matrices of a coding rate of 9/10 and a code length of 64,800. Fig. 59 is a view for explaining a method of obtaining a check matrix 从 from a check matrix initial value table. Figures 60A through C are diagrams illustrating the replacement process of the current mode. Fig. 61Α~C are diagrams showing the replacement processing of the current mode. 62A and B are diagrams showing a group of code bits and a group of symbol bits in the case where an LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 63 is a diagram showing the distribution rule in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 64A and Fig. 64 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 2/3 is modulated by 1024QAM and the multiple b is 1. 65A and B show a modulation code length of 64800 with a 1024QAM and a coding rate of 135786. Doc -291 - 200937872 2/3 LDPC code in the case of the code bit group and the symbol bit group. Fig. 66 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM. Fig. 67A and Fig. 67 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 2/3 is modulated by 1024QAM and the multiple b is 1. Fig. 68A and Fig. 68 are diagrams showing a group of code bits and a group of symbol bits in the case where the LDPC code having a code length of 16200 and a coding rate of / 3/4 is modulated by 1024QAM. Fig. 69 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM. Fig. 70A and Fig. 70 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 3/4 is modulated by 1024QAM and the multiple b is 1. 71A and FIG. 7B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of /3/4 is modulated by 1024QAM. Fig. 72 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM. Fig. 73A and Fig. 73 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 3/4 is modulated by 1024QAM and the multiple b is 1. Figure 74A, B shows the modulation code length of 16200 with 1024QAM, coding rate 135786. Doc -292- 200937872 4/5 LDPC code in the case of the code bit group and the symbol bit group. Fig. 75 is a diagram showing the distribution rule |J in the case where the LDPC code having a code length of 16200 and a coding rate of 4/;5 is modulated by 1024QAM. 76A and FIG. 76B are diagrams showing the replacement of the megabits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 1024QAM and the multiple b is 1. 77A and 77B are diagrams showing a code bit group and a symbol bit group in the case of 1024QAM modulation code length 64800 and LDPC code of 4/5/5. Fig. 78 is a diagram showing the distribution rule 1j in the case where the LDPC Ma is modulated by a code length of 64800 and a coding rate of 4/5. 79A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the 1024CAM modulation code length 64800, the coding rate 4/5 LDPC code', and the multiple b is 1. 80A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 162 〇〇 and an encoding rate of / 5/6 is modulated by 1024QAM. Fig. 81 is a diagram showing an allocation rule 1J in the case where an LDPC code having a code length of 162 〇〇 and a coding rate of 5/6 is modulated by 1024QAM. Fig. 82A and Fig. 82 are diagrams showing the replacement of the code bits in accordance with the allocation rule in the case where the LDPC code ′ of the coding length of 162 〇〇 and the coding rate of 5/6 is modulated by 1024QAM and the multiple 13 is 丨. Fig. 83A and Fig. B show the a1〇24QAM modulation length 648〇〇, coding rate 135786. Doc • 293 200937872 5/6 LDPC code in the case of the code bit group and the symbol bit group. Fig. 84 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM. 85A and FIG. 85 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 1. 86A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM. Fig. 87 is a diagram showing an allocation rule |J in the case where an LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM. 88A and FIG. 28B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 1024QAM and the multiple b is 1. 89A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 4.8/9 is modulated by 1024QAM. Fig. 90 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 1024QAM. 91A and FIG. 26B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 1024QAM and the multiple b is 1. Figure 92A and Figure B show the modulation code length of 64800 with 1024QAM and the coding rate of 135786. Doc -294- 200937872 9/10 LDPC code in the case of the code bit group and the symbol bit group. Fig. 93 is a diagram showing the distribution rule in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM. Fig. 94A and Fig. 94 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM and the multiple b is 1. Fig. 95A and Fig. 95 are diagrams showing a group of code bits and a group of symbol bits in the case where the LDPC code having a code length of 16200 and a coding rate of / 2/3 is modulated by 4096QAM. Fig. 96 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM. 97A and FIG. 97B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 1. 98A and FIG. 28B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM. Fig. 99 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM. Figs. 100A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 1. Figure 101A, B shows the modulation code length of 16200 with 4096QAM, coding rate 135786. Doc -295 - 200937872 The diagram of the code bit group and the symbol bit group in the case of the 3/4 LDPC code. Fig. 102 is a diagram showing a distribution rule ij in the case where an LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM. Fig. 103A and Fig. 103 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 1. Figs. 104A and B are views showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of / 3/4 is modulated by 4096QAM. Fig. 105 is a diagram showing an allocation rule 1J in the case where an LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM. Fig. 106A and Fig. 106 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 1. 107A and B are diagrams showing a group of code bits and a group of symbol bits in the case where an LDPC code having a code length of 16200 and a coding rate of W 4/5 is modulated by 4096QAM. Fig. 108 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM. Figs. 109A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 4/5 is modulated by 4096QAM and the multiple b is 1. Figure 110A, B shows the modulation code length of 64800 with 4096QAM, coding rate 135786. Doc -296· 200937872 4/5 LDPC code in the case of the code bit group and the symbol bit group. Fig. 111 is a diagram showing an allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM. Fig. 112A and Fig. 4B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 1. 113A and FIG. 31B are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 16200 and a coding rate of / 5/6 is modulated by 4096QAM. Fig. 114 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM. Figs. 115A and 1B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 1. Fig. 116A and Fig. 116 are diagrams showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate 〇 w 5/6 is modulated by 4096QAM. Figure 117 is a diagram showing the allocation rule |J in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM. Fig. 118A and Fig. 118 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 1. Figure 119A, B shows the modulation code length of 16200 with 4096QAM, coding rate 135786. Doc -297- 200937872 The figure of the code bit group and the symbol bit group in the case of the 8/9 LDPC code. Fig. 120 is a diagram showing the distribution rule ij in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM. 121A and B are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length 16200 and the coding rate 8/9 is modulated by 4096QAM and the multiple b is 1. Figs. 122A and B are views showing a code bit group and a symbol bit group in the case where the LDPC code having a code length of 64800 and a coding rate of / 8/9 is modulated by 4096QAM. Figure 123 is a diagram showing an allocation rule in the case where an LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM. Fig. 124A and Fig. 124 are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 4096QAM and the multiple b is 1. Figs. 125A and B are views showing a code bit group and a symbol bit group in the case where an LDPC code having a code length of 64800 and a coding rate of w 9/10 is modulated by 4096QAM. Figure 126 is a diagram showing a distribution rule ij in the case where an LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 4096QAM. 127A and BB are diagrams showing the replacement of the code bits according to the allocation rule in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 4096QAM and the multiple b is 1. Figure 128 is a diagram showing the signal point configuration of 1024QAM. 135786. Doc -298· 200937872 Figure 129 is a diagram showing the signal point configuration of 4096QAM. Fig. 130 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 131 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 132 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Figure 133 is a diagram showing the simulation results of the BER after the replacement process has been performed and the case where the process has not been performed. Figures 134A-C are diagrams showing the replacement of the code bits in the case where the multiple b is 1. Figs. 135A to CG are diagrams showing the replacement of the code bits in the case where the multiple b of the replacement mode of the code bit in the case where the multiple b is 1 is used. Figure 136 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Figure 137 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 1024QAM and the multiple b is 2. Figure 138 is a diagram showing replacement of code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Figure 139 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 1024QAM and the multiple b is 2. Fig. 140 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 1024QAM and the multiple b is 2. Figure 141 shows the modulo code length of 64800 with 1024QAM and the coding rate of 4/5. Doc -299- 200937872 LDPC code, and the replacement of the code bits in the case of multiple b is 2. Figure 142 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Figure 143 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 1024QAM and the multiple b is 2. Figure 144 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. Figure 145 is a diagram showing the replacement of the code bits in the case where the LDPC code of the code length of 64800 and the coding rate of 8/9 is modulated by 1024QAM and the multiple b is 2. Figure 146 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 9/10 is modulated by 1024QAM and the multiple b is 2. Figure 147 is a diagram showing replacement of code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Figure 148 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 2/3 is modulated by 4096QAM and the multiple b is 2. Figure 149 is a diagram showing the replacement of the code bits in the case where the W LDPC code having a code length of 16200 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Fig. 150 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 3/4 is modulated by 4096QAM and the multiple b is 2. Figure 151 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Figure 152 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 4/5 is modulated by 4096QAM and the multiple b is 2. Figure 153 shows the 4096QAM modulation code length of 16200 and the coding rate of 5/6. Doc • 300- 200937872 LDPC code, and the replacement of the code bits in the case of multiple b is 2. Figure 154 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 5/6 is modulated by 4096QAM and the multiple b is 2. Figure 155 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 16200 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figure 156 is a diagram showing the replacement of the code bits in the case where the LDPC code having a code length of 64800 and a coding rate of 8/9 is modulated by 4096QAM and the multiple b is 2. Figure 157 is a diagram showing the replacement of the code bits in the case where the LDPC code of the code length of 64800 and the coding rate of 9/10 is modulated by 4096QAM and the multiple b is 2. Figure 158 is a diagram showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 1 59 shows the case where the replacement process has been performed and the case where it has not been performed. A diagram of the simulation results of the BER. Fig. 160 is a view showing the simulation results of the case where the replacement process has been performed and the case where the BER has not been performed. Fig. 1 is a diagram showing the simulation results of the BER of the 〇 w in the case where the replacement process has been performed and the case where the replacement process has not been performed. Fig. 162 is a block diagram showing a configuration example of the receiving device 12. Figure 163 is a flow chart illustrating the receiving process. Figure 164 is a diagram showing an example of a check matrix of an LDPC code. Fig. 1 is a diagram showing a matrix (conversion check matrix) after the column replacement and row replacement are applied to the inspection matrix. Figure 166 is a diagram showing a conversion check matrix divided into 5x5 units. Figure 167 is a diagram showing an example of a structure in which P decoding devices performing node operations are summarized. Doc • Block diagram of 301 - 200937872. 168 is a block diagram showing a configuration example of the LDPC decoding unit 56. Fig. 1 is a block diagram showing a configuration example of an embodiment of a computer to which the present invention is applied. Fig. 170 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 16,200. Figure 171 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. 〇 Fig. 172 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 173 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 2/3 and a code length of 64,800. Figure 174 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 16200. Figure 175 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. ❹ Figure 176 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 177 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Figure 178 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/4 and a code length of 64,800. Fig. 1 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 16200. 135786. Doc -302- 200937872 Fig. 180 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 181 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 182 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. Figure 183 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 4/5 and a code length of 64,800. 〇 Fig. 184 is a diagram showing an example of an initial value of a check matrix of a coding rate of 5/6 and a code length of 16200. Figure 185 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 186 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. Figure 187 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 5/6 and a code length of 64,800. ® Figure 188 is a diagram showing an example of the initial value of the inspection matrix with a coding rate of 5/6 and a code length of 64,800. Figure 189 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 16200. Figure 190 is a diagram showing an example of a check matrix initial value table of a coding rate of 8/9 and a code length of 64,800. Figure 191 is a diagram showing an example of an initial value of a check matrix of a coding rate of 8/9 and a code length of 64,800. 135786. Doc -303 - 200937872 Figure 192 is a diagram showing an example of an initial value of the check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 193 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 8/9 and a code length of 64,800. Figure 194 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 195 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. © Fig. 196 is a diagram showing an example of an initial value of the check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 197 is a diagram showing an example of an initial value of a check matrix of a coding rate of 9/10 and a code length of 64,800. Figure 198 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. Figure 199 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 64,800. w Fig. 200 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 64,800. Fig. 201 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 64,800. Fig. 202 is a diagram showing an example of a check matrix initial value table of a coding rate of 2/5 and a code length of 64,800. Figure 203 is a diagram showing an example of a check matrix initial value table of a coding rate of 2/5 and a code length of 64,800. 135786. Doc -304- 200937872 Fig. 204 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 64,800. Figure 205 is a diagram showing an example of a check matrix initial value table of a coding rate of 1/2 and a code length of 64,800. Fig. 206 is a view showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 64,800. Figure 207 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. 〇 Figure 208 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Figure 209 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 3/5 and a code length of 64,800. Fig. 2 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/4 and a code length of 16,200. Figure 211 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/3 and a code length of 16200. ® Figure 212 is a diagram showing an example of an initial value of the check matrix of a coding rate of 2/5 and a code length of 16200. Figure 213 is a diagram showing an example of a table of initial values of a check matrix of a coding rate of 1/2 and a code length of 16,200. Figure 214 is a diagram showing an example of a check matrix initial value table of a coding rate of 3/5 and a code length of 16200. Figure 215 is a diagram showing another example of the check matrix initial value table of the coding rate 3/5 and the code length 16200. 135786. Doc -305- 200937872 Fig. 21 6 is a diagram illustrating a method of obtaining a check matrix 从 from a check matrix initial value table. Figure 217 is a diagram showing an alternative of a code bit. Figure 218 is a diagram showing an alternative of a code bit. Figure 219 is a diagram showing an alternative of a code bit. Figure 220 is a diagram showing an alternative of a code bit. Figure 221 is a diagram showing the simulation result of BER. Figure 222 is a diagram showing the simulation result of the BER. Ο Figure 223 is a diagram showing the simulation results of BER. Figure 224 is a diagram showing the simulation result of BER. Figure 225 is a diagram showing an alternative of a code bit. Figure 226 is a diagram showing an alternative of a code bit. Figure 227 is a diagram showing an alternative of a code bit. Figure 228 is a diagram showing an alternative of a code bit. Figure 229 is a diagram showing an alternative of a code bit. Figure 230 is a diagram showing an alternative of a code bit. ® Figure 23 1 is a diagram showing an alternative to a code bit. Figure 232 is a diagram showing an alternative of a code bit. Figure 233 is a diagram showing an alternative of a code bit. Figure 234 is a diagram showing an alternative of a code bit. Figure 2 3 5 shows a diagram of an alternative to a code bit. Figure 236 is a diagram showing an alternative of a code bit. Fig. 237A and Β are diagrams showing the processing of the multiplexer 54 constituting the deinterleaver 53. 135786. Doc-306-200937872 Figure 238 is a diagram illustrating the processing of the whirling torsional deinterlacer 55. Figure 239 is a block diagram showing another configuration example of the receiving device 12. Fig. 24 is a block diagram showing a first configuration example of a receiving system applicable to the receiving device 12. Fig. 241 is a block diagram showing a second configuration example of a receiving system applicable to the receiving device 12. Figure 242 is a block diagram showing a third configuration example of a receiving system applicable to the receiving device 12. 〇[Main component symbol description] 11 Transmitting device 12 Receiving device 21 LDPC encoding unit 22 Bit interleaver 23 Co-located interleaver 24 Vertical twist interleaver 25 Demultiplexer 26 Mapping unit 27 Quadrature modulation unit 31 Memory 32 Substitution unit 51 orthogonal demodulation unit 52 demapping unit 53 deinterleaver 54 multiplexer 135786. Doc 200937872 〇 ❹

55 vertical twist deinterleaver 56 LDPC decoding unit 300 branch data storage memory 301 selector 302 check node calculation unit 303 cyclic shift circuit 304 branch data storage memory 305 selector 306 receiving data memory 307 variable node calculation unit 308 cyclic shift circuit 309 decoded word calculation unit 310 received data rearrangement unit 311 decoded data rearrangement unit 601 coding processing unit 602 memory unit 611 coding rate setting unit 612 initial value table reading unit 613 inspection matrix Generating unit 614 Information bit reading unit 615 Coding unit calculating unit 616 Control unit 701 Bus bar 702 CPU 135786.doc -308- 200937872

703 ROM 704 RAM 705 Hard disk 706 Output unit 707 Input unit 708 Communication unit 709 Disk drive 710 Input/output interface 711 Portable recording medium 1001 Reverse replacement unit 1002 Memory 1011 Parrot deinterleaver 1021 LDPC decoding unit 1101 Acquisition unit 1102 Transmission channel decoding processing unit 1103 Information source decoding processing unit 1111 Output unit 1121 Recording unit 135786.doc 309-

Claims (1)

200937872 X. Patent application scope: 1. A data processing device, comprising a replacement mechanism, which is an LDPC (Low Density Parity Check) with a memory code length of N bits in the horizontal direction and the longitudinal direction. The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 16200 a bit element and an LDPC code having a coding rate of 2/3; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024QAM as one of the symbols. Any one of 1024 signal points; the memory mechanism includes 20 vertical rows of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; the foregoing replacement mechanism is to be in the memory mechanism The 1st and 2nd bit code bits of the 135786.doc 200937872 are read from the row direction. The i+1th bit is set to the bit bi, and the 2 consecutive symbols are 10&gt;;&lt; 2-bit symbol bit is calculated from the highest bit and the i+th bit is set to bit P '. The following replacement is performed according to the foregoing allocation rule: assigning bit bQ to bit y8, Bit b2 is assigned to bit y, bit b4 is assigned to bit y 1, bit b6 is assigned to bit y2, bit b8 is assigned to bit y3, bit b1G is assigned to bit Y4, assigning bit b12 to bit y6', assigning bit b! 4 to bit y 5, assigning bit bi 6 to bit y 9 ' allocating bit bis Assigning bit y7 ' to bit y 18 ' is assigned to bit y 18 ' assigning bit b3 to bit y 1 〇 ' assigning bit b5 to bit yu ' assigning bit b7 to bit yi2, will Bit b9 is assigned to bit y 1 3 ' assigns bit b 11 to bit y 14 ' assigns bit bi3 to bit yi6 ' assigns bit b 1 5 to bit y 1 5 ' b 1 7 is assigned to bit y 1 9 ' The bit b19 is assigned to bit yi7. -2- 135786.doc 200937872 2 A data processing apparatus comprising a replacement mechanism for LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and the specific positive integer is set to b. The memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism. After reading in the horizontal direction, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for the LDPC code are used. The element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or The code w specified by the specification of DVB-T.2 has a length N of 64,800 bits. The code rate is 2/3 LDPC code; the m bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signals determined by 1024QAM. Any one of the points; the memory mechanism includes 20 wales of 10x2 bits in the row direction and 64800/(10x2) bits in the waling direction; the replacement mechanism is in the course direction of the memory mechanism The read 10x2 bit code bit is set to 135786.doc 200937872 bit bi from the highest bit, and will be 1 〇X2 bit of 2 consecutive symbols In the case of a meta-bit, the first sub-score is calculated from the highest-order bit, and the i-th bit is set to the bit yi. The following is replaced by the rule: assigning the bit b〇 to the bit ys, the bit b2 Assigned to bit y, assign bit b4 to bit y 1, assign bit b6 to bit y2, assign bit b8 to bit y3, 〇 assign bit b! 〇 to bit y 4. Assign bit b12 to bit ' Assign bit b14 to bit y5, bit b 16 to bit y 9 ' Assign bit b!8 to Element y7, assigning bit b! to bit yi8, assigning bit b3 to bit y 1 〇' assigning bit b5 to bit y 11 ' 分配 assigning bit b7 to bit yi2, bit The element b9 is assigned to the bit y 13, the bit b! t is assigned to the bit y 14 'the bit b!3 is assigned to the bit y 16 ' and the bit b! 5 is assigned to the bit y 15 ' The element b17 is assigned to the bit yi9, and the bit bi 9 is assigned to the bit y 17. 3. A data processing device comprising a replacement mechanism 'Ssunson 4- 135786.doc 200937872 LDPC (Low Density Parity Check) having a length of N bits in the horizontal direction and the longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. Then, in the foregoing direction, when the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the code for the LDPC code is used. The bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 16,200 bits, The code rate is 3/4 LDPC code; 〇w the m bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 determined by 1024QAM. Any one of the signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction, and 16200/(10x2) bits in the waling direction; the replacement mechanism is transverse to the memory mechanism The code bit of the 10x2 bit read out in the column direction is set to the bit bi from the highest bit, and the symbol bit of the 10x2 bit of the preceding two symbols is 135786. .doc 200937872 The i+1th bit is set to bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: assigning bit bQ to bit y6, and assigning bit to bit y4, Bit b4 is assigned to bit y8, bit b6 is assigned to bit y5, bit b8 is assigned to bit y, bit b! 〇 is assigned to bit y 2 '. Bit b 12 is assigned The bit y 1 ' is assigned a bit bi 4 to the bit y 3 , the bit b 6 is assigned to the bit y9 ' The bit b 8 is assigned to the bit y7 , assigning the bit b丨 to the bit y! 6, assigning the bit b3 to the bit y 14, assigning the bit b5 to the bit y18, and assigning the bit b7 to the bit y15, ❿ the bit b 9 is assigned to the bit y 1 〇, the bit h! is assigned to the bit y12, the bit b13 is assigned to the bit yn ', the bit b! 5 is assigned to the bit y 13, and the bit b17 is assigned Bit y19, bit b19 is assigned to bit y17. A data processing apparatus comprising a replacement mechanism for LDPC having a length of N bits in a row direction and a longitudinal direction (Low 135786.doc -6 - 200937872 Density Parity Check) The m-bit of the code bit of the LDPC code read in the preceding direction of the memory direction of the memory element of the code bit is used as one symbol, and the specific positive integer is set to b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing direction, the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, and the code for the LDPC code is used. The bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified in the specification of DVB-T.2 is 64,800 bits, An LDPC code having a coding rate of 3/4; the m-bit is 10 bits, and the integer b is 2; w 10 bits of the code bit are mapped to 1024 bits determined by 1024QAM as one of the preceding symbols Any one of the signal points; the memory mechanism includes 20 wales that store 10 0 2 bits in the horizontal direction, and 64800/(10×2) bits in the longitudinal direction; the replacement mechanism is in the horizontal direction of the foregoing memory mechanism The code bit of the 10x2 bit read from the column direction is set to the bit bi from the highest bit, and the symbol bits of the 10x2 bits of the preceding two symbols are The i+th bit is set to bit yi from the highest bit, and the following replacement is performed according to the aforementioned allocation 135786.doc 200937872 rule: assigning bit bG to bit y6 ' assigning bit b2 to bit y4 'Assigning bit b4 to bit y8' assigns bit b6 to bit y5, bit b8 to bit y, bit b1Q to bit y2, bit b12 to bit Yi, 分配 assign bit b14 to bit y3, bit b16 to bit y9 ' assign bit b!8 to bit y7, will The bit b! is assigned to the bit yi6, the bit b3 is assigned to the bit y!4', the bit b5 is assigned to the bit y丨8', the bit b7 is assigned to the bit y 15, and the bit b9 is assigned The bit y 1 〇 is assigned, the bit b 丨 is assigned to the bit y 12 , and the bit b 丨 3 is assigned to the bit y 丨! The bit b丨5 is assigned to the bit y! 3, the bit b丨7 is assigned to the bit y丨9, and the bit b! 9 is assigned to the bit y]7. A data processing device comprising a replacement mechanism for recording a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction 135786.doc 200937872 The m-bit of the code bit of the LDPC code read in the preceding row direction and written in the above-mentioned column direction is regarded as one symbol, and the specific positive integer is set to b, The memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and thereafter Reading in the horizontal direction, in the case where the code © bit of the mb bit read in the direction of the direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is used. Allocating an allocation rule to the symbol bit indicating the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 16,200 bits, code The LDPC code is 4/5; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by W 1024QAM. Any one of the above; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the waling direction; the replacement mechanism is in the direction of the memory mechanism The coded bit of the read 10x2 bit is set to the bit bi from the highest bit, and the symbol bit of the 10x2 bit of the consecutive two preceding symbols is from the highest bit. From the first calculation, the i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: 135786.doc 200937872 Assigning the bit b〇 to the bit y6 'Assigning the bit b2 to the bit y4 ' Bit b4 is assigned to bit y8'. Bit b6 is assigned to bit y5'. Bit b8 is assigned to bit y〇'. Bit b is assigned to bit y2'. Bit b! 2 Assigned to bit y 1 ' Assign bit b 丨 4 to bit y 3 ' 分配 Assign bit b! 6 to bit y 9 ' Assign bit b! 8 to bit y 7 , assigning bit b! to bit y! 6, assigning bit b3 to bit y! 4, assigning bit b5 to bit y! 8 ' assigning bit b7 to bit y丨5, The bit b9 is assigned to the bit y! 〇, the bit b! i is assigned to the bit y 丨 2, 位 the bit bi 3 is assigned to the bit y! !, and the bit bi 5 is assigned to the bit yi 3. Assign bit b 1 7 to bit y丨9 and bit b! 9 to bit yi 7. 6. A data processing device, comprising: a replacement mechanism for LDPC (Low Density Parity Check) with a memory code length of N bits in a row direction and a longitudinal direction Recalling that the m-bit of the preceding LDPC code of the 135786.doc 10-200937872 written in the preceding direction of the mechanism is read as a symbol. And ι is a specific positive integer set to b, the memory means memorizes mb bits in the horizontal direction, and stores N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are in the foregoing memory mechanism Write in the wale direction, and then read in the horizontal direction, and when the code bits of the mb bits read in the direction of the memory mechanism are used as the b symbols, © Substituting the code bit of the foregoing LDPC code into an allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC Code length N specified by the specification of DVB-S.2 or DVB-T.2 64800 bits, LDPC code with a coding rate of 4/5; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols. Any one of the 1024 signal points; ¥ The memory mechanism contains 20 vertical lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction; the above replacement mechanism will be in the foregoing memory The 10x2 bit code bit read by the direction of the mechanism is set to the bit bi from the highest bit, and the symbol of 10x2 bits of the preceding two symbols is consecutive. The bit is calculated from the highest bit, and the i+th bit is set to bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y6, 135786.doc 200937872 assigns the bit b2 to Bit y4 'distribute bit b4 to bit' assigns bit b6 to bit ys, bit b8 to bit y, bit b1G to bit y2, and bit b12 to bit Bit yi ' assigns bit b! 4 to bit y 3, bit b! 6 to bit y 9, and assigns bit b! 8 to Bit y 7 ' assigns bit b to bit y16, bit b3 to bit y i4 , bit b5 to bit y 丨 8 , and bit b 7 to bit y ! 5 , bit b9 is assigned to bit y10, bit bj 1 is assigned to bit y12, bit b 丨 3 is assigned to bit yn, bit b15 is assigned to bit y13, bit b! Assigned to bit y 1 9, assigns bit b ! 9 to bit y 丨 7. 7. A data processing apparatus, comprising: a replacement mechanism for a code bit of an LdpC (L〇w Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory mechanism in the preceding direction is taken as one symbol, and 135786.doc -12-200937872 is a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to an allocation rule indicating the symbol bit of the foregoing symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code system DVB-S The code length N specified by the .2 or DVB-T.2 specification is 16,200 bits. The LDPC code with a coding rate of 5/6; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 of 1024QAM as one of the aforementioned symbols. Any one of the signal points; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction, and 16200/(10x2) bits in the longitudinal direction; the replacement mechanism is transverse to the memory mechanism The code bit of the 10x2 bit read from the column direction is set to the bit bi from the highest bit, and the symbol bits of the 10x2 bits of the preceding two symbols are The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y6, and the bit b2 is assigned to the bit y4, 135786.doc -13- 200937872 Assign bit b4 to bit ye ' Assign bit b6 to bit ys ' Assign bit b8 to bit y〇' Assign bit b! 〇 to bit y2 ' Place bit b ! 2 is assigned to bit y 1 ' assigns bit bi 4 to bit y3 ' assigns bit b! 6 to bit y 9 ' assigns bit b 18 to bit Element y7 ' © assigns bit 1 ^ to bit 丫 16 ' assigns bit b3 to bit yi4 ' assigns bit b 5 to bit y 18 and bit b 7 to bit y 15, Assigning bit b9 to bit y丨〇, assigning bit b! i to bit y 〗 2, and assigning bit 丨3 to bit yH, Bit b15 is assigned to bit y13, bit b17 is assigned to bit y19, and bit b! 9 is assigned to bit y7. A data processing device comprising: a replacement mechanism in which a code bit of an ldPC (Low Bit Check) code having a memory code length of N bits in a row direction and a wale direction is recorded in the direction of the row The m-bit specific positive integer of the code bit of the aforementioned LDPC code written as the first symbol and the Density Parity Check: the low-density memory device is read as b, 135786.doc • 14- 200937872 The memory mechanism memorizes mb bits in the preceding row direction and memorizes N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 64800 The LDPC code having a coding rate of 5/6; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 determined by 1024QAM as one of the preceding symbols. Any one of the signal points; the memory mechanism contains 20 vertical lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction; ® the replacement mechanism is in the foregoing memory mechanism The code bit of the 10x2 bit read out in the course direction is set to the bit bi from the highest bit, and the symbol bit of 10x2 bits of the preceding two symbols is consecutively The i + + Ι bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y6, and the bit b2 is assigned to the bit y4, and the bit is set. Element b4 is assigned to bit y8, 135786.doc -15- 200937872 assigns bit b6 to bit y5 ' assigns bit b8 to bit y〇' assigns bit b!〇 to bit y2 ' The element b ! 2 is assigned to the bit y 1, the bit b 丨 4 is assigned to the bit y 3 ', the bit b 丨 6 is assigned to the bit y 9, and the bit b 丨 8 The allocation bit y 7, assigns the bit bi to the bit y 16, 分配 assigns the bit b3 to the bit y 14, assigns the bit b5 to the bit y 丨 8 , and assigns the bit b 7 to the bit y 15, the bit b9 is assigned to the bit y 丨 0, the bit b 11 is assigned to the bit y 12, the bit b 13 is assigned to the bit y! 丨, and the bit b 15 is assigned to the bit y! 3. Assign bit b17 to bit y丨9, © assign bit b 1 9 to bit y丨7. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and written in the row direction of the mechanism is defined as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memory mb bit, and the preceding 135786.doc -16· 200937872 describes the longitudinal direction memory N/(mb) bit, and the code bit of the LDPC code is written in the foregoing longitudinal direction of the memory mechanism, Then, in the foregoing direction, when the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the code for the LDPC code is used. The bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol element; 〇 the aforementioned LDPC code system DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 16,200 bits An LDPC code having a coding rate of 8/9; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signals determined by 1024QAM. Any one of the points; the memory mechanism includes 20 longitudinal lines of 10x2 bits in the horizontal direction and 16200/(10x2) bits in the longitudinal direction; the replacement mechanism is in the direction of the memory mechanism The coded bit of the 10x2 bit read out is set to the bit bi from the highest bit, and the symbol of the 10x2 bit of the preceding two symbols is the highest. The bit element is calculated from the i + Ι bit as the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, and the bit b2 is assigned to the bit y 〇, the bit is allocated B4 is assigned to bit y 1, bit b6 is assigned to bit y2, 135786.doc -17- 200937872 bit 8 is assigned to bit y3 ' bit b1G is assigned to bit y4 ' bit b! 2 Assigned to bit y6 'Assign bit b ! 4 to bit y 5 ' Assign bit b! 6 to bit y9 and bit b 1 8 to bit y 7 'Assign bit b ! to bit y 1 8 and bit b3 to bit y 1 〇' 分配 Assign bit b5 to bit yn and bit b7 to bit y!2 , the bit b9 is assigned to the bit y 13, the bit bi is assigned to the bit y! 4, the bit bi 3 is assigned to the bit y 〗 6, and the bit b! 5 is assigned to the y 丨5. Assign bit b 1 7 to bit y丨9 and bit b 1 9 to bit y7. A data processing apparatus comprising: a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, the memory mechanism The mb bits are memorized in the preceding row direction, and the N/(mb) bits are memorized in the longitudinal direction, 135786.doc • 18- 200937872 The code bits of the aforementioned LDPC code are written in the foregoing longitudinal direction of the memory mechanism And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or DVB-T.2 specifications specified in the code length N is 64800 The LDPC code having a coding rate of 8/9; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 determined by 1024QAM as one of the preceding symbols. Any one of the signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the longitudinal direction; the replacement mechanism is transverse to the aforementioned memory mechanism The code bit of the 10x2 bit read out in the column direction is set from the highest bit, the i+th bit is set to the ® bit bi, and the symbol bits of the 10x2 bits of the preceding two symbols are consecutively The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y〇, Bit b4 is assigned to bit y 1, bit b6 is assigned to bit y2, bit b8 is assigned to bit y3, 135786.doc •19- 200937872 assign bit b ! 〇 to bit y4 ' Bit b 丨 2 is assigned to bit y6 ' Byte b14 is assigned to bit y5 ' Byte b16 is assigned to bit y9 ' Assign bit b18 Bit y7, bit b 1 is assigned to bit y 18 '. Bit b3 is assigned to bit y 1 〇 'Band b5 is assigned to bit y 11, 位 Bit b7 is assigned to bit y 12 , assign bit b9 to bit y 13, bit b! Assigned to bit y14, bit b! 3 is assigned to bit y6, bit b15 is assigned to bit y15, bit b17 is assigned to bit y19, bit b 1 9 is assigned to bit Y丨7. U. A data processing apparatus, comprising: a replacement mechanism, which is a code position of an LDPC (l〇w Density Parity Check) code whose memory code length is a Ν bit in the horizontal direction and the longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory device of the element is used as one symbol, and the specific positive integer is b. The memory unit memorizes the mb bits in the foregoing direction, and memorizes the N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are just described in the foregoing vertical direction of the memory mechanism 135786.doc •20 · 200937872 is written, and then read in the horizontal direction, and the code bits of the mb bits read in the direction of the memory of the memory mechanism are used as b symbols, Allocating a code bit of the foregoing LDPC code to an allocation rule indicating a symbol bit of the foregoing symbol, replacing a code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code The code length N specified by the specifications of DVB-S.2 or DVB-T.2 is 64800. LDPC code with a bit rate and a coding rate of 9/10; 前述 the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024QAM as one of the aforementioned symbols Any one of 1024 signal points; the memory mechanism includes 20 wales that store 10 0 2 bits in the horizontal direction, and 64800/(10×2) bits in the longitudinal direction; the foregoing replacement mechanism is in the foregoing memory The 10x2 bit code bit read by the direction of the mechanism is set to the bit bi from the highest bit, and the symbol of 10x2 bits of the preceding two symbols is consecutive. The bit element® is set to the bit yi from the highest bit bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y. 〇, assigning bit b4 to bit y 1, assigning bit b6 to bit y2, assigning bit b8 to bit y3, and assigning bit b! 〇 to bit y 4, 135786.doc - 21 - 200937872 assigns bit b12 to bit y6, bit b14 to bit y5 ' assigns bit b16 to bit' assigns bit b18 to Element y7' assigns bit b! to bit y! 8, assigns bit b3 to bit y! 〇 ' assigns bit b5 to bit y!!, assigns bit b7 to bit y12 ' © Assign bit b9 to bit y13, bit b! Assigned to bit y ! 4, bit b 13 is assigned to bit y 丨 6 , bit b 15 is assigned to bit y15 , bit b 1 7 is assigned to bit y 丨 9 , bit b 19 Assigned to bit y 17. 12. A data processing apparatus comprising: a replacement mechanism for a code bit of an LDPC (Low Density Parhy Check) code having a length of N bits in a row direction and a longitudinal direction The code bit element of the LDPC code read in the direction of the row in the memory direction of the memory mechanism is taken as a symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction stores mb bits, and the N/(mb) bit is memorized in the longitudinal direction, and the imaginary position of the LDPC code is written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, 135786.doc -22· 200937872 In the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are taken as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified in the specification of DVB-T.2 is 16,200 bits, The bit rate is 2/3 LDPC code; the m bit is 12 bits, and the integer b is 2; 12 12 bits of the foregoing code bit are mapped as one of the aforementioned symbols to 4096 determined by 4096QAM Any one of the signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the row direction, and 16200/(12x2) bits in the wales direction; the replacement mechanism is in the course of the foregoing memory mechanism The 12x2 bit code bit read by the direction is set to the bit ratio from the highest bit, and the 12x2 bit of the preceding two symbols is the highest. The bit i-th is set to the bit yi, and the following replacement is performed according to the above-mentioned allocation® rule: the bit bG is assigned to the bit y! 〇, and the bit b2 is assigned to the bit y〇, Bit b4 is assigned to bit yi, bit b6 is assigned to bit y2, bit b8 is assigned to bit y3, bit b! 〇 is assigned to bit y 4, bit bi 2 is assigned to Bit y 5, 135786.doc -23 - 200937872 Assign bit b ! 4 to bit y6 Assign bit b! 6 to bit y 8 Assign bit b! 8 to bit Element y 7, assigning bit b2Q to bit y 11, assigning bit b22 to bit y9 ' assign bit b! to bit y22, bit b3 to bit y 12, place bit B5 is assigned to bit y! 3, 位 bit b7 is assigned to bit y14, bit b9 is assigned to bit y! 5, bit b! 丨 is assigned to bit y丨6, bit b is 3 is assigned to the bit y 17, the bit b! 5 is assigned to the bit y] 8, the bit bi 7 is assigned to the bit y20, the bit b19 is assigned to the bit y19, and the bit b21 is assigned to Bit y23, © assigns bit b23 to bit y2 1. 13. A data processing apparatus comprising: a replacement mechanism for LDpC (L〇w Density parity Chee) ^ low density parity check code code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code, which is read in the preceding direction of the memory device of the bit, is read as the first symbol, and the specific positive integer is set to b. The memory mechanism memorizes mb bits in the foregoing direction, and stores the N/(mb) bits in the wale direction in the first 135786.doc •24·200937872, and the code bits of the LDPC code are in the foregoing memory mechanism. Writing in the wale direction, and then reading in the horizontal direction, and in the case where the code bits of the mb bits read in the row direction of the memory mechanism are used as b symbols, Allocating the code bit of the foregoing LDPC code to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; 〇 the foregoing LDPC The code length of the code system DVB-S.2 or DVB-T.2 is 6480. 0 bit, LDPC code with a coding rate of 2/3; the m bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols Any one of 4096 signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 64800/(12x2) bits in the waling direction; the foregoing replacement mechanism is in the foregoing memory mechanism The code bit of the 12x2 bit read by the direction of the row is set to the bit bi from the highest bit, and the symbol of 12x2 bits of the preceding two symbols is consecutively The bit is calculated from the highest bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y! 〇, and the bit b2 is assigned to the bit Y〇, assigning bit b4 to bit y 1, assigning bit b6 to bit y2, 135786.doc -25- 200937872 assigning bit b8 to bit y3 and bit b1G to bit y4 , assigning bit bi2 to bit ys, assigning bit b! 4 to bit y 6, assigning bit b! 6 to bit y 8, assigning bit 8 to Element y7, assigning bit b2G to bit y 1 1 ' assigning bit b22 to bit y9, © assigning bit b! to bit y22, and assigning bit b3 to bit y丨2, Bit b5 is assigned to bit y!3, bit b7 is assigned to bit y!4, bit b9 is assigned to bit y!5, bit b! 1 is assigned to bit y!6 The bit b 丨 3 is assigned to the bit y 丨 7 , the bit b _ 5 is assigned to the bit y 丨 8 , 位 the bit b 17 is assigned to the bit y 20 , and the bit b ! 9 is assigned to the bit y丨9, the bit b2! is assigned to the bit y23, and the bit b23 is assigned to the bit y21. 14. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the aforementioned LDPC code written in the preceding direction of the mechanism and read in the above-mentioned course direction is 135786.doc -26-200937872, and the specific positive integer is set as one symbol. b, the memory means memorizes mb bits in the row direction, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory means, After reading in the foregoing direction, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code for the LDPC code is used. The bit element is allocated to an allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 16,200 bits. An LDPC code having a coding rate of 3/4; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 signals determined by 4096QAM. Any of the points; the aforementioned memory mechanism contains 24 wales of 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; the replacement mechanism is in the course of the aforementioned memory mechanism The 12x2 bit code bit read by the direction is set to the bit bi from the highest bit, and the 12x2 bit of the preceding two symbols is the highest. The i+th bit is set to the bit yi from the bit bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y8, 135786.doc -27- 200937872 assigns the bit b2 to the bit Yuan y, assigning bit b4 to bit y6, bit b6 to bit y 1, assigning bit b8 to bit y4, assigning bit bt 〇 to bit y 5, bit b! 2 is assigned to bit y 2, bit b! 4 is assigned to bit y 3, bit b! 6 is assigned to bit y 7, Assigning bit b! 8 to bit y! 〇, assigning bit b2G to bit yn, assigning bit b22 to bit y9, assigning bit b! to bit y2〇, bit b3 Assigned to bit y 12, bit b5 is assigned to bit yu, bit b7 is assigned to bit y 13, bit b9 is assigned to bit yi6, bit b is assigned to bit y 17, Bit b! 3 is assigned to bit y 1 4, bit b! 5 is assigned to bit y 1 5, bit bi 7 is assigned to bit y 19, bit b 1 9 is assigned to bit y 22. The bit b2! is assigned to the bit y23, and the bit b23 is assigned to the bit y2i. 15. A data processing apparatus comprising a replacement mechanism, which is a LDPC (Low Density Parity Check) having a length of N bits in the horizontal direction and the longitudinal direction of the -28-135786.doc 200937872 The m-bit of the code bit of the LDPC code read in the preceding direction of the memory unit of the code bit is written as one symbol, and the specific positive integer is set. In the case of b, the memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified in the specification of DVB-T.2 is 64800 bits, The coding rate is 3/4 LDPC code; ® the m bit is 12 bits, and the aforementioned integer b is 2; the 12 bits of the above code bit are mapped as one of the aforementioned symbols to 4096 determined by 4096QAM Any one of the signal points; the memory mechanism includes 24 longitudinal lines of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction; the replacement mechanism is in the course of the foregoing memory mechanism The 12x2 bit code bit read by the direction is set to the bit bi from the highest bit, and the 12x2 bit of the preceding symbol is consecutively 135786. Doc •29· 200937872 The i+i bit is set to the bit yi from the highest bit. The following replacement is performed according to the above allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit. Yuan y, assigning bit b4 to bit y6, assigning bit b6 to bit y 1, assigning bit b8 to bit, and assigning bit b 1 ο to bit y 5, The bit b! 2 is assigned to the bit y 2, the bit bi 4 is assigned to the bit y 3 , the bit bi 6 is assigned to the bit y 7, and the bit b 8 is assigned to the bit y 1 〇 Assigning bit b2G to bit y 11, assigning bit b22 to bit y9, assigning bit b! to bit y2, assigning bit b3 to bit y 12, allocating bit b5 Given bit y 18, assign bit b7 to bit y 13, assign bit b9 to bit y 16, assign bit bi! to bit y 17, assign bit b! 3 to bit y 1 4, assign bit b! 5 to bit y 15, assign bit b! 7 to bit y 19, assign bit b ! 9 to bit y22, -30- 135786.doc 200937872 Bit b2! is assigned to bit y23, and bit b23 is assigned to bit y2 1. 16. A data processing apparatus comprising: a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory mechanism is read as one symbol, and the specific positive integer is b, and the memory mechanism is Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the aforementioned mb bit, ® replaces the replaced code bit as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S.2 or DVB-T. LDPC code with a code length N of 16200 bits and a coding rate of 4/5 as specified in the specification of 2 The m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; Contains 24 wales of 12x2 bits in the horizontal direction and 16200/(12x2) bits in the walith direction; 135786.doc •31 - 200937872 The above replacement mechanism will be read in the direction of the aforementioned memory mechanism. The 12x2 bit code bit is set to the bit bi from the highest bit, and the 12x2 bit symbol of the last two symbols is counted from the highest bit. The i+1th bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, the bit b2 is assigned to the bit y, and the bit b4 is assigned to the bit Element y6, © assigns bit b6 to bit y 1, assigns bit b8 to bit y4, assigns bit b! 〇 to bit y 5 ' assigns bit b! 2 to bit y 2 ' Assign bit bi4 to bit y3, bit b丨6 to bit y 7, assign bit b!8 to bit yίο 'divide bit b2 Assignment bit y 11 ' 分配 Assign bit b22 to bit y 9 ' Assign bit bi to bit y2 〇 ' Assign bit b3 to bit y 12 ' Assign bit b5 to bit yu ' Assigning bit b7 to bit yu ' assigning bit b9 to bit yi6 ' assigning bit b! t to bit y 1 7 ' assigning bit b13 to bit yi4 ' 135786.doc -32- 200937872 assigns bit b 1 5 to bit y! 5, assigns bit bi 7 to bit y! 9, assigns bit b ! 9 to bit y 22, and assigns bit b21 to bit y23 , the bit b23 is assigned to the bit y21. 17. A data processing apparatus, comprising: a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the preceding direction written in the preceding direction is regarded as one symbol, and the specific positive integer is set to b, the foregoing memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, in the case where the code bit of the mb bit read in the foregoing direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is assigned to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The code length N specified by the specification of .2 is 64800 bits, and the LDPC code with a coding rate of 4/5 The m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to 4096 signal points determined by 135786.doc -33-200937872 4096QAM. Any one of the foregoing memory means includes one wales of 12 χ 2 bits in the horizontal direction and 64800 / (12 x 2) bits in the longitudinal direction; the replacement mechanism is read in the course direction of the memory mechanism The code bit of the 12x2 bit is calculated from the highest bit, and the +1st value is set to the bit bi ' and the 12x2 bits of the 2 consecutive symbols are consecutively the highest. The i+th bit is set to the bit yi from the bit position, and the following replacement is performed according to the foregoing allocation rule: ® assigns the bit to the bit y8, and assigns the bit b2 to the bit y, the bit B4 is assigned to bit y6, bit b6 is assigned to bit y!, bit b8 is assigned to bit y4, bit b1() is assigned to bit y5, bit bi 2 is assigned to bit y 2. Assign bit b14 to bit y3, G assign bit bi6 to bit y7, and assign bit b丨8 to bit y 1 〇, The element b2G is assigned to the bit y 11 ' to assign the bit b22 to the bit y9 ' to assign the bit b 给 to the bit y2 〇 ' to assign the bit b3 to the bit y 12 ' to assign the bit b5 to the bit y 18 ' Assign bit b7 to bit y 13 ' 135786.doc -34- 200937872 Assign bit b9 to bit yu, bit b 1 1 to bit y丨7, bit b 1 3 is assigned to bit yi 4, bit b! 5 is assigned to bit y 丨 5, bit b 1 7 is assigned to bit y 1 9 , bit b -9 is assigned to bit y22, bit is placed The element b2 1 is assigned to the bit y23, and the bit b23 is assigned to the bit y2 丨. ® I8. A data processing device comprising a replacement mechanism for a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the preceding direction of the memory mechanism is taken as a symbol, and the specific positive integer is set to b, 前述 the foregoing memory mechanism Storing mb bits in the preceding array direction, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bit of the element read in the foregoing direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is assigned to the symbol The allocation rule of the symbol bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the code of the foregoing LDPC code is DVB-S.2 or DVB-T.2 The specifications are 135,786.doc -35- 200937872 and the length is 16,200. The coding rate is 5/62 LDpc code; the m bit is 12 bits, and the integer b is 2; the 12 bits of the code bit are mapped to 4096 signals determined by 4096QAM as the first symbol. Any one of the points; the memory mechanism includes 24 longitudinal lines that memorize 12 χ 2 bits in the horizontal direction and memory 16200/(12x2) bits in the longitudinal direction; the replacement mechanism is in the direction of the aforementioned memory mechanism Read out The code bit of 12 X 2 bits is set from the highest bit to the third bit and the bit is set to bit bi, and the 12x2 bits of the preceding two symbols are assigned to the highest bit. The i+1th bit from the bit count is set as the bit edge, and the following substitution is performed according to the above-mentioned sub-rule: 77 assigning the bit b〇 to the bit y 8, assigning the bit b2 to the bit y〇, Bit b4 is assigned to bit y6, bit b6 is assigned to bit yi, bit b8 is assigned to bit y4, bit b 1 〇 is assigned to bit y 5 , bit b! 2 is assigned to Bit y 2, assign bit b ! 4 to bit y 3, assign bit b 16 to bit y 7, assign bit bi8 to bit yi 〇, and assign bit b2G to bit y 11 'Assign bit b22 to bit y 9, assign bit b! to bit y2〇' 135786.doc -36- 200937872 Assign bit b3 to bit y 12 ' Assign bit b5 to bit Element y18' assigns bit b7 to bit y 13 ' assigns bit b9 to bit y 16 ' assigns bit bn to bit yn ' assigns bit bi3 to bit yu, assigns bit b15 To the bit yis, the bit b! 7 Dispensing bit y 19, ❹ 19. ❹ bit b 19 to the bit y22, the bit b 1 to the bit〗 y23 'y2i bits allocated to bit b23. A data processing device comprising a replacement mechanism for a memory device of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the row direction and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is in the foregoing row. The direction stores the mb bit, and the N/(mb) bit is memorized in the longitudinal direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism and then read in the direction of the row. In the case where the code bit of the element read in the foregoing direction of the memory mechanism is used as the b symbols, the code of the aforementioned LDPC code is used to assign the symbol 135786.doc • 37· 200937872 The allocation rule of the symbol of the meta-sub-bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is 64,800 bits and the coding rate is 5/6. LDPC code; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; The memory mechanism includes 24 vertical lines of memory 12x2 bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction; the replacement mechanism is 12x2 read in the direction of the memory mechanism. The code bit of the bit is set to the bit bi from the highest bit, and the symbol bits of the 12x2 bits of the two consecutive symbols are counted from the highest bit. The i+Ι bit is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: assigning the bit bG to the bit y 8, assigning the bit b2 to the bit y〇, ◎ allocating the bit b4 to the bit Element y6, assigning bit b6 to bit y!, - assigning bit bg to bit y4, assigning bit b! 〇 to bit y 5, and assigning bit b 12 to bit y 2, Assign bit b 14 to bit y 3, bit b! 6 to bit y 7, assign bit b! 8 to bit y! 〇, 135786.doc -38 - 2009378 72 assigning bit b2G to bit y 11 ' assigning bit b22 to bit y9 ' assigning bit bi to bit y2 〇 ' assigning bit b3 to bit y 〗 2, assigning bit b5 The bit y8 is assigned, the bit b7 is assigned to the bit y!3, the bit b9 is assigned to the bit y16, the bit b11 is assigned to the bit y丨7, and the bit b13 is assigned to the bit Y14, the bit b! 5 is assigned to the bit yf 5, the bit b17 is assigned to the bit y19, the bit b丨9 is assigned to the bit y22, and the bit b21 is assigned to the bit y23, the bit is allocated B23 is assigned to bit y21. 20. A data processing apparatus comprising a replacement mechanism for a code position of an LDpc (L〇w Density Parity Check) code having a memory code length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code, which is written in the preceding direction of the memory device of the meta-memory, is used as the symbol, and the specific positive integer is b. The memory mechanism memorizes the mb bit ' in the foregoing direction and stores N/(mb) bits in the preceding direction, and the code bits of the LDPC code are written in the preceding direction of the memory mechanism. Read in the above-mentioned course direction, 135786.doc -39· 200937872 in the case where the mb bits of the mb bits read in the aforementioned direction of the memory mechanism are used as the b symbols, The code bit of the foregoing LDPC code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code system The code length N specified by the specifications of DVB-S.2 or DVB-T.2 is 16,200 bits. An LDPC code having a coding rate of 8/9; the m-bit is 12 bits, and the integer b is 2; 12 12 bits of the code bit are mapped to 4096 bits determined by 4096QAM as one of the preceding symbols Any one of the signal points; the memory mechanism includes 24 wales that memorize 12x2 bits in the row direction, and 16200/(12x2) bits in the wales direction; the replacement mechanism is in the course of the foregoing memory mechanism The 12x2 bit code bit read by the direction is set to the bit bi from the highest bit, and the 12x2 bit of the preceding two symbols is the highest. The i+th bit is set to the bit yi from the bit bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y丨〇, and the bit b2 is assigned to the bit y〇, Bit b4 is assigned to bit y 1, bit b6 is assigned to bit y2, bit b8 is assigned to bit y3, bit b! 〇 is assigned to bit y 4, bit bi 2 is assigned to Bit y 5, 135786.doc -40- 200937872 assigns bit bi4 to bit y6 ' assigns bit b丨6 to bit y 8 ' allocates bit b 1 8 Bit y7' assigns bit b2G to bit y11', assigns bit b22 to bit y9, assigns bit bi to bit y22', assigns bit b3 to bit y12, bit b5 Assigned to bit y 13, 分配 Assign bit b7 to bit y 4, assign bit b9 to bit y 15, assign bit b ]! to bit y! 6, assign bit bi 3 to bit y丨7 , assigning bit b! 5 to bit yi 8, assigning bit b17 to bit y20, assigning bit b 19 to bit y 19, and assigning bit b2 丨 to bit y23, bit B23 is assigned to bit y2i. A data processing apparatus comprising: a replacement mechanism for remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding direction of the mechanism and written in the direction of the row is regarded as one symbol, and the specific positive integer is set to b. Memorizing the meme bits in the preceding row direction and storing the N/(mb) bits in the wale direction in the preceding paragraph 135786.doc 200937872, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, and replaces the code bit of the mb bit, and the replaced code bit is used as the symbol bit; ® LDPC code system DVB-S The code length N specified by .2 or DVB-T.2 is 64,800 bits. An LDPC code having a coding rate of 8/9; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 signals determined by 4096QAM. Any one of the points; the memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction, and 64800/(12x2) bits in the waling direction; the replacement mechanism is in the direction of the memory mechanism The read 12x2 bit code bit is set to the bit bi from the highest bit, and the 12x2 bit of the preceding two symbols is from the highest bit. The i+th bit is set to the bit yi from the bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y! 〇, and the bit b2 is assigned to the bit y〇, and the bit is The element b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, 135786.doc -42- 200937872 the bit b8 is assigned to the bit y3 'the bit b!o is assigned to the bit y4 Bi2 is assigned to bit y5, bit b is assigned to bit eight, bit b16 is assigned to bit y8, bit b!8 is assigned to bit y7, bit is set b2G is allocated to bit y 11 ' to assign bit b22 to bit y9 ' to assign bit b! to bit y22, bit b3 to bit y 12 ' to assign bit b5 to bit y 13 , assign bit b7 to bit y 〗 4, assign bit b9 to bit y! 5, assign bit b! i to bit y! 6 ' Assign bit b! 3 to bit y ! 7 'Assign bit b!5 to bit y〗 8, assign bit b丨7 to bit y2〇, assign bit b19 to bit y19, and assign bit b21 to bit y23, The bit b23 is assigned to the bit y2!. 22. A data processing apparatus comprising: a replacement mechanism for storing a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a wale direction The m-bit of the code bit of the aforementioned LDPC code, which is written in the preceding direction of the memory mechanism and read in the above-mentioned course direction, is taken as one symbol, and the specific positive integer is set. In the case of b, the memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism. Then, in the above-described course direction, when the code bits of the mb bits read in the direction of the preceding direction of the memory mechanism are used as b symbols, ® is used to use the LDPC code. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S. 2 or the code length N specified by the specification of DVB-T.2 is 64800 bits. An LDPC code having a coding rate of 9/10; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 determined by 4096QAM Any one of the signal points; the memory mechanism includes 24 longitudinal lines of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the longitudinal direction; the replacement mechanism is in the course of the foregoing memory mechanism The 12x2 bit code bit read by the direction is set to the bit bi from the highest bit, and the 12x2 bit of the preceding two symbols is the highest. The i+th bit is set to the bit yi from the bit position, and the following replacement is performed according to the foregoing allocation rule: the bit bG is assigned to the bit y, 135786.doc -44- 200937872 is allocated bit b2 The bit y is assigned, the bit b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, the bit b8 is assigned to the bit y3, and the bit b 1 〇 is assigned to the bit y 4, The bit b! 2 is assigned to the bit y 5 , the bit bi 4 is assigned to the bit y 6, the bit bi 6 is assigned to the bit y 8, and the bit b18 is divided The bit y7 is assigned, the bit b2Q is assigned to the bit y 1!, the bit b22 is assigned to the bit y9, the bit b! is assigned to the bit y22, and the bit b3 is assigned to the bit y! 2, Assigning bit b5 to bit y 13, assigning bit b7 to bit y 14, assigning bit b9 to bit y 15, assigning bit b!! to bit y16, bit b 13 Assigned to bit y 17, assigns bit b15 to bit yi8, bit b! 7 to bit y20, bit b]9 to bit y! 9, assigns bit b2 1 to Bit y23, bit b23 is assigned to bit y21. The data processing apparatus according to any one of claims 1 to 22, wherein the LDPC code is constructed by using a parity matrix corresponding to a portion corresponding to the parity bit of the LDPC code. An LDPC code obtained by checking an LDPC code of a matrix; further comprising a co-located interleave mechanism for performing co-interleaving of interleaving the same bit of the LDPC code to a position of other co-located bits. 24. The data processing device of claim 23, wherein the number of bits of the parity bit of the LDPC code is a value other than a prime number, and the number of bits of the aforesaid bit is less than 1 of the number of bits of the same bit and 2 The two divisors of the number of bits and the number of bits of the aforesaid parity are Ρ and q, and the number of bits of the information bit of the LDPC code is K, 0 or more is less than the integer of P is X, and 0 or less is less than When the integer of q is y, the co-located interleaving mechanism interleaves the K+1th to K+M code bits of the LDPC code, that is, the Κ+qx+y+1 code bits in the same bit to the first K+Py+x+1 code bit positions. The data processing apparatus of any one of claims 1 to 22, further comprising a rearrangement mechanism for rearranging the rearrangement of the code bits of the LDPC code to avoid corresponding to the LDPC code The complex digital bit of any one of the columns of the check matrix is included in the same symbol. The data processing device according to any one of claims 1 to 22, wherein the LDPC code is a part of the inspection matrix of the LDPC code corresponding to the information bit of the LDPC code, that is, the information matrix is a 135786. Doc • 46- 200937872 LDPC sarcophagus, further comprising a rearrangement mechanism for performing a change of the naming of the memory mechanism in the preceding longitudinal direction of the memory device and writing a write position of the code bit of the pre-recorded LDPC code The whirling is twisted and interleaved as a rearrangement process for rearranging the code bits of the aforementioned LDPC code. 27. The data processing apparatus of claim 26, wherein a part of the parity matrix corresponding to the LDPC code in the check matrix of the LDPC code, that is, a parity matrix, is replaced by a row, and a part of the parity matrix ® is excluded. The patrolling structure is similar to the patrolling structure. 28. The data processing apparatus of claim 27, wherein the co-located matrix is a stepped structure and is replaced by a row to form the pseudo-tour structure. 29. The data processing apparatus of claim 28, further comprising a co-located interleaving mechanism for interleaving interleaving the co-located bits of the LDPC code to other co-located bits; the rearrangement mechanism interleaving the co-located bits The aforementioned LDPC code is used as the object to perform the above-described directional twist interleaving. The data processing device of claim 29, wherein the number of bits of the parity bit of the LDPC code is a value other than a prime number, and the number of bits of the aforesaid bit is 11 and a number other than the Μ The two divisors of the two divisors and the number of bits of the aforesaid parity are Ρ and q, and the number of bits of the information bit of the LDPC code is K, 0 or more is less than the integer of P is X, and 135786. Doc -47- 200937872 0 When the integer less than q is y, the co-located interleaving mechanism is the +1+qx+y+ of the K+1th to K+M code bits of the LDPC code, that is, the same bit. The l code bits are interleaved to the position of the Κ+Py+x+l code bits. 3. The data processing device of claim 26, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is an LDPC code of 64,800 bits, and the m-bit is 10-bit, and the integer b is 2, and the 10-bit code bit of the LDPC code is mapped to any one of 1024 signal points determined by a specific modulation mode, and the memory mechanism is stored in the horizontal direction memory. 20 wales of 10x2 bits, in the case of memory 64800/(10x2) bits in the wale direction, the rearrangement mechanism is in the ascending order of the address at the beginning of the longitudinal direction of the memory mechanism is 0 When the integer indicates the address of each position in the wale direction of the memory mechanism, the start position of the first wales in the 20 wales of the memory means is set to the position where the address is 0, and the memory mechanism is The start position of the second wales of the 20 wales is the position where the address is 1, and the start position of the third wales of the 20 wales of the memory mechanism is the position of the address of 3, The beginning of the 4th wales of the 20 wales of the aforementioned memory mechanism is 135786.doc -48· 200937872 is set to the position where the address is 4, and the two vertical lines of the memory mechanism are set to the position where the address is 5, and the beginning of the fifth vertical line writes the 20 vertical positions of the memory mechanism. The row is set to the position where the address is 6, and the beginning of the sixth vertical line writes the 20 vertical lines of the memory mechanism as the address of the address of 6, and the beginning of the seventh vertical line is written. The 20 vertical lines of the memory mechanism are set to the position where the address is 9, and the 20 vertical lines of the memory mechanism are set to the position where the address is 13, and the 9th vertical of the 8th vertical line is written. At the beginning of the line, the starting position of the 10th wales in the 20 townships, ^ Λ Λ 订 前述 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 , , 20 20 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述 前述The starting write position of the 11th wales in the subscription is the position where the address is 14, and ❹ the starting position of the 12th wales of the 20 sectors of the memory mechanism is set to the address of the address of 16 , the 20 townships/sets of the aforementioned memory mechanism are located at the location of 21, The starting bit of the 13th waling in the subscription sets the 20 vertical/sets of the aforementioned memory mechanism as the address of the address 21, and the beginning of the 15th waling in the beginning of the 14th ordinate of the 写. In the beginning of the 16th wales, the 20 addresses of the memory mechanism are set to the address 23, and the 20 _彳$ 135786.doc •49-200937872 of the memory mechanism are set as the address. At the position of 25, the start writing position of the (4)th line of the 20 wales of the memory mechanism is taken as the address of the address 25, and the start writing position of the first line of the 20 wales of the memory mechanism is used as the bit position. The address is 26, and the start position of the first of the 20 wales of the memory mechanism is the address of the address address 28, and the second one of the 20 wales of the memory mechanism is traversed. Start writing the location as the location where the address is 30. 32. The data processing apparatus of claim 26, wherein said LDPC code system, DVB_S.2 or DvB-T.&amp; specification has a code length N of 64,800 bits, and said m-bit is 12 bits. And the integer b is 2, and the 12-bit code bit of the LDPC code is mapped to any one of 4096 signal points determined by a specific modulation mode, and the memory mechanism includes the memory ηχ2 in the horizontal direction. In the case of 24 vertical lines of bits, 64800/(12χ2) bits are stored in the longitudinal direction, the rearrangement mechanism is in the ascending order of the address at the beginning of the longitudinal direction of the memory mechanism. Integer table * When the address of each position in the wale direction of the memory mechanism is the address of the first ideogram of the 24 彳 si of the memory mechanism is the address of the first wales Position, write the beginning of the second wales of the 24 彳 si _ &gt; 仃 前述 of the aforementioned memory mechanism 135786.doc -50- ❹ 200937872 is set to the position where the address is 5, the 24 wales of the memory mechanism are set to the address of 8 and the 24 wales of the memory mechanism are set to the address of 8; The 24 wales of the memory mechanism are placed at a position of 8 and the 24 wales of the memory mechanism are placed at the address of 8 and the 24 wales of the memory mechanism are set as bits. The address is 1 〇, the 24 wales of the memory mechanism are set as the address of 1 〇, and the 24 wales of the memory mechanism are set as the address of the address 10, and the memory mechanism is 24 vertical rows are set as the address of the address 12, the 24 wales of the memory mechanism are set as the address of the address 13, and the 24 wales of the memory mechanism are set as the address of 16 Position, the 24 wales of the memory mechanism are set to the position of the address address 17, and the beginning of the 4th ordinate of the beginning of the 3rd wales of 135786.doc of the 24 wales of the memory mechanism is started. The sixth vertical position of the writing position of the fifth vertical line The beginning of the 7th ordinate of the beginning of the write bit, the beginning of the 8th ordinate of the write bit, the beginning of the ninth ordinate of the write bit, the beginning of the 10th ordinate of the write bit, the beginning of the 11th ordinate of the write bit At the beginning of the 13th waling of the 12th ordinate, the beginning of the 14th ordinate of the write bit is written at the beginning of the 14th ordinate. 200937872 is set to the position of the address 19, which is the second of the 24 wales of the aforementioned memory mechanism. The start position of the service line is the position where the address is 2 1 , and the start write position of the _th line of the 24 wales of the memory mechanism is the position of the address 22, and the 24 wales of the memory mechanism are used. The starting position of the fourth (4) line is the position where the address is 23, and the start writing position of the 18th wales of the 24 wales of the memory mechanism is taken as the address of the address 26, and the memory mechanism is 24 The starting write position of the 19th wales in the wales is the position where the address is 37, and the start writing position of the 2nd wales of the 24 wales of the memory mechanism is the position of the address 39, The starting write position of the 2nd wales of the 24 wales of the aforementioned memory mechanism is used as the address At the position of 40, the start writing position of the 22nd wales of the 24 wales of the memory mechanism is taken as the address of the address 41, and the start of the 23rd wales of the 24 wales of the memory mechanism is written. The position is the position where the address is 41, and the start writing position of the 24th wales of the 24 wales of the memory means is set to the position of the address 41. 33. The data processing device of claim 26, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or Dvb t 2 is an LDPC code of 16,200 bits, 135786.doc • 52· 200937872 The m bit is l〇 bit ' and the aforementioned integer b is 2, and the code bit of the 1 〇 bit of the LDPC code is mapped to any one of 1024 signal points determined by a specific modulation mode, the foregoing The mechanism includes 2 纵 ordinates of 2 bits in the horizontal direction memory, and 16200/(1 扒 2) bits in the longitudinal direction, the rearrangement mechanism is in the longitudinal direction of the memory mechanism The address at the beginning of the direction is an integer in ascending order indicating each of the bits in the wale direction of the memory mechanism, and 20 of the memory means are set to a position where the address is 0, and the start of the first walt in the walt is written. At the beginning of the third vertical line of the second vertical line, the write position of the third vertical line is set to the position where the address is 0, and the 20 vertical lines of the memory mechanism are set as bits. The location is the location of the 〇 The 20 vertical lines of the memory mechanism are set to the position where the address is 2, and the 7th vertical line of the beginning of the 5th vertical line of the beginning of the 4th vertical line is written to the 7th vertical of the beginning of the sixth vertical line. The beginning of the line writes the 20 wales of the memory mechanism as the address of the address 2, and the 20 memory devices are vertically positioned as the address of the address 2, and the 20 wales of the memory mechanism are The middle position is the position where the address is 2, 135786.doc writes the beginning of the 8th vertical line of the 20 wales of the aforementioned memory mechanism. • 53- 200937872 The beginning of the 9th vertical line of the vertical t is written '' The beginning of the 10th wales in the line, the beginning of the 11th wales in the wales, the beginning of the 12th wales in the wales, the beginning of the 13th ordinate in the wales, the beginning of the write wales The beginning of the 14th wales is written at the beginning of the 15th wales in the wales. The beginning of the 16th ordinate in the wales is written at the beginning of the 17th wales in the wales. At the beginning of the 18th wales, the writing position of the 19th waling in the waling is written as the position where the address is 2, and 20 of the aforementioned memory mechanisms are set as The address is 5, and 2 of the memory mechanisms are set to the address of 5, and 2 of the memory mechanisms are set to the address of 5, and 20 of the memory mechanisms are set as The address is 5, and 2 of the memory mechanisms are set to the address of 5, and 2 of the memory mechanisms are set to the address of 7 and 2 of the memory mechanisms are placed. As the location of the address 7, two of the memory mechanisms are set to the address of the address 7, and two of the memory mechanisms are set to the address of the address 7, and two of the memory mechanisms are used. Positioned as the address of 8, the two memory devices are set to the address of 8, and the beginning of the 20th latitude in the 2nd township-mountain of the memory mechanism is written to 135786. .doc -54 . 200937872 Set as the location of the address ίο. 34. The data processing apparatus of claim 26, wherein the code length N specified by the specification of the LDPC code system DVB-S.2 or DVB-T.2 is an LDPC code of 16,200 bits, and the m-bit is 12 a bit, and the aforementioned integer b is 2, and the 12-bit code bit of the LDPC code is mapped to any one of 4096 signal points determined by a specific modulation mode. The memory mechanism includes 24 wales that memorize 12x2 bits in the horizontal direction and 162 〇〇/(12x2) bits in the wale direction. The rearrangement mechanism is in the longitudinal direction of the memory mechanism. When the address of the beginning position is 〇', the address of each position of the longitudinal direction of the memory mechanism is represented by an integer in ascending order, and the write position sets 24 of the memory mechanisms as the address of the address, in the wales. The beginning of the first vertical The 24 vertical lines of the memory mechanism are set to the position where the address is 〇, and the fifth vertical line of the beginning of the second vertical line of the second vertical line is written at the beginning of the fourth vertical line. The beginning of the sixth vertical line of the write bit sets the 24 wales of the memory mechanism as the address of the address, and sets the 24 wales of the memory mechanism as the address. Position, the 24 memory devices are set as the address of the address, the 135786.doc *55, 200937872 of the memory mechanism is set as the address of the address, the 24 wales of the memory mechanism The start position of the seventh wales is the position where the address is 0, and the start write bit sets the eighth wales of the 24 wales of the memory mechanism as the address of the address, and the memory mechanism is The starting position of the ninth latitude in the 24 vertical 杵6 ^ Λ 仃 is the position where the address is 1, and 第 the first one of the 24 wales of the memory mechanism is set as the address. For the position of 1, the 24 wales of the aforementioned memory mechanism are set as the address At the position of 2, the start of the 11th waling of the beginning of the write position is the start position of the 12th wales of the 24 verticals of the memory mechanism as the address of the address of 2, 』 . The horse position sets the 24 longitudinal lines of the aforementioned memory mechanism as the position where the address is 2, and the beginning of the 13th vertical line in the position of the horse is to open the 14th vertical line of the 24 townships to the memory mechanism. As the location where the address is 3, the network sets the 24 vertical values of the memory mechanism as the address of the address 7, and the beginning of the write bit of the 15th vertical write start bit of the + writes the memory device 24 The vertical material is set to the position where the address is 9, and the 16th vertical line of the memory unit has 24 vertical positions of the memory mechanism as the address of the address 9. The beginning of the 17th vertical line of the bamboo will write the memory mechanism. The beginning of the 18th wales of the 24 wales is 135786.doc •56· 200937872 is set as the address of the address of 9, the beginning of the twentieth of the 19th traverse In the beginning of the 21st wales in the beginning of the 21st wales, the beginning of the 23rd wales in the beginning of the write position, the 24 wales of the memory mechanism are set to the address of 1 ,, The 24 vertical lines of the aforementioned memory mechanism are set to be 1 〇, and will be just described. 24 wales mounting mechanism as the address for the location of 10, The 24 longitudinal lines of the memory mechanism are set to the position where the address is 10, and the 24 longitudinal lines of the memory mechanism are set to the position of 1 〇, and the 24th of the 24 wales of the memory mechanism is the 24th. The start position of the wales is the position where the address is 1 1 . 35. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (L〇w Density Parity Check) code having a length of N bits in a log direction and a wale direction The memorandum of the code bit of the LDPC code read by the person in the preceding direction of the memory mechanism is used as the Hg] symbol and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code of the ^^ bit read in the foregoing direction of the memory mechanism is 135786.doc • 57· 200937872 bit is used as the b symbol, in order to use the LDPC The code bit of the code is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB- The code length N specified by the specifications of S.2 or DVB-T.2 is 16,200 bits. An LDPC code having a coding rate of 2/3; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped to 1024 of 1024QAM as one of the preceding symbols. Any one of the signal points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction, and 16200/(10x2) bits in the waling direction; the replacement step is in the horizontal direction of the foregoing memory mechanism The code bit of the 10x2 bit read from the column direction is set to the bit bi from the highest bit, and the symbol bits of the 10x2 bits of the preceding two symbols are The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y, the bit is The element b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, the bit b8 is assigned to the bit y3, the bit b! 〇 is assigned to the bit y 4 , and the bit b! 2 is assigned to Bit y 6, assigning bit b! 4 to bit y 5, 135786.doc -58- 200937872 assigning bit bI6 to bit y9, assigning bit b18 to bit Y7, the bit b! is assigned to the bit yl8, the bit b3 is assigned to the bit y! 〇, the bit b5 is assigned to the bit y 1 '', and the bit b7 is assigned to the bit y12, the bit is allocated B9 is assigned to bit y丨3, bit bn is assigned to bit y14, ® bit b13 is assigned to bit y16, bit b! 5 is assigned to bit y丨5, bit b17 is assigned to Bit y19 assigns bit b 9 to bit y丨7. 36. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are taken as b of the aforementioned symbols, 135786.doc -59- 200937872 is used to code the aforementioned LDPC code The bit element is allocated to an allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 Or the code length N specified by the specification of DVB-T.2 is 64800 bits 7〇, edited The code rate is 2/3 LDPC code; the m bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signals determined by 1024QAM. Any one of the points; 〇 the memory mechanism contains 20 wales of 10X2 bits in the horizontal direction, and 64800/(10x2) bits in the wales; the replacement step is in the horizontal direction of the aforementioned memory mechanism The code bit of the 10x2 bit read from the column direction is set to the bit bi from the highest bit, and the symbol bits of the 10x2 bits of the preceding two symbols are The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y, the bit is The element b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, the bit b8 is assigned to the bit y3, the bit b is assigned to the bit y 4 , and the bit b! 2 is assigned to Bit y 6, assigning bit b! 4 to bit y 5, assigning bit b! 6 to bit y 9, 135786.doc -60- 200937872 assigning bit b 18 to bit y 7 'Assign bit b! to bit y 18 ' Assign bit b3 to bit y 10, bit b5 to bit yn ' Assign bit b7 to bit y 12 ' Place bit B9 is assigned to bit y]3, bit b! i is assigned to bit y! 4, bit b 13 is assigned to bit y 16 ' 〇37. ❹ Bit b15 is assigned to bit y15, Bit b17 is assigned to bit y19, and bit b丨9 is assigned to bit y 17. A data processing method includes a replacement step of a memory mechanism of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The code bit bit of the LDPC code written in the preceding row direction and read in the direction of the horizontal direction is taken as a symbol and the specific positive integer is set to b, and the preceding waltz in the preceding direction The memory means stores the N/(mb) bit in the wale direction in the horizontal direction, and the code bit of the LDPC code is written in the memory means, and then read in the course direction. In the case where the bit in the preceding row direction of the memory mechanism is taken as b symbols, the code of the mb bit of S is given to indicate that the symbol is used to divide the code bit of the LDPC code into 135786. Doc 61 200937872 The allocation rule of the symbolic element of the element, replacing the code bit of the aforementioned mb bit, and replacing the replaced code bit as the above-mentioned symbol bit; The aforementioned LDPC code is DVB-S.2 or DVB-T The code length N specified in the specification of .2 is 16,200 bits, code The LDPC code is 3/4; the m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by 1024QAM. Any one of the above; the memory mechanism includes 20 vertical lines of 10x2 bits in the horizontal direction, and 16200/(10x2) bits in the longitudinal direction; in the foregoing replacement step, the direction of the memory mechanism is The coded bit of the read 10x2 bit is set to the bit bi from the highest bit, and the symbol bit of the 10x2 bit of the consecutive two preceding symbols is from the highest bit. The i+th bit is set to the bit yi from the bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y6, the bit b2 is assigned to the bit y4, and the bit b4 is allocated. The bit y8 is assigned, the bit b6 is assigned to the bit y5, the bit b8 is assigned to the bit y, the bit b 丨〇 is assigned to the bit y 2 , and the bit bi 2 is assigned to the bit y 1 , assigning bit b! 4 to bit y 3, assigning bit b 丨 6 to bit y 9, assigning bit b 丨 8 to bit y 7, 135786.doc -62- 20093 7872 assigns the bit ratio to bit y16, bit #3 &gt;3 to bit y 1 4 ' assigns bit b 5 to bit y 18 ' assigns bit b7 to bit y 15, bit B9 is assigned to bit y10, bit b 11 is assigned to bit y! 2 'Band b! 3 is assigned to bit y丨! The bit b15 is assigned to the bit y13, the bit b丨7 is assigned to the bit y 19, and the bit b!9 is assigned to the bit yi7. 38. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code, which is written in the preceding direction of the memory mechanism, is read as one symbol, and the specific positive integer is set to b, 前述 the aforementioned memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, in the case where the code bit of the bit read in the foregoing direction of the memory mechanism is used as the b symbols, the symbol is used to assign the LDPC code to the representation. The allocation rule of the symbolic symbol of the foregoing symbol replaces the code bit of the aforementioned mb bit, 135786.doc -63· 200937872 replaces the replaced code bit as the aforementioned symbol bit; the aforementioned LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 64,800 bits. An LDPC code having a coding rate of 3/4; the m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped to 1024 signals determined by 1024QAM as one of the preceding symbols. Any one of the points; the memory mechanism includes 20 wales of 10x2 bits in the horizontal direction and 64800/(10x2) bits in the waling direction; The code bit of the 10x2 bit read from the column direction is set to the bit bi from the highest bit, and the symbol bits of the 10x2 bits of the preceding two symbols are The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y6, the bit b2 is assigned to the bit y4, and the bit is allocated B4 is assigned to bit y8, 位 bit b6 is assigned to bit y 5, bit b8 is assigned to bit y 〇, bit b 1 〇 is assigned to bit y 2 , bit b! 2 is assigned The bit y 1, the bit b! 4 is assigned to the bit y3, the bit bi 6 is assigned to the bit y 9, and the bit b 丨 8 is assigned to the bit y 7, the bit is bit B 1 is assigned to bit y! 6, 135786.doc -64- 200937872 assigns bit b3 to bit y14, bit b5 to bit y 18, and bit b7 to bit y]5, The bit b9 is assigned to the bit y10, the bit b! t is assigned to the bit y12, the bit b3 is assigned to the bit yn, the bit b is assigned to the bit yl3, and the bit b is assigned 17 is assigned to bit y 〗 9, and bit b19 is assigned to bit y17. 39. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the preceding direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bit of the ^^ bit read in the foregoing direction of the memory mechanism is used as b symbols, according to the code bit for assigning the LDPC code to the representation The allocation rule of the above-mentioned symbolic bit element replaces the above-mentioned (10)-bit code bit element, and replaces the coded bit element as the aforementioned symbol bit element; 135786.doc -65- 200937872 The foregoing LDPC code system is DVB-S The code length N specified by .2 or DVB-T.2 is 16200 bits, The code rate is 4/52 LDpc code; the m bit is 1 bit, and the integer 匕 is the same; the 10 bits of the code bit are mapped to 1024QAM as the first symbol. Any one of the signal points; the memory means includes 2 纵 纵 丨〇 丨〇 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The code bit of the 10x2 bit read by the direction of the memory mechanism is set from the highest bit to the i+1 bit and is set to the bit ratio 'and will be the symbol of the iou bit of the previous two symbols. The i-bit is calculated from the highest-order bit, and the i+1th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit y6, and the bit b2 is assigned to the bit. Y4, the bit b4 is allocated to the bit y8, the bit b6 is assigned to the bit y5, the bit b8 is assigned to the bit y, the bit bi is assigned to the bit y2, and the bit b 12 is assigned Assigning bit y 1 ' to bit b 14 to bit y 3 ' assigning bit bi6 to bit y9 ' assigning bit b 1 8 to bit P ' will bit bi Assigned to bit yi6 ' Assign bit b3 to bit yi4 ' 135786.doc -66 - 200937872 Assign bit b5 to bit y18, bit b7 to bit y15, bit b9 to bit Yuan y, assigning bit b 11 to bit y 〗 2, assigning bit bi3 to bit yu, assigning bit b15 to bit y13, and assigning bit b17 to bit y19, bit Element b19 is assigned to bit y17. © 40. A data processing method comprising a replacement step of LDpc (L〇w Density Parity Check) code having a length of N bits in the horizontal direction and the longitudinal direction. The caller of the LDPC code read by the person in the preceding direction of the memory device of the bit is used as the symbol and the specific positive integer is b, the memory mechanism The mb bits are memorized in the preceding row direction, and the N/(mb) bits are memorized in the preceding direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then Reading in the horizontal direction, when the code bit of the _ element read in the row direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is allocated to Representing the allocation rule of the symbol bit of the preceding symbol, replacing the code bit of the (four) bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is defined by the specification of DVB_S uDVB T 2 Code 135786.doc •67· 200937872 Long N is 64800 bits, edited The code rate is 4/5 LDPC code; the m bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are used as one of the 1024 signal points determined by one of the aforementioned symbols 1024QAM. One; the meta-map is such that the memory mechanism contains the memory in the horizontal direction i〇&gt;&lt;2 bit rows, and the memory is 64800/(10x2) bits in the wale direction; the 20 verticals in the meta-parameter will be The code bit of the 10x2 bit read out in the course direction of the memory mechanism is set to the bit bi from the highest bit, and 1 〇 x2 of 2 consecutive symbols. The bit element of the bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: The bit bG is allocated to the bit y6, the bit is assigned to the bit y4, the bit b4 is assigned to the bit y8, the bit b6 is assigned to the bit y5, and the bit b8 is assigned to the bit y〇. Assigning bit b1G to bit y2' assigns bit b丨2 to bit y 1 ' assigns bit b14 to bit y3, bit b! 6 to bit y 9, bit b18 Assigned to bit y7, assign bit b! to bit yi6' assign bit b3 to bit yi4, assign bit b5 to bit yis ' 135786.doc -68 · 200937872 assign bit b7 to Bit y 15, assigning bit b9 to bit y 1 〇, assigning bit b! 1 to bit y丨2, assigning bit b! 3 to bit y丨丨, bit b! 5 is assigned to bit y! 3, bit b! 7 is assigned to bit y 丨 9, and bit b 丨 9 is assigned to bit y 17. 41. A data processing method, comprising: a replacement step of storing a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, and the memory mechanism is The horizontal direction stores mb bits, and the N/(mb) bits are stored in the wale direction, and the code bits of the LDPC code are written in the W direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The LDPC code with a code length N of 16200 bits and a coding rate of 5/6 as specified in the specification 135786.doc -69- 200937872 The m-bit is 10 bits, and the aforementioned integer b is 2; 1 〇 bit of the above-mentioned code bit is determined by 1024QAM as true UF von 1 刖 兀 兀Any one of 1024 signal points; the foregoing memory mechanism includes 2 纵 纵 记忆 memory of 1 〇χ 2 bits in the horizontal direction 记忆 memory 16200 / (ι 0 χ 2) bits in the longitudinal direction; The code bit of the 10x2 bit read from the row direction of the memory mechanism is set to the bit bi from the highest bit, and the 1st and 2nd bits of the 2 consecutive symbols are consecutively The meta-symbol of the element is calculated from the most local bit, and the i+l bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y 6, and the bit b is Assigned to the bit, assign bit b4 to bit y8, bit b6 to bit, assign bit bs to bit y, assign bit b! 〇 to bit y 2, Bit b 丨 2 is assigned to bit y 1, bit b! 4 is assigned to bit y 3, bit b! 6 is assigned to bit y 9, bit b18 is assigned to bit y7, The bit b! is assigned to the bit y 16 'the bit b3 is assigned to the bit yi4 ' The bit b5 is assigned to the bit y 18 ' The bit b7 is assigned to the bit y 15 ' 135786.doc -70- 200937872 Assign bit b9 to bit y! 〇, assign bit b!! to bit y丨2, and assign bit b! 3 to bit y丨! The bit b丨5 is assigned to the bit y!3, the bit b丨7 is assigned to the bit y丨9, and the bit b!9 is assigned to the bit y丨7. 42. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low 〇 Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are regarded as b symbols, according to the code bits for assigning the LDPC code to the representation The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T. LDPC code with a code length N of 64,800 bits and a coding rate of 5/6 as specified in the specification of 2 The m-bit is 10 bits, and the integer b is 2; 135786.doc -71 - 200937872 The 10 bits of the aforementioned code bit are mapped as one of the aforementioned symbols to 1 24 signals determined by 1024QAM. Any one of the points; the memory mechanism includes 2 纵 纵 丨〇χ 丨〇χ , , , , , , 记忆 64 64 64 64 64 64 64 64 64 64 64 64 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆The code bit of the 10x2 bit read out in the direction of the row is set to the bit bj ' from the highest bit, and the symbol of ι 2 bits of the preceding two symbols is consecutively The i-th bit from the highest bit is set to the bit yi from the highest bit, and the following substitution is performed according to the foregoing splitting rule: the bit be is allocated to the bit y6, and the bit b is assigned to Bit y4, bit b4 is assigned to bit y8, bit b6 is assigned to bit y5, bit b8 is assigned to bit y, bit b! 〇 is assigned to bit y 2, bit is bit The element b! 2 is assigned to the bit y!, the bit b! 4 is assigned to the bit y 3, the bit b! 6 is assigned to the bit y 9, and the bit b 1 8 is assigned to the bit y 7.Bit bi is assigned to bit yi6, bit b3 is assigned to bit y μ, bit b5 is assigned to bit y 18, bit b7 is assigned to bit yi5, bit b9 is assigned to bit y 1 〇, I35786.doc • 72· 200937872 assigns bit b 11 to bit y! 2, assigns bit b 13 to bit y! j, assigns bit b! 5 to bit y! 3, The bit bi 7 is assigned to the bit y 丨 9 and the bit b 19 is assigned to the bit y 17 . 43. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the preceding direction written in the preceding direction is regarded as one symbol, and the specific positive integer is set to b, the foregoing memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, in the case where the code W bit of the mb bit read in the foregoing direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is assigned to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T The LDPC code with a code length N of 16200 bits and a coding rate of 8/9 as specified in the specification of .2 The m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the aforementioned symbols to 1024 signal points determined by 135786.doc-73-200937872 1024QAM. Any one of the above-mentioned memory mechanisms includes 2 纵 wales of 1 〇χ 2 bits in the horizontal direction, and 16200/(10×2) bits in the longitudinal direction; the above replacement step is to be transverse to the aforementioned memory mechanism The code bit of the 10x2 bit read out in the column direction is set to the bit h from the highest bit, and the symbol bits of 1 and 2 bits of the preceding two symbols are consecutively The element is set to the bit edge from the highest bit, and the following replacement is performed according to the foregoing allocation rule: The bit be be is assigned to the bit y8, the bit b2 is assigned to the bit y 〇, the bit b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, and the bit b8 is assigned to the bit Y3, assigning bit b 1 〇 to bit y 4 , assigning bit bi 2 to bit y6 , assigning bit b 14 to bit y 5 , and assigning bit bi 6 to bit y 9 The bit bi 8 is assigned to the bit y 7, the bit b is assigned to the bit y 18 '. The bit b3 is assigned to the bit y 1 〇, and the bit bs is assigned to the bit y 1 r ' B7 is assigned to bit y 1 2 ' Assign bit bp to bit y 13 ' Assign bit b! ! to bit yi4 ' 135786.doc -74- 200937872 Assign bit b! 3 to bit y 6, the bit b 15 is assigned to the bit y! 5, the bit b 17 is assigned to the bit y 丨 9 , and the bit b 19 is assigned to the bit y 17 . 44. A data processing method, comprising: a replacement step of remembering a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding direction of the mechanism and read in the row direction is regarded as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as b symbols, 分配 are used to assign the code bits of the LDPC code to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 LDPC with a code length N of 64,800 bits and a coding rate of 8/9 The m-bit is 10 bits, and the integer b is 2; the 10 bits of the code bit are mapped as one of the symbols to one of the 1,024 signal points determined by the 1 024QAM; 135786.doc -75- 200937872 The memory mechanism contains 2 纵 纵 记忆 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The code bit of the 10x2 bit read in the direction of the memory mechanism is set to the bit h from the highest bit, and the ι 2 bit of the preceding symbol is consecutively 2 bits. Symbol: The i+1th bit is set to the bit yi from the most significant bit, and the following replacement is performed according to the foregoing allocation rule: _ assign the bit b〇 to the bit y8, 分配 Assign bit b2 to bit y, assign bit b4 to bit yi, assign bit be to bit y2, assign bit b8 to bit y3, and assign bit b! Bit y 4, bit b12 is assigned to bit y6, bit b! 4 is assigned to bit y 5, bit b! 6 is assigned to bit y9, bit b! 8 is assigned to bit y 7, assign bit b! to bit y 18 ' to assign bit b3 to bit y 1 〇, bit b5 to bit y 11 ' assign bit b7 to bit y 12 ' Bit b9 is assigned to bit y 13 ' Assign bit b! 1 to bit y 14 ' Assign bit b! 3 to bit 丫 16 ' 135786.doc -76- 200937872 Assign bit b! 5 The bit y 15, the bit b ! 7 is assigned to the bit y ! 9, and the bit bi 9 is assigned to the bit y 17. 45. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the megabit of the LDPC code read in the direction of the row in the memory direction is defined as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The LDPC code with a code length N of 64800 bits and a coding rate of 9/10 specified by the specification; The m-bit is 10 bits, and the integer b is 2; 10 bits of the code bit are mapped as one of the symbols to 1 024 signal points determined by 1 024 QAM; The mechanism contains 20 vertical 135786.doc -77·200937872 lines of 10x2 bits in the horizontal direction, and 64800/(10x2) bits in the longitudinal direction; the above replacement steps are in the direction of the aforementioned memory mechanism The coded bit of the read 10x2 bit is set to the bit bi from the highest bit, and the symbol of the ι〇χ2 bit of the two consecutive symbols is from The i+1th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit y 8, and the bit b2 is assigned to the bit y〇, © Assign bit b4 to bit y 1, assign bit b6 to bit y2, assign bit b8 to bit y 3, assign bit b! 〇 to bit y 4, place bit b12 Assigned to bit y6, bit b14 is assigned to bit y5, bit b丨6 is assigned to bit y 9 'bit p! 8 is assigned to bit y 7 ' bit b! Assigned to bit yis ' Assign bit b3 to bit y 1 〇 ' Assign bit b5 to bit yu ' Assign bit b7 to bit y 2 ' Assign bit b9 to bit y 13 'Assign bit bn to bit yi4 ' Assign bit b ! 3 to bit y 1 6 ' Assign bit b15 to bit yi5 ' 135786.doc -78- 200937872 Place bit b! 7 Assigned to bit y 19, bit b! 9 is assigned to bit y 17. 46. A data processing method, comprising: a replacement step of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the LDPC-major code bit read in the preceding direction of the memory mechanism is read as one symbol, and the specific positive integer is b, and the memory mechanism is The row direction stores mb bits, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the wale direction of the memory mechanism, and then in the direction of the row Reading, in the case where the code bit of the mb bit read in the foregoing direction of the memory mechanism is used as the b symbols, the code bit for using the LDPC code is assigned to the symbol The allocation rule of the symbol of the meta-sub-bit, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is 16200 bits, and the coding rate is 2/3 LDPC code; The m bit is 12 bits, and the integer b is 2; the 12 bits of the code bit are mapped as one of the aforementioned symbols to any one of 4096 signal points determined by 4096QAM; 24 rows of 12x2 bits are stored in the direction of the column, and 16200/(12x2) bits are memorized in the wale direction; 135786.doc -79- 200937872 The above replacement steps are read in the direction of the aforementioned memory mechanism The 12x2 bit of the mbit is calculated from the highest bit, and the i+i bit is set to bit bi, and the symbol of the Hu bit of the two consecutive symbols is from the highest bit. Counting the i+th bit as the bit yi, the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y10, the bit b2 is assigned to the bit y〇, and the bit b4 is assigned to Bit yi, ® assigns bit b6 to bit y2, bit b8 to bit y3, bit bh 〇 to bit y4, bit b12 to bit y5, bit b14 Assigned to bit y6 'Assign bit h 6 to bit y8, bit b!8 to bit y7, ▲ assign bit b2〇 to bit Element yii' 分配 assigns bit b22 to bit y9, bit bi to bit y22, bit b3 to bit y 12, bit b5 to bit yu, bit b7 The bit yH ' is assigned to the bit yi 5, the bit b!! is assigned to the bit y 16, the bit b13 is assigned to the bit yi7, 135786.doc -80- 200937872 bit b 5 is assigned to bit y丨8, bit b! 7 is assigned to bit y20, bit b! 9 is assigned to bit y 19, bit b21 is assigned to bit y23, bit b23 is assigned Give bit y21. 47. A data processing method, comprising: a replacement step of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding row direction written in the preceding direction of the memory device is regarded as one symbol, and the specific positive integer is set to b, the foregoing memory The mechanism memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for the LDPC code are assigned to An allocation rule indicating a symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T LDPC with a code length N of 64800 bits and a coding rate of 2/3 as specified in the specification of .2 The m-bit is 12 bits, and the aforementioned integer b is 2; the 12-bit of the above-mentioned code bit is mapped as one of the aforementioned symbols to 4096 signal points determined by 135786.doc -81 - 200937872 4096QAM Any one of the above; the memory means includes a longitudinal direction of memory Ι2χ2 bits in the horizontal direction of the memory bit in the wale direction; the replacement step is 12x2 bits read in the course direction of the memory mechanism The symbol bit of the element is set from the highest bit to the third bit and the bit is set to bit bi, and the symbol of 12 consecutive 2 bits of two consecutive symbols: the element is counted from the highest bit. The bit is set to bit yi, and the following replacement is performed according to the previous: allocation rule: 77 The bit b〇 is assigned to the bit y丨〇, the bit b is assigned to the bit y0, the bit b4 is assigned to the bit yj, the bit b6 is assigned to the bit y2, and the bit b8 is assigned to Bit y3, assigns bit b 1 〇 to bit y 4 , assigns bit b ! 2 to bit y 5 , assigns bit b 丨 4 to bit y 6, assigns bit b16 to bit Element y8, assigning bit b!8 to bit y7, assigning bit b2G to bit y11', assigning bit b22 to bit y9', assigning bit b1 to bit y22' B3 is assigned to bit y 12 ' assigns bit b 5 to bit y 1 3 ' assigns bit b7 to bit yi4 ' 135786.doc -82- 200937872 assigns pull b9 to bit y 15, will Bit b! is assigned to bit y丨6, bit b丨3 is assigned to bit y丨7, bit b! 5 is assigned to bit y! 8, bit b! 7 is assigned to bit Element y2 〇, bit b 19 is assigned to bit y 19, bit b2! is assigned to bit y23, and bit b23 is assigned to bit y2 1. 〇 48. A data processing method, comprising a replacement step, which is a gradation of a LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, the memory mechanism Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The code specified by the specification is 135786.doc • 83 200937872 The length N is 16,200 bits. The coding rate is 3/42 ldPC code; the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to 4096 signal points determined by 4096QAM. The memory mechanism includes 24 wales that memorize 12 χ 2 bits in the row direction and 16200/(12×2) bits in the waling direction; the replacement step is in the direction of the memory mechanism The code bit of the read 12x2 bit is set to the bit bi from the highest bit, and the symbol bits of the 2x2 bits of the preceding two symbols are from the highest bit. The i+th bit from the bit count is set to the bit yj, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, the bit b2 is assigned to the bit y〇, and the bit b4 is used. Assigned to bit y6, bit b6 is assigned to bit y 1, bit bg is assigned to bit y4, bit b 1 q is assigned to bit y 5 , bit b 12 is assigned to bit y 2, the bit b 14 is assigned to the bit y 3 , the bit b 16 is assigned to the bit y 7, the bit b 18 is assigned to the bit y 1 〇, and the bit b2G is divided The bit y 11, the bit b22 is assigned to the bit y9, the bit b 1 is assigned to the bit y2 〇 ' 135786.doc -84 - 200937872 The bit b3 is assigned to the bit y 1 2 ' B5 is assigned to bit y 18 ', bit b7 is assigned to bit y 13, bit b9 is assigned to bit y 16, bit b! 丨 is assigned to bit y! 7, bit b 13 is assigned Give bit y! 4, assign bit b丨5 to bit y丨5, assign bit b 17 to bit y 19, assign bit b 1 9 to bit y22, place bit b2 i is assigned to bit y23, and bit b23 is assigned to bit y2 !. 49. A data processing method, comprising: a replacement step of memory of a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDpC code read in the row direction and written in the row direction of the mechanism is used as one symbol, and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes mb bits, and the N/(mb) bits are memorized in the longitudinal direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism and then read in the preceding direction. And, in the case where the code bits of the mb bits read in the foregoing row direction of the foregoing suffix mechanism are used as the b symbols, the code bits of the LDPC code are allocated to The allocation rule of the symbol 135786.doc -85 - 200937872 is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB- The code length N specified by the specifications of S.2 or DVB-T.2 is 64800 bits. An LDPC code having a coding rate of 3/4; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped as one of the aforementioned symbols to 4096 signals determined by 4096QAM. Any one of the points; the memory mechanism includes 24 vertical lines that memorize 12x2 bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction; the replacement step is in the horizontal direction of the foregoing memory mechanism The code bit of the 12x2 bit read out in the column direction is set to the bit bi from the highest bit, and the symbol bits of the 12x2 bits of the preceding two symbols are The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y, the bit is The element b4 is assigned to the bit y6, the bit b6 is assigned to the bit y 1, the bit b8 is assigned to the bit y4, the bit b! 〇 is assigned to the bit y 5 , and the bit bi 2 is assigned to the bit Element y 2, assigning bit b! 4 to bit y 3, assigning bit b! 6 to bit y 7, assigning bit b! 8 to bit y 1 〇, 135786.doc -86- 200937872 Assigning bit b2G to bit yii 'Assign bit b22 to bit y9 ' Assign bit b! to bit y2〇' Assign bit b3 to bit y 12 ' B5 is assigned to bit y 18 'bit bit 7 is assigned to bit y 13 ' bit b9 is assigned to bit y 16 ' bit b 11 is assigned to bit y 17 ' bit p13 is assigned to bit Yi4, assigning bit b15 to bit yis, bit b!7 to bit y!9, bit b! 9 to bit y22, bit b21 to bit y23, bit Element b23 is assigned to bit y21. 50. A data processing method, comprising: a replacement step of storing a code position of an LDpc (L〇w Density Parity Check) code of N bits in a row direction and a longitudinal direction The m-bit of the code bit of the LDPC code read in the direction of the preceding direction of the memory device of the element is taken as a symbol and the specific positive integer is b, and the memory mechanism is as described above. The row direction memorizes the mb bit, and memorizes the N/(mb) bit in the longitudinal direction, ^ the code bit of the LDPC code is written in the foregoing longitudinal direction of the memory mechanism, and then read in the foregoing direction , 135786.doc -87· 200937872 In the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are taken as the b symbols, the code bits for using the LDPC code are used. Allocating an allocation rule to the symbol bit indicating the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB The code length N specified by the specification of -T.2 is 16,200 bits, and the coding rate is 4/5 LDPC code; the aforementioned m bit is 12 bits, and the aforementioned integer b is 2; 12 12 bits of the foregoing code bit are mapped as one of the aforementioned symbols to 4096 signal points determined by 4096QAM The memory mechanism includes 24 wales that memorize 12x2 bits in the row direction and 16200/(12x2) bits in the wales direction; the replacement step is in the direction of the memory mechanism The read 12x2 bit code bit is set to the bit bi from the highest bit, and the 12x2 bit of the preceding two symbols is from the highest bit. From the first calculation, the i+th bit is set to the bit yi, and the following replacement is performed according to the foregoing rule: the bit bG is allocated to the bit y8, and the bit b2 is assigned to the bit y, the bit is B4 is assigned to bit y6, bit b6 is assigned to bit y!, bit b8 is assigned to bit y4, bit b! 〇 is assigned to bit y 5, bit bi 2 is assigned to bit y 2, 135786.doc -88 - 200937872 assigning bit b14 to bit y3, bit b 16 to bit y 7 ' assigning bit b 丨 8 to bit y 1 'Assign bit b2G to bit y 11 ' Assign bit b22 to bit y9 ' Assign bit b! to bit y2 〇, bit b3 to bit y 12, assign bit b5 Bit y!8, ❹ 分配 Assign bit b7 to bit yi3 ' Assign bit b 9 to bit y 16, assign bit b η to bit y! 7, place bit b! 3 Assigned to bit y! 4, bit b15 is assigned to bit y15, bit b 17 is assigned to bit y丨9, bit b 1 9 is assigned to bit y22, bit b21 is assigned to bit Element y23, bit b23 is assigned to bit y2i. 51. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The bit element of the code bit of the LDPC code read in the row direction of the memory mechanism is used as one symbol, and the specific positive integer is b, and the memory mechanism is The preceding row direction stores mb bits, and the preceding 135786.doc •89-200937872 describes the longitudinal direction memory N/(mb) bits, and the code bits of the LDPC code are written in the foregoing longitudinal direction of the memory mechanism. And then reading in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit element is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol element; 〇 the aforementioned LDPC code system DVB-S The code length N specified by .2 or DVB-T.2 is 64800 The LDPC code having a coding rate of 4/5; the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the aforementioned symbols to 4096 determined by 4096QAM. Any one of the signal points; the memory mechanism includes 24 wales of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the waling direction; The 12x2 bit code bit read from the horizontal direction is set to the bit bi from the highest bit, and the 12x2 bit of the preceding symbol is consecutively The i+th bit is set to the bit yi from the highest bit, and the following replacement is performed according to the foregoing allocation rule: the bit bQ is assigned to the bit y8, and the bit b2 is assigned to the bit y〇. Assign bit b4 to bit y6 and bit b6 to bit y!, 135786.doc -90- 200937872 Bit bit b8 is assigned to bit y4, bit b1Q is assigned to bit ys, bit b! 2 is assigned to bit y 2, bit b!4 is assigned to bit y3, bit b16 is assigned The bit y7' is assigned to the bit y 1 〇, the bit b2 〇 is assigned to the bit yi 1 ', the bit b22 is assigned to the bit y9, and the bit b! is assigned to the bit Y2〇, assigning bit b3 to bit y 12, assigning bit b5 to bit y! 8, assigning bit b7 to bit y13, and assigning bit b9 to bit y丨6, bit The element b!! is assigned to the bit y17, the bit b! 3 is assigned to the bit y丨4, the bit b! 5 is assigned to the bit y 15, and the bit b丨7 is assigned to the bit y丨9 The bit bi9 is assigned to the bit y22, the bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y2 1. 52. A data processing method, comprising a replacement step of storing a code position of an LDpc (L〇w Density Parity Check) code of a N-bit length in a row direction and a longitudinal direction The m-bit of the LDPC code of the above-mentioned LMC code, which is written in the preceding direction of the 椹 兮 兮 、 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , And the specific positive integer is set to b, the memory mechanism stores mb bits in the horizontal direction, and stores N/(mb) bits in the longitudinal direction, and the code bits of the LDPC code are in the foregoing vertical direction of the memory mechanism. Writing in the row direction, and then reading in the horizontal direction, in the case where the code bits of the mb bits read in the direction of the memory of the memory mechanism are used as b symbols, ❹ Allocating a code bit of the foregoing LDPC code to an allocation rule indicating a symbol bit of the foregoing symbol, replacing a code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the LDPC code Is the code length N specified by the specifications of DVB-S.2 or DVB-T.2 16200 bits, LDPC code with a coding rate of 5/6; the m-bit is 12 bits, and the integer b is 2; 12 bits of the code bit are mapped to 4096QAM as one of the aforementioned symbols. Any one of 4096 signal points; the memory mechanism includes 24 wales of 12x2 bits in the horizontal direction and 16200/(12x2) bits in the waling direction; The 12x2 bit code bit read by the direction of the mechanism is set to the bit bi from the highest bit, and the symbol of 12x2 bits of the preceding two symbols is consecutively The bit is calculated from the highest bit, and the i+th bit is set to bit yi. The following replacement is performed according to the foregoing allocation rule: bit bG is allocated to bit y8, 135786.doc -92- 200937872 B2 is assigned to bit y, bit b4 is assigned to bit y6, bit b6 is assigned to bit y 1, bit b8 is assigned to bit y4, bit b 1 〇 is assigned to bit y 5. Assign bit b! 2 to bit y 2, bit bi 4 to bit y 3, and bit b! 6 to bit y 7. The bit bi 8 is assigned to the bit y 1 〇, the bit b2G is assigned to the bit y 11, the bit b22 is assigned to the bit y9, the bit bi is assigned to the bit y2, and the bit b3 is assigned The bit y 12 is assigned, the bit b5 is assigned to the bit y!8, the bit b7 is assigned to the bit y 13, the bit b9 is assigned to the bit y 16, and the bit b 11 is assigned to the bit y 17, assigning bit bi 3 to bit y 14, assigning bit b 15 to bit y 15, assigning bit b 17 to bit y 19, and assigning bit b! 9 to bit y22, The bit b21 is assigned to the bit y23, and the bit b23 is assigned to the bit y2 1. 5 3. A data processing method, comprising a replacement step, which is 135 786.doc • 93- 200937872 LDPC (Low Density Parity Check) with a length of N bits in the horizontal direction and the longitudinal direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory cell of the code bit is written as one symbol, and a specific positive integer Let b, the memory means memorize mb bits in the horizontal direction, and store N/(mb) bits in the wale direction, and the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism And then read in the direction of the row, and in the case where the code bits of the mb bits read in the direction of the direction of the memory mechanism are used as the b symbols, the LDPC code is used. The code bit is allocated to the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S The code length N specified by .2 or DVB-T.2 is 64,800 bits. The LDPC code having a coding rate of 5/6; w the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped to 4096 of 4096QAM as one of the aforementioned symbols. Any one of the signal points; the memory means includes 24 wales of 12x2 bits in the horizontal direction, and 64800/(12x2) bits in the wales; the replacement step is in the horizontal direction of the memory mechanism The 12x2 bit code bit read from the column direction is set to the bit bi from the highest bit, and the symbol of the 12x2 bit of the preceding two symbols is 135786. Doc -94- 200937872 The first i+i bit is set to the bit yi from the highest bit, and the following replacement is performed according to the above allocation rule: the bit bQ is assigned to the bit y8, and the bit b2 is assigned to Bit y, assigning bit b4 to bit y6, assigning bit b6 to bit y 1, assigning bit b8 to bit, and assigning bit b! 〇 to bit y 5, 〇 Bit b12 is assigned to bit y2, bit b! 4 is assigned to bit y 3, bit b 丨 6 is assigned to bit y 7, and bit b! 8 is assigned to bit Element y 1 〇, assigning bit b2G to bit yi 〗, assigning bit b22 to bit y9, assigning bit b! to bit y2〇, and assigning bit b3 to bit y 12, Bit b5 is assigned to bit y 18, bit b7 is assigned to bit yi3, bit b9 is assigned to bit yi6, bit b!! is assigned to bit y 1 7 , bit b 13 is assigned The bit y 14, the bit b15 is assigned to the bit yis, the bit b! 7 is assigned to the bit y 1 9, the bit b 19 is assigned to the bit y22, -95- 135786.doc 200937872 The element b2! is assigned to the bit y23, and the bit b23 is assigned to the bit y21. 54. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the preceding direction of the memory mechanism is read as one symbol, and the specific positive integer is b, and the memory mechanism is Storing mb bits in the direction of the row, and storing N/(mb) bits in the wale direction, the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then in the foregoing row Direction reading, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the foregoing The allocation rule of the symbol element of the symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB-T.2 The code length N specified by the specification is 16200 bits, and the coding rate is 8/9 LDPC code; The m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped as one of the 4096 signal points determined by 4096QAM as one of the symbols; the memory mechanism includes 24 rows of 12x2 bits are stored in the horizontal direction, and 16200/(12x2) bits are memorized in the longitudinal direction; 135786.doc -96-200937872 in the foregoing replacement step will be in the row direction I of the aforementioned memory mechanism The 12x2 bit code bit is the bit ii from the highest bit, and the 12x2 bit symbol of the last two symbols is counted from the highest bit. The i+i bit is set to the bit yi, and the following replacement is performed according to the ^= matching rule: the bit b〇 is assigned to the bit y10, the bit b2 is assigned to the bit y〇, and the bit b4 is assigned to Bit y 1, 分配 Assign bit b6 to bit y2, bit b8 to bit y3, bit b 1 〇 to bit y 4, bit b 12 to bit y 5, bit b !4 is assigned to bit y6, bit b16 is assigned to bit y8, bit bh 8 is assigned to bit y7, bit b2G is assigned to bit y! 1 ' bit b22 is assigned to bit y9 , assigning bit b! to bit y22', assigning bit b3 to bit y! 2, assigning bit b5 to bit y 13, assigning bit b7 to bit y 14, bit b9 Assigned to bit y 15 ' Assign bit b!! to bit y 1 6 Assign bit b! 3 to bit y 1 7 ' 135786.doc -97- 200937872 Assign bit b! 5 to Bit y 丨 8, assigning bit b! 7 to bit y20, assigning bit b! 9 to bit y! 9, assigning bit b21 to bit y23, and assigning bit b23 to bit Y2 1. 5 5. A data processing method, comprising: a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a log direction and a wale direction The m-bit of the code bit of the LDPC code read in the direction of the preceding direction written in the preceding direction is regarded as one symbol, and the specific positive integer is b, The memory means memorizes mb bits in the direction of the row, and stores N/(mb) bits in the wale direction, wherein the code bits of the LDPC code are written in the longitudinal direction of the memory mechanism, and then Reading in the course direction, in the case where the code □ bit of the mb bit read in the foregoing direction of the memory mechanism is used as the b symbols, the code bit for assigning the LDPC code is used. For the allocation rule indicating the symbol bit of the preceding symbol, replacing the code bit of the mb bit, and replacing the replaced code bit as the symbol bit; the foregoing LDPC code is DVB-S.2 or DVB- The code length N specified by the specification of T.2 is 64800 bits 7〇, and the LDPC with 8/9 encoding rate is 8/9. The m-bit is 12 bits, and the aforementioned integer b is 2; the 12-bit of the aforementioned code bit is mapped as one of the aforementioned symbols to 4096 signal points determined by 135786.doc -98-200937872 4096QAM Any one of the above; the memory mechanism includes 24 wales of 2x2 bits in the horizontal direction, and 64800/(12x2) bits in the longitudinal direction; the replacement step is in the course direction of the memory mechanism The read 12x2 bit code bit is set to the bit h ' from the highest bit and the 12x2 bit of the preceding two symbols is from the highest bit. The i+1th bit from the bit count is set to the bit yi, and the following replacement is performed according to the foregoing allocation rule: 〇 The bit b〇 is assigned to the bit yt 〇, and the bit is assigned to the bit y〇, and the bit is The element b4 is assigned to the bit y 1, the bit b6 is assigned to the bit y2, the bit b8 is assigned to the bit y3, the bit b 1 〇 is assigned to the bit, and the bit b 12 is assigned to the bit y 5. Assign bit b14 to bit y6, bit bi6 to bit ys, bit b 18 to bit y 7, bit b 2G is allocated to bit y 11 ' to assign bit b22 to bit y9, bit bi to bit y22' to bit b3 to bit y 12 ' to assign bit b5 to bit y〗 3 'Assign bit b7 to bit y 14 ' 135786.doc 200937872 Assign bit b9 to bit y 15, assign bit b! i to bit yi 6, assign bit b! 3 to bit Y丨7, the bit b! 5 is assigned to the bit y 18, the bit bi 7 is assigned to the bit y20, the bit b! 9 is assigned to the bit y 19, and the bit b21 is assigned to the bit y23 , the bit b23 is assigned to the bit y21. </ RTI> 56. A data processing method, comprising a replacement step, which is a code bit of an LDPC (Low Density Parity Check) code having a length of N bits in a row direction and a longitudinal direction. The m-bit of the code bit of the LDPC code read in the direction of the row in the memory direction is set as one symbol, and the specific positive integer is b, the memory mechanism The mb bit is memorized in the direction of the row, and the N/(mb) bit is memorized in the wale direction, and the code bit of the LDPC code is written in the longitudinal direction of the memory mechanism, and then in the horizontal direction Reading in the column direction, in the case where the code bits of the mb bits read in the foregoing direction of the memory mechanism are used as the b symbols, the code bits for assigning the LDPC code are assigned to the representation. The allocation rule of the symbol element of the symbol is replaced by the code bit of the mb bit, and the replaced code bit is used as the symbol bit; the LDPC code is DVB-S.2 or DVB-T. The code specified in the specification of 2 135786.doc -100- 200937872 Long N is 64800 bits The LDPC code having a coding rate of 9/10; the m-bit is 12 bits, and the integer b is 2; the 12-bit of the code bit is mapped to 4096QAM as one of the aforementioned symbols. Any one of the signal points; the memory mechanism includes 24 wales of 12x2 bits in the horizontal direction and 64800/(12x2) bits in the waling direction; The 12x2 bit code bit read from the horizontal direction is calculated from the highest bit. The i+th bit is set to be the bit bi, and the symbol bits of the 12x2 bits of the preceding two symbols are consecutively The element i is calculated from the highest bit, and the i+th bit is set to the bit yi. The following replacement is performed according to the foregoing allocation rule: the bit b〇 is assigned to the bit yi 〇, and the bit b2 is assigned to the bit y. 〇, assigning bit b4 to bit y 1, assigning bit b6 to bit y2, assigning bit b8 to bit y3, assigning bit b! 〇 to bit y4, allocating bit b12 Given bit y5, assign bit b! 4 to bit y 6, assign bit b! 6 to bit y 8, assign bit bi 8 to bit y 7, place bit b2Q is assigned to bit y! 1, bit b22 is assigned to bit y9, bit b! is assigned to bit y22, 135786.doc -101 - 200937872 bit b3 is assigned to bit y 12, bit The element b5 is assigned to the bit y 13, the bit b7 is assigned to the bit y 14, the bit b9 is assigned to the bit y!5, the bit bii is assigned to the bit y 16, and the bit b13 is assigned to the bit Yuan yn, assigning bit b 15 to bit y 18, assigning bit b! 7 to bit y2 〇, 位 assigning bit bi 9 to bit y 19, and assigning bit b2! to bit Y23, the bit b23 is assigned to the bit y21. •102- 135786.doc