TW200947446A - Method for erasing P-channel non-volatile memory - Google Patents

Abstract

A method of erasing a P-channel non-volatile memory is provided. This P-channel non-volatile memory includes a select transistor and a memory cell connected in series and disposed on a substrate. In the method of erasing the P-channel non-volatile memory, holes are injected into a charge storage structure by substrate hole injection effect. Hence, the applied operational voltage is low, so the power consumption is lowered, and the efficiency of erasing is enhanced. As a result, an operational speed of the memory is accelerated, and the reliability of the memory is improved.

Description

200947446 ^.498 ltwf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a method of operating a semiconductor memory device, and more particularly to a P-channel non-volatile memory. And [previous technology], Wan, Jie. Among various memory products, there is a non-volatile memory that can perform operations such as reading or erasing a plurality of data, and the stored data is also lost after the integrated component is powered off, and has become a non-volatile memory. A memory component widely used in personal computers and devices. A typical electrically erasable and programmable read-only memory system uses a doped polysilicon to make a floating gate and control gate. However, when the doped polysilicon floating gate layer is present with defects in the oxide layer, it is easy to cause reliability of the leakage current component of the device. Therefore, in the existing non-volatile memory technology, there is also a charge-trapping layer instead of a polysilicon floating gate. The material of the gamma layer is, for example, nitrogen cutting. The Wei-cut charge trapping layer usually has a layer of oxidized oxide, and forms a composite layer of oxidized stone/nitride/oxygen oxide (〇Xide_nitride_oxide, 〇N〇). Such a component is commonly referred to as a 矽/氧化 夕 //氮化 夕 // 氧化 夕 / 石 石 石 石 石 石 石 , , , , , , , , , , , , , , , , , , , , , , , , , , ,电荷 The charge is trapped on a local area of the layer. Therefore, the sensitivity to wear defects in the oxide layer is small, and the leakage current of the element is less likely to occur. Figure 2 is not a schematic diagram of the operation of the conventional non-volatile memory erasing method. In the figure, the symbol # indicates an electron. 200947446 ^-498 ltwf.doc/n Referring to Fig. 1, the P-type channel non-volatile memory is composed of, for example, a substrate 100, an N-type well region 102, a SONOS memory cell 104, and a selective transistor 1〇6. The SONOS memory cell 104 is, for example, connected in series with the selection transistor 106. The SONOS memory cell 104 includes a bottom oxide layer 〇8, a ruthenium nitride layer 110, a top oxide layer 112, a control gate 114, a source/drain region H6, and a source/no-polar region us. The select transistor includes a gate oxide layer Y〇, a select gate 122, a source/nomogram region 118, and a source/nomogram region 124. ❹ If you want to perform the erase operation, apply a voltage of 6 volts in the source/drain region ΐ16, the 井-type well region 〇2, the source/drain region 124, and apply a voltage of 3.3 volts to the selection gate 122. To open the channel below the selection gate 122, the source / / region 118 and the source / no-pole region 124 equipotential, at the control gate $ plus -6 volts to use the F_N tunneling mechanism to the original Stored _ shell material erased. However, when the F-N tunneling mechanism is used to erase the S〇N〇s memory cell 1〇4, the starting voltage of the S_S memory cell 104 decreases with the 'erase time ❹'. However, due to the voltage difference across the control gate U4 and the substrate, the electron self-control gate 114 is also injected into the nitride layer to make the effect of the light change diminish and (10) secret. 〇n) Wipe the second phenomenon to erase saturation. In this way, the erase time of the memory component is long, and (4) the erase performance of the component is recorded. It is shown as a clear view of the erasing time according to the conventional S嶋S memory cell erasing method. When using the tunneling mechanism to erase the data in the SONOS memory cell 1〇4, a different voltage difference is formed between the N-type well regions 102. The n-type well region is 6-^981twf.doc/n 200947446 /if no-pole region 116, source/no-pole region 124 applies a different positive current 2, and a voltage of 3.3 volts is applied to the selection gate 122 to hit ^

Si IS = channel J below makes the source _ area 118 and the source you 5 5 ° 伕 pile Γ. Wherein, the symbol 〇 indicates that a special voltage is applied to the control gate 114, the symbol ▲ indicates that the control electrode is u ❹ ❹ 电 = = shuttle, the control idler 114 is 5 volts, and the volt is applied to the control interpole 114. What is -5.5 volts, long, when the work is done (4) Reduce the effect with time, or even the erased saturation table will not be purchased, and with the addition of the component (Integrity), the bottom oxide of the memory Thickness "to become thinner 3 force test = = balance (such as charge retention ability, etc.) balance: to [invention] The purpose of volatilization is to provide, type channel non-power consumption, low operating voltage applied 'It can save and improve its reliability ^ government rate' and thus shorten the operation speed of the memory. The present invention proposes a kind of j&gt; penalty, s, sound, non-gu and & method, this way, non-volatile ====: 7 ^ltwf.doc/n 200947446 Selecting a transistor and a memory cell. The selection transistor has a selection gate disposed on the substrate and a first source/nomogram region and a second source disposed in the substrate on both sides of the selection gate a pole/bungee region. The memory cell has a control gate disposed on the substrate a charge storage structure disposed between the substrate and the control gate; and a second source/drain region and a third source/drain region respectively disposed in the substrate on both sides of the control gate. The erasing of the non-volatile memory, applying a first voltage to the substrate, applying a second electrical voltage to the third source/no-polar region, and applying a third voltage to the control gate to utilize the substrate hole injection effect The hole is injected into the charge storage structure. The voltage difference between the first voltage and the second voltage is sufficient to form a depletion region near the junction of the third source/drain region and under the control gate. When the first voltage and the first The voltage difference between the two voltages is large enough to cause an impact dissociation in the depletion region (near the junction of the third source/drain region), and an electron-hole pair is generated. Some holes are collided and sufficient The energy, then directly across the oxidation barrier layer. Thereafter, where the control gate is applied with a specific voltage, the holes are captured by the charge storage structure and electrically compensated for the electrons originally present in the charge storage structure. , complete forwarding In one embodiment of the invention, the first voltage is 3.5 to 6.5 volts, the first voltage is 0 volts, and the third voltage is _2 to _5 volts. In one embodiment of the invention, the above ρ The non-volatile memory erasing method of the type channel further includes applying a fourth voltage to the first source/drain region and applying a fifth voltage to the selection gate. The voltage difference between the first voltage and the fifth voltage is sufficient Select the channel area below the gate. The first voltage is 3 5 volts, the first voltage is 0 volts, and the third voltage is -2 to -5 volts. The fourth power 8 200947446 w« -4981twf.d〇c /n The voltage is 0 volts. The fifth voltage is -2 to 6 volts. The well area or the absolute two = = for the n-type substrate, n-type erase operation, so the party's pick-up, '. In the structure, the electric field between the bottom can be low voltage to control the operating speed of the idle pole and the substrate, and because of the charge storage structure: = „pressure and well potential, by selecting the opening of the gate: closed, can It is easy to perform the memory cell erasing operation. In addition, due to the substrate hole injection effect, the hole mechanism and the thickness of the bottom dielectric layer are less affected by the erasing speed. Therefore, the thickness of the bottom dielectric layer can be Thickening, can effectively avoid the leakage current of the memory, and can increase the data preservation effect of the charge storage structure. In addition, the mechanism of injecting the hole into the charge storage structure by using the substrate hole injection effect. The erasing mechanism of the present invention Other erasing mechanisms, such as the FN tunneling mechanism, can be in a more OFF state than the memory cell erasing state. Since the F_N tunneling mechanism is a less efficient erasing mechanism, when using the FN wearing random system, The balance between erase voltage, erase time and erase state requires further consideration. On the other hand, the short-channel effect is more stable by the ash; substrate thermal cavity injection mechanism, ie For the shortest channel length of the process state, a reasonable 〇FF state current can also be achieved. Therefore, when considering the stylization or erasing operation of the memory, the device is set to -4981 twf.doc/n 200947446 The above and other objects, features and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; [Embodiment] FIG. 3 is a schematic diagram of a p-type channel memory erasing operation according to a preferred embodiment of the present invention. In Fig. 3, the symbol _ indicates that the symbol 〇 indicates a hole. For η ' β , please refer to ® 3 , and the 通道-type channel-turning memory of the present invention is composed of, for example, a substrate 200, a 井-type well region 202, a memory cell 204, and a selective transistor 2〇6. The substrate 2 is, for example, a p-type substrate. The 井 type well area 2 is exemplified in the base 200. The memory cell 2〇4 and the selective transistor 2〇6 are, for example, attacked on the N-type well region 202, and the memory cell 204 and the selection transistor 206 are, for example, connected in series. The memory cell 204 includes a bottom dielectric layer 208, a charge storage structure 21, a top dielectric layer 212, a control gate 214, a source/drain region 216, and a source/drain region 218. The bottom dielectric layer 2〇8, the charge storage structure 21〇, the top dielectric layer 212 and the control gate 214 are sequentially disposed on the substrate 200 from bottom to top. The source/drain region 216 and the source/drain region 218 are, for example, disposed in a substrate 2 (N-well region 202) on both sides of the control gate 214. The material of the bottom dielectric layer 208 and the top dielectric layer 212 is, for example, ruthenium oxide. The material of the bottom dielectric layer 208 and the top dielectric layer 212 may also be other dielectric materials. The material of the charge storage structure 210 is, for example, a material such as tantalum nitride, bismuth oxynitride, strontium oxide, titanate, 200947446^4981 twf.d〇c/n, and a donor oxide. The material of the charge storage structure 21A may also be a conductive material, such as a doped polycrystalline material. The material of the control gate 214 is, for example, a conductor material such as a metal oxide or a metal oxide. The source/drain regions and the source/drain regions 218 are, for example, germanium-type p-type doped regions containing boron or boron difluoride. It is worth noting that the top dielectric layer 212 described above can be selectively disposed depending on the design of the components. In one embodiment, between the control gate 120 and the substrate 200, for example, only the bottom dielectric layer 208 and the charge storage structure 210 are disposed. The select transistor 206 includes a gate dielectric layer 220, a select gate 222, a source/&gt;, and a polar region 218 and a source/nomogram region 224. The gate dielectric layer 220 and the gate 222 are sequentially disposed on the substrate 2 from bottom to top. The source/drain regions 218 and the source/drain regions 224 are, for example, disposed in the substrate 200 on both sides of the selection gate 222. The memory cell 204 and the selection transistor 206 share the source/&gt; and the polar region 218 in series.

The material of the gate dielectric layer 220 is, for example, a dielectric material such as ruthenium oxide. The material of the gate 222 is selected to be, for example, a polysilicon material such as doped polysilicon, metal or metal oxide. The source/&gt; and the polar region 224 are, for example, P-type doped regions containing P-type broadcast materials such as sheds. In addition, the memory cell 204 and the selection transistor 206 may also be provided with a lightly doped region to mitigate short channel effects. It should be noted that, in this embodiment, the P-type substrate 200 is matched with the P-type channel non-volatile memory of the N-type well region 202 as an example. However, the memory proposed by the present invention may of course not be set. The N-type well region 'is a P-type channel non-volatile memory of the N-type substrate, or may also be a germanium substrate on the insulating layer provided with the N-type well region. 11 200947446 知;98 ltwf.doc/n Please refer to FIG. 3 'When erasing the P-type channel non-volatile memory, apply voltage Vnw in the N-type well region 202, and apply the county in the source/no-polar region 216 VD, applying a voltage I to the control interpole 214 to inject the hole into the charge storage structure 21() to neutralize the electrons in the charge storage structure 210 using the substrate t hole injection effect. • A voltage difference between % and voltage % to form a depletion region 226 below the control gate 214. The voltage Vnw is, for example, 3.5 to 6.5 volts, and is exemplified by 6 volts in the drawing. Voltage % example © = 疋 0 volts. The voltage Vcg is sufficient to pull the holes in the depletion region 226 into the charge storage structure 210 to neutralize the electrons in the charge storage structure 21'. The voltage VCG is, for example, _2 to _5 volts, and is exemplified by _3 3 volts in the drawing. When a reverse bias is applied between the well 2 and the source/drain region 216, as the voltage vNW increases, a depletion region 226 is formed under the control gate 214, and the intensity of the electric field also This increases, thereby creating an electron hole pair and creating a leakage on the reverse bias junction. At this time, electrons are attracted by the voltage VNW applied to the N-type well region 202 to move to the N-type well region 2〇2, and the Q-hole is attracted to the source V/W by the voltage VD applied to the source/drain region 216 to the source/and The polar region 216 moves. When the voltage Vcg is applied to the control gate 214 and the voltage VCG is negative with respect to the voltage Vd, the hole is attracted by the voltage VcG applied to the control gate=14 to move to the control gate 214, and is pulled into the charge storage structure. In 210, the holes are offset from the previous electrons, and the p-type channel non-volatile memory is thus erased. On the other hand, when the P-channel non-volatile memory is erased, a voltage Vs is applied to the source/drain region 224 to apply a gate voltage VSG. The voltage Vs is, for example, 0 volts. The voltage Vnw is 12 ^ 981 twf.doc / n 200947446 of the voltage Vsg , and the difference is sufficient to open the channel region below the selection gate 222. The voltage Vsg is, for example, -2 to 6 volts, in the figure, it is 3 3 volts (the voltage difference between the voltage and the voltage VSG is 2.7 volts) or 6 volts (the voltage difference between the voltage Vnw and the voltage Vsg is 〇V or Floating) as an example. When a bias is applied to the select gate 222 to open the channel region below the select gate 222, the potential of the source/drain region 218 and the source/drain region 224 are approximately equal. That is, the source/drain region 218 has a voltage corresponding to the voltage VS. Thus, a depletion region 226 is formed below the control interpole 214 on the source/no-polar region 2!8 side, thereby causing generation of an electron hole pair and forming a leakage current on the inversion junction. At this time, electrons are attracted by the voltage VN w applied to the N-type well region 2〇2 to move to the N-type well region 2 〇2, and the hole is attracted to the source/drain region 218 by the voltage Vs to the source/ The drain region 218 moves the alarm to apply a voltage VcG to the control gate 214, and when the voltage &amp; is negative with respect to the voltage ^, the hole is moved by the voltage v applied to the control gate 214 to the control gate 214, and is pulled In the charge storage structure 210, the electrons of the lightning cancel each other, and the non-volatile memory of the P-type channel is thus erased.

Figure 4 is a graph showing the relationship between the read current and the erase time obtained in accordance with the non-volatile memory method of the present invention. In the figure 验, the example U is symbolized) is applied to the N-type well region.

Voltage, a voltage of G volts is applied to the source/secret region 216; a voltage of -3 volts is applied to Z 214; 〇: = is applied to the source/nomogram region, and a voltage of 〇V is applied to the selected side electrode. In the experimental example A, the voltage of 6.5 volts is not applied to the N-type well region 202, the primary pole/no 13 w81 twf.doc/n 200947446 polar region 216 is applied with a voltage of 〇volts; and the voltage of the control gate 2i4 is applied with _4 volts. A voltage of 〇V is applied to the source/drain region 224, and a voltage of 0 volts is applied to the selection gate. As shown in Fig. 4, for Experimental Example 1, when the erasing time elapsed for 0 i seconds, the read current was rapidly reduced by 7 orders of magnitude, indicating that the effect was erased. Similarly, for Experimental Example 2, when the erasing time was passed, the reading current was rapidly decreased to the order of the experimental example i at G.G1 sec, indicating that the memory cell was effectively erased. Please refer to 2 and Figure 4 at the same time, using f to know;: Nf random except for memory cell. ‘ Even if the erasure time is more than i seconds, the money will make the reading stream fast. When the _ system wipes the memory cell, the read current can be quickly and easily reduced at a lower voltage of the exercise component and the time is less than G.i. Therefore, the present invention has a lower operating voltage than that of the postal heating system, which saves power, and can reduce the time and improve the efficiency of erasing, thereby shortening the operating speed of the components. Wiping the above-mentioned 'Purchase of the P-Road Forwarding Memory of the Invention/' Because of the use of the base hole injection effect, the hole is injected into the charge ^, in the middle to perform the erase operation' The operating voltage is low, the electric field between the two upper electrodes and the substrate can be low, which can save power and the Wei domain of the peripheral charge pump circuit, improve the operating speed of the erased t memory, and improve the reliability of the component^ 2 Selecting the opening and closing of the gate can be easily carried out. In addition, due to the use of the substrate hole injection effect, the mechanism of injecting the hole into the charge storage structure, the bottom dielectric The thickness of the layer does not affect the erasing speed. Therefore, the thickness of the bottom dielectric layer can be increased, and the leakage current of the memory can be avoided, and the life and the preservation effect of the tributary can be increased.

In addition, due to the substrate hole injection effect, the mechanism of injecting holes into the charge storage structure, the erase operation is less affected by the channel length dimension, so the component size is reduced, which can improve its electrical performance and help improve The degree of integration of components. While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. [Simple description of the diagram] The operation ^ i is in accordance with the conventional non-volatile memory FN erasing method = the relationship is the conventional 卩 type channel non-volatile statistic ^ relationship diagram in different erasing voltage The reading current obtained in the following and the method of erasing the non-volatile memory in the eradication process, the method of removing the socks of the body. The reading current and the erasing time of the electric support are +y81twf.doc/n 200947446 [Main component symbol description] 100,200: substrate 108: bottom oxide layer 110: tantalum nitride layer 112: top oxide layer 102, 202: N-type well region 104, 204: memory cell 106, 206: select transistor 114, 214: control gate 116, 118, 124, 216, 218, 224: source/drain region 110: gate oxidation Layers 122, 222: select gate 208: bottom dielectric layer 210: charge storage structure 212: top dielectric layer 220: gate dielectric layer 16

Claims (1)

200947446—X. Patent Application Range: 1. A method for erasing non-volatile memory of p-type channel, the p-type channel non-volatile memory includes: a selective transistor arranged in series on a substrate a memory cell, wherein the selection transistor comprises a substrate disposed on the substrate, a selected interpole, and the substrate disposed on both sides of the selected closed electrode: a first source/nopole region and a second source/ a non-polar region; the memory cell includes a control gate on which the e is placed on the 6-well substrate, and is disposed between the substrate and the control gate. The charge storage structure is disposed on the two sides of the control idler respectively. The second source/drain region and the third source/drain region in the substrate, the erase method includes: a applying a first voltage to the substrate, applying the third source/drain region The seventh voltage 'applies a third voltage to the control gate to inject a hole into the charge storage structure by using a substrate hole injection effect, wherein a voltage difference between the first voltage and the second voltage is sufficient A depletion zone is formed near the third source/drain region and below the control gate. The third electrical dust empty lack sufficient hole region pulled into the charge storage structure. The method of erasing a p-type channel non-volatile memory according to claim 1, wherein the first voltage is 3.5 to 6.5 volts. 3. The method of erasing a P-type channel non-volatile memory according to claim 1, wherein the second voltage is 0 volts. 4. The method of erasing a p-type channel non-volatile memory according to claim 1, wherein the third voltage is -2 to -5 volts. 5. The method for erasing the p-type overnight non-volatile memory according to claim 1 of the patent scope includes applying a fourth 17 81 twf.doc/n 200947446 to the first source/no-polar region. And applying a fifth voltage to the selection gate, wherein the voltage difference of the fifth voltage of the first voltage fish is sufficient to open a channel region below the selection gate Ϊ 6 as claimed in claim 5 The method for erasing a non-volatile memory of a p-type channel, wherein the first voltage is 3.5~6 5 volts, and the second type is 7. The p-type channel is non-volatile as described in claim 5 of the patent application scope. A method of erasing a memory, wherein the second voltage is G volts. 8. A method of erasing a P-type channel non-volatile φ cryptor as described in claim 5, wherein the third voltage is -2 to -5 volts. 9. The method of erasing a P-type channel non-volatile memory 1 according to claim 5, wherein the fourth voltage is 0 volts. The P-channel non-volatile body-character=wiping method according to claim 5, wherein the fifth voltage is -2 to 6 volts. U. The method of erasing a P-channel non-volatile marker according to claim 1, wherein the substrate is an N-type substrate or an N-type well region.