200944909 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種在陣列（Array)製程中檢測非晶矽殘留缺陷 (A-Si Residue Defect)之技術，特別是關於一種可提高非晶矽殘留 缺陷檢出能力之畫素佈局結構及其製造方法。 【先前技術】 在液晶顯不器（LCD)製程中’係經由前段的陣列（Array)製程、 組立（Cell)製程，以及後段之模組（Module)製程等，才完成整個 顯示器之製作。其中，在陣列（Array)製程中，至少包括有閘極電極 〇 (Gate 日 ectrode，GE)形成、半導髏電極（Semiconduct〇r Bectr〇de， SE)形成、源汲極電極（Source Drain electrode，SD)形成、接觸 通道（Contact Hold，CH)形成以及晝素電極（pixe| E|ectr〇cje，pE) 形成等五道階段，且每道階段使用之光罩都須經過成膜、微影、蝕刻、 剝膜等製程，反覆5次才能形成薄膜電晶體基板。 目則為止，習知的薄膜液晶顯示器構造係由一非晶石夕層結構所組 成的薄膜電晶體（TFT元件開關）、儲存電容(〇纪)及透明導電電極(丨TQ 或IZO) ’利用上、下基板提供一電壓差去驅動液晶而產生旋光效果， ❹藉由此電壓耦合而提供液晶開啟角度，再配合上基板彩色濾光片，提 供矩陣式的光源二元素紅綠藍，經掃描線(Gate Line)與資料線(Data Line)搭配控制，使晝素配光產生單點色彩，而巨集延伸到平面顯示彩 色效果。當畫素存在缺陷時，上下基板已無法保持電壓值去驅動液晶 旋光，使畫素在平面顯示器上呈現出無法控制的亮暗點分佈，甚至是 灰點，因而降低液晶顯示器的顯像品質，是故在出廠前都會先經過電 性測試後才能出貨。 陣列自動測試機（ArrayTester)主要是著重於主動區域（Actjve Area)的電氣特性，用以發現製造過程所產生的各種缺陷。就陣列測 試而言’非晶石夕殘留係指非晶石夕層因製程因素所造成之晝素缺陷，例 200944909 如，非晶矽沈積前異物、非晶矽顯影不良及非晶矽蝕刻殘留等，此 影響陣列製練率之最大瓶頸。當晝素發生非㈣_ 1Q並重叠到資 料線（data line) 12時’如第1A圖及第1B圖所示，分 同時參第1C圖所示’每一晝素包含一電晶體tft、一儲存電1心 及-寄生電容Cgd，且因存在有非紗朗1()，故亦具有—非晶發^ 留重疊電容C·。’由此可以發現晝素因非祕_1Q所造成的下降 電壓（vAS-Residue)’是與非晶石夕殘留10面積大小（其與Cas|t〇有 和資料線12供應的電壓差（VData)成正比關係。 Ο200944909 IX. Description of the Invention: [Technical Field] The present invention relates to a technique for detecting an A-Si Residue Defect in an Array process, and more particularly to an amorphous ruthenium The pixel layout structure of the residual defect detection capability and the manufacturing method thereof. [Prior Art] In the liquid crystal display (LCD) process, the entire display is completed by the Array process, the Cell process, and the module process of the latter stage. Among them, in the Array process, at least a gate electrode GE (Gate ectrode, GE) is formed, a semiconducting 髅 electrode (Semiconductor), a source Drain electrode (Source Drain electrode) , SD) formation, contact Hold (CH) formation and the formation of a halogen electrode (pixe| E|ectr〇cje, pE), and the reticle used in each stage must pass through the film, micro Film, etching, stripping and other processes can be repeated five times to form a thin film transistor substrate. As a matter of course, the conventional thin film liquid crystal display structure is composed of a thin film transistor (TFT element switch), a storage capacitor (〇纪), and a transparent conductive electrode (丨TQ or IZO) composed of an amorphous layer structure. The upper and lower substrates provide a voltage difference to drive the liquid crystal to produce an optical rotation effect, thereby providing a liquid crystal opening angle by the voltage coupling, and then matching the upper substrate color filter to provide a matrix light source two elements red green blue, scanned The Gate Line and the Data Line are combined to control the single-point color of the pixel distribution, and the macro extends to the flat display color effect. When there is a defect in the pixel, the upper and lower substrates can not maintain the voltage value to drive the liquid crystal rotation, so that the pixel exhibits an uncontrollable distribution of bright and dark spots on the flat display, or even a gray point, thereby reducing the development quality of the liquid crystal display. Therefore, it is subject to electrical testing before shipment to the factory. ArrayTester focuses on the electrical characteristics of the active area (Actjve Area) to discover various defects in the manufacturing process. In the case of array testing, 'amorphous talc residue refers to the auxin defects caused by process factors in amorphous slabs, for example, 200944909. For example, foreign matter before amorphous yttrium deposition, poor development of amorphous yttrium, and amorphous etch residue Etc. This affects the biggest bottleneck in the array training rate. When the alizarin occurs non-(4)_1Q and overlaps to the data line 12' as shown in Figure 1A and Figure 1B, it is also shown in Figure 1C. 'Each element contains a transistor tft, one The electric energy 1 heart and the parasitic capacitance Cgd are stored, and since there is a non-saulon 1 (), there is also an amorphous floating residual capacitance C·. 'There can be found that the voltage drop (vAS-Residue) caused by the non-secret _1Q of the alizarin is a 10 area difference with the amorphous stone eve (which is different from the voltage difference between the Cas|t〇 and the data line 12 (VData ) is proportional to the relationship.
而在正常測試條件下，測試能力可依非晶石夕殘留面積大至小而大 幅度遞減，若殘留面積大於畫素區域的1/3，其被檢測出來的機 95% ;若殘留面積小於晝素區域的1/3且大於其1/24，其被檢測出來 的機會則為70〜95% ;若殘留面積小於晝素區域的1/24，則被檢測出 來的機會麟到50%以下，職能力而言，若非晶頻留面積小於 畫素區域的1/3的畫素缺陷，在陣列製程檢測中，就不易被檢出使 得原本在_製程核會將其晝素殘陷修復至正常點，卻因漏檢 漏修而流向㈣細，導贱畫m社製雜補麟點，甚至 是流至後段模組製程成為亮點缺陷。 若非晶石夕殘留畫素缺陷在陣列t程段漏檢漏修，而在組立製紐 ίΪΐΪ ’會造雜立修補以及卡S (CaSSStte)傳送貞#。 ▲、缺陷在陣列與組立製程段漏檢漏修，而在模組製程段被檢出 ^這板會目非祕紗畫素缺陷卿紅亮點，时無法修補， f致面板降階（d〇wngrade)出貨而增㈣板降階之風險。甚至，在 ::答模組製程段中皆漏檢漏修’而出貨給客戶端，將造成產 时控管遭又質疑，更會造成面板品f控管的不穩定性。 圭杏，本發明係提出一種可提高非晶發殘留缺陷檢出能力之 直素佈局⑽構，以克服上述所面臨到的該等問題點。 【發明内容】 t 200944909 本發明之主要目的係在提供一種可提高非晶矽殘留缺陷檢出能力 之晝素佈局結構及其製造方法，其係此採用面板設計佈局方式，增加 虛設非晶矽層（A-Si dummy layer)的設計’使其在現有的測試條件 下’當畫素存在有非晶矽殘留時，藉以提高其電容耦合效應及電子傳 導效應，進而檢出形成晝素缺陷。 本發明之另一目的係在提供一種可提高非晶矽殘留缺陷檢出能力 之畫素佈局結構’其係可有效提南陣列自動測试機檢出發生非晶石夕殘 留之畫素缺陷’以提高產品良率，並增加面板品質控管的穩定性。 本發明之再一目的係在提供一種可提高非晶秒殘留缺陷檢出能力 〇 之畫素佈局結構，其係可降低後續組立段修補之負载，並可避免面板 因亮點而降等售出，可據此增加營收，更可減少亮點退貨之問題。 為達到上述目的，本發明提出一種可提高非晶發殘留缺陷檢出能 力之畫素佈局結構，包含有一透明基板；一第一金屬層位於該透明基 板上，以形成一晝素掃描線、一電晶體之閘極與至少一金屬遮光層； 於第-金屬層上設有-第-絕緣層；並有一非晶石夕層係位於第一絕緣 層上，以形成電晶體之通道與至少一虛設非晶矽層，且此虛設非晶矽 層位於金屬遮光層上方；位於非晶石夕層上有一第二金屬層，其係形成 Φ 畫素資料線及該電晶趙之源極與汲極；另有-第二絕緣廣位於第二 金屬層上，並具有數導通孔；更#—透明導電電極層位於該第二絕緣 層上’可經導通孔與汲極相導通。由於在每—畫素資料線之一側或二 側分別設有-虛設非晶梦層，使其在畫素存在非晶石夕殘留時，可因重 疊至虛設非晶矽層而增加殘留面積。 另外’本發明亦提出-種晝素佈局結構之製造方法，其步驟依序 包括：先提供-透明基板，其上形成一第一金屬層於透明基板上，並 侧形成-畫素掃描線、-電额之_及至少一金相光層；形成 -第-絕緣層糾-金屬層上；再於第—絕緣層上形成—非晶石夕層， 並侧形成電晶體之通道及至少—虛設非轉層，城餘非晶石夕層 7 200944909 位於金屬遮光層上方，·接著形成一第二金屬層於非晶矽層上，並蝕刻 形成一畫素資料線及電晶鱧之源極與汲極；形成一第二絕緣層於第二 金屬層上，並兹刻形成數導通孔；最後形成一透明導電電極層於第二 絕緣層上，使透明導電層可經導通孔與汲極相導通。 底下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本 發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 由於在組立（Cell)測試中的點亮（nght-on)檢測時，若晝素存 在有非晶矽殘留，在灰階測試時就會顯現出亮點缺陷，不僅須重新回 ❹至組立修補段⑽「epa丨Y)將其畫素缺陷修補成暗點，此舉會加重組 立修補段的負荷’且由組立測試中細出的殘留面積統計絕大部份 非晶石夕殘留面積範圍都介於1/3以下，足以證明陣列測試因非晶石夕殘 留面積過小而漏檢漏修之缺點。因此，本發曰月即在現有的測試條件下， 增加虛設非晶矽層（A-Sidummy iayer)，若畫素存在非晶石夕殘留時， 增面積，藉以提高其電容麵合效應及電子傳導效應，進而檢出 形成書素缺陷。 心可提高非晶械留缺陷檢出能力之晝素佈局結構，包含有複 〇 列狀；底下係以單—龛素電極排列結構來詳細說明 圖圖為本發明在製作晝素佈局結構之各步驟結構俯視 π=ο上成長形成一第一金屬層，並經濕二=二 成畫素掃描線（gate line)22、-電晶趙之閘極及金 抱丨 層24261!·Β _，.利_氣概積技術先沈積形成一 26 於金屬層上，再沈積形成一非晶石夕層於第-絕緣層 Π侧或乾侧形成薄膜電晶體之通道28及虛設非晶石夕 層30，且此虛設非晶梦層30係對應位於上述金屬遮光層24上方。再 8 200944909 如第2C圖所示，成長形成—第二金屬層於上述非晶 m形成一晝素資料線32及電晶體之源極與沒極34。i續 參考第2D圖所示，再沈積形成一第二絕緣層％ 上’並以濕綱或乾賴形成數導通孔38，用接層 電容。最後，如第2E圖所示，形成一透明導電轉存 Γί 導電電極層40可經由導通孔28與没極34 “ 石夕等介電材料=一絕緣層26或第二絕緣層36係由氧化石夕或氣化 Ο 以上述各步聰作完成之畫素佈局結構如第3 考第4A圖所示，其係為第3圖之A_A，線段的結構剖視圖，如圖二厂參 本發明之4素佈局結獅錄—透明基板2G上 二 ^，其上再覆蓋有第一絕緣層26，第一絕緣=== ϋ组t畫素紐線32，及在4素線32二取位於第一絕緣 =則設有=層3Q ’其上_—第二_36，最上 方職有透明導電電極層40。當畫素資料線3Under normal test conditions, the test ability can be greatly reduced according to the large residual area of the amorphous stone. If the residual area is larger than 1/3 of the pixel area, the detected machine is 95%; if the residual area is smaller than 1/3 of the halogen region is greater than 1/24, and the chance of being detected is 70 to 95%. If the residual area is less than 1/24 of the halogen region, the detected opportunity is less than 50%. In terms of job ability, if the amorphous frequency retention area is less than 1/3 of the pixel defect in the pixel area, it is not easy to be detected in the array process detection, so that the original 在 process core will repair its 残 残Normal point, but due to missed inspection and leakage, it flows to (4) fine, guides the painting system, and even flows to the back module process to become a bright spot defect. If the amorphous slab residual pixel defects are missed and repaired in the array t-segment, the assembly will be repaired and the card S (CaSSStte) will be transmitted. ▲, defects in the array and the assembly process section missed inspection and repair, and in the module process section is detected ^ this board will not be the secret yarn defects red highlights, can not be repaired, f-induced panel reduction (d〇 Wngrade) increases the risk of board (4) board reduction. Even in the :: answer module process section, the leak detection and repair will be shipped to the client, which will cause the production control to be questioned, and will cause instability of the panel product. In the present invention, the present invention proposes a straight layout (10) which can improve the detection ability of residual defects of amorphous hair to overcome the above-mentioned problems. SUMMARY OF THE INVENTION t 200944909 The main object of the present invention is to provide a pixel layout structure capable of improving the detection ability of amorphous germanium residual defects and a manufacturing method thereof, which adopts a panel design layout manner to add a dummy amorphous germanium layer. The design of (A-Si dummy layer) 'make it under the existing test conditions' when there is amorphous ruthenium residue in the pixel, so as to improve its capacitive coupling effect and electron conduction effect, and then detect the formation of halogen defects. Another object of the present invention is to provide a pixel layout structure capable of improving the detection ability of amorphous ruthenium residual defects, which is capable of effectively detecting the occurrence of amorphous defects in amorphous arrays by an array automatic tester. In order to improve product yield and increase the stability of panel quality control. A further object of the present invention is to provide a pixel layout structure capable of improving the detection ability of amorphous seconds residual defects, which can reduce the load of subsequent assembly of the group, and can prevent the panel from being sold due to the bright spots. According to this, the revenue can be increased, and the problem of returning the bright spot can be reduced. In order to achieve the above object, the present invention provides a pixel layout structure capable of improving the detection capability of residual defects of amorphous hair, comprising a transparent substrate; a first metal layer is disposed on the transparent substrate to form a pixel scan line, a gate of the transistor and at least one metal light shielding layer; a first-first insulating layer is disposed on the first metal layer; and an amorphous layer is disposed on the first insulating layer to form a channel of the transistor and at least one A dummy amorphous layer is disposed, and the dummy amorphous layer is located above the metal light shielding layer; and a second metal layer is formed on the amorphous layer, which forms a Φ pixel data line and a source and a drain of the electron crystal; In addition, the second insulation is widely located on the second metal layer and has a plurality of via holes. Further, the transparent conductive electrode layer is located on the second insulating layer and can be electrically connected to the drain via the via hole. Since a dummy amorphous layer is provided on one side or two sides of each pixel data line, so that the amorphous element exists in the pixel, the residual area may be increased due to overlapping to the dummy amorphous layer. . In addition, the present invention also proposes a method for manufacturing a halogen layout structure, the steps of which include: first providing a transparent substrate, forming a first metal layer on the transparent substrate, and forming a - pixel scan line on the side, - an electric quantity _ and at least one metallographic optical layer; forming a - first insulating layer correction metal layer; forming a non-amorphous layer on the first insulating layer, and forming a channel of the transistor and at least - a dummy The transfer layer, the amorphous austenite layer 7 200944909 is located above the metal light shielding layer, and then forms a second metal layer on the amorphous germanium layer, and is etched to form a pixel data line and the source and the germanium of the crystal germanium. Forming a second insulating layer on the second metal layer and forming a plurality of via holes; finally forming a transparent conductive electrode layer on the second insulating layer, so that the transparent conductive layer can be electrically connected to the drain via the via hole . The purpose, technical contents, features, and effects achieved by the present invention will become more apparent from the detailed description of the embodiments and the accompanying drawings. [Embodiment] Due to the nght-on detection in the Cell test, if there is an amorphous germanium residue in the halogen test, a bright spot defect will appear in the gray scale test, and it is necessary to not only look back. To the group repair section (10) "epa丨Y" to repair its pixel defects into dark spots, this will add the load of the reorganization of the repair section" and the residual area counted in the assembly test will be the largest part of the amorphous The area range is less than 1/3, which is enough to prove that the array test has the disadvantage of missing and repairing due to the small residual area of the amorphous stone. Therefore, the original amorphous layer is added under the existing test conditions. A-Sidummy iayer), if there is a residual amorphous phase in the pixel, the area is increased, so as to increase the capacitance surface effect and the electron conduction effect, and then the formation of the bookin defect is detected. The heart can improve the detection of the amorphous mechanical defect. The elementary layout structure of the capability includes a reticular array; the bottom is a single-parent electrode arrangement structure to explain in detail the figure is formed in the step π=ο of the steps of the structure of the pixel layout. First metal And through the wet two = two pixels of the scan line (gate line) 22, - the gate of the electric crystal Zhao and the layer of the gold hug 24261! · Β _,. Li _ gas accumulation technology first deposited to form a 26 in the metal layer Forming an amorphous layer to form a thin film transistor channel 28 and a dummy amorphous layer 30 on the first side or the dry side of the first insulating layer, and the dummy amorphous layer 30 is corresponding to the metal Above the light shielding layer 24. Further 8 200944909 As shown in Fig. 2C, the second metal layer forms a halogen data line 32 and a source and a die of the transistor 34 in the amorphous m. i. As shown in the figure, a second insulating layer is formed on the second insulating layer and the number of via holes 38 is formed by wet or dry, and the layer capacitor is used. Finally, as shown in FIG. 2E, a transparent conductive transfer Γί is formed. The electrode layer 40 can pass through the via hole 28 and the gate electrode 34. The dielectric material such as Shixia or the second insulating layer 36 is made of oxidized stone or gasified ruthenium. The structure is shown in Figure 4A of the third test, which is the A_A of Figure 3, a structural sectional view of the line segment, as shown in Figure 2 The 4th layout of the lion record - transparent substrate 2G on the second ^, which is covered with a first insulating layer 26, the first insulation === ϋ group t-pixel line 32, and located in the 4-line 32 The first insulation = then is provided with = layer 3Q 'the upper _ - the second _36, and the uppermost position has the transparent conductive electrode layer 40. When the pixel data line 3
It 7：M 4B ^32 ^ 存在有-層非晶傾留42，除了本身之異⑽非晶 ❿ ::==虛設非_ 3〇的面積相互連接，可= h曰碎殘留42的有效總面積與畫素透明導電電極層4〇之間的電容 二效應=缺陷畫素充電後的雜電壓，因產生較大的電容叙合效應 =致缺:畫素形成更大壓降，使其可更有效的降低缺陷畫素保持電 壓’以藉此改善並有效提高陣列自動測試機檢出非晶石夕殘留之畫素缺 陷的能力。 另外，虛設多晶石夕層可依據實際需求與佈局設計，而有-條或二 條=設2，當虛設非㈣層具有二條時，係鋪畫素諸線二侧·; 且每-虛設非晶石夕層下方對應設有金屬遮光層；當虛設非晶梦層只具 有-條時，則僅位於畫素資料之一側，此時亦可達到相同之功效。 9 200944909 处j者自第—金屬層、第二絕緣層及透明導電電極層組成之電極 田U可利用儲存電容利用共同走線（Cs 〇n c〇m)或是儲存電容利 =閘極走線（Cs on Gate) _結構製程。其中，電極結構為儲存電 =利用共同走線（Cs on Com)結構時，此電極結構之佈局設計又可 分為金屬層__層·氧化賴⑽）電極結構、金屬層_絕緣層半導體 層（MIS) _、结構或金屬層·絕緣層·金屬層（M|M)電極結構。 底下再針對儲存電容利用共同走線（Cs 〇n c〇m) t極結構和儲 存電容利用閘極走線（Cs on Gate)電極結構各舉一實施例來加以說 明。 〇 帛5八至5日圖為本發明運關丨丨電減難程製作畫素佈局結構 之各步驟結構俯視圖。首先’如第5A圖所示，提供一透明基板44， 例如玻璃基板；織於此透板44上成長形成—第—金屬層，並經 濕蝕刻或乾蚀刻形成一畫素掃描線（gate Hne) 46、一電晶體之閘極 及金屬遮光層（metal shadow) 48。如第5B圖所示，利用化學氣相 沈積技術統積形成-第-絕緣層5〇料—金屬層上；再沈積形成一 非晶石夕層於第-絕緣層50上，並以濕蚀刻或乾_形成薄膜電晶體之 通道52及虛設非晶石夕@ 54 ’且此虛設非晶石夕層μ係對應位於上述金 屬遮光層48上方。再如第5C圖所示，成長形成一第二金屬層於上述 非aa梦層上’並經漁姓刻或乾蚀刻形成一畫素資料線56及電晶體之源 極與汲極58。接績參考第5D圖所示，再沈積形成一第二絕緣層6〇 於上述第二金屬層上’並賴_或乾_形成數導通孔62，用以電 性連接晝素與儲存電容。最後，如第5E圖所示，形成一透明導電電極 層64於上述第二絕緣層60上，使透明導電電極層64可經由導通孔 62與汲極58相導通。完成後之完整結構即如第5F圖所示。 第6A至6E圖為本發明運用儲存電容利用閘極走線(Cs 〇n Gate) 電極結構製程製作畫素佈局結構之各步驟結構俯視圖。首先，如第 圖所示，提供-透明基板66，例如玻璃基板；然後於此透明基板66 200944909 上成長形成一第一金屬層’並經濕蝕刻或乾蝕刻形成一畫素掃描線 (gate line) 68、一電晶體之閘極及金屬遮光層（meta| shadow) 70。 如第6B圖所示，利用化學氣相沈積技術先沈積形成一第一絕緣層72 於第一金屬層上；再沈積形成一非晶矽層於第一絕緣層72上，並以濕 蚀刻或乾餘刻形成薄膜電晶體之通道74及虛設非晶矽層76，且此虛 設非晶矽層76係對應位於上述金屬遮光層7〇上方。再如第6C圖所 示，成長形成一第二金屬層於上述非晶矽層上，並經濕蝕刻或乾姓刻 形成一晝素資料線78及電晶體之源極與汲極8〇。接續參考第6D圖 所示，再沈積形成一第二絕緣層82於上述第二金屬層上，並以濕蝕刻 〇 或乾姓刻形成導通孔84，用以電性連接畫素與儲存電容。最後，如第 6E圖所示’形成一透明導電電極層86於上述第二絕緣層82上，使透 明導電電極層86可㈣導通孔84與没極80相導通。完成後之完整 結構即如第6F圖所示。 接續比較現有技術與本發明二者之間的差異性。 ，7A圖為先前技術存在有非晶發殘留之畫素電極結構示意圓，如 圖所示’當畫素存在非晶梦殘留10時並重疊到資料線12時，畫素透 明電極層14、絕緣層與非晶残冑1Q將形成電容齡效應有效面積 A1或A2 ’此反向電雜合效應將對畫素齡電容電獅成間接漏電 ，應’而有機會軸畫素缺陷，此畫素關合效應所造成賴電電屋， 係與非晶石夕殘留10耗合區域面積A1或A2及資料線12提供之反 應電壓差成正比；若此非晶㈣留1G柄合區域A1或Μ面積過小、 =向電容叙合效應也㈣低’會使得_自_試機台將無法有效檢 第二Β圖為本發明之第3圖實施例存在有非晶械留之晝素電 結構不意圖’如圖所示，當晝素存在非晶械留&並重 ΐ Ξ ^非晶械留42有效區域面積將與本發明增設之虛設非‘ 層區域面積互相連接，此時畫素透明導電電極層40、絕緣層與虛 200944909 設非晶碎層30以及非晶妙殘留42互相連接區域面積，將形成大電容 耦合效應B1或B2，此反向電容耦合效應將對晝素儲存電容電荷形成 大間接漏電效應，並大於上述現有技術中單獨存在非晶矽殘留面積所 形成之電容耦合效應’使其可容易被陣列自動測試機台檢出，故可有 效改善並提高陣列自動測試機台檢出非晶矽殘留的畫素缺陷能力。 在現有薄膜電晶體線路配置製程中，原本配置於畫素二側的第一 金屬層（金屬遮光層）條狀分布’僅係作為遮光、製程坡度控制或畫 素儲存電容作用；本發明係在金屬層上方增設有虛設非晶石夕層之設 6十’此虛設非晶梦層僅在畫素存在有非晶發殘留時，才會增加電容耦 〇 合面積之效應存在，在正常晝素無非晶石夕殘留之情況下，因無重整到 畫素資料線而沒有漏電途徑的疑慮，故其不影響正常化素作動。 綜上所述，本發明係採用面板設計佈局方式，增加虛設非晶矽層 (A-Si dummy layer)的設計，使其在現有的測試條件下，若畫素存 在有非晶矽殘留時，藉以提高其電容耦合效應及電子傳導效應，進而 檢出形成畫素缺陷，故可有效提高陣列自動測試機檢出發生非晶矽殘 留之畫素缺陷，以提高產品良率，並增加面板品質控管的穩定性；據 此亦可降低後續組立段修補之負載，避免面板因亮點而降等售出，進 而增加營收，更可減少亮點退貨之問題。 〇 以上所述之實施例僅係為說明本發明之技術思想及特點，其目的 在使熟習此項技藝之人士能夠瞭解本發明之内容並據以實施，當不能 以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均 等變化或修飾，仍應涵蓋在本發明之專利範圍内。 【圖式簡單說明】 第1A圖為先前技術單一畫素之佈局示意圖。 第1B圖為第1A圖的部份結構剖視囷。 第1C圖為第1B圖之畫素等效電路圖。 第2A至2E圖為本發明在製作畫素佈局結構之各步驟結構俯視圖。 12 200944909 第3圖為本發明之單一畫素佈局結構示意圖。 第4A圖為第3圖之A-A，線段的結構剖视圖。 第4B圖為第3圖之B-B，線段的結構剖視圖。 素佈局結構之各 第5A至5F圖為本發明運用M丨丨電極結構製程製 步驟結構俯視圖。 5 圖為本發㈣賊存電容_職 極結構製雜作晝素柄結叙各步騎電 晝素結構示意圖。 第圖為本發明存在有非晶残留之晝素結構示意圖。It 7:M 4B ^32 ^ There is a layer of amorphous deposition 42, except for the difference of its own (10) amorphous ❿ ::== dummy non- 3 〇 area is interconnected, can = h smash the residual total of 42 Capacitance two effect between the area and the pixel transparent conductive electrode layer 4 = the impurity voltage after the defective pixel is charged, due to the large capacitance rendezvous effect = defect: the pixel forms a larger voltage drop, making it available It is more effective to reduce the defect pixel retention voltage' to thereby improve and effectively improve the ability of the array automatic tester to detect the pixel defects remaining in the amorphous state. In addition, the dummy polycrystalline stone layer can be designed according to actual needs and layout, and there are - or two = set 2, when the dummy non-(four) layer has two, the system is paved with two sides of the line; and each - dummy non A metal light-shielding layer is arranged under the spar layer; when the dummy amorphous layer has only a strip, it is only located on one side of the pixel data, and the same effect can be achieved at this time. 9 200944909 The electrode field U consisting of the first metal layer, the second insulating layer and the transparent conductive electrode layer can utilize the common storage line (Cs 〇nc〇m) or the storage capacitor profit = gate trace (Cs on Gate) _ Structure process. Wherein, the electrode structure is stored electricity=using a common trace (Cs on Com) structure, the layout design of the electrode structure can be further divided into a metal layer __ layer · oxidized Lai (10) electrode structure, a metal layer _ insulating layer semiconductor layer (MIS) _, structure or metal layer, insulating layer, metal layer (M|M) electrode structure. A common trace (Cs 〇n c〇m) for the storage capacitor is used below. The t-pole structure and the storage capacitor are described using an embodiment of a gate-on-hole (Cs on Gate) electrode structure. 〇 帛5-8 to 5th is a top view of the structure of each step of the layout structure of the picture-making structure of the invention. First, as shown in FIG. 5A, a transparent substrate 44, such as a glass substrate, is provided; the first metal layer is grown on the transparent plate 44, and a pixel scan line is formed by wet etching or dry etching (gate Hne). 46. A gate of a transistor and a metal shadow 48. As shown in FIG. 5B, a chemical vapor deposition technique is used to form a -first insulating layer 5 on the metal layer; a redox layer is formed on the first insulating layer 50, and is wet etched. Or dry-forming the channel 52 of the thin film transistor and the dummy amorphous stone @54' and the dummy amorphous layer is correspondingly located above the metal light-shielding layer 48. Further, as shown in Fig. 5C, a second metal layer is grown on the non-aa layer, and a pixel data line 56 and a source and a drain 58 of the transistor are formed by fish or dry etching. Referring to the fifth embodiment, a second insulating layer 6 is formed on the second metal layer, and a plurality of via holes 62 are formed to electrically connect the halogen and the storage capacitor. Finally, as shown in FIG. 5E, a transparent conductive electrode layer 64 is formed on the second insulating layer 60, so that the transparent conductive electrode layer 64 can be electrically connected to the drain 58 via the via 62. The complete structure after completion is as shown in Figure 5F. 6A to 6E are top views showing the steps of the steps of fabricating a pixel layout structure using a storage capacitor using a gate trace (Cs 〇n Gate) electrode structure process. First, as shown in the figure, a transparent substrate 66, such as a glass substrate, is provided; then a first metal layer is grown on the transparent substrate 66 200944909 and wet-etched or dry-etched to form a pixel line. 68. A gate of a transistor and a metal shade (meta|shadow) 70. As shown in FIG. 6B, a first insulating layer 72 is deposited on the first metal layer by chemical vapor deposition, and an amorphous germanium layer is deposited on the first insulating layer 72 and wet etched or The thin film transistor channel 74 and the dummy amorphous germanium layer 76 are formed by dry etching, and the dummy amorphous germanium layer 76 is correspondingly located above the metal light shielding layer 7〇. Further, as shown in Fig. 6C, a second metal layer is grown on the amorphous germanium layer, and a halogen data line 78 and a source and a drain of the transistor are formed by wet etching or dry etching. Referring to FIG. 6D, a second insulating layer 82 is deposited on the second metal layer, and a via hole 84 is formed by wet etching or dry etching to electrically connect the pixel and the storage capacitor. Finally, a transparent conductive electrode layer 86 is formed on the second insulating layer 82 as shown in Fig. 6E, so that the transparent conductive electrode layer 86 can be electrically connected to the gate 80. The complete structure after completion is as shown in Figure 6F. The difference between the prior art and the present invention is successively compared. 7A is a schematic circle of the pixel structure of the amorphous state in the prior art. As shown in the figure, when the pixel has an amorphous dream residue 10 and overlaps to the data line 12, the pixel transparent electrode layer 14 The insulating layer and the amorphous residue 1Q will form the effective age of the capacitor age effect A1 or A2 'This reverse electrical hybrid effect will cause an indirect leakage of the aging age capacitor lion, which should have a chance of axis defects. The electricity and electricity house caused by the effect of the prime closure is proportional to the reaction voltage difference provided by the 10 area of the amorphous area, A1 or A2 and the data line 12; if the amorphous (4) leaves the 1G shank area A1 or Μ If the area is too small, the ratio of the capacitance to the capacitor is also (4) low will make the _ self-test machine will not be able to effectively check the second picture. The third figure of the present invention is the embodiment of the present invention. The intention is as shown in the figure, when the halogen exists in the amorphous mechanical retention & ΐ 非晶 ^ amorphous mechanical retention 42 effective area will be interconnected with the additional dummy non-layer area of the present invention, at this time the pixel transparent conductive Electrode layer 40, insulating layer and virtual 200944909, amorphous layer 30 and amorphous The area of the interconnected area will form a large capacitive coupling effect B1 or B2. This reverse capacitive coupling effect will form a large indirect leakage effect on the storage capacitance of the halogen storage, and is larger than the residual area of the amorphous germanium in the prior art. The capacitive coupling effect makes it easy to be detected by the array automatic test machine, so it can effectively improve and improve the ability of the array automatic test machine to detect the residual defects of amorphous germanium. In the conventional thin film transistor line configuration process, the stripe distribution of the first metal layer (metal light shielding layer) originally disposed on the two sides of the pixel is only used as a light shielding, a process slope control or a pixel storage capacitor; the present invention is A dummy amorphous stone layer is added above the metal layer. This virtual amorphous layer only increases the effect of the capacitive coupling area when the amorphous element remains in the pixel. In the absence of amorphous australis, there is no doubt about the leakage path because there is no reorganization to the pixel data line, so it does not affect the normalization of the action. In summary, the present invention adopts a panel design layout method to increase the design of a dummy AA layer, so that under the existing test conditions, if there is an amorphous germanium residue in the pixel, In order to improve the capacitive coupling effect and the electron conduction effect, and then detect the formation of pixel defects, it can effectively improve the pixel defect detected by the array automatic test machine to improve the product yield and increase the panel quality control. The stability of the tube; according to this, the load of the subsequent group section repairing can be reduced, the panel can be sold due to the bright spot, and the revenue can be increased, thereby reducing the problem of the bright spot return. The embodiments described above are merely illustrative of the technical spirit and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and practice the present invention. Equivalent changes or modifications made by the spirit of the present invention should still be included in the scope of the present invention. [Simple Description of the Drawing] Figure 1A is a schematic diagram of the layout of a single pixel of the prior art. Figure 1B is a partial cross-sectional view of Figure 1A. Fig. 1C is a pixel equivalent circuit diagram of Fig. 1B. 2A to 2E are plan views showing the steps of the steps of the pixel layout structure of the present invention. 12 200944909 Fig. 3 is a schematic diagram showing the structure of a single pixel layout of the present invention. Fig. 4A is a cross-sectional view showing the structure of the line segment taken along line A-A of Fig. 3. Fig. 4B is a cross-sectional view showing the structure of the line segment B-B of Fig. 3. Each of the prime layout structures is a top view of the step structure of the M? electrode structure manufacturing process of the present invention. 5 Figure is the first (four) thief storage capacitor _ occupational structure making miscellaneous 昼 柄 结 结 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各The figure is a schematic diagram of the structure of a halogen having amorphous residues in the present invention.
第6A至6F © 【主要元件符號說明】 10非晶矽殘留 12資料線 14透明電極層 20透明基板 24金屬遮光層 28薄膜電晶體之通道 32晝素資料線 36第二絕緣層 ® 40透明導電電極層 44透明基板 48金屬遮光層 52薄膜電晶體之通道 56畫素資料線 60第二絕緣層 64透明導電電極層 66透明基板 70金屬遮光層 22晝素掃描線（gate line) 26第一絕緣層 30虛設非晶矽層 34汲極 38導通孔 42非晶矽殘留 46畫素掃描線 50第一絕緣層 54虚設非晶矽層 58汲極 62導通孔 68畫素掃描線 72第一絕緣層 13 200944909 74薄膜電晶體之通道 76 78畫素資料線 80 82第二絕緣層 84 86透明導電電極層 虚設非晶矽層 汲極 導通孔6A to 6F © [Main component symbol description] 10 amorphous germanium residue 12 data line 14 transparent electrode layer 20 transparent substrate 24 metal light shielding layer 28 thin film transistor channel 32 halogen data line 36 second insulating layer ® 40 transparent conductive Electrode layer 44 transparent substrate 48 metal light shielding layer 52 thin film transistor channel 56 pixel data line 60 second insulating layer 64 transparent conductive electrode layer 66 transparent substrate 70 metal light shielding layer 22 pixel line (gate line) 26 first insulation Layer 30 dummy amorphous germanium layer 34 drain 38 via hole 42 amorphous germanium residual 46 pixel scan line 50 first insulating layer 54 dummy amorphous germanium layer 58 drain 62 via hole 68 pixel scan line 72 first insulation Layer 13 200944909 74 thin film transistor channel 76 78 pixel data line 80 82 second insulating layer 84 86 transparent conductive electrode layer dummy amorphous germanium layer drain via