200939607 九、發明說明： 【發明所屬之技術領域】 本發明涉及一種電壓轉換器，尤其涉及一種具有較少 功率損耗之電壓轉換器。 【先前技術】 隨著科技之發展及社會之進步，電子產品之種類越來 越多，電子產品中之積體電路之集成程度也越來越高。而 多數之電子產品需要對其施加一穩定直流電壓以使其工 Ο作。 電壓轉換器主要用來將輸入之直流電壓，作電壓位準 之調節，並使其穩定於所設定之一電壓值，其利用驅動上 橋及下橋功率元件之切換而產生脈波，此脈波經過電感電 容組成之低通濾波器後產生穩定之直流電壓，以供給各種 電子產品，具體請參閱Volkan Kursun等人2004年於IEEE 系統中發表之 “ HIGH INPUT VOLTAGE STEP-DOWN DC-DC CONVERTERS FOR INTEGRATION IN A LOW V VOLTAGE CMOS PROCESS” 一文。 常用之電壓轉換器其一般包括一脈寬調變控制晶片， 利用該脈寬調變控制晶片所產生之驅動訊號分別驅動該上 橋及下橋功率元件。該脈寬調變控制晶片通常為一封裝好 之晶片，其通過設置於其上之基本引腳來實現其基本功 能，即產生之驅動訊號分別驅動該上橋及下橋功率元件。 但是，隨著科技之發展，人們對該脈寬調變控制晶片賦予 了更多之功能，如過電流保護等等，以使採用該脈寬調變 7 200939607 控制晶片之電壓轉換器工作更完善，符合人們之需求。但 是’相應得’於增加這些功能之同時，其需要另外設置額 .外之引腳以與外部各種電子器件相連接以實現上述功能。 ‘隨著積體電路小型化之發展趨勢，該脈寬調變控制晶片於 增加其功能之同時，也需要盡可能地減小其尺寸。而該脈 寬調變控制晶片上之這些額外之引腳極大地限制了使其小 型化之可能性。 ❾ 一種先前技術中所提供之電壓轉換器，其於所採用之 脈寬調變控制晶片上設置一多功能引腳，該脈寬調變控制 曰曰片利用其基本引腳來實現其基本功能，即提供驅動訊號 分別驅動該上橋及下橋功率元件，而採用該多功能引腳來 實現各種增加之功能，如過電流保護等等。但是，該脈寬 調變控制晶片與僅實現基本功能之脈寬調變控制晶片相 比其還疋需要多一個多功能引腳，因此該脈寬調變控制 晶片之尺寸還是比較大，不適合小型化之需求。 Φ 【發明内容】 下面將以實施例說明一種電壓轉換器，該電壓轉換器 所採用之脈寬調變控制晶片之引腳數比較少。 -種電壓轉換器’其包括一個脈寬調變控制晶片，一 ^橋電晶體’-下橋電晶體，—低通濾波器，該上橋電晶 體之源極電連接至—輸人電壓，纽極與訂橋電晶體之 =極相連接，其相連接之處定義為第—節點，該下橋電晶 卽點進一步電連接至該低通濾波器 U入端，該低通ϋ波器之輸出端作為該電壓轉換器之輸 8 200939607 出端，該脈寬調變控制晶片上設置有BOOT引腳，PHASE 引腳，UGATE引腳，LGATE引腳，Vcc引腳以及GND引 .腳，通過這些引腳，該脈寬調變控制晶片進行工作以驅動 該上橋電晶體和該下橋電晶體，該脈寬調變控制晶片内包 毳 括一電流源，一起始重置電路，一第一比較器，一第一驅 動器，一第二驅動器以及一閘極控制邏輯電路，該電流源 與一第一二極體之負極相連接，該連接之處定義為第三節 點，該第一二極體之正極接地，該第一比較器之正向輸入 〇端電連接至該第三節點，其反向輸入端電連接至一第一參 考電壓，其輸出端至該起始重置電路之一個輸入端，該起 始重置電路之另一輸入端電連接至該脈寬調變控制晶片之 Vcc引腳，通過該Vcc引腳與一外接電壓相連接，其輸出 端所輸出之上電重定訊號傳輸至該閘極控制邏輯電路，該 閘極控制邏輯電路接受該上電重定訊號之控制，且該閘極 控制邏輯電路之第一輸出端電連接至該第一驅動器之輸入 端，其第二輸出端電連接至該第二驅動器之輸入端，以輸 ❹ 出一第一脈衝訊號及一與該第一脈衝訊號相反之第二脈衝 訊號以分別驅動該第一驅動器及第二驅動器，該第一驅動 器之正電壓端子電連接至該脈寬調變控制晶片之BOOT引 腳，該第一驅動器之負電壓端子電連接至該脈寬調變控制 晶片之PHASE引腳，該第一驅動器之輸出端電連接至該脈 寬調變控制晶片之UGATE引腳，該第二驅動器之正電壓端 子電連接至該脈寬調變控制晶片之Vcc引腳以與該外接電 壓相連接，該第二驅動器之負電壓端子電連接至該脈寬調 9 200939607 變控制晶片之GND引腳以使其接地，該第二驅動器之輸出 端電連接至該脈寬調變控制晶片之LGATE引腳，該外接電 .壓電連接至-第二二極體之正極，該第二二極體之負極電 .連接至-第-電容之一端，該連接之處定義為第四節點， u第電谷之另一端電連接至該第一節點，該脈寬調變控 制曰曰片之BOOT引腳電連接至該第四節點，其pHASE引腳 電連接至該第-節點，其UGATE引腳電連接至該上橋電晶 體之閘極，其LGATE引腳電連接至該下橋電晶體之問極， 其中，該脈寬調變控制晶片内還進一步包括一第一電阻， 該第-電阻之-端電連接至該第三節點，其另一端電連接 至該脈寬調變控制晶片之PHASE引腳以使該脈寬調變控 制晶片之PHASE引腳作為一多功能引腳。 優選之，該第一比較器之正向輸入端通過一第一控制 開關，連接至該第二節點，該第一控制開關接受該閉極控 制邏輯電路第一輸出端所輸出之第一脈衝訊號之控制，以 ❹使該第一比較器與該上橋電晶體同步工作。 優選之，該低通濾波器包括一電感及一電容，該電感 之一端作為該低通濾波器之輸入端，其電連接至該第一節 ，，該電感之另一端電連接至該電容之一端，其連接之處 疋義為第一節點’其作為該低通滤波器之輸出端，該電容 之另一端接地。 優選之，該脈寬調變控制晶片内還進一步包括一第二 比較器，該第二比較器之反向輸入端電連接至該第三節 點其正向輸入端電連接至一第二參考電壓，其輸出端所 200939607 輸出之過電流訊料輸至該祕控·輯電路，該第二比 較器’電流源，第一電阻以及下擦 保護電路。 電阻及下橋電a曰體組成-個過電流 .之，該第二比較器之反向輸入端通過—第二控制 開關電連接至該第三節點，該第二控制開關接受該間極控 制邏輯電路之第二輸出端所輸出之第二脈衝訊號之控制， 以使該第二比較器與該下橋電晶體同步工作。 〇 優選之，該脈寬調變控制晶片内還進一步包括一第三 比較器，該第三比較器之反向輸入端接地，其正向輸入端 電連接至該脈寬調變控制晶片之PHASE引腳，其輸出端電 連接至該閘極控制邏輯電路以輸出一逆電流控制訊號至該 閘極控制邏輯電路，該第三比較器與該下橋電晶體組成一 個逆電流控制電路。 優選之’該第三比較器之正向輸入端通過一第三控制 開關電連接至該脈寬調變控制晶片之phase引腳，該第三 0控制開關接受該閘極控制邏輯電路第二輸出端所輸出之第 一脈衝訊號之控制’以使該第三比較器與該下橋電晶體同 步工作。 優選之，該脈寬調變控制晶片内還進一步設置一電感 電流感測器，一計數步階電流產生器，一振盪器，一第四 比較器以及一第五比較器，該電感電流感測器之輸入端電 連接至該第三節點，其輸出端電連接至該計數步階電流產 生器之輸入端，該計數步階電流產生器之輸出端電連接至 該振盪器之輸入端，該振盪器之輸出端電連接至該第五比 11 200939607 較器之反向輸入端，該第四比較器之正向輸入端電連接至 一第三參考電壓，其反向輪入端電連接一回饋電壓，該第 .四比較器之輸出端電連接至該第五比較器之正向輸入端， •該第五比較器之輸出端電連接至該閘極控制邏輯電路，該 電感電流感測器，計數步階電流產生器，振盪器，第四比 較器，第五比較器，電流源，以及該第一電阻下橋電晶 體組成了一個輕載效率改善電路。 優選之，該電感電流感測器之輸入端通過一第四控制 開關電連接至該第三節點，該第四控制開關接受該閉極控 制邏輯電路第二輸出端所輸出第二脈衝訊號之控制，以使 該電感電流感測器與下橋電晶體同步工作。 優選之，該回饋電壓為該電壓轉換器之輸出端所輸出 優選之，該電壓轉換器進一步包括一第二電阻與—第 :電，’該第二電阻之—端電連接至該電壓轉換器之輸出 •Ϊ為該第三電阻之一端，該連接之處定 電阻之另一端接地，該回饋電壓為 該第五知點處之電壓。 相較於先刖技術，本發明之電壓轉^ ^ ^ ^ ^ ^ ^ ^ ^ 變控制晶片上之職則腳作器利用該脈寬調 錄撼度η 51腳作為多功能引腳，從而實現各 等=!:，：過電流保護’逆電流控制，輕載效率改善 脈心二=需要額外設置多功能引腳，因此，該 地目=數較少’其尺寸可得到進-步 、八適應目前積體電路小型化之需求。 12 200939607 【實施方式】 下面結合附圖將對本發明實施例作進一步之詳細說 .明。 請參閱圖1，本發明實施例提供之一種電壓轉換器 100，該電壓轉換器100包括一脈寬調變控制晶片200，串 聯於一輸入電壓Vin及接地電位GND之間之一上橋電晶體 110及一下橋電晶體120，及一低通濾波器130，該低通濾 波器130之輸入端連接至該上橋電晶體110與該下橋電晶 〇體120之間，該低通濾波器130之輸出端作為該電壓轉換 器100之輸出端Vout以輸出一穩定之電壓值。 該上橋電晶體110之源極電連接至該輸入電壓Vin，其 汲極與該下橋電晶體120之汲極相連接，該相連接之處定 義為第一節點A，該下橋電晶體120之源極接地。該低通 濾波器130之輸入端電連接至該第一節點A。該低通濾波 器130可由一電感L及一電容C所組成，該電感L之一端 ©作為該低通濾波器130之輸入端，該電感L之另一端與該 電容C之一端相電連接，該連接之處定義為第二節點B， 該電容C之另一端接地，該第二節點B作為該電壓轉換器 100之輸出端Vout。 該脈寬調變控制晶片200上設置有複數基本引腳，其 包括BOOT引腳，PHASE引腳，UGATE引腳，LGATE引 腳，Vcc引腳以及GND引腳。通過這些基本引腳，該脈寬 調變控制晶片200進行工作以分別驅動該上橋電晶體110 以及該下橋電晶體120，使該電壓轉換器100進行工作。 13 200939607 該脈寬調變控制晶片200内設置有一電流源210, 一起 始重置電路 220(Power on Reset, POR)，一第一比較器 230， .一第一驅動器240，一第二驅動器250，以及一閘極控制邏 輯電路260。 該閘極控制邏輯電路260之第一輸出端電連接至該第 一驅動器240之輸入端，以輸出一第一脈衝訊號Vcl至該 第一驅動器240。該閘極控制邏輯電路260之第二輸出端電 連接至該第二驅動器250之輸入端，以輸出一第二脈衝訊 ❹號Vc2至該第二驅動器250。該第一脈衝訊號Vcl與該第 二脈衝訊號Vc2為一對互反之訊號。該第一驅動器240與 該第二驅動器250分別為一放大器。 該第一驅動器240之正電壓端子電連接至該脈寬調變 控制晶片200之BOOT引腳上，其負電壓端子電速接至該 脈寬調變控制晶片200之PHASE引腳上，其輸出端電連接 至該脈寬調變控制晶片200之UGATE引腳上。 ^ 該第二驅動器250之正電壓端子電連接至該脈寬調變 控制晶片200之Vcc引腳上，其通過該Vcc引腳與一外接 電壓Vcc相連接。該第二驅動器250之負電壓端子電連接 至該脈寬調變控制晶片200之GND引腳上，其通過該GND 引腳使該第二驅動器250之負電壓端子接地。（為了表示方 便，圖1中僅將該脈寬調變控制晶片200中之第二驅動器 250之負電壓端子電連接至該GND引腳，而該脈寬調變控 制晶片200中之其他電子元件需要接地時，均採用直接接 地之形式進行體現，惟，本領域普通技術人員可理解的是， 14 200939607 該脈寬調變控制晶片200中需要接地之電子元件均是電連 接至該GND引腳，通過該GND引腳使其接地）。該第二驅 .動器250之輸出端電連接至該脈寬調變控制晶片200之 LGATE引腳。 該電流源210反接一第一二極體211後接地，即該電 流源210與該第一二極體211之負極相連接，該相連接之 處定義為第三節點C，該第一二極體211之正極接地。 該起始重置電路220之一個輸入端電連接至該脈寬調 〇 變控制晶片200之Vcc引腳上，其通過該Vcc引腳與該外 接電壓Vcc相連接，由該外接電壓Vcc提供給該起始重置 電路220能量使其工作。該起始重置電路220之另一輸入 端電連接至該第一比較器230之輸出端。該第一比較器230 之正向輸入端電連接至該第三節點C，其反向輸入端電連 接至一第一參考電壓Vinsen。該起始重置電路220之輸出 端輸出一上電重定訊號POR至該閘極控制邏輯電路260以 @使該閘極控制邏輯電路260輸出第一脈衝訊號Vcl及第二 脈衝訊號Vc2。優選地，該第一比較器230之正向輸入端 電連接一第一控制開關231後電連接至該第三節點C。該 控制開關231接受該閘極控制邏輯電路260之第一輸出端 所輸出之第一脈衝訊號Vcl之控制，以使該第一比較器230 與該上橋電晶體110同步工作。 該外接電壓Vcc進一步地電連接至一第二二極體151 之正極，該第二二極體151之負極與一第一電容152之一 端相連接，該連接之處定義為第四節點D，該第一電容152 15 200939607 之另一端電連接至該第一節點A。 該脈寬調變控制晶片200之BOOT引腳電連接至該第 四節點D，其UGATE引腳電連接至該上橋電晶體110之閘 極，其PHASE引腳電連接至該第一節點A，其LGATE引 腳電連接至該下橋電晶體120之閘極。 該脈寬調變控制晶片200内還進一步設置一第一電阻 Rocset，其一端電連接至該第三節點C，另一端電連接至該 脈寬調變控制晶片200之PHASE引腳，使該脈寬調變控制 晶片200之PHASE引腳作為一多功能引腳，以擴展該脈寬 調變控制晶片200之功能。 該起始重置電路220與該第一比較器230以及上橋電 晶體110組成了 一個電源偵測電路，以判斷該電壓轉換器 100是否處於工作狀態，即其利用該第一比較器240偵測該 第一節點A處之電壓，以判斷電壓轉換器100是否處於工 作狀態。 該電壓轉換器100之工作原理為：當該脈寬調變控制 晶片200被致能後，該脈寬調變控制晶片200會發出一個 致能訊號至該閘極控制邏輯電路260以致能該閘極控制邏 輯電路260。於該閘極控制邏輯電路260被致能後，該電壓 轉換器100之輸出端Vout所輸出之電壓仍為0，而第一驅 動器240及第二驅動器250尚未有驅動訊號輸入。此時， 該閘極控制邏輯電路260發出一確認訊號至該第一驅動器 250，使第一驅動器250導通該上橋電晶體110，該第一節 點A及該脈寬調變控制晶片200之PHASE引腳上之電壓開 16 200939607 始上升。 由於該第一比較器230通過第一控制開關231電連接 .至第三節點C，而第一控制開關231受該閘極控制邏輯電 ，路260之第一輸出端所輸出之第一脈衝訊號Vcl之控制， 因此當上橋電晶體110導通時，該第一控制開關231閉合， 該第一比較器230開始工作。 該第一比較器230之正向輸入端通過該第一電阻 Rocset電連接至該脈寬調變控制晶片200之PHASE引腳， 〇 因此，脈寬調變控制晶片200之PHASE引腳上之電壓上 升，該第一比較器230之正向輸入端之電壓上升。當該第 一比較器230之正向輸入端之電壓大於其反向輸入端輸入 之第一參考電壓Vinsen時，表示該輸入電壓Vin已經啟動。 此時，該第一比較器230之輸出端輸出一 PORE訊號 至該起始重置電路220,且當該起始重置電路220通過該脈 寬調變控制晶片200之Vcc引腳感測到該外接電壓Vcc也 &被啟動時，其輸出一上電重定訊號P0R至該閘極控制邏輯 電路260以使該閘極控制邏輯電路260第一輸出端輸出第 一脈衝訊號Vcl，第二輸出端輸出第二脈衝訊號Vc2。該第 一脈衝訊號Vcl與該第二脈衝訊號Vc2分別透過該第一驅 動器240及第二驅動器250以切換上橋電晶體110及下橋 電晶體120。 由於該第一脈衝訊號Vcl與該第二脈衝訊號Vc2為一 對互為相反之訊號，因此，當上橋電晶體110導通時，該 下橋電晶體120截止；而當上橋電晶體110截止時，該下 17 200939607 橋電晶體120導通。 當該上橋電晶體110導通，下橋電晶體120截止時， .該輸入電壓Vin通過上橋電晶體110對該電感L及電容C 所組成之低通濾波器130進行充電；當該上橋電晶體110 截止，下橋電晶體120導通時，該低通濾波器130通過下 橋電晶體120進行放電。於該低通濾波器130充放電之過 程中，該電壓轉換器100產生輸出電流I，並將該輸入電壓 Vin轉換成一個穩定之電壓，並通過該電壓轉換器100之輸 ❹出端Vout輸出。 由於該第一比較器230之正向輸入端是通過第一控制 開關231後電連接至第三節點C，而該控制開關231接受 該閘極控制邏輯電路260之第一輸出端所輸出之第一脈衝 訊號Vcl之控制，因此，該第一比較器230是與該上橋電 晶體110同步工作之，即該起始重置電路220，該第一比較 器230以及上橋電晶體110所組成之電源偵測電路僅偵測 義該上橋電晶體110導通時該脈寬調變控制晶片200之 ❹ PHASE引腳上之電壓，以判斷該電壓轉換器100是否處於 工作狀態。 由於該第一電阻Rocset是設置於該脈寬調變控制晶片 200内，並通過該第一電阻Rocset將該脈寬調變控制晶片 200之第三節點C與該脈寬調變控制晶片200之PHASE引 腳相互電連接，因此，該脈寬調變控制晶片200之PHASE 引腳可作為多功能引腳。 該脈寬調變控制晶片200内還進一步設置一第二比較 18 200939607 器270。該第二比較器270之反向輸入端電連接至該第三節 點C，其正向輸入端電連接至一第二參考電壓Voc。優選 .地，該第二比較器270之反向輸入端通過一第二開關271 電連接至該第三節點C，該第二開關271接受該閘極控制 邏輯電路260之第二輸出端所輸出之第二脈衝訊號Vc2之 控制，以使該第二比較器270與該下橋電晶體120同步工 作。 該第二比較器270，電流源210，第一電阻Rocset以及 ® 下橋電晶體120組成了 一個過電流保護電路，當該第二比 較器270工作時，其輸出端輸出一過電流訊號0C至該閘極 控制邏輯電路260。 由於本發明之電壓轉換器100還包括由第二比較器 270，電流源210，第一電阻Rocset以及下橋電晶體120所 組成之一過電流保護電路，因此，當該下橋電晶體120導 通時，該電流源210，第一電阻Rocset以及下橋電晶體120 巍組成一個回路。由於該第二比較器270通過第二控制開關 ❹ 271電連接至第三節點C，而第二控制開關271受該閘極控 制邏輯電路260之第二輸出端所輸出之第二脈衝訊號Vc2 之控制，因此當下橋電晶體120導通時，第二控制開關271 閉合，該第二比較器270開始工作。此時如果該脈寬調變 控制晶片200上之PHASE引腳上之電壓低於該第二參考電 壓Voc時，則表示該電壓轉換器100之輸出電流I過大， 此時，該第二比較器270會發出過電流訊號0C至該閘極控 制邏輯電路260，以使該上橋電晶體110及下橋電晶體120 19 200939607 截止，從而降低該輸出電流I，對該電壓轉換器100形成過 電流保護。 . 由於本發明之電壓轉換器100是利用該脈寬調變控制 晶片200上之PHASE引腳從而形成了由第二比較器270， 家 電流源210，第一電阻Rocset以及下橋電晶體120所組成 之過電流保護電路，因此，其並不需要額外地於該脈寬調 變控制晶片200上設置引腳從而實現該過電流保護功能。 此外，該脈寬調變控制晶片200内還可進一步設置一 〇 第三比較器280。該第三比較器280之反向輸入端接地，其 正向輸入端電連接至該脈寬調變控制晶片200之PHASE引 腳，該第三比較器280之輸出端電連接至該閘極控制邏輯 電路260之一輸入端。優選之，該第三比較器280之正向 輸入端通過一第三控制開關281電連接至該脈寬調變控制 晶片200之PHASE引腳，該第三控制開關281之接受該閘 極控制邏輯電路260之第二輸出端所輸出之第二脈衝訊號 a Vc2之控制，以使該第三比較器280與該下橋電晶體120 同步工作。 該第三比較器280與該下橋電晶體120組成了 一個逆 電流控制電路。當該第三比較器280工作時，其輸出端輸 出一逆電流控制訊號至該閘極控制邏輯電路260。 由於本發明之電壓轉換器100還包括由第三比較器 280以及下橋電晶體120所組成之逆電流控制電路，因此， 當該下橋電晶體120導通時，由於該第三比較器280通過 第三控制開關281電連接至第三節點C，而第三控制開關 200939607 281受該閘極控制邏輯電路260之第二輸出端所輸出之第 二脈衝訊號Vc2之控制，因此當下橋電晶體120導通時， ,第三控制開關281閉合，該第三比較器280開始工作。此 ，時如果該脈寬調變控制器200之PHASE引腳上之電壓小於 地電位，則表示該電壓轉換器100處於非連續模式（DCM)， 會產生電流於該下橋電晶體120逆流之現象，從而造成該 電壓轉換器100之效率損耗，此時該第三比較器280之輸 出端產生逆電流控制訊號至該閘極控制邏輯電路260,以立 〇即截止該下橋電晶體120,從而避免該電壓轉換器100之效 率損耗。 由於本發明之電壓轉換器100是利用該脈寬調變控制 晶片200上之PHASE引腳從而形成了由第三比較器280以 及下橋電晶體120所組成之逆電流控制電路，因此，其並 不需要額外地於該脈寬調變控制晶片200上設置引腳從而 實現該逆電流保護之功能。 ^ 進一步地，該脈寬調變控制晶片200内還可設置一電 響 感電流感測器291 (Inductor Current Sense)，一計數步階電 流產生器 292(Counter & Current Step)，一 振盪器 293，一 第四比較器294以及一第五比較器295。 該電感電流感測器291之輸入端電連接至該第三節點 C，以感測該脈寬調變控制晶片200之PHASE引腳上之電 壓，該電感電流感測器291之輸出端電連接至該計數步階 電流產生器292之輸入端，該計數步階電流產生器292之 輸出端電連接至該振盪器293之輸入端，該振盪器293之 21 200939607 輸出端電連接至該第五比較器295之反向輸入端。 該第四比較器294之正向輸入端電連接至一第三參考 .電壓Vref，其反向輸入端電連接至一回饋電壓，該回饋電 ，壓對應於該電壓轉換器100之輸出端Vout所輸出之電壓。 於本實施例中，該電壓轉換器100之輸出端Vout進一步串 聯一第二電阻161及一第三電阻162後接地，該第二電阻 161與第三電阻162之連接之處定義為第五節點E，將該第 五節點E處之電壓Vfb作為該回饋電壓。當然可理解之是， ®該電壓轉換器100之輸出端Vout所輸出之電壓也可作為回 饋電壓。 該第四比較器294之輸出端電連接至該第五比較器 295之正向輸入端，該第五比較器295之輸出端電連接至該 閘極控制邏輯電路260之另一輸入端。 優選之，該電感電流感測器291之輸入端通過一第四 控制開關296電連接至該第三節點C，以感測該脈寬調變 義控制晶片200之PHASE引腳上之電壓。該第四控制開關296 ❹ 接受該閘極控制邏輯電路260之第二輸出端所輸出之第二 脈衝訊號Vc2之控制，以使該電感電流感測器291與該下 橋電晶體120同步工作。 該電感電流感測器291，計數步階電流產生器292，振 盪器293，第四比較器294，第五比較器295，第一電阻 Rocset，下橋電晶體120及電流源210組成一個輕載效率改 善電路，用以改善該電壓轉換器100於輕載模式下之效率。 由於本發明之電壓轉換器100還包括由電感電流感測 22 200939607 器291，計數步階電流產生器292，振盪器293，第四比較 器294，第五比較器295，電流源210，第一電阻Rocset以 .及下橋電晶體120組成之一輕載效率改善電路，因此，當 該下橋電晶體120導通時，該電流源210，第一電阻Rocset 1 以及導通之下橋電晶體120組成一回路。由於該電感電流 感測器291通過第四控制開關296電連接至第三節點C， 而第四控制開關296受該閘極控制邏輯電路260之第二輸 出端所輸出之Vc2訊號之控制，因此當下橋電晶體120導 〇通時，第四控制開關296閉合，該電感電流感測器291開 始工作偵測脈寬調變控制器200之PHASE引腳上之電流， 即偵測判斷該電流源210，第一電阻Rocset以及導通之下 橋電晶體120所組成回路中之電流。 該計數步階電流產生器292通過電感電流感測器291 所輸出之訊號判斷是否持續地產生輕載電流，如持續地產 生輕載電流，則表示該電壓轉換器100持續地處於輕載模 應式下，此時，該計數步階電流產生器292產生一電流至該 振盪器293中，以降低該振盪器293之輸出頻率，其輸出 頻率通過第五比較器295輸出至該閘極控制邏輯電路260 以降低其輸出之第一脈衝訊號Vcl及第二脈衝訊號Vc2之 頻率，從而降低了該上橋電晶體110及下橋電晶體120之 切換頻率，減少由於該上橋電晶體110及下橋電晶體120 之切換而造成之效率損耗，使採用該電壓轉換器100之電 子裝置可具有更長之待機時間。 由於本發明之電壓轉換器100主要是利用該脈寬調變 23 200939607 控制晶片200上之PHASE引腳從而形成了由電感電流感測 器291，計數步階電流產生器292，振盪器293，第四比較 .器294，第五比較器295，第一電阻Rocset，下橋電晶體120 及電流源210所組成之輕載效率改善電路，因此，其也相 * 應得減少了該脈寬調變控制晶片200上之引腳數。 相較於先前技術，本發明之電壓轉換器100利用該脈 寬調變控制晶片200上之PHASE引腳作為多功能引腳，從 而實現各種功能，如過電流保護，逆電流控制，輕載效率 〇改善等各種功能，其並不需要額外設置多功能引腳，因此， 該脈寬調變控制晶片200上之引腳數較少，其尺寸可得到 進一步地減少，其適應目前積體電路小型化之需求。 綜上所述，本發明確已符合發明專利之要件，遂依法 提出專利申請。惟，以上所述者僅為本發明之較佳實施方 式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案 技藝之人士援依本發明之精神所作之等效修飾或變化，皆 π應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 圖1係本發明實施例所提供之一種電壓轉換器之電路 示意圖。 【主要元件符號說明】 電壓轉換器 100 脈寬調變控制晶片 200 上橋電晶體 110 下橋電晶體 120 24 200939607 低通濾、波器 130 電流源 210 • 起始重置電路 220 第一比較器 230 第一驅動器 240 第二驅動器 250 閘極控制邏輯電路 260 ❹ 第一二極體 211 第一控制開關 231 第二二極體 151 第一電容 152 第二比較器 270 第二控制開關 271 第三比較器 280 第三控制開關 281 ο 電感電流感測器 291 計數步階電流產生器 292 振盪器 293 第四比較器 294 第五比較器 295 第二電阻 161 第三電阻 162 第四控制開關 296BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage converter, and more particularly to a voltage converter having less power loss. [Prior Art] With the development of technology and the advancement of society, there are more and more types of electronic products, and the integration of integrated circuits in electronic products is becoming higher and higher. Most electronic products require a stable DC voltage to be applied to them. The voltage converter is mainly used to adjust the input DC voltage as a voltage level and stabilize it to a set voltage value, which generates a pulse wave by switching between the upper bridge and the lower bridge power component. The wave passes through a low-pass filter composed of an inductor and a capacitor to generate a stable DC voltage for supply to various electronic products. For details, please refer to "High INPUT VOLTAGE STEP-DOWN DC-DC CONVERTERS FOR" published by Volkan Kursun et al. INTEGRATION IN A LOW V VOLTAGE CMOS PROCESS" article. A commonly used voltage converter generally includes a pulse width modulation control chip, and the driving signals generated by the pulse width modulation control chip respectively drive the upper and lower bridge power components. The pulse width modulation control chip is typically a packaged wafer that implements its basic function by means of a basic pin disposed thereon, i.e., the resulting drive signal drives the upper and lower bridge power components, respectively. However, with the development of technology, people have given more functions to the pulse width modulation control chip, such as overcurrent protection, etc., so that the voltage converter using the pulse width modulation 7 200939607 control chip is more perfect. , in line with people's needs. However, while correspondingly adding these functions, it is necessary to additionally set the external pins to connect with various external electronic devices to achieve the above functions. ‘With the trend toward miniaturization of integrated circuits, this pulse width modulation control chip needs to reduce its size as much as possible while increasing its function. These extra pins on the pulse width modulation control chip greatly limit the possibility of miniaturization. A voltage converter provided in the prior art, which is provided with a multi-function pin on the pulse width modulation control chip used, and the pulse width modulation control chip uses its basic pin to realize its basic function. The driving signal is separately driven to drive the upper and lower bridge power components, and the multi-function pin is used to implement various added functions, such as overcurrent protection and the like. However, the pulse width modulation control chip requires one more multi-function pin than the pulse width modulation control chip which only implements the basic function. Therefore, the pulse width modulation control chip is relatively large in size and is not suitable for small size. Demand for change. Φ [Description of the Invention] A voltage converter will be described with reference to an embodiment in which the pulse width modulation control chip has a relatively small number of pins. a voltage converter comprising a pulse width modulation control chip, a bridge transistor '-lower bridge transistor, a low pass filter, the source of the upper bridge transistor being electrically connected to the input voltage, The neopolar pole is connected to the pole of the bridge transistor, and the junction is defined as a first node, and the lower bridge transistor is further electrically connected to the low-pass filter U-input, the low-pass chopper The output end is used as the output of the voltage converter 8200939607. The pulse width modulation control chip is provided with a BOOT pin, a PHASE pin, a UGATE pin, a LGATE pin, a Vcc pin and a GND pin. Through these pins, the pulse width modulation control chip operates to drive the upper bridge transistor and the lower bridge transistor, and the pulse width modulation control chip includes a current source, a start reset circuit, and a first a comparator, a first driver, a second driver and a gate control logic circuit, the current source is connected to a negative pole of a first diode, the connection is defined as a third node, the first two The anode of the polar body is grounded, and the positive input of the first comparator The terminal is electrically connected to the third node, and the inverting input end is electrically connected to a first reference voltage, and the output end thereof is to an input end of the initial reset circuit, and the other input end of the initial reset circuit is electrically Connected to the Vcc pin of the pulse width modulation control chip, connected to an external voltage through the Vcc pin, and the output electrical signal of the output end of the output terminal is transmitted to the gate control logic circuit, the gate control logic The circuit receives the control of the power-on reset signal, and the first output end of the gate control logic circuit is electrically connected to the input end of the first driver, and the second output end is electrically connected to the input end of the second driver, And outputting a first pulse signal and a second pulse signal opposite to the first pulse signal to respectively drive the first driver and the second driver, wherein a positive voltage terminal of the first driver is electrically connected to the pulse width modulation Controlling the BOOT pin of the chip, the negative voltage terminal of the first driver is electrically connected to the PHASE pin of the pulse width modulation control chip, and the output end of the first driver is electrically connected to the pulse width modulation control chip The UGATE pin, the positive voltage terminal of the second driver is electrically connected to the Vcc pin of the pulse width modulation control chip to be connected to the external voltage, and the negative voltage terminal of the second driver is electrically connected to the pulse width adjustment 9 200939607 The control GND pin of the control chip is grounded, and the output of the second driver is electrically connected to the LGATE pin of the pulse width modulation control chip, and the external connection is electrically connected to the second diode a positive pole of the second diode, connected to one end of the -first capacitor, the connection is defined as a fourth node, and the other end of the u electric valley is electrically connected to the first node, the pulse width The BOOT pin of the modulation control chip is electrically connected to the fourth node, the pHASE pin is electrically connected to the first node, and the UGATE pin is electrically connected to the gate of the upper bridge transistor, and the LGATE pin thereof Electrically connected to the bottom of the lower bridge transistor, wherein the pulse width modulation control chip further includes a first resistor, the end of the first resistor is electrically connected to the third node, and the other end is electrically connected Up to the PHASE pin of the pulse width modulation control chip to make the pulse width adjustment PHASE pin control wafer as a multi-function pin. Preferably, the forward input end of the first comparator is connected to the second node through a first control switch, and the first control switch receives the first pulse signal outputted by the first output end of the closed-loop control logic circuit Controlling the first comparator to operate in synchronization with the upper bridge transistor. Preferably, the low pass filter comprises an inductor and a capacitor, one end of the inductor being an input end of the low pass filter, electrically connected to the first section, and the other end of the inductor is electrically connected to the capacitor At one end, where it is connected, the first node is referred to as the output of the low-pass filter, and the other end of the capacitor is grounded. Preferably, the pulse width modulation control chip further includes a second comparator, wherein the inverting input terminal of the second comparator is electrically connected to the third node, and the forward input terminal thereof is electrically connected to a second reference voltage. The output current of the output terminal 200939607 is output to the secret control circuit, the second comparator 'current source, the first resistor and the lower erase protection circuit. The resistor and the lower bridge are composed of an overcurrent. The inverting input of the second comparator is electrically connected to the third node through a second control switch, and the second control switch accepts the interpole control Controlling the second pulse signal outputted by the second output of the logic circuit to synchronize the second comparator with the lower bridge transistor. Preferably, the pulse width modulation control chip further comprises a third comparator, wherein the inverting input terminal of the third comparator is grounded, and the forward input terminal is electrically connected to the PHASE of the pulse width modulation control chip. a pin whose output is electrically connected to the gate control logic circuit to output a reverse current control signal to the gate control logic circuit, the third comparator and the lower bridge transistor forming a reverse current control circuit. Preferably, the positive input terminal of the third comparator is electrically connected to the phase pin of the pulse width modulation control chip through a third control switch, and the third zero control switch receives the second output of the gate control logic circuit. The control of the first pulse signal outputted by the terminal is such that the third comparator operates in synchronization with the lower bridge transistor. Preferably, the pulse width modulation control chip further comprises an inductor current sensor, a step current generator, an oscillator, a fourth comparator and a fifth comparator, the inductor current sensing The input end of the device is electrically connected to the third node, and the output end thereof is electrically connected to the input end of the counting step current generator, and the output end of the counting step current generator is electrically connected to the input end of the oscillator, The output end of the oscillator is electrically connected to the inverting input terminal of the fifth ratio 11 200939607, the positive input end of the fourth comparator is electrically connected to a third reference voltage, and the reverse wheel end is electrically connected a feedback voltage, an output of the fourth comparator is electrically connected to a forward input of the fifth comparator, and an output of the fifth comparator is electrically connected to the gate control logic circuit, the inductor current sensing The step-by-step current generator, the oscillator, the fourth comparator, the fifth comparator, the current source, and the first resistor lower bridge transistor form a light load efficiency improving circuit. Preferably, the input end of the inductor current sensor is electrically connected to the third node through a fourth control switch, and the fourth control switch receives the control of the second pulse signal outputted by the second output end of the closed-loop control logic circuit. So that the inductor current sensor works in synchronization with the lower bridge transistor. Preferably, the feedback voltage is preferably outputted by the output of the voltage converter, the voltage converter further comprising a second resistor and a first electrical connection, wherein the terminal of the second resistor is electrically connected to the voltage converter The output Ϊ is one end of the third resistor, and the other end of the fixed resistor is grounded, and the feedback voltage is the voltage at the fifth known point. Compared with the prior art, the voltage of the invention is controlled by the ^^^^^^^^ variable on the wafer, and the pulse width of the pulse width η 51 is used as a multi-function pin, thereby realizing Each =!:,: Overcurrent protection 'reverse current control, light load efficiency improves pulse heart two = need to set additional multi-function pins, therefore, the land size = fewer 'its size can get advanced - step, eight adaptation The current demand for miniaturization of integrated circuits. [Embodiment] Hereinafter, embodiments of the present invention will be further described in detail with reference to the accompanying drawings. Referring to FIG. 1 , a voltage converter 100 is provided in an embodiment of the present invention. The voltage converter 100 includes a pulse width modulation control chip 200 connected in series between an input voltage Vin and a ground potential GND. 110 and a lower bridge transistor 120, and a low pass filter 130, the input end of the low pass filter 130 is connected between the upper bridge transistor 110 and the lower bridge transistor 120, the low pass filter The output of 130 acts as the output Vout of the voltage converter 100 to output a stable voltage value. The source of the upper bridge transistor 110 is electrically connected to the input voltage Vin, and the drain thereof is connected to the drain of the lower bridge transistor 120. The phase connection is defined as a first node A, the lower bridge transistor The source of 120 is grounded. An input of the low pass filter 130 is electrically coupled to the first node A. The low-pass filter 130 can be composed of an inductor L and a capacitor C. One end of the inductor L is used as an input end of the low-pass filter 130, and the other end of the inductor L is electrically connected to one end of the capacitor C. The connection is defined as the second node B, the other end of which is grounded, and the second node B serves as the output Vout of the voltage converter 100. The pulse width modulation control chip 200 is provided with a plurality of basic pins including a BOOT pin, a PHASE pin, a UGATE pin, an LGATE pin, a Vcc pin, and a GND pin. Through these basic pins, the pulse width modulation control chip 200 operates to drive the upper bridge transistor 110 and the lower bridge transistor 120, respectively, to operate the voltage converter 100. 13 200939607 The pulse width modulation control chip 200 is provided with a current source 210, a start reset circuit 220 (Power on Reset, POR), a first comparator 230, a first driver 240, and a second driver 250. And a gate control logic circuit 260. The first output of the gate control logic circuit 260 is electrically coupled to the input of the first driver 240 to output a first pulse signal Vcl to the first driver 240. The second output of the gate control logic circuit 260 is electrically coupled to the input of the second driver 250 to output a second pulse signal Vc2 to the second driver 250. The first pulse signal Vcl and the second pulse signal Vc2 are a pair of signals opposite to each other. The first driver 240 and the second driver 250 are respectively an amplifier. The positive voltage terminal of the first driver 240 is electrically connected to the BOOT pin of the pulse width modulation control chip 200, and the negative voltage terminal is connected to the PHASE pin of the pulse width modulation control chip 200, and the output thereof is output. The terminal is electrically connected to the UGATE pin of the pulse width modulation control chip 200. The positive voltage terminal of the second driver 250 is electrically connected to the Vcc pin of the pulse width modulation control chip 200, and is connected to an external voltage Vcc through the Vcc pin. The negative voltage terminal of the second driver 250 is electrically connected to the GND pin of the pulse width modulation control chip 200, and the negative voltage terminal of the second driver 250 is grounded through the GND pin. (For convenience of illustration, only the negative voltage terminal of the second driver 250 in the pulse width modulation control wafer 200 is electrically connected to the GND pin in FIG. 1, and the pulse width modulation control other electronic components in the wafer 200 When grounding is required, it is embodied in the form of direct grounding. However, those skilled in the art can understand that 14 200939607 electronic components that need to be grounded in the pulse width modulation control chip 200 are electrically connected to the GND pin. , grounded through the GND pin). The output of the second driver 250 is electrically coupled to the LGATE pin of the pulse width modulation control chip 200. The current source 210 is connected to the first diode 211 and grounded, that is, the current source 210 is connected to the negative pole of the first diode 211, and the phase connection is defined as the third node C, the first two The anode of the polar body 211 is grounded. An input terminal of the initial reset circuit 220 is electrically connected to the Vcc pin of the pulse width modulation control chip 200, and is connected to the external voltage Vcc through the Vcc pin, and is supplied by the external voltage Vcc. The initial reset circuit 220 energizes it to operate. The other input of the initial reset circuit 220 is electrically coupled to the output of the first comparator 230. The forward input of the first comparator 230 is electrically coupled to the third node C, and the inverting input is electrically coupled to a first reference voltage Vinsen. The output of the initial reset circuit 220 outputs a power-on reset signal POR to the gate control logic circuit 260 to enable the gate control logic circuit 260 to output the first pulse signal Vcl and the second pulse signal Vc2. Preferably, the forward input terminal of the first comparator 230 is electrically connected to a first control switch 231 and then electrically connected to the third node C. The control switch 231 receives the control of the first pulse signal Vcl outputted by the first output terminal of the gate control logic circuit 260 to synchronize the first comparator 230 with the upper bridge transistor 110. The external voltage Vcc is further electrically connected to the anode of a second diode 151, and the cathode of the second diode 151 is connected to one end of a first capacitor 152, and the connection is defined as a fourth node D, The other end of the first capacitor 152 15 200939607 is electrically connected to the first node A. The BOOT pin of the pulse width modulation control chip 200 is electrically connected to the fourth node D, the UGATE pin is electrically connected to the gate of the upper bridge transistor 110, and the PHASE pin is electrically connected to the first node A. The LGATE pin is electrically connected to the gate of the lower bridge transistor 120. Further, a first resistor Rocset is further disposed in the pulse width modulation control chip 200, one end of which is electrically connected to the third node C, and the other end is electrically connected to the PHASE pin of the pulse width modulation control chip 200, so that the pulse The PHASE pin of the wide modulation control chip 200 serves as a multi-function pin to expand the function of the pulse width modulation control chip 200. The initial reset circuit 220 and the first comparator 230 and the upper bridge transistor 110 form a power detection circuit to determine whether the voltage converter 100 is in an active state, that is, it utilizes the first comparator 240 to detect The voltage at the first node A is measured to determine whether the voltage converter 100 is in an active state. The voltage converter 100 operates on the principle that when the pulse width modulation control chip 200 is enabled, the pulse width modulation control chip 200 sends an enable signal to the gate control logic circuit 260 to enable the gate. The pole control logic circuit 260. After the gate control logic circuit 260 is enabled, the voltage output from the output terminal Vout of the voltage converter 100 is still 0, and the first driver 240 and the second driver 250 have not yet received a drive signal input. At this time, the gate control logic circuit 260 sends a confirmation signal to the first driver 250, so that the first driver 250 turns on the upper bridge transistor 110, the first node A and the PHASE of the pulse width modulation control chip 200. The voltage on the pin turns on 16 200939607 and starts to rise. Since the first comparator 230 is electrically connected to the third node C through the first control switch 231, and the first control switch 231 is controlled by the gate control logic, the first pulse signal outputted by the first output end of the path 260 The control of Vcl, therefore, when the upper bridge transistor 110 is turned on, the first control switch 231 is closed, and the first comparator 230 starts to operate. The forward input terminal of the first comparator 230 is electrically connected to the PHASE pin of the pulse width modulation control chip 200 through the first resistor Rocset, and thus, the voltage on the PHASE pin of the pulse width modulation control chip 200 is controlled. Ascending, the voltage at the forward input of the first comparator 230 rises. When the voltage at the forward input of the first comparator 230 is greater than the first reference voltage Vinsen input to its inverting input, it indicates that the input voltage Vin has been activated. At this time, the output of the first comparator 230 outputs a PORE signal to the start reset circuit 220, and when the start reset circuit 220 is sensed through the Vcc pin of the pulse width modulation control chip 200, When the external voltage Vcc is also activated, it outputs a power-on reset signal P0R to the gate control logic circuit 260 to cause the first output terminal of the gate control logic circuit 260 to output the first pulse signal Vcl, the second output. The terminal outputs a second pulse signal Vc2. The first pulse signal Vcl and the second pulse signal Vc2 are respectively transmitted through the first driver 240 and the second driver 250 to switch the upper bridge transistor 110 and the lower bridge transistor 120. Since the first pulse signal Vcl and the second pulse signal Vc2 are mutually opposite signals, when the upper bridge transistor 110 is turned on, the lower bridge transistor 120 is turned off; and when the upper bridge transistor 110 is turned off; At the time, the next 17 200939607 bridge transistor 120 is turned on. When the upper bridge transistor 110 is turned on and the lower bridge transistor 120 is turned off, the input voltage Vin is charged by the upper bridge transistor 110 to the low pass filter 130 composed of the inductor L and the capacitor C; when the upper bridge is When the transistor 110 is turned off and the lower bridge transistor 120 is turned on, the low pass filter 130 is discharged through the lower bridge transistor 120. During the charging and discharging of the low-pass filter 130, the voltage converter 100 generates an output current I, converts the input voltage Vin into a stable voltage, and outputs it through the output terminal Vout of the voltage converter 100. . Since the forward input terminal of the first comparator 230 is electrically connected to the third node C through the first control switch 231, the control switch 231 receives the output of the first output terminal of the gate control logic circuit 260. The control of a pulse signal Vcl, therefore, the first comparator 230 operates in synchronization with the upper bridge transistor 110, that is, the initial reset circuit 220, the first comparator 230 and the upper bridge transistor 110 The power detection circuit detects only the voltage on the PHASE pin of the pulse width modulation control chip 200 when the upper bridge transistor 110 is turned on to determine whether the voltage converter 100 is in operation. The first resistor Rocset is disposed in the pulse width modulation control chip 200, and the third node C of the pulse width modulation control chip 200 and the pulse width modulation control chip 200 are disposed by the first resistor Rocset. The PHASE pins are electrically connected to each other, so the PHASE pin of the pulse width modulation control chip 200 can be used as a multi-function pin. A second comparison 18 200939607 270 is further disposed in the pulse width modulation control chip 200. The inverting input of the second comparator 270 is electrically coupled to the third node C, the forward input of which is electrically coupled to a second reference voltage Voc. Preferably, the inverting input terminal of the second comparator 270 is electrically connected to the third node C through a second switch 271, and the second switch 271 receives the output from the second output terminal of the gate control logic circuit 260. The second pulse signal Vc2 is controlled to synchronize the second comparator 270 with the lower bridge transistor 120. The second comparator 270, the current source 210, the first resistor Rocset and the lower bridge transistor 120 form an overcurrent protection circuit. When the second comparator 270 operates, the output terminal outputs an overcurrent signal 0C to The gate control logic circuit 260. Since the voltage converter 100 of the present invention further includes an overcurrent protection circuit composed of the second comparator 270, the current source 210, the first resistor Rocset and the lower bridge transistor 120, when the lower bridge transistor 120 is turned on The current source 210, the first resistor Rocset, and the lower bridge transistor 120 巍 form a loop. The second comparator 270 is electrically connected to the third node C through the second control switch 271 271, and the second control switch 271 is received by the second pulse signal Vc2 outputted by the second output terminal of the gate control logic circuit 260. Control, so when the lower bridge transistor 120 is turned on, the second control switch 271 is closed and the second comparator 270 begins to operate. At this time, if the voltage on the PHASE pin on the pulse width modulation control chip 200 is lower than the second reference voltage Voc, it indicates that the output current I of the voltage converter 100 is too large. At this time, the second comparator 270 will send an overcurrent signal 0C to the gate control logic circuit 260 to turn off the upper bridge transistor 110 and the lower bridge transistor 120 19 200939607, thereby reducing the output current I, forming an overcurrent on the voltage converter 100. protection. Since the voltage converter 100 of the present invention controls the PHASE pin on the wafer 200 by the pulse width modulation, the second comparator 270, the home current source 210, the first resistor Rocset and the lower bridge transistor 120 are formed. The overcurrent protection circuit is composed, and therefore, it is not necessary to additionally provide a pin on the pulse width modulation control chip 200 to implement the overcurrent protection function. In addition, a third comparator 280 may be further disposed in the pulse width modulation control chip 200. The inverting input terminal of the third comparator 280 is grounded, and the forward input terminal thereof is electrically connected to the PHASE pin of the pulse width modulation control chip 200, and the output terminal of the third comparator 280 is electrically connected to the gate control. One of the inputs of logic circuit 260. Preferably, the positive input terminal of the third comparator 280 is electrically connected to the PHASE pin of the pulse width modulation control chip 200 through a third control switch 281, and the third control switch 281 accepts the gate control logic. The second pulse signal a Vc2 outputted by the second output of the circuit 260 is controlled to cause the third comparator 280 to operate in synchronization with the lower bridge transistor 120. The third comparator 280 and the lower bridge transistor 120 form an inverse current control circuit. When the third comparator 280 is in operation, its output terminal outputs a reverse current control signal to the gate control logic circuit 260. Since the voltage converter 100 of the present invention further includes a reverse current control circuit composed of the third comparator 280 and the lower bridge transistor 120, when the lower bridge transistor 120 is turned on, since the third comparator 280 passes The third control switch 281 is electrically connected to the third node C, and the third control switch 200939607 281 is controlled by the second pulse signal Vc2 outputted by the second output terminal of the gate control logic circuit 260, so that when the lower bridge transistor 120 When turned on, the third control switch 281 is closed and the third comparator 280 starts operating. Therefore, if the voltage on the PHASE pin of the PWM controller 200 is less than the ground potential, it indicates that the voltage converter 100 is in a discontinuous mode (DCM), and a current is generated in the downstream transistor 120. a phenomenon that causes the efficiency of the voltage converter 100 to be lost. At this time, the output of the third comparator 280 generates a reverse current control signal to the gate control logic circuit 260 to turn off the lower bridge transistor 120. Thereby the efficiency loss of the voltage converter 100 is avoided. Since the voltage converter 100 of the present invention controls the PHASE pin on the wafer 200 by using the pulse width modulation to form a reverse current control circuit composed of the third comparator 280 and the lower bridge transistor 120, It is not necessary to additionally provide a pin on the pulse width modulation control wafer 200 to implement the function of the reverse current protection. Further, a pulse-sensing current sensor 291 (Inductor Current Sense), a count step current generator 292 (Counter & Current Step), and an oscillator 293 may be disposed in the pulse width modulation control chip 200. A fourth comparator 294 and a fifth comparator 295. The input end of the inductor current sensor 291 is electrically connected to the third node C to sense the voltage on the PHASE pin of the pulse width modulation control chip 200. The output of the inductor current sensor 291 is electrically connected. Up to the input end of the counting step current generator 292, the output end of the counting step current generator 292 is electrically connected to the input end of the oscillator 293, and the output end of the oscillator 293 is electrically connected to the fifth The inverting input of comparator 295. The forward input terminal of the fourth comparator 294 is electrically connected to a third reference voltage Vref, and the reverse input terminal is electrically connected to a feedback voltage corresponding to the output terminal Vout of the voltage converter 100. The voltage that is output. In this embodiment, the output terminal Vout of the voltage converter 100 is further connected in series with a second resistor 161 and a third resistor 162, and is grounded. The connection between the second resistor 161 and the third resistor 162 is defined as a fifth node. E. The voltage Vfb at the fifth node E is used as the feedback voltage. Of course, it can be understood that the voltage output from the output terminal Vout of the voltage converter 100 can also be used as the feedback voltage. The output of the fourth comparator 294 is electrically coupled to the forward input of the fifth comparator 295, and the output of the fifth comparator 295 is electrically coupled to the other input of the gate control logic 260. Preferably, the input of the inductor current sensor 291 is electrically coupled to the third node C via a fourth control switch 296 to sense the voltage on the PHASE pin of the pulse width modulation control chip 200. The fourth control switch 296 接受 receives the control of the second pulse signal Vc2 outputted by the second output terminal of the gate control logic circuit 260 to synchronize the inductor current sensor 291 with the lower bridge transistor 120. The inductor current sensor 291, the counting step current generator 292, the oscillator 293, the fourth comparator 294, the fifth comparator 295, the first resistor Rocset, the lower bridge transistor 120 and the current source 210 form a light load. A efficiency improvement circuit for improving the efficiency of the voltage converter 100 in a light load mode. Since the voltage converter 100 of the present invention further includes an inductor current sensing 22 200939607 291, a counting step current generator 292, an oscillator 293, a fourth comparator 294, a fifth comparator 295, a current source 210, first The resistor Rocset is a light load efficiency improving circuit composed of the lower bridge transistor 120. Therefore, when the lower bridge transistor 120 is turned on, the current source 210, the first resistor Rocset 1 and the underlying bridge transistor 120 are formed. First circuit. Since the inductor current sensor 291 is electrically connected to the third node C through the fourth control switch 296, and the fourth control switch 296 is controlled by the Vc2 signal output by the second output terminal of the gate control logic circuit 260, When the lower bridge transistor 120 is turned on, the fourth control switch 296 is closed, and the inductor current sensor 291 starts to work to detect the current on the PHASE pin of the pulse width modulation controller 200, that is, the current source is detected and determined. 210, the first resistor Rocset and the current in the loop formed by the bridge transistor 120. The counting step current generator 292 determines whether the light load current is continuously generated by the signal outputted by the inductor current sensor 291. If the light load current is continuously generated, it indicates that the voltage converter 100 is continuously in the light load mode. In this case, at this time, the counting step current generator 292 generates a current into the oscillator 293 to lower the output frequency of the oscillator 293, and the output frequency thereof is output to the gate control logic through the fifth comparator 295. The circuit 260 reduces the frequency of the output of the first pulse signal Vcl and the second pulse signal Vc2, thereby reducing the switching frequency of the upper bridge transistor 110 and the lower bridge transistor 120, and reducing the upper bridge transistor 110 and the lower The loss of efficiency caused by the switching of the bridge transistor 120 allows the electronic device employing the voltage converter 100 to have a longer standby time. Since the voltage converter 100 of the present invention mainly uses the pulse width modulation 23 200939607 to control the PHASE pin on the wafer 200 to form the inductor current sensor 291, the step current generator 292, the oscillator 293, The comparator 294, the fifth comparator 295, the first resistor Rocset, the lower bridge transistor 120 and the current source 210 constitute a light load efficiency improving circuit, and therefore, the phase width modulation is reduced. The number of pins on the wafer 200 is controlled. Compared with the prior art, the voltage converter 100 of the present invention utilizes the PHASE pin on the pulse width modulation control chip 200 as a multi-function pin to implement various functions such as overcurrent protection, reverse current control, and light load efficiency. 〇Improvement and other functions, it does not need to additionally set the multi-function pin, therefore, the pulse width modulation control chip 200 has a small number of pins, and its size can be further reduced, which is suitable for the current integrated circuit small Demand for change. In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Any equivalent modifications or variations made by persons skilled in the art to the spirit of the present invention are intended to be included in the scope of the following claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a circuit of a voltage converter according to an embodiment of the present invention. [Main component symbol description] Voltage converter 100 Pulse width modulation control chip 200 Upper bridge transistor 110 Lower bridge transistor 120 24 200939607 Low pass filter, wave device 130 Current source 210 • Initial reset circuit 220 First comparator 230 first driver 240 second driver 250 gate control logic circuit 260 ❹ first diode 211 first control switch 231 second diode 151 first capacitor 152 second comparator 270 second control switch 271 third comparison 280 third control switch 281 ο inductor current sensor 291 count step current generator 292 oscillator 293 fourth comparator 294 fifth comparator 295 second resistor 161 third resistor 162 fourth control switch 296