200939548 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種發光裝置，尤其關於一種高效率發光 裝置。 【先前技術】200939548 VI. Description of the Invention: [Technical Field] The present invention relates to a light-emitting device, and more particularly to a high-efficiency light-emitting device. [Prior Art]
發光二極體(Light-Emitting Diode ; LED)之應用頗為廣 泛，可應用於例如光學顯示裝置、交通號誌、資料儲存裝置、 通訊裝置、照明裝置以及醫療裝置。 在傳統LED中，通常用金屬層做為電極，例如為鈦/金或 鉻/金。但是金屬會吸收光線，導致LED的低發光效率。因此， ^ED包含一反射層位於電極與發光疊層之間，以增進發光效 然而因為高反射率的金屬層與半導體的發光疊層之間的黏 …不易，導致上述的結構具有可靠度與剝離的問題。 【發明内容】 向效率發光裝置包含一基板；一反射層形成於基板之 厂點歸形成於反射層之上；—第一半導體層形成於黏結 二a ，一活性層形成於第一半導體層之上；以及一第二半導 夹二?成於活性層之上。第二半導體層包含—第—表面，第-人一&有一第一低區域與一第一高區域。高效率發光裝置更包 導電結構’導電結構包含一第一電極形成於第一低區域之 Μ及一第二電極形成於基板之下。 形成t實施例巾’高效率發光裝置更包含ϋ流阻擔層 導體乂 低區域之上，以及一第一電流擴散層形成於第二半 層覆=第—表面與第—電触制之上，其巾第—電流擴散 弟一咼區域。第一電極位於第一電流擴散層之上且位於 200939548 第一電流阻擋層之上方。 又-實施例中’第-高區域更包含自第—表面向下之 第一複數個六角孔穴’以增進光摘出效率。 另一實施例中，一高效率發光裝置包含一基板；一反射層 形成於基板之上；一黏結層形成於反射層之上；一第一半導^ 層形成於黏結層之上；一活性層形成於第一半導體層之上；以 及一第二半導體層形成於活性層之上。第二半導體層包含一第 一表面，第一表面包括一第一低區域與一第一高區域。第一半 ^體層包含一第一表面，第二表面包括一第二低區域與一第二Light-Emitting Diodes (LEDs) are widely used in applications such as optical display devices, traffic signs, data storage devices, communication devices, lighting devices, and medical devices. In conventional LEDs, a metal layer is usually used as the electrode, such as titanium/gold or chrome/gold. However, the metal absorbs light, resulting in low luminous efficiency of the LED. Therefore, ^ED includes a reflective layer between the electrode and the light-emitting layer to enhance the light-emitting effect. However, because the adhesion between the high-reflectivity metal layer and the semiconductor light-emitting layer is not easy, the above structure has reliability and The problem of stripping. SUMMARY OF THE INVENTION A light-emitting device includes a substrate; a reflective layer is formed on the substrate to be formed on the reflective layer; a first semiconductor layer is formed on the bonding layer a, and an active layer is formed on the first semiconductor layer. And a second semi-conductor is formed on the active layer. The second semiconductor layer includes a first surface, a first low region and a first high region. The high efficiency illuminating device further comprises a conductive structure. The conductive structure comprises a first electrode formed on the first low region and a second electrode formed under the substrate. Forming an embodiment towel, the high-efficiency light-emitting device further includes a lower region of the turbulent resistance layer conductor, and a first current diffusion layer is formed on the second half-layer layer - the first surface and the first electrical contact The towel is the first to spread the current. The first electrode is over the first current spreading layer and above the first current blocking layer of 200939548. Further, in the embodiment, the 'first-high region further includes the first plurality of hexagonal holes from the first surface to the left surface to enhance the light extraction efficiency. In another embodiment, a high efficiency light emitting device comprises a substrate; a reflective layer is formed on the substrate; a bonding layer is formed on the reflective layer; a first semiconducting layer is formed on the bonding layer; A layer is formed over the first semiconductor layer; and a second semiconductor layer is formed over the active layer. The second semiconductor layer includes a first surface, the first surface including a first low region and a first high region. The first half of the body layer includes a first surface, and the second surface includes a second low area and a second
❹ 高區域。高效率發光裝置更包含一導電結構，導電結^包含二 第一電極形成於第一低區域之上與一第二電極形成於第二低 區域之f*。 ' 一 - /又實施例中’南效率發光裝置更包含一第一電流阻擒層 形成於第-低區域，以及-第—電流擴散層形成於第二半導^ ^之第-表面與第-電流阻擔層之上，其中第一電流擴散層 蓋第二高區域。此外，高效率發光裝置更包含一第二電流阻擔 2成於第二低區域之上’以及—第二電流擴散層形成於第二 +導體，之第二表面與第二電流阻擋層之上，其中第二電流擴 散層覆蓋第二高區域。第一電極係位於第一電流擴散層之上， 且位於第一電流阻擋層之上方。第二電極係位於第二電流擴散 層之上，且位於第二電流阻播層之上方。 、 另一實施例中，第一高區域與第二高區域分別包含自第一 表f向下延伸之第一複數個六角孔穴與自第二表面向下延伸 之第二複數個六角孔穴’以增進光摘出效率。 另一實施例中，一製造高效率發光裝置之方法包含提供一 基板；形成一反射層於基板上；形成一黏結層於反射層上；形 成第一半導體層於黏結層上’形成一活性層於第一半導體層 上；形成一第二半導體層於活性層上；移除部份之第二半導體 200939548 ^ 導體層以裸露第—半導體層之一第二表 ηΐ=之一第一表面與第二表面;形成-第士 成一第一電流阻擋層於第一低區域之上與t^ 於第二低區域之上；形成一笛一番、讀也興第一電抓阻擋層 第-電流阻擋層之上，與—第於第二半導體層與 f-電抓阻擒層之上，形成—第—電極於第—電流擴 上，以及形成-第二電極於第二電流擴散層之上。’、 【實施方式】 Ο❹ High area. The high-efficiency light-emitting device further comprises a conductive structure, wherein the conductive electrode comprises two first electrodes formed on the first low region and a second electrode formed on the second low region f*. In the first embodiment, the south efficiency light-emitting device further comprises a first current blocking layer formed in the first-low region, and the first-current diffusion layer is formed on the second surface of the second semiconductor. Above the current blocking layer, wherein the first current spreading layer covers the second high region. In addition, the high efficiency light emitting device further includes a second current blocking 2 formed on the second low region 'and a second current diffusion layer is formed on the second + conductor, the second surface and the second current blocking layer Where the second current spreading layer covers the second high region. The first electrode is located above the first current diffusion layer and above the first current blocking layer. The second electrode is located above the second current spreading layer and above the second current blocking layer. In another embodiment, the first high region and the second high region respectively include a first plurality of hexagonal holes extending downward from the first table f and a second plurality of hexagonal holes extending downward from the second surface. Improve light extraction efficiency. In another embodiment, a method of fabricating a high efficiency light emitting device includes providing a substrate; forming a reflective layer on the substrate; forming a bonding layer on the reflective layer; forming a first semiconductor layer on the bonding layer to form an active layer On the first semiconductor layer; forming a second semiconductor layer on the active layer; removing a portion of the second semiconductor 200939548 ^ conductor layer to expose one of the first semiconductor layers, the second surface η ΐ = one of the first surface and the first Two surfaces; forming - a first current blocking layer on the first low region and t ^ above the second low region; forming a flute, reading the first electric scratch barrier first-current blocking Above the layer, and above the second semiconductor layer and the f-electric scratching layer, a first electrode is formed on the first current, and a second electrode is formed on the second current diffusion layer. ‘, [Embodiment] Ο
如第1A所示，一高效率發光裝置i包 一 射層11形成於基板10之上.一點社爲7 土 ’反 上.-室-主道^ ^ 黏結層12形成於反射層11之 上丄第+V體層13形成於黏結層12 形成於第-半導體層13之上= 性層14 、、紐爲…了 ” 及一第二半導體層15形成於 半導體層15具有遠離活性層14之一第 一古 ’、中第一表面151具有一第-低區域152與-第 二述第—表面151係移除部份第二半導體層15 ^二較，性層14之第一低區域152，以及-較遠離 活性層14之第一高區域153。 艰離 形J第-低區域152之方法例如為濕蝕刻、乾蝕刻 機械研磨法或感應輕合式電漿_，第—低區域152之反 至?為-般鋁鏡反射率之7〇%。為了獲得更佳的反射率，第一 ，區域152之表面粗輪度低於第一高區域153之表面粗糙度， 最佳為一平整表面。因為第一低區域152之表面具有較小之表 面粗糙度，導致介於一第一電極A與第一低區域152間之介 面的臨界角減小，增加潍層14射向第—低區域152的光線 被全反射的機率。被第一低區域152反射之光線可在被反射層 11 後射向第一高區域153，光摘出的機率較高。此外，自 第=高區域153到第一低區域152之高度差約為100奈米〜1 微米，更佳為200奈米〜300奈米。第一低區域152佔第二半 200939548 . 導體層15之第-表面151表面積之比例低於3〇%。 在蠢晶製程中藉由輕與控㈣韻參數，例如氣體流 率、氣至壓力或溫度等，可使第一高區域153形成一非平整表 面。也可經由濕蝕刻、乾蝕刻或微影等方式移除部分第二半導 體層I5，使第-1^區域I53形成一週期性、類週期性或任意 之圖案。因為第一高區域153的非平整表面，射向第一高區域 153之光線的光摘出效率因而提高^第—高區域153也可為複 數個凸部與/或複數個凹部。 基板ίο可為金屬基複合材料（Metal Matrix c〇mp〇site; ❹ MMC)、陶兗基複合材料（Ceramic Matrix Composite; CMC)、 矽(Si)、構化蛾(ip)、刪匕鋅吻㈣、氮化紹⑻的、石申化鎵 (GaAs)、碳化矽(SiC)、磷化鎵(GaP)、磷砷化鎵(GaAsP)、氧化 鋅(ZnO)、麟化銦(inp)、鎵酸鐘①iGa〇2)、紹酸鐘①认从)或上 述材料之組合。反射層11可為銦(In)、錫(Sn)、鋁(A1)、金(Au)、 鉑(Pt)、鋅(Zn)、銀(Ag)、鈦(Ti)、錯(Pb)、錯(Ge)、銅(Cu)、鎳 ⑽、鈹化金(AuBe)、鍺化金(AuGe)、鋅化金(AuZn)、錫化鉛 (PbSn)、上述材料之組合或布拉格反射層（DBR)。黏結層12 可為Su8、笨并環丁烯（BCB)、過氟環丁烷（PFCB)、環氧 樹脂（Epoxy)、聚亞醯胺（η)、氧化矽(Si〇2)、氧化鈦(Ti〇2)、 © 氮化矽(SiNx)、旋塗玻璃(s〇G)、氧化銦錫(no)、氧化鎂 (MgO)、銦(In)、錫(Sn)、鋁(A1)、金(Au)、鉑(Pt)、鋅(Zn)、銀 (Ag)、鈦(Ti)、鉛(Pb)、鈀(Pd)、鍺(Ge)、銅(Cu)、鎳(Ni)、錫 化金(AuSn)、銀化銦(inAg)、金化銦(inAu)、鈹化金(AuBe)、 鍺化金(AuGe)、鋅化金(AuZn)、錫化鉛(PbSn)、銦化鈀(Pdln)、 有機黏結材料或上述材料之組合。第一半導體層13之電性與 第二半導體層15相異，活性層14可為II-VI族或III-V族材 料’例如為鱗化鋁鎵銦（AlGalnP)、氮化鋁(A1N)、氮化鎵 (GaN)、氮化鋁鎵(AlGaN)、氮化銦鎵(inGaN)、氮化鋁銦鎵 (AlInGaN)或硒化鎘鋅(CdZnSe)。高效率發光裝置1更包含一 200939548 ίΐΊϋϊ結構包含第一ι：極Α形成於第-低區域152 層11盘黏,電極B形成於基板1〇之下。基板！〇、反射 之材f以可導電為佳ϋ極A與第二 从川it基板10之相異侧’並分別與第二半導體層15與 二-呈右姆接觸。第—低區域152也可形成—圖形，例 數個向外延伸的突出部之圓形或其他形狀。第一電 有相^之第一低區域152之上，並與第一低區域152具 ο 如第1Β圖所示，另一實施例中，導電結構更包含一第一 電流阻檔層16形成於第一低區域152之上並位於第—電極Α ^下方’以阻擋電流通過，降低活性層戶斤發出之光線為第一電 極巧射或吸收之機率，以及H流舰層17形成於第 二半導體層15與第-電流阻擋層16之上，並覆蓋第一高區域 153 ’第一電極Α係位於第一電流擴散層17之上。第一電流 阻擋層16可為介電材料，例如Su8、苯并環丁烯（BCB)、過 氟環丁烷（PFCB)、環氧樹脂（Ep0Xy)、丙稀酸樹脂 Resin^)、環烯煙聚合物（c〇c )、聚甲基丙烯酸曱酯（pMMA )、 聚對苯二甲酸乙二酯（pET)、聚碳酸酯（pc)、聚醚醯亞胺 (Polyetherimide)、氟碳聚合物（Fiuorocarb〇nP〇lymer)、石夕膠 ❹ (Silicone)、玻璃(Glass)、氧化鋁(Al2〇3)、氮化矽(siNx)、氧 化梦(Si〇2)、氧化欽(Ti〇2)、絕緣材料或上述材料之組合。因為 第一電流阻擋層16之電阻較高，電流被第一電流擴散層17導 向第一尚區域153 ’然後流經活性層14以產生光線。然而電 流沒有通過活性層14位於第一電流阻擋層16下方之區域，所 以活性層14位於第一電流阻擋層16下方之區域沒有產生光 線。因此，活性層14位於第一電流阻擋層16正下方之部分所 產生之光被第一電極A吸收的機率下降。第一電流擴散層口 可將電流均勻地擴散向第二半導體層15,可為透明導電材料， 例如氧化銦錫(IT0)、氧化銦(InO)、氧化錫（SnO)、氧化鎘錫 (CT0)、氧化銻錫(ΑΤΟ)、氧化鋅(ZnO)、磷化鎵(GaP)或上述 200939548 材料之組合。 如第1C圖所示’第一高區域153可為自第一表面151向 下延伸之第一複數個六角孔穴154 ’用以增進光摘出效率。第 一尚區域153與第一低區域152之間的高度差約為丨〇〇奈米〜丄 微米，較佳為200奈米〜300奈米。第一低區域152之&面粗 縫度小於第一高區域153之表面粗糙度，更佳為接近平滑表面 之表面粗經度。此外’第二半導體層15可為氮化物半導體， 基板10可為藍寶石基板。詳細說明可參考美國專利申請案「發 光裝置」’案號11/160,354’申請曰為6/21/2005,作為本案之 參考文獻。As shown in FIG. 1A, a high-efficiency light-emitting device i is formed on the substrate 10 on the substrate 10. The point is 7 soil 'reversely. - chamber-main track ^ ^ The adhesion layer 12 is formed on the reflective layer 11 The 丄+V body layer 13 is formed on the adhesion layer 12 formed on the first semiconductor layer 13 = the smectic layer 14 , the nucleus is ... and a second semiconductor layer 15 is formed on the semiconductor layer 15 having one of the away from the active layer 14 The first ancient surface 151 has a first-lower region 152 and a second-first surface 151 is a portion of the second semiconductor layer 15 removed, and the first low region 152 of the layer 14 is And - a first high region 153 that is farther away from the active layer 14. The method of squeezing the J-lower region 152 is, for example, wet etching, dry etching mechanical polishing or induction light bonding plasma, the inverse of the first low region 152 To achieve a better reflectivity, first, the surface roughness of the region 152 is lower than the surface roughness of the first high region 153, preferably a flat surface. Because the surface of the first low region 152 has a small surface roughness, resulting in a first electrode A and a first low region 152 The critical angle of the interface is reduced, increasing the probability that the light of the germanium layer 14 to be directed toward the first low region 152 is totally reflected. The light reflected by the first low region 152 may be directed toward the first high region 153 after being reflected by the reflective layer 11. The probability of light extraction is higher. Further, the height difference from the first = high region 153 to the first low region 152 is about 100 nm to 1 μm, more preferably 200 nm to 300 nm. The first low region 152 The second half 200939548. The ratio of the surface area of the first surface 151 of the conductor layer 15 is less than 3%. In the stupid process, by light and control (four) rhyme parameters, such as gas flow rate, gas to pressure or temperature, etc. The first high region 153 is formed into a non-flat surface. A portion of the second semiconductor layer I5 may also be removed by wet etching, dry etching, or lithography to form the first -1 region I53 into a periodic, periodic-like or Arbitrary pattern. Because of the non-flat surface of the first high region 153, the light extraction efficiency of the light directed toward the first high region 153 is thus increased. The first high region 153 may also be a plurality of convex portions and/or a plurality of concave portions. The substrate ίο can be a metal matrix composite (Metal Matrix c〇mp〇site ; ❹ MMC), Ceramic Matrix Composite (CMC), bismuth (Si), structured moth (ip), 匕 zinc kiss (four), nitriding (8), shi sheng rong (GaAs), Barium carbide (SiC), gallium phosphide (GaP), gallium arsenide (GaAsP), zinc oxide (ZnO), indium linide (inp), gallium hydride clock 1iGa〇2), succinic acid clock 1 recognized) or The combination of the above materials. The reflective layer 11 may be indium (In), tin (Sn), aluminum (A1), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), Wr (Pb), (Ge), copper (Cu), nickel (10), gold (AuBe), gold (AuGe), gold (AuZn), lead (PbSn), a combination of the above materials Or Bragg reflection layer (DBR). The bonding layer 12 may be Su8, stupid cyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Epoxy), polyamidamine (η), cerium oxide (Si〇2), titanium oxide. (Ti〇2), © tantalum nitride (SiNx), spin-on glass (s〇G), indium tin oxide (no), magnesium oxide (MgO), indium (In), tin (Sn), aluminum (A1) , gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), lead (Pb), palladium (Pd), germanium (Ge), copper (Cu), nickel (Ni) , AuSn, indium, ina, gold, AuBe Palladium indium (Pdln), an organic bonding material or a combination of the above. The electrical properties of the first semiconductor layer 13 are different from those of the second semiconductor layer 15. The active layer 14 may be a II-VI or III-V material, such as squamous aluminum gallium indium (AlGalnP), aluminum nitride (A1N). GaN, GaN, AlGaN, inGaN, AlInGaN or CdZnSe. The high-efficiency illuminating device 1 further includes a 200939548 ΐΊϋϊ structure including a first ι: a crucible formed in the first-low region 152, the layer 11 is disk-bonded, and the electrode B is formed under the substrate 1〇. Substrate! The tantalum and reflective material f is electrically conductive as the opposite side of the second drain layer A and the second slave semiconductor substrate 10 and is in contact with the second semiconductor layer 15 and the second semiconductor layer, respectively. The first-lower region 152 can also be formed as a pattern, such as a circular or other shape of a plurality of outwardly extending projections. The first electrical region has a first low region 152 and is opposite to the first low region 152. As shown in FIG. 1 , in another embodiment, the conductive structure further includes a first current blocking layer 16 formed. Above the first low region 152 and below the first electrode Α ^ to block the passage of current, reducing the probability that the light emitted by the active layer is the first electrode to be shot or absorbed, and the H-stream layer 17 is formed in the first The second semiconductor layer 15 is over the first current diffusion layer 17 and covers the first high region 153'. The first current blocking layer 16 may be a dielectric material such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin (Ep0Xy), acrylic resin Resin(TM), cycloolefin Tobacco polymer (c〇c), polymethyl methacrylate (pMMA), polyethylene terephthalate (pET), polycarbonate (pc), polyetherimide (Polyetherimide), fluorocarbon polymerization (Fiuorocarb〇nP〇lymer), Silicone, Glass, Alumina (Al2〇3), Niobium Nitride (siNx), Oxidation Dream (Si〇2), Oxidation (Ti〇) 2), an insulating material or a combination of the above. Because the resistance of the first current blocking layer 16 is higher, current is conducted by the first current spreading layer 17 to the first still region 153' and then flows through the active layer 14 to generate light. However, the current does not pass through the active layer 14 in the region below the first current blocking layer 16, so that the active layer 14 is located in the region below the first current blocking layer 16 without generating light. Therefore, the probability that the light generated by the active layer 14 located at a portion directly under the first current blocking layer 16 is absorbed by the first electrode A is lowered. The first current diffusion layer can uniformly diffuse the current to the second semiconductor layer 15, and can be a transparent conductive material such as indium tin oxide (IT0), indium oxide (InO), tin oxide (SnO), or cadmium tin oxide (CT0). ), bismuth tin oxide (yttrium), zinc oxide (ZnO), gallium phosphide (GaP) or a combination of the above 200939548 materials. As shown in Fig. 1C, the first high region 153 may be a first plurality of hexagonal cavities 154' extending downward from the first surface 151 for enhancing light extraction efficiency. The height difference between the first still region 153 and the first low region 152 is about 丨〇〇 nanometer ~ 丄 micrometer, preferably 200 nanometer to 300 nanometer. The & surface roughness of the first low region 152 is less than the surface roughness of the first high region 153, and more preferably the surface roughness of the smooth surface. Further, the second semiconductor layer 15 may be a nitride semiconductor, and the substrate 10 may be a sapphire substrate. For a detailed description, reference is made to the U.S. Patent Application "Lighting Device", No. 11/160,354, filed on Jun. 6/21/2005, which is incorporated herein by reference.
如第2A圖所示，另一實施例中，一高效率發光裝置 含一基板20 ; —反射層21形成於基板20之上；一黏姓層2 形成於反射層21之上；-第-半導體層23形成於黏^ 2 之上；一活性層24形成於第一半導體層23之上；以及一 半導體層25形成於活性層24之上。第二半導體層25且有 離活性層24之一第一表面25卜其中第一表面251具^一 低區域252與一第一肉區域253。第一半導體層23且右 近活性層24之一第二表面23卜其中第二表面231具^一 二低區域232與一第二高區域233。上述第一表面251、係 部份第二半導體層25後形成一較靠近活性層24之第一低區 252 ’以及一較遠離活性層24之第一高區域2幻。上第二’ 面^31係移除部份第二半導體層23後形成一較遠離活性^ 之第-低區域232’以及-較靠近活性層24之第一高區域 形成第一低區域252與第二低區域232之方法例 蝕刻、乾韻刻、化學機械研磨法或感應耦合式電漿蝕 低區域252與第二低區域232之反射率至少 之·。為了獲得更佳的反射率，第一低區域拉與 域232之表面粗糙度分別低於第一高區域253 —古〜 说之表面粗糙度，最佳為接近一平整表面之表面= 8 200939548As shown in FIG. 2A, in another embodiment, a high-efficiency light-emitting device includes a substrate 20; a reflective layer 21 is formed on the substrate 20; a sticky layer 2 is formed on the reflective layer 21; The semiconductor layer 23 is formed on the adhesive layer 2; an active layer 24 is formed on the first semiconductor layer 23; and a semiconductor layer 25 is formed on the active layer 24. The second semiconductor layer 25 has a first surface 25 of the active layer 24, wherein the first surface 251 has a low region 252 and a first meat region 253. The first semiconductor layer 23 and the second surface 23 of the right active layer 24 have a second surface 231 having a second low region 232 and a second high region 233. The first surface 251 and the second semiconductor layer 25 are formed to form a first low region 252 ′ closer to the active layer 24 and a first high region 2 farther away from the active layer 24 . The second second surface 31 removes a portion of the second semiconductor layer 23 to form a first-lower region 232' that is further away from the active surface, and - a first high region closer to the active layer 24 to form a first low region 252 and The method of the second low region 232 is at least etched, dried, chemically polished, or inductively coupled to the low region 252 and the second low region 232. In order to obtain a better reflectance, the surface roughness of the first low region pull and the region 232 is lower than the first high region 253 - the surface roughness is preferably the surface close to a flat surface = 8 200939548
❹ 為第一低區域252與第二低區域232之表面具有較小之表面粗 糙度，導致介於一第一電極A與第一低區域252間之介面， 以及介於一第二電極B與第二低區域232間之介面的臨界角 減小’增加活性層24射向第一低區域252與第二低區域232 的光線被全反射的機率。被第一低區域252與第二低^域232 反，之光線可在被反射層21反射後射向第一高區域與第 二兩區域233 ’光摘出的機率較高。此外，自第一高區域 到第一低區域252之南度差與自第二高區域233到區域 232之而度差为別約為1〇〇奈米〜1微米，更佳為奈米〜3〇〇 奈米。第一低區域252佔第二半導體層25之第一表^251表 面積之比例低於30%，第二低區域232佔第一半導體層23之 第二表面231表面積之比例低於30%。 …在遙晶製程中藉由調整與控制製程的參數，例如氣體产 率、氣室壓力或溫度等，可使第一高區域253與第二高區^ 233形成非平整表面。也可經由濕蝕刻、乾餘刻或微影等方式 =部分第二半導體層25與第-半導體層23，使第一高區域 與第二高區域233形成一週期性、類週期性或任意 案。因為第一高區域253與第二高區域233的非平整表面， = '高區域253與第二高區域233之光線的光摘出效率因此 /一南區域253與第二高區域233也可為複數個凸部與 /或複數個Μ都。 # 向效率發光裝置2更包含一導電結構，導電結構包含$ ，極Α與第二電極Β。移除部分第一半導體層23、活性声 二第二半導體層25以裸露第二表面231，第一電極人與^ ，極B分別位於第一低區域252與第二低區域232之上: 二第一半導體層25與第-半導體層23形成歐姆接觸。j 、反射層21與黏結層22之材質以可電絕緣為佳。第一々 與第二低區域232可形成圖形，例如具有複數個向夕 申的大出部之圓形或其他形狀。第一低區域252之上之第_ 9 200939548 ，f 第一低區域252具有相同之圖形，第二低區域232 士士之第二電極B可與第二低區域232具有相同之圖形。第 、極A與第二電極b可分別依據第一低區域252盘第 區域232定義之圖案形成不同之圖案。 ”第一低 如第2B圖所示，另一實施例中，導電結構更包含一第一 電流阻播層26形成於第一低區域252之上並位於第一電極A 之下方’以阻猜電流通過，降低活性層所發出光一 極A反射纽收之機―第—錢擴散;^^彡^ -半導體層25與第-電流阻擋層26之上，其中第—電流擴散 層27覆蓋第一面區域253，第一電極A係位於第一電流擴散 層27之上。此外，導電結構更包含一第二電流阻撐層28形成 於第二低區域232之上並位於第二電極b之下方，以阻播電 流通過，降低活性層所發出之光線為第二電極B反射或吸收 之機率，以及一第二電流擴散層29形成於第一半導體層23與 第二電流阻擋層28之上’其中第二電流擴散層29覆蓋第二高 區域233 ’第二電極B係位於第二電流擴散層29之上。第一 電流阻擋層26與第二電流阻擋層28可為介電材料，例如 Su8、苯并環丁烯（BCB)、過氟環丁烷（PFCB)、環氧樹脂 (EP〇xy )、丙稀酸樹脂（Acrylic Resin )、環烯烴聚合物 ❹ （C0C)、聚曱基丙烯酸曱酯（PMMA)、聚對苯二曱馥乙二酉旨 (PET)、聚碳酸酯（pc)、聚醚醯亞胺（Polyetherimide)、氟 碳聚合物（Fluorocarbon Polymer)、矽膠（Silicone)、玻璃 (Glass)、氧化鋁(Al2〇3)、氮化矽(SiNx)、氧化矽(Si02)、氧化鈦 (Ti〇2)、絕緣材料或上述材料之組合。因為第一電流阻擔層％ 與第二電流阻擋層28之電阻較高，電流被第一電流擴散層27 與第二電流擴散層29導向第一高區域253與第二高區域233, 然後流經活性層24以產生光線。然而電流沒有通過活性層24 位於第一電流阻擋層26下方之區域，所以活性層24位於第一 電流阻措層26下方之區域沒有產生光線。因此，活性層24位 於第一電流阻擋層26正下方之部分所產生之光被第一電極a 200939548 吸收的機率下降。第一電流擴散層27與第二電流擴散層29可 將電流均勻地擴散向第二半導體層25與第一半導體層23，可 為透明導電材料，例如氧化銦錫(IT〇)、氧化銦(In〇)、氧化 錫(SnO)、氧化録錫(CTO)、氧化録錫(ΑΤ〇)、氧化鋅(Zn〇)、 填化嫁(GaP)或上述材料之組合。 ❹ ❹ 如第2C圖所示，第一高區域253與第二高區域233可分 別為自第一表面251向下延伸之第一複數個六角孔穴254與自 第二表面231向下延伸之第二複數個六角孔穴234，用以^進 光摘出，率。第一高區域253與第一低區域252之間的高^差 與第一间區域233與第二低區域232之間的高度差約為1〇〇奈 米〜1微米，較佳為200奈米〜300奈米。第一低區域2兄與^ 二低區域232之表面粗糙度分別小於第一高區域2幻與第^高 區域233之表面粗糙度’更佳為兩者皆接近平滑表面之表面g 糙度。此外，第二半導體層25與第一半導體層23可為氮化物 半導體，基板2〇可為藍寶石基板。詳細說明可參考美 發ί裝置」，案號11/16G，354,中請日為6/21/2005，❹ having a surface roughness of the surface of the first low region 252 and the second low region 232, resulting in an interface between a first electrode A and a first low region 252, and between a second electrode B and The critical angle reduction of the interface between the second low region 232 ' increases the probability that the active layer 24 will be totally reflected toward the first low region 252 and the second low region 232. Opposite to the first low region 252 and the second low region 232, the light rays are reflected by the reflective layer 21 and are incident on the first high region and the second two regions 233'. In addition, the difference between the south degree from the first high region to the first low region 252 and the difference from the second high region 233 to the region 232 is about 1 nanometer ~ 1 micrometer, more preferably nanometer ~ 3 〇〇 nano. The ratio of the first low region 252 to the surface area of the first surface 251 of the second semiconductor layer 25 is less than 30%, and the ratio of the second low region 232 to the surface area of the second surface 231 of the first semiconductor layer 23 is less than 30%. The first high region 253 and the second high region 233 may be formed into a non-flat surface by adjusting and controlling the parameters of the process, such as gas yield, chamber pressure or temperature, in the remote crystal process. The first high region and the second high region 233 may also be formed into a periodic, periodic or arbitrary case by means of wet etching, dry etching or lithography = part of the second semiconductor layer 25 and the first semiconductor layer 23. . Because of the non-flat surface of the first high region 253 and the second high region 233, the light extraction efficiency of the light of the 'high region 253 and the second high region 233//the south region 253 and the second high region 233 may also be plural Convex and / or a plurality of Μ. The energy illuminating device 2 further includes a conductive structure, and the conductive structure includes $, a pole and a second electrode. A portion of the first semiconductor layer 23 and the active acoustic second semiconductor layer 25 are removed to expose the second surface 231. The first electrode and the second electrode B are respectively located above the first low region 252 and the second low region 232: The first semiconductor layer 25 forms an ohmic contact with the first semiconductor layer 23. j, the material of the reflective layer 21 and the adhesive layer 22 are preferably electrically insulating. The first and second low regions 232 may be patterned, such as circular or other shapes having a plurality of large portions of the sunburst. The first low region 252 has the same pattern on the first low region 252, and the second low region 232 has the same pattern as the second low region 232. The first, second and second electrodes b may respectively form different patterns according to the pattern defined by the first low region 252 disk region 232. The first low is as shown in FIG. 2B. In another embodiment, the conductive structure further includes a first current blocking layer 26 formed on the first low region 252 and located below the first electrode A to block the guess. The current passes through, reducing the light emitted by the active layer, the pole-A reflection, the first-permeability diffusion, the semiconductor layer 25 and the first-current blocking layer 26, wherein the first current-diffusion layer 27 covers the first The surface region 253, the first electrode A is located above the first current diffusion layer 27. Further, the conductive structure further comprises a second current blocking layer 28 formed on the second low region 232 and below the second electrode b. Passing the current through, reducing the probability that the light emitted by the active layer is reflected or absorbed by the second electrode B, and a second current diffusion layer 29 is formed on the first semiconductor layer 23 and the second current blocking layer 28' The second current diffusion layer 29 covers the second high region 233'. The second electrode B is located above the second current diffusion layer 29. The first current blocking layer 26 and the second current blocking layer 28 may be dielectric materials such as Su8. Benzocyclobutene (BCB), perfluorocyclobutane (PFCB) Epoxy resin (EP〇xy), Acrylic resin (Acrylic Resin), cycloolefin polymer ❹ (C0C), polydecyl methacrylate (PMMA), poly(p-phenylene terephthalate) (PET) ), polycarbonate (pc), polyetherimide, fluorocarbon polymer, silicone, silica, alumina (Al2〇3), tantalum nitride (SiNx) ), cerium oxide (SiO 2 ), titanium oxide (Ti 〇 2 ), insulating material or a combination of the above materials. Since the first current blocking layer % and the second current blocking layer 28 have higher resistance, the current is diffused by the first current The layer 27 and the second current diffusion layer 29 are directed to the first high region 253 and the second high region 233, and then flow through the active layer 24 to generate light. However, the current does not pass through the active layer 24 under the first current blocking layer 26, Therefore, no light is generated in the region of the active layer 24 under the first current blocking layer 26. Therefore, the probability that the light generated by the active layer 24 located directly under the first current blocking layer 26 is absorbed by the first electrode a 200939548 is lowered. First current diffusion layer 27 and second current diffusion layer 29 The current is uniformly diffused to the second semiconductor layer 25 and the first semiconductor layer 23, and may be a transparent conductive material such as indium tin oxide (IT〇), indium oxide (In〇), tin oxide (SnO), or oxidized recording tin ( CTO), oxidized tin (ΑΤ〇), zinc oxide (Zn〇), filled with graft (GaP) or a combination of the above materials. ❹ ❹ As shown in Fig. 2C, the first high region 253 and the second high region 233 The first plurality of hexagonal holes 254 extending downward from the first surface 251 and the second plurality of hexagonal holes 234 extending downward from the second surface 231 are respectively used for light extraction. The height difference between the first high region 253 and the first low region 252 and the height difference between the first inter-region 233 and the second low region 232 are about 1 nanometer to 1 micrometer, preferably 200 nanometer. Meters ~ 300 nm. The surface roughness of the first low region 2 brother and the second low region 232 is smaller than the surface roughness of the first high region 2 and the second region 233, respectively, and both are closer to the surface g roughness of the smooth surface. Further, the second semiconductor layer 25 and the first semiconductor layer 23 may be nitride semiconductors, and the substrate 2 may be a sapphire substrate. For details, please refer to the US-made device, case number 11/16G, 354, and the date of the request is 6/21/2005.
作為本案之參考文獻D 如第3圖所示，另-實施例中，一製造高效率發 之方法包含提供-基板20 ;形成-反射層21於基板2〇上； 形成-黏結層22於反射層21上；形成一第一半導 3於 黏，22上；形成-活性層24於第一半導體層23上曰；形成 -弟二半導體層25於活性層24上，其中第二轉 ^且 有遠離活性層24之-第-表面；移除部份之第曰^ 25:活性層24與第一半導體層23以裸露第一半導 3 ^ 一第二表面231 ;粗化第一表面251與第—表 ?251 第一表面231之上，其中第一表面251包含 二表第面231包含鄰接第二低區域 之第一冋£域233,形成一弟一電流阻擋層26於第一低 11 200939548 ’與一第二電流阻擔層28於第二低區域232之 阻於屠27乂電流擴散層27於第二半導體層25與第一電流 與阻梓第二電流擴散層29於第一半導體層23 散層27H t l之上；形成一第一電極A於第一電流擴 以;— #八中第一電極入位於第一低區域252之上方； 電極B 1^二^極B於第二電流擴散層29之上’其中第二 232之上方。第一低區域252之表面 矣‘二#,同區域253之表面粗缝度，第二低區域232之 魯 ❹ 253輿第二、=二高區域233之表面粗縫度。第一高區域 區域252之間的高度差與第二高區域233與第二 iilnnii間的高度差約為⑽奈米〜1微米，較佳為200 余米〜300奈米。 湘251與第三表面231之方式包含腿刻、乾 -式’使第一高區域253與第二高區域233形成 二週期性、類週期性或任意之圖案。此外，可經由在蟲 調製程的參數，例如氣舰率、缝壓力或溫度 -矣f 一表面251與第二表面231，包含分別形成自第 = 251向下延伸之第—複數個六角孔穴254與自第二表面 231向下延伸之第二複數個六纽穴234。詳細說明可參考美 國專利申請案「發光襄置」，案號11/16〇 乂 6/21/2005，作為本案之參考文獻。 Τ月㈡马 塗佈一電感或光感薄膜於第一表面251與第二表面231之 上，再將電_或光感_膜暴露在電子束微影、雷射光 或紫外線輻射等之下’形成—預設_案。形成預設圖案之 後，形成第-低區域252於第-表面251與形成第二低區域 232於第二表面231之方法包含乾侧、濕餘刻、化學機械 磨(CMP)或感應搞合式電漿蝕刻pep)，蝕刻液包含但不限於 酸(^P〇4)或氫氧化鉀(KOH)。製程中較佳之環境溫度約為 120°C，以穩定和控制時刻速率。第一高區域253與第一低區 12 200939548 域f52之間的高度差與第二高區域233與第二低區域232之間 的尚度差約為1〇〇奈米〜丨微米，較佳為2〇〇奈米〜3〇〇奈米。 第-低區域252與第二低區域攻之表面粗糙度分別小於第一 尚區域253與第二高區域233之表面粗糙度 惟上述實施例僅為例示性說明本發明之原理及其功效， =非用於_本發明。任何熟於此項技藝之人士均可在不違 月本發明之技術顧騎神的軌下，對上述實翻進行修 改及變化。因此本㈣之權娜護範圍如後狀㈣專利範 ❹ 第1A圖係依據本發明之一實施例之剖面圖。 第1B圖係依據本發明之另—實施例之剖面圖。 第1C圖係依據本發明之又—實施例之剖面圖。 第2A圖係依據本發明之另一實施例之剖面圖。As a reference D in the present case, as shown in FIG. 3, in another embodiment, a method for manufacturing high efficiency includes providing a substrate 20; forming a reflective layer 21 on the substrate 2; forming a bonding layer 22 for reflection On the layer 21; forming a first semiconductor 3 on the adhesive layer 22; forming an active layer 24 on the first semiconductor layer 23; forming a second semiconductor layer 25 on the active layer 24, wherein the second turn There is a surface-away surface away from the active layer 24; a second portion of the removed portion 25: the active layer 24 and the first semiconductor layer 23 to expose the first semiconductor 3^ a second surface 231; the first surface 251 is roughened And the first surface 231 of the first table 251, wherein the first surface 251 comprises a second surface 231 comprising a first surface 233 adjacent to the second low region, forming a first-current barrier layer 26 at the first low 11 200939548 'with a second current blocking layer 28 in the second low region 232 blocking the current diffusion layer 27 in the second semiconductor layer 25 and the first current and the second current diffusion layer 29 in the first The semiconductor layer 23 is over the bulk 27H tl; a first electrode A is formed to be expanded by the first current; The upper region 252 of the low; an electrode B 1 ^ ^ two electrode B 'of the top 232 wherein the second current on the second diffusion layer 29. The surface of the first low region 252 is 矣 '二#, the surface of the same region 253 is rough, the second low region 232 is 鲁 253 舆 second, = the second high region 233 surface rough seam. The height difference between the first high region region 252 and the height difference between the second high region 233 and the second iilnnii are about (10) nanometers to 1 micrometer, preferably 200 to 300 nanometers. The manner of the second surface 231 of the 251 and the third surface 231 includes a leg etch, a dry pattern, such that the first high region 253 and the second high region 233 form a two-period, periodic-like or arbitrary pattern. In addition, the first plurality of hexagonal cavities 254 extending downward from the second = 251 may be formed via parameters of the insect modulation process, such as a gas ship rate, a slit pressure or a temperature - 矣f surface 251 and the second surface 231, respectively. And a second plurality of six-holes 234 extending downward from the second surface 231. For a detailed description, please refer to the US patent application "Light-emitting device", Case No. 11/16〇 乂 6/21/2005, as a reference for this case. The moon (2) is coated with an inductive or light-sensitive film on the first surface 251 and the second surface 231, and then exposes the electric_photosensitive film to electron beam lithography, laser light or ultraviolet radiation, etc. Form - default_ case. After the predetermined pattern is formed, the method of forming the first-lower region 252 on the first surface 251 and the forming the second low region 232 on the second surface 231 includes a dry side, a wet residual, a chemical mechanical grinding (CMP) or an induction bonding type. Slurry etching pep), the etching solution includes but is not limited to an acid (^P〇4) or potassium hydroxide (KOH). The preferred ambient temperature in the process is about 120 ° C to stabilize and control the rate of time. The difference between the height difference between the first high region 253 and the first low region 12 200939548 domain f52 and the difference between the second high region 233 and the second low region 232 is about 1 nanometer ~ 丨 micrometer, preferably For 2 〇〇 nano ~ 3 〇〇 nano. The surface roughness of the first low region 252 and the second low region is smaller than the surface roughness of the first region 253 and the second high region 233, respectively. However, the above embodiments are merely illustrative of the principle and efficacy of the present invention, Not used for the present invention. Anyone who is familiar with this skill can modify and change the above-mentioned real-life under the guidance of the technology of the invention. Therefore, the scope of the (4) power protection is as follows (4) Patent Specification 1A is a cross-sectional view according to an embodiment of the present invention. Figure 1B is a cross-sectional view of another embodiment in accordance with the present invention. 1C is a cross-sectional view of still another embodiment in accordance with the present invention. Figure 2A is a cross-sectional view of another embodiment of the present invention.
第2β圖係依據本發明之又—實施例之剖面圖。 第2C圖係依據本發明之又—實施例之剖面圖。 第3圖係依據本發明之又一實 ^ 造方法之製造流程圖。 例之一尚效率發光元件之製 13 200939548The second beta diagram is a cross-sectional view of a further embodiment of the invention. 2C is a cross-sectional view of still another embodiment in accordance with the present invention. Figure 3 is a manufacturing flow diagram of yet another embodiment of the present invention. One example is the system of efficient light-emitting components 13 200939548
【主要元件符號說明】 基板:10、20 反射層:11、21 黏結層:12、22 第一半導體層:13、23 活性層:14、24 第二半導體層:15、25 第一表面:151、251 第一低區域:152、252 第一高區域:153、253 第一複數個六角孔穴:154 第一電流阻擋層:16、26 第一電流擴散層:17、27 第二表面:231 第二低區域:232 第二高區域:233 第二複數個六角孔穴:234 第二電流擴散層29 第一電極:A 第二電極:B 14[Main component symbol description] Substrate: 10, 20 Reflective layer: 11, 21 Bonding layer: 12, 22 First semiconductor layer: 13, 23 Active layer: 14, 24 Second semiconductor layer: 15, 25 First surface: 151 251 First low area: 152, 252 First high area: 153, 253 The first plurality of hexagonal holes: 154 First current blocking layer: 16, 26 First current diffusion layer: 17, 27 Second surface: 231 Two low areas: 232 Second high area: 233 Second multiple hexagonal holes: 234 Second current diffusion layer 29 First electrode: A Second electrode: B 14