200933240 i219twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種顯示面板的母板及其製作方 法’且特別是有關於一種具有不同尺寸之顯示面板單元的 母板及其製作方法。 【先前技術】 液晶顯示器主要是由一液晶顯示面板(liquid cryStai display panel，LCD panel)以及一背光模組（backUght module)所構成’其中，液晶顯示面板包括彩色濾光基板、 主動元件陣列基板(active device array substrate)以及位於 兩基板之間的液晶層（liquid crystal layer)。 現行液晶顯示面板的製作是先以一整片的主動元件 陣列基板與一整片的彩色濾光基板進行組立，並將液晶層 街封於其間’進而形成具有多個面板單元的液晶顯示面板 的母板。之後’再對液晶顯示面板的母板進行切割 (cutting)’以形成多個獨立的液晶顯示面板。 液晶顯示面板的產線隨著所製作之液晶顯示面板的母 板尺寸不同’也有不同世代的演進。早期一代廠所製作的 液晶顯示面板的母板尺寸大約是300公厘χ400公厘，約可 製作一片15叶的顯示面板。到了 1996年時，技術已進步 到3.5代薇，而其所製作的液晶顯示面板的母板尺寸約為 600公厘Χ720公厘。演進至今，六代廠的液晶顯示面板的 母板尺寸已達到了 1500公厘χ1850公厘，其所製作的液晶 顯示面板的母板可切割為30片15吋的面板。與先前的一 200933240 ▲,〜219twf，doc/n 代廠或3.5代廠相較，六代廠的產能增加，相對地降低製 程成本。此外，六代廠的液晶顯示面板的母板也可以切割 為大尺寸的液晶顯示面板，例如製作8片32吋的液晶顯示 面板，或是6片37吋的液晶顯示面板。 近年來，為了符合使用者對於大尺寸顯示器的需求， 液晶顯示面板也繼續朝向更大的尺寸發展，例如4 〇吋、4 2 吋、50吋等，而液晶顯示面板的產線也演進到了七代廠與 ❹ 7.5代廠。以40吋的液晶顯示面板為例，七代廠的液晶顯 示面板的母板尺寸為1870公厘χ22〇〇公厘，而將七代廠的 液晶顯示面板的母板切割為多片的40吋面板時，母板的利 用率約為92°/(^ 相較於前幾代的產線，目前7.5代廠的液晶顯示面板 的母板尺寸為1950公厘χ2250公厘，然而，將其切割為多 片的40叶或其他尺寸的液晶顯示面板時，母板的利用率卻 不升反降’約只有85%至86%。此乃是因為上述的液晶顯 示面板尺寸無法與母板的尺寸有效匹配’使得母板上的空 ® 間無法被有效利用所導致。 【發明内容】 本發明關於一種顯示面板的母板’其可有效利用母板 上的可用空間’解決母板利用率受到限制的問題。 本發明另關於一種適於製作上述之顯示面板的母板 的方法’其可大幅改善顯示面板的母板利用率’進而提升 整體的產能。 為具體描述本發明之内容，在此提出一種顯示面板的 200933240 a __________ _J219twf.doc/n 母板，其具有一第一尺寸的第一面板單元群組與一第二尺 寸的弟一面板單元群組。第一面板單元群組中的每一第一 面板單元具有至少一第一單元間隙，而第二面板單元群組 中的母一第一面板單元具有至少一第二單元間隙，且第一 尺寸實質上不同於第二尺寸。該母板主要由一切換元件陣 列基板、一對向基板、一顯示介質層(display medium layer) 以及一襯層所構成。切換元件陣列基板具有陣列排列的多 ， 個切換元件以及對應連接切換元件的多個晝素電極。對向 基板與切換元件陣列基板實質上平行，且對向基板具有一 共用電極層。顯示介質層配置於切換元件陣列基板與對向 基板之間。此外，襯層配置於切換元件陣列基板與對向基 板之間，襯層對應於第一面板單元群組，且襯層的厚度與 第一單元間隙的總和實質上等於第二單元間隙。 在此更提出一種顯示面板的母板的製作方法，此顯示 面板的母板具有一第一尺寸的第一面板單元群組與一第二 尺寸的第一面板單元群組。第一面板單元群纟中备一 面板單元具有至少一第一單元間隙，而第二=4 組中的每一第二面板單元具有至少一第二單元間隙，且第 尺寸只質上不同於第二尺寸。此母板的製作方法包括： 製作一切換元件陣列基板，該切換元件陣列基板具有陣列 排列的多個切換元件以及對應連接切換元件的多個晝素電 極；製作一對向基板；以及形成一顯示介質層於切ς元件 陣列基板與對向基板之間。並且，在製作切換元件陣列基 板及/或對向基板時，更形成一襯層於局部的切換元件陣^ 7 200933240 ---------- »219twf.doc/n 基板或對向基板上，其中襯層對應於第一面板單元群組， 且襯層的厚度與第一單元間隙的總和實質上等於第二單元 間隙。 基於上述，本發明藉由在同一顯示面板的母板上規劃 多種不同尺寸的顯示面板單元，以有效利用母板上的可用 空間，改善顯示面板的母板利用率，進而提升整體的產能。 此外著眼於母板需整合不同尺寸的面板單元，本發明更 ⑩ 藉由襯層來補償該些不同尺寸之面板單元的單元間隙差 異’以符合每一面板單元的規格需求。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉實施例，並配合所附圖式，作詳細說明如 下。 【實施方式】 以下多個實施例所提及的母板，係指將一整片的切換 元件陣列基板與一整片的對向基板進行組立，並將顯示介 質層密封於其間’所形成之具有多個面板單元的成品。對 Ο 該母板進行切割’便可形成多個獨立的顯示面板。 該些實施例並不限定顯示面板的型態’其中隨著顯示 介質層的不同，顯示面板具有不同的作用機制。舉例而言， 顯示介質層可為液晶材料’則顯示面板稱為液晶顯示面 板，如··穿透型顯示面板、半穿透型顯示面板、反射型顯 示面板、COA顯示面板、AOC顯示面板、垂直配向型(VA) 顯示面板、水平切換型(IPS)顯示面板、多域垂直配向型 (MVA)顯示面板、扭曲向列型(TN)顯示面板、超扭曲向列 8 200933240 __________ 5219twf.doc/n 型(STN)顯示面板、圖案垂直配向型(pva)顯示面板、超級 圖案垂直配向型（S-PVA)顯示面板、先進大視角型(ASV) 顯示面板、邊緣電場切換型(FFS)顯示面板、連續焰火狀排 列型(CPA)顯示面板、軸對稱排列微胞型(ASM)顯示面板、 光學補償彎曲排列型（OCB)顯示面板、超級水平切換型 (S-IPS)顯示面板、先進超級水平切換型（AS_IPS)顯示面 板、極端邊緣電場切換型(UFFS)顯示面板、高分子穩定配 • 向型顯示面板、雙視角型(dual-view)顯示面板、三視角型 (triple-view)顯示面板、三維顯示面板(three_dimensi〇nal) 或其它型面板、或上述之組合。另外，若顯示介質層為電 激發光材料，則顯示面板稱為電激發光顯示面板，例如： 螢光電激發光顯示面板、填光電激發光顯示面板、或上述 之組合，且電激發光顯示面板的電激發光材質包含有機材 質、無機材質、或上述之組合，而電激發光材質之分子， 包含小分子、高分子或上述之組合。 下述實施例將以液晶顯示面板作為範例來進行說 ’明’然而本領域中具有通常知識者應能理解該些實施例的 設計概念仍可被合理地應用於其他類型的顯示面板中。 此外，下列實施例所指的切換元件陣列基板至少具有 陣列排列的多個切換元件以及對應連接該些切換元件的多 個晝素電極。在實際的應用上，切換元件陣列基板例如是 具有主動式的薄膜電晶體陣列的基板，對向基板例如是具 有彩色渡光層的彩色遽光基板。在其它實施例亦可使用被 動式的切換元件陣列基板。當然，切換元件陣列基板也可 200933240 __________ -219twf.doc/n 以是整合了彩色濾光層於主動層上的COA基板或是整合 了主動層於彩色滤光片上的AOC基板，此時，對向基板 上不須製作彩色濾光層。下文會分別就該些變化舉例說明。 本發明藉由在同一顯示面板的母板上規劃多種不同 尺寸的顯示面板單元’以有效利用母板上的可用空間。圖 1繪示依照本發明之一實施例的一種顯示面板之母板的上 視圖。如圖1所示，本實施例的母板100尺寸例如是75 D 代薇所採用的規格’其長寬為1950公厘X2250公厘，但不 限於此，亦可選用其它規格，如先前技術中之母板尺寸規 格。在母板100上規劃了 32吋的第一面板單元(或稱為第 —顯示面板單元)11〇的群組與52吋的第二面板單元(或稱 為第二顯示面板單元)12〇的群組，分別排列為兩直行。藉 由這樣的規劃’可以有效利用母板1〇〇上的可用空間，改 善顯示面板的母板利用率，進而提升整體的產能。 〇π 值得注意的是，上述實施例採用整合兩種尺寸之面板 ❹ 單元的設計來作說明，但本發明並不以此為限。亦即，在 其它實施例中’亦可採用其它尺寸的面板單元，如：i吋 〜1〇〇吋間的面板單元或大於1〇〇吋的面板單元。實作上， 亦可以整合更多尺寸的面板單元於同一母板上，並且調整 ，些面板單元之間的位置關係，以求得最佳化的母板利用 此外，雖然前述實施例提出了在母板上整合不同尺寸 的面板單元的設計概念，但由於既有製程中母板是藉由一 整片的切換元件陣列基板與一整片的彩色濾光基板組立而 200933240 ---------- j219twf.doc/n 成，因此在實作上，切換元件陣列基板與彩色濾光基板之 間的單元間隙無法隨不同尺寸的面板單元做彈性的調整。 特別疋’當顯不面板需有特定規格時，將受限於既有製程 而無法滿足設計上的需求。 圖2纷示由前述母板100所製得之顯示面板2〇〇的剖 面圖。如圖2所示，本實施例的顯示面板200包括切換元 件陣列基板210、對向基板220、顯示介質層230、間隙物 ❹ 240等元件。切換元件陣列基板21〇例如是由切換元件 212、共用配線214、閘絕緣層216、保護層218以及晝素 電極219等所組成來說明，而對向基板220例如是由黑矩 陣222、彩色濾光層224以及共用電極層220等所組成的 卷色滤光基板來s兒明。在其它實施例中，切換元件陣列農 板210例如是由切換元件212、閘絕緣層216、保護層218 以及晝素電極219等所組成，而對向基板220例如是由專 矩陣222以及彩色濾光層224等所組成的彩色濾光基板: 切換元件212於本實施例中，以底閘型電晶體為例，但不 〇 限於此，亦可使用頂閘型、或其它適合之電晶體、或上述 之組合。而電晶體之半導體層為單層或多層結構，且其^ 質包含非晶石夕、多晶石夕、單晶石夕、微晶石夕、上述晶格之矽 化鍺、或其它適合之半導體材質、或上述之組合。在本實 施例中，單元間隙250係指切換元件陣列基板21〇與對向 基板220之間的距離，更詳細而言，單元間隙係指切 換元件陣列基板210的晝素電極219與對向基板22〇 ^共 用電極層226之間的距離。易言之，單元間隙25〇係指切 11 200933240 _219twf.doc/n ^件陣列基板21G的畫素電極2i9接近顯示介質现之 =計算起點與對向基板220的共用電極層226接近顯 之表面來為計算起點而所得到的二者之間的距 福i關社絲亦會依各基板原所存在的晝素電 m o 而_ Li f電極層226上是否有另—膜層(未顯示)存在 動之，例如：以另一膜層(未繪示)接近顯示 ;一丨133〇之表面來為計算起點或仍以晝素電極训接近顯 =質330之表面為起點或共用電極層挪接近顯示介質 面為起點。此時’依光學影響效果或輯公式而 1术心略另一膜層（未緣示）或不忽略另一膜層（未繪 Γ)^然’另一膜層的選用依設計之需要而定。舉例而言， =有一配向膜(未顯示)分別於各基板之晝素電極219及於 =電極層226上，則單元間隙25〇係指切換元件陣列基 上的配向膜(未顯示)與對向基板22〇上的配向膜(未 的距離L在其它實施例中，若對向基板不具有共 斑科^ 322時單兀間隙250係指切換元件陣列基板210 $向基板220之間的距離，更詳細而言，單元間隙25〇 2川曰切換疋件陣列基板210的晝素電極219與對向基板 (未顯ί β存在另一膜層 :”)及k用方式’亦如前述之規則。基於與前述相同 由於採用:整片的切換元件陣列基板與-整片的 光基板’並經由相同的製程步驟來製作因此圖2 ^不的顯示面板綱的剖面圖可代表母板100上，以32 呀為例的第-面板單元11〇與以％对為例的第二面板單元 12 200933240 〜…叫〜」219twf-doc/n 120 ^局部剖面結構。換言之，第一面板單元⑽與第二 面板單it 12G都會具有單元間隙25()，而無法因應面板單 ^尺寸差異而導致各單元_之計算起點或計算終點的 差八所形成的不同大小的單元間隙。 ^於此’本發明更進一步對該些不同尺寸之面板單 兀的單7L間隙差異進行簡，以更佳地實現上述整合不同 尺寸之顯示面板於同一母板上的設計概念。 ^為了對不同尺寸之面板單元的單元間隙差異進行補 仏’本發明可在製作切換元件陣列基板或對向基板的同時 形成襯層於切換元件陣列基㈣對向基板的特定區域上， 以在切換元件陣列基板與對向基板組立之後，形成不同大 小的單元間隙。 圖3繪示依照本發明之另一實施例的一種顯示面板之 母板的結構圖。為了便於了解，本實施例同樣採用如圖丄 所緣示之具有兩種尺寸之面板單元的佈局來進行說明，即 母板300例如具有第一尺寸的第一面板單元3〇〇A的群組 與第二尺寸的第二面板單元3〇〇B的群組，且第一尺寸實 質上不同於第二尺寸。在本實施例中，第一尺寸實質上小 於第二尺寸。然而’在其它實施例中’兩者的尺寸大小關 係亦可互換。此外’各第一面板單元3〇〇A及各第二面板 單元300B皆具有顯示區（未標示)及相鄰顯示區之周邊電 路區（未標示）。 如圖3所示，母板3〇〇主要包括切換元件陣列基板 310、對向基板320、顯示介質層330以及襯層340。切換 13 200933240 219twf.doc/n200933240 i219twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a motherboard for a display panel and a method of fabricating the same, and in particular to a motherboard having display panel units of different sizes And its production method. [Prior Art] The liquid crystal display is mainly composed of a liquid cryStai display panel (LCD panel) and a backUght module. The liquid crystal display panel includes a color filter substrate and an active device array substrate ( An active device array substrate) and a liquid crystal layer between the two substrates. The current liquid crystal display panel is formed by forming a whole piece of active device array substrate and a whole color filter substrate, and sealing the liquid crystal layer therebetween to form a liquid crystal display panel having a plurality of panel units. motherboard. Thereafter, the mother board of the liquid crystal display panel is 'cutted' to form a plurality of independent liquid crystal display panels. The production line of the liquid crystal display panel has evolved in different generations depending on the size of the mother board of the liquid crystal display panel produced. The size of the mother panel of the LCD panel produced by the early generation was about 300 mm to 400 mm, which made it possible to make a 15-leaf display panel. By 1996, the technology had progressed to 3.5 generations, and the size of the mother panel of the liquid crystal display panel was about 600 mm Χ 720 mm. Up to now, the mother panel size of the liquid crystal display panel of the six generations has reached 1500 mm χ 1850 mm, and the mother board of the liquid crystal display panel can be cut into 30 15 吋 panels. Compared with the previous 200933240 ▲, ~219twf, doc/n or 3.5-generation plants, the capacity of the six-generation plant increased, which relatively reduced the cost of the process. In addition, the mother board of the liquid crystal display panel of the sixth generation factory can also be cut into a large-sized liquid crystal display panel, for example, eight 32-inch liquid crystal display panels or six 37-inch liquid crystal display panels. In recent years, in order to meet the user's demand for large-size displays, liquid crystal display panels have continued to move toward larger sizes, such as 4 〇吋, 4 2 吋, 50 吋, etc., and the production line of liquid crystal display panels has also evolved to seven. Foundry and 7.5 7.5 generation factory. Taking a 40-inch liquid crystal display panel as an example, the mother panel size of the liquid crystal display panel of the 7th generation factory is 1870 mm χ 22 〇〇 mm, and the mother board of the liquid crystal display panel of the 7th generation factory is cut into 40 pieces of multiple pieces. When the panel is used, the utilization rate of the motherboard is about 92°/(^ compared to the previous generations. The current 7.5-generation LCD panel has a mother board size of 1950 mm χ 2250 mm, however, it is cut into When a multi-chip 40-leaf or other size liquid crystal display panel is used, the utilization rate of the mother board is not increased by about 85% to 86%. This is because the above-mentioned liquid crystal display panel size cannot be effectively matched with the size of the mother board. The matching 'causes the empty space between the motherboards to be effectively utilized. [Invention] The present invention relates to a motherboard of a display panel that can effectively utilize the available space on the motherboard to solve the problem that the utilization of the motherboard is limited. The present invention further relates to a method for fabricating a mother board of the above display panel, which can greatly improve the mother board utilization of the display panel, thereby improving the overall productivity. To specifically describe the contents of the present invention, a The 200933240 a __________ _J219twf.doc/n motherboard of the display panel has a first panel unit group of a first size and a second panel unit group of the second size. Each of the first panel unit groups The first panel unit has at least one first cell gap, and the parent-first panel unit in the second panel unit group has at least one second cell gap, and the first size is substantially different from the second size. Mainly composed of a switching element array substrate, a pair of substrates, a display medium layer and a lining layer. The switching element array substrate has a plurality of array elements, a plurality of switching elements and a plurality of corresponding switching elements. The polarizing electrode is substantially parallel to the switching element array substrate, and has a common electrode layer on the opposite substrate. The display medium layer is disposed between the switching element array substrate and the opposite substrate. Further, the lining layer is disposed on the switching element Between the array substrate and the opposite substrate, the lining layer corresponds to the first panel unit group, and the thickness of the lining layer and the sum of the first unit gaps are substantially The second cell gap is equal to the second cell gap. The motherboard of the display panel has a first panel unit group of a first size and a first panel unit group of a second size. The first panel unit group has a panel unit having at least one first cell gap, and each of the second panel groups has at least one second cell gap, and the first size is qualitatively different. The manufacturing method of the motherboard includes: fabricating a switching element array substrate having a plurality of switching elements arranged in an array and a plurality of pixel electrodes corresponding to the switching elements; and forming a pair of substrates; And forming a display medium layer between the switching element array substrate and the opposite substrate. Further, when the switching element array substrate and/or the opposite substrate are fabricated, a lining layer is locally formed on the switching element array. --------- »219twf.doc/n on the substrate or on the opposite substrate, wherein the liner corresponds to the first panel unit group, and the thickness of the liner and the sum of the gaps of the first unit The second unit is equal to the gap. Based on the above, the present invention can effectively utilize the available space on the motherboard by using a plurality of display panel units of different sizes on the motherboard of the same display panel, thereby improving the utilization rate of the motherboard of the display panel, thereby improving the overall productivity. In addition, focusing on the motherboard to integrate panel units of different sizes, the present invention further compensates for the difference in cell gaps of the panel units of different sizes by the lining to meet the specification requirements of each panel unit. The above and other objects, features and advantages of the present invention will become more <RTIgt; [Embodiment] The motherboard referred to in the following embodiments refers to a whole piece of the switching element array substrate and a whole piece of the opposite substrate, and the display medium layer is sealed therebetween. A finished product with multiple panel units. A plurality of independent display panels can be formed by cutting the mother board. These embodiments do not limit the type of display panel 'where the display panel has a different mechanism of action depending on the display medium layer. For example, the display medium layer can be a liquid crystal material. The display panel is called a liquid crystal display panel, such as a transmissive display panel, a transflective display panel, a reflective display panel, a COA display panel, an AOC display panel, Vertical alignment type (VA) display panel, horizontal switching type (IPS) display panel, multi-domain vertical alignment type (MVA) display panel, twisted nematic (TN) display panel, super twisted nematic 8 200933240 __________ 5219twf.doc/ N-type (STN) display panel, pattern vertical alignment type (pva) display panel, super pattern vertical alignment type (S-PVA) display panel, advanced large viewing angle (ASV) display panel, edge electric field switching type (FFS) display panel Continuous flame-like arrangement (CPA) display panel, axisymmetric array microcell type (ASM) display panel, optical compensation curved alignment type (OCB) display panel, super horizontal switching type (S-IPS) display panel, advanced super level Switching type (AS_IPS) display panel, extreme edge electric field switching type (UFFS) display panel, polymer stable matching type display panel, dual view type (dual-view) display panel, triple view type (triple-view A display panel, a three-dimensional display panel (three_dimensi〇nal) or other type of panel, or a combination thereof. In addition, if the display medium layer is an electroluminescent material, the display panel is referred to as an electroluminescent display panel, such as: a fluorescent photoelectric excitation light display panel, a filled photoelectric excitation light display panel, or a combination thereof, and an electroluminescent display panel The electroluminescent material comprises an organic material, an inorganic material, or a combination thereof, and the molecule of the electroluminescent material comprises a small molecule, a polymer or a combination thereof. The following embodiments will be described with the liquid crystal display panel as an example. However, those of ordinary skill in the art should understand that the design concepts of the embodiments can be reasonably applied to other types of display panels. Furthermore, the switching element array substrate referred to in the following embodiments has at least a plurality of switching elements arranged in an array and a plurality of pixel electrodes corresponding to the switching elements. In practical applications, the switching element array substrate is, for example, a substrate having an active thin film transistor array, and the opposite substrate is, for example, a color light-emitting substrate having a color light-emitting layer. An alternate switching element array substrate can also be used in other embodiments. Of course, the switching element array substrate can also be 200933240 __________ -219twf.doc/n to integrate the color filter layer on the active layer of the COA substrate or the active layer on the color filter on the AOC substrate. A color filter layer is not required to be formed on the opposite substrate. Examples of these changes are given below. The present invention effectively utilizes the available space on the motherboard by planning a plurality of display panel units of different sizes on the motherboard of the same display panel. 1 is a top view of a motherboard of a display panel in accordance with an embodiment of the present invention. As shown in FIG. 1 , the size of the motherboard 100 of the present embodiment is, for example, 75 D. The dimension used is '1950 mm×2250 mm, but is not limited thereto, and other specifications may be selected, such as the prior art. Mother board size specifications. A 32-inch first panel unit (or referred to as a first display panel unit) 11〇 group and a 52-inch second panel unit (or referred to as a second display panel unit) 12〇 are planned on the motherboard 100. Groups are arranged in two straight rows. With such a plan, the available space on the motherboard can be effectively utilized to improve the utilization of the motherboard of the display panel, thereby increasing the overall production capacity. 〇π It is worth noting that the above embodiment is described with the design of a panel unit integrating two sizes, but the invention is not limited thereto. That is, in other embodiments, panel units of other sizes may be employed, such as panel units between i吋 and 1〇〇吋 or panel units larger than 1 inch. In practice, it is also possible to integrate more sized panel units on the same motherboard and adjust the positional relationship between the panel units to optimize the use of the motherboard. In addition, although the foregoing embodiments have The design concept of integrating different size panel units on the motherboard, but since the motherboard in the existing process is assembled by a whole piece of switching element array substrate and a whole piece of color filter substrate, 200933240 ------ ---- j219twf.doc / n into, so in practice, the cell gap between the switching element array substrate and the color filter substrate can not be flexibly adjusted with different size panel units. In particular, when a panel is specified to have a specific specification, it will be limited to the existing process and cannot meet the design requirements. Fig. 2 is a cross-sectional view showing the display panel 2A made of the above-described mother board 100. As shown in FIG. 2, the display panel 200 of the present embodiment includes elements such as a switching element array substrate 210, a counter substrate 220, a display medium layer 230, and an interstitial spacer 240. The switching element array substrate 21 is, for example, composed of a switching element 212, a common wiring 214, a gate insulating layer 216, a protective layer 218, a halogen electrode 219, and the like, and the opposite substrate 220 is, for example, a black matrix 222, a color filter. The color filter substrate composed of the optical layer 224 and the common electrode layer 220 is clarified. In other embodiments, the switching element array agricultural board 210 is composed of, for example, a switching element 212, a gate insulating layer 216, a protective layer 218, and a halogen electrode 219, and the opposite substrate 220 is, for example, a dedicated matrix 222 and a color filter. The color filter substrate composed of the light layer 224 or the like: the switching element 212 is exemplified by the bottom gate type transistor in the embodiment, but is not limited thereto, and a top gate type or other suitable transistor may be used. Or a combination of the above. The semiconductor layer of the transistor is a single layer or a multi-layer structure, and the material thereof comprises amorphous stellite, polycrystalline slab, single crystal slab, microcrystalline slab, the above crystal lattice, or other suitable semiconductor. Material, or a combination of the above. In the present embodiment, the cell gap 250 refers to the distance between the switching element array substrate 21A and the opposite substrate 220. In more detail, the cell gap refers to the pixel electrode 219 and the opposite substrate of the switching element array substrate 210. 22〇^ the distance between the common electrode layers 226. In other words, the cell gap 25 〇 指 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 2009 = = = = = = = = = The distance between the two obtained for the calculation of the starting point is also based on the elemental electric mo which exists in each substrate, and whether there is another layer on the electrode layer 226 (not shown). Existence, for example: close to the display with another film layer (not shown); a surface of 丨133丨 is used as the starting point for calculation or is still near the surface of the display device or the common electrode layer Close to the display media surface as the starting point. At this time, according to the optical influence effect or the formula, the technique is slightly different from another layer (not shown) or the other layer is not ignored (the other layer is not selected). set. For example, if there is an alignment film (not shown) on the pixel electrode 219 and the electrode layer 226 of each substrate, the cell gap 25〇 refers to the alignment film (not shown) and the pair on the switching element array substrate. The alignment film on the substrate 22 (the distance L is not in other embodiments, if the opposite substrate does not have the common plaque 322), the single-turn gap 250 refers to the distance between the switching element array substrate 210 and the substrate 220. More specifically, the cell gap 25〇2曰 switches the elementary electrode 219 of the element array substrate 210 and the opposite substrate (the other film layer is not present): and the method of k is also as described above. The rule is based on the same as the foregoing, since the entire switching element array substrate and the entire optical substrate are used and manufactured through the same process steps, so that the cross-sectional view of the display panel can be represented on the motherboard 100. The first panel unit 11〇, which is exemplified by 32, is the second panel unit 12, which is exemplified by the % pair, 200933240~...called ~"219twf-doc/n 120^ partial section structure. In other words, the first panel unit (10) and The second panel single it 12G will have a cell gap of 25 (), and no Different sizes of cell gaps formed by the difference between the calculation start point or the calculation end point of each unit_ according to the difference in panel size. ^ This invention further separates the single 7L gap of the panel of the different sizes. The difference is simplified to better realize the above-mentioned design concept of integrating display panels of different sizes on the same motherboard. ^ In order to complement the cell gap difference of panel units of different sizes, the present invention can be used to fabricate a switching element array substrate. Or forming a lining layer on the specific area of the opposite substrate of the switching element array base (4) to form a cell gap of different sizes after the switching element array substrate and the opposite substrate are assembled. FIG. 3 illustrates the invention according to the present invention. A structural diagram of a mother board of a display panel according to another embodiment of the present invention. For ease of understanding, the present embodiment is also illustrated by using a layout of panel units having two sizes as shown in the figure, that is, the motherboard 300 is, for example, a group of a first panel unit 3〇〇A having a first size and a second panel unit 3〇〇B of a second size, and first The inch is substantially different from the second size. In this embodiment, the first size is substantially smaller than the second size. However, 'in other embodiments, the size relationship of the two may be interchanged. In addition, 'the first panel unit 3A and each of the second panel units 300B have a display area (not shown) and a peripheral circuit area (not labeled) of the adjacent display area. As shown in FIG. 3, the motherboard 3A mainly includes a switching element array substrate. 310, the opposite substrate 320, the display medium layer 330, and the liner layer 340. Switching 13 200933240 219twf.doc/n
元件陣列基板310具有陣列排列的多個切換元件312以及 對應連接切換元件的多個晝素電極314。此外，對向基板 320與切換元件陣列基板31〇實質上平行，且對向基板32〇 具有共用電極層322為例，但不限於此，亦可不包含共用 電極層322。在製程上，本實施例例如是分別製作切換元 件陣列基板310與對向基板320,將切換元件陣列基板31〇 與對向基板320進行組立，並將顯示介質層33〇密封於其 間，以形成具有第一面板單元3〇〇a與第二面板單元3〇〇B 的母板300。當然，在完成該些製成之後，還需對母板3〇〇 進行切割，使該些第一面板單元3〇〇A與第二面板單元 300B成為獨立的顯示面板。 在本實施例中，切換元件陣列基板31〇例如是採用薄 膜電晶體作為切換元件312的薄膜電晶體陣列基板，而對 向基板320例如是彩色遽光基板，其上更具有黑矩陣似 與彩色滤光層326等元件。顯示介質層獨配置於切換元 件陣列基板310與對向基板32〇之間，本實施例之顯示介 質層330例如是液晶層或上述其他可能之材料層。 承上述，襯層340配置於切換元件陣列基板31〇與對 向基板320之間的特定區域上，例如對應於第一面 使得第—面板單元3嶋具有第—單元間隙 /概層340對應於第二面板單元誦的群 3:5夕太第—面板單元3〇〇B具有第二單元間隙 觸由在第—面板單元觀㈣置概層 ’而不在第二面板單元3咖内配置襯層34〇，以形成The element array substrate 310 has a plurality of switching elements 312 arranged in an array and a plurality of halogen electrodes 314 corresponding to the switching elements. Further, the counter substrate 320 is substantially parallel to the switching element array substrate 31, and the counter substrate 32 has the common electrode layer 322. However, the present invention is not limited thereto, and the common electrode layer 322 may not be included. In the process, in this embodiment, for example, the switching element array substrate 310 and the opposite substrate 320 are respectively formed, the switching element array substrate 31 and the opposite substrate 320 are assembled, and the display medium layer 33 is sealed therebetween to form A mother board 300 having a first panel unit 3A and a second panel unit 3A. Of course, after the fabrication is completed, the mother board 3A is also cut so that the first panel unit 3A and the second panel unit 300B become independent display panels. In the present embodiment, the switching element array substrate 31 is, for example, a thin film transistor array substrate using a thin film transistor as the switching element 312, and the opposite substrate 320 is, for example, a color light-emitting substrate having a black matrix and color thereon. Filter layer 326 and other components. The display medium layer is disposed between the switching element array substrate 310 and the opposite substrate 32A. The display medium layer 330 of the present embodiment is, for example, a liquid crystal layer or the other possible material layers. In the above, the lining layer 340 is disposed on a specific region between the switching element array substrate 31 〇 and the opposite substrate 320, for example, corresponding to the first surface such that the first panel unit 3 嶋 has the first cell gap/profile 340 corresponding to Group 3 of the second panel unit :: 5 太 第 — 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板 面板34〇 to form
本實施例’較佳地，係將襯層340製作於對向基板320 上。舉例而言，使襯層34〇位於顯示介質層33〇與對向基 板320之間。更詳細而言，本實施例先形成襯層340，再 形成共用電極層322，以使第—面板單元·Α的共用電極 層322 2蓋襯層340，而位於襯層34〇與顯示介質層33〇 之間。當然，在其他實施例中，例如：先形成共用電極層 322再形成襯層34〇 ’使襯層綱配置於共用電極層3D 上在另一實施例中，形成襯層340可形成於下列至少一 種位置上，如對向基板320與彩色濾光層326以及黑矩陣 200933240 ---------- 2\9twldoc/n 不同大小的第-單元間隙35()A與第二單元間隙3。因 而，較佳地’讓母板上的第—面板單元細A之對向 320外表面與第-面板單元3讎之對向基板32〇外表^實 質亡呈水平面。換言之’本實施例之襯層34〇的厚度與第 -單元間隙35GA的總和實質上等於第二單^間隙35〇β。 ，者’第-單兀間隙35GA及第二單元間隙35GB皆是位於 第-面板單元3·之顯㈣（未標*)及第二面板單元 300B之顯不區(未標不)來定義之。此外，襯層鳩為單層 f層結構，且其材質可為無機材質，如氧化碎、氮化石夕、 氮氧化發、碳切、氧化給、氧倾、或其它材f、或上 述之無機材質的組合；有機㈣，如雜、色阻、苯並環 丁稀(enZocyclobutane，BCB)、環烯類、聚酿亞胺類、聚醯 麵、聚_、聚賴、聚環氧乙絲、聚苯類、樹脂類、 1趟1^員類、或其它材料、或上述之有機材質的組合； 甚或是上述之無機材質與有機材質的組合。 15 200933240 219twf.doc/n 324之間、對向基板320與彩色濾光層326之間以及黑矩 陣324之上、或是對向基板320與黑矩陣324之間以及彩 色遽光層326之上、或其它膜層位置、上述之組合，以使 得襯層340位於對向基板320與顯示介質層330之間。易 a之’襯層340位於某一膜層（例如：共用電極層322)之上 及/或之下。此外，本實施例以黑矩陣324及共用電極層 322為例’則黑矩陣324被共用電極層322所覆蓋，但不 限於此，亦可位於共用電極層322上。 另一方面，在其它實施例中，也可以改為將襯層340 製作於切換元件陣列基板310的局部區域上，使其對應於 特定尺寸的面板單元。例如，先形成襯層34〇，再形成晝 素電極314 ’或是先形成晝素電極314，再於其上形成襯層 340 ’或是，先形成襯層340於閘絕緣層216形成之前，或 是先形成襯層340於閘絕緣層216與保護層218之間，或 或其它膜層位置、上述之組合，以使襯層34〇位於第一面 板單元300A的晝素電極340之上及/或之下。基於前述的 說明，這樣的設計同樣能達到形成不同之單元間隙35〇a 與350B的效果。 本實施例的襯層340為單層或多層結構，且其材質例 如是光阻或是上述其他材質。以光阻材質的襯層34〇為 例，則开>成襯層340的方法例如是藉由塗佈乾膜光阻於局 部的切換元件陣列基板310及/或對向基板32〇上。如圖\ 即是繪示一種藉由多排式乾膜光阻塗佈機台4〇〇塗佈乾膜 光阻410於基板420上的製程，此為較佳模式，但不限於 16 200933240 5219twf.doc/n 此’亦可使用單排式機台。應用該製程，可以直接在切換 ^件陣列基板310及/或對向基板32〇的局部區域上形成襯 曰34〇。當,然’本實施例也可以採用傳統的微影製程，包 括進行光阻塗佈、曝光、顯影等步驟來形成襯層34〇，或 是印刷製程、魅製程、或其它合適製程、或上述之組合。 此外’本實施例之切換元件陣列基板別及/或是對向基板 3如上的其他膜層也可以採_似的乾佈、或是微影 襄程、或是印㈣程、喷墨製程、或其它合適製程、或上 述之組合來製作，此處不再逐一贅述。 5月再參考圖3 ’本實施例的對向基板32〇具有黑矩陣 324，且黑矩p車324例如是對應於切換元件陣列基板則 ⑩ ΐΪί屬/案’如城科312或相關配線(如掃描線及資 枓線等）等。當然’參照其它現有製程，本發明也可以選擇 將黑矩陣製作於切換元㈣縣板上’且黑轉可以位於 切換凡件之上或之下。亦即，先製作黑矩卩車，再製作切換 7G件於其上；或是’先製作切換元件，再製作黑矩陣於其 上。此部分應為本領域的技術依據财技術所能理ς ί斜再贅述。另外’為了維持切減件陣列基板310 與對向基板320之間的距離，本實施例更在切換元件陣列 基板310與對向基板32〇之間配置多個間隙物⑽。該些 間隙物360的型態包含光間隙物、球間隙物、或其它間隙 物、或上述之組合’而間隙物綱的位置可對應黑矩陣似 與切換兀件陣列基板31Q上的金屬圖案配置以減少開口 率的損失。同樣地，參照現有的製程技術，除了本實施例 17 200933240In this embodiment, the liner layer 340 is preferably formed on the opposite substrate 320. For example, the liner 34 is positioned between the display medium layer 33A and the opposing substrate 320. In more detail, in this embodiment, the liner layer 340 is formed first, and then the common electrode layer 322 is formed so that the common electrode layer 322 2 of the first panel unit is covered with the liner layer 340, and is located on the liner layer 34 and the display medium layer. Between 33 。. Of course, in other embodiments, for example, the common electrode layer 322 is formed first and then the liner layer 34 is formed to configure the liner layer on the common electrode layer 3D. In another embodiment, the liner layer 340 may be formed in at least the following A position, such as the opposite substrate 320 and the color filter layer 326 and the black matrix 200933240 ---------- 2\9twldoc/n different size of the first cell gap 35 () A and the second cell gap 3. Therefore, it is preferable to let the outer surface of the opposite surface of the first panel unit A of the mother panel and the opposite substrate 32 of the first panel unit 3 be in a horizontal plane. In other words, the sum of the thickness of the lining 34 本 of the present embodiment and the first-cell gap 35GA is substantially equal to the second single gap 35 〇 β. , the 'first-single gap 35GA and the second unit gap 35GB are all defined in the display panel of the first panel unit 3 (four) (not marked *) and the second panel unit 300B (not marked) . In addition, the lining layer is a single-layer f-layer structure, and the material thereof may be an inorganic material, such as oxidized ash, nitriding stone, oxynitride, carbon cutting, oxidizing, oxygen tilting, or other materials f, or the above-mentioned inorganic Combination of materials; organic (four), such as impurities, color resistance, benzocyclobutane (BC), cycloolefins, polyaniline, polythene, poly-, poly-, polyethylene oxide, Polyphenylene, resin, 1趟1^, or other materials, or a combination of the above organic materials; or even a combination of the above inorganic materials and organic materials. 15 200933240 219twf.doc/n 324, between the opposite substrate 320 and the color filter layer 326 and above the black matrix 324, or between the opposite substrate 320 and the black matrix 324 and above the color phosphor layer 326 Or other film locations, combinations of the above, such that the liner 340 is between the opposing substrate 320 and the display dielectric layer 330. The lining layer 340 is located above and/or below a certain film layer (e.g., the common electrode layer 322). Further, in the present embodiment, the black matrix 324 and the common electrode layer 322 are taken as an example. The black matrix 324 is covered by the common electrode layer 322. However, the present invention is not limited thereto and may be located on the common electrode layer 322. On the other hand, in other embodiments, the liner layer 340 may be formed on a partial area of the switching element array substrate 310 so as to correspond to a panel unit of a specific size. For example, the liner 34 is formed first, then the halogen electrode 314 ' is formed or the halogen electrode 314 is formed first, and then the liner 340 ' is formed thereon. Alternatively, the liner layer 340 is formed before the gate insulating layer 216 is formed. Or forming a liner layer 340 between the gate insulating layer 216 and the protective layer 218, or other film layer locations, in combination with the above, such that the liner layer 34 is positioned over the pixel electrode 340 of the first panel unit 300A and / or below. Based on the foregoing description, such a design can also achieve the effect of forming different cell gaps 35a and 350B. The lining layer 340 of this embodiment has a single layer or a multilayer structure, and its material is, for example, a photoresist or the other materials described above. For example, the photoresist layer lining 34 , is formed by, for example, applying a dry film photoresist to the local switching element array substrate 310 and/or the counter substrate 32. FIG. 1 is a process for coating a dry film photoresist 410 on a substrate 420 by a multi-row dry film photoresist coater 4, which is a preferred mode, but is not limited to 16 200933240 5219twf .doc/n This 'can also use a single row machine. By applying this process, the liner 34 can be formed directly on the partial region of the switching array substrate 310 and/or the counter substrate 32A. When, however, the present embodiment may also employ a conventional lithography process, including photoresist coating, exposure, development, etc. to form the liner 34, or a printing process, a process, or other suitable process, or the above The combination. In addition, the switching element array substrate of the present embodiment and/or the other film layers of the opposite substrate 3 may be similar to a dry cloth, or a lithography process, or a printing process, an inkjet process, or Or other suitable processes, or combinations of the above, are not described here. Referring again to FIG. 3 in FIG. 3, the opposite substrate 32 of the present embodiment has a black matrix 324, and the black moment p car 324 is, for example, corresponding to the switching element array substrate, such as the city 312 or related wiring (such as the city 312 or related wiring ( Such as scanning lines and asset lines, etc.). Of course, with reference to other existing processes, the present invention may also choose to make the black matrix on the switching element (four) county board' and the black turn may be above or below the switching element. That is, first make a black moment brake, and then make a switch 7G on it; or 'make a switching element first, and then make a black matrix on it. This part should be explained in the technical and financial aspects of this field. Further, in order to maintain the distance between the cut-off element array substrate 310 and the counter substrate 320, the present embodiment further arranges a plurality of spacers (10) between the switching element array substrate 310 and the counter substrate 32A. The shape of the spacers 360 includes a light spacer, a ball spacer, or other spacers, or a combination thereof. The position of the spacers may correspond to the black matrix-like and metal pattern configuration on the switching element array substrate 31Q. To reduce the loss of aperture ratio. Similarly, referring to the existing process technology, in addition to this embodiment 17 200933240
Gl9twf.d〇c/n =置方式之外’本發明也可以藉由不同顏色的彩色渡光 曰直接堆疊形成所需的黑矩陣與_物，此處不再逐一資 述。 圖5纷不依照本發明之又一實施例的-麵示面板之 母板的結湘。為了便於了解，本實施烟樣採用如圖1 所繪示之具有^種尺寸之面板單元的佈局來進行說明即 母板漏例如具有第一尺寸的第一面板單元5〇〇A的群組 與第二尺寸的第二面板單元500B的群組，且第一尺寸實 質上不同於第二尺寸。在本實施例中第一尺寸實質上小 於第二尺寸。然而，在其它實施例中，兩者的尺寸大小關 係亦可互換。此外，各第一面板單元5〇〇A及各第二面板 單元500B皆具有顯示區（未標示)及相鄰顯示區之周邊電 路區(未標示）。 如圖5所示，母板500主要包括切換元件陣列基板 510、對向基板520、顯示介質層530以及襯層540。切換 元件陣列基板510具有陣列排列的多個切換元件512以及 對應連接切換元件的多個晝素電極514。此外，對向基板 520與切換元件陣列基板51〇實質上平行。在製程上，本 實施例例如是分別製作切換元件陣列基板51〇與對向基板 520，將切換元件陣列基板51〇與對向基板52〇進行組立， 並將顯示介質層530密封於其間，以形成具有第一面板單 元500A與第二面板單元500B的母板500。本實施例，以 對向基板520具有共用電極層522為範例，但不限於此， 亦可不具共用電極層522。當然，在完成該些製成之後， 18 200933240 >219twf.doc/n 還需對母板500進行切割，使該些第一面板單元5〇〇A與 第二面板單元500B成為獨立的顯示面板。 在本實施例中，切換元件陣列基板510例如是c〇A 基板，其可採用薄膜電晶體作為切換元件512，且整合了 彩色滤光層516於切換元件512上方。其中，電晶體之矣士 構及其半導體層材質’其可採用圖2所描述之。此外，對 向基板520除了共用電極層522之外，還具有黑矩陣524 _ 等元件。顯示介質層530配置於切換元件陣列基板51〇與 對向基板520之間，本實施例之顯示介質層53〇例如是液 晶層或前述其他可能之材料層。 同樣地’本實施例將襯層540配置於切換元件陣列基 板510與對向基板520之間的特定區域上，例如對應於第 一面板單元500A的群組’使得第一面板單元5〇〇A具有第 一單元間隙550A。相對地，襯層540對應於第二面&單元 500B的群組之外，使得第二面板單元5〇〇B具有第二單元 卩3隙55GB。本實施例藉由在第—面板單元·A内配置概 ® 層540 ’而不在第二面板單元·B内配置襯層54〇，以形 成不同大小的第一單元間隙550A與第二單元間隙55〇B。 因而，較佳地，讓母板上的第一面板單元5〇〇A之對向基 板520外表面與第一面板單元5〇〇B之對向基板52〇外^ 面實質上呈水平面。換言之，襯層54〇的厚度與第一單元 間隙5/0A的總和實質上等於第二單元間隙55〇B。再者， 第二單元間隙550A及第二單元間隙55〇B皆是位於第—面 板單元500A之顯示區(未標示)及第二面板單元漏B之顯 200933240 _219twf.doc/n 示區（未標示)來定義之。此外，襯層54〇為單層或多層結 構，且其材質可為無機材質，如氧化石夕、氮化石夕、氮氧化 石夕、碳化石夕、氧化铪、氧化紹、或其它材質、或上述之無 機材質的組合’·有機材質，如光阻、色阻、苯並環丁烯 (enZocyclobutane，BCB)、環烯類、聚醯亞胺類、聚醯胺類、 聚醋類、聚醇類、聚環氧乙烧類、聚苯類、樹脂類、聚鍵 ❹ 類、聚_員、或其它材料、或上述之有機材質的組合；甚 或是上述之無機材質與有機材質的組合。 制I與上述實補相較，本實齡说為轉㈣光層516 ^胁切換元件陣列基板51〇上，使其成為C0A基板， /、中必色遽光層M6位於切換元件512上方，並且被書 Ϊ2覆蓋。在其它實施例中，亦可以將彩色遽光層 =於切換兀件的下方’使切換元件陣列基板成為A% ί者：SC領域的技術人員依據現有技術所能理 板内本實施例所指的C0A基板或A〇C基 層與切換树的上下_是指在製程中所 的相對=的材料ΐ層的上下關係’並非強調圖式中所示 卜/、。即’若先形成製作彩色遽 個枒偏d層 絲形成製作切換元件的多 =層元件 與上述實施例相似，本實施例將襯層54〇製作於對向 20 200933240 ---- '219twf.doc/n 基板520上，亦即使襯層540位於顯示介質層53〇與對向 基板520之間。更詳細而言，本實施例先形成襯層54〇， 再形成共用電極層522,以使第一面板單元500A的共用電 極層522覆蓋襯層54〇,而位於襯層54〇與顯示介質層53〇 之間。當然，在其他實施例中，例如：先形成共用電θ極層 522 ’再形成襯層540，使襯層540配置於共用電極層522 上。 θ ❹ 另一方面，在本發明的其它實施例中，也可以改為將 襯層540製作於切換元件陣列基板51〇的局部區域上，使 其對應於特定尺寸的面板單元。例如，先形成襯層54〇， 再形成畫素電極514 ’或是先形成晝素電極514，再於其上 形成襯層540，或是’先形成襯層54〇於閘絕緣層（未繪示） 形成之前，或是先形成襯層540於閘絕緣層（未繪示)與保 濩層（未緣示)之間，或其它膜層位置、上述之組合，以使 襯層540位於第一面板單元5〇〇Α的晝素電極54〇之上及/ 或之I。基於前述的說明，這樣的設計同樣能達到形成不 ® 同之單元間隙550Α與550Β的效果。 本實施例的襯層540為單層或多層結構，且其材質例 如是光阻或是上述其他材質。以光阻材質的襯層54〇為 例，則如同前述實施例所述，形成襯層54〇的方法，較佳 地，是藉由塗佈乾膜光阻於局部的切換元件陣列基板51〇 及/或對向基板520上，但不限於此，亦可進行光阻塗佈、 曝光、顯影等微影製程、印刷製程、噴墨製程、或其它合 適製程、或上述之組合。同樣地，切換元件陣列基板51〇 21 200933240 _ j219twf.doc/n 及/或是對向基板520上的其他膜層也可以採用類似的乾 膜塗佈、或是微影製程、或是印刷製程、喷墨製程、或其 它合適製程、或上述之組合來製作，此處不再逐一贅述。 請再參考圖5，本實施例同樣是將黑矩陣524製作於 對向基板520上，且黑矩陣524例如是對應於切換元件陣 列基板510上的金屬圖案，如切換元件512或相關配線(如 掃描線及資料線等）等。此外，本實施例以黑矩陣524及共 用電極層502為例，則黑矩陣524被共用電極層5〇2所覆 蓋，但不限於此，亦可位於共用電極層5〇2上。當然參 照其它現有製程’也可以選擇將黑矩陣製作於切換元件陣 列基板上’且黑矩陣可以位於切換元件之上或之下。亦即， 先製作黑矩陣，再製作切換元件於其上；或是，先製作切 ❺Gl9twf.d〇c/n=Outside the mode </ RTI> The present invention can also be directly stacked by color light 不同 of different colors to form a desired black matrix and _ thing, which will not be reported one by one. Figure 5 is a representation of a mother panel of a face panel in accordance with yet another embodiment of the present invention. For ease of understanding, the smoke sample of the present embodiment is illustrated by the layout of the panel unit having the size shown in FIG. 1 , that is, the motherboard leakage, for example, the group of the first panel unit 5A having the first size and A group of second panel units 500B of a second size, and the first size is substantially different than the second size. In this embodiment the first dimension is substantially smaller than the second dimension. However, in other embodiments, the size relationships of the two are also interchangeable. In addition, each of the first panel unit 5A and each of the second panel units 500B has a display area (not shown) and a peripheral circuit area (not labeled) of the adjacent display area. As shown in FIG. 5, the mother board 500 mainly includes a switching element array substrate 510, a counter substrate 520, a display medium layer 530, and a liner layer 540. The switching element array substrate 510 has a plurality of switching elements 512 arranged in an array and a plurality of halogen electrodes 514 corresponding to the switching elements. Further, the opposite substrate 520 and the switching element array substrate 51 are substantially parallel. In the process, in this embodiment, for example, the switching element array substrate 51 and the opposite substrate 520 are separately formed, and the switching element array substrate 51 and the opposite substrate 52 are assembled, and the display medium layer 530 is sealed therebetween. A mother board 500 having a first panel unit 500A and a second panel unit 500B is formed. In the present embodiment, the counter electrode substrate 520 has the common electrode layer 522 as an example. However, the present invention is not limited thereto, and the common electrode layer 522 may not be provided. Of course, after the completion of the fabrication, 18 200933240 >219twf.doc/n also needs to cut the mother board 500, so that the first panel unit 5A and the second panel unit 500B become independent display panels. . In the present embodiment, the switching element array substrate 510 is, for example, a c〇A substrate, which can employ a thin film transistor as the switching element 512, and integrates the color filter layer 516 over the switching element 512. Wherein, the structure of the transistor and its semiconductor layer material can be as described in Fig. 2. Further, the opposite substrate 520 has elements such as a black matrix 524 _ in addition to the common electrode layer 522. The display medium layer 530 is disposed between the switching element array substrate 51 and the opposite substrate 520. The display medium layer 53 of the present embodiment is, for example, a liquid crystal layer or the other possible material layers. Similarly, the present embodiment configures the liner layer 540 on a specific region between the switching element array substrate 510 and the opposite substrate 520, for example, corresponding to the group ' of the first panel unit 500A such that the first panel unit 5A There is a first cell gap 550A. In contrast, the lining 540 corresponds to a group other than the second face & unit 500B such that the second panel unit 5 〇〇 B has a second unit 卩 3 gap 55 GB. In this embodiment, the lining layer 54 〇 is disposed in the first panel unit·B without disposing the lining layer 54 ′ in the second panel unit·B to form the first unit gap 550A and the second unit gap 55 of different sizes. 〇B. Therefore, it is preferable that the outer surface of the opposite substrate 520 of the first panel unit 5A on the mother board and the opposite substrate 52 of the first panel unit 5B are substantially horizontal. In other words, the sum of the thickness of the lining 54" and the first cell gap 5/0A is substantially equal to the second cell gap 55 〇 B. Furthermore, the second cell gap 550A and the second cell gap 55〇B are all located in the display area (not labeled) of the first panel unit 500A and the second panel unit drain B. 200933240 _219twf.doc/n display area (not Mark) to define it. In addition, the lining layer 54 is a single layer or a multi-layer structure, and the material thereof may be an inorganic material, such as oxidized stone, cerium nitride, nitrous oxide, carbonized stone, cerium oxide, oxidized, or other materials, or Combination of the above inorganic materials'·organic materials, such as photoresist, color resistance, enZocyclobutane (BCB), cycloolefins, polyimines, polyamines, polyacetates, polyalcohols a combination of an inorganic material and an organic material, or a combination of the above-mentioned inorganic materials and organic materials, or a combination of the above-mentioned organic materials. The system I is compared with the above-mentioned real complement, and the actual age is said to be the (four) optical layer 516, the switching element array substrate 51 is turned on, so that it becomes a C0A substrate, and the /·················· And covered by Book 2. In other embodiments, the color light-emitting layer can also be used to make the switching element array substrate A% below the switching element: those skilled in the SC field can refer to the embodiment in the prior art. The upper and lower _ of the C0A substrate or the A 〇 C base layer and the switching tree _ means that the relative relationship between the material ΐ layer in the process is not emphasized in the drawing. That is, if a multi-layer element which is formed into a color-made d-layered wire to form a switching element is formed similarly to the above embodiment, the lining layer 54 is formed in the opposite direction 20 200933240 ---- '219twf. On the doc/n substrate 520, even if the liner 540 is located between the display medium layer 53A and the opposite substrate 520. In more detail, in this embodiment, the lining layer 54 is formed first, and then the common electrode layer 522 is formed so that the common electrode layer 522 of the first panel unit 500A covers the lining 54 〇 and is located on the lining layer 54 〇 and the display medium layer. Between 53 。. Of course, in other embodiments, for example, the common electric θ pole layer 522 ' is formed first to form the lining layer 540, and the lining layer 540 is disposed on the common electrode layer 522. θ ❹ On the other hand, in other embodiments of the present invention, the liner layer 540 may be formed on a partial region of the switching element array substrate 51 to be corresponding to a panel unit of a specific size. For example, the lining layer 54 is formed first, then the pixel electrode 514 ' is formed or the ruthenium electrode 514 is formed first, and then the lining layer 540 is formed thereon, or the lining layer 54 is formed first on the gate insulating layer (not drawn) Before the formation, the liner layer 540 is formed between the gate insulating layer (not shown) and the protective layer (not shown), or other film layer positions, in combination with the above, so that the liner layer 540 is located A panel unit 5〇〇Α is above the halogen electrode 54〇 and/or I. Based on the foregoing description, such a design can also achieve the effect of forming a cell gap of 550 Α and 550 不. The lining layer 540 of this embodiment has a single layer or a multi-layer structure, and its material is, for example, a photoresist or the other materials described above. Taking the lining layer 54 of the photoresist material as an example, as in the foregoing embodiment, the method of forming the lining layer 54 is preferably by applying a dry film photoresist to the local switching element array substrate 51. And/or the counter substrate 520, but not limited thereto, may also be subjected to a photolithography process such as photoresist coating, exposure, development, a printing process, an inkjet process, or other suitable process, or a combination thereof. Similarly, the switching element array substrate 51〇21 200933240 _ j219twf.doc/n and/or other film layers on the opposite substrate 520 can also adopt a similar dry film coating, or a lithography process, or a printing process. , inkjet process, or other suitable process, or a combination of the above, is not repeated here. Referring to FIG. 5 again, in this embodiment, the black matrix 524 is also formed on the opposite substrate 520, and the black matrix 524 is, for example, corresponding to a metal pattern on the switching element array substrate 510, such as the switching element 512 or related wiring (eg, Scan lines, data lines, etc.). Further, in the present embodiment, the black matrix 524 and the common electrode layer 502 are taken as an example, and the black matrix 524 is covered by the common electrode layer 5〇2, but is not limited thereto, and may be located on the common electrode layer 5〇2. Of course, other black processes may be selected to be fabricated on the switching element array substrate' and the black matrix may be located above or below the switching element. That is, first make a black matrix, and then make a switching component on it; or, first make a cut
換=件’再製作黑轉於其上。此部分應為本領域的技術 人員依據現有技術所能理解者，因此不再贅述。另外，為 了維持切換元件陣列基板51()與對向基板52〇之間的距 離，本實施例更在切換元件陣列基板51G與對向基板52〇 之間配置多個間隙物56Q。該些間隙物56()的鄕包含光 間隙物、球_物、或其它_物、或上狀組合，而間 隙物560的位置可對應黑矩陣524與切換元件陣列基板 510上的金屬圖案§&置，以減少開口率的損失。同樣地， 參照現有的製程技術，除了本實施例的配置方式之外，本 不同顏色的彩色遽光層直接堆疊形成所需 的”、、矩陣與間隙物，此處不再逐一贅述。 必舄說月的疋，上述實施例較佳地以襯層3仙或 22 200933240 ----------—219twf.doc/n ，面地形成於第一面板單元3〇〇A或5〇〇A上，即包含顯示 區及周邊電路區’但不限於此，亦可使襯層34〇或54❶形 成於部份第一面板單元300八或5〇〇人上，即僅包含顯示區。 _綜^所述，本發明整合了多種不同尺寸的面板單元於 同一顯不面板的母板上，並且可視實際的需求調整面板單 =的配置。此外，本發明因應於母板上之不同尺寸的面板 單兀，更藉由襯層來補償該些不同尺寸之面板單元的單元 ❹ 間隙差異，以符合每一面板單元的規格需求。在本發明中， 襯層可以被形成於切換元件陣列基板或是對向基板上，且 切換元件陣列基板與對向基板的型態與内部元件配置可以 有諸多變化。據此，本發明所提出的顯示面板的母板及其 製作方法可被應用於各類型的顯示面板上，以有效利用^ 板上的可用空間，改善顯示面板的母板利用率，並有助於 提升整體的產能。 雖然本發明已以實施例揭露如上，然其並非用以限定 树明’任何所屬領域中具有通常知識者，在不脫離本發 明之精神和範圍内，當可作些許之更動與潤飾，因此本發 明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 ^ 圖1緣示依照本發明之一實施例的-種顯示面板之母 板的上視圖。 圖2繪示由圖i之母板100所製得的顯示面板的剖面 圖。 圖3緣示依照本發明之另-實施例的—麵示面板之 23 200933240 _.219twf.doc/n 母板的結構圖。 圖4繪示一種藉由多排式乾膜光阻塗佈機台塗佈乾膜 光阻於基板上的製程。 圖5繪示依照本發明之又一實施例的一種顯示面板之 母板的結構圖。 【主要元件符號說明】 100 :母板 110:第一面板單元 ® 120 :第二面板單元 200 :顯示面板 210 :切換元件陣列基板 212 :切換元件 214 :共用配線 216 :閘絕緣層 218 :保護層 219 :晝素電極 G 220:對向基板 222 :黑矩陣 224 :彩色濾光層 226 :共用電極層 230 :顯示介質層 240 :間隙物 250 :單元間隙 300、500 :母板 24 200933240 __________ _ _219twf.doc/n 300A、500A :第一面板單元 300B、500B :第二面板單元 310、510 :切換元件陣列基板 312、512 :切換元件 314、514 :晝素電極 320、520 :對向基板 322、522 :共用電極層 324、524 :黑矩陣 326、516 :彩色濾光層 330、530 :顯示介質層 340、540 :襯層 350A、550A :第一單元間隙 350B、550B :第二單元間隙 360、560 :間隙物 400 :乾膜光阻塗佈機台 410 :乾膜光阻 25Change the piece to make black and turn it on. This section should be understood by those skilled in the art based on the prior art, and therefore will not be described again. Further, in order to maintain the distance between the switching element array substrate 51 () and the opposite substrate 52A, in the present embodiment, a plurality of spacers 56Q are disposed between the switching element array substrate 51G and the opposite substrate 52A. The germanium of the spacers 56() includes a light spacer, a sphere, or other material, or an upper combination, and the position of the spacer 560 may correspond to the metal pattern on the black matrix 524 and the switching element array substrate 510. & set to reduce the loss of aperture ratio. Similarly, referring to the existing process technology, in addition to the configuration mode of the embodiment, the color light-emitting layers of different colors are directly stacked to form a desired matrix, a spacer, and a spacer, which will not be described one by one. In the case of a month, the above embodiment is preferably formed on the first panel unit 3A or 5 in a lining layer of 3 sen or 22 200933240 ---------- 219 twf.doc/n. 〇〇A, that is, including the display area and the peripheral circuit area 'but not limited thereto, the lining 34 〇 or 54 亦可 may also be formed on some of the first panel unit 300 eight or five people, that is, only the display area According to the above, the present invention integrates a plurality of panel units of different sizes on the motherboard of the same display panel, and adjusts the configuration of the panel single = according to actual needs. Moreover, the present invention is adapted to the motherboard. The size of the panel unit is further compensated by the lining layer to compensate for the difference in the unit 间隙 gap of the panel units of different sizes to meet the specification requirements of each panel unit. In the present invention, the lining layer can be formed on the switching element array. The substrate or the opposite substrate, and the switching element The configuration of the array substrate and the counter substrate may vary widely. Accordingly, the motherboard of the display panel and the manufacturing method thereof can be applied to various types of display panels for effective use. ^ The available space on the board improves the board utilization of the display panel and helps to increase the overall capacity. Although the invention has been disclosed above by way of example, it is not intended to limit the invention in any field. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims. [Simple Description] ^ 1 is a top view of a mother board of a display panel in accordance with an embodiment of the present invention. FIG. 2 is a cross-sectional view of the display panel made of the motherboard 100 of FIG. Another embodiment of the invention - the face panel 23 200933240 _.219twf.doc / n structure of the mother board. Figure 4 shows a dry film light coated by a multi-row dry film photoresist coating machine Blocking the process on the substrate FIG. 5 is a structural diagram of a motherboard of a display panel according to still another embodiment of the present invention. [Description of Main Components] 100: Motherboard 110: First Panel Unit® 120: Second Panel Unit 200: Display Panel 210: switching element array substrate 212: switching element 214: common wiring 216: gate insulating layer 218: protective layer 219: halogen electrode G 220: opposite substrate 222: black matrix 224: color filter layer 226: common electrode layer 230: display medium layer 240: spacer 250: cell gap 300, 500: mother board 24 200933240 __________ _ _219twf.doc/n 300A, 500A: first panel unit 300B, 500B: second panel unit 310, 510: switching element Array substrate 312, 512: switching elements 314, 514: halogen electrodes 320, 520: opposite substrates 322, 522: common electrode layers 324, 524: black matrix 326, 516: color filter layers 330, 530: display medium layer 340, 540: lining layers 350A, 550A: first cell gaps 350B, 550B: second cell gaps 360, 560: spacers 400: dry film photoresist coater 410: dry film photoresist 25