200931435 九、發明說明： 【發明所屬之技術領域】 本發明係與一記憶體電路有關’尤其係與—種具高讀 取速率及低切換雜訊的記憶體電路有關。 【先前技術】 吁夕歡位積體電路系統中.'…〜.叫〜疋吩丫，项.申 Ο ❹ 會有複數個輸出緩衝器的陣列設置於其上，以用來對輸出 的數位資料串（digital data stream)進行輪出處理。然 而，在一般的記憶體電路中，對於數位資料 出、 通常會存在-些問題，亦即在資料的輪出路徑=常二 電阻值變化及/或輸出路徑彼此_感應效 的延遲與雜訊干擾等問題。再者，尤 (例二St料信號若在傳遞過程中有發生相位切換 轉換成高電位）的情況時，在相位=疋從低電位 訊干擾問題將會特㈣重。 &財所產生的雜 有提出一種預的^前習，技術中，已經 先調整電壓值的托μ 1緩衝器之輸出端進行預 其電壓差值的變：二以：低輸出信號在相位切換期間， 出端進行預二;值=這樣預先對輸出緩㈣ 的目的，而日、速又而達到提昇記憶體電路之讀取速度 因為電壓差值變化幅度縮小，造成輸出缓衝 5 200931435 器中產生直流電流值的幅度也得以降低，進而降低在資料 傳遞的過程中，因為相位的切換而產生的切換信號干擾的 問題。 . 在美國專利公告號US 4, 992, 677號專利中即揭露一種 ❹ 使用2述技術方案的積體電路設計。請參閱第}圖其係 表示前述專利中的一種用來對一積體電路的輸出緩衝器進 行預先調整電壓值的預設電路設計。如該第i圖中所示， 該預設電路10係包含串聯連接的一第一金氧半電晶體 (MOSFET) 11及-第二金氧半電晶體12，以及一第一與第 二差動放大器15、16分別與該第—與第二金氧半電晶體 =2相互電性連接；其中’該第一與第二差動放大器Η 及16分別被輸入一第一與第二參考電壓17及18，以用於 : = 10的一輸出電壓值v〇進行比較進而分別 號’以控制該第一與第二金氧半電晶體 12的開啟與關閉。從該第丨圖中可以更進 ❹ =金氧半電晶體U係與—供應電壓源2，例如_ J 、二也而料二金氧半電晶體12則係連接到-接地端3， =流過該第一與第二金氧半電晶體『12的 向，進而達到調整該預設電路 值之目的。 J輙出螭1的輸出電壓 舉例來說，當該輸出電壓v〇大於該 18時’該第二金氧半電晶體12將會被: 、值 16所輸出的控制信號所開啟， ：= 通過該第二經氧半電晶趙]2而流到接 6 200931435 輸出電壓值之目的；同樣的，當該輸出電壓Vo小於該第一 參考電壓值17時，該第一金氧半電晶體11將會被該第一 差動放大器15所輸出的控制信號所開啟，進而讓電流iH 從該供應電壓源2通過該第一經氧半電晶體1而流到該輸 出端1，以達到提昇該輸出電壓值之目的。 根據前述專利中所揭露之内容，前述之預設電路10中 所包含的第一與第二金氧半電晶體Π、12除了可以由兩個 N通道的金氧半電晶體所組成外，也可以用雙極電晶體 ❹ （bipolar transistor )或由一 P通道及一 N通道串疊而 成的電晶體對所組成。不過，無論是採用哪一種電晶體結 構設計，前述之預設電路於操作時均只會有其中一個電壓 體開啟，這也表示說，用來控制該電壓體開啟與關閉的差 動放大器及輸入該放大器的參考電壓信號皆須要有兩組。 然而，這樣的結果不僅會使該預設電路的電路結構因為元 件數目較多而無法有效縮減電路所佔之區域，且因為較多 的元件數目也會造成電路佈局設計及製造時的複雜度，同 ❹ 時，材料與製造成本的增加可能會對產品的量產會產生阻 礙。 綜合以上所述，申請人鑑於習知技術中應用於一般積 體電路的輸出電壓調整之預設電路仍存在許多亟待克服的 缺現，遂經過悉心試驗與研究，並一本鍥而不捨之精神， 終於構思出本案一種具高讀取速度及低切換雜訊之記憶體 電路，其具有預設電路之設計，以克服前述之諸多缺失。 【發明内容】 7 200931435 本發明之第一構想係提出一種記憶體電路，其包含一 第一與一第二三態緩衝器（tri_state buffer)以及一預 設電路（pre—set circuit)，其中，該第一三態緩衝器 (tri state buffer)係被輸入具有一第一電壓位準之一 ❹200931435 IX. Description of the Invention: [Technical Field] The present invention relates to a memory circuit, in particular, to a memory circuit having a high read rate and low switching noise. [Prior Art] In the circuit of the circuit, the '....~.called~疋,丫.申Ο ❹ There will be an array of multiple output buffers set on it for the digital digits of the output. The data stream is rounded out. However, in a general memory circuit, there are usually some problems with the digital data, that is, the round-trip path of the data = the change of the resistance value of the second and/or the delay and noise of the output path of each other. Interference and other issues. Furthermore, especially in the case where the phase signal of the St material is converted to a high potential during the transfer, the phase interference = the low potential interference problem will be (4) heavy. The miscellaneous sums produced by & Cai have proposed a pre-existing technique. In the technique, the output of the μμ1 buffer, which has been adjusted with the voltage value, is pre-varied to the voltage difference: second: the low output signal is in phase. During the switching period, the output is pre-selected; the value = such that the output is slow (4) in advance, and the reading speed of the memory circuit is increased by the day and the speed, because the voltage difference changes by a small amount, resulting in an output buffer 5 200931435 The amplitude of the generated DC current value is also reduced, thereby reducing the problem of switching signal interference caused by phase switching during data transmission. An integrated circuit design using the above-described technical solution is disclosed in U.S. Patent No. 4,992,677. Please refer to the figure below for a preset circuit design for pre-adjusting the voltage value of an output buffer of an integrated circuit. As shown in the figure i, the preset circuit 10 includes a first MOS transistor 11 and a second MOS transistor 12 connected in series, and a first and second difference. The dynamic amplifiers 15, 16 are electrically connected to the first and second MOS transistors = 2, respectively; wherein the first and second differential amplifiers Η and 16 are respectively input with a first and second reference voltage 17 and 18 are compared for an output voltage value v = of 10 = 10 to control the opening and closing of the first and second MOS transistors 12, respectively. From this figure, it is possible to change the 金 = MOS semi-transistor U system and - supply voltage source 2, such as _ J, and the second MOS transistor 12 is connected to the - ground terminal 3, = Flowing through the first and second MOS transistors "12", thereby achieving the purpose of adjusting the preset circuit value. For example, when the output voltage v 〇 is greater than the 18, the second MOS transistor 12 will be turned on by the control signal outputted by the value 16 : := The second oxygen-containing semi-electrode crystal 2 flows to the purpose of outputting the voltage value of 6 200931435; similarly, when the output voltage Vo is less than the first reference voltage value 17, the first gold-oxygen semiconductor 11 The control signal outputted by the first differential amplifier 15 is turned on, and then the current iH flows from the supply voltage source 2 through the first oxygen-containing transistor 1 to the output terminal 1 to enhance the current The purpose of the output voltage value. According to the disclosure of the foregoing patent, the first and second MOS transistors 12, 12 included in the foregoing preset circuit 10 can be composed of two N-channel MOS transistors, It can be composed of a bipolar transistor or a pair of transistors formed by stacking a P channel and an N channel. However, no matter which type of transistor structure is used, the aforementioned preset circuit will only have one of the voltage bodies turned on during operation, which means that the differential amplifier and input for controlling the voltage body to be turned on and off are also shown. The amplifier's reference voltage signal requires two sets. However, such a result not only makes the circuit structure of the preset circuit unable to effectively reduce the area occupied by the circuit because of the large number of components, but also because the number of components also causes the complexity of circuit layout design and manufacturing. At the same time, increased material and manufacturing costs may hinder the mass production of the product. In summary, the applicant still has many shortcomings to be overcome in view of the conventional circuit applied to the output voltage adjustment of the general integrated circuit in the prior art. After careful testing and research, and a spirit of perseverance, finally The present invention contemplates a memory circuit with high read speed and low switching noise, which has a preset circuit design to overcome the aforementioned shortcomings. [Description of the Invention] 7 200931435 The first concept of the present invention is to provide a memory circuit including a first and a second tristate buffer and a pre-set circuit. The first tristate buffer is input with one of the first voltage levels.
資料信號，且當該第-三態緩衝器開啟時，該資料信號係 經由一第一負載線路輸出；該第二三態緩衝器係與該第一 負載線路電性連接’當該第二三態緩衝器開啟時，該第二 三態緩衝器係接收並輸出該資料信號；域預設電路係包 含- N型金氧半電晶體及__ p型金氧半電晶體，且該預設 電路係在該第-三態緩衝器開啟之前提供具有—第二電壓 位準的一預設電壓至該第一負載線路，其中，續 接收-控制信號以同時開啟該N型及p型金氧半電晶體， 且當該第-三態緩衝器開啟時，該第—負載電路的電壓值 係從該第二電壓位準振盪到該第一電壓位準。 根據上述構想，其中該N型金氧半電晶體係與一供應 電壓電性連接’而該P型金氧半電晶體係與—接地端電性 根據上述構想，其中該控制信號係通過一反向器 傳送至該N型金氧半電晶體，以使該控制信 號同時開啟該N型與該p型金氧半電晶體。 _根據上述構想，其中該預設電路從該P型與該N型金 氧半電晶體之間的-輸出端輸出該預設電壓 細二㈣位準係相當於該供應電歷的1/2。預又電 根據上述構想，其中該第一與第二三態缓衝器係選自 8 200931435 傳輸閘（transmission gates)、PU/PD三態緩衝器及串 疊三態缓衝器其中之一。 根據上述構想，其中該第一負載線路係選自金氧半電 晶體、繞線（rout i ng 1 i nes )、電容器及電阻器其中之一。 根據上述構想，其中該第二三態緩衝器更透過一第二 負載線連接至一穩態電源。 本發明之又一構想係提出一種具高讀取速度及低切換 雜訊的記憶體電路，該記憶體電路包含一輸出緩衝器裝置 〇 及一預設電路（pre-set circuit )，其中，該輸出緩衝器 裝置更包含一第一輸入，用以接收具有一第一電壓位準之 一資料信號；一第二輸入，用以接收具有一第二電壓位準 之一預設電壓；以及一輸出，用以輸出該資料信號；該預 設電路係包含一對金氧半電晶體且該預設電路係在該輸出 緩衝器接收該資料信號之前提供該預設電壓至該第二輸 入，其中，該預設電路接收一控制信號以同時開啟該對金 氧半電晶體，且當該輸出緩衝器接收該資料信號時，該第 ❹二輸入的電壓值係從該第二電壓位準振盪到該第一電壓位 準。 根據上述構想，其中該預設電路係為一串疊的金氧半 電晶體電路，且該對金氧半電晶體係包含彼此串聯連接的 一 N型金氧半電晶體及一 P型金氧半電晶體。 根據上述構想，其中該輸出緩衝器裝置係包含第一與 第二三態緩衝器，且該第二輸入係設置與該第一與該第二 三態緩衝器之間。 9 200931435 本發明之又一構想係提出一種記憶體電路，其包一輸 入負載線路、一三態緩衝器及一預設電路（pre_set Circuit)’其中，輸入負載線路係傳送具有第一電壓位準 的一資料信號，該三態緩衝器係於開啟時係從該輸入負載 線路接收並輸出該資料信號，且該預設電路係包含一對金 氧半電晶體，該預設電路係在該輸入負載線路傳遞該資料 k號到該三態緩衝器之前提供具有一第二電壓位準的一預 :電壓至該輸出負載線路，其中，該預設電路接收一控制 L就t同時開啟該對金氧半電晶體，且當該三態缓衝器接 收該貝料信號時’該輪出負載線路的電壓值係從該第二電 壓位準振盪到該第—電壓位準。 根據上述構想’其中該三態緩衝器更透過連接至一穩 態電源的另一三態緩衝器輸出該資料信號。 本發明之又一構想係提出一種提高記憶體電路之讀取 速度與降低其切換雜訊的方法其至少包含下列步驟：（D 提供第一二癌缓衝器（tri-state buffer)，其中，當該 ^ 一二態緩衝器開啟時，具有一第一電壓位準之一資料信 號係經由該第-三態緩衝器接收與傳輸；⑺提供一第二 =態緩衝H ’其中，當該第二三態緩衝器開啟時，該第二 三態緩衝器接收並輪出該資料信號；以及⑻提供一預設 電=(pre-set circuit)，用以在該第一三態缓衝器開啟 之前提供具有-第二電壓位準的—預設電壓至該第一與第 =態緩衝器之間的-連接線路其中，當該第一三態緩 -器開啟時’ 4連接電路的電壓值係從該第二電壓位準振 200931435 盪到該第一電壓位準。 ❹ ❹ 本發明之又一構想係提出另一種提高記憶體電路之讀 取速度與降低其切換雜訊的方法’其至少包含下列步驟： (1)提供一輸出緩衝器裝置，用以接收並輪出具有一第一 電壓位準之一資料信號；以及（2)提供一預設電路（pre_set circuit)，用以在該輸出緩衝器接收該資料信號之前提供 具有一第二電壓位準之一預設電壓至該輸出緩衝器，以使 該輸出緩衝器裝置的一信號傳輸線路具有該第二電壓位 準，其中，當該輸出缓衝器接收該資料信號時，該第二輸 入的電壓值係從該第二電壓位準振盪到該第一電壓位準。 本發明之又一構想係提出另一種提高記憶體電路之讀 取速度與降低其切換雜訊的方法，其至少包含下列步驟： (1)提仏一態緩衝器（tri-state buffer)，用以接收 並傳輸具有第-電壓位準的—資料信號；以及（2)提供一 :::: (pr"et circui〇,用以在該三態緩衝器開啟 3 =有一第二電壓位準的一預設電壓至該三態緩衝 :的-輸出線路，其中’當該三態緩衝器開啟時該輸出 =的電壓值係從該第二f壓位準振盪到該第—電麗位 藉由下列之圖式及具體實施制詳 俾侍一更深入之了解： n 【實施方式】 請參閱第2圖，其係表示根據 施例的記憶體電路的區塊矛㈣」狀難具體實 尾不葸圖。如第2圖中所示，當— 200931435 數位資料信號21從一三態緩衝器22傳送到另一三態緩衝 器23時，在兩個三態缓衝器22、23之間的傳輸路徑25上 將會有壓降的情況產生，尤其如果是所傳遞的數位資料信 號有產生相位變化的情況時，例如由一邏輯上的高電位轉 換成邏輯上的低電位或其相反情況時，該數位資料信號的 將會有切換雜訊及傳遞延遲的情況產生。而為了有效克服 這些問題，本發明係採用一預設電路24來提供一預設電壓 到該傳輸路徑25上。藉由這樣的預設電路之設置，在該數 © 位資料信號21的相位變化期間，發生在傳輸路徑25上的 電壓變化值將會有效的降低，進而可以有效地緩和信號傳 遞延遲與切換雜訊等問題。除此之外，在另一三態緩衝器 23的輸出線路（沒有顯示於圖中）上，由於該輸出線路上 的等效電阻值是相對難以估計的，而一但該另一三態緩衝 器23開啟時，常常也會因為在該輸出線路上出現劇烈的電 壓變動情況，而造成不必要的功率消耗。為了有效克服這 樣的問題，該另一三態緩衝器23可以透過額外電性連接到 © —穩態電源來解決這樣的問題。 請再進一步參閱第3圖，其係表示根據本發明之一較 佳具體實施例之記憶體電路的等效電路圖。如第3圖中所 是，根據本發明之較佳具體實施例的記憶體電路300係包 含一輸出緩衝器裝置36，該輸出緩衝器裝置36具有一第 一輸入361，用以接收具有一第一壓電位準的一資料信號 31 ; —第二輸入362，用以接收具有一第二電壓位準的預 設電壓；以及一輸出363，用以輸出該資料信號。該記憶 12 200931435 體電路300更進一步配置一預設電路30，其中該預設電路 係包含一對金氧半電晶體（MOSFET) 301、302 ’並且在該輸 出緩衝器裝置36接收該資料信號31之前，從該對金氧半 電晶體30卜302之間的一輸出端提供該預設電壓到該輸出 緩衝器裝置36的第二輸入362。更進一步來說，該預設電 路30係為一金氧半電晶體的串疊電路，且該對金氧半電晶 體係包含串聯連接的一 N型金氧半電晶體301及P型金氧 半電晶體302。而且，該N型金氧半電晶體301更與一供 ❹ 應電壓VDD電性連接，而該P型金氧半電晶體302則與一 接地GND電性連接。除此之外，該預設電路3〇也具有輸入 304，接收用以同時啟動該對金氡半電晶體3〇1、3〇2的一 控制信號，其中該控制信號係透過一反向器3〇3傳送到該 N型金氧半電晶體3〇1，不過，在傳送到該p型金氧半電晶 體302時則不需透過反向器。藉由這樣的電路設置，該控 制仏號可以同時啟動該N型金氧半電晶體301以及P塑金 氧半電晶體302。而該N型金氧半電晶體301與P型金氧 ❹半電晶體3〇2同時啟動之後’該預設電路3〇便可以從該輸 出端305輸出具有該第二電壓位準的預設電壓到該輸出缓 衝器裝置36的第二輸入。而且，因為該預設電壓係透過同 時開啟的P型與N型金氧半電晶體所產生，因此該預設電 壓的第二電壓位準可相當於該供應電壓值的1/2。 另—方面’當該輸出緩衝器裝置36也進一步包含相互 串聯連接的-第-與-第二三態緩衝器364、365，其中該 輸出緩衝器^^二輪入則設置於該第一與第二缓 200931435 衝器364、365之間。不過，該第一與第二三態緩衝器364、 365之間的線路上一般來說都會存在一等效電阻值，而該 等效電阻值可視為設置在該第一與第二三態緩衝器364、 365之間的一負載電路366。而因為該輸出緩衝器36的第 二輸入362係設置於該第一與第二三態緩衝器364、365之 間，因而當該預設電壓從該預設電路輸出至該第二輸入 時，該負載線路366上的電壓位準也會被預先設定到欲該 第二輸入相等。因此，當一輸出緩衝器裝置36接收該資料 〇 信號31時，也就是該第一緩衝器364被開啟時，在該第二 輸入362 (也就是該負載線路366 )的電壓位準將會從該預 設電壓值的電壓位準擺盪到該資料信號的電壓位準。除此 之外，在該負載線路的電壓位準擺盪至該資料信號的電壓 位準後，該輸出緩衝器裝置36進一步透過與該第二三態緩 衝器365電性連接的該輸出363輸出該資料信號。不過， 當該資料信號透過該第二三態緩衝器365輸出時，在該第 二三態緩衝器365的輸出線路上同樣會存在一等效電阻 Ο 值，這樣的等效電阻值就相當於是該第二三態緩衝器365 具有一輸出負載線路37 —樣，而該輸出負載線路37上同 樣會因為等效電阻值的存在而消耗用來驅動該資料信號的 功率。尤其是，在該輸出缓衝器裝置36的操作期間，當該 第二三態緩衝器365開啟之前，該輸出363將會輸出多大 電壓位準的信號是無法得知的。因此，為了防範過多不必 要的功率消耗在該輸出負載線路37上，該輸出負載線路 37將會連接一穩態電源39，以降低該輸出負載線路37上 14 200931435 所產生的電流，進而有效降低不必要的功率消耗。在一較 佳具體實施例中’前述之穩態電源39可以是與該資料信號 具有相同電屢位準的電壓值，也就是說該穩態電麼可以是 具有邏輯上的高電位及低電位其令之一。 在另一較佳具體實施例令，該第一與第二三態緩衝器 可以是選自傳輸閘（transmission gates)、pu/PD三熊 緩衝器及串疊三態緩衝器等其中之一。而且，前述之負^ f路，不論是該[與第二緩衝器之間的負載線路366或 ❹是該第二三態緩衝器的輸出附在線路37均可以選自金氧 半電晶體、繞線（routing lines)、電容器及電阻器其中 —— 〇 請繼續參閱第4圖，其係表示根據本發明之記憶體電 路中在S亥第一三態緩衝器的一輸入及該預設電路的一輸入 及該預設電路的一輸出所偵測到的電壓位準與在該第一三 態緩衝器的輸出負載線路上的功率消耗之波形圖。從該第 4圖中可以看出，在該第一三態緩衝器364被啟動之前， 亦即如第4圖中的第一條波形（A)被從邏輯上的低電位提 昇至高電位之前，在該第4圖的第二條波形（B)會產生一 脈衝波形，該脈衝波形即表示該控制信號的產生並且被傳 送至該預設電路中的該第一與第二金氧半電晶體，以用於 同時開啟該第一與第二金氧半電晶體，進而達到產生該預 »又電壓至该第_三態緩衝器的輸出負載線路（亦即第3圖 中的負載線路366)的效果。而在同一時間，當該預設電 路被啟動時’在該第一三態緩衝器的輸出負載線路上的電 15 200931435 壓值會被提昇至與該預設電壓相當的電壓位準，如同第4 圖的第三條波形（c)中所示。而等到該第一三態緩衝器真 的被啟動時，亦即該第一波形（A)中從邏輯上的低電位信 號轉換成高電位信號時，該預設電路將會被關閉，也就是 該第二條波形（B)中的脈衝波形結束的時候。而同—時間， 在該第一三態緩衝器的輸出附在線路上的電壓位準則是從 原先預設電壓的電壓位準再進一步擺盪至該資料信號的電 壓準位。必須進一步說明的是，前述實施例中係以該資料 〇 信號為邏輯上的高電壓位準為例，然而該資料信號也有可 能是具有邏輯上的低電壓位準，此時，當該第一三態緩衝 器開啟時，該第一緩衝器的輸出負載線路的電壓就$從該 預設電壓的電壓位準下降至與該資料信號的電壓位準相 / 當。不過，這樣的操作方式和前述之實施例係完全對應， 彼此並不會有所不同。 〜 除此之外，關於第4圖中的第四波形（D)，其係表示 發生在該第一二態緩衝器的輸出負载線路中的功率消耗之 〇波形圖。如同從該第四波形（D)中可以看出，每當該第一 三態緩衝器的輸出負載線路中發生電壓變化時，載線 路上將會產生不同程度的功率消耗。而這些的功率消耗的 程度將會視該電壓變化的程度與該電壓轉換的時間來決 定。在本實施例中，在該輸出負載線路中共發生兩次的功 率消耗情況，其-即為當該輸出負載線路的電壓從一邏輯 上的低電壓位準提昇至-預設電壓的電壓位準時所造成的 功率消耗，而另-次則是當該輪出負載線路的電壓從該預 16 200931435 設電壓的電壓位準擺盪至該資料信號的電壓位準時。不 過’如果再原來的輸出負載電路中沒有透過兩次的電壓位 準的擺Μ而是直接從邏輯上的低電壓位準直接提昇至該資 料信號的高電壓位準時，在該輸出負載電路上所產生的功 率消耗的尖峰值將會陡峭的增加’這樣的結果將會導致嚴 重的切換雜訊及嚴重的信號傳遞延遲，嚴重時會使所傳遞 的乜號產生錯誤的情況。而本發明透過預設電路的設置， 使該輸出負載電路的功率消耗可以分散成複數個較小的功 © 率消耗值，以緩和不必要的功率消耗所造成的影響。 本發明雖以上述數個較佳實施例揭露如上其益# 用以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作些許之更動與潤飾’因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係表示習知技術中的一種預設電路的等效電路 圖。 © 帛2 _表錄據本發明之-較佳具體實施例的記憶 體電路的區塊示意圖。 第3圖係表不根據本發明之一較佳具體實施例之記憶 體電路的等效電路圖。 第4圖係表示根據本發明之記憶體電路中在該第一三 態緩衝器的-輸入及該預設電路的一輸入及該預設電路的 一輸出所偵測到的電壓位準與在該第一三態緩衝器的輸出 負載線路上的功率消耗之波形圖。 17 200931435 【主要元件符號說明】 1 輸出端 10、24 預設電路 2 輸入電壓 11 > 12 金氧半電晶體 3 接地 15、16 差動放大器 17、18 參考電壓 21 > 31 資料信號 22、23 三態緩衝器 26、39 穩態電源 25 傳輸路徑 36 缓衝器裝置 30 預設電路 363 輸出 361、362 輸入 366 、 37 負載線路 364 > 365 三態緩衝器 303 反向器 304 輸入 305 輸出端 3(H、302金氧半電晶體 ❹ 18a data signal, and when the first-tristate buffer is turned on, the data signal is output via a first load line; the second tri-state buffer is electrically connected to the first load line 'When the second three When the state buffer is turned on, the second tristate buffer receives and outputs the data signal; the domain preset circuit includes an -N type MOS transistor and a __p type MOS transistor, and the preset The circuit provides a predetermined voltage having a second voltage level to the first load line before the first-tristate buffer is turned on, wherein the receiving-control signal continues to turn on the N-type and p-type gold oxide simultaneously a semi-transistor, and when the first-tri-state buffer is turned on, a voltage value of the first-load circuit is oscillated from the second voltage level to the first voltage level. According to the above concept, wherein the N-type gold-oxygen semi-electron crystal system is electrically connected to a supply voltage, and the P-type gold-oxygen semi-electron crystal system and the grounding terminal are electrically connected according to the above concept, wherein the control signal passes through an inverse The transistor is transferred to the N-type MOS transistor so that the control signal simultaneously turns on the N-type and the p-type MOS transistor. According to the above concept, the preset circuit outputs the preset voltage fine two (four) level from the output terminal between the P-type and the N-type MOS transistor, which is equivalent to 1/2 of the supply electric calendar. . Pre-recurrent According to the above concept, the first and second tri-state buffers are selected from one of 8 200931435 transmission gates, PU/PD tri-state buffers, and serial tri-state buffers. According to the above concept, the first load line is selected from one of a metal oxide semiconductor, a winding, a capacitor, and a resistor. According to the above concept, the second tri-state buffer is further connected to a steady state power supply through a second load line. Another aspect of the present invention is to provide a memory circuit having a high read speed and low switching noise, the memory circuit including an output buffer device and a pre-set circuit, wherein The output buffer device further includes a first input for receiving a data signal having a first voltage level, a second input for receiving a predetermined voltage having a second voltage level, and an output For outputting the data signal; the preset circuit includes a pair of MOS transistors and the preset circuit provides the preset voltage to the second input before the output buffer receives the data signal, wherein The preset circuit receives a control signal to simultaneously turn on the pair of MOS transistors, and when the output buffer receives the data signal, the voltage value of the second input voltage oscillates from the second voltage level to the The first voltage level. According to the above concept, wherein the predetermined circuit is a series of MOS transistors, and the pair of MOS systems comprises an N-type MOS transistor and a P-type gold oxide connected in series with each other. Semi-transistor. According to the above concept, wherein the output buffer device includes first and second tristate buffers, and the second input system is disposed between the first and second tristate buffers. 9 200931435 Another idea of the present invention is to provide a memory circuit that includes an input load line, a tristate buffer, and a preset circuit (pre_set circuit), wherein the input load line transmits the first voltage level. a data signal, the tristate buffer receives and outputs the data signal from the input load line when the circuit is turned on, and the preset circuit includes a pair of MOS transistors, the preset circuit is at the input Before the load line transmits the data k number to the tristate buffer, a pre-voltage having a second voltage level is provided to the output load line, wherein the preset circuit receives a control L to simultaneously turn on the pair of gold An oxygen semi-transistor, and when the tri-state buffer receives the bedding signal, the voltage value of the wheel-out load line oscillates from the second voltage level to the first voltage level. According to the above concept, the tristate buffer outputs the data signal through another tristate buffer connected to a steady state power supply. Another idea of the present invention is to provide a method for improving the reading speed of a memory circuit and reducing the switching noise thereof, which comprises at least the following steps: (D provides a first two-state buffer, wherein When the two-state buffer is turned on, a data signal having a first voltage level is received and transmitted via the first-tristate buffer; (7) a second = state buffer H' is provided, wherein When the two-three-state buffer is turned on, the second tri-state buffer receives and rotates the data signal; and (8) provides a pre-set circuit for turning on the first three-state buffer Providing a pre-set voltage having a -second voltage level to a -connection line between the first and the second state buffers, wherein the voltage value of the '4 connection circuit when the first tri-state buffer is turned on The second voltage level vibration 200931435 is oscillated to the first voltage level. ❹ 又一 Another concept of the present invention is another method for improving the reading speed of the memory circuit and reducing the switching noise thereof. The following steps are included: (1) Provide an output buffer a device for receiving and rotating a data signal having a first voltage level; and (2) providing a pre-set circuit for providing a first data before the output buffer receives the data signal One of the two voltage levels presets a voltage to the output buffer such that a signal transmission line of the output buffer device has the second voltage level, wherein when the output buffer receives the data signal, the The voltage value of the second input is oscillated from the second voltage level to the first voltage level. Another concept of the present invention is to provide another method for improving the reading speed of the memory circuit and reducing the switching noise. It comprises at least the following steps: (1) a tri-state buffer for receiving and transmitting a data signal having a first voltage level; and (2) providing a :::: (pr" ;et circui〇, for turning on the tristate buffer 3 = a predetermined voltage of a second voltage level to the tristate buffer: - output line, where 'the output when the tristate buffer is turned on = the voltage value is from the second f The level oscillation to the first electric position is further understood by the following drawings and specific implementation details: n [Embodiment] Please refer to Fig. 2, which shows the memory circuit according to the embodiment. The block spear (four) is difficult to be specific. As shown in Fig. 2, when the 200931435 digital data signal 21 is transmitted from a tristate buffer 22 to another tristate buffer 23, in two There will be a voltage drop on the transmission path 25 between the tristate buffers 22, 23, especially if the transmitted digital data signal has a phase change, such as by a logic high potential. When converted to a logical low potential or vice versa, the digital data signal will have switching noise and transfer delay. In order to effectively overcome these problems, the present invention employs a predetermined circuit 24 to provide a predetermined voltage to the transmission path 25. With the setting of such a preset circuit, during the phase change of the digital bit data signal 21, the voltage change value occurring on the transmission path 25 is effectively reduced, thereby effectively alleviating the signal transmission delay and switching miscellaneous News and other issues. In addition, on the output line of another tri-state buffer 23 (not shown), since the equivalent resistance value on the output line is relatively difficult to estimate, the other tri-state buffer When the device 23 is turned on, it often causes unnecessary power consumption due to a violent voltage fluctuation on the output line. In order to effectively overcome such problems, the other tri-state buffer 23 can be additionally connected to the ©-steady state power supply to solve such problems. Referring to Figure 3, there is shown an equivalent circuit diagram of a memory circuit in accordance with a preferred embodiment of the present invention. As shown in FIG. 3, a memory circuit 300 in accordance with a preferred embodiment of the present invention includes an output buffer device 36 having a first input 361 for receiving a a data level 31 of a piezoelectric level; a second input 362 for receiving a predetermined voltage having a second voltage level; and an output 363 for outputting the data signal. The memory circuit 12 200931435 is further configured with a predetermined circuit 30, wherein the predetermined circuit includes a pair of metal oxide semiconductor (MOSFET) 301, 302' and the data signal 31 is received at the output buffer device 36. Previously, the predetermined voltage is supplied from an output between the pair of MOS transistors 30 to 302 to the second input 362 of the output buffer device 36. Furthermore, the predetermined circuit 30 is a cascode circuit of a MOS transistor, and the pair of MOS semi-electrode system comprises an N-type MOS transistor 301 and P-type gold oxide connected in series. Half transistor 302. Moreover, the N-type MOS transistor 301 is further electrically connected to a supply voltage VDD, and the P-type MOS transistor 302 is electrically connected to a ground GND. In addition, the preset circuit 3 〇 also has an input 304 for receiving a control signal for simultaneously starting the pair of metal 氡 semi-transistors 3 〇 1 , 3 〇 2 , wherein the control signal is transmitted through an inverter 3〇3 is transferred to the N-type MOS transistor 3〇1, but it is not required to pass through the inverter when it is transferred to the p-type MOS transistor 302. With such a circuit arrangement, the control nickname can simultaneously activate the N-type MOS transistor 301 and the P-metal oxy-oxygen transistor 302. After the N-type MOS transistor 301 and the P-type MOSFET semi-transistor 3〇2 are simultaneously activated, the preset circuit 3 can output a preset having the second voltage level from the output terminal 305. The voltage is applied to the second input of the output buffer device 36. Moreover, since the predetermined voltage is generated by P-type and N-type MOS transistors which are simultaneously turned on, the second voltage level of the preset voltage may be equivalent to 1/2 of the supply voltage value. In another aspect, the output buffer device 36 further includes a -th-and-second tristate buffer 364, 365 connected in series with each other, wherein the output buffer is disposed in the first and the second Second slow 200931435 between 364, 365. However, there is generally an equivalent resistance value on the line between the first and second tristate buffers 364, 365, and the equivalent resistance value can be regarded as being set in the first and second tristate buffers. A load circuit 366 between the devices 364, 365. And because the second input 362 of the output buffer 36 is disposed between the first and second tristate buffers 364, 365, when the preset voltage is output from the preset circuit to the second input, The voltage level on the load line 366 is also preset to be equal to the second input. Therefore, when an output buffer device 36 receives the data buffer signal 31, that is, when the first buffer 364 is turned on, the voltage level at the second input 362 (that is, the load line 366) will be from the The voltage level of the preset voltage value swings to the voltage level of the data signal. In addition, after the voltage level of the load line swings to the voltage level of the data signal, the output buffer device 36 further outputs the output 363 electrically connected to the second tristate buffer 365. Data signal. However, when the data signal is output through the second tristate buffer 365, an equivalent resistance 同样 value is also present on the output line of the second tristate buffer 365, and the equivalent resistance value is equivalent to The second tri-state buffer 365 has an output load line 37, and the output load line 37 also consumes power for driving the data signal due to the presence of an equivalent resistance value. In particular, during operation of the output buffer device 36, the signal at which the output 363 will output a large voltage level is not known until the second tri-state buffer 365 is turned "on". Therefore, in order to prevent excessive unnecessary power consumption on the output load line 37, the output load line 37 will be connected to a steady state power supply 39 to reduce the current generated by the 14 200931435 on the output load line 37, thereby effectively reducing Unnecessary power consumption. In a preferred embodiment, the aforementioned steady state power supply 39 can be a voltage value having the same electrical level as the data signal, that is, the steady state power can be a logic high potential and a low potential. One of its orders. In another preferred embodiment, the first and second tristate buffers may be one selected from the group consisting of transmission gates, pu/PD triple bear buffers, and tandem tristate buffers. Moreover, the aforementioned negative path, whether the load line 366 between the second buffer or the output of the second three-state buffer is attached to the line 37, may be selected from a metal oxide semi-transistor, Circling lines, capacitors, and resistors - wherein, please continue to refer to FIG. 4, which shows an input of the first tristate buffer in Shai and the preset circuit in the memory circuit according to the present invention. A waveform diagram of an input and a voltage level detected by an output of the predetermined circuit and a power consumption on an output load line of the first tristate buffer. As can be seen from FIG. 4, before the first tristate buffer 364 is activated, that is, before the first waveform (A) in FIG. 4 is raised from a logic low level to a high level, In the second waveform (B) of FIG. 4, a pulse waveform is generated, which represents the generation of the control signal and is transmitted to the first and second MOS transistors in the preset circuit. For simultaneously turning on the first and second MOS transistors, thereby achieving an output load line (ie, the load line 366 in FIG. 3) that generates the pre-voltage to the third-state buffer. Effect. At the same time, when the preset circuit is activated, 'the voltage on the output load line of the first tri-state buffer 15 200931435 will be raised to a voltage level equivalent to the preset voltage, as in the first Figure 4 shows the third waveform (c). When the first three-state buffer is actually activated, that is, when the first low waveform signal is converted into a high potential signal in the first waveform (A), the preset circuit will be turned off, that is, When the pulse waveform in the second waveform (B) ends. In the same time, the voltage level criterion on the line of the output of the first tri-state buffer is further swinged from the voltage level of the original preset voltage to the voltage level of the data signal. It should be further noted that, in the foregoing embodiment, the data 〇 signal is taken as a logical high voltage level, but the data signal may also have a logical low voltage level. In this case, when the first When the tristate buffer is turned on, the voltage of the output load line of the first buffer drops from the voltage level of the preset voltage to the voltage level of the data signal. However, such an operation is completely compatible with the foregoing embodiments, and does not differ from each other. ~ In addition to this, regarding the fourth waveform (D) in Fig. 4, it is a 〇 waveform diagram showing the power consumption occurring in the output load line of the first binary buffer. As can be seen from the fourth waveform (D), each time a voltage change occurs in the output load line of the first tri-state buffer, different levels of power consumption will occur on the carrier line. The extent of these power consumption will depend on the degree of voltage change and the time of the voltage transition. In this embodiment, a total of two power consumption situations occur in the output load line, that is, when the voltage of the output load line is raised from a logic low voltage level to a voltage level of a preset voltage. The resulting power consumption, and the other time is when the voltage of the wheel load line swings from the voltage level of the pre- 16 200931435 voltage to the voltage level of the data signal. However, if the original output load circuit is not directly transmitted through the voltage level of two times, but directly raised from the logic low voltage level to the high voltage level of the data signal, on the output load circuit. The sharp peak of the power consumption generated will increase steeply. This result will result in severe switching noise and severe signal transmission delays, which can lead to erroneous transmission of the nickname in severe cases. The present invention, through the setting of the preset circuit, allows the power consumption of the output load circuit to be dispersed into a plurality of smaller power consumption values to mitigate the effects of unnecessary power consumption. The present invention has been described with reference to the above-described preferred embodiments of the present invention. It is intended that the present invention may be modified and modified in a manner that does not depart from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an equivalent circuit diagram showing a preset circuit in the prior art. © 帛 2 _ Table A block diagram of a memory circuit in accordance with a preferred embodiment of the present invention. Figure 3 is an equivalent circuit diagram of a memory circuit not according to a preferred embodiment of the present invention. Figure 4 is a diagram showing the voltage level detected in the input of the first tri-state buffer and an input of the predetermined circuit and an output of the preset circuit in the memory circuit according to the present invention. A waveform diagram of power consumption on the output load line of the first tri-state buffer. 17 200931435 [Explanation of main component symbols] 1 Output terminal 10, 24 Preset circuit 2 Input voltage 11 > 12 Gold oxide half transistor 3 Ground 15, 16 Differential amplifier 17, 18 Reference voltage 21 > 31 Data signal 22, 23 Tristate Buffer 26, 39 Steady State Power Supply 25 Transmission Path 36 Buffer Device 30 Preset Circuit 363 Output 361, 362 Input 366, 37 Load Line 364 > 365 Tristate Buffer 303 Inverter 304 Input 305 Output End 3 (H, 302 MOS semi-transistor ❹ 18