KR100801058B1 - Signaling circuit reducing skew, Method there-of and System including the circuit - Google Patents

Abstract

A signal transfer circuit, a signal transfer method, and a system having the circuit are disclosed to reduce skew. The signal transmission circuit of the present invention relates to a signal transmission circuit having two or more transmission lines having different delay characteristics by parasitic capacitances of adjacent transmission lines. The signal transmission circuit of the present invention receives a first input signal. A first inverter circuit for generating an inversion signal; A second inverter circuit configured to receive an output signal of the first inverter circuit and generate an inverted signal; And a first control circuit that operates in response to a second input signal and an output signal of the first inverter circuit. The output terminal of the second inverter circuit and the output terminal of the first control circuit are connected by hard wires. By the signal transmission circuit of the present invention, delay times of a plurality of signal transmission lines having different delay characteristics can be accurately synchronized.

Description

Signaling circuit reducing skew, method there-of and system including the circuit

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 shows a configuration of an embodiment of a signal transmission circuit according to the prior art.

2 shows a configuration of an embodiment of a signal receiving circuit according to the prior art.

3 is a diagram showing a system having a signal transmission circuit according to a first embodiment of the invention.

4 shows a configuration of one embodiment of a control circuit according to the first embodiment of the invention.

5 is a view showing a signal transmission circuit according to another embodiment of the present invention.

6 shows the configuration of an embodiment of a timing diagram of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic circuits, and more particularly, to a signal transmission circuit and a signal transmission method for equalizing delay times of signal transmission lines having different delay characteristics.

In the process of transmitting a signal through the signal transmission line, the delay time of the signal varies depending on the characteristics and structure of the signal transmission line, so the delay time also varies. However, in the case of a circuit operating by receiving signals transmitted through a plurality of signal transmission lines as inputs, signals transmitted through the signal transmission lines need to be input at the same time. In particular, when a plurality of signal transmission lines are adjacent to each other, there is a problem that delay times of signal transmission lines do not coincide due to capacitances existing between adjacent signal transmission lines.

1 shows a configuration of an embodiment of a signal transfer circuit according to the prior art. 2 shows a configuration of an embodiment of a signal receiving circuit according to the prior art.

An example of a signal transmission circuit having different delay characteristics in the related art will be described with reference to FIGS. 1 and 2.

Referring to FIG. 1, a signal transmitted to a transmission line when the plurality of transmission lines 130, 131, and 132 are adjacent to each other and the input signals IN1, IN2, and IN3 are simultaneously applied to the plurality of transmission lines 130, 131, and 132. Due to the potential difference of the coupling capacitance is present, thereby causing a difference in the time to reach the first inverter 150, the second inverter 151 and the third inverter 152 as the receiving end. Capacitors 140 and 141 model the coupling capacitance.

In more detail, when the first input signal IN1, the second input signal IN2, and the third input signal IN3 have the same phase, the coupling between each other exerts a synergistic effect. When the delay time is shortened and the phase of the second input signal IN2 is opposite to the first input signal IN1 and the third input signal IN3, the coupling exhibits a delay effect, and thus the transmission line is more than when operating alone. Therefore, the skew generated between signals reduces the setup time and hold time margin in a circuit or device that receives and controls the received signals of the three transmission lines 130, 131, and 132 together. Is degraded. One way to solve this is presented in FIG. 2. In FIG. 2, when the delay time of the second transmission line 131 is shorter than that of the first transmission line 130, inverters 210 and 220 having an appropriate delay time are connected to an output terminal of the second transmission line 131 having a relatively short delay time. In addition, the circuit compensates for the difference in delay time between transmission lines. According to this method, the second transmission line 131 is effective when the delay time is always shorter than that of the first transmission line 130, but the delay time of the transmission line is variably changed, for example, the delay time of the first transmission line 130 is set to zero. If it is shorter than the two transmission lines 131, the time of arrival at the receiving circuits 150 and 151 of the transmission line is changed.

In the past, various other methods have been proposed to solve the present problem, but a circuit having a complicated configuration is required to have the same delay time according to a variable transmission line.

The technical problem of the present invention is to achieve the same transmission time even when the transmission lines to which the output of the signal transmission circuit is transmitted are adjacent to each other and parasitic capacitances exist between the transmission lines, so that signals transmitted to the transmission lines have different delay times due to the capacitance. It is to provide a signal transfer circuit, a signal transfer method, and a system having the signal transfer circuit.

According to an aspect of the present invention, a signal transmission circuit includes: a first inverter circuit configured to receive a first input signal and generate an inverted signal; A second inverter circuit configured to receive an output signal of the first inverter circuit and generate an inverted signal; And a first control circuit that operates in response to a second input signal and an output signal of the first inverter circuit. The output terminal of the second inverter circuit and the output terminal of the first control circuit are connected by hard wires.

The first control circuit includes a first pull-up transistor and a second pull-up transistor connected in series between a first power supply voltage and an output terminal; And a first pull-down transistor and a second pull-down transistor connected in series between the output terminal and the second power supply voltage.

The output signal of the first inverter circuit is input to the gate of the first pull-up transistor and the gate of the second pull-down transistor, and the second input is input to the gate of the second pull-up transistor and the gate of the first pull-down transistor. A signal can be input.

According to another preferred aspect of the present invention, a signal transmission circuit generates an output signal based on a corresponding input signal among a plurality of input signals, and outputs the output signal to a plurality of signal transmission lines. Among them, a plurality of output buffers are transmitted through corresponding signal transmission lines.

The first output buffer of the plurality of output buffers includes a first inverter circuit for receiving a first input signal of the plurality of input signals to generate an inverted signal; A second inverter circuit configured to receive an output signal of the first inverter circuit and generate an inverted signal; And a first control circuit operating in response to a second input signal of the plurality of input signals and an output signal of the first inverter circuit. The output terminal of the second inverter circuit and the output terminal of the first control circuit are connected by hard wires and connected to a first signal transmission line of the plurality of signal transmission lines.

A third inverter circuit of the plurality of output buffers may include a third inverter circuit configured to receive the second input signal and generate an inverted signal; A fourth inverter circuit configured to receive the output signal of the third inverter circuit and generate an inverted signal; And a second control circuit which operates in response to a third input signal of the plurality of input signals and an output signal of the third inverter circuit. The output terminal of the fourth inverter circuit and the output terminal of the second control circuit may be connected by hard wires and connected to a second signal transmission line of the plurality of signal transmission lines.

The first output buffer further includes a second control circuit that operates in response to a third input signal of the plurality of input signals and an output signal of the first inverter circuit, the output terminal of the second inverter circuit, the The output terminal of the first control circuit and the output terminal of the second control circuit may be connected by hard wires and connected to the first signal transmission line.

According to a preferred aspect of the present invention, a signal transmission method includes a first digital signal transmitted through a first signal transmission line and a second signal transmitted through a second signal transmission line adjacent to the first signal transmission line. A signal transfer method for reducing skew between digital signals, the method comprising: supplying additional current to the first signal transmission line in response to the first and second digital signals that transition to opposite logic values, or providing the first signal; Sinking additional current from the transmission line; And in response to the first and second digital signals transitioning to the same logic values, stopping further supply of current to the first signal transmission line or sinking additional current from the first signal transmission line.

Sourcing additional current to the first signal transmission line or sinking additional current from the first signal transmission line may include the first digital signal and the transition from a high logic value to a low logic value; Sinking additional current from the first signal transmission line in response to the second digital signal transitioning simultaneously with a first digital signal but transitioning from the low logic value to the high logic value; Or / and respond to the second digital signal transitioning from the high logic value to the low logic value simultaneously with the first digital signal and the first digital signal transitioning from the low logic value to the high logic value. The method may include providing an additional current to the first signal line.

The signal transmission method may be configured to supply additional current to the first signal transmission line or to receive additional current from the first signal transmission line in response to the first digital signal and the third digital signal transitioning to mutually opposite logic values. Sinking; And in response to the first and third digital signals not transitioning to opposite logic values, stopping further supply of current to the first signal transmission line or sinking additional current from the first signal transmission line. Can be.

A system according to a preferred aspect of the present invention for achieving the above object, the first and second signal transmission line adjacent to each other; Transmitters (signal transmission circuits) for transmitting first and second digital signals through the first and second signal transmission lines; And a receiver (signal receiving circuit) for receiving the second and second digital signals through the first and second signal transmission lines.

The transmitter (signal transmission circuit) comprises: a first driver circuit for transmitting the first digital signal through the first signal transmission line; A second driver circuit for transmitting the second digital signal through the second signal transmission line; And sourcing current from the first signal transmission line or sinking current from the first signal transmission line in response to the first and second digital signals transitioning to opposite logic values. And a sub driver for stopping supply of current to the first signal transmission line or sinking current from the first signal transmission line.

The sub-driver responds to the second digital signal that simultaneously transitions from the low logic value to the high logic value while simultaneously transitioning from the high logic value to the low logic value and the first digital signal. Sinking a current from the first signal transmission line or simultaneously with the first digital signal and the first digital signal that transitions from the low logic value to the high logic value, the low at the high logic value A current may be supplied to the first signal transmission line in response to the second digital signal transitioning to a logic value.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

3 is a diagram illustrating a system including a signal transmission circuit according to an embodiment of the present invention. Referring to this, the system transmits a signal through a plurality of signal transmission lines (eg, first to third signal transmission lines 340, 341 and 342) and signal transmission lines 340, 341 and 342. 31 and a signal receiving circuit 33 for receiving a signal transmitted through the signal transmission lines 340, 341 and 342.

The signal transfer circuit 31 according to an embodiment of the present invention includes a plurality of output buffers 31a, 31b, and 31c. The signal transfer circuit 31 may be referred to as a transmitter and may be provided in the first semiconductor device.

The first output buffer 31a is a first inverter circuit 320 for generating the inverted signal IN1B by receiving the first input signal IN1 received and the output signal IN1B of the first inverter 320. And a second inverter circuit 320 and a first control circuit 310 for generating an inverted signal as an input. The first control circuit 310 generates a first output signal by inputting the received second input signal IN2 and the output signal IN1B of the first inverter circuit 320. The output of the second inverter circuit 330 and the output of the control circuit 310 are connected by hard wires. The second inverter circuit 320 serves as a main driver, and the first control circuit 310 serves as a sub driver. This will be described later in detail.

The configuration of the second and third output buffers 31b and 31c, like the configuration of the first output buffer 31a, includes two inverters and one control circuit, respectively. Operations of the second and third output buffers 31b and 31c are similar to those of the first output buffer 31a, and thus a detailed description thereof will be omitted. The output signal of each output buffer 31a, 31b, 31c is input to the signal receiving circuit 32 via the corresponding signal transmission lines 340, 341, 342.

The signal receiving circuit 32 includes a plurality of inverters 360, 361, 362, 370, 371, 372. The signal receiving circuit 32 may be referred to as a receiver and may be provided in a second semiconductor device (not shown).

The capacitors 350 and 351 model the coupling capacitance between the signal transmission lines.

4 is a diagram illustrating the control circuit 310 according to an embodiment of the present invention.

Referring to this, the control circuit 310 according to an exemplary embodiment of the present invention may include a first pull-up transistor 410 and a second pull-up transistor connected in series between a first power supply voltage VDD and an output terminal 470. 420, a first pull-down transistor 430 and a second pull-down transistor 440 connected in series between the output terminal 470 and the second power supply voltage.
In this case, as illustrated in FIG. 4, the first power supply voltage is 'VDD', and the second power supply voltage is 'GND'. That is, the first power supply voltage is preferably higher than the second power supply voltage.
Meanwhile, in FIG. 4, the first pull-up transistor 410 and the second pull-up transistor 420 are each composed of P-MOS transistors, and the first pull-down transistor 430 and the second pull-down transistor 440 are each N-MOS. An example composed of transistors is shown.

The control circuit 310 having the above configuration receives the signal IN1B and the second input signal IN2 obtained by inverting the first input signal IN1 through the inverter 320. More specifically, the output signal IN1B of the first inverter circuit 320 is input to the gate 450 of the first pull-up transistor and the gate 450 of the second pull-down transistor, and the second pull-up is input. The second input signal IN2 is input to the gate 460 of the transistor and the gate 460 of the first pull-down transistor. The output terminal 470 of the control circuit 310 is simply connected to the output terminal of the second inverter 330 by a hard wire method and is connected to the first transmission line 340.

Since the other control circuits 311 and 312 may also be implemented in the same manner as the control circuit 310 shown in FIG. 4, detailed descriptions of the other control circuits 311 and 312 will be omitted.

Hereinafter, the operation of the control circuit according to an embodiment of the present invention will be described in detail.

In the first case, assuming that the first input signal IN1, the second input signal IN2, and the third input signal IN3 are equally high, the control circuits 310, 311, and 312 are not present. In this case, since the phases of the first input signal IN1 and the second input signal IN2 adjacent to each other are the same, the delay time of the transmission lines 340, 341, and 342 is higher than when the coupling is mutually effective. This shortens. In this case, when the present invention is applied, the inverting signal IN1B of the first input signal of the input of the control circuit 310 becomes a “Low” signal, and the second input signal IN2 of the input of the control circuit 310. Becomes a "High" signal, and the first pull-up transistor 410 and the first pull-down transistor 430 of the control circuit 310 are "turned on" and the second pull-up of the control circuit 310 is connected by a path connected thereto. The transistor 420 and the second pull-down transistor 440 are "turn off" so that the output of the control circuit 310 becomes "high impedance". In addition, the first input signal IN1 transmitted to the transmission line 340 becomes a "High" signal through two stages of the inverters 320 and 330. As described above, the output of the control circuit 310 is "High Impedance". do. The level of the signal transmitted to the transmission line 340 is almost the same as the case without the control circuit 310. Therefore, the delay time for the first input signal IN1, the second input signal IN2, and the third input signal IN3 is almost insignificant.

As a second case, assuming that the first input signal IN1, the second input signal IN2, and the third input signal IN3 are equally "Low", the control circuits 310, 311, and 312 are not present. In this case, the coupling of each other exerts a synergistic effect, and the delay time of the transmission line is shorter than when operating alone. In this case, when the present invention is applied, the inverted signal IN1B of the first input signal among the inputs of the control circuit 310 becomes a “High” signal and the second input signal IN2 of the input of the control circuit 310. Becomes a "Low" signal, and the first pull-up transistor 410 and the first pull-down transistor 430 of the control circuit 310 become "Turn Off" by the path connected, and the second pull-up of the control circuit 310 is performed. The transistor 420 and the second pull-down transistor 440 are "turned on" so that the output of the control circuit 310 becomes "high impedance". In addition, the first input signal IN1 transmitted to the transmission line 340 becomes a "Low" signal through the inverter 320 and 330 circuits. As described above, the output of the control circuit 310 is "High Impedance". Therefore, the level of the signal transmitted to the transmission line 340 is almost the same as the case without the control circuit 310. Therefore, the delay time for the first input signal IN1, the second input signal IN2, and the third input signal IN3 is almost insignificant.

As a third case, assuming that the first input signal IN1 and the third input signal IN3 are "High" and the second input signal IN2 is "Low", the control circuits 310, 320, and 330 If there is no), since the phase of the second input signal IN2 adjacent to the first input signal IN1 is different, the delay time increases due to the coupling. In this case, when the present invention is applied, the inverting signal IN1B of the first input signal of the control circuit 310 becomes a "Low" signal, and the second input signal IN2 of the input of the control circuit 310. The first pull-up transistor 410 and the second pull-up transistor 420 of the control circuit 310 are "turned on" and the first pull-down of the control circuit 310 becomes a "low" signal. The transistor 430 and the second pull-down transistor 440 are “turn off” so that a current path is formed between the output terminal 470 of the control circuit 310 and the first power voltage VDD. That is, additional current is supplied to the output terminal 470, that is, the signal transmission line by the first pull-up transistor 410 and the second pull-up transistor 420. In addition, the first input signal IN1 transmitted to the transmission line 340 becomes a "High" signal through two stage inverter circuits 320 and 330. As described above, the output terminal 470 of the control circuit 310 is also " High "state improves the voltage driving capability to compensate for delayed propagation time. That is, the potential of the transmission line 340 is higher than that without the control circuit 310 so that the potential difference with another transmission line 341 due to the input of the second input signal IN2 decreases, so that the signal delay time due to coupling Will be reduced.

As a fourth case, assuming that the first input signal IN1 and the third input signal IN3 are "Low" and the second input signal IN2 is "High", the control circuits 310, 311, and 312 are used. As described above, since the phases of the first input signal IN1 and the second input signal IN2 adjacent to each other are different from each other, the delay time increases due to the coupling. In this case, when the present invention is applied, the inverted signal IN1B of the first input signal among the inputs of the control circuit 310 becomes a “High” signal, and the second input signal IN2 of the input of the control circuit 310 is applied. The first pull-up transistor 410 and the second pull-up transistor 420 of the control circuit 310 are "turned off" and the first pull-down of the control circuit 310 becomes a "High" signal. The transistor 430 and the second pull-down transistor 440 are "turned on" so that a current path is formed between the output terminal 470 of the control circuit 310 and the second power supply voltage (eg, ground). . That is, additional current is sinked from the output terminal 470, that is, the signal transmission line, to the ground by the first pull-down transistor 430 and the second pull-down transistor 440. In addition, the first input signal IN1 transmitted to the transmission line 340 becomes a "Low" signal through the circuits of the two inverters 320 and 330. As described above, the output terminal 470 of the control circuit 310 is also " Low "state improves the voltage driving capability to compensate for delayed propagation time. That is, the potential of the transmission line 340 is lower than that without the control circuit 310 so that the potential difference with other transmission lines 341 due to the input of the second input signal IN2 is reduced, so that the signal delay time due to coupling is reduced. do.

The operation of the control circuit 310 described above is summarized in Table 1 below.

Case IN1 IN2 410 420 430 440 470 One H H C O C O Hi-Z 2 L L O C O C Hi-Z 3 H L C C O O P 4 L H O O C C G

In Table 1, H is the high logic value ("High"), L is the low logic value ("Low"), C is "Turn-On" O is Turn-Off, and Hi-Z is high impedance. Represent each. P denotes that current is supplied to the signal transmission line by the control circuit 310 and G denotes that current is sinked from the signal transmission line to the ground by the control circuit 310.

Therefore, when the first and second input signals IN1 and IN2 have different logic values, the control circuit 310 operates to supply current to the signal transmission line or sink the current from the signal transmission line. The driving capability of the buffer (eg 31a) is improved.

On the other hand, when the first and second input signals IN1 and IN2 have the same logic value, the control circuit 310 is turned off and the output terminal 470 is in a high impedance state.

Therefore, when the first and second input signals IN1 and IN2 transition to opposite logic values (for example, when transitioning from case3 to case4 or vice versa in Table 1), the control circuit 310 Sourcing additional current to the first signal transmission line 340 or sinking additional current from the first signal transmission line 340.

On the other hand, when the first and second input signals IN1 and IN2 transition to the same logic values (in case3 or case4 to case1 or case2), the control circuit 310 may include the first signal transmission line 340. C) stops supplying additional current or sinks additional current from the first signal transmission line 340 and causes the output terminal 470 to be in a high impedance state.

5 is a diagram illustrating a signal transmission circuit according to another embodiment of the present invention. Referring to this, the signal transmission circuit according to another embodiment of the present invention includes a plurality of output buffers 50a, 50b, 50c.

The output buffer 50b is called a first output buffer for convenience of description. The first output buffer 50b receives a corresponding one of the plurality of input signals IN1, IN2, and IN3, and receives a corresponding input signal IN2 to generate an inverted signal. The first inverter And a second inverter circuit 531 for receiving an output signal of the circuit 521 and generating an inverted signal, and first and second control circuits 510 and 511.

The first control circuit 510 operates in response to another input signal IN1 of the plurality of input signals and an output signal of the first inverter circuit 521. The second control circuit 511 operates in response to another input signal IN3 of the plurality of input signals and an output signal of the first inverter circuit 521.

Each of the first and second control circuits 510 and 511 may be configured in the same manner as the control circuit 310 shown in FIG. 4. Therefore, detailed description thereof will be omitted.

In the signal transmission circuit according to another embodiment of the present invention, the first and second control circuits 510 and 511 are added to one output buffer 50b so as to reduce skew caused by two adjacent transmission lines. And a hard wire connecting the output terminals of the second control circuits 510 and 511 to the output terminals of the second inverter 531.

This is because the second input signal IN2 is connected to the first input signal IN1 and the third input signal IN3 so as to reduce the skew generated in the transmission line by the first input signal and the third input signals IN1 and IN3. This is to reflect the change in the output of the second input signal using the control circuits 510 and 511.

The second and third output buffers 50a and 50c have a similar configuration to a conventional output buffer, each having two inverters.

However, the second and third output buffers 50a and 50c may also be configured in the same manner as the first output buffer 50b.

6 is a diagram illustrating a timing diagram of the present invention shown in FIGS. 1 and 3.

In the drawing, waveforms 610, 611, and 612 are waveforms applied to the input terminal IN1 of the first input signal in FIG. 3 or first input signals IN1 in FIG. 1 are applied to the input terminals of the first output buffer 31a. Waveforms 620, 621, and 622 show the second input signal IN2 in FIG. 3 as the input terminal of the second output buffer 31b or the second input signal IN2 in FIG. 1 as the input of the inverter 111. FIG. Waveforms 630, 631, and 632 are signals that are applied to the terminal, and are signals transmitted to the transmission line by waveforms applied to the input terminal in FIG. 1, which is a conventional signal transmission circuit to which the present invention is not applied, and waveforms 640, 641, and 642 are present inventions. 3 is a signal transmitted to a transmission line by a waveform applied to the input terminal in FIG.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true scope of protection of the present invention should be defined only by the appended claims.

As described above, according to the signal transmission circuit and the signal transmission method of the present invention, delay times of a plurality of signal transmission lines having different delay characteristics can be accurately synchronized.

Claims (22)

A first inverter circuit configured to receive the first input signal and generate an inverted signal; A second inverter circuit configured to receive an output signal of the first inverter circuit and generate an inverted signal; And A first control circuit operating in response to a second input signal and an output signal of the first inverter circuit, The signal transmission circuit of claim 1, wherein the output terminal of the second inverter circuit and the output terminal of the first control circuit are connected by hard wires. The method of claim 1, wherein the first control circuit A first pull-up transistor and a second pull-up transistor connected in series between the first power supply voltage and the output terminal; And A first pull-down transistor and a second pull-down transistor connected in series between the output terminal and a second power supply voltage; An output signal of the first inverter circuit is input to the gate of the first pull-up transistor and the gate of the second pull-down transistor, And the second input signal is input to the gate of the second pull-up transistor and the gate of the first pull-down transistor. 3. The circuit of claim 2, wherein the signal transfer circuit is A third inverter circuit configured to receive the second input signal and generate an inverted signal; And And a fourth inverter circuit for receiving the output signal of the third inverter circuit and generating an inverted signal. The method of claim 3, wherein the signal transmission circuit And a second control circuit operating in response to a third input signal and an output signal of the third inverter circuit. And an output terminal of the fourth inverter circuit and an output terminal of the second control circuit are hardwired. The method of claim 3, wherein the signal transmission circuit And a second control circuit operating in response to a third input signal and an output signal of the first inverter circuit. And the output terminal of the second inverter circuit, the output terminal of the first control circuit and the output terminal of the second control circuit are connected by hardwire. The method of claim 2, The first pull-up transistor and the second pull-up transistor are each composed of P MOS transistors, And the first pull-down transistor and the second pull-down transistor are each composed of N MOS transistors. The method of claim 2, And the first power supply voltage is higher than the second power supply voltage. A plurality of output buffers each generating an output signal based on a corresponding input signal of the plurality of input signals, and transmitting the output signal through a corresponding one of the plurality of signal transmission lines; The first output buffer of the plurality of output buffers A first inverter circuit configured to receive a first input signal among the plurality of input signals and generate an inverted signal; A second inverter circuit configured to receive an output signal of the first inverter circuit and generate an inverted signal; And A first control circuit operating in response to a second input signal of the plurality of input signals and an output signal of the first inverter circuit, And the output terminal of the second inverter circuit and the output terminal of the first control circuit are hardwired and connected to a first signal transmission line of the plurality of signal transmission lines. The method of claim 8, wherein the first control circuit A first pull-up transistor and a second pull-up transistor connected in series between the first power supply voltage and the output terminal; And A first pull-down transistor and a second pull-down transistor connected in series between the output terminal and a second power supply voltage; An output signal of the first inverter circuit is input to the gate of the first pull-up transistor and the gate of the second pull-down transistor, And the second input signal is input to the gate of the second pull-up transistor and the gate of the first pull-down transistor. The method of claim 9, The first pull-up transistor and the second pull-up transistor are each composed of a P-MOS transistor, And the first pull-down transistor and the second pull-down transistor are each composed of N MOS transistors. The method of claim 9, And a driving capability of the first and second pull-up transistors and the first and second pull-down transistors of the first control circuit is smaller than that of the first inverter and the second inverter. 10. The method of claim 8, wherein the second output buffer of the plurality of output buffers A third inverter circuit configured to receive the second input signal and generate an inverted signal; A fourth inverter circuit configured to receive the output signal of the third inverter circuit and generate an inverted signal; And A second control circuit operating in response to a third input signal of the plurality of input signals and an output signal of the third inverter circuit, And an output terminal of the fourth inverter circuit and an output terminal of the second control circuit are hardwired to be connected to a second signal transmission line of the plurality of signal transmission lines. The method of claim 8, wherein the first output buffer is And a second control circuit which operates in response to a third input signal of the plurality of input signals and an output signal of the first inverter circuit. And the output terminal of the second inverter circuit, the output terminal of the first control circuit and the output terminal of the second control circuit are connected by hard wires and connected to the first signal transmission line. A signal transmission method for reducing skew between a first digital signal transmitted through a first signal transmission line and a second digital signal transmitted through a second signal transmission line adjacent to the first signal transmission line, Sourcing additional current from the first signal transmission line or sinking the additional current from the first signal transmission line in response to the first and second digital signals transitioning to opposite logic values; And In response to the first and second digital signals transitioning to the same logic values, stopping supplying additional current to the first signal transmission line or sinking additional current from the first signal transmission line. . 15. The method of claim 14, wherein supplying additional current to the first signal transmission line or sinking additional current from the first signal transmission line In response to the first digital signal transitioning from a high logic value to a low logic value and the second digital signal transitioning from the low logic value to the high logic value simultaneously with the first digital signal. Sinking additional current from the signal transmission line; And In response to the first digital signal transitioning from the low logic value to the high logic value and the second digital signal transitioning from the high logic value to the low logic value simultaneously with the first digital signal; Supplying additional current to the first signal transmission line And at least one step of the method. 15. The method of claim 14, wherein stopping supplying additional current to the first signal transmission line or sinking additional current from the first signal transmission line is performed. When only one of the first digital signal and the second digital signal transitions between the high logic value and the low logic value, an additional current supply to the first signal transmission line or an additional current sinking from the first signal transmission line is caused. And stopping the signal. The method of claim 14, wherein the signal transmission method In response to the first digital signal and the third digital signal transitioning to opposite logic values, sourcing additional current to the first signal transmission line or sinking the additional current from the first signal transmission line. ; And In response to the first and third digital signals that do not transition to the same logic values, stopping supplying additional current to the first signal transmission line or sinking additional current from the first signal transmission line, And the third digital signal is a signal transmitted to a third signal transmission line adjacent to the first signal transmission line. In a signal transfer circuit for reducing skew between signals, A first driver circuit for transmitting the first digital signal through the first signal transmission line; A second driver circuit for transmitting a second digital signal through a second signal transmission line adjacent to the first signal transmission line; And In response to the first and second digital signals transitioning to mutually opposite logic values, sourcing current from the first signal transmission line or sinking current from the first signal transmission line; And a sub-driver for stopping supply of current to the first signal transmission line or sinking current from the first signal transmission line. The method of claim 18, wherein the sub-driver The first signal in response to the first digital signal transitioning from a high logic value to a low logic value and the second digital signal transitioning simultaneously from the low logic value to the high logic value Sinking current from the transmission line, The second digital signal transitioning from the low logic value to the high logic value simultaneously with the first digital signal and the second digital signal transitioning from the high logic value to the low logic value; 1 A signal transmission circuit characterized by supplying current to a signal transmission line. The method of claim 18, wherein the sub-driver is When only one of the first digital signal and the second digital signal transitions between the high logic value and the low logic value, the current supply to the first signal transmission line or the current sinking from the first signal transmission line is stopped. A signal transmission circuit, which maintains its output terminal in a high impedance state. The method of claim 18, The sub driver is a first sub driver, The signal transmission circuit In response to the first and third digital signals transitioning to opposite logic values, sourcing current from the first signal transmission line or sinking current from the first signal transmission line; And a second sub driver for stopping supply of current to the first signal transmission line or sinking current from the first signal transmission line, And the third digital signal is a signal transmitted to a third signal transmission line adjacent to the first signal transmission line. First and second signal transmission lines adjacent to each other; A transmitter for transmitting first and second digital signals through the first and second signal transmission lines; And And a receiver configured to receive the second and second digital signals through the first and second signal transmission lines, The transmitter is A first driver circuit for transmitting the first digital signal through the first signal transmission line; A second driver circuit for transmitting the second digital signal through the second signal transmission line; And Sourcing current from the first signal transmission line or sinking current from the first signal transmission line in response to the first and second digital signals transitioning to mutually opposite logic values; And a sub-driver for stopping current supply to the signal transmission line or current sinking from the first signal transmission line.

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