200925786 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種曝光方法及光罩組件，特別關於一 種光罩對位爆光方法及光罩組件。 【先前技術】 於液晶顯不面板中’利用薄膜電晶體基板上之晝素電 極與彩色濾光片基板中之共同電極配合，輸入不同的電 Ο 壓’可以在晝素電極與彩色；;慮光片基板間產生不同的電 場，可驅動液晶分子產生各種不同轉向角度，以顯示所要 表現的晝面。薄膜電晶體基板的製造方式係藉由一光罩製 程，經過鍍膜、光阻塗佈、曝光、顯影、蝕刻及光阻移除 等步驟，以於一基板上形成所需電路圖案。 請參照圖1所示，其中位於基板2表面的箭頭，為習 知技術中進行曝光製程時，曝光掃描的方向示意圖。基板 2係為一玻璃基板，用以製作複數個尺寸較小的薄膜電晶 〇 體基板21，因此利用一面積大於等於薄膜電晶體基板21 的光罩1上即可完成一個薄膜電晶體基板21的曝光製 程。藉此，利用光罩1經過一次曝光（如圖1中的空心箭 頭方向，其表示曝光掃描方向）即可完成一個薄膜電晶體 基板21之圖案的曝光動作。另外，若基板2的面積大於 光罩1時，則藉由承載基板2的承載台（圖中未顯示）及 光罩1之移動來進行多次曝光（如圖1中的實心箭頭方 向，其表示多個薄膜電晶體基板21的曝光順序），即可於 200925786 基板2上設置多個薄膜電晶體基板21的圖案，再經由切 割即可同時完成多個薄膜電晶體基板21。 ‘ 然而，當液晶顯示面板的尺寸不斷增加，製程上可能 需要複數個光罩才能完成一個薄膜電晶體基板21的曝光 製程。請參照圖2所示，習知之另一種曝光方法係利用同 一個光罩上設計複數個圖形，再將該些複數個圖形以相互 接合的方式（stitch mode)來進行曝光製程。接合方式的 曝光製程係將薄膜電晶體基板31上欲曝光形成的圖案， 〇 區分為中間複數個第一曝光區A1、兩側外圍線路區域（fan out area)的第二曝光區A2及第三曝光區A3。為了形成不 同的曝光區，請參照圖3所示，習知之接合方式所利用的 光罩4係同時具有一第一圖案區Z1、一第二圖案區Z2及 一第三圖案區Z3,而且該等圖案區分別對應設置有複數個 定位點m2。 請參照圖4所示，當利用光罩4對一基板3進行曝光 製程時，由於光罩4上同時具有3個不同圖案區Z1、Z2 〇 及Z3，因此當進行其中一區域（於此以第三曝光區A3為 例）之曝光動作時，則需將光罩4上其他兩圖案區Z卜Z2 以機台的遮光機制B (如斜線部分所示）作遮蔽，以避免 不同圖案區造成干擾，並導致曝光錯誤。 另外，為了確保曝光之位置正確，每次進行曝光前， 設置於光罩4上方的兩個感測元件T1、T2會先檢測基板3 與光罩4上的定位點ml、m2以進行對位。因此，當感測 元件ΤΙ、T2分別檢測到定位點ml、m2重合形成一對位 6 200925786 才示把後’即表示基板3與光罩4的對位完成可進行曝光。 其:’圖4中之實心箭頭方向表示於基板3上曝光形成兩 個薄膜電晶體基板31之圖案時各個不同圖案區域的曝光 順序。 . 然而’感測元件ΤΙ、T2受限於曝光機台的設計，僅 能分別由光罩4的兩端移動到光罩4的中央位置c。當進 打兩側外圍線路區域（於此以第三曝光區A3為例）的曝 光時，由於必須將光罩4上不需曝光之圖案區zi、Z2遮 © 蔽，因此也會使得光罩4上被遮蔽區域的面積大於其整體 面積的一半。如此也造成感測元件T2無法檢測定位點來 進行對位感測，僅能藉由單一感測元件T1來進行對位， 故無法達成準確地對位，如此一來，更會造成兩側外圍線 路的曝光區A2、A3與中央的曝光區A1之間的對位精準 度大幅下降，因而於第一曝光區A1、第二曝光區八2與第 三曝光區A3之區域因沒有對準而產生相互重疊或是具有 ❾严曰1隙等問題，進而於液晶顯示面板上產生接合不均的現象 (stitching mura )，導致產品品質降低。另外，若僅採取曝 .光機台之承載台的步進移動，而不利用定位點ml、m2作 定位，由於承載台步進精度並無法確保兩個曝光區可以準 確地接合，故也會有接合不均的現象。 因此，如何設計一種能準確對位並提高製造效率的光 罩對位曝光方法及光罩組件’已成為重要課題之一。 【發明内容】 200925786 有鑑於上述課題’本發日狀目的為提供—種能準禮對 位並提，製造效率的光罩對位曝光方法及光罩組件。 緣疋’為達上述目的，依本發明之—種光罩對位曝光 方法包含以下步驟：利用„第一光罩之―第一圖⑽於— 基板^光阻層進行曝光，以形成至少一第一曝光區利 用Γ第一光罩之一第二圖案區於光阻層進行曝光，以形成 /第一曝錢，利用第二光罩之—第三圖案區於光阻層進BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and a reticle assembly, and more particularly to a reticle aligning method and a reticle assembly. [Prior Art] In the liquid crystal display panel, 'using the halogen electrode on the thin film transistor substrate and the common electrode in the color filter substrate, input different electric voltages' can be in the pixel electrode and color; Different electric fields are generated between the light sheet substrates, and the liquid crystal molecules can be driven to generate various steering angles to display the desired surface. The thin film transistor substrate is formed by a photomask process, through coating, photoresist coating, exposure, development, etching, and photoresist removal to form a desired circuit pattern on a substrate. Referring to Fig. 1, an arrow on the surface of the substrate 2 is a schematic view of the direction of exposure scanning when the exposure process is performed in the prior art. The substrate 2 is a glass substrate for fabricating a plurality of thin film electro-ceramic substrates 21 having a small size. Therefore, a thin film transistor substrate 21 can be completed by using a mask 1 having an area equal to or larger than the thin film transistor substrate 21. Exposure process. Thereby, the exposure operation of the pattern of the thin film transistor substrate 21 can be completed by one exposure of the mask 1 (in the direction of the hollow arrow in Fig. 1, which indicates the exposure scanning direction). In addition, when the area of the substrate 2 is larger than that of the reticle 1, the exposure is performed by the carrier (not shown) of the substrate 2 and the movement of the reticle 1 (such as the direction of the solid arrow in FIG. 1 , The exposure order of the plurality of thin film transistor substrates 21 is shown, and a plurality of thin film transistor substrates 21 can be formed on the 200925786 substrate 2, and the plurality of thin film transistor substrates 21 can be simultaneously completed by dicing. ‘However, when the size of the liquid crystal display panel is continuously increased, a plurality of masks may be required in the process to complete the exposure process of the thin film transistor substrate 21. Referring to Fig. 2, another conventional exposure method utilizes the same mask to design a plurality of patterns, and then performs the exposure process by stitching the plurality of patterns in a joint mode. The bonding process of the bonding method is to divide the pattern to be exposed on the thin film transistor substrate 31 into a plurality of first exposure regions A1, a second exposure region A2 and a third of the fan out area. Exposure area A3. In order to form different exposure regions, please refer to FIG. 3, the mask 4 used in the conventional bonding method has a first pattern region Z1, a second pattern region Z2 and a third pattern region Z3, and The pattern areas are respectively provided with a plurality of positioning points m2. Referring to FIG. 4, when the substrate 3 is exposed by the reticle 4, since the reticle 4 has three different pattern regions Z1, Z2 〇 and Z3 at the same time, when one region is performed, When the exposure operation of the third exposure area A3 is taken as an example, the other two pattern areas Z and Z2 on the mask 4 are shielded by the shading mechanism B (shown by the oblique line portion) of the machine to avoid different pattern areas. Interference and lead to exposure errors. In addition, in order to ensure the correct position of the exposure, before each exposure, the two sensing elements T1 and T2 disposed above the reticle 4 first detect the positioning points ml, m2 on the substrate 3 and the reticle 4 for alignment. . Therefore, when the sensing elements ΤΙ, T2 respectively detect that the positioning points ml, m2 coincide to form a pair of bits 6 200925786, it means that the alignment of the substrate 3 and the reticle 4 can be performed. It is noted that the direction of the solid arrow in Fig. 4 indicates the exposure order of the respective pattern regions when the pattern of the two thin film transistor substrates 31 is exposed on the substrate 3. However, the sensing elements ΤΙ, T2 are limited by the design of the exposure machine, and can only be moved from the both ends of the reticle 4 to the central position c of the reticle 4, respectively. When the exposure of the peripheral line areas on both sides (herein, the third exposure area A3 is taken as an example), since the pattern areas zi and Z2 which are not required to be exposed on the mask 4 must be shielded, the mask is also made. The area of the shaded area on 4 is greater than half of its overall area. Therefore, the sensing component T2 can not detect the positioning point for the alignment sensing, and can only be aligned by the single sensing component T1, so that the accurate alignment cannot be achieved, and thus, the two sides are even more caused. The alignment accuracy between the exposure areas A2 and A3 of the line and the central exposure area A1 is greatly reduced, so that the areas of the first exposure area A1, the second exposure area 八2 and the third exposure area A3 are not aligned. Problems such as overlapping or having a sturdy 曰1 gap occur, and a staggering mura occurs on the liquid crystal display panel, resulting in deterioration of product quality. In addition, if only the stepping movement of the stage of the exposure machine is adopted, and the positioning points ml and m2 are not used for positioning, since the stepping accuracy of the stage cannot ensure that the two exposure areas can be accurately engaged, There is a phenomenon of uneven bonding. Therefore, how to design a reticle aligning method and a reticle assembly that can accurately align and improve manufacturing efficiency has become one of the important topics. SUMMARY OF THE INVENTION 200925786 In view of the above-mentioned problems, the purpose of the present invention is to provide a reticle aligning exposure method and a reticle assembly capable of achieving alignment and manufacturing efficiency. In order to achieve the above object, a reticle aligning exposure method according to the present invention comprises the steps of: exposing at least one of the first photoresist (the first mask) to the substrate and the photoresist layer to form at least one The first exposure area is exposed to the photoresist layer by using a second pattern region of the first mask to form a first exposure, and the third pattern region of the second mask is used in the photoresist layer.
〇 ，曝光’以形成-第三曝光區。其中，第—曝光區係位於 弟一曝光區與第三曝光區之間。 為達上述目的，依本發明之一種光罩組件，係用於對 基板之一光阻層曝光，光罩組件包含一第一光罩及一第 二光罩’第一光罩係具有一第一圖案區及複數第一光罩定 位‘』4等第—光罩定位點位於第-圖案區之周圍。第二〇 , Exposure 'to form a third exposure zone. Wherein, the first exposure zone is located between the first exposure zone and the third exposure zone. In order to achieve the above object, a photomask assembly according to the present invention is used for exposing a photoresist layer of a substrate, and the photomask assembly comprises a first photomask and a second photomask. A pattern area and a plurality of first mask positions '4' - the mask positioning point is located around the first pattern area. second
鮮係具有-第二圖案區、—第三圖案區以及複數第二Z 軍定位點’該等第二光罩定位點位於第二圖案區與第三圖 案區之間。 一 〃承上所述’依本發明之光罩對位曝光方法及光罩 係將對應第一曝光區的第—圖案區獨立設置於一第一光 罩上’而第-曝光區為基板上中間圖案重覆的區域，可藉 :增加第一圖案區於第—光罩上之面積以減少基板中； 區域的曝光次數’進而縮短製程時間並增加製造效率。另 外’對應基板上兩側外圍線路區域之第二曝光區及第三曝 光區的第二圖案區及第三圖案區，則一同設置於—第二光 罩上，且第二光罩上的定位點係設置於第二圖案區及第三 200925786 圖案區之間1避免兩感測元件無法同時進行光軍對 逆’而造成無法有效對位的問題。因此，本發明除可; =罩對位準確度，亚減少接合不均現象亦可以提高製程效 【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之光 罩對位曝光方法及光罩組件，其中相同元件係以相同標號 〇 表示。不儿 請參照圖5所示，本發明較佳實施例之—種光罩對位 曝光方法係可用於製作一液晶顯示面板之一薄膜電晶體 基板，其包含步驟S1至步驟S3。 請同時參照圖5、圖6A及圖6B所示，步驟S1係為 利用一第一光罩51之一第一圖案區P1於一基板6之一光 阻層61進行曝光，以形成至少一第一曝光區E1。基板6 ❹上係可先利用旋轉塗佈（spin coating)或狹縫式塗佈（slit coating)方式塗佈一光阻層61，而光阻層61的材質例如 為一正光阻材質或一負光阻材質，於此係以正光阻材質為 例作說明。基板6可設置於一承載台（圖中未顯示）上， 以進行X或Y方向的移動。另外，在基板6 土會形成有複 數個第一定位點611、複數個第二定位點612及複數個第 三定位點613 ’於本實施例中，係以8個第一定位點611、 4個第二定位點612以及4個第三定位點613為例作說明， 然其非用以限制本發明。. 200925786 光光罩51上具有―第—圖案區pux及複數個第— 先罩定位點511，於太每 ^ 夂双似弟 ,,,n . y 、本男轭例中，係以4個第一光罩定位 U為例作說明，然其非用以限制本發明。 動作r先:r:;rr行第一曝光區-之曝光 基板6上之各第^ 上之各第—光罩定位點511與 Γ點611對準，並利用二感測元件 Ο ❹ 位，對位完成 方:兩侧移動來_ 則合形成i 1先罩疋位點511與各第一定位點611 ϋ 對位標記M1後，曝光機㈣可進 光巴曝光動作，以於基板6上形成第-曝 先㈣。於本㈣财，係以左右 光 （主要為晝素的區域）、然其非限制性，依不同 可有不同的分區方式。由於第一圖案區P1單獨設 上’故可增大其面積範圍，以減少基板6 膜°例如本實施例中，一個大尺寸的薄 、电曰曰體基板的中間畫素區域只需要二次曝光即可完 1而且’第一光罩51上只有一個第一圖案區P1，因此 -感mTl、T2可同時進行感測’以增進對位精準度。 凊同時參照圖5、圖7 a »同ιτ) π - p 刹m —# -、ϋ 7Α及圖几所不，步驟S2係為 弟一光罩52之一第二圖案區P2於光阻層61進行 曝光’以形成-第二曝光區E2。第二圖案區打及第三圖 案區P3設置於—第二光罩52，且第二光罩定位,點⑵係 200925786 設置於第二圖案區P2及第三圖案區P3之間。因此，當欲 於光阻層61上進行第二曝光區E2之曝光動作時，曝光機 台先以遮光機制B遮蔽不需曝光之第三圖案區P3,且以第 二光罩52上之各第二光罩定位點521與基板6上之各第 二定位點612對準。其中，由於各第二光罩定位點521係 位於第二圖案區P2及第三圖案區P3之間，因此，感測元 件ΤΙ、T2可由兩側移動並對各光罩定位點521同時進行 感測對位，以增加對位的精準度。藉由基板6與第二光罩 Ο 52之相對移動對位，兩者對位完成時會形成一第二對位標 記M2 (如圖7B所示）。當二感測元件ΤΙ、T2分別感測到 第二對位標記M2後，即可進行第二曝光區E2之曝光動 作，以形成第二曝光區E2。 請同時參照圖5、圖8A及圖8B所示，步驟S3係為 利用第二光罩52之第三圖案區P3於光阻層61進行曝光， 以形成一第三曝光區E3。當欲於光阻層61上進行第三曝 光區E3之曝光動作時，曝光機台先以遮光機制B遮蔽不The fresh mask has a second pattern area, a third pattern area, and a plurality of second Z-position points. The second mask positioning points are located between the second pattern area and the third pattern area. According to the present invention, the reticle aligning method and the reticle according to the present invention independently set the first pattern region corresponding to the first exposure region on a first reticle, and the first exposure region is on the substrate The area where the intermediate pattern overlaps can be increased by increasing the area of the first pattern area on the first mask to reduce the number of exposures in the area, thereby shortening the processing time and increasing the manufacturing efficiency. In addition, the second exposure area corresponding to the peripheral line areas on the two sides of the substrate and the second pattern area and the third pattern area of the third exposure area are disposed together on the second photomask, and the positioning on the second mask The point system is disposed between the second pattern area and the third 200925786 pattern area 1 to avoid the problem that the two sensing elements cannot simultaneously perform the opposite direction of the light army and cannot effectively align. Therefore, the present invention can improve the process efficiency by substituting the mask alignment accuracy and sub-reducing the unevenness of the bonding. [Embodiment] The reticle alignment exposure according to the preferred embodiment of the present invention will be described below with reference to the related drawings. Method and reticle assembly, wherein the same elements are denoted by the same reference numerals 。. Referring to FIG. 5, a reticle alignment exposure method according to a preferred embodiment of the present invention can be used to fabricate a thin film transistor substrate of a liquid crystal display panel, which includes steps S1 to S3. Referring to FIG. 5, FIG. 6A and FIG. 6B, step S1 is performed by exposing a photoresist layer 61 of a substrate 6 by using a first pattern region P1 of a first mask 51 to form at least one An exposure area E1. The substrate 6 may be first coated with a photoresist layer 61 by spin coating or slit coating, and the material of the photoresist layer 61 is, for example, a positive photoresist material or a negative The photoresist material is described by taking a positive photoresist material as an example. The substrate 6 can be disposed on a carrier (not shown) for movement in the X or Y direction. In addition, a plurality of first positioning points 611, a plurality of second positioning points 612, and a plurality of third positioning points 613' are formed on the substrate 6 in the embodiment, and eight first positioning points 611, 4 are used in this embodiment. The second positioning point 612 and the four third positioning points 613 are exemplified, but are not intended to limit the present invention. 200925786 The light mask 51 has a "first" pattern area pux and a plurality of first - first cover positioning points 511, in the case of each of the two pairs of brothers, n, y, and the male yoke example, four The first mask positioning U is exemplified, but it is not intended to limit the invention. The action r first: r:; rr line first exposure area - each of the first mask positions 511 on the exposure substrate 6 is aligned with the defect point 611, and the second sensing element is used to ❹ position, The alignment completion side: moving on both sides _ to form i 1 first cover 疋 position 511 and each first positioning point 611 ϋ align mark M1, the exposure machine (4) can enter the light bar exposure action on the substrate 6 Form the first exposure (four). In this (four) fiscal, it is based on the left and right light (mainly the area of the vegetarian), but it is not restrictive, depending on the difference, there may be different ways of partitioning. Since the first pattern region P1 is separately provided, the area of the substrate can be increased to reduce the film of the substrate 6. For example, in the present embodiment, a large-sized thin, intermediate pixel region of the electric substrate only needs to be twice. The exposure can be completed 1 and there is only one first pattern area P1 on the first mask 51, so that the senses mT1 and T2 can be simultaneously sensed to improve the alignment accuracy.凊 Simultaneously referring to FIG. 5, FIG. 7 a » same as ιτ) π - p brake m — # —, ϋ 7Α and the figure, step S2 is the second pattern area P2 of the photomask 52 in the photoresist layer. Exposure is performed 61 to form a second exposure region E2. The second pattern area and the third pattern area P3 are disposed on the second mask 52, and the second mask is positioned, and the dot (2) system 200925786 is disposed between the second pattern area P2 and the third pattern area P3. Therefore, when the exposure operation of the second exposure region E2 is performed on the photoresist layer 61, the exposure machine first shields the third pattern region P3 that is not to be exposed by the light shielding mechanism B, and each of the second mask 52 The second reticle locating point 521 is aligned with each of the second locating points 612 on the substrate 6. Wherein, since each of the second mask positioning points 521 is located between the second pattern area P2 and the third pattern area P3, the sensing elements ΤΙ, T2 can be moved from both sides and the reticle positioning points 521 are simultaneously sensed. Align the alignment to increase the accuracy of the alignment. By the relative movement of the substrate 6 and the second mask 52, a second alignment mark M2 is formed when the alignment is completed (as shown in Fig. 7B). After the second sensing elements ΤΙ, T2 respectively sense the second alignment mark M2, the exposure operation of the second exposure area E2 can be performed to form the second exposure area E2. Referring to FIG. 5, FIG. 8A and FIG. 8B simultaneously, step S3 is performed on the photoresist layer 61 by using the third pattern region P3 of the second mask 52 to form a third exposure region E3. When the exposure operation of the third exposure region E3 is to be performed on the photoresist layer 61, the exposure machine first shields the light by the shading mechanism B.
Q 需曝光之第二圖案區P2後，並以第二光罩52上之各第二 光罩定位點521與基板6上之各第三定位點613對準，其 中，各第二光罩定位點521係位於第二圖案區P2及第三 圖案區P3之間，因此，二感測元件ΤΙ、T2可由兩侧移動 並對各第二光罩定位點521同時進行感測對位，以增加對 位的精準度。藉由基板6與第二光罩52之相對移動對位， 兩者對位完成後會形成一第三對位標記M3 (如圖8B所 示）。當二感測元件ΤΙ、T2分別感測到第三對位標記M3 11 200925786 後，即可進行第三曝光區E3之曝光動作，以形成第三曝 光區E3。藉此，進行兩侧之第二曝光區E2及第三曝光區 E3的曝光動作時，經由第二光罩52即可減少曝光時所需 遮蔽區域的面積，以避免兩感測元件T1、T2無法同時進 行對位感測，而造成無法有效對位的問題。 另外，需注意者，第一曝光區E1、第二曝光區E2及 第三曝光區E3的曝光順序非限制性，可依不同的考量可 有不同的曝光順序，例如亦可先進行兩侧外圍線路的第二 〇 曝光區E2及第三曝光區E3的曝光動作後，再進行第一曝 光區E1的曝光動作。 最後，當所有基板6上的該等曝光區El、E2及E3皆 曝光完成後，即可進行顯影的製程。 需注意者，於本實施例中，第一對位標記Ml (如圖 6B所示）、第二對位標記M2 (如圖7B所示）與第三對位 標記M3 (如圖8B所示）之圖案並非本案重點，可依不同 需求可有不同的設計方式。且三者亦可形成相同之圖案， 〇 端以能使光罩51、52與基板6準確對位為優先考量。 另外，請參照圖9所示，完成大尺寸基板6’之曝光製 程後，再經由切割即可形成多個薄膜電晶體基板，於此以 兩個薄膜電晶體基板為例作說明。因此，可先藉由第一光 罩51來進行第一曝光區E1的曝光（圖9中的實線箭頭方 向係表示曝光第一曝光區E1時，曝光的順序），再藉由第 二光罩52來進行第二曝光區E2及第三曝先區E3的曝光 (圖9中的空心箭頭方向係表示曝光第二曝光區E2及第 12 200925786 ，曝光區E3時，曝光的順序），即可於基板6，上形成兩個 薄膜電晶體基板的圖案。其令，需注意者，曝光順序係非 限制性，依不同設計可有不同的曝光順序。 凊同時參照圖6A及圖7A所示，本發明之一種光罩組 件，係用於對-基板6之—光阻層61曝光，光罩組件包 :第一光罩51及一第二光罩52。第一光罩51係具有一 第圖案區P1及複數第一光罩定位點511，該等第一光罩 定位點511位於第一圖案區？1之周目。第二光罩％係具 Ο有第—圖案區P2及—第三圖案區？3以及複數第二光罩 疋位點52卜該等第二光罩定位點521位於第二圖案區 與第三圖案區P3之間。 —由於光罩組件之第—光罩51及第二光罩52已於前述 貫施例中詳述，於此不再贅述。 /紅所述，依本發明之光罩對料光方法及光罩組件 係將對應第-曝光區的第—圖案區獨立設置於一第一光 ❹罩上’而第-曝光區為基板上中間圖案重覆的區域，可藉 由增加第®案區於第—光罩上之面積以減少基板中間 區域的曝光次數’進而縮短製程時間並增加製造效率。另 外，對應基板上兩側外圍線路區域之第二曝光區及第三曝 光區的第二圖案區及第三圖案區，則一同設置於一第二光 罩上，且第二光罩上的定位點係設置於第二圖案區及第三 圖案區之間，以避免兩感测元件無法同時進行光罩對位减 f’而造成無法有效對位的_。因此，本發明除可提高 光罩對位準確度，並減少接合不均現象亦可以提高製程效 13 200925786 率0 以上所述僅為舉例性，而非為限制性者。任何未脫離 本發明之精神與範轉，而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 【圖式簡單說明】 圖1係為習知之一種曝光方法的工作流程示意圖； .圖2係為習知之另一種曝光方法利用接合方式所形成 ❾的基板示意圖； 圖3係為習知之接合方式曝光方法所利用的光罩示意 圖； 圖4係為習知之接合方式曝光方法的工作流程示意 圖； 圖5係為本發明較佳實施例之光罩對位曝光方法之一 流程圖； 圖6A係為本發明較佳實施例之光罩對位曝光方法之 ® -工作流程示意圖； 圖6B為本發明較佳實施例之光罩對位曝光方法所形 成的第一對位標記示意圖； 圖7A係為本發明較佳實施例之光罩對位曝光方法之 一工作流程示意圖； 圖7B為本發明較佳.實施例之光罩對位曝光方法所形 成的第二對位標記示意圖；. 圖8A係為本發明較佳實施例之光罩對位曝光方法之 14 200925786 一工作流程示意圖； 圖8B為本發明較佳實施例之光罩對位曝光方法所形 成的第三對位標記示意圖；以及 圖9係為本發明較佳實施例之光罩對位曝光方法用於 一較大基板之一工作流程示意圖。 【主要元件符號說明】 1、4 :光罩 〇 2、3、6、6,：基板 21、31 :薄膜電晶體基板 51 :第一光罩 511 :第一光罩定位點 52 :第二光罩 521 :第二光罩定位點 61 :光阻層 611 :第一定位點 ® 612 :第二定位點 613 :第三定位點 Al、E1 :第一曝光區 A2、E2 :第二曝光區 A3、E3 :第三曝光區 B :遮光機制 C :中央位置 ml、m2 :定位點 15 200925786After the second pattern area P2 to be exposed, the second mask positioning points 521 on the second mask 52 are aligned with the third positioning points 613 on the substrate 6, wherein each second mask is positioned. The point 521 is located between the second pattern area P2 and the third pattern area P3. Therefore, the two sensing elements ΤΙ, T2 can be moved from both sides and the second mask positioning points 521 are simultaneously sensed and aligned to increase The accuracy of the alignment. By the relative movement of the substrate 6 and the second mask 52, a third alignment mark M3 is formed after the alignment of the two is completed (as shown in Fig. 8B). After the second sensing elements ΤΙ, T2 respectively sense the third alignment mark M3 11 200925786, the exposure operation of the third exposure area E3 can be performed to form the third exposure area E3. Thereby, when the exposure operation of the second exposure area E2 and the third exposure area E3 on both sides is performed, the area of the shielding area required for exposure can be reduced via the second mask 52 to avoid the two sensing elements T1 and T2. It is not possible to perform the alignment sensing at the same time, resulting in a problem that cannot be effectively aligned. In addition, it should be noted that the exposure order of the first exposure area E1, the second exposure area E2, and the third exposure area E3 is not limited, and different exposure orders may be used according to different considerations, for example, both sides may be first performed. After the exposure operation of the second exposure area E2 and the third exposure area E3 of the line, the exposure operation of the first exposure area E1 is performed. Finally, when all of the exposure areas El, E2, and E3 on the substrate 6 are exposed, the development process can be performed. It should be noted that, in this embodiment, the first alignment mark M1 (shown in FIG. 6B), the second alignment mark M2 (shown in FIG. 7B), and the third alignment mark M3 (as shown in FIG. 8B) The pattern is not the focus of this case, but can be designed according to different needs. And the three can also form the same pattern, and the end is used to make the optical masks 51, 52 and the substrate 6 accurately aligned as a priority. Further, referring to Fig. 9, after the exposure process of the large-sized substrate 6' is completed, a plurality of thin film transistor substrates can be formed by dicing. Here, two thin film transistor substrates will be described as an example. Therefore, the exposure of the first exposure region E1 can be performed first by the first mask 51 (the direction of the solid arrow in FIG. 9 indicates the order of exposure when the first exposure region E1 is exposed), and the second light is used. The cover 52 performs exposure of the second exposure area E2 and the third exposure area E3 (the direction of the hollow arrow in FIG. 9 indicates the order of exposure when the second exposure area E2 and the 12th 200925786, the exposure area E3 are exposed), that is, A pattern of two thin film transistor substrates can be formed on the substrate 6. It is important to note that the exposure sequence is not restrictive and may have different exposure sequences depending on the design. Referring to FIG. 6A and FIG. 7A simultaneously, a photomask assembly of the present invention is used for exposing the photoresist layer 61 of the substrate 6. The photomask assembly includes a first mask 51 and a second mask. 52. The first mask 51 has a first pattern area P1 and a plurality of first mask positioning points 511. The first mask positioning points 511 are located in the first pattern area. 1 of the week. The second mask % tie has the first pattern area P2 and the third pattern area? 3 and a plurality of second reticle 疋 positions 52, the second reticle positioning points 521 being located between the second pattern area and the third pattern area P3. - Since the first photomask 51 and the second photomask 52 of the photomask assembly have been described in detail in the foregoing embodiments, they will not be described again. According to the present invention, the reticle pairing method and the reticle assembly are configured to independently set the first pattern region corresponding to the first exposure region on a first reticle, and the first exposure region is on the substrate. The area in which the intermediate pattern is repeated can reduce the number of exposures in the intermediate portion of the substrate by increasing the area of the first film on the first mask to further shorten the processing time and increase the manufacturing efficiency. In addition, the second exposure area corresponding to the two peripheral line areas on the substrate and the second pattern area and the third pattern area of the third exposure area are disposed together on a second mask, and the positioning on the second mask The dot system is disposed between the second pattern region and the third pattern region to prevent the two sensing elements from simultaneously failing to perform the reticle alignment minus f', thereby causing the _ to be effectively aligned. Therefore, the present invention can improve the alignment accuracy of the mask and reduce the unevenness of the joint, and can also improve the process efficiency. 13 200925786 Rate 0 The above description is merely exemplary and not limiting. Any equivalent modifications or alterations of the present invention are intended to be included within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing the workflow of a conventional exposure method; FIG. 2 is a schematic view of a substrate formed by a bonding method in another exposure method; FIG. 3 is a conventional bonding method. FIG. 4 is a schematic diagram of a working flow of a conventional bonding mode exposure method; FIG. 5 is a flow chart of a photomask alignment exposure method according to a preferred embodiment of the present invention; FIG. 6B is a schematic diagram of a first alignment mark formed by a reticle alignment exposure method according to a preferred embodiment of the present invention; FIG. 7A is a schematic diagram of a first embodiment of a reticle exposure method according to a preferred embodiment of the present invention; FIG. FIG. 7B is a schematic diagram showing a second alignment mark formed by a reticle alignment exposure method according to a preferred embodiment of the present invention; FIG. 8A is a schematic diagram of a working process of a reticle alignment exposure method according to a preferred embodiment of the present invention; A reticle alignment method of a preferred embodiment of the present invention 14 200925786 A schematic diagram of a working flow; FIG. 8B is a third alignment formed by a reticle alignment exposure method according to a preferred embodiment of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 9 is a schematic diagram showing the working process of a reticle alignment exposure method for a larger substrate according to a preferred embodiment of the present invention. [Description of main component symbols] 1, 4: mask 〇 2, 3, 6, 6, : substrate 21, 31: thin film transistor substrate 51: first mask 511: first mask positioning point 52: second light Cover 521: second mask positioning point 61: photoresist layer 611: first positioning point® 612: second positioning point 613: third positioning point A1, E1: first exposure area A2, E2: second exposure area A3 , E3 : third exposure zone B : shading mechanism C : central position ml, m2 : positioning point 15 200925786
Ml :第一對位標記 M2 :第二對位標記 M3 :第三對位標記 P1、Z1 :第一圖案區 P2、Z2 :第二圖案區 P3、Z3 :第三圖案區 S1〜S3 :本發明之光罩對位曝光方法之流程步驟 Τί、T2 :感測元件M1: first alignment mark M2: second alignment mark M3: third alignment mark P1, Z1: first pattern area P2, Z2: second pattern area P3, Z3: third pattern area S1 to S3: present Flow path of the reticle alignment exposure method of the invention Τί, T2 : sensing element
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