200924138 ------------…… 九、發明說明： 【發明所屬之技術領域】 本^明疋有關於一種陣列封裝基板（array package SUbstrate)，且特別是有關於一種球格陣列（ball grid array， - BGA)封襞基板。 • 【先前技術】 ζ) 近年來，隨著電子技術的曰新月異，高科技電子產業 的相繼問世，使得更人性化、功能更佳的電子產品不斷地 推陳出新，並朝向輕、薄、短、小的趨勢設計。目前在半 V體封裝製程中，陣列封裝基板是經常使用的構裝元件之 ，而半導體元件（例如晶片）可對應位於每一陣列基板 上。當半導體元件與陣列基板完成電性連接之後，係以一 封膠（molding compound)包覆每一陣列基板中所有的半 導體元件’以形成陣列封裝型態之晶片封裝結構。最後， 切割每一陣列基板及其對應的封膠體，以形成獨立分開的 〇 晶片封裝單元。 承上所述’在晶片封裝結構微型化之趨勢中，半導體 封裝技術也開始面對高腳數(high pin count)，小間距(fme Pitch)的挑戰，而球格陣列(BGA)封裝即是現今常用於高腳 數、小間距(fine pitch)元件之封裝方式。值得—提的是， 在應用球格陣列(BGA)封裝技術來微型化晶片封裝結構， 以使晶片封裝結構符合小間距(fme pitch)設計的過程中， 由於陣列基板上之焊墊（bonding pad)面積也會隨之縮小， 200924138 口此知球（solder ball)即不易黏附於接觸面積較小之焊塾 表面，焊球即容易自焊墊上脫落，導致產品良率不佳。 習知之另一種技術是利用增加焊球尺寸來使焊球與 焊墊有較大之接觸面積，以改善焊球自焊墊上脫落之問 ' 靖」而，日日片封裝結構在符合小間距（fine pitch)之情況 下，增加焊球尺寸會使得兩相鄰之焊球的間距過小，兩相 鄰之焊球即容易有不當接觸而導致短路之情況發生。因 ζ) 此如何使日日片封裝結構在符合小間距（fine pitch)之情況 下’焊球亦能有效及穩固地黏附於微型化晶片封裝結構之 焊墊表面是一重要課題。 【發明内容】 本發明提供一種陣列封裝基板，其符合小間距(fme pitch)之設計。 本發明提供-種陣列封裝基板，其能解決焊球容易脫 洛的問題。 ^ 、本發明提iH-辦贿裝基板，其包括—圖案化金屬 連接層（patterned metal connecting layer)、多個接替 (connecting pad)、一第一絕緣層(insulating 、多個導 電凸柱(conductive pillar)以及一第二絕緣層。圖案化金屬 連接層具有一第一表面以及一與第一表面相對應之一第二 f面二這些接妓配設於第—表面，而這些導電凸柱是配 »又於第一表面，且這些導電凸柱經由圖案化金屬連接層枭 這些接整電性連接。其中，每一個導電凸柱具有一連接部 200924138 凸柱之連接部與圖案化金屬連 層疋配設與第—表面或是第二 ，且暴露出這些接墊。第二絕 —側，且暴露出每一個導電凸 以及一凸出部，每一個導電 接層相接。此外，第一絕緣 表面共平面之一表面的一側 緣層則是配設於此表面之另 柱之凸出部。 陣列封裝基板更包括多個與 這些焊球配置於這些導電凸200924138 ------------...... IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an array package SUBstrate, and in particular to a ball A ball grid array (BGA) is used to encapsulate the substrate. • [Prior Art] ζ) In recent years, with the rapid development of electronic technology, the high-tech electronics industry has emerged, making more humanized and functional electronic products continue to evolve, and are light, thin and short. Small trend design. Currently, in a semi-V body package process, an array package substrate is a commonly used component, and a semiconductor element (e.g., a wafer) can be correspondingly disposed on each array substrate. After the semiconductor component is electrically connected to the array substrate, all of the semiconductor elements in each array substrate are coated with a molding compound to form an array package type wafer package structure. Finally, each array substrate and its corresponding encapsulant are cut to form separate 〇 wafer package units. In the trend of miniaturization of chip package structures, semiconductor package technology is also facing the challenge of high pin count and small pitch (fme pitch), while the ball grid array (BGA) package is Nowadays it is often used for the packaging of high pitch and fine pitch components. It is worth mentioning that in the application of the ball grid array (BGA) packaging technology to miniaturize the chip package structure, in order to make the chip package structure conform to the fme pitch design, due to the bonding pad on the array substrate ) The area will also shrink. 200924138 The so-called solder ball is not easy to adhere to the surface of the solder joint with a small contact area. The solder ball is easy to fall off from the solder pad, resulting in poor product yield. Another technique is to increase the size of the solder ball to make the solder ball and the pad have a larger contact area, so as to improve the solder ball from the solder pad. The Japanese package structure is in accordance with the small pitch ( In the case of fine pitch, increasing the size of the solder ball causes the spacing between two adjacent solder balls to be too small, and the two adjacent solder balls are liable to have improper contact and cause a short circuit. Because of this, how to make the solder joints of the Japanese and Japanese package structures conform to the fine pitch, and the solder balls can effectively and firmly adhere to the surface of the pad of the miniaturized chip package structure. SUMMARY OF THE INVENTION The present invention provides an array package substrate that conforms to the design of a small pitch (fme pitch). The present invention provides an array package substrate which solves the problem that the solder balls are easily detached. ^, the present invention provides an iH-plated package substrate, which includes a patterned metal connecting layer, a plurality of connecting pads, a first insulating layer (insulating, a plurality of conductive studs (conductive a pillar and a second insulating layer. The patterned metal connecting layer has a first surface and a second f-plane corresponding to the first surface. The contacts are disposed on the first surface, and the conductive bumps are The arrangement is further on the first surface, and the conductive bumps are electrically connected via the patterned metal connection layer, wherein each of the conductive protrusions has a connection portion 200924138, a connection portion of the protrusions and a patterned metal layer The first surface or the second surface is exposed, and the pads are exposed. The second side is exposed, and each of the conductive protrusions and a protrusion is exposed, and each of the conductive layers is connected. Further, the first One edge layer of one surface of the coplanar surface of the insulating surface is a protrusion of another pillar disposed on the surface. The array package substrate further includes a plurality of solder balls disposed on the conductive bumps
Ο 在本發明之一實施例中 這些導電凸柱相對應之焊球 柱之凸出部。 化声實施例中，陣列封裝基板更包括一抗氧 化層，其覆盍母一個導電凸柱之凸出部。 錫居在之—實施例中’抗氧化層為—鎳金層、金層、 賜層、或銅層。 镇日狀—實施财，圖案化金屬連接層之材質為 鎳（Νι)或鎳鉻(Ni_c〇。 ^本發明之—實補巾，這些接墊之材質為銅（Cu)。 本發明之—實施例中，這些導電凸柱之材質為銅。 發月之陣列封裝基板具有與接整電性連接之導電 凸柱。每-個導電凸柱之凸㈣是外露於第二絕緣層外， =出部相較於習知之焊塾有較大之外露面積。因此，當 1配置於這些導電凸㈣，_與凸出部之間即有較大 ^接觸面積，焊球即可有效且穩固地連接於導電凸柱上。 方面’由於焊球與凸出部之間有較大之接觸面積，因 ^㈣距(fine pitch)之設計中，焊球亦仍能穩固地 於導電凸柱上。 200924138 為讓本發明之上述特徵和優 舉較佳實施例，並配合所_式，作詳細說日ii下了文特 【實施方式】 目1緣示本發明一實施例 請參考圖卜本實施例之陣列_基板 .=是⑼的，體科。陣列封裝基板獅主要2二 Ο 疋鎳或是鎳鉻的圖案化金屬連接層UG(圖案化 接層一？」列如是蝕刻阻障層)、多個材質例如是銅之 ，弟—絕緣層13G、多個材質例如是銅的導電凸 柱140以及一第二絕緣層15〇。 凸 屬連接層m具有中’圖案化金 八另罘表面110a以及一與第一#而 =相對應之-第二表面⑽，這些接塾12G是配設= =面卜U二上’十而這些導電凸柱140是配設於第二表面 110b上。如此一來，這些導電凸柱14Q即可經由_化金 屬連接層110與這些接墊120電性連接。 、〃这些 In one embodiment of the invention, the conductive studs correspond to the projections of the solder ball posts. In an embodiment, the array package substrate further includes an anti-oxidation layer covering the protrusion of one of the conductive posts. Tin is in the embodiment - the antioxidant layer is a nickel gold layer, a gold layer, a layer, or a copper layer. The shape of the town is realized. The material of the patterned metal connecting layer is nickel (Νι) or nickel chrome (Ni_c〇. ^ The present invention is a solid patch, and the material of these pads is copper (Cu). In an embodiment, the conductive studs are made of copper. The array of the lunar array has a conductive stud connected to the electrical connection. The convex (four) of each of the conductive studs is exposed outside the second insulating layer. The outer part has a larger exposed area than the conventional soldering iron. Therefore, when 1 is disposed on the conductive protrusions (four), there is a large contact area between the _ and the protruding portion, and the solder ball can be effectively and stably Connected to the conductive stud. Aspect 'Because of the large contact area between the solder ball and the protrusion, the solder ball can still be firmly on the conductive stud in the design of the fine pitch. 200924138 In order to make the above-mentioned features and preferred embodiments of the present invention, and in conjunction with the formula, the details are described below. [Embodiment] FIG. 1 shows an embodiment of the present invention, please refer to FIG. Example array_substrate.=Yes (9), body. Array package substrate lion main 2 Ο 疋 nickel or The nickel-chromium patterned metal connection layer UG (patterned layer one? column) is an etch barrier layer, a plurality of materials such as copper, a mother-insulating layer 13G, and a plurality of materials such as copper conductive pillars 140 And a second insulating layer 15 〇. The convex connecting layer m has a middle 'patterned gold eight 罘 surface 110a and a second surface (10) corresponding to the first # and =, these interfaces 12G are configured = The conductive pillars 140 are disposed on the second surface 110b. The conductive pillars 14Q can be electrically connected to the pads 120 via the metallization layer 110. 〃
Lj 、θ此外，第-絕緣層13G則是配設於與第-表面110a 或是第二表面共平面之一表面s的—側，且會暴露出這些 接塾120(圖1繪示第一絕緣層13〇配設於與第一表面施 共平面之-表面S的-側）。因此，例如是晶片的半導體 兀件即可藉由這些接墊12〇來與陣列封襄基板刚電性連 接’以傳遞電性訊號。另外，第二絕緣層15〇則是配設於 此表面S之另一側，且會暴露出每—個導電凸柱m〇之部 分柱體。更詳細地說，本實施例之導電凸柱刚是由一連 200924138 接部142以及一凸出部144所組成。其中，每一個導電凸 柱M0之連接部H2會與圖案化金屬連接層ιι〇相接，而 凸出部144則是會暴露於第二絕緣層15〇外。上述第—絕 、緣層13G以及第二絕緣層15G的材質例如是聚酿亞胺 (polyimide，PI)或是其他適當之絕緣材質。 值得-提的是，由於每一個導電凸柱14〇之凸出部144 • ^外露於第二絕緣層150外，且凸出部144相較於習知之 〇 焊墊有較大之外露面積。因此，每一個導電凸柱140之凸 出部144即適於有效地與焊球相接，進而讓焊球穩固地固 接於凸出I44上。為能更清楚地了解導電凸柱⑽盘焊 球搭配之實施方式，本文將再舉另—實施例作說明，、 圖2即!會示本發明另一實施例的陣列封裝基板的示意 Θ本貝知例之陣列封裝基板1〇〇’與上述實施例之陣列封 裝基板100類似，惟二者主要差異在於本實施之陣列封裝 基板·更包括多個與這些導電凸柱刚相對應之焊球 16〇’攻些焊球16〇即是配置於這些導電凸柱140之凸出部 〇 =4。其中，由於凸出部144相較於習知之焊墊有較大之^ 露面積，以供焊球160附著，因此本實施例之焊球160可 有效且穩固地連接於導電凸柱140上。 另外，由於本實施例是藉由凸出部144與焊球16〇之 間有較大之接觸面積來使焊球160穩固地附著於導電凸柱 140,上，因此在適當地縮減兩相鄰導電凸枉間之間距，且 適當縮減焊球尺寸之情況下，亦Μ造成兩相鄰之焊 球不當接觸以及焊球160自凸出部144上脫落。亦即，本 IT、In addition, the first insulating layer 13G is disposed on the side of the surface s which is coplanar with the first surface 110a or the second surface, and the contacts 120 are exposed (the first is shown in FIG. 1) The insulating layer 13 is disposed on the side of the surface S that is coplanar with the first surface. Therefore, for example, the semiconductor components of the wafer can be electrically connected to the array package substrate by these pads 12' to transmit electrical signals. In addition, the second insulating layer 15 is disposed on the other side of the surface S, and exposes a portion of each of the conductive studs m〇. In more detail, the conductive stud of this embodiment is composed of a joint of the 200924138 joint 142 and a projection 144. Wherein, the connecting portion H2 of each of the conductive posts M0 is in contact with the patterned metal connecting layer ιι, and the protruding portion 144 is exposed to the outside of the second insulating layer 15. The material of the first insulating layer 13G and the second insulating layer 15G is, for example, polyimide (PI) or other suitable insulating material. It is worth mentioning that since the protruding portions 144 of each of the conductive studs 14 are exposed outside the second insulating layer 150, the protruding portions 144 have a larger exposed area than the conventional solder pads. Therefore, the projections 144 of each of the conductive studs 140 are adapted to effectively contact the solder balls, thereby allowing the solder balls to be firmly fixed to the projections I44. In order to more clearly understand the embodiment of the conductive stud (10) disk solder ball collocation, another embodiment will be described herein, and FIG. 2 is a schematic diagram showing an array package substrate according to another embodiment of the present invention. The array package substrate 1' is similar to the array package substrate 100 of the above embodiment, but the main difference between the two is that the array package substrate of the present embodiment further includes a plurality of solder balls corresponding to the conductive bumps. 16〇' attacking some of the solder balls 16 is the protrusion 〇=4 disposed on these conductive posts 140. In this case, since the protruding portion 144 has a larger exposed area than the conventional solder pad for the solder ball 160 to be attached, the solder ball 160 of the embodiment can be effectively and stably connected to the conductive bump 140. In addition, since the solder ball 160 is firmly attached to the conductive bump 140 by the large contact area between the protruding portion 144 and the solder ball 16A, the two adjacent portions are appropriately reduced. In the case where the distance between the conductive bumps is appropriately reduced and the size of the solder ball is appropriately reduced, the adjacent solder balls are improperly contacted and the solder balls 160 are detached from the protruding portion 144. That is, this IT,
Lj 200924138 實施例可適當地縮減兩相鄰導電凸 焊球160尺寸，以使陣列封梦 以及細減 ρ滅)之輯。 峨基板⑽D、fa_ne 凊接者同時參考圖1食网〇 _如圖！所示）或是刚，（=1為使陣闕裝基板 能力，本㈣會於触12G ^ 有較佳之抗氧化 它以及每一個導電凸柱140之Λ 出部144上覆蓋一抗氧化層ι7〇 以及蕭之抗氧化能力。其中，封f基板100 金層、金層、錫層、或是銅層抗乳化層170例如為一鎳 綜上所述’本發暇在陣酸裝基板中設置多個 ，電性連接之導電凸柱，且每—鱗電 是 5第二絕緣層外。其令，由於凸出部相較於二塾卜 積，以供焊球附著，因此焊球可有效且穩 固地連接於導電凸柱上，而不易有職之情況發生。 另一方面，由於本發明是藉由凸出部有較大之外露面 ，焊球穩固地連接於導電凸柱上，因此本 導電凸柱間距，且縮減焊球尺寸，以使^ 歹j封裝基板更符合小間距之設計。 ，然本發明已以較佳實施例揭露如上，然其並非用以 二本發明，任何所屬技術領域巾具有通常知識者，在不 =發明之精神和範圍内’當可作些許之更動與潤飾， 2本發明之保魏圍#視_之申請專圍所界定者 200924138 【圖式簡單說明】 圖1繪示本發明一實施例之陣列封裝基板的示意圖。 圖2繪示本發明另一實施例的陣列封裝基板的示意 圖。 【主要元件符號說明】 100、100’ ：陣列封裝基板 110 :圖案化金屬連接層 110a :第一表面 120a :第二表面 120 :接墊 130 :第一絕緣層 140 :導電凸柱 142 :連接部 144 :凸出部 150 :第二絕緣層 160 :焊球 170 :抗氧化層 S :表面 11The embodiment of Lj 200924138 can appropriately reduce the size of two adjacent conductive bumps 160 to make the array seal and reduce the ruthenium.峨Substrate (10)D, fa_ne Adapters refer to Figure 1 food net _ _ Figure! Shown) or just, (=1 is to make the substrate capacity of the array, this (4) will have a better anti-oxidation at the touch of 12G^ and an anti-oxidation layer ι7 on the exit portion 144 of each of the conductive posts 140 〇 and Xiao's antioxidant capacity. Among them, the f-substrate 100 gold layer, gold layer, tin layer, or copper layer anti-emulsification layer 170 is, for example, a nickel-sand on the above-mentioned hairpin. , electrically connected conductive studs, and each scale is 5 outside the second insulating layer. Therefore, since the protruding portion is compared with the second, for the solder balls to adhere, the solder ball can be effectively and stably The ground is connected to the conductive stud and is not easy to be used. On the other hand, since the present invention has a large exposed surface by the protruding portion, the solder ball is firmly connected to the conductive stud, so the conductive bump The column spacing is reduced, and the size of the solder ball is reduced, so that the package substrate is more suitable for a small pitch design. However, the present invention has been disclosed in the preferred embodiment as above, but it is not used in the present invention, and any technical field is disclosed. Those who have the usual knowledge, not in the spirit and scope of the invention' 2 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 A schematic diagram of an array package substrate according to another embodiment of the present invention is shown. [Main component symbol description] 100, 100': array package substrate 110: patterned metal connection layer 110a: first surface 120a: second surface 120: pad 130: first insulating layer 140: conductive stud 142: connecting portion 144: protruding portion 150: second insulating layer 160: solder ball 170: oxidation resistant layer S: surface 11