TW200924137A - Chip package carrier, chip package and method for fabricating the same - Google Patents

Abstract

A chip package including a circuit substrate, at least a chip, and an encapsulant is provided. The circuit substrate includes a conductive pattern, a circuit layer, a dielectric layer, and a plurality of conductive via structures. The conductive pattern includes a plurality of pads. The circuit layer is disposed over the conductive pattern. The dielectric layer is disposed between the conductive pattern and the circuit layer. The dielectric layer exposes the bottom surface of the pads entirely and covers the surface of the pads except the bottom surface. The dielectric layer has a plurality of blind holes. The conductive via structures are disposed in the blind holes separately. The conductive pattern is connected with the circuit layer by the conductive via structures. The chip is disposed on the circuit substrate. The encapsulant packages the chip. A method for fabricating chip package and a chip package carrier are also provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and, more particularly, to a chip package carrier, a chip package, and a method of fabricating the same. [Prior Art]

Today's semiconductor technology is developed, with many wafers having a large and dense array of transistor elements and a number of pads disposed on the surface of the wafer. In order to package these wafers, these wafers are typically mounted on a chip package carrier to form a chip package, while current wafer packages are typically copper cl substrates (Copper Clad Laminate). , CCL). 1A to 1E are flowcharts showing a manufacturing method of a conventional wafer package body. Please refer to FIG. 1A and FIG. 1B for the manufacturing method of the conventional chip package.

Includes the following steps. First, a copper foil substrate 110 is provided which includes a dielectric core layer 112 and a non-layered germanium foil 114' disposed on opposite sides of the dielectric core layer 112, respectively. Next, the copper foil substrate 11 is sequentially subjected to mechanical drilling, electroless plating, electroplating, and etching to form a copper circuit layer 114 and conductive vias T, wherein the copper layers 114 are It consists of a plurality of traces n4a, a plurality of crystals M and a plurality of solder ball pads 114c. Referring to Fig. 1C, afterwards, on these copper wiring layers 114, respectively, a second solder resist layer 12 is formed, and these anti-plating layers 12 暴露 expose the 曰a 200924137 chip pads 114b and the solder ball pads 114c. Next, a nickel gold layer 13 is formed on each of the wafer pads 114b and the respective solder ball pads ii4c. After the formation of the nickel gold layer 130, the conventional wafer package carrier 1a has been completed. Referring to FIG. 1D, a wafer 140 is adhered to one of the solder resist layers 120, and the wafers 14 are electrically connected to the die pads 114b by wire bonding. Thereafter, the package 140 is coated with a package of resin 140 and a plurality of wires 15 connected between the wafer 14 and the wafer pads U4b f. Referring to FIG. 1E, a ball 170 is formed on the solder ball pads 114c. After these fresh balls 170 are formed, unit singulation is performed. Thus, a single chip package 1 〇〇 has been completed. Portable electronic devices such as mobile phones, personal digital assistants (PDAs), and digital cameras, which are currently used by modern people, are moving toward a trend toward diversification and volume miniaturization. In order to enable the chip package 100 to be accommodated in a portable electronic device that is compact in size, and to enable the portable electronic device to accommodate more electronic components, the crystal (: chip package body is oriented toward a thinner feature) For this reason, various companies and companies are now developing a thinner copper foil substrate 110. However, once the thickness of the copper foil substrate 110 becomes too thin, the copper foil substrate 110 becomes very fragile, so that it is easy Therefore, the copper foil substrate 110 having a thin thickness cannot be manufactured by using the existing production equipment in accordance with the current manufacturing process (as shown in FIG. 1A to FIG. 1E), and must be manufactured by using special production equipment. However, This special production equipment is very expensive, and the thin copper foil substrate 110 is very fragile and can be easily crushed, punctured or broken by the machine. 200924137 WV/1. *f i.· VAW V>/ ix The invention provides a wafer package board for mounting a wafer. The present invention provides a wafer seal attack. It has a thinner thickness.

The present invention provides a method of fabricating a chip package capable of reducing the thickness of a wafer package. 1 I invention proposes a small ~ 1 q clothing hair, its envelope 咏 tower storm board, to the sound, and - package colloid 'the towel circuit substrate includes - conductive pattern 槿 1 a circuit layer, - the first dielectric layer and more The first conductive blind via conductive pattern layer comprises a plurality of first pads, wherein each of the first and second sides: a bottom surface. The first circuit layer is disposed above the conductive pattern layer, and the first dielectric layer is disposed between the conductive pattern layer and the first circuit layer, wherein the Sth bottom and the second bottom are opposite to the bottom surface of the first The surface, and the first electrical layer that does not cover the layer, extends from the first circuit layer to the conductive pattern. The ninth-child-conductive blind hole structure is respectively disposed in these connections: the line: the second L layer through the first The conductive blind hole structure is connected to the base. Sealing the "on the circuit substrate" and electrically connecting the wiring body on the circuit substrate and covering the wafer. The conductive bumps ίτττ, 'the above chip package further includes a plurality of," and the conductive bumps are respectively connected to the present In one embodiment of the invention, the conductive pattern layers are composed of the first pads of 200924137. In the embodiment of the invention, the surfaces of the first dielectric layers are substantially aligned. In one embodiment of the invention, the first circuit layer is connected, and the wafer is electrically connected to the second via pads. In the embodiment of the present invention, the wafer is sealed. The key is 'line' and the wafer is passed through the bonding wires. In the embodiment of the present invention, the wafer is sealed. The solder layer covers the first circuit layer and exposes the first circuit line. 3: In the embodiment, the circuit board further includes i;: the line ^; the electric layer is a second conductive blind structure, and the .s is disposed above the first circuit layer, and the second dielectric Thick brother - / circuit layer and second line The second blind hole extending from the second dielectric layer to the first layer is disposed in the second blind hole, and the second second: the second conductive hole is connected. The first circuit layer. The layer is moved through the second embodiment. The second circuit layer includes a plurality of the first plurality of the second plurality of the same, and the second substrate is electrically connected to the second substrate. The layer 'and the solder mask layer is lighter than the second circuit layer, and exposes the money. ^ The solder mask is also proposed. The chip package carrier board includes the second picture: the substrate is disposed on the carrier substrate, = Conductive blind hole structure, _s office

200924137

Z^66UlWI.UOU/U first pads, which are completely covered. The first circuit layer is disposed on the conductive pad, the bottom of the opposite carrier substrate is disposed above the conductive pattern layer and the first layer, and the first dielectric layer and the carrier substrate, and between the first layer and the conductive pattern layer, And the first layer of the tail layer-W layer does not cover the surface of the bottom dielectric layer of the first pad other than the bottom surface of the pad. One died;? 4 夕 攸 攸 线路 线路 线路 线路 线路 线路 线路 线路 线路 线路 导电 导电 导电 导电 导电 导电 导电 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第In an embodiment, the carrier substrate includes a first material, a second material disposed between the first material layer and the conductive pattern layer, in the embodiment of the present invention, the first material The material of the layer includes metal or ceramic. In an embodiment of the invention, the material of the first material layer comprises copper, Ming or Ming copper alloy. In an embodiment of the invention, the material of the second material layer comprises a metal or a polymer material. In an embodiment of the invention, the material of the second material layer comprises nickel. In one embodiment of the invention, the conductive pattern layers are comprised of the first pads. In an embodiment of the invention, the chip package carrier further includes a solder resist layer, and the first circuit layer includes a plurality of second pads. The solder mask covers the 10th 200924137 /456UlWl.a〇C/n circuit layer and exposes these second pads. ο

In an embodiment of the invention, the circuit substrate further includes a second circuit layer, a second dielectric layer, and a plurality of second conductive blind via structures. The second circuit layer is disposed above the first circuit layer, and the second dielectric layer is disposed between the second circuit layer and the second circuit layer, wherein the second dielectric layer has a plurality of extending from the second circuit layer to the first The second blind hole of a circuit layer. These second conductive = hole = components are placed in these second blind vias, and the second wiring layer is connected to the first wiring layer through these second conductive blind via structures. In an embodiment of the invention, the chip package carrier further includes a solder resist layer, and the second circuit layer includes a plurality of second pads. The lining covers the second circuit layer' and exposes these second pads. The present invention further provides a method of fabricating a chip package. First, the carrier substrate and a layer of conductive material disposed on the carrier substrate are removed. The layer of conductive material is patterned to form a conductive pattern layer, wherein the layer comprises a plurality of first-junctions. Next, the circuit substrate is formed on the substrate, and the wafer is placed on the circuit substrate. Next, an encapsulant is formed on the circuit substrate, and the sealant encapsulates the wafer in J. Next, the carrier substrate is removed. </ RTI>, the invention of #财, after the removal of the shingle board, the package name is a plurality of conductive bumps connecting the first pads. The method of removing the carrier substrate includes performing an etching process on the carrier substrate. In the present invention, the carrier substrate includes a first phase 4 layer and a second material disposed between the first material layer and the conductive material layer 11 200924137 厶*+ut) υ l vy i. The layer of the second layer is different from the layer of the conductive material. In an embodiment of the invention, the material of the first material layer comprises metal or ceramic. In an embodiment of the invention, the material of the first material layer comprises copper or ruthenium. In an embodiment of the invention, the material of the second material layer comprises a metal or a south molecular material.

In an embodiment of the invention, the material of the second material layer comprises nickel. In one embodiment of the invention, the method of removing the carrier substrate includes stripping the &quot;&quot; material layer. In one embodiment of the invention, the method of electrically connecting a wafer to a wiring substrate includes wire bonding. Then, in one embodiment of the present invention, the method of forming a circuit substrate includes: first, forming a first dielectric layer on the carrier substrate, wherein the first dielectric layer covers the carrier substrate and the conductive pattern layer. Next, a first conductive layer is formed on the first dielectric layer. Next, a plurality of first-blind holes are formed, wherein the first-blind holes extend from the first conductive layer to the conductive pattern layer. And a plurality of conductive blind holes are formed in the first conductive holes in the first blind holes to form a first circuit layer. In an embodiment of the invention, the method of forming the first dielectric-electrically conductive layer comprises laminating a back-coated copper ‘

Coated Copper, RCC) is on the carrier substrate. - Blind holes are formed by lasers in one embodiment of the invention, which are formed by the above-mentioned 12th 200924137 j. drilling process or electric path. The method includes the above-mentioned method of forming the first-blind hole of the above-mentioned 盲---------------------------------------------------------------------------------------------------------------------------------------------------------- The circuit layer includes: firstly, a method of forming a 人 'man's upper handle into a circuit substrate is further formed—a second conductive electric layer is on the first circuit layer. Then, a blind hole is formed on the t-dielectric layer. Then, forming a plurality of second contacts: forming a plurality of first guides, extending to the first line, and then removing portions of the second second blind holes. The conductive layer is formed by the second dielectric layer and the second is pressed —# glue copper falls on the bearing plate. The hole reading process or the electric process is formed. The eye hole is covered by the laser method: ii (4) In the example, the above-mentioned second blind hole is formed by the second brother; Performing the exposure and development process. The line is slightly overlaid. In the example, the method further includes forming a -p layer in the second layer, wherein the solder resist layer partially covers the second circuit layer. Solid, = the above-mentioned 'the money of the present invention The brittle circuit substrate becomes firm | the physical energy of the package substrate is not easily damaged. Therefore, the production of the wafer package body J of the present invention In this way, the wafer of the present invention is sealed to reduce the thickness of the package. Since it is not required to be manufactured by special production equipment, it can improve the yield. In addition, by carrying the substrate from the 13 200924137 circuit substrate In addition, the present invention can produce a thinner chip package to meet the development trend of today's portable electronic devices. ~ To make the above features and advantages of the present invention more apparent, some embodiments are described below. 2A is a cross-sectional view of a chip package according to an embodiment of the present invention. Referring to FIG. 2A, the chip package 200a includes a circuit substrate 300a. A chip 210 and an encapsulant 220, wherein the circuit substrate 300a shown in FIG. 2A has a two-layer circuit structure. In detail, the circuit substrate 300a includes a conductive pattern layer 31, a first circuit layer 320a, and a first dielectric layer. The electrical layer 330 and the plurality of first conductive via structures 340a. The conductive pattern layer 310 includes a plurality of first interfaces 312, and each of the pads 312 has a bottom surface B. In this embodiment The conductive pattern layer 310 may include only the first pads 312. That is, the conductive pattern layers 310 are composed of the first pads 312. The first circuit layer 320a is disposed above the conductive pattern layer 310, and The electrical layer 330 is disposed between the conductive pattern layer 31A and the first wiring layer 32A. The first dielectric layer 330 has a plurality of first-blind holes 332 extending from the first wiring layer 320a to the = pattern layer 310. The first dielectric layer 33 covers the surface other than the bottom surface B of the first pads 312, and has no bottom surface B. In the above embodiment, the bottom surface B of the first pads 312 and the first surface The surface 334 of the w electrical layer 330 is substantially aligned. However, these 14th 200924137 pads 312 may also be out of line with the surface 334 of the first dielectric layer 330. For example, the first pads 312 may be recessed on the surface 334 of the first dielectric layer 330 because of its thin thickness. .曰

The conductive-type blind via structures 340a are respectively disposed in the first via holes 332, and the conductive pattern layer 310 is connected to the first wiring layer 320a through the first conductive blind via structures 340a. These first conductive blind via structures 34A &amp; may be located above the first pads 312, i.e., the first conductive via structures 340a may be vias in the pacj. These first conductive blind via structures 340a can be conformally formed in these first blind vias 332, respectively (as shown in Figure 2). Of course, these first conductive blind via structures 34 may be conductive pillars that fill the first blind vias 332. The wafer 210 is disposed on the circuit substrate 3A and electrically connected to the wiring substrate 300a. In this embodiment, the wafer 21A can be adhered to the circuit substrate 3, as described above, and the first circuit layer 320a includes a plurality of second pads 322 and a plurality of traces 324 through which the wafers 210 pass through the second pads 322. The circuit board 300a is connected. There are many methods for electrically connecting the wafer 210 to the wiring substrate 3A. The wafer 210 shown in Fig. 2A is electrically connected to the wiring substrate 300a by wire bonding. In detail, the chip package 2A further includes a plurality of bonding wires W, and the wafer 210 is connected to the second pads 322 through the bonding wires w to electrically connect the circuit substrates 3A. In addition to the above-described method of wire bonding, the wafer 21 can also be in the form of a flip chip or other method of electrically connecting the circuit board lion 15 200924137. Therefore, it is emphasized herein that FIG. 2A is merely illustrative and does not limit the method of electrically connecting the wafer 210 to the circuit substrate 300a. The encapsulant 220 is disposed on the circuit substrate 300a and covers the wafer 210. When the wafer 210 is electrically connected to the circuit substrate 3A by wire bonding, the encapsulant 220 not only covers the wafer 210, but also covers the bonding wires W' to ensure that the wafer 210 can be electrically connected to the circuit normally. The substrate 30〇a avoids the occurrence of short circuits and open circuits.

The chip package 200a may further include a plurality of conductive bumps 23, and the conductive bumps 230 are respectively connected to the first pads 312. In detail, the conductive bumps 230 are adhered to the bottom surface B of the first pads 312. The conductive bumps 230 may be solder balls, and the shapes of the conductive bumps 23 may be spherical, cylindrical, and pin. Shape or other suitable shape. In this embodiment, the chip package 200a may further include a solder resist layer 350. The solder resist layer 350 covers the traces 324 of the first wiring layer 32A and exposes the second pads 322. As such, the solder resist layer 35G can protect the traces 324 from damage. It should be noted that the upper and lower surfaces of the conventional chip package are respectively covered by two solder mask layers (please refer to FIG. 1E), and the two layers of the second layer prevent the upper surface of the wafer pads from being respectively exposed. Solder ball pad on the lower surface. In the present embodiment, these are: the solder layer 35 electrically connected to the wafer 21?. When exposed, the conductive: block is connected; the pad 312 is exposed by the first dielectric layer 330. A first-circuit layer 3; two: mention = 16 200924137 some, - the solder mask of the junction 312. Further, the color of the anti-friction layer 35() is generally significantly different from the color of the first dielectric layer 330. Therefore, the opposite surfaces of the circuit substrate 3a can be clearly seen to have different colors. In addition, the solder resist layer 350 may cover the surrounding area of the top surfaces of the second pads 322. That is, the anti-friction layer 350 may be of the type of the anti-recording layer definition (10) derMask Defme, SMD, as shown in FIG. 2A. In other embodiments not shown, the anti-friction layer 350 may also be of the type of N〇n_s〇lder Mask Define (NSMD). However, the first dielectric layer 330 covers only the surfaces other than the bottom surface B of the first pads 312, and does not cover the bottom surfaces B. In other words, the first dielectric layer 330 is not covered by the bottom surface B of the first pads 312, and is not like a solder mask defined by the solder mask layer, and the first dielectric layer 33 is also not completely exposed. These first pads 312 are not like a solder mask of a non-solderproof layer definition type. In addition, the circuit substrate 300a may further include a plurality of oxidation resistant layers 36, and the oxidation resistant layers 360 may be formed on the second pads 322. The oxidation resistant layer 360 may be a nickel gold layer or made of other oxidation resistant materials, and the anti-oxidation layer 360 functions to protect the second pads 322 from oxidation to ensure the wafer 210 and the wiring substrate 3a The quality of the electrical connection between. - Figure 2B is a cross-sectional view of a chip package in accordance with another embodiment of the present invention. Referring to FIG. 2B, the chip package body 2% of the present embodiment is similar to the chip package body 200a of the above-described embodiment only, and the difference between the two is that the circuit substrate 300b of the chip package body 200b has a three-layer line structure. The circuit substrate 3〇〇b includes a conductive pattern layer 31〇, a first 17 200924137 Z.HOOVIW1.UUC/11 circuit layer 320b, a first dielectric layer 33〇, these first conductive blind via structures 340a, A second circuit layer 37A, a second dielectric layer 38A, and a plurality of second conductive blind via structures 340b. The second circuit layer 370 is disposed above the 32% of the first circuit layer of the Junmei Cup, and the second is between the first circuit layer 320b and the second circuit layer 370, wherein the second dielectric layer 380 has a plurality of second blind holes 382 〇3 extending from the second circuit layer 37 至 to the first line 320b are disposed in the second blind holes 382 and the second circuit layer 37〇 connects the first-line layer 320b through these second blind passes. These second conductive blind shapes may be the same as the first conductive blind hole structure 340a, that is, the second conductive hole structures 3働 may be formed in a divided manner in the blind state diagram), or these second conductive blinds may be The hole structure 鸠 can fill the conductive pillars of the second blind holes 382. And in the embodiment, the second circuit layer 37G includes a plurality of second pads 372 j stalks 374 ′ and the wafers are traversed through the second pads 372 372, which are connected to the line and = board ^%' The second pads H are electrically connected to the circuit board 300b. The wafer training may be wire bonding, flip chip bonding, or the like, and the wiring substrate 300b may be transferred to the wiring board 300b as shown in Fig. 2β. Circuit board 3〇〇b% diagram wire bonding method electrical connection and circuit board description, not limited to crystal clear please refer to Figure 2A and Figure 2B, value, road substrate ·, degree ^ 2, = 18 200924137 έγΓ line The thickness D2 of the substrate 3 can be below 15Q microns. The chip packages 200a and 200b of the example of the sound of the If and the mouth have a thin thickness. The electronic bird and the fiber are suitable for the current ^ ^

2 and FIG. 2, although the circuit substrate and the layer line shown in FIG. 2A, the second layer of the substrate, and the structure of the (4) structure and the third layer may be: there are four g ί in other embodiments not shown, the circuit substrate is emphasized. Figure 1 The structure of the line. Therefore, in particular, the circuit boards 3GGa and 3_way junctions disclosed in the above-described manner are not limited to the lines of the circuit board of the present embodiment, and only the structure of the chip package of the present invention is described. A method of manufacturing a wafer cracker of the present invention will be described. In this regard, the following will be shown in Figure 2Β\

The two pieces of money 2_ are described as an example, and the method of manufacturing the chip package of FIG. 3A to FIG. 3L is described in detail. Since the L is strong for one week, the coating &amp; method of the wafer cleavage body disclosed in the following Figs. 3A to 3L is not intended to limit the present invention. A f 3A to FIG. 3L is a cross-sectional view of the method for fabricating the chip package of FIG. 2B. Referring to FIG. 3A, a method for manufacturing the chip package of the present embodiment first provides a carrier substrate 240 and a configuration. The conductive material layer 310 on the smile board 240 is supported. For example, the conductive material layer 310 may be made of copper, smelting, age-old gold or other suitable metal, and the carrier substrate 240 may include a first material layer 242 and a first material layer 242 and a conductive layer. Material layer 19 is a second material layer 244 between 200924137 2488 Utwt.cioc/n 310'. The material of the first material layer 242 may be metal or ceramic, and the material of the second material layer 244 may be metal or polymer material, wherein the material of the second material layer 244 is different from the conductive material layer 310'. The polymer material having the viscosity ‘that is, the second material layer 244 made of a polymer material may be adhered between the first material layer 242 and the conductive material layer 310.

When the first material layer 242 and the second material layer 244 are both metal, the material of the first material layer 242 may be copper, Ming or other suitable metal material, and the material of the second material layer 244 may be recorded or otherwise different. The metal material of the conductive material layer 310'. Referring to FIG. 3A and FIG. 3B′, the conductive material layer 31 is patterned to form a conductive pattern layer 310, wherein the conductive pattern layer 31 is disposed on the carrier substrate 240, and each first pad of the conductive pattern layer 310 is formed. The bottom surface B of the 312 has a bottom surface B with respect to the carrier substrate 24 as shown in FIG. 3B. According to the above, the method of patterning the conductive material layer 310 may be to perform a lithography and etching process on the conductive material layer 310. Since the material of the second material layer is not = the conductive material layer 31. Therefore, when the conductive material layer 310 is subjected to ▼ to take the H (five) engraved conductive material layer 31G without damaging the chemical agent of the second material layer 244. Therefore, the second material layer 244 can be used as the conductive layer of the conductive material 31 〇, the money engraving layer (de-mailing the line into the circuit substrate 3_ (please refer to, 3H) on the carrier base cup circuit substrate 鸠 including the conductive pattern Layer 310. Regarding , , ' soil, the following will be described in detail with reference to Figures 3C to 311. 20 200924137

ZHOOVLWl.UUt./iJ It must be discernible that although the secret circuit substrate b has a three-layer circuit structure', other methods of manufacturing the crystal body of the unpainted embodiment can also be used to manufacture two layers ( As shown in FIG. 2, the circuit board 3A), the four-layer or four-layer any layer of the secret structure (10) road substrate.

Referring to FIG. 3C, regarding the formation of the circuit substrate 3b, first, a first dielectric layer 330 is formed on the carrier substrate 24, wherein the first dielectric layer 330 covers the carrier substrate 24 and is electrically conductive. The pattern layer 31 is. The first dielectric layer 330 may be made of a resin 'prepreg or its = insulating material, so that the first dielectric layer 330 can cover the first pads 312. Next, a first conductive layer 32b is formed on the first dielectric layer 33, wherein the first conductive layer 32Gb, the smear copper f|, and the woven fabric are made of other suitable metal materials. The first dielectric layer 330 and the first conductive layer 32〇b may be sequentially formed on the carrier substrate 240, that is, the first dielectric layer 33〇 and the first conductive layer 32〇b may be formed at different times. Of course, the first dielectric layer 330 and the first conductive layer = 〇b' can be formed simultaneously. For example, the method of forming the first dielectric layer 33A and the second electrical layer 320b includes pressing a backing copper foil onto the carrier substrate 240. Referring to FIG. 3D, a plurality of first blind vias 332 are formed, wherein the first via vias 332 extend from the first conductive layer 32〇b to the conductive pattern layer ^0. . In an embodiment, the first blind vias 332 may be formed by a laser drilling process, a plasma process. The field shots used in the above laser drilling process may be carbon monoxide lasers, ultraviolet lasers (UV-YAG laSer) or other suitable lasers. 21 200924137 Z^f〇&amp;ULWl.UUWll

Wit some of the flutes die π M mesh When the process is formed, the bottom of the two § L 332 will leave some slag from the first dielectric layer. These slags will affect the circuit board bird manufacturing method = 332 for desmear. In addition to the hole 33 hole = mine, hole process and plasma etching process, these first blind holes 332 can also be formed for the first target.

C = Cheng. In detail, the first dielectric layer 33 is a molecular material, that is, the first dielectric wall, to illuminate the local light and the development process of the shirt, and may also be: light. Therefore, the blind hole 332 is exposed through. Forming these first on the —-7 electrical layer 330, please refer to FIG. 3E, and the gamma gamma is connected to the first conductive reed 32 to the second conductive &amp; electroporation structure 340a conductive blind hole The structure 34θ% is electrically connected between the two conductive pattern layers 31G, that is, the -31〇. In addition, the %-conducting layer 320b, and the conductive pattern layer may be 320b by the recording path and the electric blind hole structure ^, after rushing, and then 'removing part of the first conductive layer is divided into - conductive; Layer 320b. In this embodiment, the method of removing the first-line sound! 20h report may adopt a lithography and etching process. In the substrate ' (after the embodiment of the circuit having the two-layer circuit structure, the body 6 is completed, and in the other non-green circuit layer 320h, the clothing process of the can include the formation of the solder resist layer The first line &quot;the eight solder mask partially covers the first circuit layer 320b. 22 200924137 24880twf.doc/n Referring to FIG. 3G, then, a second dielectric layer 38 is formed on the first circuit layer 320b. Forming a second conductive layer (not shown) on the second dielectric layer 380. Next, forming a plurality of second blind vias 382, wherein the second blind vias 382 extend from the second conductive layer to the first circuit layer After 32%. = a plurality of second conductive blind via structures 340b are formed in the second blind vias 382. Then, a portion of the second conductive layer is removed to form a second wiring layer 37. The first dielectric layer is formed. 380, the second conductive layer, the second circuit layer 37A, (') the first blind vias 382 and the second conductive via structures 340b are formed in sequence with the first dielectric layer 330, the first conductive layer 320b , the second circuit layer 370, the first blind vias 332, and the first conductive blind via structures 34 are the same Therefore, after the formation of the second wiring layer 370, a wiring substrate 300b having a three-layer wiring structure is substantially completed. Meanwhile, a wafer package carrier including the wiring substrate 300b and the carrier substrate 240 is simultaneously completed. The chip package carrier 202 can be manufactured by an upstream circuit board factory, and the chip package carrier 202 is sent to a downstream wafer package factory for subsequent assembly after fabrication. The procedure of the wafer. In the above, the circuit substrate 300b may further include a solder resist layer 350. In other words, after the second wiring layer 370 is formed, the solder resist layer 35 may be formed on the second wiring layer 370, wherein the solder resist is formed. The layer 350 partially covers the second wiring layer 370' and exposes the second pads 372. Please refer to FIG. 3H. In addition, the circuit substrate 3〇〇b may further include a plurality of oxidation resistant layers 360. An oxide layer 360 may be formed on the second pads 372. Thus, when the wafer package carrier 202 is transporting 23 200924137 24^«utwr.aoc/n to a downstream wafer packaging factory, these oxidation resistant layers can be protected. The second pad 372 avoids oxidation. Secondly, it is worth mentioning that, from the ffi 3C to the figure: 3H, the method of forming the circuit 3b, the circuit substrate 300b is like a build-up layer (build- The circuit substrate 3〇〇b can be fabricated in one layer. Therefore, the method for forming a circuit substrate of the present embodiment can manufacture a circuit substrate having a two-layer circuit structure, and even more can be manufactured. A circuit board with a secret structure of two layers, four layers, five layers, and six layers. In addition, those skilled in the art to which the present invention pertains can know how to manufacture a circuit substrate having a wiring structure of at least two layers or other layers, from Fig. 3C to the drawings and the above. Therefore, it is emphasized here that the manufacturing method of the wiring substrate 3_ shown in Figs. 3C and 3B does not limit the number of layers of the wiring structure which the wiring substrate has. After reading the wafer 31, the wafer 210 is placed on the wiring substrate 3〇〇b' to electrically connect the wafer 210 to the wiring substrate 300b. In this embodiment, the method of electrically connecting the ribs of the circuit board 3 to the ribs 210 may be that the wire bonding P forms the connection between the wafer 210 and the second pads 372. In other embodiments not shown, the method of electrically etching the wafer 210 to the substrate 3 〇〇b may also be a flip chip bonding or other suitable tea reading FIG. 3J, followed by 'forming the encapsulant 220 on the circuit substrate. , the upper, wherein the encapsulant 220 covers the wafer 210. In the present embodiment, the method of forming the encapsulant 220 includes sealing and post-sealing 24 200924137 24880 twi.doc/n post-molding (PMC), and post-sealing baking, for example, encapsulation colloid 220 is sent to a temperature of about 18 (rc environment for 4 hours of baking. Of course, depending on the product requirements, the temperature and time of baking the encapsulant 22 也 are also different. See Figure 3J and Figure 3K, then, the carrier substrate 240 is removed. Thus, the first dielectric layer 330 can completely expose the bottom surface B of the first pads 312, and a chip package 200b is substantially fabricated.

k, the first dielectric layer 330, which can be used as the turn-on of the first pads 312, is not formed by an exposure and development process, and the first-dielectric layer 330 does not cover these first The bottom surface B of the pad 312 surrounds the side edges of the first pads 3丨2. The "electric layer 330" can automatically align the first pads 312 without exposure and development processes, and will not cover the bottom surfaces B, thereby becoming the anti-recording layer of the first pads 312. . Thus, the first dielectric layer ' can be said to have a self-aligned structure (Sdf-aligned structure). - Regarding the method of removing the carrier substrate 240, when the first material layer is confusing: the material layer 244 is all metal, the method of removing the carrier substrate can be performed on the carrier substrate 240. When the second material layer is applied as a polymer material, the method of removing the carrier substrate may include stripping the first material layer 242. 3K and the hole, the chip package 200b may further include an electrical bump 230. In detail, after the carrier substrate is removed, the conductive bumps 23 may be formed, wherein the conductive bumps 23〇 Connected to each of the first pads 312, respectively, 25 200924137 /4S8UlWI.a〇C/n. Thus, by these conductive bumps 23, the wafer package 2A0 can be assembled on a wiring board having a large wiring size such as a motherboard. After forming the conductive bumps 230, the individual wafers can be formed to form a single wafer package body 2〇〇b. As described above, by carrying the substrate, the present invention can make the circuit substrate sturdy so that the wafer package substrate and the wafer package are not easily damaged during the manufacturing process, and can be manufactured by using existing production equipment. In this way, () the chip package and the chip package carrier of the invention need not be specially produced «replacement k, thereby reducing the cost, and at the same time improving the yield of the chip package and the chip package carrier. Secondly, by removing the carrier substrate from the circuit substrate, the present invention can produce a thinner chip package having a thickness of the substrate of up to 100 microns. Obviously, the chip package of the present invention conforms to the chip package carrier in the current development trend of portable electronic devices. In addition, the first dielectric layer can serve as a solder resist layer for the first pads, and the dielectric layer can automatically align these u-pads without material and development processes, and will not cover these. The first contact connects the bottom surfaces of the conductive bumps. Compared with the conventional method for forming the solder resist layer, the solder resist layer of the first: pad (ie, the first dielectric layer) has a time (10) and a miss-alignment. The disadvantage "can further improve the yield of the wafer package body and the wafer listening board. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. 26

200924137 Z^0 0L/LW1.UUC/U The scope of protection of the present invention is defined by the scope of the appended patent application. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1E are schematic flowcharts showing a method of manufacturing a conventional chip package. Fig. 2A is a cross-sectional view showing a chip package in accordance with an embodiment of the present invention. Fig. 2B is a schematic cross-sectional view showing a chip package according to another embodiment of the present invention. 3A to 3L are schematic cross-sectional views showing a method of manufacturing the chip package of Fig. 2B. [Main component symbol description] 100, 200a, 200b: chip package 100a, 202: chip package carrier 110: copper foil substrate 112: dielectric core layer 114': copper foil 114: copper wiring layers 114a, 324, 374: Trace 114b: Wafer Pad 114c: Solder Ball Pad 120, 350: Solder Mask 27 200924137 Z^COUlWl.UUWil 130: Nickel Gold Layer 140, 210: Wafer 150. Wire 160: Package Resin 170: Solder Ball 220: Package body 230: conductive bump 240: carrier substrate 242: first material layer 244: second material layer 300a, 300b: circuit substrate 310: conductive pattern layer 310': conductive material layer 312: first pads 320a, 320b: The first circuit layer 320b': the first conductive layer I 322, 372: the second pad 330: the first dielectric layer 332: the first blind hole 334: the surface 340a: the first conductive blind hole structure 340b: the second conductive blind Pore structure 360: oxidation resistant layer 370: second wiring layer 28 200924137

Z.HOOUIW1.UUWU 380: second dielectric layer 382: second blind hole B: bottom surface Dl, D2: thickness W: bonding wire T: conductive via

Claims (1)

200924137 Ί \J \J\J i. TT W/ LA X. Patent application scope: 1. A chip package comprising: a circuit substrate comprising: a conductive pattern layer comprising a plurality of first pads, wherein each The first interface has a bottom surface; a first circuit layer disposed above the conductive pattern layer; a first dielectric layer disposed between the conductive pattern layer and the first circuit layer, wherein the first The dielectric layer covers a surface other than the bottom surface of the first pads, and does not cover the bottom surfaces, the first dielectric layer has a plurality of first blind holes extending from the first circuit layer to the conductive pattern layer a plurality of first conductive blind via structures respectively disposed in the first blind vias, wherein the conductive pattern layer is connected to the first circuit layer through the plurality of conductive via holes; at least one wafer disposed on the circuit substrate And electrically connecting the circuit substrate; and 'an encapsulant' disposed on the circuit substrate and coating the wafer. 2. The chip package of claim 1, further comprising a plurality of conductive bumps, the conductive bumps respectively connecting the first pads. 3. The chip package of claim 1, wherein the conductive pattern layers are composed of the first pads. 4. The chip package of claim 1, wherein a bottom surface of the first pads is substantially aligned with a surface of the first dielectric layer. The chip package of claim 1, wherein the first circuit layer comprises a plurality of second pads, and the wafer is electrically connected to the circuit substrate through the second pads. 6. The chip package of claim 5, further comprising a plurality of bonding wires, the wafer connecting the second pads through the bonding wires. 7. The chip package of claim 5, further comprising an anti-recording layer covering the first circuit layer ′ and exposing the second pads. 8. The chip package of claim 1, wherein the circuit substrate further comprises: a second circuit layer disposed above the first circuit layer; a second dielectric layer disposed on the first Between a circuit layer and the second circuit layer, wherein the second dielectric layer has a plurality of second blind vias extending from the second circuit layer to the first circuit layer; and a plurality of second conductive blind via structures The second circuit layer is respectively disposed in the second blind holes, and the second circuit layer is connected to the first circuit layer through the second conductive blind via structures. 9. The chip package of claim 8, wherein the second circuit layer comprises a plurality of second pads, the wafer being electrically connected to the circuit substrate through the second pads. 10. The chip package of claim 8, wherein the circuit substrate further comprises a solder resist layer covering the second wiring layer and exposing the second pads. 31 200924137 11. A chip package carrier board, comprising: a carrier substrate; a circuit substrate disposed on the carrier substrate, and comprising: a conductive pattern layer disposed on the carrier substrate and including a plurality of first pads Each of the first pads has a bottom surface opposite to the carrier substrate; a first circuit layer disposed above the conductive pattern layer; a first dielectric layer disposed on the conductive pattern layer and the first line The first conductive layer does not cover the bottom surface of the first pads, and the first dielectric layer covers the first pads. a first dielectric layer having a plurality of first conductive vias extending from the first wiring layer to the conductive pattern layer; and a plurality of first conductive blind via structures respectively disposed on the first blinds And the conductive pattern layer is connected to the first circuit layer by the first conductive blind via structures. The wafer package carrier of claim 11, wherein the carrier substrate comprises a first material layer and a second material layer disposed between the first material layer and the conductive pattern layer; . 13. The wafer package carrier of claim 12, wherein the material of the first material layer comprises metal or ceramic. 14. The wafer package carrier of claim 12, wherein the material of the first material layer comprises copper, aluminum or aluminum copper alloy. 15. The wafer package carrier of claim 12, wherein the material of the second material layer in 32 200924137 comprises a metal or a polymer material. 16. The material of the wafer package as described in claim 12 is included in the material of the material layer. π. The wafer packaged carrier according to the patent application scope of the invention is composed of the first pads. 18. The wafer package carrier of claim 11, further comprising a solder mask layer, wherein the first circuit layer comprises a plurality of second pads, the 'dry layer covering the first circuit layer, And exposing the second pads. Medium 4:=(4)U Na is called a package carrier, and the second circuit layer is disposed above the first circuit layer; 1 is a dielectric layer disposed on the first circuit layer and the second circuit layer The second dielectric layer has a plurality of second blind m 狎 狎 多 多 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二 第二^The second line is connected through the (four) two-conductor structure, including the chip package carrier as described in claim 19, further front M = solder layer, and the second circuit layer includes a plurality of second connections a pad, the tamper is disposed on the second circuit layer, and the second pads are exposed. A method for manufacturing a chip package, comprising: patterning a carrier substrate and a conductive material disposed on the carrier substrate to pattern the conductive material layer to form a conductive pattern layer, wherein the 33 200924137 conductive pattern The layer includes a plurality of first pads; forming a circuit substrate on the carrier substrate; arranging a wafer on the circuit substrate, and electrically connecting the wafer to the circuit substrate; and reversing the coating on the circuit substrate The colloidal package removes the carrier substrate. The wafer package method of claim 21, further comprising forming a plurality of conductive bumps connecting the pads after removing the carrier substrate. μ二弟 23. As described in claim 21, the method for removing the carrier substrate in the cracked body includes the carrier substrate: 24. The chip package described in claim 21 of the patent application The substrate of the county, the medium-sampling substrate comprises a first material layer and a second material layer disposed between the material layer and the conductive material layer, wherein the material of the material layer is different from the conductive material 1. The method of manufacturing the chip package as described in claim 24, wherein the material of the first material layer comprises metal or n. 2, as claimed in claim 2 The method of claim 4, wherein the material of the material layer comprises copper or aluminum, and the method of the chip package according to claim 24, wherein the material of the second material layer The method of manufacturing a chip package according to claim 24, wherein the material of the second material layer comprises nickel. 29. According to claim 24, Chip package manufacturing method The method for carrying the substrate includes stripping the first material layer. The method for fabricating the chip package according to claim 21, or the method for electrically connecting the wafer to the circuit substrate includes 〇31. The wafer method as described in claim 21, wherein the dicing of the parent group (4) comprises: forming a garment ks ^ forming a dielectric layer on the carrier substrate, wherein The first dielectric layer covers the carrier substrate and the conductive pattern layer; forming a first conductive layer on the first dielectric layer; and delaying the #^:: § hole, wherein the first blind holes are from the The first conductive layer extends to the conductive pattern layer; and the first conductive layer has a portion of the first H-f' and the electric layer to form a first circuit layer. The manufacture of the chip package - the method of bonding the first conductive layer comprises the manufacture of the crystal can body described in the method item. The mesh hole is formed by a laser drilling process or a plasma etching method. j: The manufacture of the chip package described in the 31st item is performed for exposure and blind holes The method of manufacturing a chip package as described in claim 31, further comprising forming a solder resist layer on the first circuit layer, wherein the solder resist layer The method of manufacturing the chip package of claim 31, wherein the method of forming the circuit substrate further comprises: forming a second dielectric layer on the first circuit layer Forming a second conductive layer on the second dielectric layer; forming a plurality of second blind vias, wherein the second blind vias extend from the second conductive layer to the first wiring layer; forming a plurality of Two conductive blind vias are formed in the second blind vias; and a portion of the second conductive layer is removed to form a second trace layer. 37. The method of fabricating a chip package of claim 36, wherein the method of forming the second dielectric layer and the second conductive layer comprises: laminating a backing copper foil on the carrier substrate. 38. The method of fabricating a chip package of claim 36, wherein the second blind vias are formed by a laser drilling process or a plasma etching process. 39. The method of fabricating a chip package of claim 36, wherein the forming the second via holes comprises exposing and developing the second dielectric layer. 40. The method of fabricating a chip package of claim 36, further comprising forming a solder resist layer on the second wiring layer, wherein the solder resist layer partially covers the second wiring layer. 36