200923609 ----------“5845twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電壓調節器，且特別是有關於一 種具有斜波補償的電壓調節器。 【先前技術】 —般來說，伺服器（Server)所使用的電壓調節器，其設 計主要有兩種’分別為電壓模式及電流模式。圖i為一般 〇 使用電壓模式的電壓調節器。請參照圖i，電壓調節器1〇〇 透過誤差放大器110來比較輸出電壓Vo與參考電壓V1， 而並輪出誤差值。之後’再利用PWM比較器π〇將誤差 值與銀齒斜波信號V2進行比較，而PWJV[比較器120所 輸出之信號’則是用來控制電晶體Μ的工作週期(Duty cycle)。 然而，電流模式與電壓模式不同之處在於二者的調變 f波信號來自不同的信號源。電流模式所使用的調變斜波 ^ 信號為與電晶體的電流相關，且電流模式的動態性能表現 u 亦較佳於電壓模式，尤其是於非連續電流模式時，其對於 降壓轉換器(buck-converter)中輸入電壓的擾動有很強的抗 =擾能力。另外，剛開始採用電流模式控制時，會出現次 諧波振盪，導致電晶體的脈波會於長短脈波之間切換，而 此種，象於工作週期大於50%時較有可能發生，造成系統 不穩疋的現象，因此便需要進行斜波補償來解決此問題。 此外，一般在電流模式下的電壓調節器並不提供任何振盪 200923609 」5845twfdoc/n 的鋸齒斜波信號，若是要使用到鑛齒斜波 額外的電路來產生，如此—來，將會使用 【發明内容】 电硌的成本提高。 本發明提供-種具有斜波補償的電屋w 由脈寬調變信號來產生斜波信號，並;可以藉 進行補償以及降低電路成本。 以對斜波信號 本發明提出一種具有斜波補償的電壓# Ο ^信號產生H、比㈣、斜波信號產生‘換電^ 误差信號產生器具有第—輸人端、第二輪人端;^奐電路。 ί誤差信號產生器之第-輸入端接收參考電樹=出= 產之第二輸入端接收輸出電壓，而此誤卽； 產生之輪出端產生誤差信號。 σ 'ϋ 較心器^:輸入端、第二輸入端與輪出端，此比 =之第-輸人端接收—斜波信號，此比較器 號差信號’而此比較器之輸出端產生脈寬調變^ Ο 波號產生電路用以依據脈寬調變信號，而產生斜 轉換路用以依據脈寬調變信號，而將輪入電壓 體之另外，此轉換電路包括電晶體，此電晶 而复二t接收脈寬調變信號’其没極端接收輸入電墨， 原極端產生輸出電壓。 -2本ί明一實施例中’上述斜波信號產生電路包括第 第-㈣ί 一電阻、第一二極體與第一電容。第一電阻之 苴笙至電晶體之源極端與比較器之第-輸入端，且 /、弟—端輕接至地端。第二電阻之第一端麵接比較器之輸 200923609 -5845twf.doc/n ^且其—端搞接至比較器之第一輪入嫂^ 體之陽極端減至第二電阻之第 ’°弟—二極 第二電阻之笛 嚷 ^ ，、陰極端麵接至 弟一缟，且其第二端耦接至地端。 电阻之 〜在本發明—實施例中’上述斜波信號產 弟二電阻與第四電阻。第三電 匕括 之筮一钟 电疋·弟一端耦接至第一雷II月 電阻之第:玆:::轉;至比較器之第-輸入端。第四 至第三第-電阻之第二端，且其第二端轉接 體、二施:：’亡述轉換電路更包括第二二極 端耦ΐ至;ΐ- 第五電阻。第二二極體之陰極 %耦接至電晶體之源極端，豆 電感之第-端_至第-耦接至地端。第— —端耦接至;第二電容之第 極體之％極端。第五電阻與第二電容並聯。 -- 在本發明—實施例中 武货一 ,K Jτ上述轉換電路更包括第-雷 :接忿=、第三!容與第六電阻。第二電感 :-極“之二座’且其弟—端耦接至電晶體之汲極端。第 至第二電感之第二端。第三電容： 第六電阻與第三電容並^如，其第二馳接地端。 另二=二實施例中二上述電晶體為N型電晶體。在 A也 ' 述斜波域為三角波信號或顯波信號。 200923609 ：5845twf.doc/n 本發明藉由斜波信號產生電路，且依據比較器所產生 的脈見調變信號來產生斜波信號，並可以達成斜波補償的 功施。另外，斜波信號產生電路是利用簡單的電路元件所 組成的，亦可以降低電路成本。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 〇 圖2繪示為本發明一實施例之具有斜波補償的電壓調 即器電路圖。在本實施例中，電壓調節器適用於電流模式。 請f照圖2，電壓調節器·包括誤差信號產生器21〇、比 較器220、斜波信號產生電路23〇與轉換電路24〇。 誤差信號產生器210之第一輸入端(例如為正輸入端） 接收參考電壓信號n誤差信號產生器21G之第二輪 入，(例如為負輸入端)接收輸出電壓v〇ut，而誤差信號產 生态210之輸出端則產生誤差信號。 比較器220之第一輸入端(例如為正輸入端)接收用斜 U 波信號Vramp，比較器220之第二輪入端(例如為負輪入端） =誤差_ ，並藉由峨毅㈣u %與誤差信 说V⑽r的大小，而於比較器、22〇之輸出端產生脈寬調變信 號 VpWM。 斜波^號產生電路23〇用以依據脈寬調變信號 VPWM’而產生信號V，。在 產生⑽_謂〜R4、二極⑽與電 阻Ri之第-端減至電晶體M1之源極端與比較器22〇 5845twf.doc/n 200923609 之第一輸入端，且其第二端耦接至地端。電阪R2之第一 端耦接比較器220之輸出端’且其第二端耦接至比較器22〇 之第一輸入端。二極體D1之陽極端耦接至電阻R2 ^第一 端’且其陰極端叙接至電阻R2之第一端，用以限制電& 方向。200923609 ---------- "5845twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a voltage regulator, and more particularly to a method with ramp compensation [Previous Technology] In general, the voltage regulator used by the server is mainly designed in two types: voltage mode and current mode. Figure i shows the voltage of the voltage mode. Regulator. Referring to Figure i, the voltage regulator 1〇〇 compares the output voltage Vo with the reference voltage V1 through the error amplifier 110, and rotates the error value. Then, the PWM comparator π〇 is used to compare the error value with the silver tooth. The ramp signal V2 is compared, and the PWJV [the signal output by the comparator 120] is used to control the duty cycle of the transistor 。. However, the current mode differs from the voltage mode in the modulation of the two. The f-wave signal comes from different sources. The modulated ramp wave signal used in the current mode is related to the current of the transistor, and the dynamic performance of the current mode is better than the voltage mode, especially In continuous current mode, it has strong anti-interference ability for the input voltage disturbance in the buck converter. In addition, when the current mode control is used, subharmonic oscillation occurs, resulting in the transistor. The pulse wave will switch between long and short pulse waves, and this is more likely to occur when the duty cycle is greater than 50%, causing the system to be unstable. Therefore, ramp compensation is needed to solve this problem. Generally, the voltage regulator in current mode does not provide any sawtooth ramp signal of the oscillation of 200923609"5845twfdoc/n. If it is to be used to add extra circuits to the ore tooth ramp, this will be used. The cost of electricity is increasing. The invention provides an electric house w with ramp compensation to generate a ramp signal from a pulse width modulation signal, and can compensate and reduce the circuit cost. The present invention proposes a voltage with a ramp wave compensation. The signal generates a H, a ratio (4), and a ramp signal generates a 'switching power'. The error signal generator has a first input end and a second round human end; ^奂 Circuit.第 The first input of the error signal generator receives the reference tree = out = the second input of the output receives the output voltage, and the error occurs; the generated wheel produces an error signal. σ 'ϋ Contrast device ^: input terminal, second input terminal and wheel output terminal, the ratio of the first-input terminal receiving - ramp signal, the comparator difference signal 'and the output of the comparator Pulse width modulation ^ Ο wave number generating circuit is used for generating a diagonal switching path according to the pulse width modulation signal, and according to the pulse width modulation signal, and turning into the voltage body, the conversion circuit includes a transistor, The electric crystal and the second two receive the pulse width modulation signal. 'It does not receive the input ink extremely, and the original terminal produces the output voltage. In the embodiment of the present invention, the ramp signal generating circuit includes a first-(fourth)-th resistor, a first diode, and a first capacitor. The first resistor is connected to the source terminal of the transistor and the first input terminal of the comparator, and the / terminal is lightly connected to the ground terminal. The first end face of the second resistor is connected to the comparator 200923609 -5845twf.doc/n ^ and the end of the second resistor is connected to the anode of the first wheel of the comparator to the second end of the second resistor Dipole - the second pole of the second resistor, the cathode end is connected to the younger brother, and the second end is coupled to the ground end. In the present invention - in the embodiment - the ramp signal is produced as a second resistor and a fourth resistor. The third electric power is included in the first one. The electrician and the younger one are coupled to the first thunder. The first of the resistance is: z::: turn; to the first input of the comparator. The second end of the fourth to third ninth resistors, and the second end of the converter, the second:: 'description conversion circuit further includes a second diode terminal coupled to; ΐ - the fifth resistor. The cathode of the second diode is coupled to the source terminal of the transistor, and the first end to the first end of the bean inductor are coupled to the ground. The first end is coupled to; the extreme of the second pole of the second capacitor. The fifth resistor is connected in parallel with the second capacitor. In the present invention - the embodiment of the goods, K Jτ, the above conversion circuit further includes a -th: interface =, third! and sixth resistor. The second inductor: the "pole" of the "pole" and the other end of the transistor is coupled to the 汲 terminal of the transistor. The second end of the second to the second inductor. The third capacitor: the sixth resistor and the third capacitor The second grounding terminal is the second. In the second embodiment, the above transistor is an N-type transistor. In A, the oblique wave domain is a triangular wave signal or a sensible wave signal. 200923609 : 5845twf.doc/n The ramp signal generating circuit generates a ramp signal according to the pulse modulation signal generated by the comparator, and can realize the ramp wave compensation function. In addition, the ramp signal generating circuit is composed of simple circuit components. In order to make the above features and advantages of the present invention more comprehensible, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. FIG. A circuit diagram of a voltage regulator with ramp compensation according to an embodiment of the invention is shown. In this embodiment, the voltage regulator is adapted to the current mode. Please refer to FIG. 2, the voltage regulator includes an error signal generator 21 〇, comparator 220, oblique The signal generating circuit 23 is coupled to the converting circuit 24. The first input of the error signal generator 210 (for example, the positive input terminal) receives the second round of the reference voltage signal n the error signal generator 21G (for example, the negative input terminal) Receiving an output voltage v〇ut, and an output of the error signal generating state 210 generates an error signal. The first input of the comparator 220 (for example, a positive input terminal) receives the oblique U-wave signal Vramp, and the comparator 220 The second round input (for example, the negative round input) = error _, and the pulse width modulation signal VpWM is generated at the output of the comparator and 22 藉 by means of 峨(4)u% and the error signal saying V(10)r. The wave generating circuit 23 is configured to generate the signal V according to the pulse width modulation signal VPWM', and the source terminal of the transistor M1 is reduced at the first end of the generating (10)_preferred to R4, the two poles (10) and the resistor Ri. The first end of the comparator 22〇5845twf.doc/n 200923609, and the second end thereof is coupled to the ground end. The first end of the electric squirrel R2 is coupled to the output end of the comparator 220 and the second end thereof is coupled To the first input of the comparator 22, the anode terminal of the diode D1 is coupled to the resistor R2 ^ The first end' and its cathode end are connected to the first end of the resistor R2 for limiting the electric & direction.
承上述，電容Cl之第一端耦接至電阻汉2之第二端， 且其第二端耦接至地端。電阻R3之第一端耦接至電阻 之第一端，且其第二端耦接至比較器22〇之第一輸入端。 電阻R4之第一端耦接至電阻及2之第二端，且其第二端耦 接至電阻R3之第二端。 請繼續參照圖2,轉換電路240包括電晶體Ml，此電 曰曰體· Ml之閘極端接收脈寬調變信號vpwM,並且依據脈寬 °周交彳§號Vpwm的電壓準位不同而導通或截止，而轉換電 路240則據以將輸入電壓Vin轉換為輸出電壓。 ^ 另外’轉換電路240還包括二極體D2、電感L1、電 各C2與電阻R5。二極體之陰極端耦接至電晶體M1 之源極端，且其陽極端耦接至地端。電感L1之第—端耦 接至二極體1)2之陰極端。電容C2之第一端耦接至電感In the above, the first end of the capacitor C1 is coupled to the second end of the resistor 2, and the second end thereof is coupled to the ground end. The first end of the resistor R3 is coupled to the first end of the resistor, and the second end of the resistor R3 is coupled to the first input of the comparator 22A. The first end of the resistor R4 is coupled to the second end of the resistor and 2, and the second end of the resistor R4 is coupled to the second end of the resistor R3. Referring to FIG. 2, the conversion circuit 240 includes a transistor M1. The gate terminal of the electrode body M1 receives the pulse width modulation signal vpwM, and is turned on according to the voltage level of the pulse width 周 § § Vpwm. Or off, and the conversion circuit 240 converts the input voltage Vin into an output voltage. Further, the conversion circuit 240 further includes a diode D2, an inductor L1, an electric C2, and a resistor R5. The cathode end of the diode is coupled to the source terminal of the transistor M1, and the anode end thereof is coupled to the ground terminal. The first end of the inductor L1 is coupled to the cathode terminal of the diode 1)2. The first end of the capacitor C2 is coupled to the inductor
Ll之第二端’且其第二端耦接至二極體D2之陽極端。電 =R5與電容C2並聯。在本實施例中，轉換電路240中的 兔晶體Ml、二極體d2、電感Li、電容C2與電阻r5組 合成一個完整的降壓(Buck)電路。另外，電晶體Ml例如 為N型電晶體，而斜波信號Vramp為三角波信號或鋸齒波 信號。 200923609 !5845twf.doc/aThe second end of L1 and the second end thereof are coupled to the anode terminal of the diode D2. Electricity = R5 is connected in parallel with capacitor C2. In the present embodiment, the rabbit crystal M1, the diode d2, the inductor Li, the capacitor C2 and the resistor r5 in the conversion circuit 240 are combined to form a complete buck circuit. Further, the transistor M1 is, for example, an N-type transistor, and the ramp signal Vramp is a triangular wave signal or a sawtooth wave signal. 200923609 !5845twf.doc/a
在整體作動上，當比較器220所輸出的脈寬調變信號 Vpwm為邏輯高電壓準位時，電晶體M1導通，使得轉換電 路=40會對應的將輪入電壓％轉換成輸出電壓乂⑽，同時 脈寬調變信號Vpwm會通過電阻R2對電容C1進行充電。 另一方面，由於電晶體M1導通，電晶體1^1會產生二電 流II，此電流II 一部份會流經電阻R1，另一部份會經由 電阻R3#R4傳送至電容c卜輯電紅丨進行充電二 n 、換言之，當比較器220所輸出的脈寬調變信號VPWM 為邏輯低電壓準位時，則電晶體M1不導通，使得電容〇 上的電壓經由:且R4、R3、R1至地端進行放電。值得一 提的是’藉由脈寬調變信號VpwM的電愿準位變換，以反 覆的對電容a進行統電，而產生斜餘號\—。如此 一來，就不需要額外且複雜設計的電路來產生斜波信號 vramp ’將可以有效地降低電路成本。 另外’使用者可調整斜波信號產生電路23〇中，電阻 R2。的電阻值以及電容α的電容值，以便產生所需的斜波 U 信號Vramp。此外，使用者也可藉由調整電阻R1的電阻值， 來改變電流II對電容C1的充電速度，以調整斜波信號 Vramp。而本實施例可以藉由改變誤差信號Verw與斜波信 號vramp，來調整脈寬調變信號VpwM的工作週期 cycle)、’以避免工作週期大於5〇%時會產生不穩定的現象。 然而，本發明之具有斜波補償的電壓調節器，不限制 應用在降壓電路，亦可使用於升壓電路，且如圖3所示。 圖3繪示為本發明另一實施例之具有斜波補償的電壓調節 器電路圖。請參照圖3,本實施例與圖2的電路差別在於： 200923609 :5845twf.doc/n 圖2之轉換電路240中，二極體D2、電感u、電容C2、 電阻R5與電晶體Ml組成完整的降壓電路，而在圖3之 轉換電路240 ’電感L2、二極體D3、電容C3、電阻R6 組合程完整的升壓電路。 請繼續參照圖3，轉換電路24〇包括了電感L2、二極 f D3、電容C3與電阻R6。電感L2之第一端接收輸入電 壓Vin ’且其第二端耦接至電晶體M1之汲極端。二極體 〇 D3之陽極端耦接至電感L2之第二端。電容C3之第一端 耦接至二極體D3之陰極端，且其第二端耦接地端。電阻 R6與電容C3並聯。而圖3的斜波信號產生的操作可以參 照圖2之實施例，故在此不再贅述。 1综上所述，本發明藉由斜波信號產生電路，且依據比 較器所產生的脈寬調變信號來產生斜波信號，並可以達成 斜波補償的功能。另外，斜波信號產生電路是利用簡單的 電路元件所組成的，因此亦可以降低電路成本。藉此，本 發，無需使用額外的斜波信號產生器，並且也可以避免工 〇 脈寬調變信號的工作週期大於5 0 %時而使得電壓調節器產 生不穩定的現象。 〜雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何所屬技術領域中具有通常知識者，在 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 本發明之保護範圍當視後附之申請專利範圍所界定者 【圖式簡單說明】 圖1為一般使用電壓模式的電壓調節器。 11 5845twf.doc/n 200923609 圖2繪示為本發明一實施例之具有斜波補償的電壓調 節器電路圖。 圖3繪示為本發明另一實施例之具有斜波補償的電壓 調節器電路圖。 【主要元件符號說明】 100、200 :電壓調節器 110 :誤差放大器 120 : PWM比較器 〇 vi:參考電壓 V2 :鋸齒斜波信號 Vo、:輸出電壓 210 :誤差信號產生器 220 :比較器 230 :斜波信號產生電路 240 :轉換電路 R1〜R6 :電阻 q Ml :電晶體 D1 〜D3 . _ C1〜C3 :電容 U、L2 :電感 Vref : 參考電壓信號 VenOI·:誤差信號 Vramp ··斜波信號 VpwM :脈寬調變信號 vin:輸入電壓 12In the overall operation, when the pulse width modulation signal Vpwm outputted by the comparator 220 is at a logic high voltage level, the transistor M1 is turned on, so that the conversion circuit=40 correspondingly converts the wheel-in voltage into an output voltage 乂(10). At the same time, the pulse width modulation signal Vpwm charges the capacitor C1 through the resistor R2. On the other hand, since the transistor M1 is turned on, the transistor 1^1 generates two currents II, one part of which will flow through the resistor R1, and the other part will be transmitted to the capacitor c via the resistor R3#R4. The red cymbal is charged two n, in other words, when the pulse width modulation signal VPWM output by the comparator 220 is at a logic low voltage level, the transistor M1 is not turned on, so that the voltage on the capacitor 经由 passes through: and R4, R3, R1 to the ground discharge. It is worth mentioning that the electric potential level change of the pulse width modulation signal VpwM is used to reverse the capacitance a, and the oblique residual number \- is generated. In this way, an additional and complicated design circuit is not required to generate the ramp signal vramp', which can effectively reduce the circuit cost. Further, the user can adjust the resistance R2 in the ramp signal generating circuit 23A. The resistance value and the capacitance of the capacitance α are such as to generate the desired ramp U signal Vramp. In addition, the user can also adjust the charging speed of the current II to the capacitor C1 by adjusting the resistance value of the resistor R1 to adjust the ramp signal Vramp. In this embodiment, the duty cycle of the pulse width modulation signal VpwM can be adjusted by changing the error signal Verw and the ramp signal vramp to avoid an unstable phenomenon when the duty cycle is greater than 5〇%. However, the voltage regulator with ramp compensation of the present invention is not limited to the buck circuit, and can also be used for the boost circuit, and is shown in FIG. 3 is a circuit diagram of a voltage regulator with ramp compensation according to another embodiment of the present invention. Referring to FIG. 3, the difference between the embodiment and the circuit of FIG. 2 is: 200923609: 5845twf.doc/n In the conversion circuit 240 of FIG. 2, the diode D2, the inductor u, the capacitor C2, the resistor R5 and the transistor M1 are completely composed. The step-down circuit, while in the conversion circuit 240 of Figure 3, the inductor L2, the diode D3, the capacitor C3, and the resistor R6 are combined to complete the boost circuit. Referring to FIG. 3, the conversion circuit 24A includes an inductor L2, a diode f D3, a capacitor C3, and a resistor R6. The first end of the inductor L2 receives the input voltage Vin' and the second end thereof is coupled to the 汲 terminal of the transistor M1. The anode end of the diode 〇 D3 is coupled to the second end of the inductor L2. The first end of the capacitor C3 is coupled to the cathode end of the diode D3, and the second end of the capacitor C3 is coupled to the ground. Resistor R6 is connected in parallel with capacitor C3. The operation of the ramp signal generation of FIG. 3 can be referred to the embodiment of FIG. 2, and therefore will not be described herein. In summary, the present invention generates a ramp signal based on a ramp signal generating circuit and a pulse width modulation signal generated by the comparator, and can achieve a ramp compensation function. In addition, the ramp signal generating circuit is composed of simple circuit components, so that the circuit cost can also be reduced. In this way, the present invention eliminates the need for an additional ramp signal generator, and also avoids the instability of the voltage regulator when the duty cycle of the pulse width modulation signal is greater than 50%. The present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements within the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims [Simplified Description of the Drawings] FIG. 1 is a voltage regulator generally using a voltage mode. 11 5845twf.doc/n 200923609 FIG. 2 is a circuit diagram of a voltage regulator with ramp compensation according to an embodiment of the invention. 3 is a circuit diagram of a voltage regulator with ramp compensation according to another embodiment of the present invention. [Main component symbol description] 100, 200: voltage regulator 110: error amplifier 120: PWM comparator 〇vi: reference voltage V2: sawtooth ramp signal Vo, output voltage 210: error signal generator 220: comparator 230: Ramp signal generation circuit 240: conversion circuits R1 to R6: resistance q Ml : transistors D1 to D3 . _ C1 to C3 : capacitance U, L2 : inductance Vref : reference voltage signal VenOI ·: error signal Vramp · · ramp signal VpwM: pulse width modulation signal vin: input voltage 12