200921917 23954twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種主動元件的製造方法，且特別是 有關於一種薄膜電晶體的製造方法。 【先前技術】 〇200921917 23954twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a method of manufacturing an active device, and more particularly to a method of manufacturing a thin film transistor. [Prior Art] 〇
隨著科技日新月異，技術的日漸成熟，液晶顯示器 (Liquid Crystal Display，LCD)已廣泛的被應用在曰常生活 中’而薄膜電晶體(Thin Film Transistor，TFT)是應用液晶顯 示益中的驅動元件。電晶體(Transistor)的通道材料分為兩 種’一種為非晶石夕材料(amorphous silicon, a-Si)，一種為多 晶石夕材料(p〇ly-silicon, p_Si)。一般來說，非晶矽薄膜電晶 體具有較低的漏電流(leakage current)，但是其電子遷移率 (electron mobility)卻較低，其不超過 1 cm2/Vsec，不敷 目則咼速元件應用之需求。然而，多晶矽薄膜電晶體相較 於非晶矽薄膜電晶體而言，具有較高之電子遷移率（約比 非晶矽高2〜3個數量級），卻有較高的漏電流，以致於無 法應用於大尺吋的液晶顯示器。因此，為了有效改盖多晶 石夕薄膜電晶體偏高的漏電流’―般便於薄膜電晶體的闊極 兩側以淺掺雜j：及極的結構來降低漏電流。 圖1A至圖1D緣示-種習知的薄膜電晶體的製造方 法的示意圖。請參考圖1A’此習知_膜電晶咖方 純括^步驟，於基板11Q上形成—多晶 (poly-silicon island) 120。 請參考圖IB，形成一圖案化光阻層125，然後，以圖 200921917 23954twf.doc/p 案化光阻層125為遮罩進行一離子植入製程（i〇n implantationprocess)S110,以於圖案化光阻層125兩側下 方之多晶石夕島狀物120内形成一源極/没極121。然後，移 除圖案化光阻層125。 請參考圖1C，形成一閘絕緣層13〇於基板上11〇，並 覆盍住多晶矽島狀物12〇 ;接著，形成一閘極14〇於基板 110上。然後，以閘極14〇為遮罩’進行一淺摻雜離子植 Ο 入製程（ughtly doped drain ion implantation process ) S120， 以於閘極140兩側之下方之多晶矽島狀物12〇内形成一淺 摻雜汲極區123，而位於閘極層14〇正下方之多晶矽島狀 物120即是一通道區127。 請參考圖1D，於基板110上分別形成一圖案化介電 層150，並移除部份閘絕緣層13〇，以暴露出部分源極級 極121。然後， 160，而圖者化 ，在圖案化介電層150上形成圖案化導體層 160 ’而圖案化導體層160與源極/没極121電性連接。至 此，大致上完成習知的薄膜電晶體之製程。With the rapid development of technology and the maturity of technology, liquid crystal displays (LCDs) have been widely used in everyday life, and Thin Film Transistors (TFTs) are driving components for liquid crystal display applications. . The channel material of the transistor is divided into two types: an amorphous silicon (a-Si) and a polycrystalline silicon (p_Si). In general, amorphous germanium thin film transistors have a lower leakage current, but their electron mobility is lower, which does not exceed 1 cm 2 /Vsec. Demand. However, polycrystalline germanium thin film transistors have higher electron mobility (about 2 to 3 orders of magnitude higher than amorphous germanium) than amorphous germanium thin film transistors, but have higher leakage currents, so that they cannot It is applied to LCD monitors with large size. Therefore, in order to effectively change the high leakage current of the polycrystalline thin film transistor, it is convenient to reduce the leakage current by the shallow doping j: and the polar structure on both sides of the wide side of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1D are schematic views showing a conventional method for producing a thin film transistor. Referring to FIG. 1A', the conventional method of forming a poly-silicon island 120 is formed on the substrate 11Q. Referring to FIG. 1B, a patterned photoresist layer 125 is formed, and then an ion implantation process S110 is performed as a mask with the pattern of the 200921917 23954twf.doc/p photoresist layer 125 as a mask. A source/no electrode 121 is formed in the polycrystalline stone island 120 below the two sides of the photoresist layer 125. Then, the patterned photoresist layer 125 is removed. Referring to FIG. 1C, a gate insulating layer 13 is formed on the substrate 11 〇 and covered with the polysilicon island 12 〇; then, a gate 14 is formed on the substrate 110. Then, a shallow doped drain ion implantation process S120 is performed with the gate 14〇 as a mask, so as to form a polycrystalline germanium island 12 below the two sides of the gate 140. The shallow doping region 123, and the polycrystalline germanium island 120 directly under the gate layer 14 is a channel region 127. Referring to FIG. 1D, a patterned dielectric layer 150 is formed on the substrate 110, and a portion of the gate insulating layer 13 is removed to expose a portion of the source electrode 121. Then, 160, and patterned, a patterned conductor layer 160' is formed on the patterned dielectric layer 150, and the patterned conductor layer 160 is electrically connected to the source/no. Thus, the process of the conventional thin film transistor is substantially completed.
一種習知薄膜電晶體的製 此習知的薄膜電晶體的製 200921917 ν/ τ, 23954twf.doc/p 造方法包括下列步驟。於一基板上21〇依疼 島狀物220、一閘絕緣層23〇與一閘極層24〇&。接著，彤 成一圖案化光阻層250於閘極層240a之上，其 ’ ^ 阻層250具有一頂部光阻層結構25〇a與—基部光阻層結構 250b ’且頂部光阻層結構25〇a與基部光阻層結構ϋ 接。 請參考圖2Β，進行離子植入製程咖，以於在閑極 〇 i24Ga兩側下方之多轉島狀物，_歧極/源極 221 〇 請參考圖m漿灰域其_等向性_的方 式剝除部分厚度之基部光阻層結構2通，以暴露出部分問 極層=〇a。然後，移除部分閘極層240a，以形成閘極24%。 "月參考圖2D，進行淺摻雜離子植入製程S22〇，以於 閘極層240b兩侧下方之多晶石夕島狀物22〇内形成淺換雜汲 極1J 223 ’而位於閘極層24〇b正下方之多晶矽島狀物22〇 即是—通道區mm除剩餘的基部光阻層結構 (J 250b。 請參考圖2E’於基板210上分別形成一圖案化介電層 260，並移除部份閘絕緣層23{)，轉露出部分源極/沒^ 221。然後，在圖案化介電層26〇上形成圖案化導體層 而圖案化導體層270與源極/汲極電性221連接。 值得注意的是，此種製造方法雖然可以減少一道光 部需要增加電漿灰化或其他非等向性制製程來剝除 部份圖案化光崎25〇(亦即基部光阻層結構2赐），並增 200921917 23954twf.doc/p 加閘極二次侧的製程’其對於整體製造的料並未減少。 【發明内容】 有鑒於此，本發明提供一種薄膜電晶體的製造方法， 以減少所使用的光罩數。 f) 本發明提出一種薄膜電晶體的製作方法，JL步驟包 f j基板上形成多晶料狀物。接著，依序形成閘絕緣 I、導體層於基板上，域蓋住多㈣島錄。之後，形 成圖案化:¾阻層於導體層上，並藉由圖案化S阻層對於導 體層進行-過蝕刻製程’以形成閘極，其中閘極的寬度小 於圖案化光阻層的寬度。接著，妨離子植人製程，以於 ，案化光阻層兩側下方之多晶矽島狀物内形成一源極/汲 極’而閘極正下方之多晶矽島狀物為一通道區 除圖案化光阻層，並進行—雜雜子植人製程，以於 =兩側下方之多轉島狀物_成淺摻雜汲純，並中 4雜錄區位於源極/汲極與通道區之間。之後，A conventional thin film transistor is manufactured by the conventional thin film transistor. The manufacturing method of the present invention includes the following steps. On a substrate, 21 〇 疼 island 220, a gate insulating layer 23 〇 and a gate layer 24 〇 & Then, a patterned photoresist layer 250 is formed on the gate layer 240a, and the 'resist layer 250 has a top photoresist layer structure 25〇a and a base photoresist layer structure 250b' and the top photoresist layer structure 25 〇a is connected to the base photoresist layer structure. Please refer to Figure 2Β, the ion implantation process coffee is used to make the multi-turn island below the idle pole 〇i24Ga, _disparity pole/source 221 〇 please refer to the figure m ash field _ isotropic _ The portion of the base photoresist layer structure is stripped to expose a portion of the interrogation layer = 〇a. Then, part of the gate layer 240a is removed to form a gate 24%. "Monthly with reference to Fig. 2D, a shallow doping ion implantation process S22〇 is performed to form a shallow exchange jig 1J 223 ' in the polycrystalline stone island 22 below the both sides of the gate layer 240b. The polysilicon island 22 directly under the pole layer 24〇b is the channel region mm except for the remaining base photoresist layer structure (J 250b. Please refer to FIG. 2E′ to form a patterned dielectric layer 260 on the substrate 210, respectively. And remove part of the gate insulating layer 23{), revealing part of the source / no ^ 221. Then, a patterned conductor layer is formed on the patterned dielectric layer 26, and the patterned conductor layer 270 is connected to the source/drain 221. It is worth noting that although this method of fabrication can reduce the need for a plasma portion to increase plasma ashing or other anisotropic processes to strip a portion of the patterned photonica 25 〇 (ie, the base photoresist layer structure 2) And increase the 200921917 23954twf.doc / p plus the secondary side of the process 'which does not reduce the overall manufacturing material. SUMMARY OF THE INVENTION In view of the above, the present invention provides a method of manufacturing a thin film transistor to reduce the number of masks used. f) The present invention provides a method for fabricating a thin film transistor, and a JL step package forms a polycrystalline material on the substrate. Then, the gate insulation I and the conductor layer are sequentially formed on the substrate, and the domain covers the multi-(4) island record. Thereafter, patterning is formed: a resist layer is formed on the conductor layer, and the gate layer is subjected to an over-etching process by patterning the S-resist layer to form a gate, wherein the width of the gate is smaller than the width of the patterned photoresist layer. Next, the ion implantation process is such that a source/drain is formed in the polycrystalline island below the two sides of the photoresist layer, and the polycrystalline island directly below the gate is a channel region except for patterning. The photoresist layer is subjected to a heterogeneous implant process, so that the multi-turn islands below the two sides are shallow doped yttrium, and the middle miscellaneous recording zone is located in the source/drainage and channel regions. between. after that,
O 2於閘絕緣層上，叫蓋_。鎌部分 1 f二;出源r極’並形成圖— =閘心緣g L源極/汲極導體層於圖案化介 其中源極/没極導體層分別與源極/没極電性連接。口 制依據本發明之-實施例，上述之源極/汲極的離子植入 衣权所植入的離子的摻雜濃度可以是介於5E14 i〇ns/cm2 之間。 依據本發明之-實關，上叙_雜子植入 所植入的離子的摻雜濃度可以是介於1E13至1E14 200921917 ------ 23954twf.doc/p ions/cm2 之間。 ，依據本發明之一實施例，上述之在形成多晶矽島狀物 之前，更可以先於基板上形成一緩衝層。 依據本發明之一實施例，上述之圖案化光阻層的邊緣 與閘極的邊緣可以相距1.5至2微米。 依據本發明之一實施例，上述之閘極的材質可以包括 銅(Cu)、鋁(A1)、鎢(W)、鉻(Cr)、鉬(Mo)、鈦(Ti)、鈕(Ta)、 〇 矽化鎢(WSi2)、矽化鈦(TiSi2)、矽化鈕(TaSi2)、矽化鉬(MoSi2) 或矽化鈷(CoSiJ。 基於以上所述，本發明利用過蝕刻的方式，以使得形 成閘極所需之圖案化光阻層大於閘極，並以圖案化光阻層 與閘極為遮罩分別進行離子植入製程，以形成源極/汲極與 淺摻雜没極區，藉此可減少薄膜電晶體的製程光罩數目， 並降低製程成本與時間。 為讓本發明之上述與其目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例’並配合所附圖式，作詳細說明 Ο 如下。 【實施方式】 圖3A至3F繪示為本發明實施例之一種薄膜電晶體的 製作方法的示意圖。請參考圖3A，本實施例之薄膜電晶體 的製造方法包括下列步驟。首先，於基板310上形成一多 晶矽島狀物320。更詳細而言，形成多晶矽島狀物32〇的 步驟例如是先在基板310上形成一非晶矽層（未繪示）， 而形成非晶矽層的方式例如是化學氣相沉積（chemicai 200921917 -------..23954twf.doc/p vapor deposition，CVD)製程或電漿加強化學氣相沉積 (plasma enhanced CVD，PECVD)製程。接著，對於此^ 晶石夕層進行雷射退火（laser annealing)製程，以使非晶石夕 層轉變成多晶矽層。然後，對於此多晶矽層進行微影 (photolithography )製程與钱刻（etching )製程，以在美 板310上形成多晶矽島狀物320。 土 此外’在形成多晶發島狀物320之前，更可以先於灵 板上形成一緩衝層311，以減少基板31〇内的金屬離子擴 散至多晶矽島狀物320内。而形成緩衝層311的方式可以 是低壓化學氣相沉積（low pressure CVD，LPCVD)製程或 疋PECVD製程。更洋細而言，緩衝層311例如是單層氧 化石夕或是氧化石夕/氮化石夕之雙層結構。 請參考圖3B，在基板上形成一閘絕緣層33〇，並覆蓋 住多晶矽島狀物320。更詳細而言，閘絕緣層33〇形成的 方式可以疋採用PECVD製程。接著，在閘絕緣層mo之 上形成一導體層340於基板上。更詳細而言，導體層 Ο 形成的方式可以是先在閘絕緣層330上以物理氣相沉積 (physical vapor deposition)製程或是濺鍍(sputtering)製程形 成一閘極材料層，而閘極材料層的材質可以是銅(Cu)、鋁 (A1)、鎢（W)、鉻(Cr)、铜（Mo)、鈦(Ti)、组(Ta)、石夕化鶴 (wsi2)、矽化鈦(Tisi2)、矽化鈕(Tasi2)、矽化鉬(MoSi2)或 矽化鈷(CoSi2)。然後，於導體層340上形成一圖案化光阻 層 410。 請參考圖3C ’藉由濕蝕刻的方式進行過蝕刻，以形 200921917 23954twf.doc/p 成閘極341，並使得閘極341的寬度小於圖案化光阻層4i〇 的寬度。更詳細而言，圖案化光阻層410的邊緣與閘極341 的邊緣可以相距1.5至2微米，如圖3C所示之d。 請參考圖3D，以圖案化光阻層410為遮罩進行離子 植入S310製程，以於圖案化光阻層41〇兩側下方之多晶 矽島狀物320内形成一源極/汲極321。更詳細而言，離子 植入製程S310所植入的離子可以是n型摻雜物，其中n 〇 ，摻雜物可以是磷離子，而所植入的離子的摻雜濃度可以 疋介於5Ε14至1Ε16 ions/cm2之間。 請參考圖3E，去除圖案化光阻層410後，以閘極341 為遮罩進行淺摻雜離子植入製程幻2〇，以於間極341兩侧 之下方多晶矽島狀物320内形成淺摻雜汲極區323，而閘 極341 ^下方之多晶矽島狀物32〇即是一通道區3%。更 f細而言，淺摻雜離子植入製程⑽所植入的離子可以 雜物’其中11型摻雜物可以是鱗離子，所植入的 〇 ^雜濃度可以是介於則至lE14i〇ns/em2之間。 為遮罩== 二3成21 =圖案化光阻層 邊緣*円垒几止 #所开乂成’因此’源極/汲極321的 是以閘邊緣對齊。此外，淺摻雜區奶 此，淺摻雜區行淺接雜離子植入製程所形成，因 ^ 的邊緣與閘極341邊緣對齊。 350，1參+考圖奸，於該閘絕緣層33G上形成-介雷# 接者移除部份介雷爲 電曰 部分源極/沒極321上、閘、、、巴緣層330’以暴露出 更#細而έ，移除部分介電層350與 11 200921917 23954twf.doc/p 閘絕緣層330的方法包括微影製程與姓刻製程。然後，在 介電層350上形成源極/汲極導體層編，而源極/汲極導體 層360與源極/汲極321電性連接。 曰子植人製程巾所摻_離子，依實際薄膜電 又心求，可以是n型或p型摻雜物，以形成η通道 或疋Ρ通道金屬氧化物半導體。 综上所述，本發明之薄膜電晶體的製造方法包括下列 盘㈣^目較^ f知猶需要兩道鮮才脑彡絲極/汲極 本發明利用侧方式，使得閘極的圖 層的騎，並分取_化光阻層料 方法僅需-道光:本發明的薄膜電晶體的製造 僅而道先罩’可以減少薄膜電晶體的製程O 2 is on the gate insulation layer, called cover _.镰 part 1 f 2; source r pole ' and form a graph - = gate core g L source / drain conductor layer in the patterning medium source / electrodeless conductor layer respectively with the source / no pole electrical connection . According to the embodiment of the present invention, the doping concentration of ions implanted in the above-mentioned source/drain ion implantation apparatus may be between 5E14 i〇ns/cm2. According to the present invention, the doping concentration of the implanted ions may be between 1E13 and 1E14 200921917 ------ 23954 twf.doc/p ions/cm 2 . According to an embodiment of the present invention, before the formation of the polycrystalline islands, a buffer layer may be formed on the substrate. According to an embodiment of the invention, the edge of the patterned photoresist layer and the edge of the gate may be 1.5 to 2 microns apart. According to an embodiment of the invention, the material of the gate may include copper (Cu), aluminum (A1), tungsten (W), chromium (Cr), molybdenum (Mo), titanium (Ti), button (Ta). Tungsten telluride (WSi2), titanium telluride (TiSi2), bismuth teller (TaSi2), molybdenum telluride (MoSi2) or cobalt telluride (CoSiJ. Based on the above, the present invention utilizes an overetching method to form a gate The patterned photoresist layer is larger than the gate electrode, and the ionizing process is performed by patterning the photoresist layer and the gate mask to form a source/drain and a shallow doped non-polar region, thereby reducing the film. The number of process masks of the transistor, and the cost and time of the process are reduced. In order to make the above-described objects, features and advantages of the present invention more apparent and easy to understand, the preferred embodiment is described below in detail with the accompanying drawings. 3A to 3F are schematic views showing a method of fabricating a thin film transistor according to an embodiment of the present invention. Referring to FIG. 3A, the method for manufacturing a thin film transistor of the present embodiment includes the following steps. A polycrystalline island 320 is formed on the substrate 310. More specifically, The step of forming the polycrystalline germanium island 32 is, for example, first forming an amorphous germanium layer (not shown) on the substrate 310, and forming an amorphous germanium layer by chemical vapor deposition (chemicai 200921917 ----- --..23954twf.doc/p vapor deposition (CVD) process or plasma enhanced CVD (PECVD) process. Next, a laser annealing process is performed on the slab layer. In order to convert the amorphous layer into a polycrystalline layer, a photolithography process and an etching process are performed on the polysilicon layer to form a polycrystalline island 320 on the sheet 310. Before forming the polycrystalline islands 320, a buffer layer 311 may be formed on the slab to reduce the diffusion of metal ions in the substrate 31 into the polycrystalline islands 320. The buffer layer 311 may be formed. It is a low pressure CVD (LPCVD) process or a 疋PECVD process. More specifically, the buffer layer 311 is, for example, a single layer of oxidized oxide or a double layer structure of oxidized stone/nitride. Refer to Figure 3 B, a gate insulating layer 33 is formed on the substrate, and covers the polysilicon island 320. In more detail, the gate insulating layer 33 is formed by a PECVD process. Then, above the gate insulating layer mo A conductor layer 340 is formed on the substrate. In more detail, the conductor layer may be formed by first forming a physical vapor deposition process or a sputtering process on the gate insulating layer 330. The gate material layer, and the material of the gate material layer may be copper (Cu), aluminum (A1), tungsten (W), chromium (Cr), copper (Mo), titanium (Ti), group (Ta), stone Xihua crane (wsi2), titanium telluride (Tisi2), strontium button (Tasi2), molybdenum molybdenum (MoSi2) or cobalt telluride (CoSi2). Then, a patterned photoresist layer 410 is formed on the conductor layer 340. Referring to FIG. 3C', the etching is performed by wet etching to form the gate 341 in the shape of 200921917 23954twf.doc/p, and the width of the gate 341 is made smaller than the width of the patterned photoresist layer 4i. In more detail, the edge of the patterned photoresist layer 410 and the edge of the gate 341 may be 1.5 to 2 microns apart, as shown by d in FIG. 3C. Referring to FIG. 3D, the patterned photoresist layer 410 is used as a mask for ion implantation in the S310 process to form a source/drain 321 in the polycrystalline island 320 below the two sides of the patterned photoresist layer 41. In more detail, the ions implanted in the ion implantation process S310 may be n-type dopants, wherein n 〇, the dopant may be phosphorus ions, and the implanted ions may have a doping concentration of 5Ε14. Between 1Ε16 ions/cm2. Referring to FIG. 3E, after the patterned photoresist layer 410 is removed, the shallow doping ion implantation process is performed with the gate 341 as a mask to form a shallow shallow polycrystalline island 320 on both sides of the interpole 341. The drain region 323 is doped, and the polysilicon island 32 under the gate 341 ^ is a channel region of 3%. More specifically, the ions implanted in the shallow doping ion implantation process (10) can be heterogeneous 'where the type 11 dopant can be a scale ion, and the implanted impurity concentration can be between lE14i〇 Between ns/em2. For the mask == two 3 into 21 = patterned photoresist layer edge * 円 几 # # 所 所 所 所 所 所 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 因此 源 。 。 。 。 。 。 。 。 。 。 。 In addition, the shallow doped region is formed by a shallow doped ion implantation process, since the edge of ^ is aligned with the edge of the gate 341. 350, 1 ginseng + test map, formed on the gate insulating layer 33G - Jie Lei # 接接 remove part of the ray for the electric part of the source / no pole 321 on the gate, gate, edge layer 330' To expose a portion of the dielectric layer 350 and 11 200921917 23954twf.doc/p gate insulating layer 330, the method includes a lithography process and a surname process. Then, a source/drain conductor layer is formed on the dielectric layer 350, and the source/drain conductor layer 360 is electrically connected to the source/drain 321 . The ionic ions doped by the scorpion implant process towel can be either n-type or p-type dopants to form an n-channel or germanium channel metal oxide semiconductor, depending on the actual film. In summary, the manufacturing method of the thin film transistor of the present invention includes the following discs (four), which are required to be used in the side of the invention, so that the layer of the gate is riding. And the method of taking the photoresist layer material only needs to be-channel light: the manufacturing of the thin film transistor of the invention can only reduce the process of the thin film transistor
糊稱==:可;產生光罩間的對位誤差無法 阻為遮罩以及利發明採用間極層之圖案化光 對多晶/?、式似彳具有均勻等向性的優點， 摻雜汲極_對=離子植人製程’因此_兩側的淺 化光ί進綱極/雜犧，對圖案 植入上間極層後’才進行淺推雜離子 化光阻作為遮罩/進發明則是利用閘極層之圖案 進仃故摻雜離子植入以形成淺摻雜汲極 12 200921917 23954twf.doc/p 區。因此相較於習知技術，本發明之薄膜電晶體的製造方 法，所需的製程程序較少。 ^雖然本發明已以較佳實施例揭露如上，然其並非用以 限疋本發明，任何所屬技術領域中具有通常知識者，在不 $離本發明之精神和範_，當可作些許之更動與满飾， =本發明之保護範圍當視後附之中請專利範圍所界定者 Ο 【圖式簡單說明】 晶體的製造方法的 —圖1A至圖1D繪示習知之薄膜略 示意圖。 、兒 的示if。至圖π緣不另一習知之薄賤電晶體的製造方法 圖3A是圖3F本發明實施例中之〜 】 作方法的示意圖。 麵薄膜電晶髏的象 【主要元件符號說明】 110、210、310 :基板 120、 220、320 ·多晶石夕島狀物 121、 221、321 :源極/汲極 123、223、323 :淺摻雜汲極區 125、250、410 :圖案化光阻層 127、325 :通道區 130、230、330 :閘絕緣層 140、240b、341 :閘極 150、260、350 :介電層 13 200921917 ▽_______ “ , 23954twf.doc/p 160、270、360 :源極/汲極導體層 S110、S210、S310 :離子植入製程 S120、S220、S320 :淺摻雜離子植入製程 240a :閘極層 250a :頂部光阻層結構 250b :基部光阻層結構 311 :缓衝層 340 :導體層 〇 14Paste ==: Yes; the alignment error between the reticle can not be blocked as a mask and the invention uses the patterned light of the interpole layer to have the advantage of uniformity of polycrystalline/?, like 彳, doping Bungee _ pair = ion implant process 'so the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The invention utilizes a pattern of gate layers to implant ion implants to form shallow doped gates 12 200921917 23954 twf.doc/p regions. Therefore, the manufacturing method of the thin film transistor of the present invention requires less processing procedures than the conventional technique. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art will be able to make some changes without departing from the spirit and scope of the invention. With the full decoration, the scope of protection of the present invention is defined by the scope of the patent application Ο [Simple description of the drawing] The method of manufacturing the crystal - FIG. 1A to FIG. 1D are schematic diagrams of a conventional film. , child's show if. FIG. 3A is a schematic diagram of the method of FIG. 3F in the embodiment of the present invention. FIG. Image of surface film transistor [Main component symbol description] 110, 210, 310: substrate 120, 220, 320 · polycrystalline islands 121, 221, 321 : source/drain 123, 223, 323: Shallow doped drain regions 125, 250, 410: patterned photoresist layers 127, 325: channel regions 130, 230, 330: gate insulating layers 140, 240b, 341: gates 150, 260, 350: dielectric layer 13 200921917 ▽_______ " , 23954twf.doc / p 160 , 270 , 360 : source / drain conductor layer S110 , S210 , S310 : ion implantation process S120 , S220 , S320 : shallow doping ion implantation process 240a : gate Layer 250a: top photoresist layer structure 250b: base photoresist layer structure 311: buffer layer 340: conductor layer 〇14