TW200919722A - Semiconductor device - Google Patents

Abstract

A semiconductor device is provided. An isolation structure is formed in a substrate to define a first and a second active region, and a channel active region therebetween. A field implant region is formed below a portion of the isolation structure around the first, second, and channel active regions. A channel active region includes two first sides defining a channel width. The distance from each first side to a second side of a neighboring field implant region is d1. The shortest distance from a third side of each first or second active region to an extension line of each second side of the field implant region is d2. R = d1/d2, where 0. 15 ≤ R ≤ 0. 85. A gate structure covers the channel active region and extends over a portion of the isolation structure. Source/drain doped regions are formed in the first and the second active regions.

Description

200919722 /-v/v 74 24922twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit and particularly to a semiconductor element. [Prior Art]

O The gold oxide half element is a widely used semiconductor component. When the component is defective. When the benefits are reduced, the shortened channel length will accelerate the speed of the MOS transistor, but the short channel effect (Sh〇rt Channel Effect) derived from the channel shortening will become more and more serious. According to the electric field=voltage/length formula 'if the applied voltage forest' and the electro-crystal channel length test, the energy I of the electrons in the pass-through will be boosted by the electric field acceleration, thereby increasing the situation of the collapse (Electmal Breakdown); The increase in the strength of the electric field also increases the electron energy of the channel (10), which also causes an electrical collapse. - The average voltage of 7L pieces will occur earlier. This is because the phenomenon of PGtling C ding near the bungee area is relatively high, so that the breakdown voltage is not easy to increase. The conventional high-voltage S-pieces mainly use the 13⁄4 hybrid structure (four) to increase or decrease the distance between the poles (four) poles and the low-channel _ transverse electric field. In addition, the formation of the % implanted area below the isolation structure can also block the effect of the component breakdown voltage. # Figure 1 is a schematic diagram of the J-face of the 孟 孟 孟 半 half element. Please refer to Figure 1, ^ lifting component breakdown voltage. Typically, a square, gift zone 112 will be placed under the isolation structure 102. However, since the field implant region 12 is generally formed, 200919722 υΜ〇υ-^υυ/-υυ 74 24922twf.doc/n is not only located below the isolation structure 102, but also extends upwardly adjacent to the channel region 104. When the gold-oxide half element is applied to the high voltage, the pressure difference between the substrate 1 〇〇 and the gate 124 is large, and when a certain pressure difference is reached, the channel region 1 〇 4 will be reversed. The resulting inversion layer and field implant region 112 form a > 1 junction, causing severe leakage current. SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device having a sufficiently high breakdown voltage and a low leakage current. The present invention provides a semiconductor device including an isolation structure, a field implant region, a gate structure, and a source/drain doping region. The isolation structure is located in the substrate, and defines a first active region and a second active region and a channel active region between the two in the substrate, the active regions being separated by an isolation structure. The field implanted region is located below the first active region, the second active region, and a portion of the isolation structure around the channel=moving region, wherein the channel active region has two first-edges bounded by the channel width, and each of the first edges is adjacent thereto The second edge of the field implant region is spaced apart by a distance, and the shortest distance between each of the first active region and the second edge of each first active region and the second edge extension of the field implant region is d2 , R = dl / d2, its frame 15 you 〇 85. The closed-pole structure covers the channel filament region and extends over a portion of the isolation structure. The source/drain doping regions are respectively located in the first active region and the second active region. According to an embodiment of the invention, in the above semiconductor device, 26.26 < R < 〇. 52 °. According to the embodiment of the present invention, in the above semiconductor device, the conductivity type of the dopant implanted in the field entrance region is the same as that of the surface germanium-doped region. According to an embodiment of the invention, in the above semiconductor device, the semiconductor element comprises a P-type gold oxide half element. According to an embodiment of the invention, in the above semiconductor device, the p-type metal oxide half element includes a P-type high voltage element. According to an embodiment of the invention, in the above semiconductor device, the dopant implanted in the field implant region is N-type. According to an embodiment of the invention, in the above semiconductor device, the semiconductor element comprises an N-type gold oxide half element. According to the present invention, in the above semiconductor element, the N-type metal oxide half element includes an N-type high voltage element. According to the embodiment of the invention, in the above semiconductor device, the dopant implanted in the field implant region is p-type. According to the embodiment of the invention, in the above semiconductor component, field planting

The ingress area surrounds the first active area, the second active area, and a portion of the isolation structure around the active area of the channel. According to an embodiment of the invention, the isolation structure within the field region of the semiconductor device includes first, second, and third isolation junctions. The brother-isolation structure is surrounded by the first active area. The second isolation junction t is rotten around the second filament region. The third isolation structure is located around the first edge of the active area of the channel. According to an embodiment of the invention, the semiconductor device isolation structure and the second isolation structure protrude from the active region of the channel. According to an embodiment of the invention, among the above semiconductor components, the first 200919722 UMCD-2007-0074 24922twf.doc/n

Rl is substantially co-bounded from the structure and the surface area of the second isolation structure. According to an embodiment of the invention, in the above semiconductor device, the channel active region protrudes from the first isolation structure and the second isolation structure. According to an embodiment of the invention, in the semiconductor device, the third P-high is away from the edge of the portion of the first isolation structure in the active region of the structure-clad channel. Again, Wo

The structure in accordance with an embodiment of the invention includes a shallow trench isolation structure. The structure in accordance with an embodiment of the invention includes a field oxide layer. In the above semiconductor element, among the above-described semiconductor elements, the semiconductor element of the present invention is isolated to have a sufficiently high breakdown current and a low leakage current. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention.

[Embodiment] Figs. 2A to 2B are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 3A through 3B are top views of a flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 4A through 4B are top views of a flow of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. 5A through 5B are top views of a flow of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention. Referring to FIGS. 2A and 3A', a method of fabricating a semiconductor device of the present invention 200919722 - w, 74 24922 twf.d〇c/n is to form an isolation structure 202 in a substrate 200 and form a field implant region under a portion of the isolation structure 202. 212. The substrate 2 is, for example, a semiconductor substrate such as a germanium substrate, or a semiconductor compound substrate, or a germanium (?) substrate on the insulating layer. The isolation structure 202 defines a channel active region 204, active regions 2〇6 and active regions 2〇8 on both sides thereof, and active regions 210′ among the substrates 200. The active regions 204, 206, 208, and 210 are mutually They are separated by an isolation structure 202. The isolation structure 2〇2 may be formed by a shallow trench isolation process Γ' to form a shallow trench isolation structure, or a partial area oxidation method to form a field emulsion layer. The field implant region 212 surrounds the channel active region 204 and the periphery of the active regions 200 and 208 and the active region 21A. The field implant region 212 surrounding the channel active region 204 and the field implant region 212 surrounding the active regions 2〇6 and 2〇8 do not extend to the channel active region 2〇4 and the active regions 206 and 208. The isolation structure 202 is underneath with a spacing. In particular, the channel active zone 204 has two first edge % edges 204a defining a channel width W, each first edge 204a being spaced apart from the first edge 212a of the adjacent field implant zone 212 by a distance d1. The shortest distance between the edges 206a, 208a of the active regions 206 and 208 and the extended line L. of the second edge 212a of the field implant region 212 is d2. The range of the spacing dl can be changed according to actual needs. R is the ratio between the spacing dl and the distance d2, R = dl / d2. Figure 6 is a graph showing the relationship between the ratio R of the PM 〇S and the breakdown voltage and the ratio of the ratio to the residual current (减少) of the PM 〇 S according to an embodiment of the invention. When R is less than 0.15, the pitch dl between the channel active region and the ion implantation region is too small, and the breakdown voltage will be too low. When R is greater than 〇85, 200919722 uml:u-/uu/-uu74 24922twf.doc/n The spacing dl between the active region of the channel and the ion implantation region is too large, the channel width W is too narrow, and the saturation current will be too low. Affect the operational characteristics of the component. In the second embodiment, R = dl / d2' where 0.154 + 0.85. In another embodiment, R = dl / d2, where 〇.26SR^0.52. To achieve the shape and positional relationship of the 0.15 SR^0.85' isolation structure 202 and the field implant region 212, there are various possible variations, which are illustrated by the following three embodiments. 3A through 3B are top views of the flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 4A through 4B are top views of processes of a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. 5A through 5B are top views of a flow of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention. Referring to FIG. 3A, in an embodiment, the purpose of retaining the spacing dl is achieved by the retraction of the width W of the channel active region 2〇4. More specifically, the isolation structure 202 within the field implant region 212 can include isolation structures 214, 216, 218. Isolation structures 216 and 218 surround and extend beyond active regions 206 and 208, respectively. Isolation structure 214 is then located around edge 204a of channel active region 204 between isolation structures 216 and 218. Referring to FIG. 4A, in another embodiment, the width W of the channel active region 204 remains substantially the same, which is substantially the same as the boundary of the isolation structure 202 around the active regions 206 and 208, and corresponds to the field implant region 212. A notch 220 is formed at the edge 204a of the channel active region 204 for the purpose of maintaining the spacing dl. More specifically, isolation structures 202 200919722, 24922 twf.doc/n within field implant region 212 may include isolation structures 214, 216, 218. Isolation structures 216 and 218 surround the active regions 206 and 208, respectively, and generally have a common boundary with the channel active regions 2〇4. Isolation structure 214 is then located around edge 204a of channel active region 204, which protrudes from isolation structures 216, 218 and is located within recess 22'. Referring to FIG. 5A, in another embodiment, the width W of the channel active region 2〇4 is wider, which protrudes from the boundary of the isolation structure 202 around the active regions 206 and 208, and corresponds to the field implant region 212. A notch 222 is formed at the edges 204a and 204b of the channel active region 204 for the purpose of maintaining the spacing di. More specifically, the isolation structure 202 within the field implant region 212 can include isolation structures 214, 216, 218. Isolation structures 216 and 218 surround the active regions 206 and 208, respectively, but cause channel active regions 2〇4 to protrude from isolation structures 216 and 218. The isolation structure 214 is located outside the isolation structures 216 and 218, and the edges 2〇4a and 2〇牝 of the cladding channel active region 2〇4 protruding from the portions of the isolation structure 216 and the isolation structure 218 are located at the recess 222. Inside.

The dopant implanted in the field implant region 212 may be either p-type or N-type. The N-type dopant is, for example, phosphorus or arsenic. The P-type dopant is, for example, boron. The conductivity type of the dopant implanted in the field implant region 212 is different from the subsequently formed doped regions 23A, 232. When the formed component is a ^ channel gold oxide half component,

- The implant implanted in the field implant region 212 is P-type. When the formed component is a P-type channel MOS half-element, the dopant (4) _ S implanted in the field implant region 212. The field implanting area 212 can be formed by the ionic implant method. When the isolation structure 202 is formed by shallow trench isolation, the shape of the field implant region 212 200919722 —----74 24922 tw £ d 〇 C/n after forming the shallow trench, before filling the insulating layer, first The substrate is implanted into a mask layer. Next, an ion implantation process is performed to form a field: ===. When the isolation structure 2°2 can be used to form the implantation method of the implanted area 212, the second method of the implantation process is performed, and the mask layer is removed. ϋ 社 社 社 社 社 社 社 社 社 社 社 1 1 1 1 1 5Β 'The base 200 is formed to open to the periphery of the crucible ii=222, and the channel active region 204 is extended and interposed. The gate structure 224 can include a patterned gate conductive layer 228 patterned t# 226 ^^-4^. Gate dielectric oxidized Mengyang, nitrogen oxide bed dielectric method. Gate conduction method 3: If it is thermal oxidation or chemical vapor deposition, it is doped with yttrium, which is a material based on stone foundation, such as -. When the gate is conducted, the polycrystalline silicon or the undoped polycrystalline silicon is composed of a metal layer. The chemical layer is composed of a doped polysilicon layer and a bismuth compound, a refractory metal such as a refractory metal such as a refractory metal, an alloy of the metal, and an electrical layer of the metal, via a lithography layer and a gate. The guided gate dielectric layer 226 is patterned to rise/map, and then in the active region 2; 8 = 2 electrical layer 228. And doping regions 230, 12 200919722 to 74 24922twf.doc/n 232, 234 are formed in 21 , to complete the fabrication of the semiconductor device 2 . The method of cultivating the area, attacking, and 234 can be adopted by the lining method to implant the human 206, the application and the middle. When the formed semiconducting, = 234 yuan = 2 zone 230' 232 can be used as the source (four) zone two = as a pick up region. When the semiconductor component is added, for example, an N-type high voltage device, the dopant in the doped regions 23A, 232 is N-type. N type doping _ such as dish or Kun. = 20 is a P-type channel of gold oxide semi-dilute, for example, the dopant in the p-type high voltage field doping regions 230, 232 is p-type. The p-type push substance is, for example: In the above embodiment of the present invention, the field implanted area is not formed under the structure around the active area of the channel, and the distance between the proportional ranges is left. "The rule of 0.15 plus 0.85 of the present invention is due to 〇.15 or, therefore, in the area The PN junction is not formed, and the breakdown voltage can be increased. On the other hand, due to the inspection 85, an appropriate saturation electric current can be controlled. In the above embodiment of the present invention, the active region of the channel can be changed. L, two widths and / or field implants (four) position, so that the channel active ^ ^ = leaving a gap below the structure, therefore, it is very useful in the application, although the invention has been disclosed by way of example 'It is not intended to limit the invention to the present invention. Any modifications and refinements may be made without departing from the spirit of the invention. Therefore, the present invention is protected & The definition of the patent scope shall prevail. 巳 [Simplified description of the drawings] Figure 1 is a schematic cross-sectional view of a gold-oxide half element. 13 200919722 One to one, vv74 24922twf.doc / n Figures 2A to 2B are implemented in accordance with the present invention Example 3A to 3B are top views of a flow of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. FIGS. 4A through 4B are diagrams showing another embodiment of the present invention. Figure 5A to Figure 5B are top views of a flow of a method of fabricating a semiconductor device in accordance with still another embodiment of the present invention. Figure 6 is a diagram of a process for fabricating a semiconductor device in accordance with another embodiment of the present invention. A ratio of the ratio R of the PMOS and the breakdown voltage and the percentage of the saturation current reduction shown in the embodiment. [Main component symbol description] 20: Semiconductor component 202, 214, 216, 218: isolation structure 204: channel active Regions 204a, 204b, 206a, 208a, 212a: edges 206, 208, 210: active regions 212. Field implant regions 220, 222: recess 224: gate structure 226: gate dielectric layer 228: gate conductive layer 230, 232, 234: doped area W: channel width dl, d2: spacing 14

Claims (1)

200919722 -----^. . 74 24922twf. doc/n X. Patent Application Range: 1. A semiconductor component comprising: - an isolation structure is located in a substrate, wherein a first active region and a a second active region and a channel active region between each other are separated from each other by the isolation structure; the field implant region is located around the first active region, the second active region, and the active region of the channel a portion of the isolation structure, wherein the channel active region has two first edges defining a channel width, and each of the first edges is spaced apart from a second edge of the adjacent one of the field implant regions by a distance d1 The shortest distance between the third active edge of the first active region and each of the second active regions and the second edge extending line of the field implant region is d2, R = dl/d2, wherein 0.15 New Zealand .85; a gate structure covering the channel region extends over a portion of the isolation structure; and a source/drain doping region is located in the first active region 盥 the active region. /'π 2. If the material is in the range of (Four), the semi-guided 0.26 is 〇·52. The semiconductor component of the above-mentioned patent scope, wherein: the phase = the conductivity type of the implanted dopant and the source/drain doped region semi-conductive body range The semiconductor device according to item 1, wherein the bovine V body 7 element comprises a p-type gold oxide half element. 5. The semiconductor component of claim 4, wherein the 15 200919722 --------- 74 24922 twf.doc/n P-type gold-oxygen half component comprises a P-type high voltage component. 6. The semiconductor component of claim 4, wherein the field implanted region is implanted with an N-type. 7. The semiconductor component of claim 1, wherein the semiconductor component comprises an N-type gold oxide half component. 8. The semiconductor component of claim 7, wherein the N-type gold-oxide half component comprises an n-type high voltage component. 9. The dopant implanted in the field implant area as described in claim 7 is p-type. The semiconductor component of claim 1, wherein the first active region, the second active region, and a portion of the peripheral region m of the communication region are below the isolation structure. The semiconductor unit of claim 1, wherein the isolation structure located within the % implant-in area comprises: - an isolation structure surrounding the first active area; ::: an isolation structure surrounding Around the second active zone; and around the edge. Off-structure, located in the first side of the active area of the channel 12. 13. In the first common boundary 2, please refer to the semiconductor components described in Item 11, ^, ,, . And the second isolation structure protrudes from the channel, and the semiconductor isolation structure as described in claim 11 and the second isolation structure and the active region of the channel are included in the channel active area ^ 16 200919722 ______ . . . 74 24922twf.doc/n 14. The semiconductor component of claim 11, wherein the channel active region protrudes from the first isolation structure and the second isolation structure. 15. The semiconductor component of claim 14, wherein the third isolation structure is overlaid on an edge of the active region of the first isolation structure and the second isolation structure. 16. The semiconductor component of claim 1, wherein the isolation structure comprises a shallow trench isolation structure. 17. The semiconductor component of claim 1, wherein the isolation structure comprises a field oxide layer. 17