200918906 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種主機板電源信號之測試電路，且 特別是有關於一種具多個電壓準位之主機板電源信號測試 電路。 【先前技術】 富主機被啟動時，主機之電源供應單元（p〇wer Supply200918906 IX. Description of the Invention: [Technical Field] The present invention relates to a test circuit for a power supply signal of a motherboard, and more particularly to a test circuit for a power supply signal of a motherboard having a plurality of voltage levels. [Prior Art] When the rich host is started, the power supply unit of the host (p〇wer Supply)
Unit)會先進行一次自我測試。若所有的電流和電壓達到預 叹值，電源供應單元會發送一個電源良好信號（Power Good) 佗唬給主機板。微處理器則一直會處於重啟狀態（reset)，直 到微處理器的時間控制晶片接收到電源良好信號。 傳統主機板之電壓源通常僅提供一個電壓準位，因此 傳統的主機板僅需測試電壓源是否達到此一電壓準位即 可。然而若電壓源需要提供兩個以上的電壓準位，則主機 板無法正確的測試電I源是否達已到所需的電>1準位。 口此需要一個新的多電壓準位偵測電路，在電壓源需 要提供兩個以上的電壓準位時，正確的偵測電壓源是否達 到所需之電壓準位。 【發明内容】 種多電壓準位偵測 ，月夠測得各電源 因此本發明之一方面就是在提供一 電路，適用於具多種電壓準位之主機板 仏號之電壓準位是否合乎預期。 200918906 依照本發明之一實施例’多電壓準位偵測電路包括複 數個比較器、複數個第一電阻、一電源信號輸入埠以及一 或閘。電源信號輸入埠以及第一電阻係電性連接比較器。 或閘係電性連接各個比較器之輸出端，該或閘係依據比較 器之比較結果輪出一第一電源良好信號。 因此本發明之另一方面就是在提供一種多電壓準位偵 測電路，適用於具有至少兩電壓準位之主機板，能夠測得 各電源信號之電壓準位是否合乎預期。 依照本發明之另一實施例，多電壓準位偵測電路包括 一第一電阻、一第二電阻、一第三電阻、一第四電阻、一 第一比較器、一第二比較器、一第三比較器以及一或閘。 第一電阻、第二電阻、第三電阻以及第四電阻係串接 以分壓一參考電壓，來產生一第一電壓準位、一第二電壓 準位以及一第三電壓準位。第一比較器電性連接第一電阻 以及第二電阻’以比較一輸入電壓以及第一電壓準位。第 二比較器電性連接第二電阻以及第三電阻，以比較輸入電 壓以及第二電壓準位。第三比較器，電性連接第三電阻以 及第四電阻’以比較輸入電壓以及第三電壓準位。或閘則 電性連接第一比較器、第二比較器以及第三比較器。此一 或閘係根據比較器之比較結果產生—第一電源良好信號。 根據上述實施例，多電壓準位偵測電路能夠測得電源 信號之多個電壓準位是否合乎預期。 【實施方式] 200918906 電壓車位偵測電路，適用於具有多種 電壓準位之主機板，能鈞、Βρβ + “ 是否合乎預期 夠測传主機板電源信號之電壓準位 請參照第1Α圖，ji给-+ a 八繪不本發明一實施例電源良好信號 之真值表。在此真值裘φ Α ^, 表中A、B、c分別代表三個比較器 之輸出值或反相輸出值。pGn GD代表電源良好信號。電源良 好信號之數值為1代表雷；e π衣暹源k諕之電壓準位合乎預期，反 之則代表電源信號尚未達到預期準位。 當a、b、c之數值分別等於〇、〇」時，代表電源信 號之電壓值達到第—個電壓準位，使電源良好信號數值為 卜當A、B、C之數值等於卜卜"，代表電源信號之 電壓值達到第二個電壓準位，電源良好信號數值同樣為卜 相對的’當A、B、C之數值分別等於^^時代表電 源信號之電壓值尚未達到第—個電壓準位，使電源良好信 號數值為0。當A、B、C之數值分別等於〇、卜丄時，代 表電源信號之電壓值已超過第一個電壓準位，但是尚未達 到第二個電壓準位’因此使電源良好信號數值亦為〇。 由於上述四個組合的A、B、C數值已可偵測出電源良 好信號的兩個電壓準位是否合乎預期，其他電源良好信號 之數值（符號X)則可視情況選擇為〇或 請參照第1B圖，其繪示本發明—實施例電源良好信號 之卡諾圖。在此卡諾圖中，第一攔代表A之數值，第 則代表B、C之數值，卡諾圖内的其他欄位則代表電源良好 信號之數值。爲了實現簡化電源良好信號所需之邏輯電 200918906 =，我們使卡諾圖上部份x(don，tcare)之數值為丨。因此可 得到電源良好信號PGD之布林函數為 J + Sc。 明參照第2圖，其繪示本發明一實施例多電壓準位偵 測電路之邏輯電路圖。電源良好信號之邏輯電路包括第一 ' 電阻、第二電阻R2、第三電阻R3、第四電阻R4、參考 ^ 電壓輸入埠201、電源信號輸入埠2〇3以及輸出埠217。參 考電壓輸入埠201提供一參考電壓。電阻R1、R2、R3以 及114係串接來分壓參考電壓，以產生第一電壓準位、第二 電壓準位以及一第三電壓準位。或閘211之輪出即為電源 良好信號（PGD)，此一電源良好信號經由及閘215後再由輸 出埠217輪出。 如圖所示，第一比較器2〇5、第二比較器2〇7以及第三 比較器209之正負輸入端電性連接電源信號輪入埠2〇3以 及相應電阻，來比較第一電壓準位、第二電壓準位、第三 電壓準位以及電源信號之電壓值，並據以產生a、&、C。 Ο 或閘211電性連接至上述三個比較器。當4、石、c至少有 一為邏輯1時，或閘211會產生邏輯位準為i的電源良好 信號’並由輸出埠217輸出電源良好信號。 若電源信號的預定電壓值為第二邏輯位準，應該等待 電源信號上升至第二邏輯位準，或閘211輸出之電源良好 信號才為邏輯位準為i的信號。然而當電源信號之電壓值 、 上升至第一邏輯位準，但未達到第二邏輯位準時，或閘211 ' 仍然可能輸出邏輯1，使主機板誤認為電源信號之電壓值已 上升至第二邏輯準位。爲了避免主機板誤認電源信號已上 200918906 升至第二邏輯位準，多電壓準位侦測電路增設了延遲電路 219與及閘215，等待電源信號上升超過第一邏輯位準時才 致能及閘215，使及閘215輸出電源良好信號。換言之，及 閘215以及延遲電路219延遲了或閘211所輸出之電源良 好信號（PGD)。 及閘215電性連接或閘211之輸出端以及延遲電路 ' 219。延遲電路219主要包括緩衝器213、延遲電阻尺7，以 ( 及電容C卜延遲電阻R7電性連接緩衝器213與及閘215， 電容ci則電性連接延遲電阻R7與及閘215。選擇適當的 延遲電阻R7以及電容（^之阻抗值，能夠在電源信號之電 壓值超過第一邏輯準位以後才致能及閘215，使主機板不會 將第一邏輯位準誤認為第二邏輯位準。 請參照第3 A圖，其繪示本發明另—實施例電源良好信 號之真值表。在此真值表中，A、B、C、D分別代表四個 比較器之輪出值或反相輸出值。PGD同樣代表電源良好信 U 號較之第之真值表，第3A圖之真值表多了超額電壓 之判斷。也就是說，當電源信號之電壓值超過第二邏輯準 位過多時（例如第二邏輯準位為5V，而電源信號已上升至 )使電源良好k號之數值為〇，表示此—電源良好信號 不如預期。 類似第1A圖地真值表，當A、B、C、D等於〇〇〇1或 0111時，分別代表電源信號之電壓值達到第一個電壓準位 -以及第二邏輯位準，使電源良好信號數值為丨。當A、B、 C、D之數值等於_Q以及_!時，分別代表^源信號之 200918906 電壓值尚未達到第—電壓準位或第二電壓準位。當A、B、 C D等於1111時，代表電源信號之電壓值超過第二邏輯 準位過多，使電源良好传锛 了此灯琥之數值為〇。由於上述五個組合 的A B C D已可偵測出兩個電壓位準的電源良好信號， 其他電源良好信號之數值（符號χ)則可視情況選擇為°〇或 1 ° 凊參照第3Β圖’其緣示本發明另—實施例電源良好信 、 號之卡諾圖。在此卡諾圖中，第一攔代表A、Β之數值， 第-列則代表C、D之數值，卡諾圖内的其他攔位則代表 電源良好信號之數值。爲了實現簡化電源良好信號所需之 邏輯電路，我們使卡諾圖上部份x(d〇n，t care)之數值等於 1。因此可得到電源良好信號PGD之布林函數為。 請參照第4圖’其繪示本發明另一實施例多電壓準位 偵測電路之邏輯電路圖。電源良好信號之邏輯電路包括第 一電阻R1、第二電阻R2、第三電阻R3、第四電阻r4、第 五電阻R5、參考電壓輸入埠401以及輸出埠419。參考電 壓輸入埠401提供一參考電壓。電阻Ri、R2、R3、R4以 及係串接來分壓參考電壓，以產生第一電壓準位、第二電 壓準位、第三電壓準位以及第四電壓準位。 如第4圖所示，第一比較器405、第二比較器407、第 三比較器409以及第四比較器411之正負輸入端電性連接 電源信號輸入埠403以及相應之電阻，來比較第一電壓準 位、第二電壓準位、第三電壓準位、第四電壓準位以及電 源信號之電壓值，並據以產生比較結果256以及£>。 200918906 或間413電性連接上述四個比較器。當2、5、0以及乃至 少有一為邏輯1時，或閘4ί3會輸出邏輯位準為】的電源 良好信號，並由輸出埠419輸出此一電源良好信號。 不同於第2圖之多電壓準位偵測電路，當電源信號之 電壓值超過第二邏輯準位之合理範圍時，比較器之輸出2、 5、6D分別等於 0、1、〇、1(Α、Β、c、D 等於 1U1)， 使得或閘413輸出邏輯位準為〇之電源良好信號，告知主 機板電源信號之電壓超出合理範圍。 類似第2目，帛4圖實施例之多電壓準位偵測電路亦 增設了延遲電路421與及間417，避免主機板將第一邏輯準 位誤認為第二邏輯準位。及閘417電性連接或閘4丨3之輸 出端以及延遲電路421。延遲電路421 ±要包括緩衝器 415、延遲電阻R7 ’以及電容C1。延遲電阻R7電性連接 緩衝器415與及閘417，電容C1則電性連接延遲電阻R7 與及閘417。當電源錢上升至適#邏輯位準時（例如電源 信號超過第一邏輯位準），延遲電路421才使及閘417之一 輸入端為1，致能及閘417輸出電源良好信號，換言之，及 閘4Π以及延遲電路421延遲了或閘413所輸出:電源 好信號（PGD)。因此當電源信號上升至第一邏輯準位時，主 機板才不會誤認電源信號已上升至第二邏輯準位。 縱上所述’多電壓準位偵測電路適用於具有多種電壓 準位之主機板，能夠測得主機板電源信號是否合乎某一預 定電壓準位。 ' 上，然其並非用 雖然本發明已以一較佳實施例揭露如 200918906 ，限定本發明，任何在本發明所屬技術領域中具有通常知 識者，在不脫離本發明之精神和範圍内，當可作各種之更 動與潤飾’因此本發明之保護範圍當視後附之申請專利範 圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 ( 此更明顯易懂，所附圖式之詳細說明如下： 第1A圖係繪示本發明一實施例電源良好信號之真值 表。 第1B圖係繪示本發明一實施例電源良好信號之卡諾 圖。 第2圖係繪示本發明一實施例多電壓準位偵測電路之 邏輯電路圖。 ϋ 第3Α圖係繪示本發明另一實施例電源良好信號之直 值表。 ^ 第3Β圖，其繪示本發明另一實施例電源良好信號之 諾圖。 第4圖係繪示本發明另一實施例多電壓準位偵測電路 之邏輯電路圖。 i要元件符號說明】 203 :電源信號輪入埠 2〇1 :參考電壓輸入埠 12 200918906 205、207、209 :比較器 211 :或閘 213 :緩衝器 215 :及閘 217 :輸出埠 219 :延遲電路 403 :電源信號輸入埠 401 :參考電壓輸入埠 405、407、409、411 :比較器 413 :或閘 415 :緩衝器 417 :及閘 419 :輸出埠 421 :延遲電路 R1〜R5 :電阻 R7 :延遲電阻 C1 :電容Unit) will conduct a self-test first. If all currents and voltages reach the pre-sense value, the power supply unit sends a Power Good signal to the motherboard. The microprocessor is always in a reset state until the microprocessor's time control chip receives a power good signal. The voltage source of a traditional motherboard usually only provides one voltage level, so the traditional motherboard only needs to test whether the voltage source reaches this voltage level. However, if the voltage source needs to provide more than two voltage levels, the host board cannot correctly test whether the power source I has reached the required power level. This requires a new multi-voltage level detection circuit to correctly detect whether the voltage source has reached the required voltage level when the voltage source needs to provide more than two voltage levels. SUMMARY OF THE INVENTION A multi-voltage level detection method can measure each power supply in a month. Therefore, one aspect of the present invention is to provide a circuit suitable for a voltage level of a motherboard having multiple voltage levels which is expected to be satisfactory. 200918906 In accordance with an embodiment of the present invention, a multi-voltage level detection circuit includes a plurality of comparators, a plurality of first resistors, a power signal input port, and a NAND gate. The power signal input port and the first resistor are electrically connected to the comparator. Or the gate is electrically connected to the output of each comparator, and the OR gate rotates a first power good signal according to the comparison result of the comparator. Therefore, another aspect of the present invention is to provide a multi-voltage level detecting circuit suitable for a motherboard having at least two voltage levels, which can measure whether the voltage level of each power signal is expected. According to another embodiment of the present invention, the multi-voltage level detecting circuit includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first comparator, a second comparator, and a second comparator. The third comparator and one or the gate. The first resistor, the second resistor, the third resistor, and the fourth resistor are connected in series to divide a reference voltage to generate a first voltage level, a second voltage level, and a third voltage level. The first comparator is electrically connected to the first resistor and the second resistor ‘ to compare an input voltage and a first voltage level. The second comparator is electrically connected to the second resistor and the third resistor to compare the input voltage with the second voltage level. The third comparator is electrically connected to the third resistor and the fourth resistor ' to compare the input voltage with the third voltage level. Or the gate is electrically connected to the first comparator, the second comparator, and the third comparator. The one or the gate is generated based on the comparison result of the comparator - the first power good signal. According to the above embodiment, the multi-voltage level detecting circuit can measure whether the plurality of voltage levels of the power signal are satisfactory. [Embodiment] 200918906 Voltage parking space detection circuit is suitable for motherboards with multiple voltage levels. It can 钧, Βρβ + "Whether it is expected to measure the voltage level of the motherboard power supply signal, please refer to the first picture, ji - + a The true value table of the power good signal according to an embodiment of the present invention. In this true value 裘 φ Α ^, A, B, and c in the table represent the output values or inverted output values of the three comparators, respectively. pGn GD stands for power good signal. The value of power good signal is 1 for lightning; the voltage level of e π clothing Siam source k合 is expected, otherwise the power signal has not reached the expected level. When a, b, c value When respectively equal to 〇, 〇", it means that the voltage value of the power signal reaches the first voltage level, so that the value of the power good signal is the value of A, B, C is equal to Bu Bu ", the voltage value of the power signal is reached. The second voltage level, the power good signal value is also the opposite of 'when the values of A, B, and C are equal to ^^ respectively, the voltage value of the power signal has not reached the first voltage level, so that the power good signal value Is 0 . When the values of A, B, and C are equal to 〇 and 丄, respectively, it means that the voltage value of the power signal has exceeded the first voltage level, but the second voltage level has not yet been reached, so the power good signal value is also 〇 . Since the A, B, and C values of the above four combinations can detect whether the two voltage levels of the power good signal are expected, the value of other power good signals (symbol X) can be selected as the case or 参照1B is a diagram showing the Karnaugh map of the power good signal of the present invention. In this Karnaugh map, the first block represents the value of A, the second represents the value of B and C, and the other fields in the Karnaugh map represent the value of the power good signal. In order to achieve the logic power required to simplify the power good signal 200918906 =, we make the value of the part x (don, tcare) on the Karnaugh map to 丨. Therefore, the Boolean function of the power good signal PGD can be obtained as J + Sc. Referring to FIG. 2, a logic circuit diagram of a multi-voltage level detecting circuit according to an embodiment of the present invention is shown. The logic circuit of the power good signal includes a first 'resistor, a second resistor R2, a third resistor R3, a fourth resistor R4, a reference voltage input port 201, a power signal input port 〇2〇3, and an output port 217. Reference voltage input 埠 201 provides a reference voltage. Resistors R1, R2, R3 and 114 are connected in series to divide the reference voltage to generate a first voltage level, a second voltage level, and a third voltage level. Or the turn of the gate 211 is the power good signal (PGD). This power good signal passes through the AND gate 215 and then exits by the output 埠217. As shown, the positive and negative inputs of the first comparator 2〇5, the second comparator 2〇7, and the third comparator 209 are electrically connected to the power signal wheel 埠2〇3 and the corresponding resistors to compare the first voltage. The level, the second voltage level, the third voltage level, and the voltage value of the power signal, and accordingly generate a, &, C. Ο or gate 211 is electrically connected to the above three comparators. When at least one of 4, stone, and c is logic 1, or gate 211 generates a power good signal ' with a logic level i' and a power good signal is output from output 217. If the predetermined voltage value of the power signal is the second logic level, it should wait for the power signal to rise to the second logic level, or the power good signal output by the gate 211 is the signal with the logic level i. However, when the voltage value of the power signal rises to the first logic level, but does not reach the second logic level, or the gate 211 ' may still output a logic 1, causing the motherboard to mistakenly believe that the voltage value of the power signal has risen to the second. Logical level. In order to prevent the motherboard from misidentifying that the power signal has risen to the second logic level on 200918906, the multi-voltage level detection circuit adds a delay circuit 219 and a gate 215 to enable and gate when the power signal rises above the first logic level. 215, and the gate 215 outputs a power good signal. In other words, the AND gate 215 and the delay circuit 219 delay the power good signal (PGD) output from the OR gate 211. The gate 215 is electrically connected or the output of the gate 211 and the delay circuit '219. The delay circuit 219 mainly includes a buffer 213 and a delay resistor 7 to electrically connect the buffer 213 and the gate 215 to the capacitor C. The capacitor ci is electrically connected to the delay resistor R7 and the gate 215. The delay resistor R7 and the impedance value of the capacitor (^ can enable the gate 215 after the voltage value of the power signal exceeds the first logic level, so that the motherboard does not mistake the first logic level as the second logic bit. Please refer to FIG. 3A, which shows a truth table of the power good signal of another embodiment of the present invention. In the truth table, A, B, C, and D represent the round values of the four comparators, respectively. Or inverting the output value. PGD also represents the power good signal U number compared to the first truth value table, the true value table of Figure 3A has more excess voltage judgment. That is, when the voltage value of the power signal exceeds the second logic When the level is too high (for example, the second logic level is 5V, and the power signal has risen to), the value of the power good k number is 〇, indicating that the power good signal is not as expected. Similar to the true value table of Figure 1A, when When A, B, C, and D are equal to 〇〇〇1 or 0111, The voltage value representing the power signal reaches the first voltage level - and the second logic level, so that the power good signal value is 丨. When the values of A, B, C, and D are equal to _Q and _!, respectively represent ^ The voltage value of the source signal of 200918906 has not reached the first voltage level or the second voltage level. When A, B, and CD are equal to 1111, it means that the voltage value of the power signal exceeds the second logic level too much, so that the power supply is well transmitted. The value of this light is 〇. Since the above five combinations of ABCD can detect the power good signal of two voltage levels, the value of other good power signals (symbol χ) can be selected as °〇 or 1 ° depending on the situation.凊 Referring to Figure 3, the present invention is another embodiment of the power good signal, the Karna map. In this Karnaugh map, the first block represents the value of A, Β, the first column represents C, D The value of the other blocks in the Karnaugh map represents the value of the power good signal. In order to achieve the logic required to simplify the power good signal, we make the value of the x (d〇n, t care) on the Karnaugh map. Is equal to 1. Therefore, the power good signal P can be obtained. The Boolean function of GD is as follows. Please refer to FIG. 4, which illustrates a logic circuit diagram of a multi-voltage level detecting circuit according to another embodiment of the present invention. The logic circuit of the power good signal includes a first resistor R1 and a second resistor R2. The third resistor R3, the fourth resistor r4, the fifth resistor R5, the reference voltage input 埠401, and the output 埠419. The reference voltage input 埠401 provides a reference voltage. The resistors Ri, R2, R3, and R4 are connected in series to divide the voltage. The reference voltage is generated to generate a first voltage level, a second voltage level, a third voltage level, and a fourth voltage level. As shown in FIG. 4, the first comparator 405, the second comparator 407, and the third The positive and negative input terminals of the comparator 409 and the fourth comparator 411 are electrically connected to the power signal input port 403 and the corresponding resistors to compare the first voltage level, the second voltage level, the third voltage level, and the fourth voltage level. The bit and the voltage value of the power signal are used to generate a comparison result 256 and £>. 200918906 or 413 is electrically connected to the above four comparators. When 2, 5, 0 and at least one is logic 1, or gate 4ί3 will output a power good signal with logic level, and output 埠419 outputs this power good signal. Different from the voltage level detecting circuit of FIG. 2, when the voltage value of the power signal exceeds the reasonable range of the second logic level, the outputs 2, 5, and 6D of the comparator are equal to 0, 1, 〇, and 1 respectively. Α, Β, c, D is equal to 1U1), so that the gate 413 outputs a power good signal with a logic level of 〇, and informs the motherboard that the voltage of the power signal is out of a reasonable range. Similar to the second item, the multi-voltage level detecting circuit of the embodiment of FIG. 4 also adds a delay circuit 421 and an interval 417 to prevent the motherboard from mistaking the first logic level as the second logic level. The gate 417 is electrically connected or the output of the gate 4丨3 and the delay circuit 421. The delay circuit 421 ± includes a buffer 415, a delay resistor R7', and a capacitor C1. The delay resistor R7 is electrically connected to the buffer 415 and the gate 417, and the capacitor C1 is electrically connected to the delay resistor R7 and the gate 417. When the power supply rises to the appropriate logic level (for example, the power signal exceeds the first logic level), the delay circuit 421 causes one of the inputs of the gate 417 to be 1, and the enable and the gate 417 output a good power signal, in other words, The gate 4Π and the delay circuit 421 are delayed by the output of the gate 413: a power good signal (PGD). Therefore, when the power signal rises to the first logic level, the host board does not mistakenly recognize that the power signal has risen to the second logic level. In the vertical direction, the multi-voltage level detecting circuit is suitable for a motherboard having a plurality of voltage levels, and can measure whether the power signal of the motherboard meets a predetermined voltage level. It is to be understood that the present invention is not limited to the scope of the present invention, and the present invention is not limited by the spirit and scope of the present invention. Various changes and modifications may be made. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other objects, features, advantages and embodiments of the present invention, which are more obvious, the detailed description of the drawings is as follows: FIG. 1A shows a power supply according to an embodiment of the present invention. The true value table of the good signal. Fig. 1B is a diagram showing the card power of the power good signal according to an embodiment of the present invention. Fig. 2 is a logic circuit diagram of the multi-voltage level detecting circuit according to an embodiment of the present invention. 3 is a straight-valued diagram of a power good signal according to another embodiment of the present invention. ^ FIG. 3 is a diagram showing a power good signal according to another embodiment of the present invention. FIG. 4 is a diagram showing another embodiment of the present invention. The logic circuit diagram of the multi-voltage level detecting circuit of the embodiment. i. Symbol description of the component] 203: power signal wheel 埠2〇1: reference voltage input 埠12 200918906 205, 207, 209: comparator 211: or gate 213: Buffer 215: and gate 217: output 埠 219: delay circuit 403: power signal input 埠 401: reference voltage input 埠 405, 407, 409, 411: comparator 413: or gate 415: buffer 417: and gate 419: Output 埠421: delay circuit R1~R 5 : Resistor R7 : Delay resistor C1 : Capacitor
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