TWI614609B - Inter-integrated circuit bus arbitration system - Google Patents

Abstract

The integrated circuit bus arbitration control system includes a first host circuit, a second host circuit, an analog switch circuit, a start determination circuit, and a selection control circuit. When the first data line of the first host circuit changes from a high level to a low level, and the first clock line of the first host circuit is maintained at a high level, the initial determining circuit generates a first start pulse signal. When the second data line of the second host circuit changes from a high level to a low level, and the second clock line of the second host circuit is maintained at a high level, the initial determining circuit generates a second start pulse signal. When the first start pulse signal leads the second start pulse signal, the selection control circuit generates the first control signal, so that the analog switch circuit turns on the electrical connection between the first host circuit and the external clock line and the external data line.

Description

Integrated circuit busbar arbitration control system

The invention relates to an integrated circuit busbar arbitration control system, in particular to an integrated circuit busbar arbitration control system capable of avoiding different hosts simultaneously occupying the same integrated circuit busbar.

INTER-INTEGRATED CIRCUIT (I2C) transmits information between integrated circuits through a data line and a clock line. For example, the host can transmit clock signals and data through the clock and data lines. The signal, the slave can interpret the content of the data signal according to the frequency of the clock signal, and further complete the instructions issued by the host end, such as reading or writing... and the like. Because of the ease of implementation and simple wiring, it is widely used in the design of integrated circuits.

In practice, different host terminals may need to control the same slave. For example, in a sensing system, different processors may need to access the values sensed by the same sensor to make different Analysis and processing. In general, to simplify wiring, the slaves may only have a single integrated circuit bus, so different host terminals are coupled to the same integrated circuit bus. In this case, in order to prevent different host terminals from issuing control commands to the slaves at the same time, the slaves cannot recognize the commands. In the prior art, some hosts may have a built-in detection mechanism, and before issuing commands to the slaves, Detects whether the integrated circuit bus is occupied by other hosts. However, in practice, it is not guaranteed that all the host terminals coupled to the same integrated circuit bus have built-in detection mechanisms, so it only depends on the built-in mechanism of the host, and cannot effectively avoid the use of each host. A collision occurs when the integrated circuit bus is used to control the slave.

An embodiment of the present invention provides an integrated circuit-integrated circuit (I2C) arbitration control system, and the integrated circuit bus arbitration control system includes a first host circuit, a second host circuit, an analog switch circuit, and an initial The judgment circuit and the selection control circuit.

The first host circuit has a first clock line and a first data line, and the first host circuit controls the potential of the first clock line and the first data line according to the data to be transmitted. The second host circuit has a second clock line and a second data line, and the second host circuit controls the potentials of the second clock line and the second data line according to the data to be transmitted.

The analog switch circuit is coupled to the first host circuit, the second host circuit, the external clock line and the external data line. When the analog switch circuit receives the first control signal, the analog switch circuit turns on the first clock line and the external clock. The electrical connection of the line and the electrical connection of the first data line and the external data line. When the analog switch circuit receives the second control signal, the analog switch circuit turns on the electrical connection between the second clock line and the external clock line and the electrical connection between the second data line and the external data line.

The initial determining circuit is coupled to the first host circuit and the second host circuit, and when the potential of the first data line changes from a high potential to a low potential, and the potential of the first clock line is maintained at a high potential, the initial determining circuit is started. A first start pulse signal is generated. When the potential of the second data line changes from a high potential to a low potential, and the potential of the second clock line is maintained at a high potential, the initial determination circuit generates a second start pulse signal.

The selection control circuit is coupled to the initial determination circuit. When the first start pulse signal leads the second start pulse signal, the selection control circuit generates the first control signal. When the first start pulse signal lags behind the second start pulse signal, the selection control circuit generates a second control signal.

FIG. 1 is a schematic diagram of an integrated circuit-integrated circuit (I2C) arbitration control system 100 according to an embodiment of the present invention. The integrated circuit bus arbitration control system 100 includes a first host circuit M1, a second host circuit M2, an analog switch circuit 110, a start determination circuit 120, an end determination circuit 130, and a selection control circuit 140.

The first host circuit M1 has a first clock line SCL1 and a first data line SDA1. The first host circuit M1 can transmit data by controlling the potential of the first clock line SCL1 and the first data line SDA1, that is, the first host. The circuit M1 can transmit the clock signal through the first clock line SCL1 and transmit the data message through the first data line SDA1. Similarly, the second host circuit M2 has a second clock line SCL2 and a second data line SDA2, and the second host circuit M2 can transmit data by controlling the potentials of the second clock line SCL2 and the second data line SDA2.

The analog switch circuit 110 is coupled to the first host circuit M1, the second host circuit M2, the external clock line SCL and the external data line SDA, and the external clock line SCL and the external data line SDA can be coupled to the external slave device. When the analog switch circuit 110 receives the first control signal VCC1, the analog switch circuit 110 can electrically connect the first clock line SCL1 with the external clock line SCL and the electrical properties of the first data line SDA1 and the external data line SDA. When connected, the first host circuit M1 can control the external clock line SCL and the external data line SDA, and operate the slave device connected to the external clock line SCL and the external data line SDA. When the analog switch circuit 110 receives the second control signal VCC2, the analog switch circuit 110 can electrically connect the second clock line SCL2 to the external clock line SCL and the second data line SDA2 and the external data line SDA. Sexual connection. At this time, the second host circuit M2 can control the external clock line SCL and the external data line SDA, and operate the slave device connected to the external clock line SCL and the external data line SDA.

The initial determination circuit 120 is coupled to the first host circuit M1 and the second host circuit M2. According to the transmission protocol of the integrated circuit bus, when the first host circuit M1 wants to control the integrated circuit bus to operate the slave device, the first host circuit M1 will set the potential of the first data line SDA1 to a high potential. It goes low and maintains the potential of the first clock line SCL1 at a high level to indicate that the integrated circuit bus is being mastered. Therefore, when the initial determination circuit 120 detects that the potential of the first data line SDA1 changes from a high potential to a low potential, and the potential of the first clock line SCL1 is maintained at a high potential, the initial determination circuit 120 generates a first start. The pulse signal ST1 is used to indicate that the first host circuit M1 is to be mastered on the integrated circuit bus. Similarly, when the initial determination circuit 120 detects that the potential of the second data line SDA2 changes from a high potential to a low potential, and the potential of the second clock line SCL2 is maintained at a high potential, the initial determination circuit 120 generates a The two start pulse signals ST2 are used to indicate that the second host circuit M2 is to be mastered on the integrated circuit bus.

The selection control circuit 140 is coupled to the initial determination circuit 120. When the selection control circuit 140 detects that the first start pulse signal ST1 leads the second start pulse signal ST2, that is, the second start pulse signal ST2 is generated after the first start pulse signal ST1 is generated, or even After the first start pulse signal ST1 is generated, when the second start pulse signal ST2 is not generated, the selection control circuit 140 generates the first control signal VCC1, and the analog switch circuit 110 turns on the first clock line SCL1 and the outside. The electrical connection of the pulse line SCL and the electrical connection between the first data line SDA1 and the external data line SDA enable the first host circuit M1 to control the external clock line SCL and the external data line SDA.

On the contrary, when the first start pulse signal ST1 lags behind the second start pulse signal ST2, the selection control circuit 140 generates the second control signal VCC2, and the analog switch circuit 110 turns on the second clock line SCL2 and the external clock line. The electrical connection of the SCL and the electrical connection of the second data line SDA2 and the external data line SDA enable the second host circuit M2 to control the external clock line SCL and the external data line SDA.

FIG. 2 is a schematic diagram of a start determination circuit 120 according to an embodiment of the present invention. The initial judgment circuit 120 includes a first D-type flip-flop FF1, a second D-type flip-flop FF2, an exclusive or gate (XOR gate) XOR1, a first pulse generator 122, and a third D. The type flip-flop FF3, the fourth D-type flip-flop FF4, the second mutex or gate XOR2, and the second pulse generator 124.

The first D-type flip-flop FF1 has a data terminal D, a negative-edge clock terminal CLK' and an output terminal Q. The data terminal D of the first D-type flip-flop D1 is coupled to the first clock line SCL1, and the negative edge The clock terminal CLK' is coupled to the first data line SDA1. The second D-type flip-flop FF2 has a data terminal D, a negative edge clock terminal CLK' and an output terminal Q, and a data terminal D of the second D-type flip-flop FF2 is coupled to the output of the first D-type flip-flop FF1. The terminal Q, the negative edge clock terminal CLK' of the second D-type flip-flop FF2 is coupled to the first data line SDA1. The first mutex or gate XOR1 has a first input terminal, a second input terminal, and an output terminal. The first input end of the first mutex or gate XOR1 is coupled to the output terminal Q of the first D-type flip-flop FF1. The second input end of the first mutex or gate XOR1 is coupled to the output terminal Q of the second D-type flip-flop FF2. The first pulse generator 122 can generate the first start pulse signal ST1 according to the potential of the output of the first mutex or gate XOR1.

The first pulse generator 122 includes a first resistor R1, a first capacitor C1, a third mutex or a gate XOR3. The first resistor R1 has a first end and a second end, and the first end of the first resistor R1 is coupled to the output end of the first mutex or gate XOR1. The first capacitor C1 has a first end and a second end. The first end of the first capacitor C1 is coupled to the second end of the first resistor R1, and the second end of the first capacitor C1 is coupled to the ground GND. The third mutex or gate XOR3 has a first input end, a second input end, and an output end, and the first input end of the third mutex or gate XOR3 is coupled to the output end of the first mutex or gate XOR1, and the third mutual The second input end of the repeller or gate XOR3 is coupled to the second end of the first resistor R1, and the output end of the third mutex or gate XOR3 can output the first start pulse signal ST1.

In Fig. 2, in the initial state, the output terminal Q of the first D-type flip-flop FF1 and the output terminal Q of the second D-type flip-flop FF2 are both low (or logic 0), at this time, the first The outputs of the mutex or gate XOR1 and the second mutex or gate XOR2 are also low (or logic 0).

When the first host terminal M1 pulls the potential of the first data line SDA1 from a high potential to a low potential and maintains the potential of the first clock line at a high potential, the potential change of the first data line SDA1 triggers the first The negative edge clock terminal CLK' of the D-type flip-flop FF1 and the negative edge clock terminal CLK' of the second D-type flip-flop FF2, so the output terminal Q of the first D-type flip-flop FF1 outputs the first time The high potential of the pulse line SCL1, and the output terminal Q of the second D-type flip-flop FF2 outputs the low potential of the output terminal Q of the original first D-type flip-flop FF1. Therefore, the first mutex or gate XOR1 will output a high potential (or logic 1) and start charging the first capacitor C1. When the potential of the first capacitor C1 is charged to a critical value, the third mutex or gate XOR3 The potential at the output changes from high (logic 1) to low (logic 0). That is, after receiving the high potential output by the first mutex or gate XOR1, the first pulse generator 122 will generate the first start pulse signal ST1. In some embodiments of the present invention, by selecting the capacitance value of the first capacitor C1 and the resistance value of the first resistor R1, the charging speed of the first capacitor C1 can be adjusted, thereby changing the pulse length of the first starting pulse signal ST1. .

Similarly, the second pulse generator 124 includes the second resistor R2, the second capacitor C2, and the fourth mutex or gate XOR4, the second resistor R2, the second capacitor C2, and the fourth mutex or gate XOR4 operating principle and connection The architecture will be the same as the operating principle and connection architecture of the first resistor R1, the first capacitor C1, and the third mutex or gate XOR3. The connection mode and operation principle of the third D-type flip-flop FF3, the fourth D-type flip-flop FF4, the second mutual-repulsion or gate XOR2, and the second pulse generator 124 are also the same as the first D-type flip-flop FF1 The second D-type flip-flop FF2, the first mutex or gate XOR1 and the first pulse generator 122 are identical, so the potential of the second data line SDA2 is pulled from the high potential to the low potential at the second host terminal M2, and When the potential of the second clock line SCL2 is maintained at a high level, the initial determination circuit 120 also generates a second start pulse signal ST2.

In some embodiments of the present invention, in order to allow the host circuit of the main control integrated circuit bus to terminate the operation of the slave device, the master control of the integrated circuit bus can be given to other host circuits. The circuit bus arbitration control system 100 can use the end determination circuit 130 to detect whether the host circuit ends the operation, and further generate an end pulse signal to reset the D-type flip-flop in the start determination circuit 120. FIG. 3 is a schematic diagram of the end determination circuit 130 according to an embodiment of the present invention.

The end determining circuit 130 is coupled to the first host circuit M1 and the second host circuit M2. According to the communication protocol of the integrated circuit bus, when the potential of the first data line SDA1 changes from a low level to a high level, and the potential of the first clock line SCL1 is maintained at a high level, it indicates that the first host circuit M1 is about to end. The operation of the slave device, at this time, the end determining circuit 130 generates the first end pulse signal CLR1. In the implementation of FIG. 2, the first D-type flip-flop FF1 further includes a reset terminal RST, and the reset terminal RST of the first D-type flip-flop FF1 can receive and reset according to the first end pulse signal CLR1. A D-type flip-flop FF1 causes the potential of the output terminal Q of the first D-type flip-flop FF1 to become a low potential (logic 0). In addition, the second D-type flip-flop FF2 also includes a reset terminal RST, and the reset terminal RST of the second D-type flip-flop FF2 can receive and reset the second D-type flip-flop according to the first end pulse signal CLR1. FF2.

Similarly, when the potential of the second data line SDA2 changes from a low potential to a high potential, and the potential of the second clock line SCL2 is maintained at a high potential, it indicates that the second host circuit M2 is about to end the operation of the slave device, The end of judgment circuit 130 generates a second end pulse signal CLR2. In the implementation of FIG. 2, the third D-type flip-flop FF3 further includes a reset terminal RST, and the reset terminal RST of the third D-type flip-flop FF3 can receive and reset according to the second end pulse signal CLR2. The three-D type flip-flop FF3 causes the potential of the output terminal Q of the third D-type flip-flop FF3 to become a low potential (logic 0). In addition, the fourth D-type flip-flop FF4 also includes a reset terminal RST, and the reset terminal RST of the fourth D-type flip-flop FF4 can receive and reset the fourth D-type flip-flop according to the second end pulse signal CLR2. FF4.

In the embodiment of FIG. 3, the end judging circuit 130 includes a fifth D-type flip-flop FF5, a sixth D-type flip-flop FF6, a fifth mutex or gate XOR5, a third pulse generator 132, and a seventh D. The type flip-flop FF7, the eighth D-type flip-flop FF8, the sixth mutex or gate XOR6, and the fourth pulse generator 134.

The fifth D-type flip-flop FF5 has a data terminal D, a positive-edge clock terminal CLK and an output terminal Q. The data terminal D of the fifth D-type flip-flop FF5 is coupled to the first clock line SCL1, and the fifth D-type The positive edge clock terminal CLK of the flip-flop FF5 is coupled to the first data line SDA1. The sixth D-type flip-flop FF6 has a data terminal D, a positive-edge clock terminal CLK and an output terminal Q. The data terminal D of the sixth D-type flip-flop FF6 is coupled to the output end of the fifth D-type flip-flop FF5. Q, the positive edge clock terminal CLK of the sixth D-type flip-flop FF6 is coupled to the first data line SDA1. The fifth mutex or gate XOR5 has a first input terminal, a second input terminal, and an output terminal. The first input end of the fifth mutex or gate XOR5 is coupled to the output terminal Q of the fifth D-type flip-flop FF5. The second input end of the fifth exclusive OR gate XOR5 is coupled to the output terminal Q of the sixth D-type flip-flop FF6. The third pulse generator 132 can generate the first end pulse signal CLR1 according to the potential of the output of the fifth mutex or gate XOR5.

In other words, the operating principle and connection structure of the fifth D-type flip-flop FF5, the sixth D-type flip-flop FF6, the fifth mutually exclusive or gate XOR5, and the third pulse generator 132 are the same as the first D-type flip-flop FF1. The second D-type flip-flop FF2, the first mutex or gate XOR1 and the first pulse generator 122 are similar, the main difference is that in order to match the communication start and end conditions of the integrated circuit bus, the fifth D-type is positive The clock terminal CLK of the inverter FF5 and the sixth D-type flip-flop FF6 is a positive edge trigger, and the clock terminal CLK' of the first D-type flip-flop FF1 and the second D-type flip-flop FF2 is triggered by a negative edge. . In this way, the end determination circuit 130 can generate the first end pulse signal CLR1 when the potential of the first data line SDA1 is changed from the low potential to the high potential and the potential of the first clock line SCL1 is maintained at the high potential.

Similarly, the operation principle and connection structure of the seventh D-type flip-flop FF7, the eighth D-type flip-flop FF8, the sixth mutually exclusive or gate XOR6, and the fourth pulse generator 134 and the fifth D-type flip-flop FF5 The sixth D-type flip-flop FF6, the fifth mutex or gate XOR5, and the third pulse generator 132 are the same, so the end determination circuit 130 can change from the low potential to the high potential at the potential of the second data line SDA2, and When the potential of the second clock line SCL2 is maintained at a high level, a second end pulse signal CLR2 is generated.

Further, in the embodiment of FIG. 3, the third pulse generator 132 includes a third resistor R3, a third capacitor C3, a seventh mutex or gate XOR7, and a first AND gate AND1. The third resistor R3 has a first end and a second end, and the first end of the third resistor R3 is coupled to the output end of the fifth mutex or gate XOR5. The third capacitor C3 has a first end and a second end. The first end of the third capacitor C3 is coupled to the second end of the third resistor R3, and the second end of the third capacitor C3 is coupled to the ground end GND. The seventh mutex or gate XOR7 has a first input end, a second input end and an output end, and the first input end of the seventh mutex or gate XOR7 is coupled to the output end of the fifth mutex or gate XOR5, the seventh mutual The second input end of the repeller or gate XOR7 is coupled to the second end of the third resistor R3. The first AND gate AND1 has a first input end, a second input end and an output end, and the first input end of the first AND gate AND1 is coupled to the output end of the seventh mutex or gate XOR7, and the first gate AND1 The two inputs are used to receive the system reset signal SRST, and the output of the first AND gate AND1 can output the first end pulse signal CLR1.

That is, after the third pulse generator 132 receives the high potential of the fifth mutex or gate XOR5 output, the two inputs of the seventh mutex or gate XOR7 will be at different potentials, thus the seventh mutex The output of the gate XOR7 will first go high until the third capacitor C3 is charged to a high potential, and the output of the seventh mutex or gate XOR7 will return to a low potential, so that the first end pulse signal CLR1 can be generated. In addition, in the embodiment of FIG. 3, the first end pulse signal CLR1 is logically outputted through the first pole gate AND1 and the reset signal SRST, that is, the end judging circuit 130 is resetting the signal. When SRST is high (logic 1), that is, the first end pulse signal CLR1 is output when the system is not reset. If the reset signal SRST is low (logic 0), it means that the integrated circuit bus arbitration control system 100 needs to be reset. At this time, the fifth D-type flip-flop FF5 in the determination circuit 130 is ended. The reset terminal RST of the six D-type flip-flop FF6, the seventh D-type flip-flop FF7, and the eighth D-type flip-flop FF8 will receive the reset signal SRST, so that the fifth D-type flip-flop FF5, sixth The D-type flip-flop FF6, the seventh D-type flip-flop FF7, and the eighth D-type flip-flop FF8 are correspondingly reset.

Similarly, in the embodiment of FIG. 3, the fourth pulse generator 134 includes a fourth resistor R4, a fourth capacitor C4, an eighth mutex or gate XOR8, and a second AND gate AND2, and the fourth pulse generator 134 The internal connection mode and operation principle of the third pulse generator 132 are also the same, so that the potential of the second data line SDA2 can be changed from a low potential to a high potential, and the potential of the second clock line SCL2 is maintained at a high potential. A second end pulse signal CLR2 is generated.

FIG. 4 is a schematic diagram of a selection control circuit 140 in accordance with an embodiment of the present invention. The selection control circuit 140 includes a first inverter INV1, a second inverter INV2, a third AND gate AND3, a ninth D-type flip-flop FF9, a fourth AND gate AND4, and a tenth D-type flip-flop FF10. The first inverter INV1 has an input end and an output end, and the second inverter INV2 has an input end and an output end. The third AND gate AND3 has a first input end, a second input end and an output end, the first input end of the third AND gate AND3 can receive the first start pulse signal ST1, and the second input end of the third AND gate AND3 is coupled At the output of the first inverter INV1. The ninth D-type flip-flop FF9 has a preset end PRST and an output terminal Q, and the preset end PRST of the ninth D-type flip-flop FF9 is coupled to the output end of the third AND gate AND3, and the ninth D-type flip-flop The output terminal Q of the FF9 is coupled to the input end of the second inverter INV2, and can output the first control signal VCC1. The fourth AND gate AND4 has a first input end, a second input end and an output end, the first input end of the fourth AND gate AND4 can receive the second start pulse signal ST2, and the second input end of the fourth AND gate AND4 It is coupled to the output end of the second inverter INV2. The tenth D-type flip-flop FF10 has a preset end PRST and an output terminal Q, and the preset end PRST of the tenth D-type flip-flop FF10 is coupled to the output end of the fourth AND gate AND4, and the tenth D-type flip-flop The output end of the FF10 is coupled to the input end of the first inverter INV1, and can output the second control signal VCC2.

Since the first control signal VCC1 and the second control signal VCC2 are both low (logic 0) in the initial state, the second input of the third AND gate AND3 is high. When the selection control circuit 140 receives the first start pulse signal ST1, the first input terminal of the third AND gate AND3 becomes high, so the output of the third AND gate AND3 becomes high (logic 1). At the same time, the ninth D-type flip-flop FF9 is preset to output a high potential, so the selection control circuit 140 can output the first control signal VCC1. At this time, the second input terminal of the fourth AND gate AND4 is fixed at a low potential via the second inverter INV2, so that even if the selection control circuit 140 receives the second start pulse signal ST2, the second input pulse signal ST2 will not be generated. Two control signals VCC2.

On the contrary, if the selection control circuit 140 first receives the second start pulse signal ST2, the second input terminal of the third AND gate AND3 is fixed at a low potential, so that even after the selection control circuit 140 receives the first start pulse The signal ST1 also does not generate the first control signal VCC1.

In this way, the integrated circuit bus arbitration control system 100 can effectively and quickly distribute the integrated circuit bus to the host circuit that first proposes the master control without causing conflicts between different host circuits.

In addition, in the embodiment of FIG. 4, the ninth D-type flip-flop FF9 and the tenth D-type flip-flop FF10 may further include a reset terminal RST, and the reset terminal RST of the ninth D-type flip-flop FF9 may be The first end pulse signal CLR1 is received, and the reset terminal RST of the tenth D-type flip-flop FF10 can receive the second end pulse signal CLR2. In this way, when the end determining circuit 130 detects that the first host circuit M1 or the second host circuit M2 is about to stop the operation of the slave device, the first end pulse signal CLR1 or the second end pulse signal CLR2 may also be used. The ninth D-type flip-flop FF9 and the tenth D-type flip-flop FF10 are reset so that the selection control circuit 140 can return to the initial state and judge the next operation.

In some embodiments of the present invention, the integrated circuit bus arbitration control system 100 can also support more than two host circuits. For example, the initial determination circuit 120 can determine the operation of each host circuit to correspondingly generate the start pulse signal and the end pulse signal by using the structure as shown in FIG. 2, and in the selection control circuit 140, The number of supported host circuits is adjusted to the number of inputs to the gate, for example with four inputs. In this way, as long as any one of the four host circuits first presents a master control request to the integrated circuit bus, the selection control circuit 140 preferentially generates a corresponding control signal, and the structure according to FIG. The control signal can prevent the selection control circuit 140 from continuing to generate other control signals, thereby preventing the other three host circuits from simultaneously acquiring the master control of the integrated circuit bus.

In summary, the integrated circuit bus arbitration control system proposed by the embodiment of the present invention can effectively arbitrate between the host circuits, so that the host circuit that firstly requests the use of the integrated circuit bus can be obtained. The mastership of the integrated circuit bus, while avoiding the use of the required host circuit to occupy the integrated circuit bus, causes collisions with each other. Moreover, the components required for the integrated circuit busbar arbitration control system proposed by the embodiments of the present invention are simple, and do not require complicated software control, thereby simplifying the design of the overall system without excessively increasing the burden on the hardware. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100‧‧‧Integrated Circuit Bus Arbitration Control System

110‧‧‧ analog switch circuit

120‧‧‧Start judgment circuit

130‧‧‧End judgment circuit

140‧‧‧Select control circuit

M1, M2‧‧‧ host circuit

SDA1, SDA2, SDA‧‧‧ data lines

SCL1, SCL2, SCL‧‧‧ clock line

ST1, ST2‧‧‧ starting pulse signal

CLR1, CLR2‧‧‧ end pulse signal

VCC1, VCC2‧‧‧ control signals

122, 124, 132, 134‧‧ ‧ pulse generator

FF1, FF2, FF3, FF4, FF5, FF6, FF7, FF8, FF9, FF10‧‧‧D type flip-flops

XOR1, XOR2, XOR3, XOR4, XOR5, XOR6, XOR7, XOR8‧‧‧ Mutual exclusion or gate

R1, R2, R3, R4‧‧‧ resistance

C1, C2, C3, C4‧‧‧ capacitors

D‧‧‧ data side

Q‧‧‧output

RST‧‧‧Reset

CLK’‧‧‧ negative edge clock end

AND1, AND2, AND3, AND4‧‧‧ and gate

SRST‧‧‧Reset signal

CLK‧‧‧ positive edge

INV1, INV2‧‧‧ inverter

PRST‧‧‧ Preset

FIG. 1 is a schematic diagram of an integrated circuit busbar arbitration control system according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a start determination circuit according to an embodiment of the present invention. FIG. 3 is a schematic diagram of an end judging circuit according to an embodiment of the present invention. Figure 4 is a schematic diagram of a selection control circuit in accordance with an embodiment of the present invention.

100‧‧‧Integrated Circuit Bus Arbitration Control System

110‧‧‧ analog switch circuit

120‧‧‧Start judgment circuit

130‧‧‧End judgment circuit

140‧‧‧Select control circuit

M1, M2‧‧‧ host circuit

SDA1, SDA2, SDA‧‧‧ data lines

SCL1, SCL2, SCL‧‧‧ clock line

ST1, ST2‧‧‧ starting pulse signal

CLR1, CLR2‧‧‧ end pulse signal

VCC1, VCC2‧‧‧ control signals

Claims (9)

An integrated circuit-integrated circuit (I2C) arbitration control system includes: a first host circuit having a first clock line and a first data line for controlling the data according to a data to be transmitted a second clock circuit and a second data line for controlling the second clock line and the first data line according to the data to be transmitted The potential of the second data line; the analog switch circuit is coupled to the first host circuit, the second host circuit, an external clock line and an external data line for turning on when a first control signal is received Electrically connecting the first clock line to the external clock line and the first data line and the external data line, and when receiving a second control signal, turning on the second clock line An electrical connection with the external clock line and an electrical connection between the second data line and the external data line; a first determining circuit coupled to the first host circuit and the second host circuit for The potential of the first data line changes from a high potential to a high potential a potential, and when the potential of the first clock line is maintained at the high potential, generating a first start pulse signal, and when the potential of the second data line changes from the high potential to the low potential, and the second time When the potential of the pulse line is maintained at the high potential, a second start pulse signal is generated, and the initial judgment circuit includes: a first D-type flip-flop having a data end coupled to the first clock line, a negative edge clock end is coupled to the first data line, and an output end; a second D-type flip-flop has a data end coupled to the output end of the first D-type flip-flop, The first edge of the negative edge is coupled to the first data line and the output end; and the first exclusive input or gate (XOR gate) has a first input coupled to the first D type The output end of the inverter, a second input end coupled to the output end of the second D-type flip-flop, and an output end; a first pulse generator for generating the first start pulse signal according to the potential of the output of the first mutex or gate; a third D-type flip-flop having a data end coupled to the second a pulse line, a negative edge clock end coupled to the second data line, and an output end; a fourth D-type flip-flop having a data end coupled to the output of the third D-type flip-flop a negative edge clock terminal coupled to the second data line, and an output terminal; a second mutual repulsion gate having a first input coupled to the output of the third D-type flip-flop a second input end coupled to the output end of the fourth D-type flip-flop and an output end; and a second pulse generator for outputting the output according to the second mutex or gate a second start pulse signal is generated by the potential; and a selection control circuit is coupled to the initial determination circuit for generating the first control signal when the first start pulse signal leads the second start pulse signal And generating the second control signal when the first start pulse signal lags behind the second start pulse signal. The integrated circuit bus arbitrating control system of claim 1, wherein the first pulse generator comprises: a first resistor having a first end coupled to the output of the first mutex or gate And a second end; a first capacitor having a first end coupled to the second end of the first resistor, and a second end coupled to the ground end; and a third mutually exclusive or gate The first input end is coupled to the output end of the first mutex or the gate, the second input end is coupled to the second end of the first resistor, and an output end is configured to output the first start Pulse signal; and The second pulse generator includes: a second resistor having a first end coupled to the output end of the second mutex or gate, and a second end; a second capacitor having a first end coupling Connected to the second end of the second resistor, and a second end coupled to the ground end; and a fourth mutex or gate having a first input coupled to the second mutex or gate The output terminal has a second input end coupled to the second end of the second resistor, and an output end configured to output the second start pulse signal. The integrated circuit bus arbitration control system of claim 1 or 2, further comprising an end determining circuit coupled to the first host circuit and the second host circuit for using the potential of the first data line When the low potential changes to the high potential, and the potential of the first clock line is maintained at the high potential, a first end pulse signal is generated, and when the potential of the second data line changes from the low potential to the low potential a high potential, and the potential of the second clock line is maintained at the high potential, generating a second end pulse signal, wherein: the first D-type flip-flop further includes a reset end for receiving and according to the The first end pulse signal resets the first D-type flip-flop; the second D-type flip-flop further includes a reset terminal for receiving and resetting the second D-type according to the first end pulse signal The third D-type flip-flop further includes a reset terminal for receiving and resetting the third D-type flip-flop according to the second end pulse signal; and the fourth D-type flip-flop A reset terminal is included for receiving and resetting the fourth D-type flip-flop according to the second end pulse signal. The integrated circuit bus arbitration control system according to claim 3, wherein the termination determining circuit comprises: a fifth D-type flip-flop having a data terminal coupled to the first clock line, a positive edge clock The end is coupled to the first data line, and an output end; a sixth D-type flip-flop having a data end coupled to the output end of the fifth D-type flip-flop, a positive edge clock end The first data input is coupled to the output end of the fifth D-type flip-flop, and the second input end is coupled to the output terminal of the fifth D-type flip-flop. The output terminal of the sixth D-type flip-flop and an output terminal; and a third pulse generator for generating the first end pulse signal according to the potential of the output terminal of the fifth mutex or gate a seventh D-type flip-flop having a data terminal coupled to the second clock line, a positive edge clock terminal coupled to the second data line, and an output terminal; an eighth D-type positive The inverter has a data terminal coupled to the output end of the seventh D-type flip-flop, a positive-edge clock terminal coupled to the second data line, and an output terminal; a mutually exclusive switch having a first input coupled to the output of the seventh D-type flip-flop, a second input coupled to the output of the eighth D-type flip-flop, and a And a fourth pulse generator for generating the second end pulse signal according to the potential of the output of the sixth mutex or gate. The integrated circuit bus arbitration control system of claim 4, wherein the third pulse generator comprises: a third resistor having a first end coupled to the output of the fifth mutex or gate And a second end; a third capacitor having a first end coupled to the second end of the third resistor, and a second The end is coupled to the ground; and a seventh mutually exclusive switch having a first input coupled to the output of the fifth mutex or gate, and a second input coupled to the third resistor The second end, and an output end; and the fourth pulse generator includes: a fourth resistor having a first end coupled to the output end of the sixth mutex or gate, and a second end; a fourth capacitor having a first end coupled to the second end of the fourth resistor, and a second end coupled to the ground end; and an eighth mutex or gate having a first input coupling A second input end is coupled to the second end of the fourth resistor, and an output end. The integrated circuit bus arbitration control system of claim 5, wherein the third pulse generator further includes a first AND gate having a first input coupled to the seventh mutual exclusion Or the output end of the gate, a second input terminal for receiving a system reset signal, and an output terminal for outputting the first end pulse signal; the fourth pulse generator further comprising a second gate and having a first input end is coupled to the output end of the eighth mutex or gate, a second input end is configured to receive the system reset signal, and an output end is configured to output the second end pulse signal; The fifth D-type flip-flop further includes a reset terminal for receiving and resetting the fifth D-type flip-flop according to the system reset signal; the sixth D-type flip-flop further includes a reset end, Receiving and resetting the sixth D-type flip-flop according to the system reset signal; the seventh D-type flip-flop further includes a reset terminal for receiving and resetting according to the system reset signal The seventh D-type flip-flop; and the eighth D-type flip-flop further includes a reset terminal for receiving and resetting the eighth D-type flip-flop according to the system reset signal. The integrated circuit bus arbitration control system according to claim 1 or 2, wherein the selection control circuit comprises: a first inverter having an input end and an output end; and a second inverter having an input And a third output gate having a first input terminal for receiving the first start pulse signal, a second input terminal coupled to the output end of the first inverter, and an output a ninth D-type flip-flop having a pre-set coupled to the output of the third AND gate, an output coupled to the input of the second inverter, and configured to output the a first control signal; a fourth input gate having a first input terminal for receiving the second start pulse signal, a second input terminal coupled to the output end of the second inverter, and an output And a tenth D-type flip-flop having a preset end coupled to the output end of the fourth AND gate, an output end coupled to the input end of the first inverter, and configured to output The second control signal. The integrated circuit bus arbitration control system of claim 7, further comprising an end determining circuit coupled to the first host circuit and the second host circuit for using the potential of the first data line The low potential becomes the high potential, and when the potential of the first clock line is maintained at the high potential, a first end pulse signal is generated, and when the potential of the second data line changes from the low potential to the high potential And the second end pulse signal is generated when the potential of the second clock line is maintained at the high potential, wherein: the first D-type flip-flop further includes a reset end for receiving and according to the first End pulse signal weight Positioning the first D-type flip-flop; the second D-type flip-flop further includes a reset terminal for receiving and resetting the second D-type flip-flop according to the first end pulse signal; The D-type flip-flop further includes a reset terminal for receiving and resetting the third D-type flip-flop according to the second end pulse signal; and the fourth D-type flip-flop further includes a reset end. And configured to receive and reset the fourth D-type flip-flop according to the second end pulse signal. The integrated circuit bus arbitrating control system of claim 8, wherein the end determining circuit comprises: a fifth D-type flip-flop having a data terminal coupled to the first clock line, a positive edge clock The end is coupled to the first data line, and an output end; a sixth D-type flip-flop having a data end coupled to the output end of the fifth D-type flip-flop, a positive edge clock end The first data input is coupled to the output end of the fifth D-type flip-flop, and the second input end is coupled to the output terminal of the fifth D-type flip-flop. The output terminal of the sixth D-type flip-flop and an output terminal; and a third pulse generator for generating the first end pulse signal according to the potential of the output terminal of the fifth mutex or gate a seventh D-type flip-flop having a data terminal coupled to the second clock line, a positive edge clock terminal coupled to the second data line, and an output terminal; an eighth D-type positive The inverter has a data terminal coupled to the output end of the seventh D-type flip-flop, a positive-edge clock terminal coupled to the second data line, and an output terminal; An exclusive or gate (XOR gate) having a first input coupled to the output of the seventh D-type flip-flop, and a second input coupled to the eighth D-type forward and reverse Device The output terminal, and an output terminal; and a fourth pulse generator for generating the second end pulse signal according to the potential of the output terminal of the sixth mutex or gate.