200915564 九、發明說明： 【發明所屬之技術領域】 本發明大體上係關於整流器’且更明確地說，係關於 使用場效應結構的整流器。 【先前技術】 整流器係一種雙終端裝置，其通常係使用在電路中用 以於其中一個方向中導通電流並且於相反的方向中阻隔電 流。整流器的主元件係一電位屏障，其會相依於被施加至 外部電極的電位的記號來控制電流載子流動。近年來僅使 用兩種主要技術來製造整流器。在蕭特基屏障二極體（80〇) 中^在金屬與一半導體之間的介面處創造該電位屏 障。此屏障係由彼此接觸的該金屬與該半導體的功函數之 間的差值來定義。SBD提供非常良好的低正向電壓降（高達 o.4v)，其為二極體的主效能特徵，不過已知的係會有可靠 度問題。由於沒有載子調變的關係、，所以它們並無法耐受 高正向電流突波。在金屬化製程期間會因為尖波的關係而 引起額外的可靠度問題出現，其會降低崩潰電壓並且會降 減^量。即制㈣槽㈣基技術，其Μ允許取得較 高的崩潰電壓’但是實際的SBD仍會被限制在以下 的崩潰電壓。ΡΝ接面技術通常係用於更高電壓。它們通 會提供較高的VF(在〇·7ν以上），並且因而會提供較低的致 率，但卻會提供較高的可靠度U由於载子密度調變的 關係，它們能夠耐受大額的電流突波。另夕卜，因為最大電 200915564 場係在PN接面處而並非如動之中係在表面處，所以， 金屬化尖波並不會造成早期崩潰的問題。 已、·’呈有人提出以在M〇s閘極下方的場效應為基礎的其 匕方式用以結合一 SBD的高效率與pN接面二極體的高 可罪度。舉例來說，在虛擬蕭特基屏障：極體與超屏障整 流器中，會透過處理（舉例來說’植入、擴散、氧化、…等） 在該閘極下方於該半導體的本體中創造該電位屏障。在該 MOS閘極下方的通道僅會被輕微地反向並且可被視為多數 載子的屏障。此屏障的高度可受控於閑極厚度以及該閑極 下方的摻雜濃度。該屏障的存在會造成和SBD雷同的整流 仃為。SBD可能具有一固定的屏障高度，其會對應於和矽 產生良好接觸的金屬；而在先前技術裝置中，該屏障高度 則可能會連續地改變。短通道長度以及良好控制該通道區 域中的摻雜作用對製造實用裝置來說皆非常重要。低電壓 (100V以下的崩潰電壓）超屏障整流器已經顯現出結合高可 靠度（和PN接面二極體雷同）與高效率的結果。 不過，此等先前技術裝置的許多高電壓形式（額定電壓 在1 50V以上）卻會表現出負微分電阻。任何負電阻區均可 用來製造振盪器；但是，在整流器，這卻係不樂見的行為 而且必須避免。因此，該些先前技術裝置在高電壓處會受 到明顯的限制。 為克服先前技術的缺陷以便可靠地操作在高電壓處， 控制該負電阻區非常地重要，其可能會相依於其它因素而 增加或縮減。負電阻的來源係因注入載子的關係造成漂移 200915564 £电阻係數快速下降。如圖1中所不’圖中所示的係一典 型先前技術場效應屏障整流器的模型，總漂移區電阻通常 會被模擬分成兩個部分，R i與R2。頂端電阻R 1，其通常會 控制P-N接面上的電壓；以及底部電阻r2。一旦電阻R玉 與通道上的電壓降之總和在該P-N接面的膝部電壓v*之上 時’電洞便會從P-N接面被注入該漂移區。為維持準中性， 電子會k基板處被注入。此快速成長的載子濃度會降低該 漂移區的電阻係數以及電阻上的電壓降。該漂移區上的 電壓降便可能會造成負電阻。藉由改變電阻Ri便能夠有效 地控制該負電阻’因為其能夠改變開始注入時的臨界電流 (I )並且因為負電阻的斜率會相依於比值。因此，Ri 下降會增加負電阻區，而Ri提高則會縮減負電阻區。 R2/R1 —Nd | A1W2/ND2 A2 W ι 其中，八2為汲極區的總面積；而〜會比較小，因為電 流無法流過P區。Wi接近該P區的厚度，而W2為介於該p 區與基板之間的距離。必要的崩潰電壓會設定底部磊晶區 (Ν〇2)中的施體濃度，而頂端區（Ndi)中的施體濃度則可以被 調整。 用以在場效應整流器中控制負電阻的其中一方式係調 王頂層中的施體遭度，其已在R〇d〇v V.，Ankoudinov A.L.，200915564 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to rectifiers' and more particularly to rectifiers using field effect structures. [Prior Art] A rectifier is a dual terminal device that is typically used in a circuit to conduct current in one of the directions and to block current in the opposite direction. The main component of the rectifier is a potential barrier that controls the flow of current carriers depending on the sign of the potential applied to the external electrodes. In recent years, only two main techniques have been used to fabricate rectifiers. This potential barrier is created at the interface between the metal and a semiconductor in the Schottky barrier diode (80 〇). This barrier is defined by the difference between the metal in contact with each other and the work function of the semiconductor. The SBD provides a very good low forward voltage drop (up to o.4v), which is the main performance characteristic of the diode, but the known system has reliability issues. Because they have no carrier modulation, they cannot withstand high forward current surges. Additional reliability issues arise during the metallization process due to the sharp wave relationship, which reduces the breakdown voltage and reduces the amount. Instant (four) slot (four) base technology, which allows for higher crash voltages', but the actual SBD will still be limited to the following crash voltages. The ΡΝ junction technique is typically used for higher voltages. They provide higher VF (above 〇·7ν) and thus provide lower yields, but provide higher reliability. U can withstand large carriers due to carrier density modulation. The amount of current surge. In addition, because the maximum power of 200915564 is at the PN junction and not at the surface, the metallized spike does not cause early collapse. It has been proposed that the 匕 method based on the field effect under the M〇s gate is used to combine the high efficiency of an SBD with the high sin of the pN junction diode. For example, in a virtual Schottky barrier: a polar body and a super-barrier rectifier, the process is created in the body of the semiconductor under the gate by processing (eg, 'implantation, diffusion, oxidation, ..., etc.) Potential barrier. The channel below the MOS gate is only slightly reversed and can be considered a barrier to most carriers. The height of this barrier can be controlled by the thickness of the idler and the doping concentration below the idler. The presence of this barrier will result in the same rectification as the SBD. The SBD may have a fixed barrier height that will correspond to the metal that produces good contact with the crucible; in prior art devices, the barrier height may change continuously. The short channel length and good control of the doping in this channel region are very important for the fabrication of practical devices. Low voltage (crash voltages below 100V) ultra-barrier rectifiers have been shown to combine high reliability (similar to PN junction diodes) with high efficiency. However, many of the high voltage forms of these prior art devices (rated at voltages above 150 V) exhibit negative differential resistance. Any negative resistance region can be used to make the oscillator; however, in the rectifier, this is an unpleasant behavior and must be avoided. Therefore, these prior art devices are subject to significant limitations at high voltages. To overcome the deficiencies of the prior art in order to operate reliably at high voltages, controlling the negative resistance region is very important, which may increase or decrease depending on other factors. The source of the negative resistance is drift due to the relationship of the injected carrier. 200915564 The resistivity decreases rapidly. The model of a typical prior art field effect barrier rectifier, as shown in Figure 1 of Figure 1, the total drift region resistance is typically divided into two parts, R i and R2. The top resistor R 1, which normally controls the voltage on the P-N junction; and the bottom resistor r2. Once the sum of the voltage drop across the resistor R and the channel is above the knee voltage v* of the P-N junction, the hole is injected into the drift region from the P-N junction. In order to maintain quasi-neutrality, the electrons will be injected into the substrate. This rapidly growing carrier concentration reduces the resistivity of the drift region and the voltage drop across the resistor. The voltage drop across this drift region can cause negative resistance. The negative resistance can be effectively controlled by changing the resistance Ri because it can change the critical current (I) at the start of injection and because the slope of the negative resistance will depend on the ratio. Therefore, a decrease in Ri will increase the negative resistance region, while an increase in Ri will reduce the negative resistance region. R2/R1 — Nd | A1W2/ND2 A2 W ι where 8 2 is the total area of the drain region; and ~ will be smaller because current cannot flow through the P region. Wi is close to the thickness of the P region, and W2 is the distance between the p region and the substrate. The necessary breakdown voltage sets the donor concentration in the bottom epitaxial zone (Ν〇2), while the donor concentration in the tip zone (Ndi) can be adjusted. One of the ways to control the negative resistance in a field effect rectifier is to adjust the donor body in the top layer of the king, which is already in R〇d〇v V., Ankoudinov A.L.,
Gh〇Sh P.所著的 Solid State Electronics 2007，51:714-718 中作過分析。藉由使用雙層磊晶結構將N d i縮減兩倍已足以 從I-V曲線中移除負電阻。不過，此種解決負電阻問題的方 200915564 式可能並非係最佳的實用方式’因為要製造出雙層磊晶結 構係更困難的作法。 另一項主要關心議題則係該二極體可從正向電流導通 被切換成反向電流阻隔的速度。反向復原中的其中一項主 要關心的議題係儲存時間，其至少部分相依於存在於該屏 p早區中的多少電荷數量。在能夠產生空乏層以支持反向電 壓之A，要移除此電荷會耗費一些時間。雖然總儲存電荷 仍然會主要決定該總反向復原作用，不過，某些合理數額 的儲存電荷卻相當實用，因為其能夠提供軟恢復（s〇ft recovery)並且減少電磁干擾問題。因此，反向復原的柔軟性 會文到總儲存電荷和接面電容的影響。為最佳化二極體反 向復原作用，若能夠快速地空乏該通道區並且能夠在反向 復原與電磁發射的速度之間進行取捨的話會很有幫助。 簡要概述先前技術會得到下面結論： 場效應二極體可提供習知蕭特基技術或PN接面技術無 法達成的效能與可靠度之良好結合。 為防止負電阻’先前技術場效應二極體通常會需要特 殊手段來調整頂層電阻。 快速地空乏該通道區並且操作在高頻處而沒有大額電 磁干擾的能力，在至少某些實施例中係所希的結果。 【發明内容】 本發明包括一種可調節的場效應整流器（下文中有時候 會稱為「AFER」）裝置’其具有一調節囊袋或區域，其可讓 200915564 。亥表置在冋電ε處可靠且有效地運作，而不需先前技術裝 置的負電阻’同日守還可在高頻處進行快速恢復與操作而不 會有大額電磁干擾。用於製造根據本發明之裝置的方法包 括挖開該閘極氧化物，接著則進行離子植入，用以在該開 口下方創#雜物濃度。倘若不希望該摻雜區與該金屬 之間有接觸的話，可以氧化物覆蓋該開口。 引進本發明的調節囊袋會提供更彈性的裝置設計，因 為其允許在處理期間修正頂層電阻。於某些實施例中，會 「希望提高該項層電阻，藉由於該囊袋中進行p +植入便可達 成此目的。或者，亦可使用N +植入來降低該頂層電阻。對 高電壓裝置來說，P +植入可用來移除負電阻並且從而改正 場效應整流器效能。N+植入則可用來改善低電壓二極體的 效月b。該調$囊袋結構的額外優點係可卩降低接面電容以 及被儲存在該通道區中的電荷，從而改善二極體的反向恢 復特徵。 【實施方式】 首先參考圓2，圖中以200來顯示一可調節的場效應整 流器（為簡化起見，下文中有時候會簡稱為「afeRj )的實 施例，而於該圖示配置中，其包含一可調節的區域，或囊 袋，下文將作更詳細的討論。由於該場效應的關係，該载 子傳輸的屏障會產生在MOS閘極2〇5的下方。該屏障高度 會受控於閘極材料、閘極氧化物厚度、以及該閘極下方的 半導體中的摻雜濃度。於該閘極的中央會蝕出一囊袋21〇; 200915564 而在該開口的下方則會創造出一淺P +植入區，其可能會透 過氣化物層220而與源極215產生絕緣，或是會直接被連 接至該源極電極（以達更快速的效能）。上面所述的配置已繪 製在圖2中。為清楚起見，圖2中已經省略源極、閘極、 以及囊袋之間的連接線；不過’其會被包含在圖4之中。 該連接線通常係由一導體層來施行，舉例來說，一金屬層。 5亥淺P +植入區225會限制多數載子的流動，從而提高頂層 電阻R1。熟習本技術的人士便會明白，本發明的裝置可能 係Ν型或Ρ型，端視該基板和相關的處理而定。為達簡化 的目的，下文將說明的係一 Ν型基板，但是其不應被視為 具有限制意義。 該調節囊袋210包括一位於該閘極2〇5之中的開口 220，於該開口中會植入一摻雜物。於某些實施例中，該調 節囊袋可能還包括一位於該開口 22〇上方的氧化物，用以 幫助確保沒有任何明顯電流能夠通過該調節區。於至少某 些實施例中會希望從該閘極開口的兩側處有實質相等的電 阻器1以防止其中一側在操作期間會變成較不具作用 性。如此的不平衡會造成裝置效能的惡化。為幫助在該閉 極的兩側創造實質相等的電阻，於一眚 1 ^ 貫施例中會使用自對 準處理。 小型Ν+接點230會為電子声担Iy a 于机& i、連接至金屬的歐姆接 點。於某些實施例中，倘若該 /接點處的蕭特基屏障高度小 於閘極下方的屏障高度的話， 則可此會避免產生該N+接 點。於此實施例中’整流行A仫 丁馮係取決於通道屏障而非該蕭 200915564 特基屏障高度 並且提供和由 維持準中性。 。N++基板235會在結構的 背面提供歐姆接點 240所產生的電洞一樣多的電子，從而 化圖式中’本發明的AFER結構類似m〇sfet 、、，。構，其閘極會被短路至源極。因此，可以修正一刪服 ^電路符號來代表該AFER裝置，如圖3中所示。不過，根 本毛明為充當_有效的整流器，會大幅地修正 數⑽極氧化物厚度、通道長度、通道之間的距離、.等）參 其包含實質移除先前技術中用以絕緣閘極與源極的氧化物 層。此外’會加入該調節區，該調節區也會被短路至該閘 極與忒源極。其結果係，本發明之結構的行為會如同一不 見負電阻的网效能二極體。所生成的二極體的極性和本 質體二極體的極性相同。因此’對_ N型裝置來說，該源 極電極會變成該二極體的陽極；而對一 p型裝置來說，該 源極則會變成該二極體的陰極。 接著參考圖4,在正向偏壓中，電流會從閘極4〇5下方 水平地從頂端源極電極41〇處流出，克服通道屏障達到載 子傳輸的目的。接著，電流會經由N磊晶層42〇來散佈， 改變成主要為垂直的方向，並且流向汲極電極425。p井4川 的空乏層與淺P植入區44〇的空乏層（圖4中的虛線 與440 A)並未重豐，不過會將電流流動侷限在一狹窄的區域 中並且決定電阻R1。在該通道與電阻R1上的組合電壓降 抵達「膝部」電壓（約0.6V)之前，垂直本質pN二極體43〇 並未扮演任何角色。在該電壓之上，p井43〇會將電洞注入 200915564 該N磊晶層420之中’其會造成導電性調變並且提供本發 明的場效應整流器處置大額正向突波電流的At力 於反向偏麼期間，並且因為顯示在：二閉極、以及 囊袋區之間的連接線445的關係，在與p囊袋440 附近的空乏層430A與440A的尺寸合士 e T攻長，而且最後會開 始重疊，如圖4令的虛線曲線45〇處所示。熟習本技術的 人士便會明白，曲線450可被視為係一等位線，用以描述 反向偏壓期間該空乏層的成長。這會決定該裝置的漏電 流。對較高的外加反向偏壓來說，哕处 ^凡这空乏層的行為雷同於 PN、接面二極體的行為。請注意，p囊袋會促成早期央止作 用並且降低該裝置的漏電流。 偏壓數個實施例中’該調節囊袋在正向偏壓與反向 偏壓之間的切換期間會為裝置效能提供數項重要的改善。 部！的閑極被移除’所以，接面電容會自動下降。 ί穑：4者’當該裝置被正向偏壓時，會有較少的載子被 累積在該閘極下方。古合 很 產生該空乏層之…: 縮短在反向恢復期間開始 例中，用於批曰 過的儲存時間。因此’於—實施 連同該調㈣命（舉例來說’電子照射）的傳統方法 允許操作在最二頻:虛佳化反向恢復作用，其接著便 如圖5中所僅會有最小的電磁干擾。 調節該頂端電’於至少某些實施例中，該調節區還會 阻。虛線所示的二Γ在高電麼AFER中避免出現負電 二極體的J_ v # '又本發明之調節區並且呈現負電阻的 特徵。實曲線所示的係根據本發明加入0.25 12 200915564 ::之調節區’針對相同裝置參數的 亚未顯現任何負 曲線而且該曲線 之調節區的裝置的吓丁㈣具有〇.35“m 阻已經移卜, 曲線，而且該曲線同樣顯現出該負電 勻的掺雜物濃产，其^電阻的方法的優點係可以使用均 山谓/辰度，其會比較容易製造。 兩阻=電M WO伏特以下的低電壓裝置通常不會有負 :向2门 化該結構，本發明希望最小化該裝置的 ^ =同日守㈣漏保持在可接受的位準處。於某些實施 ::，該調節區藉由納入一 Ν+囊袋植入區來降低在圖：中 被模擬成電阻5| R I &带 ° ，電阻同樣有助於此最佳化作用。於該 貫〇中 厚氧化物較佳的係會被沉積在該調節囊袋 中，用以防止電流流過該囊袋。雖然並非所有實施例皆需 要，不過’此步驟仍會被納入下文討論的方法流程内。 熟習本技術的人士便會明白，上面所述的afer結構會 改善反向恢復作用並且會控制頂端電阻以的數值。如上文 的討論’高R1數值可讓高電壓裝置解決負電阻問題，而低 R1數值則可用來改善低電壓裝置的效率。 接著參考圖61 16,從圖中大體上可以更明白一種用 於製造AFER裝置的製程的其中一實施例。圖中假設已經在 一基板上成長出一磊晶層，連同後面典型的半導體裝置生 產步驟在内，圖中均不會詳細顯示。藉由改變摻雜濃度（n 型）和此磊晶層的厚度可以調節崩潰電壓。一保護環（Guard Ring ; GR)結構（於至少某些實施例中，其大小等級為〇5至 5/zm)會使用該等標準方法中其中一種方法被建立，並且會 13 200915564 藉由熱氧化、對石夕氧化物進行CVD、結合此兩種方法、或 是任何其它合宜方法來形成-場氧化物。該保護環遮罩伟 用來在該場氧化物中挖開―視窗，經由該視窗會引二罩: 井植入區，接著便會進行熱擴散。接著便會使用該場遮罩 在該場氧化物中挖開一視窗，用以製造該裝置的主動區。 請特別參考圖6，—閘極氧化物_會被成長至具有 30至200A的大小等級，垃t &上、e , 、 接著會成長一大小等級為600至 12〇〇A的多晶石夕層605。接著會顯影一閘極遮罩610,而後 便會垂直㈣該多^ 6G5，其會造成圖6中所示之具有開 口 615與620的結構。倘若特殊實施例希望降低圖2中如 R1所示之電阻的話，便可於此階段經由開口 615與62〇來 進行接點砷（As)植入。 接著參考圖7,在閘極遮罩71〇的頂端會製造一第二覆 蓋遮罩700，用以覆蓋調節囊袋7〇5。於某些實施例申，會 希望將該閘極遮罩黏著附接至晶s ;或者，用以利用氮化 矽或其匕〇且材料來製造該閘極遮罩。此遮罩排列有助於 使用在«置的整個Φ積中具有均勻屏g高度和R1數值的 自對準製程。 接著參考圖8，接點砷植入物8〇5與p井硼會被植入， 從而造成多個P井810。於某些實施例中，p井硼的劑量會 經過選擇而使其夠高，以限制主電流流過該通道區。 接著參考圖9’ 一接點井9〇〇會被垂直蝕刻至矽之中， 用以接觸該P井。若沒有此接點，p井中的電荷便可能會受 到經由該保護環結構的P井流至陽極的電洞流的影響。於 200915564 某些實例中，這可能會降低裝置操作速度。該等接點井有 助於最佳化主動裝置區的使用並且讓電洞從p井直接流至 源極電極。此外，還會保留充分的歐姆接點讓電子流動， 因為大部分的電子流都會流過閘極下方的狹窄通道。熟習 本技術的人士便會明白’於某些實施例中’在形成該等接 點井之後，該等已植入As中僅有一小部分會殘留。 接著參考圖10，閘極遮罩71〇與覆蓋遮罩7〇〇會被等 向蝕刻，其會為圖U中所示的通道硼1100植入提供一自 對準遮罩，從巾幫助綠保該裝置的才目關部I中會有均勻的 屏障高度。該覆蓋遮罩同樣會在此階段中被蝕刻，不過仍 會覆蓋該調節區。 —參考圖12，該等閘極遮罩與覆蓋遮罩均會被移除，接 著θ進订P型囊袋12GG植入，用以提高頂端區的電阻R1， 以便限制電流流動。於某些實施例中，尤其是該調節囊袋 中的閘極下方的摻雜濃度大於通道區中的摻雜濃度的實施 圖12中所示的結構便係最終的結構。這便可能不需要 作進一步的處理步驟。 不過於某些實施例中，可能會希望藉由加入多個氧 化物側壁或是一氧化物層來更進一步產生該調節囊袋。這An analysis was made in Solid State Electronics 2007, 51: 714-718 by Gh〇Sh P. Reducing N d i by twice using a two-layer epitaxial structure is sufficient to remove the negative resistance from the I-V curve. However, this method of solving the negative resistance problem may not be the best practical method' because it is more difficult to manufacture a double-layer epitaxial structure. Another major concern is the speed at which the diode can be switched from forward current conduction to reverse current blocking. One of the main concerns in reverse recovery is the storage time, which depends, at least in part, on the amount of charge present in the early region of the screen p. In A, which is capable of generating a depletion layer to support the reverse voltage, it takes some time to remove this charge. Although the total stored charge will still primarily determine the total reverse recovery, some reasonable amount of stored charge is quite useful because it provides soft recovery and reduces electromagnetic interference problems. Therefore, the softness of the reverse recovery will affect the total stored charge and junction capacitance. To optimize the reverse recovery of the diode, it can be helpful if the channel area can be quickly depleted and the trade-off between reverse recovery and electromagnetic emission speed can be made. A brief overview of the prior art leads to the following conclusions: Field effect diodes provide a good combination of performance and reliability that is not possible with conventional Schottky or PN junction technology. To prevent negative resistance, prior art field effect diodes typically require special means to adjust the top layer resistance. The ability to quickly deplete the channel region and operate at high frequencies without large amounts of electromagnetic interference is the result of at least some embodiments. SUMMARY OF THE INVENTION The present invention includes an adjustable field effect rectifier (hereinafter sometimes referred to as "AFER") device that has an adjustment pocket or region that allows for 200915564. The hai table is reliably and efficiently operated at the ε ε, without the need for the negative resistance of the prior art device. The same day can also be quickly recovered and operated at high frequencies without large electromagnetic interference. The method for making the device according to the invention comprises excavating the gate oxide, followed by ion implantation to create a # impurity concentration below the opening. If it is not desired to have contact between the doped region and the metal, the opening can be covered by an oxide. The introduction of the regulatory pouch of the present invention provides a more flexible device design as it allows for correction of the top layer resistance during processing. In some embodiments, "it is desirable to increase the resistance of the layer by p+ implantation in the pouch. Alternatively, N+ implantation may be used to reduce the top resistance. For voltage devices, P+ implants can be used to remove negative resistance and thereby correct field-effect rectifier performance. N+ implants can be used to improve the efficiency of low-voltage diodes. The additional advantage of this pocket-bag structure is The junction capacitance and the charge stored in the channel region can be reduced, thereby improving the reverse recovery characteristics of the diode. [Embodiment] Referring first to the circle 2, an adjustable field effect rectifier is shown at 200 in the figure. (For simplicity, the following will sometimes be referred to simply as "afeRj" embodiment, and in the illustrated configuration, it includes an adjustable area, or pocket, as discussed in more detail below. In the field effect relationship, the barrier of the carrier transmission is generated below the MOS gate 2〇5. The barrier height is controlled by the gate material, the gate oxide thickness, and the doping in the semiconductor under the gate. Miscellaneous concentration The center will erode a pocket 21〇; 200915564 and below the opening will create a shallow P + implant area, which may be insulated from the source 215 through the vapor layer 220, or directly Connected to the source electrode (for faster performance). The configuration described above has been drawn in Figure 2. For clarity, the source, gate, and pocket have been omitted from Figure 2. The connection line; however, it will be included in Figure 4. The connection line is usually implemented by a conductor layer, for example, a metal layer. 5 HI shallow P + implant area 225 will limit the majority of the carrier Flowing, thereby increasing the top layer resistance R1. Those skilled in the art will appreciate that the apparatus of the present invention may be of the Ν type or Ρ type depending on the substrate and associated processing. For the sake of simplicity, as will be explained below. A type of substrate, but it should not be considered limiting. The conditioning pouch 210 includes an opening 220 in the gate 2〇5 in which a dopant is implanted. In some embodiments, the conditioning pouch may further include a slot in the opening The oxide above 22 turns to help ensure that no significant current can pass through the conditioning region. In at least some embodiments it may be desirable to have substantially equal resistors 1 from both sides of the gate opening to prevent one of them. The side becomes less active during operation. Such imbalance can cause deterioration of the device's performance. To help create substantially equal resistance on both sides of the closed pole, self-alignment is used in a uniform example. Quasi-processing. The small Ν+contact 230 will be an electronic sound source Iy a to the machine & i, an ohmic junction connected to the metal. In some embodiments, if the Schottky barrier height at the junction is less than The height of the barrier below the gate can avoid the generation of the N+ junction. In this embodiment, the rectification line A depends on the channel barrier rather than the height of the Xiao 200915564 special barrier and is maintained and maintained. Quasi-neutral. . The N++ substrate 235 will provide as many electrons as the holes generated by the ohmic contacts 240 on the back side of the structure, so that the AFER structure of the present invention is similar to m〇sfet, . The gate is shorted to the source. Therefore, it is possible to correct a circuit symbol to represent the AFER device, as shown in FIG. However, the fundamental Mao Ming acts as a _effective rectifier, which will greatly correct the number of (10) electrode oxides, the length of the channel, the distance between the channels, etc.), including the substantial removal of the prior art used to insulate the gate and The oxide layer of the source. In addition, the adjustment zone will be added, and the adjustment zone will also be shorted to the gate and the source. As a result, the structure of the present invention behaves as if the net performance diode of the negative resistance is not the same. The polarity of the generated diode is the same as the polarity of the body diode. Thus, for a _N-type device, the source electrode becomes the anode of the diode; for a p-type device, the source becomes the cathode of the diode. Referring next to Figure 4, in forward bias, current will flow horizontally from the top source electrode 41〇 below the gate 4〇5, overcoming the channel barrier for carrier transfer. Then, the current is spread through the N epitaxial layer 42 ,, changed to a predominantly vertical direction, and flows to the drain electrode 425. The depleted layer of p-well 4 and the shallow layer of shallow P-embedded zone 44 (dashed line and 440 A in Figure 4) are not heavy, but limit current flow to a narrow area and determine resistance R1. The vertical essential pN diode 43〇 does not play any role until the combined voltage drop across the channel and resistor R1 reaches the "knee" voltage (about 0.6V). Above this voltage, the p-well 43〇 will inject holes into the N15 epitaxial layer 420 of 200915564, which will cause conductivity modulation and provide the field effect rectifier of the present invention to handle large forward surge currents. During the reverse bias period, and because of the relationship between the two closed poles and the connecting line 445 between the pocket regions, the size of the depletion layers 430A and 440A near the p pocket 440 is equal to the attack. Long, and will eventually begin to overlap, as shown in the dotted line 45〇 of Figure 4. Those skilled in the art will appreciate that curve 450 can be viewed as an equipotential line to describe the growth of the depletion layer during reverse bias. This will determine the leakage current of the device. For higher applied reverse bias, the behavior of this depletion layer is similar to that of PN and junction diodes. Please note that the p-bag will contribute to the early central stop and reduce the leakage current of the device. In the bias embodiment, the adjustment pocket provides several important improvements in device performance during switching between forward bias and reverse bias. unit! The idle pole is removed. Therefore, the junction capacitance will automatically drop.穑: 4' When the device is forward biased, fewer carriers are accumulated under the gate. The ancient combination produces the vacant layer...: Shorten the storage time for the batch during the reverse recovery period. Thus the traditional method of '--implementation along with the tone (four) life (for example, 'electron illumination) allows operation at the second-order frequency: virtual optimization reverse recovery, which then has only minimal electromagnetics as shown in Figure 5. interference. Adjusting the tip power in at least some embodiments, the adjustment zone is also blocked. The diwax shown by the dashed line avoids the negative voltage of the diode J_v # ' in the high-voltage AFER and the regulation region of the present invention and exhibits the characteristics of a negative resistance. The solid curve is shown in accordance with the present invention by adding 0.25 12 200915564 :: the adjustment zone 'there is no negative curve for the same device parameter, and the device of the adjustment zone of the curve has a 〇.35"m resistance already The transfer curve, and the curve also shows that the negatively charged dopant is rich in production, and the advantage of the method of resistance is that the average value can be used, which is relatively easy to manufacture. Two resistance = electric M WO Low voltage devices below volts typically do not have a negative: to gate the structure, the present invention contemplates minimizing the device's ^ = same day (4) leakage remains at an acceptable level. In some implementations::, The adjustment zone is reduced by the inclusion of a Ν + capsular implant region in the figure: it is modeled as a resistor 5 | RI & with °, the resistance also contributes to this optimization. Preferably, the system is deposited in the conditioning pouch to prevent current flow through the pouch. Although not all embodiments are required, 'this step will still be incorporated into the method flow discussed below. People will understand that the above The afer structure will improve the reverse recovery and will control the value of the top resistor. As discussed above, the high R1 value allows the high voltage device to resolve the negative resistance problem, while the low R1 value can be used to improve the efficiency of the low voltage device. Referring to Figure 61, one embodiment of a process for fabricating an AFER device can be substantially more apparent from the drawings. It is assumed that an epitaxial layer has been grown on a substrate, along with typical semiconductor device fabrication steps that follow. None of the figures will be shown in detail. The breakdown voltage can be adjusted by varying the doping concentration (n-type) and the thickness of the epitaxial layer. A guard ring (GR) structure (in at least some embodiments) Medium, the size of which is 〇5 to 5/zm) will be established using one of these standard methods, and will be tempered by thermal oxidation, CVD, or both methods, or Is any other suitable method to form a field oxide. The guard ring mask is used to dig a window in the field oxide, through which the second cover is introduced: the well implanted area, and then Thermal diffusion will occur. The field mask will then be used to dig a window in the field oxide to fabricate the active area of the device. Please refer specifically to Figure 6, the gate oxide _ will be grown to have A size of 30 to 200A, lat & upper, e, and then will grow a polysilicon layer 605 of size 600 to 12 A. A gate mask 610 will then be developed and then Vertical (d) the plurality of 6G5, which results in the structure having openings 615 and 620 as shown in Figure 6. If a particular embodiment wishes to reduce the resistance as shown by R1 in Figure 2, it can be via the opening 615 at this stage. 62 〇 to perform contact arsenic (As) implantation. Referring next to Fig. 7, a second cover mask 700 is formed at the top end of the gate mask 71 to cover the adjustment pockets 7〇5. In some embodiments, it may be desirable to adhere the gate mask to the crystal s; or to fabricate the gate mask using tantalum nitride or a tantalum thereof. This mask arrangement facilitates the use of a self-aligned process with a uniform screen g height and R1 value throughout the entire Φ product. Referring next to Figure 8, the junction arsenic implant 8〇5 and the p-well boron will be implanted, resulting in a plurality of P-wells 810. In some embodiments, the dose of boron in the p-well is selected to be high enough to limit the flow of primary current through the channel region. Referring next to Figure 9', a contact well 9 is vertically etched into the crucible for contacting the P well. Without this contact, the charge in the p-well may be affected by the flow of the P-well to the anode via the guard ring structure. In some instances of 200915564, this may reduce the speed of operation of the device. These contact wells help optimize the use of the active device area and allow the holes to flow directly from the p-well to the source electrode. In addition, sufficient ohmic contacts are retained to allow electrons to flow because most of the electron flow will flow through the narrow passage below the gate. Those skilled in the art will appreciate that in some embodiments, only a small portion of the implanted As will remain after the formation of the contact wells. Referring next to Figure 10, the gate mask 71 and the cover mask 7 are equally etched, which provides a self-aligned mask for the channel boron 1100 implant shown in Figure U. There is a uniform barrier height in the gate I of the device. The cover mask will also be etched at this stage, but will still cover the adjustment area. - Referring to Figure 12, the gate mask and the cover mask are both removed, and then the θ-booking P-bag 12GG is implanted to increase the resistance R1 of the tip region to limit current flow. In some embodiments, particularly the doping concentration below the gate in the conditioning pouch is greater than the doping concentration in the channel region. The structure shown in Figure 12 is the final configuration. This may not require further processing steps. In some embodiments, however, it may be desirable to further produce the conditioning pouch by the addition of multiple oxide sidewalls or an oxide layer. This
:從圖1 3開始顯示，圖中先沉積一大小等級為50至500A f的氧化物層（圖中以數字13〇〇來表示），接著會擺放一覆 蓋遮罩1305。Ah — 接者’參考圖14，該氧化物會被垂直蝕刻， 接著則會移除该覆蓋遮罩1305，如圖15中所示。圖15所 丁的便係希望降低圖2中R1所示之電阻的實施例的最終結 15 200915564 構’並且其已在該調節 I·- 丫 lie N型植入區。此方式舍 降低R1，同時還合ρ大® — B 電子、.里由該調節區的開口流至源極。 妾著纟圖16中所不’該氧化物會被垂直蝕刻，直到 僅留下該等氧化物侧卷主 iL ^, _ 堃為止。此結構所示的係希望提高R j 之數值的最終結構’而且其會在該調節區中使㈣p型植 "此 '、。構允卉电洞從該調節區中的p接點流至源極電極， 從而達成快速操作的目#，同時限制流至該源極的電子流 僅會經過該通道區。 本文已經對本發明的實施例$同其眾多帛代例與等效 例：了完整說明，，"本技術的人士便會明白，本發明存 在著眾多替代例與等效例，它們並不脫離本發明並且希望 、.’内入其範疇内。因此，本發明並不受限於前面說明。 【圖式簡單說明】 圖1所示的係場效應屏障整流器的先前技術結構。頂 端的氧化物是自對準製程的殘留物並且代表金屬黏著與熱 移除的問題。電阻R1必須要降低以解決負電阻問題。 圖2所示的係根據本發明的可調節的場效應整流器 (AFER)的一實施例。電阻R1已因幾何形狀而降低並且解決 了負電阻問題。該實施例還會促進較佳的熱接觸與電性接 觸。 圖3所示的係以一 MOSFET來表示該AFER的電路圖， 其閘極電極會被短路至源極。二極體的極性和該M〇SFET 本質體二極體的極性相同。此已短路的MOSFET無法一直 16 200915564 當作一有效的二極體，而且需要慎選結構性參數（閘極氧化 物厚度、通道長度、…等）。 圖4所*的係該AFER的操作。在正向偏壓期間，各個 P區的空乏層並不會重疊(圖中以虛線顯示)並且電子能夠從 通道區輕易地流至汲極。在反向偏壓期間，空乏層的尺寸 會增長並且會在夾止之後開始重疊（參見點虛線）。此夾止作 用效應有助於降低該裝置的洩漏。 圖5所示的係600V AFER的正向電流密度相對於外加 電壓的關係圖。不具有調節區的結構會呈現負電阻。引進 0.2 5 # m寬與0.35# m寬的調節區便會解決該問題。該調節 區中的寬度與摻雜濃度亦可用來改善低電流密度處的裝置 效能。 圖6所示的係使用閘極遮罩垂直蝕穿多晶矽間極與閘 極氧化物（其可能會留下一些閘極氧化物以降低穿隧作用 之後的結構。 圖7顯示出覆蓋遮罩會被放置在該閘極遮罩上，用以 覆蓋該調節區開口。 圖8所不的係實施p +井硼植入與接點砷植入的示意圖。 圖9顯不出會在矽之中蝕出一溝槽，用以提供連接至 忒P井的歐姆接點。請注意，已植入的砷中僅小部分會被 留下。 圖1〇顯示出兩個遮罩均會被等向蝕刻。此自對準步驟 會在整個裝置中提供均勻的屏障高度。 圖11顯不出通道硼會被植入。植入劑量會決定通道内 17 200915564 部的電位屏障高度。在至少某些實施例中會希望使用 準製程’用以幫助確保整個晶片中會具有相同的屏障高度。 圖12顯示出閘極遮罩與覆蓋遮罩會被移除。接點硼會 =。倘若劑量很高的話’調節區中的屏障高度會高於 =區中料障高度。於此情況中，其可能係最終結構。 、便可旎會將氧化物或氧化物壁放進該調節區之中， .2*^ ISl 匕〆 一 · 圖"顯不出絕緣氧化物層會被沉積。覆蓋遮罩會被放 ，用以讓氧化物保持在調節區之中。 圖14顯示出氧化物會被蝕刻。 圖b顯示出覆蓋遮罩會被移除。其可作為最終結構，: Starting from Figure 13, the oxide layer of the size of 50 to 500 Å is first deposited (indicated by the number 13 图 in the figure), and then a cover mask 1305 is placed. Ah — Receiver Referring to Figure 14, the oxide will be etched vertically, and then the cover mask 1305 will be removed, as shown in FIG. Figure 15 is intended to reduce the final junction of the embodiment of the resistor shown by R1 in Figure 2 and it is already in the adjustment I·- 丫 lie N-type implant region. In this way, R1 is lowered, and at the same time, ρ大® — B electrons are transferred from the opening of the adjustment zone to the source. Next, the oxide is etched vertically until the oxide side roll main iL ^, _ 留下 is left. The structure shown in this structure is intended to increase the final structure of the value of R j ' and it will make (iv) p-type plant " this in the adjustment zone. The structure allows the hole to flow from the p-junction in the adjustment zone to the source electrode, thereby achieving a fast operation, while limiting the flow of electrons flowing to the source through the channel zone. The embodiments of the present invention have been described in terms of numerous embodiments and equivalents thereof. It will be understood by those skilled in the art that the present invention is susceptible to numerous alternatives and equivalents. The invention is also intended to be in its scope. Therefore, the present invention is not limited to the foregoing description. BRIEF DESCRIPTION OF THE DRAWINGS The prior art structure of a field effect barrier rectifier shown in FIG. The top oxide is a residue of the self-aligned process and represents a problem of metal adhesion and heat removal. Resistor R1 must be lowered to account for the negative resistance problem. Figure 2 shows an embodiment of an adjustable field effect rectifier (AFER) in accordance with the present invention. Resistor R1 has been reduced due to geometry and solves the problem of negative resistance. This embodiment also promotes better thermal and electrical contact. Figure 3 shows a circuit diagram of the AFER with a MOSFET whose gate electrode is shorted to the source. The polarity of the diode is the same as the polarity of the M〇SFET body diode. This shorted MOSFET cannot be used as an effective diode, and structural parameters (gate oxide thickness, channel length, etc.) need to be carefully selected. Figure 4 is the operation of the AFER. During forward biasing, the depletion layers of the various P regions do not overlap (shown in phantom in the figure) and electrons can easily flow from the channel region to the drain. During reverse biasing, the size of the depletion layer will increase and will begin to overlap after the pinch (see dotted line). This pinching effect helps to reduce leakage from the device. Fig. 5 is a graph showing the relationship between the forward current density of the 600 V AFER and the applied voltage. Structures that do not have a regulation zone will exhibit a negative resistance. The introduction of a 0.2 5 # m wide and 0.35 # m wide adjustment zone will solve this problem. The width and doping concentration in the conditioning region can also be used to improve device performance at low current densities. Figure 6 shows the use of a gate mask to vertically etch through the inter-gate interpole and gate oxide (which may leave some gate oxide to reduce the structure after tunneling. Figure 7 shows the mask mask It is placed on the gate mask to cover the opening of the adjustment zone. Figure 8 is a schematic diagram of p + well boron implantation and contact arsenic implantation. Figure 9 shows that it will be in the middle. A trench is etched to provide an ohmic junction to the 忒P well. Note that only a small portion of the implanted arsenic will be left. Figure 1〇 shows that both masks are isotropic Etching. This self-aligned step provides a uniform barrier height throughout the device. Figure 11 shows that the channel boron will be implanted. The implant dose will determine the potential barrier height of the 17 200915564 portion of the channel. In at least some implementations In the example, it would be desirable to use a quasi-process' to help ensure the same barrier height across the wafer. Figure 12 shows that the gate mask and the overlay mask will be removed. The contact boron will be = if the dose is high 'The height of the barrier in the adjustment zone will be higher than the height of the barrier in the zone. In the case, it may be the final structure. The oxide or oxide wall can be placed in the adjustment zone, .2*^ ISl 匕〆一·图"The insulating oxide layer will be revealed The overlay mask is placed to hold the oxide in the conditioning area. Figure 14 shows that the oxide will be etched. Figure b shows that the mask will be removed. It can be used as the final structure.
任何電流流過調節區。這係調節區植入類型和EPI 型相同時的姓m m n 裳一、了的、、，。構，用以降低電阻器（於此情況中，可能會在 _人放置覆蓋遮罩之前先完成接點植入一參見圖1}。 ’肩不出氧化物會被垂直蝕刻，用以僅留下該等氧 -該接點植人區係和EPI類型為相反類型時此 :門：構為較佳的結構。沒有氧化物側壁’該調節區中位 、甲1下方的電位屏障可能會過小。 【主要元件符號說明】 200 205 21〇 可調節的場效應整流器 闊極 囊袋 源極 18 215 200915564 220 氧化物層 225 淺P +植入區 230 N+接點 235 N++基板 240 P井 405 閘極 410 源極電極 420 N蟲晶層 425 汲極電極 430 P井 430A P井空乏層 440 淺P植入區 440A 淺P植入區空乏層 445 連接線 450 重疊線 600 閘極氧化物 605 多晶矽層 610 閘極遮罩 615 開口 620 開口 700 覆蓋遮罩 705 囊袋 710 閘極遮罩 805 接點神植入物 19 200915564 p井 接點井 通道硼 P型囊袋 氧化物層 覆蓋遮罩 i 20Any current flows through the regulation zone. This is the last name of the adjustment zone implant type and the EPI type. Structure to reduce the resistor (in this case, the contact implant may be completed before the _ person places the cover mask. See Figure 1). 'The oxide will be etched vertically to leave only When the oxygen-the implanted fauna and the EPI type are of the opposite type: the gate: a preferred structure. There is no oxide sidewall. The potential barrier in the neutral region of the regulatory region may be too small. [Main component symbol description] 200 205 21〇 Adjustable field effect rectifier wide-pocket source 18 215 200915564 220 oxide layer 225 shallow P + implant area 230 N+ junction 235 N++ substrate 240 P well 405 gate 410 source electrode 420 N worm layer 425 电极 electrode 430 P well 430A P well vacant layer 440 shallow P implant area 440A shallow P implant area vacant layer 445 connecting line 450 overlapping line 600 gate oxide 605 polycrystalline layer 610 Gate Mask 615 Opening 620 Opening 700 Covering Mask 705 Pouch 710 Gate Mask 805 Contact God Implant 19 200915564 p Well Contact Well Channel Boron P Type Capsule Oxide Layer Covering Mask i 20